1; RUN: llc < %s -mcpu=cortex-a8
2; Test that this doesn't crash.
3; <rdar://problem/12183003>
4
5target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
6target triple = "thumbv7-apple-ios5.1.0"
7
8declare { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0i8(i8*, i32) nounwind readonly
9
10declare void @llvm.arm.neon.vst1.p0i8.v16i8(i8*, <16 x i8>, i32) nounwind
11
12define void @findEdges(i8*) nounwind ssp {
13  %2 = icmp sgt i32 undef, 0
14  br i1 %2, label %5, label %3
15
16; <label>:3                                       ; preds = %5, %1
17  %4 = phi i8* [ %0, %1 ], [ %19, %5 ]
18  ret void
19
20; <label>:5                                       ; preds = %5, %1
21  %6 = phi i8* [ %19, %5 ], [ %0, %1 ]
22  %7 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0i8(i8* null, i32 1)
23  %8 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %7, 0
24  %9 = getelementptr inbounds i8, i8* null, i32 3
25  %10 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0i8(i8* %9, i32 1)
26  %11 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %10, 2
27  %12 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0i8(i8* %6, i32 1)
28  %13 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %12, 0
29  %14 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %12, 1
30  %15 = getelementptr inbounds i8, i8* %6, i32 3
31  %16 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0i8(i8* %15, i32 1)
32  %17 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %16, 1
33  %18 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %16, 2
34  %19 = getelementptr inbounds i8, i8* %6, i32 48
35  %20 = bitcast <16 x i8> %13 to <2 x i64>
36  %21 = bitcast <16 x i8> %8 to <2 x i64>
37  %22 = bitcast <16 x i8> %14 to <2 x i64>
38  %23 = shufflevector <2 x i64> %22, <2 x i64> undef, <1 x i32> zeroinitializer
39  %24 = bitcast <1 x i64> %23 to <8 x i8>
40  %25 = zext <8 x i8> %24 to <8 x i16>
41  %26 = sub <8 x i16> zeroinitializer, %25
42  %27 = bitcast <16 x i8> %17 to <2 x i64>
43  %28 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %26) nounwind
44  %29 = mul <8 x i16> %28, %28
45  %30 = add <8 x i16> zeroinitializer, %29
46  %31 = tail call <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16> undef, <8 x i16> %30) nounwind
47  %32 = bitcast <16 x i8> %11 to <2 x i64>
48  %33 = shufflevector <2 x i64> %32, <2 x i64> undef, <1 x i32> zeroinitializer
49  %34 = bitcast <1 x i64> %33 to <8 x i8>
50  %35 = zext <8 x i8> %34 to <8 x i16>
51  %36 = sub <8 x i16> %35, zeroinitializer
52  %37 = bitcast <16 x i8> %18 to <2 x i64>
53  %38 = shufflevector <2 x i64> %37, <2 x i64> undef, <1 x i32> zeroinitializer
54  %39 = bitcast <1 x i64> %38 to <8 x i8>
55  %40 = zext <8 x i8> %39 to <8 x i16>
56  %41 = sub <8 x i16> zeroinitializer, %40
57  %42 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %36) nounwind
58  %43 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %41) nounwind
59  %44 = mul <8 x i16> %42, %42
60  %45 = mul <8 x i16> %43, %43
61  %46 = add <8 x i16> %45, %44
62  %47 = tail call <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16> %31, <8 x i16> %46) nounwind
63  %48 = bitcast <8 x i16> %47 to <2 x i64>
64  %49 = shufflevector <2 x i64> %48, <2 x i64> undef, <1 x i32> zeroinitializer
65  %50 = bitcast <1 x i64> %49 to <4 x i16>
66  %51 = tail call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> %50, <4 x i16> undef) nounwind
67  %52 = tail call <4 x i16> @llvm.arm.neon.vqshiftnu.v4i16(<4 x i32> %51, <4 x i32> <i32 -6, i32 -6, i32 -6, i32 -6>)
68  %53 = bitcast <4 x i16> %52 to <1 x i64>
69  %54 = shufflevector <1 x i64> %53, <1 x i64> undef, <2 x i32> <i32 0, i32 1>
70  %55 = bitcast <2 x i64> %54 to <8 x i16>
71  %56 = tail call <8 x i8> @llvm.arm.neon.vshiftn.v8i8(<8 x i16> %55, <8 x i16> <i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8>)
72  %57 = shufflevector <2 x i64> %20, <2 x i64> undef, <1 x i32> <i32 1>
73  %58 = bitcast <1 x i64> %57 to <8 x i8>
74  %59 = zext <8 x i8> %58 to <8 x i16>
75  %60 = sub <8 x i16> zeroinitializer, %59
76  %61 = shufflevector <2 x i64> %21, <2 x i64> undef, <1 x i32> <i32 1>
77  %62 = bitcast <1 x i64> %61 to <8 x i8>
78  %63 = zext <8 x i8> %62 to <8 x i16>
79  %64 = sub <8 x i16> %63, zeroinitializer
80  %65 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %60) nounwind
81  %66 = mul <8 x i16> %65, %65
82  %67 = add <8 x i16> zeroinitializer, %66
83  %68 = shufflevector <2 x i64> %27, <2 x i64> undef, <1 x i32> <i32 1>
84  %69 = bitcast <1 x i64> %68 to <8 x i8>
85  %70 = zext <8 x i8> %69 to <8 x i16>
86  %71 = sub <8 x i16> zeroinitializer, %70
87  %72 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> undef) nounwind
88  %73 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %71) nounwind
89  %74 = mul <8 x i16> %72, %72
90  %75 = mul <8 x i16> %73, %73
91  %76 = add <8 x i16> %75, %74
92  %77 = shufflevector <2 x i64> %32, <2 x i64> undef, <1 x i32> <i32 1>
93  %78 = bitcast <1 x i64> %77 to <8 x i8>
94  %79 = zext <8 x i8> %78 to <8 x i16>
95  %80 = sub <8 x i16> %79, zeroinitializer
96  %81 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %80) nounwind
97  %82 = mul <8 x i16> %81, %81
98  %83 = add <8 x i16> zeroinitializer, %82
99  %84 = tail call <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16> %76, <8 x i16> %83) nounwind
100  %85 = tail call <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16> %67, <8 x i16> %84) nounwind
101  %86 = bitcast <8 x i16> %85 to <2 x i64>
102  %87 = shufflevector <2 x i64> %86, <2 x i64> undef, <1 x i32> <i32 1>
103  %88 = bitcast <1 x i64> %87 to <4 x i16>
104  %89 = tail call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> %88, <4 x i16> undef) nounwind
105  %90 = tail call <4 x i16> @llvm.arm.neon.vqrshiftnu.v4i16(<4 x i32> %89, <4 x i32> <i32 -6, i32 -6, i32 -6, i32 -6>)
106  %91 = bitcast <4 x i16> %90 to <1 x i64>
107  %92 = shufflevector <1 x i64> undef, <1 x i64> %91, <2 x i32> <i32 0, i32 1>
108  %93 = bitcast <2 x i64> %92 to <8 x i16>
109  %94 = tail call <8 x i8> @llvm.arm.neon.vshiftn.v8i8(<8 x i16> %93, <8 x i16> <i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8>)
110  %95 = bitcast <8 x i8> %56 to <1 x i64>
111  %96 = bitcast <8 x i8> %94 to <1 x i64>
112  %97 = shufflevector <1 x i64> %95, <1 x i64> %96, <2 x i32> <i32 0, i32 1>
113  %98 = bitcast <2 x i64> %97 to <16 x i8>
114  tail call void @llvm.arm.neon.vst1.p0i8.v16i8(i8* null, <16 x i8> %98, i32 1)
115  %99 = icmp slt i32 undef, undef
116  br i1 %99, label %5, label %3
117}
118
119declare <4 x i16> @llvm.arm.neon.vqshiftnu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
120
121declare <8 x i8> @llvm.arm.neon.vshiftn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
122
123declare <4 x i16> @llvm.arm.neon.vqrshiftnu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
124
125declare <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
126
127declare <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
128
129declare <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16>) nounwind readnone
130