1; RUN: llc -mtriple=armv7 -mattr=+neon -mcpu=swift %s -o - | FileCheck %s 2; RUN: llc -mtriple=armv7 -mattr=+neon -mcpu=cortex-a8 %s -o - | FileCheck --check-prefix=CHECK-NONEONFP %s 3; RUN: llc -mtriple=armv7 -mattr=-neon -mcpu=cortex-a8 %s -o - | FileCheck --check-prefix=CHECK-NONEON %s 4 5; RUN: llc -mtriple=thumbv7m -mcpu=cortex-m4 %s -o - \ 6; RUN: | FileCheck --check-prefix=CHECK-NO-XO %s 7 8; RUN: llc -mtriple=thumbv7m -mattr=+execute-only -mcpu=cortex-m4 %s -o - \ 9; RUN: | FileCheck --check-prefix=CHECK-XO-FLOAT --check-prefix=CHECK-XO-DOUBLE %s 10 11; RUN: llc -mtriple=thumbv7meb -mattr=+execute-only -mcpu=cortex-m4 %s -o - \ 12; RUN: | FileCheck --check-prefix=CHECK-XO-FLOAT --check-prefix=CHECK-XO-DOUBLE-BE %s 13 14; RUN: llc -mtriple=thumbv7m -mattr=+execute-only -mcpu=cortex-m4 -relocation-model=ropi %s -o - \ 15; RUN: | FileCheck --check-prefix=CHECK-XO-ROPI %s 16 17; RUN: llc -mtriple=thumbv8m.main -mattr=fp-armv8 %s -o - \ 18; RUN: | FileCheck --check-prefix=CHECK-NO-XO %s 19 20; RUN: llc -mtriple=thumbv8m.main -mattr=+execute-only -mattr=fp-armv8 %s -o - \ 21; RUN: | FileCheck --check-prefix=CHECK-XO-FLOAT --check-prefix=CHECK-XO-DOUBLE %s 22 23; RUN: llc -mtriple=thumbv8m.maineb -mattr=+execute-only -mattr=fp-armv8 %s -o - \ 24; RUN: | FileCheck --check-prefix=CHECK-XO-FLOAT --check-prefix=CHECK-XO-DOUBLE-BE %s 25 26; RUN: llc -mtriple=thumbv8m.main -mattr=+execute-only -mattr=fp-armv8 -relocation-model=ropi %s -o - \ 27; RUN: | FileCheck --check-prefix=CHECK-XO-ROPI %s 28 29define arm_aapcs_vfpcc float @test_vmov_f32() { 30; CHECK-LABEL: test_vmov_f32: 31; CHECK: vmov.f32 d0, #1.0 32 33; CHECK-NONEONFP: vmov.f32 s0, #1.0 34 ret float 1.0 35} 36 37define arm_aapcs_vfpcc float @test_vmov_imm() { 38; CHECK-LABEL: test_vmov_imm: 39; CHECK: vmov.i32 d0, #0 40 41; CHECK-NONEON-LABEL: test_vmov_imm: 42; CHECK-NONEON: vldr s0, {{.?LCPI[0-9]+_[0-9]+}} 43 44; CHECK-NO-XO-LABEL: test_vmov_imm: 45; CHECK-NO-XO: vldr s0, {{.?LCPI[0-9]+_[0-9]+}} 46 47; CHECK-XO-FLOAT-LABEL: test_vmov_imm: 48; CHECK-XO-FLOAT: movs [[REG:r[0-9]+]], #0 49; CHECK-XO-FLOAT: vmov {{s[0-9]+}}, [[REG]] 50; CHECK-XO-FLOAT-NOT: vldr 51 ret float 0.0 52} 53 54define arm_aapcs_vfpcc float @test_vmvn_imm() { 55; CHECK-LABEL: test_vmvn_imm: 56; CHECK: vmvn.i32 d0, #0xb0000000 57 58; CHECK-NONEON-LABEL: test_vmvn_imm: 59; CHECK-NONEON: vldr s0, {{.?LCPI[0-9]+_[0-9]+}} 60 61; CHECK-NO-XO-LABEL: test_vmvn_imm: 62; CHECK-NO-XO: vldr s0, {{.?LCPI[0-9]+_[0-9]+}} 63 64; CHECK-XO-FLOAT-LABEL: test_vmvn_imm: 65; CHECK-XO-FLOAT: mvn [[REG:r[0-9]+]], #-1342177280 66; CHECK-XO-FLOAT: vmov {{s[0-9]+}}, [[REG]] 67; CHECK-XO-FLOAT-NOT: vldr 68 ret float 8589934080.0 69} 70 71define arm_aapcs_vfpcc double @test_vmov_f64() { 72; CHECK-LABEL: test_vmov_f64: 73; CHECK: vmov.f64 d0, #1.0 74 75; CHECK-NONEON-LABEL: test_vmov_f64: 76; CHECK-NONEON: vmov.f64 d0, #1.0 77 78 ret double 1.0 79} 80 81define arm_aapcs_vfpcc double @test_vmov_double_imm() { 82; CHECK-LABEL: test_vmov_double_imm: 83; CHECK: vmov.i32 d0, #0 84 85; CHECK-NONEON-LABEL: test_vmov_double_imm: 86; CHECK-NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}} 87 88; CHECK-NO-XO-LABEL: test_vmov_double_imm: 89; CHECK-NO-XO: vldr d0, {{.?LCPI[0-9]+_[0-9]+}} 90 91; CHECK-XO-DOUBLE-LABEL: test_vmov_double_imm: 92; CHECK-XO-DOUBLE: movs [[REG:r[0-9]+]], #0 93; CHECK-XO-DOUBLE: vmov {{d[0-9]+}}, [[REG]], [[REG]] 94; CHECK-XO-DOUBLE-NOT: vldr 95 96; CHECK-XO-DOUBLE-BE-LABEL: test_vmov_double_imm: 97; CHECK-XO-DOUBLE-BE: movs [[REG:r[0-9]+]], #0 98; CHECK-XO-DOUBLE-BE: vmov {{d[0-9]+}}, [[REG]], [[REG]] 99; CHECK-XO-DOUBLE-NOT: vldr 100 ret double 0.0 101} 102 103define arm_aapcs_vfpcc double @test_vmvn_double_imm() { 104; CHECK-LABEL: test_vmvn_double_imm: 105; CHECK: vmvn.i32 d0, #0xb0000000 106 107; CHECK-NONEON-LABEL: test_vmvn_double_imm: 108; CHECK-NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}} 109 110; CHECK-NO-XO-LABEL: test_vmvn_double_imm: 111; CHECK-NO-XO: vldr d0, {{.?LCPI[0-9]+_[0-9]+}} 112 113; CHECK-XO-DOUBLE-LABEL: test_vmvn_double_imm: 114; CHECK-XO-DOUBLE: mvn [[REG:r[0-9]+]], #-1342177280 115; CHECK-XO-DOUBLE: vmov {{d[0-9]+}}, [[REG]], [[REG]] 116; CHECK-XO-DOUBLE-NOT: vldr 117 118; CHECK-XO-DOUBLE-BE-LABEL: test_vmvn_double_imm: 119; CHECK-XO-DOUBLE-BE: mvn [[REG:r[0-9]+]], #-1342177280 120; CHECK-XO-DOUBLE-BE: vmov {{d[0-9]+}}, [[REG]], [[REG]] 121; CHECK-XO-DOUBLE-BE-NOT: vldr 122 ret double 0x4fffffff4fffffff 123} 124 125; Make sure we don't ignore the high half of 64-bit values when deciding whether 126; a vmov/vmvn is possible. 127define arm_aapcs_vfpcc double @test_notvmvn_double_imm() { 128; CHECK-LABEL: test_notvmvn_double_imm: 129; CHECK: vldr d0, {{.?LCPI[0-9]+_[0-9]+}} 130 131; CHECK-NONEON-LABEL: test_notvmvn_double_imm: 132; CHECK-NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}} 133 134; CHECK-NO-XO-LABEL: test_notvmvn_double_imm: 135; CHECK-NO-XO: vldr d0, {{.?LCPI[0-9]+_[0-9]+}} 136 137; CHECK-XO-DOUBLE-LABEL: test_notvmvn_double_imm: 138; CHECK-XO-DOUBLE: mvn [[REG1:r[0-9]+]], #-1342177280 139; CHECK-XO-DOUBLE: mov.w [[REG2:r[0-9]+]], #-1 140; CHECK-XO-DOUBLE: vmov {{d[0-9]+}}, [[REG2]], [[REG1]] 141; CHECK-XO-DOUBLE-NOT: vldr 142 143; CHECK-XO-DOUBLE-BE-LABEL: test_notvmvn_double_imm: 144; CHECK-XO-DOUBLE-BE: mov.w [[REG1:r[0-9]+]], #-1 145; CHECK-XO-DOUBLE-BE: mvn [[REG2:r[0-9]+]], #-1342177280 146; CHECK-XO-DOUBLE-BE: vmov {{d[0-9]+}}, [[REG2]], [[REG1]] 147; CHECK-XO-DOUBLE-BE-NOT: vldr 148 ret double 0x4fffffffffffffff 149} 150 151define arm_aapcs_vfpcc float @lower_const_f32_xo() { 152; CHECK-NO-XO-LABEL: lower_const_f32_xo 153; CHECK-NO-XO: vldr {{s[0-9]+}}, {{.?LCPI[0-9]+_[0-9]+}} 154 155; CHECK-XO-FLOAT-LABEL: lower_const_f32_xo 156; CHECK-XO-FLOAT: movw [[REG:r[0-9]+]], #29884 157; CHECK-XO-FLOAT: movt [[REG]], #16083 158; CHECK-XO-FLOAT: vmov {{s[0-9]+}}, [[REG]] 159; CHECK-XO-FLOAT-NOT: vldr 160 ret float 0x3FDA6E9780000000 161} 162 163define arm_aapcs_vfpcc double @lower_const_f64_xo() { 164; CHECK-NO-XO-LABEL: lower_const_f64_xo 165; CHECK-NO-XO: vldr {{d[0-9]+}}, {{.?LCPI[0-9]+_[0-9]+}} 166 167; CHECK-XO-DOUBLE-LABEL: lower_const_f64_xo 168; CHECK-XO-DOUBLE: movw [[REG1:r[0-9]+]], #6291 169; CHECK-XO-DOUBLE: movw [[REG2:r[0-9]+]], #27263 170; CHECK-XO-DOUBLE: movt [[REG1]], #16340 171; CHECK-XO-DOUBLE: movt [[REG2]], #29884 172; CHECK-XO-DOUBLE: vmov {{d[0-9]+}}, [[REG2]], [[REG1]] 173; CHECK-XO-DOUBLE-NOT: vldr 174 175; CHECK-XO-DOUBLE-BE-LABEL: lower_const_f64_xo 176; CHECK-XO-DOUBLE-BE: movw [[REG1:r[0-9]+]], #27263 177; CHECK-XO-DOUBLE-BE: movw [[REG2:r[0-9]+]], #6291 178; CHECK-XO-DOUBLE-BE: movt [[REG1]], #29884 179; CHECK-XO-DOUBLE-BE: movt [[REG2]], #16340 180; CHECK-XO-DOUBLE-BE: vmov {{d[0-9]+}}, [[REG2]], [[REG1]] 181; CHECK-XO-DOUBLE-BE-NOT: vldr 182 ret double 3.140000e-01 183} 184 185; This is a target independent optimization, performed by the 186; DAG Combiner, which promotes floating point literals into 187; constant pools: 188; 189; (a cond b) ? 1.0f : 2.0f -> load (ConstPoolAddr + ((a cond b) ? 0 : 4) 190; 191; We need to make sure that the constant pools are placed in 192; the data section when generating execute-only code: 193 194define arm_aapcs_vfpcc float @lower_fpconst_select(float %f) { 195 196; CHECK-NO-XO-LABEL: lower_fpconst_select 197; CHECK-NO-XO: adr [[REG:r[0-9]+]], [[LABEL:.?LCPI[0-9]+_[0-9]+]] 198; CHECK-NO-XO: vldr {{s[0-9]+}}, {{[[]}}[[REG]]{{[]]}} 199; CHECK-NO-XO-NOT: .rodata 200; CHECK-NO-XO: [[LABEL]]: 201; CHECK-NO-XO: .long 1335165689 202; CHECK-NO-XO: .long 1307470632 203 204; CHECK-XO-FLOAT-LABEL: lower_fpconst_select 205; CHECK-XO-FLOAT: movw [[REG:r[0-9]+]], :lower16:[[LABEL:.?LCP[0-9]+_[0-9]+]] 206; CHECK-XO-FLOAT: movt [[REG]], :upper16:[[LABEL]] 207; CHECK-XO-FLOAT: vldr {{s[0-9]+}}, {{[[]}}[[REG]]{{[]]}} 208; CHECK-XO-FLOAT: .rodata 209; CHECK-XO-FLOAT-NOT: .text 210; CHECK-XO-FLOAT: [[LABEL]]: 211; CHECK-XO-FLOAT: .long 1335165689 212; CHECK-XO-FLOAT: .long 1307470632 213 214; CHECK-XO-ROPI-LABEL: lower_fpconst_select 215; CHECK-XO-ROPI: movw [[REG:r[0-9]+]], :lower16:([[LABEL1:.?LCP[0-9]+_[0-9]+]]-([[LABEL2:.?LPC[0-9]+_[0-9]+]]+4)) 216; CHECK-XO-ROPI: movt [[REG]], :upper16:([[LABEL1]]-([[LABEL2]]+4)) 217; CHECK-XO-ROPI: [[LABEL2]]: 218; CHECK-XO-ROPI: vldr {{s[0-9]+}}, {{[[]}}[[REG]]{{[]]}} 219; CHECK-XO-ROPI: .rodata 220; CHECK-XO-ROPI-NOT: .text 221; CHECK-XO-ROPI: [[LABEL1]]: 222; CHECK-XO-ROPI: .long 1335165689 223; CHECK-XO-ROPI: .long 1307470632 224 225 %cmp = fcmp nnan oeq float %f, 0.000000e+00 226 %sel = select i1 %cmp, float 5.000000e+08, float 5.000000e+09 227 ret float %sel 228} 229