1; RUN: llc < %s -mtriple=arm-none-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s --check-prefix=ARM --check-prefix=ACORE
2; RUN: llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m4 2>&1 | FileCheck %s --check-prefix=ARM --check-prefix=MCORE
3
4define i32 @read_i32_encoded_register() nounwind {
5entry:
6; ARM-LABEL: read_i32_encoded_register:
7; ARM: mrc p1, #2, r0, c3, c4, #5
8  %reg = call i32 @llvm.read_register.i32(metadata !0)
9  ret i32 %reg
10}
11
12define i64 @read_i64_encoded_register() nounwind {
13entry:
14; ARM-LABEL: read_i64_encoded_register:
15; ARM: mrrc p1, #2, r0, r1, c3
16  %reg = call i64 @llvm.read_register.i64(metadata !1)
17  ret i64 %reg
18}
19
20define i32 @read_apsr() nounwind {
21entry:
22; ARM-LABEL: read_apsr:
23; ARM: mrs r0, apsr
24  %reg = call i32 @llvm.read_register.i32(metadata !2)
25  ret i32 %reg
26}
27
28define i32 @read_fpscr() nounwind {
29entry:
30; ARM-LABEL: read_fpscr:
31; ARM: vmrs r0, fpscr
32  %reg = call i32 @llvm.read_register.i32(metadata !3)
33  ret i32 %reg
34}
35
36define void @write_i32_encoded_register(i32 %x) nounwind {
37entry:
38; ARM-LABEL: write_i32_encoded_register:
39; ARM: mcr p1, #2, r0, c3, c4, #5
40  call void @llvm.write_register.i32(metadata !0, i32 %x)
41  ret void
42}
43
44define void @write_i64_encoded_register(i64 %x) nounwind {
45entry:
46; ARM-LABEL: write_i64_encoded_register:
47; ARM: mcrr p1, #2, r0, r1, c3
48  call void @llvm.write_register.i64(metadata !1, i64 %x)
49  ret void
50}
51
52define void @write_apsr(i32 %x) nounwind {
53entry:
54; ARM-LABEL: write_apsr:
55; ACORE: msr APSR_nzcvq, r0
56; MCORE: msr apsr_nzcvq, r0
57  call void @llvm.write_register.i32(metadata !4, i32 %x)
58  ret void
59}
60
61define void @write_fpscr(i32 %x) nounwind {
62entry:
63; ARM-LABEL: write_fpscr:
64; ARM: vmsr fpscr, r0
65  call void @llvm.write_register.i32(metadata !3, i32 %x)
66  ret void
67}
68
69declare i32 @llvm.read_register.i32(metadata) nounwind
70declare i64 @llvm.read_register.i64(metadata) nounwind
71declare void @llvm.write_register.i32(metadata, i32) nounwind
72declare void @llvm.write_register.i64(metadata, i64) nounwind
73
74!0 = !{!"cp1:2:c3:c4:5"}
75!1 = !{!"cp1:2:c3"}
76!2 = !{!"apsr"}
77!3 = !{!"fpscr"}
78!4 = !{!"apsr_nzcvq"}
79