1; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o - | FileCheck %s --check-prefix=CHECK-V6 2; RUN: llc -mtriple=arm-eabi -mattr=+v7 %s -o - | FileCheck %s --check-prefix=CHECK-V7 3 4define zeroext i8 @test1(i32 %A.u) { 5 ; CHECK-LABEL: test1 6 ; CHECK-V6: uxtb 7 ; CHECK-V7: uxtb 8 %B.u = trunc i32 %A.u to i8 9 ret i8 %B.u 10} 11 12define zeroext i32 @test2(i32 %A.u, i32 %B.u) { 13 ; CHECK-LABEL: test2 14 ; CHECK-V6: uxtab r0, r0, r1 15 ; CHECK-V7: uxtab r0, r0, r1 16 %C.u = trunc i32 %B.u to i8 17 %D.u = zext i8 %C.u to i32 18 %E.u = add i32 %A.u, %D.u 19 ret i32 %E.u 20} 21 22define zeroext i32 @test3(i32 %A.u) { 23 ; CHECK-LABEL: test3 24 ; CHECK-V6-NOT: ubfx 25 ; CHECK-V7: ubfx r0, r0, #8, #16 26 %B.u = lshr i32 %A.u, 8 27 %C.u = shl i32 %A.u, 24 28 %D.u = or i32 %B.u, %C.u 29 %E.u = trunc i32 %D.u to i16 30 %F.u = zext i16 %E.u to i32 31 ret i32 %F.u 32} 33 34define zeroext i32 @test4(i32 %A.u) { 35 ; CHECK-LABEL: test4 36 ; CHECK-V6-NOT: ubfx 37 ; CHECK-V7: ubfx r0, r0, #8, #8 38 %B.u = lshr i32 %A.u, 8 39 %C.u = shl i32 %A.u, 24 40 %D.u = or i32 %B.u, %C.u 41 %E.u = trunc i32 %D.u to i8 42 %F.u = zext i8 %E.u to i32 43 ret i32 %F.u 44} 45 46define zeroext i16 @test5(i32 %A.u) { 47 ; CHECK-LABEL: test5 48 ; CHECK-V6: uxth 49 ; CHECK-V7: uxth 50 %B.u = trunc i32 %A.u to i16 51 ret i16 %B.u 52} 53 54define zeroext i32 @test6(i32 %A.u, i32 %B.u) { 55 ; CHECK-LABEL: test6 56 ; CHECK-V6: uxtah r0, r0, r1 57 ; CHECK-V7: uxtah r0, r0, r1 58 %C.u = trunc i32 %B.u to i16 59 %D.u = zext i16 %C.u to i32 60 %E.u = add i32 %A.u, %D.u 61 ret i32 %E.u 62} 63 64define zeroext i32 @test7(i32 %A, i32 %X) { 65; CHECK-LABEL: test7 66; CHECK-V6: uxtab r0, r1, r0, ror #8 67; CHECK-V7: uxtab r0, r1, r0, ror #8 68 %B = lshr i32 %A, 8 69 %C = shl i32 %A, 24 70 %D = or i32 %B, %C 71 %E = trunc i32 %D to i8 72 %F = zext i8 %E to i32 73 %G = add i32 %F, %X 74 ret i32 %G 75} 76 77define zeroext i32 @test8(i32 %A, i32 %X) { 78; CHECK-LABEL: test8 79; CHECK-V6: uxtab r0, r1, r0, ror #16 80; CHECK-V7: uxtab r0, r1, r0, ror #16 81 %B = lshr i32 %A, 16 82 %C = shl i32 %A, 16 83 %D = or i32 %B, %C 84 %E = trunc i32 %D to i8 85 %F = zext i8 %E to i32 86 %G = add i32 %F, %X 87 ret i32 %G 88} 89 90define zeroext i32 @test9(i32 %A, i32 %X) { 91; CHECK-LABEL: test9 92; CHECK-V6: uxtah r0, r1, r0, ror #8 93; CHECK-V7: uxtah r0, r1, r0, ror #8 94 %B = lshr i32 %A, 8 95 %C = shl i32 %A, 24 96 %D = or i32 %B, %C 97 %E = trunc i32 %D to i16 98 %F = zext i16 %E to i32 99 %G = add i32 %F, %X 100 ret i32 %G 101} 102 103define zeroext i32 @test10(i32 %A, i32 %X) { 104; CHECK-LABEL: test10 105; CHECK-V6: uxtah r0, r1, r0, ror #24 106; CHECK-V7: uxtah r0, r1, r0, ror #24 107 %B = lshr i32 %A, 24 108 %C = shl i32 %A, 8 109 %D = or i32 %B, %C 110 %E = trunc i32 %D to i16 111 %F = zext i16 %E to i32 112 %G = add i32 %F, %X 113 ret i32 %G 114} 115 116define zeroext i32 @test11(i32 %A, i32 %X) { 117; CHECK-LABEL: test11 118; CHECK-V6: uxtab r0, r1, r0 119; CHECK-V7: uxtab r0, r1, r0 120 %B = and i32 %A, 255 121 %add = add i32 %X, %B 122 ret i32 %add 123} 124 125define zeroext i32 @test12(i32 %A, i32 %X) { 126; CHECK-LABEL: test12 127; CHECK-V6: uxtab r0, r1, r0, ror #8 128; CHECK-V7: uxtab r0, r1, r0, ror #8 129 %B = lshr i32 %A, 8 130 %and = and i32 %B, 255 131 %add = add i32 %and, %X 132 ret i32 %add 133} 134 135define zeroext i32 @test13(i32 %A, i32 %X) { 136; CHECK-LABEL: test13 137; CHECK-V6: uxtab r0, r1, r0, ror #16 138; CHECK-V7: uxtab r0, r1, r0, ror #16 139 %B = lshr i32 %A, 16 140 %and = and i32 %B, 255 141 %add = add i32 %and, %X 142 ret i32 %add 143} 144 145define zeroext i32 @test14(i32 %A, i32 %X) { 146; CHECK-LABEL: test14 147; CHECK-V6: uxtah r0, r1, r0 148; CHECK-V7: uxtah r0, r1, r0 149 %B = and i32 %A, 65535 150 %add = add i32 %X, %B 151 ret i32 %add 152} 153 154define zeroext i32 @test15(i32 %A, i32 %X) { 155; CHECK-LABEL: test15 156; CHECK-V6: uxtah r0, r1, r0, ror #8 157; CHECK-V7: uxtah r0, r1, r0, ror #8 158 %B = lshr i32 %A, 8 159 %and = and i32 %B, 65535 160 %add = add i32 %and, %X 161 ret i32 %add 162} 163 164define zeroext i32 @test16(i32 %A, i32 %X) { 165; CHECK-LABEL: test16 166; CHECK-V6: uxtah r0, r1, r0, ror #24 167; CHECK-V7: uxtah r0, r1, r0, ror #24 168 %B = lshr i32 %A, 24 169 %C = shl i32 %A, 8 170 %D = or i32 %B, %C 171 %E = and i32 %D, 65535 172 %F = add i32 %E, %X 173 ret i32 %F 174} 175