1; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s 2 3define <8 x i8> @vabss8(<8 x i8>* %A) nounwind { 4;CHECK-LABEL: vabss8: 5;CHECK: vabs.s8 6 %tmp1 = load <8 x i8>, <8 x i8>* %A 7 %tmp2 = call <8 x i8> @llvm.arm.neon.vabs.v8i8(<8 x i8> %tmp1) 8 ret <8 x i8> %tmp2 9} 10 11define <8 x i8> @vabss8_fold(<8 x i8>* %A) nounwind { 12; CHECK-LABEL: vabss8_fold: 13; CHECK: vldr d16, .LCPI1_0 14; CHECK: .LCPI1_0: 15; CHECK-NEXT: .byte 128 @ 0x80 16; CHECK-NEXT: .byte 127 @ 0x7f 17; CHECK-NEXT: .byte 1 @ 0x1 18; CHECK-NEXT: .byte 0 @ 0x0 19; CHECK-NEXT: .byte 1 @ 0x1 20; CHECK-NEXT: .byte 127 @ 0x7f 21; CHECK-NEXT: .byte 128 @ 0x80 22; CHECK-NEXT: .byte 1 @ 0x1 23 %tmp1 = call <8 x i8> @llvm.arm.neon.vabs.v8i8(<8 x i8> <i8 -128, i8 -127, i8 -1, i8 0, i8 1, i8 127, i8 128, i8 255>) 24 ret <8 x i8> %tmp1 25} 26 27define <4 x i16> @vabss16(<4 x i16>* %A) nounwind { 28;CHECK-LABEL: vabss16: 29;CHECK: vabs.s16 30 %tmp1 = load <4 x i16>, <4 x i16>* %A 31 %tmp2 = call <4 x i16> @llvm.arm.neon.vabs.v4i16(<4 x i16> %tmp1) 32 ret <4 x i16> %tmp2 33} 34 35define <4 x i16> @vabss16_fold() nounwind { 36; CHECK-LABEL: vabss16_fold: 37; CHECK: vldr d16, .LCPI3_0 38; CHECK: .LCPI3_0: 39; CHECK-NEXT: .short 32768 @ 0x8000 40; CHECK-NEXT: .short 32767 @ 0x7fff 41; CHECK-NEXT: .short 255 @ 0xff 42; CHECK-NEXT: .short 32768 @ 0x8000 43 %tmp1 = call <4 x i16> @llvm.arm.neon.vabs.v4i16(<4 x i16> <i16 -32768, i16 -32767, i16 255, i16 32768>) 44 ret <4 x i16> %tmp1 45} 46 47define <2 x i32> @vabss32(<2 x i32>* %A) nounwind { 48;CHECK-LABEL: vabss32: 49;CHECK: vabs.s32 50 %tmp1 = load <2 x i32>, <2 x i32>* %A 51 %tmp2 = call <2 x i32> @llvm.arm.neon.vabs.v2i32(<2 x i32> %tmp1) 52 ret <2 x i32> %tmp2 53} 54 55define <2 x i32> @vabss32_fold() nounwind { 56; CHECK-LABEL: vabss32_fold: 57; CHECK: vldr d16, .LCPI5_0 58; CHECK: .LCPI5_0: 59; CHECK-NEXT: .long 2147483647 @ 0x7fffffff 60; CHECK-NEXT: .long 2147483648 @ 0x80000000 61 %tmp1 = call <2 x i32> @llvm.arm.neon.vabs.v2i32(<2 x i32> <i32 -2147483647, i32 2147483648>) 62 ret <2 x i32> %tmp1 63} 64 65define <2 x float> @vabsf32(<2 x float>* %A) nounwind { 66;CHECK-LABEL: vabsf32: 67;CHECK: vabs.f32 68 %tmp1 = load <2 x float>, <2 x float>* %A 69 %tmp2 = call <2 x float> @llvm.fabs.v2f32(<2 x float> %tmp1) 70 ret <2 x float> %tmp2 71} 72 73define <16 x i8> @vabsQs8(<16 x i8>* %A) nounwind { 74;CHECK-LABEL: vabsQs8: 75;CHECK: vabs.s8 76 %tmp1 = load <16 x i8>, <16 x i8>* %A 77 %tmp2 = call <16 x i8> @llvm.arm.neon.vabs.v16i8(<16 x i8> %tmp1) 78 ret <16 x i8> %tmp2 79} 80 81define <8 x i16> @vabsQs16(<8 x i16>* %A) nounwind { 82;CHECK-LABEL: vabsQs16: 83;CHECK: vabs.s16 84 %tmp1 = load <8 x i16>, <8 x i16>* %A 85 %tmp2 = call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %tmp1) 86 ret <8 x i16> %tmp2 87} 88 89define <4 x i32> @vabsQs32(<4 x i32>* %A) nounwind { 90;CHECK-LABEL: vabsQs32: 91;CHECK: vabs.s32 92 %tmp1 = load <4 x i32>, <4 x i32>* %A 93 %tmp2 = call <4 x i32> @llvm.arm.neon.vabs.v4i32(<4 x i32> %tmp1) 94 ret <4 x i32> %tmp2 95} 96 97define <4 x float> @vabsQf32(<4 x float>* %A) nounwind { 98;CHECK-LABEL: vabsQf32: 99;CHECK: vabs.f32 100 %tmp1 = load <4 x float>, <4 x float>* %A 101 %tmp2 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %tmp1) 102 ret <4 x float> %tmp2 103} 104 105declare <8 x i8> @llvm.arm.neon.vabs.v8i8(<8 x i8>) nounwind readnone 106declare <4 x i16> @llvm.arm.neon.vabs.v4i16(<4 x i16>) nounwind readnone 107declare <2 x i32> @llvm.arm.neon.vabs.v2i32(<2 x i32>) nounwind readnone 108declare <2 x float> @llvm.fabs.v2f32(<2 x float>) nounwind readnone 109 110declare <16 x i8> @llvm.arm.neon.vabs.v16i8(<16 x i8>) nounwind readnone 111declare <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16>) nounwind readnone 112declare <4 x i32> @llvm.arm.neon.vabs.v4i32(<4 x i32>) nounwind readnone 113declare <4 x float> @llvm.fabs.v4f32(<4 x float>) nounwind readnone 114 115define <8 x i8> @vqabss8(<8 x i8>* %A) nounwind { 116;CHECK-LABEL: vqabss8: 117;CHECK: vqabs.s8 118 %tmp1 = load <8 x i8>, <8 x i8>* %A 119 %tmp2 = call <8 x i8> @llvm.arm.neon.vqabs.v8i8(<8 x i8> %tmp1) 120 ret <8 x i8> %tmp2 121} 122 123define <4 x i16> @vqabss16(<4 x i16>* %A) nounwind { 124;CHECK-LABEL: vqabss16: 125;CHECK: vqabs.s16 126 %tmp1 = load <4 x i16>, <4 x i16>* %A 127 %tmp2 = call <4 x i16> @llvm.arm.neon.vqabs.v4i16(<4 x i16> %tmp1) 128 ret <4 x i16> %tmp2 129} 130 131define <2 x i32> @vqabss32(<2 x i32>* %A) nounwind { 132;CHECK-LABEL: vqabss32: 133;CHECK: vqabs.s32 134 %tmp1 = load <2 x i32>, <2 x i32>* %A 135 %tmp2 = call <2 x i32> @llvm.arm.neon.vqabs.v2i32(<2 x i32> %tmp1) 136 ret <2 x i32> %tmp2 137} 138 139define <16 x i8> @vqabsQs8(<16 x i8>* %A) nounwind { 140;CHECK-LABEL: vqabsQs8: 141;CHECK: vqabs.s8 142 %tmp1 = load <16 x i8>, <16 x i8>* %A 143 %tmp2 = call <16 x i8> @llvm.arm.neon.vqabs.v16i8(<16 x i8> %tmp1) 144 ret <16 x i8> %tmp2 145} 146 147define <8 x i16> @vqabsQs16(<8 x i16>* %A) nounwind { 148;CHECK-LABEL: vqabsQs16: 149;CHECK: vqabs.s16 150 %tmp1 = load <8 x i16>, <8 x i16>* %A 151 %tmp2 = call <8 x i16> @llvm.arm.neon.vqabs.v8i16(<8 x i16> %tmp1) 152 ret <8 x i16> %tmp2 153} 154 155define <4 x i32> @vqabsQs32(<4 x i32>* %A) nounwind { 156;CHECK-LABEL: vqabsQs32: 157;CHECK: vqabs.s32 158 %tmp1 = load <4 x i32>, <4 x i32>* %A 159 %tmp2 = call <4 x i32> @llvm.arm.neon.vqabs.v4i32(<4 x i32> %tmp1) 160 ret <4 x i32> %tmp2 161} 162 163declare <8 x i8> @llvm.arm.neon.vqabs.v8i8(<8 x i8>) nounwind readnone 164declare <4 x i16> @llvm.arm.neon.vqabs.v4i16(<4 x i16>) nounwind readnone 165declare <2 x i32> @llvm.arm.neon.vqabs.v2i32(<2 x i32>) nounwind readnone 166 167declare <16 x i8> @llvm.arm.neon.vqabs.v16i8(<16 x i8>) nounwind readnone 168declare <8 x i16> @llvm.arm.neon.vqabs.v8i16(<8 x i16>) nounwind readnone 169declare <4 x i32> @llvm.arm.neon.vqabs.v4i32(<4 x i32>) nounwind readnone 170