1//===- IntrinsicsRISCV.td - Defines RISCV intrinsics -------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines all of the RISCV-specific intrinsics.
11//
12//===----------------------------------------------------------------------===//
13
14let TargetPrefix = "riscv" in {
15
16//===----------------------------------------------------------------------===//
17// Atomics
18
19class MaskedAtomicRMW32Intrinsic
20    : Intrinsic<[llvm_i32_ty],
21                [llvm_anyptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
22                [IntrArgMemOnly, NoCapture<0>]>;
23
24class MaskedAtomicRMW32WithSextIntrinsic
25    : Intrinsic<[llvm_i32_ty],
26                [llvm_anyptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
27                 llvm_i32_ty],
28                [IntrArgMemOnly, NoCapture<0>]>;
29
30def int_riscv_masked_atomicrmw_xchg_i32 : MaskedAtomicRMW32Intrinsic;
31def int_riscv_masked_atomicrmw_add_i32  : MaskedAtomicRMW32Intrinsic;
32def int_riscv_masked_atomicrmw_sub_i32  : MaskedAtomicRMW32Intrinsic;
33def int_riscv_masked_atomicrmw_nand_i32 : MaskedAtomicRMW32Intrinsic;
34def int_riscv_masked_atomicrmw_max_i32  : MaskedAtomicRMW32WithSextIntrinsic;
35def int_riscv_masked_atomicrmw_min_i32  : MaskedAtomicRMW32WithSextIntrinsic;
36def int_riscv_masked_atomicrmw_umax_i32 : MaskedAtomicRMW32Intrinsic;
37def int_riscv_masked_atomicrmw_umin_i32 : MaskedAtomicRMW32Intrinsic;
38
39def int_riscv_masked_cmpxchg_i32
40    : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty, llvm_i32_ty, llvm_i32_ty,
41                                llvm_i32_ty, llvm_i32_ty],
42                [IntrArgMemOnly, NoCapture<0>]>;
43
44} // TargetPrefix = "riscv"
45