1 //===---- ScheduleDAGInstrs.cpp - MachineInstr Rescheduling ---------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file This implements the ScheduleDAGInstrs class, which implements
11 /// re-scheduling of MachineInstrs.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
16 #include "llvm/ADT/IntEqClasses.h"
17 #include "llvm/ADT/MapVector.h"
18 #include "llvm/ADT/SmallPtrSet.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/ADT/SparseSet.h"
21 #include "llvm/ADT/iterator_range.h"
22 #include "llvm/Analysis/AliasAnalysis.h"
23 #include "llvm/Analysis/ValueTracking.h"
24 #include "llvm/CodeGen/LiveIntervals.h"
25 #include "llvm/CodeGen/LivePhysRegs.h"
26 #include "llvm/CodeGen/MachineBasicBlock.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstr.h"
30 #include "llvm/CodeGen/MachineInstrBundle.h"
31 #include "llvm/CodeGen/MachineMemOperand.h"
32 #include "llvm/CodeGen/MachineOperand.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/PseudoSourceValue.h"
35 #include "llvm/CodeGen/RegisterPressure.h"
36 #include "llvm/CodeGen/ScheduleDAG.h"
37 #include "llvm/CodeGen/ScheduleDFS.h"
38 #include "llvm/CodeGen/SlotIndexes.h"
39 #include "llvm/CodeGen/TargetRegisterInfo.h"
40 #include "llvm/CodeGen/TargetSubtargetInfo.h"
41 #include "llvm/Config/llvm-config.h"
42 #include "llvm/IR/Constants.h"
43 #include "llvm/IR/Function.h"
44 #include "llvm/IR/Instruction.h"
45 #include "llvm/IR/Instructions.h"
46 #include "llvm/IR/Operator.h"
47 #include "llvm/IR/Type.h"
48 #include "llvm/IR/Value.h"
49 #include "llvm/MC/LaneBitmask.h"
50 #include "llvm/MC/MCRegisterInfo.h"
51 #include "llvm/Support/Casting.h"
52 #include "llvm/Support/CommandLine.h"
53 #include "llvm/Support/Compiler.h"
54 #include "llvm/Support/Debug.h"
55 #include "llvm/Support/ErrorHandling.h"
56 #include "llvm/Support/Format.h"
57 #include "llvm/Support/raw_ostream.h"
58 #include <algorithm>
59 #include <cassert>
60 #include <iterator>
61 #include <string>
62 #include <utility>
63 #include <vector>
64
65 using namespace llvm;
66
67 #define DEBUG_TYPE "machine-scheduler"
68
69 static cl::opt<bool> EnableAASchedMI("enable-aa-sched-mi", cl::Hidden,
70 cl::ZeroOrMore, cl::init(false),
71 cl::desc("Enable use of AA during MI DAG construction"));
72
73 static cl::opt<bool> UseTBAA("use-tbaa-in-sched-mi", cl::Hidden,
74 cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"));
75
76 // Note: the two options below might be used in tuning compile time vs
77 // output quality. Setting HugeRegion so large that it will never be
78 // reached means best-effort, but may be slow.
79
80 // When Stores and Loads maps (or NonAliasStores and NonAliasLoads)
81 // together hold this many SUs, a reduction of maps will be done.
82 static cl::opt<unsigned> HugeRegion("dag-maps-huge-region", cl::Hidden,
83 cl::init(1000), cl::desc("The limit to use while constructing the DAG "
84 "prior to scheduling, at which point a trade-off "
85 "is made to avoid excessive compile time."));
86
87 static cl::opt<unsigned> ReductionSize(
88 "dag-maps-reduction-size", cl::Hidden,
89 cl::desc("A huge scheduling region will have maps reduced by this many "
90 "nodes at a time. Defaults to HugeRegion / 2."));
91
getReductionSize()92 static unsigned getReductionSize() {
93 // Always reduce a huge region with half of the elements, except
94 // when user sets this number explicitly.
95 if (ReductionSize.getNumOccurrences() == 0)
96 return HugeRegion / 2;
97 return ReductionSize;
98 }
99
dumpSUList(ScheduleDAGInstrs::SUList & L)100 static void dumpSUList(ScheduleDAGInstrs::SUList &L) {
101 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
102 dbgs() << "{ ";
103 for (const SUnit *su : L) {
104 dbgs() << "SU(" << su->NodeNum << ")";
105 if (su != L.back())
106 dbgs() << ", ";
107 }
108 dbgs() << "}\n";
109 #endif
110 }
111
ScheduleDAGInstrs(MachineFunction & mf,const MachineLoopInfo * mli,bool RemoveKillFlags)112 ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
113 const MachineLoopInfo *mli,
114 bool RemoveKillFlags)
115 : ScheduleDAG(mf), MLI(mli), MFI(mf.getFrameInfo()),
116 RemoveKillFlags(RemoveKillFlags),
117 UnknownValue(UndefValue::get(
118 Type::getVoidTy(mf.getFunction().getContext()))) {
119 DbgValues.clear();
120
121 const TargetSubtargetInfo &ST = mf.getSubtarget();
122 SchedModel.init(&ST);
123 }
124
125 /// If this machine instr has memory reference information and it can be
126 /// tracked to a normal reference to a known object, return the Value
127 /// for that object. This function returns false the memory location is
128 /// unknown or may alias anything.
getUnderlyingObjectsForInstr(const MachineInstr * MI,const MachineFrameInfo & MFI,UnderlyingObjectsVector & Objects,const DataLayout & DL)129 static bool getUnderlyingObjectsForInstr(const MachineInstr *MI,
130 const MachineFrameInfo &MFI,
131 UnderlyingObjectsVector &Objects,
132 const DataLayout &DL) {
133 auto allMMOsOkay = [&]() {
134 for (const MachineMemOperand *MMO : MI->memoperands()) {
135 if (MMO->isVolatile())
136 return false;
137
138 if (const PseudoSourceValue *PSV = MMO->getPseudoValue()) {
139 // Function that contain tail calls don't have unique PseudoSourceValue
140 // objects. Two PseudoSourceValues might refer to the same or
141 // overlapping locations. The client code calling this function assumes
142 // this is not the case. So return a conservative answer of no known
143 // object.
144 if (MFI.hasTailCall())
145 return false;
146
147 // For now, ignore PseudoSourceValues which may alias LLVM IR values
148 // because the code that uses this function has no way to cope with
149 // such aliases.
150 if (PSV->isAliased(&MFI))
151 return false;
152
153 bool MayAlias = PSV->mayAlias(&MFI);
154 Objects.push_back(UnderlyingObjectsVector::value_type(PSV, MayAlias));
155 } else if (const Value *V = MMO->getValue()) {
156 SmallVector<Value *, 4> Objs;
157 if (!getUnderlyingObjectsForCodeGen(V, Objs, DL))
158 return false;
159
160 for (Value *V : Objs) {
161 assert(isIdentifiedObject(V));
162 Objects.push_back(UnderlyingObjectsVector::value_type(V, true));
163 }
164 } else
165 return false;
166 }
167 return true;
168 };
169
170 if (!allMMOsOkay()) {
171 Objects.clear();
172 return false;
173 }
174
175 return true;
176 }
177
startBlock(MachineBasicBlock * bb)178 void ScheduleDAGInstrs::startBlock(MachineBasicBlock *bb) {
179 BB = bb;
180 }
181
finishBlock()182 void ScheduleDAGInstrs::finishBlock() {
183 // Subclasses should no longer refer to the old block.
184 BB = nullptr;
185 }
186
enterRegion(MachineBasicBlock * bb,MachineBasicBlock::iterator begin,MachineBasicBlock::iterator end,unsigned regioninstrs)187 void ScheduleDAGInstrs::enterRegion(MachineBasicBlock *bb,
188 MachineBasicBlock::iterator begin,
189 MachineBasicBlock::iterator end,
190 unsigned regioninstrs) {
191 assert(bb == BB && "startBlock should set BB");
192 RegionBegin = begin;
193 RegionEnd = end;
194 NumRegionInstrs = regioninstrs;
195 }
196
exitRegion()197 void ScheduleDAGInstrs::exitRegion() {
198 // Nothing to do.
199 }
200
addSchedBarrierDeps()201 void ScheduleDAGInstrs::addSchedBarrierDeps() {
202 MachineInstr *ExitMI = RegionEnd != BB->end() ? &*RegionEnd : nullptr;
203 ExitSU.setInstr(ExitMI);
204 // Add dependencies on the defs and uses of the instruction.
205 if (ExitMI) {
206 for (const MachineOperand &MO : ExitMI->operands()) {
207 if (!MO.isReg() || MO.isDef()) continue;
208 unsigned Reg = MO.getReg();
209 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
210 Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg));
211 } else if (TargetRegisterInfo::isVirtualRegister(Reg) && MO.readsReg()) {
212 addVRegUseDeps(&ExitSU, ExitMI->getOperandNo(&MO));
213 }
214 }
215 }
216 if (!ExitMI || (!ExitMI->isCall() && !ExitMI->isBarrier())) {
217 // For others, e.g. fallthrough, conditional branch, assume the exit
218 // uses all the registers that are livein to the successor blocks.
219 for (const MachineBasicBlock *Succ : BB->successors()) {
220 for (const auto &LI : Succ->liveins()) {
221 if (!Uses.contains(LI.PhysReg))
222 Uses.insert(PhysRegSUOper(&ExitSU, -1, LI.PhysReg));
223 }
224 }
225 }
226 }
227
228 /// MO is an operand of SU's instruction that defines a physical register. Adds
229 /// data dependencies from SU to any uses of the physical register.
addPhysRegDataDeps(SUnit * SU,unsigned OperIdx)230 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) {
231 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);
232 assert(MO.isDef() && "expect physreg def");
233
234 // Ask the target if address-backscheduling is desirable, and if so how much.
235 const TargetSubtargetInfo &ST = MF.getSubtarget();
236
237 // Only use any non-zero latency for real defs/uses, in contrast to
238 // "fake" operands added by regalloc.
239 const MCInstrDesc *DefMIDesc = &SU->getInstr()->getDesc();
240 bool ImplicitPseudoDef = (OperIdx >= DefMIDesc->getNumOperands() &&
241 !DefMIDesc->hasImplicitDefOfPhysReg(MO.getReg()));
242 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true);
243 Alias.isValid(); ++Alias) {
244 if (!Uses.contains(*Alias))
245 continue;
246 for (Reg2SUnitsMap::iterator I = Uses.find(*Alias); I != Uses.end(); ++I) {
247 SUnit *UseSU = I->SU;
248 if (UseSU == SU)
249 continue;
250
251 // Adjust the dependence latency using operand def/use information,
252 // then allow the target to perform its own adjustments.
253 int UseOp = I->OpIdx;
254 MachineInstr *RegUse = nullptr;
255 SDep Dep;
256 if (UseOp < 0)
257 Dep = SDep(SU, SDep::Artificial);
258 else {
259 // Set the hasPhysRegDefs only for physreg defs that have a use within
260 // the scheduling region.
261 SU->hasPhysRegDefs = true;
262 Dep = SDep(SU, SDep::Data, *Alias);
263 RegUse = UseSU->getInstr();
264 }
265 const MCInstrDesc *UseMIDesc =
266 (RegUse ? &UseSU->getInstr()->getDesc() : nullptr);
267 bool ImplicitPseudoUse =
268 (UseMIDesc && UseOp >= ((int)UseMIDesc->getNumOperands()) &&
269 !UseMIDesc->hasImplicitUseOfPhysReg(*Alias));
270 if (!ImplicitPseudoDef && !ImplicitPseudoUse) {
271 Dep.setLatency(SchedModel.computeOperandLatency(SU->getInstr(), OperIdx,
272 RegUse, UseOp));
273 ST.adjustSchedDependency(SU, UseSU, Dep);
274 } else
275 Dep.setLatency(0);
276
277 UseSU->addPred(Dep);
278 }
279 }
280 }
281
282 /// Adds register dependencies (data, anti, and output) from this SUnit
283 /// to following instructions in the same scheduling region that depend the
284 /// physical register referenced at OperIdx.
addPhysRegDeps(SUnit * SU,unsigned OperIdx)285 void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
286 MachineInstr *MI = SU->getInstr();
287 MachineOperand &MO = MI->getOperand(OperIdx);
288 unsigned Reg = MO.getReg();
289 // We do not need to track any dependencies for constant registers.
290 if (MRI.isConstantPhysReg(Reg))
291 return;
292
293 // Optionally add output and anti dependencies. For anti
294 // dependencies we use a latency of 0 because for a multi-issue
295 // target we want to allow the defining instruction to issue
296 // in the same cycle as the using instruction.
297 // TODO: Using a latency of 1 here for output dependencies assumes
298 // there's no cost for reusing registers.
299 SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output;
300 for (MCRegAliasIterator Alias(Reg, TRI, true); Alias.isValid(); ++Alias) {
301 if (!Defs.contains(*Alias))
302 continue;
303 for (Reg2SUnitsMap::iterator I = Defs.find(*Alias); I != Defs.end(); ++I) {
304 SUnit *DefSU = I->SU;
305 if (DefSU == &ExitSU)
306 continue;
307 if (DefSU != SU &&
308 (Kind != SDep::Output || !MO.isDead() ||
309 !DefSU->getInstr()->registerDefIsDead(*Alias))) {
310 if (Kind == SDep::Anti)
311 DefSU->addPred(SDep(SU, Kind, /*Reg=*/*Alias));
312 else {
313 SDep Dep(SU, Kind, /*Reg=*/*Alias);
314 Dep.setLatency(
315 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
316 DefSU->addPred(Dep);
317 }
318 }
319 }
320 }
321
322 if (!MO.isDef()) {
323 SU->hasPhysRegUses = true;
324 // Either insert a new Reg2SUnits entry with an empty SUnits list, or
325 // retrieve the existing SUnits list for this register's uses.
326 // Push this SUnit on the use list.
327 Uses.insert(PhysRegSUOper(SU, OperIdx, Reg));
328 if (RemoveKillFlags)
329 MO.setIsKill(false);
330 } else {
331 addPhysRegDataDeps(SU, OperIdx);
332
333 // Clear previous uses and defs of this register and its subergisters.
334 for (MCSubRegIterator SubReg(Reg, TRI, true); SubReg.isValid(); ++SubReg) {
335 if (Uses.contains(*SubReg))
336 Uses.eraseAll(*SubReg);
337 if (!MO.isDead())
338 Defs.eraseAll(*SubReg);
339 }
340 if (MO.isDead() && SU->isCall) {
341 // Calls will not be reordered because of chain dependencies (see
342 // below). Since call operands are dead, calls may continue to be added
343 // to the DefList making dependence checking quadratic in the size of
344 // the block. Instead, we leave only one call at the back of the
345 // DefList.
346 Reg2SUnitsMap::RangePair P = Defs.equal_range(Reg);
347 Reg2SUnitsMap::iterator B = P.first;
348 Reg2SUnitsMap::iterator I = P.second;
349 for (bool isBegin = I == B; !isBegin; /* empty */) {
350 isBegin = (--I) == B;
351 if (!I->SU->isCall)
352 break;
353 I = Defs.erase(I);
354 }
355 }
356
357 // Defs are pushed in the order they are visited and never reordered.
358 Defs.insert(PhysRegSUOper(SU, OperIdx, Reg));
359 }
360 }
361
getLaneMaskForMO(const MachineOperand & MO) const362 LaneBitmask ScheduleDAGInstrs::getLaneMaskForMO(const MachineOperand &MO) const
363 {
364 unsigned Reg = MO.getReg();
365 // No point in tracking lanemasks if we don't have interesting subregisters.
366 const TargetRegisterClass &RC = *MRI.getRegClass(Reg);
367 if (!RC.HasDisjunctSubRegs)
368 return LaneBitmask::getAll();
369
370 unsigned SubReg = MO.getSubReg();
371 if (SubReg == 0)
372 return RC.getLaneMask();
373 return TRI->getSubRegIndexLaneMask(SubReg);
374 }
375
376 /// Adds register output and data dependencies from this SUnit to instructions
377 /// that occur later in the same scheduling region if they read from or write to
378 /// the virtual register defined at OperIdx.
379 ///
380 /// TODO: Hoist loop induction variable increments. This has to be
381 /// reevaluated. Generally, IV scheduling should be done before coalescing.
addVRegDefDeps(SUnit * SU,unsigned OperIdx)382 void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
383 MachineInstr *MI = SU->getInstr();
384 MachineOperand &MO = MI->getOperand(OperIdx);
385 unsigned Reg = MO.getReg();
386
387 LaneBitmask DefLaneMask;
388 LaneBitmask KillLaneMask;
389 if (TrackLaneMasks) {
390 bool IsKill = MO.getSubReg() == 0 || MO.isUndef();
391 DefLaneMask = getLaneMaskForMO(MO);
392 // If we have a <read-undef> flag, none of the lane values comes from an
393 // earlier instruction.
394 KillLaneMask = IsKill ? LaneBitmask::getAll() : DefLaneMask;
395
396 // Clear undef flag, we'll re-add it later once we know which subregister
397 // Def is first.
398 MO.setIsUndef(false);
399 } else {
400 DefLaneMask = LaneBitmask::getAll();
401 KillLaneMask = LaneBitmask::getAll();
402 }
403
404 if (MO.isDead()) {
405 assert(CurrentVRegUses.find(Reg) == CurrentVRegUses.end() &&
406 "Dead defs should have no uses");
407 } else {
408 // Add data dependence to all uses we found so far.
409 const TargetSubtargetInfo &ST = MF.getSubtarget();
410 for (VReg2SUnitOperIdxMultiMap::iterator I = CurrentVRegUses.find(Reg),
411 E = CurrentVRegUses.end(); I != E; /*empty*/) {
412 LaneBitmask LaneMask = I->LaneMask;
413 // Ignore uses of other lanes.
414 if ((LaneMask & KillLaneMask).none()) {
415 ++I;
416 continue;
417 }
418
419 if ((LaneMask & DefLaneMask).any()) {
420 SUnit *UseSU = I->SU;
421 MachineInstr *Use = UseSU->getInstr();
422 SDep Dep(SU, SDep::Data, Reg);
423 Dep.setLatency(SchedModel.computeOperandLatency(MI, OperIdx, Use,
424 I->OperandIndex));
425 ST.adjustSchedDependency(SU, UseSU, Dep);
426 UseSU->addPred(Dep);
427 }
428
429 LaneMask &= ~KillLaneMask;
430 // If we found a Def for all lanes of this use, remove it from the list.
431 if (LaneMask.any()) {
432 I->LaneMask = LaneMask;
433 ++I;
434 } else
435 I = CurrentVRegUses.erase(I);
436 }
437 }
438
439 // Shortcut: Singly defined vregs do not have output/anti dependencies.
440 if (MRI.hasOneDef(Reg))
441 return;
442
443 // Add output dependence to the next nearest defs of this vreg.
444 //
445 // Unless this definition is dead, the output dependence should be
446 // transitively redundant with antidependencies from this definition's
447 // uses. We're conservative for now until we have a way to guarantee the uses
448 // are not eliminated sometime during scheduling. The output dependence edge
449 // is also useful if output latency exceeds def-use latency.
450 LaneBitmask LaneMask = DefLaneMask;
451 for (VReg2SUnit &V2SU : make_range(CurrentVRegDefs.find(Reg),
452 CurrentVRegDefs.end())) {
453 // Ignore defs for other lanes.
454 if ((V2SU.LaneMask & LaneMask).none())
455 continue;
456 // Add an output dependence.
457 SUnit *DefSU = V2SU.SU;
458 // Ignore additional defs of the same lanes in one instruction. This can
459 // happen because lanemasks are shared for targets with too many
460 // subregisters. We also use some representration tricks/hacks where we
461 // add super-register defs/uses, to imply that although we only access parts
462 // of the reg we care about the full one.
463 if (DefSU == SU)
464 continue;
465 SDep Dep(SU, SDep::Output, Reg);
466 Dep.setLatency(
467 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
468 DefSU->addPred(Dep);
469
470 // Update current definition. This can get tricky if the def was about a
471 // bigger lanemask before. We then have to shrink it and create a new
472 // VReg2SUnit for the non-overlapping part.
473 LaneBitmask OverlapMask = V2SU.LaneMask & LaneMask;
474 LaneBitmask NonOverlapMask = V2SU.LaneMask & ~LaneMask;
475 V2SU.SU = SU;
476 V2SU.LaneMask = OverlapMask;
477 if (NonOverlapMask.any())
478 CurrentVRegDefs.insert(VReg2SUnit(Reg, NonOverlapMask, DefSU));
479 }
480 // If there was no CurrentVRegDefs entry for some lanes yet, create one.
481 if (LaneMask.any())
482 CurrentVRegDefs.insert(VReg2SUnit(Reg, LaneMask, SU));
483 }
484
485 /// Adds a register data dependency if the instruction that defines the
486 /// virtual register used at OperIdx is mapped to an SUnit. Add a register
487 /// antidependency from this SUnit to instructions that occur later in the same
488 /// scheduling region if they write the virtual register.
489 ///
490 /// TODO: Handle ExitSU "uses" properly.
addVRegUseDeps(SUnit * SU,unsigned OperIdx)491 void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
492 const MachineInstr *MI = SU->getInstr();
493 const MachineOperand &MO = MI->getOperand(OperIdx);
494 unsigned Reg = MO.getReg();
495
496 // Remember the use. Data dependencies will be added when we find the def.
497 LaneBitmask LaneMask = TrackLaneMasks ? getLaneMaskForMO(MO)
498 : LaneBitmask::getAll();
499 CurrentVRegUses.insert(VReg2SUnitOperIdx(Reg, LaneMask, OperIdx, SU));
500
501 // Add antidependences to the following defs of the vreg.
502 for (VReg2SUnit &V2SU : make_range(CurrentVRegDefs.find(Reg),
503 CurrentVRegDefs.end())) {
504 // Ignore defs for unrelated lanes.
505 LaneBitmask PrevDefLaneMask = V2SU.LaneMask;
506 if ((PrevDefLaneMask & LaneMask).none())
507 continue;
508 if (V2SU.SU == SU)
509 continue;
510
511 V2SU.SU->addPred(SDep(SU, SDep::Anti, Reg));
512 }
513 }
514
515 /// Returns true if MI is an instruction we are unable to reason about
516 /// (like a call or something with unmodeled side effects).
isGlobalMemoryObject(AliasAnalysis * AA,MachineInstr * MI)517 static inline bool isGlobalMemoryObject(AliasAnalysis *AA, MachineInstr *MI) {
518 return MI->isCall() || MI->hasUnmodeledSideEffects() ||
519 (MI->hasOrderedMemoryRef() && !MI->isDereferenceableInvariantLoad(AA));
520 }
521
addChainDependency(SUnit * SUa,SUnit * SUb,unsigned Latency)522 void ScheduleDAGInstrs::addChainDependency (SUnit *SUa, SUnit *SUb,
523 unsigned Latency) {
524 if (SUa->getInstr()->mayAlias(AAForDep, *SUb->getInstr(), UseTBAA)) {
525 SDep Dep(SUa, SDep::MayAliasMem);
526 Dep.setLatency(Latency);
527 SUb->addPred(Dep);
528 }
529 }
530
531 /// Creates an SUnit for each real instruction, numbered in top-down
532 /// topological order. The instruction order A < B, implies that no edge exists
533 /// from B to A.
534 ///
535 /// Map each real instruction to its SUnit.
536 ///
537 /// After initSUnits, the SUnits vector cannot be resized and the scheduler may
538 /// hang onto SUnit pointers. We may relax this in the future by using SUnit IDs
539 /// instead of pointers.
540 ///
541 /// MachineScheduler relies on initSUnits numbering the nodes by their order in
542 /// the original instruction list.
initSUnits()543 void ScheduleDAGInstrs::initSUnits() {
544 // We'll be allocating one SUnit for each real instruction in the region,
545 // which is contained within a basic block.
546 SUnits.reserve(NumRegionInstrs);
547
548 for (MachineInstr &MI : make_range(RegionBegin, RegionEnd)) {
549 if (MI.isDebugInstr())
550 continue;
551
552 SUnit *SU = newSUnit(&MI);
553 MISUnitMap[&MI] = SU;
554
555 SU->isCall = MI.isCall();
556 SU->isCommutable = MI.isCommutable();
557
558 // Assign the Latency field of SU using target-provided information.
559 SU->Latency = SchedModel.computeInstrLatency(SU->getInstr());
560
561 // If this SUnit uses a reserved or unbuffered resource, mark it as such.
562 //
563 // Reserved resources block an instruction from issuing and stall the
564 // entire pipeline. These are identified by BufferSize=0.
565 //
566 // Unbuffered resources prevent execution of subsequent instructions that
567 // require the same resources. This is used for in-order execution pipelines
568 // within an out-of-order core. These are identified by BufferSize=1.
569 if (SchedModel.hasInstrSchedModel()) {
570 const MCSchedClassDesc *SC = getSchedClass(SU);
571 for (const MCWriteProcResEntry &PRE :
572 make_range(SchedModel.getWriteProcResBegin(SC),
573 SchedModel.getWriteProcResEnd(SC))) {
574 switch (SchedModel.getProcResource(PRE.ProcResourceIdx)->BufferSize) {
575 case 0:
576 SU->hasReservedResource = true;
577 break;
578 case 1:
579 SU->isUnbuffered = true;
580 break;
581 default:
582 break;
583 }
584 }
585 }
586 }
587 }
588
589 class ScheduleDAGInstrs::Value2SUsMap : public MapVector<ValueType, SUList> {
590 /// Current total number of SUs in map.
591 unsigned NumNodes = 0;
592
593 /// 1 for loads, 0 for stores. (see comment in SUList)
594 unsigned TrueMemOrderLatency;
595
596 public:
Value2SUsMap(unsigned lat=0)597 Value2SUsMap(unsigned lat = 0) : TrueMemOrderLatency(lat) {}
598
599 /// To keep NumNodes up to date, insert() is used instead of
600 /// this operator w/ push_back().
operator [](const SUList & Key)601 ValueType &operator[](const SUList &Key) {
602 llvm_unreachable("Don't use. Use insert() instead."); };
603
604 /// Adds SU to the SUList of V. If Map grows huge, reduce its size by calling
605 /// reduce().
insert(SUnit * SU,ValueType V)606 void inline insert(SUnit *SU, ValueType V) {
607 MapVector::operator[](V).push_back(SU);
608 NumNodes++;
609 }
610
611 /// Clears the list of SUs mapped to V.
clearList(ValueType V)612 void inline clearList(ValueType V) {
613 iterator Itr = find(V);
614 if (Itr != end()) {
615 assert(NumNodes >= Itr->second.size());
616 NumNodes -= Itr->second.size();
617
618 Itr->second.clear();
619 }
620 }
621
622 /// Clears map from all contents.
clear()623 void clear() {
624 MapVector<ValueType, SUList>::clear();
625 NumNodes = 0;
626 }
627
size() const628 unsigned inline size() const { return NumNodes; }
629
630 /// Counts the number of SUs in this map after a reduction.
reComputeSize()631 void reComputeSize() {
632 NumNodes = 0;
633 for (auto &I : *this)
634 NumNodes += I.second.size();
635 }
636
getTrueMemOrderLatency() const637 unsigned inline getTrueMemOrderLatency() const {
638 return TrueMemOrderLatency;
639 }
640
641 void dump();
642 };
643
addChainDependencies(SUnit * SU,Value2SUsMap & Val2SUsMap)644 void ScheduleDAGInstrs::addChainDependencies(SUnit *SU,
645 Value2SUsMap &Val2SUsMap) {
646 for (auto &I : Val2SUsMap)
647 addChainDependencies(SU, I.second,
648 Val2SUsMap.getTrueMemOrderLatency());
649 }
650
addChainDependencies(SUnit * SU,Value2SUsMap & Val2SUsMap,ValueType V)651 void ScheduleDAGInstrs::addChainDependencies(SUnit *SU,
652 Value2SUsMap &Val2SUsMap,
653 ValueType V) {
654 Value2SUsMap::iterator Itr = Val2SUsMap.find(V);
655 if (Itr != Val2SUsMap.end())
656 addChainDependencies(SU, Itr->second,
657 Val2SUsMap.getTrueMemOrderLatency());
658 }
659
addBarrierChain(Value2SUsMap & map)660 void ScheduleDAGInstrs::addBarrierChain(Value2SUsMap &map) {
661 assert(BarrierChain != nullptr);
662
663 for (auto &I : map) {
664 SUList &sus = I.second;
665 for (auto *SU : sus)
666 SU->addPredBarrier(BarrierChain);
667 }
668 map.clear();
669 }
670
insertBarrierChain(Value2SUsMap & map)671 void ScheduleDAGInstrs::insertBarrierChain(Value2SUsMap &map) {
672 assert(BarrierChain != nullptr);
673
674 // Go through all lists of SUs.
675 for (Value2SUsMap::iterator I = map.begin(), EE = map.end(); I != EE;) {
676 Value2SUsMap::iterator CurrItr = I++;
677 SUList &sus = CurrItr->second;
678 SUList::iterator SUItr = sus.begin(), SUEE = sus.end();
679 for (; SUItr != SUEE; ++SUItr) {
680 // Stop on BarrierChain or any instruction above it.
681 if ((*SUItr)->NodeNum <= BarrierChain->NodeNum)
682 break;
683
684 (*SUItr)->addPredBarrier(BarrierChain);
685 }
686
687 // Remove also the BarrierChain from list if present.
688 if (SUItr != SUEE && *SUItr == BarrierChain)
689 SUItr++;
690
691 // Remove all SUs that are now successors of BarrierChain.
692 if (SUItr != sus.begin())
693 sus.erase(sus.begin(), SUItr);
694 }
695
696 // Remove all entries with empty su lists.
697 map.remove_if([&](std::pair<ValueType, SUList> &mapEntry) {
698 return (mapEntry.second.empty()); });
699
700 // Recompute the size of the map (NumNodes).
701 map.reComputeSize();
702 }
703
buildSchedGraph(AliasAnalysis * AA,RegPressureTracker * RPTracker,PressureDiffs * PDiffs,LiveIntervals * LIS,bool TrackLaneMasks)704 void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
705 RegPressureTracker *RPTracker,
706 PressureDiffs *PDiffs,
707 LiveIntervals *LIS,
708 bool TrackLaneMasks) {
709 const TargetSubtargetInfo &ST = MF.getSubtarget();
710 bool UseAA = EnableAASchedMI.getNumOccurrences() > 0 ? EnableAASchedMI
711 : ST.useAA();
712 AAForDep = UseAA ? AA : nullptr;
713
714 BarrierChain = nullptr;
715
716 this->TrackLaneMasks = TrackLaneMasks;
717 MISUnitMap.clear();
718 ScheduleDAG::clearDAG();
719
720 // Create an SUnit for each real instruction.
721 initSUnits();
722
723 if (PDiffs)
724 PDiffs->init(SUnits.size());
725
726 // We build scheduling units by walking a block's instruction list
727 // from bottom to top.
728
729 // Each MIs' memory operand(s) is analyzed to a list of underlying
730 // objects. The SU is then inserted in the SUList(s) mapped from the
731 // Value(s). Each Value thus gets mapped to lists of SUs depending
732 // on it, stores and loads kept separately. Two SUs are trivially
733 // non-aliasing if they both depend on only identified Values and do
734 // not share any common Value.
735 Value2SUsMap Stores, Loads(1 /*TrueMemOrderLatency*/);
736
737 // Certain memory accesses are known to not alias any SU in Stores
738 // or Loads, and have therefore their own 'NonAlias'
739 // domain. E.g. spill / reload instructions never alias LLVM I/R
740 // Values. It would be nice to assume that this type of memory
741 // accesses always have a proper memory operand modelling, and are
742 // therefore never unanalyzable, but this is conservatively not
743 // done.
744 Value2SUsMap NonAliasStores, NonAliasLoads(1 /*TrueMemOrderLatency*/);
745
746 // Remove any stale debug info; sometimes BuildSchedGraph is called again
747 // without emitting the info from the previous call.
748 DbgValues.clear();
749 FirstDbgValue = nullptr;
750
751 assert(Defs.empty() && Uses.empty() &&
752 "Only BuildGraph should update Defs/Uses");
753 Defs.setUniverse(TRI->getNumRegs());
754 Uses.setUniverse(TRI->getNumRegs());
755
756 assert(CurrentVRegDefs.empty() && "nobody else should use CurrentVRegDefs");
757 assert(CurrentVRegUses.empty() && "nobody else should use CurrentVRegUses");
758 unsigned NumVirtRegs = MRI.getNumVirtRegs();
759 CurrentVRegDefs.setUniverse(NumVirtRegs);
760 CurrentVRegUses.setUniverse(NumVirtRegs);
761
762 // Model data dependencies between instructions being scheduled and the
763 // ExitSU.
764 addSchedBarrierDeps();
765
766 // Walk the list of instructions, from bottom moving up.
767 MachineInstr *DbgMI = nullptr;
768 for (MachineBasicBlock::iterator MII = RegionEnd, MIE = RegionBegin;
769 MII != MIE; --MII) {
770 MachineInstr &MI = *std::prev(MII);
771 if (DbgMI) {
772 DbgValues.push_back(std::make_pair(DbgMI, &MI));
773 DbgMI = nullptr;
774 }
775
776 if (MI.isDebugValue()) {
777 DbgMI = &MI;
778 continue;
779 }
780 if (MI.isDebugLabel())
781 continue;
782
783 SUnit *SU = MISUnitMap[&MI];
784 assert(SU && "No SUnit mapped to this MI");
785
786 if (RPTracker) {
787 RegisterOperands RegOpers;
788 RegOpers.collect(MI, *TRI, MRI, TrackLaneMasks, false);
789 if (TrackLaneMasks) {
790 SlotIndex SlotIdx = LIS->getInstructionIndex(MI);
791 RegOpers.adjustLaneLiveness(*LIS, MRI, SlotIdx);
792 }
793 if (PDiffs != nullptr)
794 PDiffs->addInstruction(SU->NodeNum, RegOpers, MRI);
795
796 if (RPTracker->getPos() == RegionEnd || &*RPTracker->getPos() != &MI)
797 RPTracker->recedeSkipDebugValues();
798 assert(&*RPTracker->getPos() == &MI && "RPTracker in sync");
799 RPTracker->recede(RegOpers);
800 }
801
802 assert(
803 (CanHandleTerminators || (!MI.isTerminator() && !MI.isPosition())) &&
804 "Cannot schedule terminators or labels!");
805
806 // Add register-based dependencies (data, anti, and output).
807 // For some instructions (calls, returns, inline-asm, etc.) there can
808 // be explicit uses and implicit defs, in which case the use will appear
809 // on the operand list before the def. Do two passes over the operand
810 // list to make sure that defs are processed before any uses.
811 bool HasVRegDef = false;
812 for (unsigned j = 0, n = MI.getNumOperands(); j != n; ++j) {
813 const MachineOperand &MO = MI.getOperand(j);
814 if (!MO.isReg() || !MO.isDef())
815 continue;
816 unsigned Reg = MO.getReg();
817 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
818 addPhysRegDeps(SU, j);
819 } else if (TargetRegisterInfo::isVirtualRegister(Reg)) {
820 HasVRegDef = true;
821 addVRegDefDeps(SU, j);
822 }
823 }
824 // Now process all uses.
825 for (unsigned j = 0, n = MI.getNumOperands(); j != n; ++j) {
826 const MachineOperand &MO = MI.getOperand(j);
827 // Only look at use operands.
828 // We do not need to check for MO.readsReg() here because subsequent
829 // subregister defs will get output dependence edges and need no
830 // additional use dependencies.
831 if (!MO.isReg() || !MO.isUse())
832 continue;
833 unsigned Reg = MO.getReg();
834 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
835 addPhysRegDeps(SU, j);
836 } else if (TargetRegisterInfo::isVirtualRegister(Reg) && MO.readsReg()) {
837 addVRegUseDeps(SU, j);
838 }
839 }
840
841 // If we haven't seen any uses in this scheduling region, create a
842 // dependence edge to ExitSU to model the live-out latency. This is required
843 // for vreg defs with no in-region use, and prefetches with no vreg def.
844 //
845 // FIXME: NumDataSuccs would be more precise than NumSuccs here. This
846 // check currently relies on being called before adding chain deps.
847 if (SU->NumSuccs == 0 && SU->Latency > 1 && (HasVRegDef || MI.mayLoad())) {
848 SDep Dep(SU, SDep::Artificial);
849 Dep.setLatency(SU->Latency - 1);
850 ExitSU.addPred(Dep);
851 }
852
853 // Add memory dependencies (Note: isStoreToStackSlot and
854 // isLoadFromStackSLot are not usable after stack slots are lowered to
855 // actual addresses).
856
857 // This is a barrier event that acts as a pivotal node in the DAG.
858 if (isGlobalMemoryObject(AA, &MI)) {
859
860 // Become the barrier chain.
861 if (BarrierChain)
862 BarrierChain->addPredBarrier(SU);
863 BarrierChain = SU;
864
865 LLVM_DEBUG(dbgs() << "Global memory object and new barrier chain: SU("
866 << BarrierChain->NodeNum << ").\n";);
867
868 // Add dependencies against everything below it and clear maps.
869 addBarrierChain(Stores);
870 addBarrierChain(Loads);
871 addBarrierChain(NonAliasStores);
872 addBarrierChain(NonAliasLoads);
873
874 continue;
875 }
876
877 // If it's not a store or a variant load, we're done.
878 if (!MI.mayStore() &&
879 !(MI.mayLoad() && !MI.isDereferenceableInvariantLoad(AA)))
880 continue;
881
882 // Always add dependecy edge to BarrierChain if present.
883 if (BarrierChain)
884 BarrierChain->addPredBarrier(SU);
885
886 // Find the underlying objects for MI. The Objs vector is either
887 // empty, or filled with the Values of memory locations which this
888 // SU depends on.
889 UnderlyingObjectsVector Objs;
890 bool ObjsFound = getUnderlyingObjectsForInstr(&MI, MFI, Objs,
891 MF.getDataLayout());
892
893 if (MI.mayStore()) {
894 if (!ObjsFound) {
895 // An unknown store depends on all stores and loads.
896 addChainDependencies(SU, Stores);
897 addChainDependencies(SU, NonAliasStores);
898 addChainDependencies(SU, Loads);
899 addChainDependencies(SU, NonAliasLoads);
900
901 // Map this store to 'UnknownValue'.
902 Stores.insert(SU, UnknownValue);
903 } else {
904 // Add precise dependencies against all previously seen memory
905 // accesses mapped to the same Value(s).
906 for (const UnderlyingObject &UnderlObj : Objs) {
907 ValueType V = UnderlObj.getValue();
908 bool ThisMayAlias = UnderlObj.mayAlias();
909
910 // Add dependencies to previous stores and loads mapped to V.
911 addChainDependencies(SU, (ThisMayAlias ? Stores : NonAliasStores), V);
912 addChainDependencies(SU, (ThisMayAlias ? Loads : NonAliasLoads), V);
913 }
914 // Update the store map after all chains have been added to avoid adding
915 // self-loop edge if multiple underlying objects are present.
916 for (const UnderlyingObject &UnderlObj : Objs) {
917 ValueType V = UnderlObj.getValue();
918 bool ThisMayAlias = UnderlObj.mayAlias();
919
920 // Map this store to V.
921 (ThisMayAlias ? Stores : NonAliasStores).insert(SU, V);
922 }
923 // The store may have dependencies to unanalyzable loads and
924 // stores.
925 addChainDependencies(SU, Loads, UnknownValue);
926 addChainDependencies(SU, Stores, UnknownValue);
927 }
928 } else { // SU is a load.
929 if (!ObjsFound) {
930 // An unknown load depends on all stores.
931 addChainDependencies(SU, Stores);
932 addChainDependencies(SU, NonAliasStores);
933
934 Loads.insert(SU, UnknownValue);
935 } else {
936 for (const UnderlyingObject &UnderlObj : Objs) {
937 ValueType V = UnderlObj.getValue();
938 bool ThisMayAlias = UnderlObj.mayAlias();
939
940 // Add precise dependencies against all previously seen stores
941 // mapping to the same Value(s).
942 addChainDependencies(SU, (ThisMayAlias ? Stores : NonAliasStores), V);
943
944 // Map this load to V.
945 (ThisMayAlias ? Loads : NonAliasLoads).insert(SU, V);
946 }
947 // The load may have dependencies to unanalyzable stores.
948 addChainDependencies(SU, Stores, UnknownValue);
949 }
950 }
951
952 // Reduce maps if they grow huge.
953 if (Stores.size() + Loads.size() >= HugeRegion) {
954 LLVM_DEBUG(dbgs() << "Reducing Stores and Loads maps.\n";);
955 reduceHugeMemNodeMaps(Stores, Loads, getReductionSize());
956 }
957 if (NonAliasStores.size() + NonAliasLoads.size() >= HugeRegion) {
958 LLVM_DEBUG(
959 dbgs() << "Reducing NonAliasStores and NonAliasLoads maps.\n";);
960 reduceHugeMemNodeMaps(NonAliasStores, NonAliasLoads, getReductionSize());
961 }
962 }
963
964 if (DbgMI)
965 FirstDbgValue = DbgMI;
966
967 Defs.clear();
968 Uses.clear();
969 CurrentVRegDefs.clear();
970 CurrentVRegUses.clear();
971 }
972
operator <<(raw_ostream & OS,const PseudoSourceValue * PSV)973 raw_ostream &llvm::operator<<(raw_ostream &OS, const PseudoSourceValue* PSV) {
974 PSV->printCustom(OS);
975 return OS;
976 }
977
dump()978 void ScheduleDAGInstrs::Value2SUsMap::dump() {
979 for (auto &Itr : *this) {
980 if (Itr.first.is<const Value*>()) {
981 const Value *V = Itr.first.get<const Value*>();
982 if (isa<UndefValue>(V))
983 dbgs() << "Unknown";
984 else
985 V->printAsOperand(dbgs());
986 }
987 else if (Itr.first.is<const PseudoSourceValue*>())
988 dbgs() << Itr.first.get<const PseudoSourceValue*>();
989 else
990 llvm_unreachable("Unknown Value type.");
991
992 dbgs() << " : ";
993 dumpSUList(Itr.second);
994 }
995 }
996
reduceHugeMemNodeMaps(Value2SUsMap & stores,Value2SUsMap & loads,unsigned N)997 void ScheduleDAGInstrs::reduceHugeMemNodeMaps(Value2SUsMap &stores,
998 Value2SUsMap &loads, unsigned N) {
999 LLVM_DEBUG(dbgs() << "Before reduction:\nStoring SUnits:\n"; stores.dump();
1000 dbgs() << "Loading SUnits:\n"; loads.dump());
1001
1002 // Insert all SU's NodeNums into a vector and sort it.
1003 std::vector<unsigned> NodeNums;
1004 NodeNums.reserve(stores.size() + loads.size());
1005 for (auto &I : stores)
1006 for (auto *SU : I.second)
1007 NodeNums.push_back(SU->NodeNum);
1008 for (auto &I : loads)
1009 for (auto *SU : I.second)
1010 NodeNums.push_back(SU->NodeNum);
1011 llvm::sort(NodeNums);
1012
1013 // The N last elements in NodeNums will be removed, and the SU with
1014 // the lowest NodeNum of them will become the new BarrierChain to
1015 // let the not yet seen SUs have a dependency to the removed SUs.
1016 assert(N <= NodeNums.size());
1017 SUnit *newBarrierChain = &SUnits[*(NodeNums.end() - N)];
1018 if (BarrierChain) {
1019 // The aliasing and non-aliasing maps reduce independently of each
1020 // other, but share a common BarrierChain. Check if the
1021 // newBarrierChain is above the former one. If it is not, it may
1022 // introduce a loop to use newBarrierChain, so keep the old one.
1023 if (newBarrierChain->NodeNum < BarrierChain->NodeNum) {
1024 BarrierChain->addPredBarrier(newBarrierChain);
1025 BarrierChain = newBarrierChain;
1026 LLVM_DEBUG(dbgs() << "Inserting new barrier chain: SU("
1027 << BarrierChain->NodeNum << ").\n";);
1028 }
1029 else
1030 LLVM_DEBUG(dbgs() << "Keeping old barrier chain: SU("
1031 << BarrierChain->NodeNum << ").\n";);
1032 }
1033 else
1034 BarrierChain = newBarrierChain;
1035
1036 insertBarrierChain(stores);
1037 insertBarrierChain(loads);
1038
1039 LLVM_DEBUG(dbgs() << "After reduction:\nStoring SUnits:\n"; stores.dump();
1040 dbgs() << "Loading SUnits:\n"; loads.dump());
1041 }
1042
toggleKills(const MachineRegisterInfo & MRI,LivePhysRegs & LiveRegs,MachineInstr & MI,bool addToLiveRegs)1043 static void toggleKills(const MachineRegisterInfo &MRI, LivePhysRegs &LiveRegs,
1044 MachineInstr &MI, bool addToLiveRegs) {
1045 for (MachineOperand &MO : MI.operands()) {
1046 if (!MO.isReg() || !MO.readsReg())
1047 continue;
1048 unsigned Reg = MO.getReg();
1049 if (!Reg)
1050 continue;
1051
1052 // Things that are available after the instruction are killed by it.
1053 bool IsKill = LiveRegs.available(MRI, Reg);
1054 MO.setIsKill(IsKill);
1055 if (addToLiveRegs)
1056 LiveRegs.addReg(Reg);
1057 }
1058 }
1059
fixupKills(MachineBasicBlock & MBB)1060 void ScheduleDAGInstrs::fixupKills(MachineBasicBlock &MBB) {
1061 LLVM_DEBUG(dbgs() << "Fixup kills for " << printMBBReference(MBB) << '\n');
1062
1063 LiveRegs.init(*TRI);
1064 LiveRegs.addLiveOuts(MBB);
1065
1066 // Examine block from end to start...
1067 for (MachineInstr &MI : make_range(MBB.rbegin(), MBB.rend())) {
1068 if (MI.isDebugInstr())
1069 continue;
1070
1071 // Update liveness. Registers that are defed but not used in this
1072 // instruction are now dead. Mark register and all subregs as they
1073 // are completely defined.
1074 for (ConstMIBundleOperands O(MI); O.isValid(); ++O) {
1075 const MachineOperand &MO = *O;
1076 if (MO.isReg()) {
1077 if (!MO.isDef())
1078 continue;
1079 unsigned Reg = MO.getReg();
1080 if (!Reg)
1081 continue;
1082 LiveRegs.removeReg(Reg);
1083 } else if (MO.isRegMask()) {
1084 LiveRegs.removeRegsInMask(MO);
1085 }
1086 }
1087
1088 // If there is a bundle header fix it up first.
1089 if (!MI.isBundled()) {
1090 toggleKills(MRI, LiveRegs, MI, true);
1091 } else {
1092 MachineBasicBlock::instr_iterator First = MI.getIterator();
1093 if (MI.isBundle()) {
1094 toggleKills(MRI, LiveRegs, MI, false);
1095 ++First;
1096 }
1097 // Some targets make the (questionable) assumtion that the instructions
1098 // inside the bundle are ordered and consequently only the last use of
1099 // a register inside the bundle can kill it.
1100 MachineBasicBlock::instr_iterator I = std::next(First);
1101 while (I->isBundledWithSucc())
1102 ++I;
1103 do {
1104 if (!I->isDebugInstr())
1105 toggleKills(MRI, LiveRegs, *I, true);
1106 --I;
1107 } while(I != First);
1108 }
1109 }
1110 }
1111
dumpNode(const SUnit & SU) const1112 void ScheduleDAGInstrs::dumpNode(const SUnit &SU) const {
1113 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1114 dumpNodeName(SU);
1115 dbgs() << ": ";
1116 SU.getInstr()->dump();
1117 #endif
1118 }
1119
dump() const1120 void ScheduleDAGInstrs::dump() const {
1121 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1122 if (EntrySU.getInstr() != nullptr)
1123 dumpNodeAll(EntrySU);
1124 for (const SUnit &SU : SUnits)
1125 dumpNodeAll(SU);
1126 if (ExitSU.getInstr() != nullptr)
1127 dumpNodeAll(ExitSU);
1128 #endif
1129 }
1130
getGraphNodeLabel(const SUnit * SU) const1131 std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const {
1132 std::string s;
1133 raw_string_ostream oss(s);
1134 if (SU == &EntrySU)
1135 oss << "<entry>";
1136 else if (SU == &ExitSU)
1137 oss << "<exit>";
1138 else
1139 SU->getInstr()->print(oss, /*SkipOpers=*/true);
1140 return oss.str();
1141 }
1142
1143 /// Return the basic block label. It is not necessarilly unique because a block
1144 /// contains multiple scheduling regions. But it is fine for visualization.
getDAGName() const1145 std::string ScheduleDAGInstrs::getDAGName() const {
1146 return "dag." + BB->getFullName();
1147 }
1148
1149 //===----------------------------------------------------------------------===//
1150 // SchedDFSResult Implementation
1151 //===----------------------------------------------------------------------===//
1152
1153 namespace llvm {
1154
1155 /// Internal state used to compute SchedDFSResult.
1156 class SchedDFSImpl {
1157 SchedDFSResult &R;
1158
1159 /// Join DAG nodes into equivalence classes by their subtree.
1160 IntEqClasses SubtreeClasses;
1161 /// List PredSU, SuccSU pairs that represent data edges between subtrees.
1162 std::vector<std::pair<const SUnit *, const SUnit*>> ConnectionPairs;
1163
1164 struct RootData {
1165 unsigned NodeID;
1166 unsigned ParentNodeID; ///< Parent node (member of the parent subtree).
1167 unsigned SubInstrCount = 0; ///< Instr count in this tree only, not
1168 /// children.
1169
RootDatallvm::SchedDFSImpl::RootData1170 RootData(unsigned id): NodeID(id),
1171 ParentNodeID(SchedDFSResult::InvalidSubtreeID) {}
1172
getSparseSetIndexllvm::SchedDFSImpl::RootData1173 unsigned getSparseSetIndex() const { return NodeID; }
1174 };
1175
1176 SparseSet<RootData> RootSet;
1177
1178 public:
SchedDFSImpl(SchedDFSResult & r)1179 SchedDFSImpl(SchedDFSResult &r): R(r), SubtreeClasses(R.DFSNodeData.size()) {
1180 RootSet.setUniverse(R.DFSNodeData.size());
1181 }
1182
1183 /// Returns true if this node been visited by the DFS traversal.
1184 ///
1185 /// During visitPostorderNode the Node's SubtreeID is assigned to the Node
1186 /// ID. Later, SubtreeID is updated but remains valid.
isVisited(const SUnit * SU) const1187 bool isVisited(const SUnit *SU) const {
1188 return R.DFSNodeData[SU->NodeNum].SubtreeID
1189 != SchedDFSResult::InvalidSubtreeID;
1190 }
1191
1192 /// Initializes this node's instruction count. We don't need to flag the node
1193 /// visited until visitPostorder because the DAG cannot have cycles.
visitPreorder(const SUnit * SU)1194 void visitPreorder(const SUnit *SU) {
1195 R.DFSNodeData[SU->NodeNum].InstrCount =
1196 SU->getInstr()->isTransient() ? 0 : 1;
1197 }
1198
1199 /// Called once for each node after all predecessors are visited. Revisit this
1200 /// node's predecessors and potentially join them now that we know the ILP of
1201 /// the other predecessors.
visitPostorderNode(const SUnit * SU)1202 void visitPostorderNode(const SUnit *SU) {
1203 // Mark this node as the root of a subtree. It may be joined with its
1204 // successors later.
1205 R.DFSNodeData[SU->NodeNum].SubtreeID = SU->NodeNum;
1206 RootData RData(SU->NodeNum);
1207 RData.SubInstrCount = SU->getInstr()->isTransient() ? 0 : 1;
1208
1209 // If any predecessors are still in their own subtree, they either cannot be
1210 // joined or are large enough to remain separate. If this parent node's
1211 // total instruction count is not greater than a child subtree by at least
1212 // the subtree limit, then try to join it now since splitting subtrees is
1213 // only useful if multiple high-pressure paths are possible.
1214 unsigned InstrCount = R.DFSNodeData[SU->NodeNum].InstrCount;
1215 for (const SDep &PredDep : SU->Preds) {
1216 if (PredDep.getKind() != SDep::Data)
1217 continue;
1218 unsigned PredNum = PredDep.getSUnit()->NodeNum;
1219 if ((InstrCount - R.DFSNodeData[PredNum].InstrCount) < R.SubtreeLimit)
1220 joinPredSubtree(PredDep, SU, /*CheckLimit=*/false);
1221
1222 // Either link or merge the TreeData entry from the child to the parent.
1223 if (R.DFSNodeData[PredNum].SubtreeID == PredNum) {
1224 // If the predecessor's parent is invalid, this is a tree edge and the
1225 // current node is the parent.
1226 if (RootSet[PredNum].ParentNodeID == SchedDFSResult::InvalidSubtreeID)
1227 RootSet[PredNum].ParentNodeID = SU->NodeNum;
1228 }
1229 else if (RootSet.count(PredNum)) {
1230 // The predecessor is not a root, but is still in the root set. This
1231 // must be the new parent that it was just joined to. Note that
1232 // RootSet[PredNum].ParentNodeID may either be invalid or may still be
1233 // set to the original parent.
1234 RData.SubInstrCount += RootSet[PredNum].SubInstrCount;
1235 RootSet.erase(PredNum);
1236 }
1237 }
1238 RootSet[SU->NodeNum] = RData;
1239 }
1240
1241 /// Called once for each tree edge after calling visitPostOrderNode on
1242 /// the predecessor. Increment the parent node's instruction count and
1243 /// preemptively join this subtree to its parent's if it is small enough.
visitPostorderEdge(const SDep & PredDep,const SUnit * Succ)1244 void visitPostorderEdge(const SDep &PredDep, const SUnit *Succ) {
1245 R.DFSNodeData[Succ->NodeNum].InstrCount
1246 += R.DFSNodeData[PredDep.getSUnit()->NodeNum].InstrCount;
1247 joinPredSubtree(PredDep, Succ);
1248 }
1249
1250 /// Adds a connection for cross edges.
visitCrossEdge(const SDep & PredDep,const SUnit * Succ)1251 void visitCrossEdge(const SDep &PredDep, const SUnit *Succ) {
1252 ConnectionPairs.push_back(std::make_pair(PredDep.getSUnit(), Succ));
1253 }
1254
1255 /// Sets each node's subtree ID to the representative ID and record
1256 /// connections between trees.
finalize()1257 void finalize() {
1258 SubtreeClasses.compress();
1259 R.DFSTreeData.resize(SubtreeClasses.getNumClasses());
1260 assert(SubtreeClasses.getNumClasses() == RootSet.size()
1261 && "number of roots should match trees");
1262 for (const RootData &Root : RootSet) {
1263 unsigned TreeID = SubtreeClasses[Root.NodeID];
1264 if (Root.ParentNodeID != SchedDFSResult::InvalidSubtreeID)
1265 R.DFSTreeData[TreeID].ParentTreeID = SubtreeClasses[Root.ParentNodeID];
1266 R.DFSTreeData[TreeID].SubInstrCount = Root.SubInstrCount;
1267 // Note that SubInstrCount may be greater than InstrCount if we joined
1268 // subtrees across a cross edge. InstrCount will be attributed to the
1269 // original parent, while SubInstrCount will be attributed to the joined
1270 // parent.
1271 }
1272 R.SubtreeConnections.resize(SubtreeClasses.getNumClasses());
1273 R.SubtreeConnectLevels.resize(SubtreeClasses.getNumClasses());
1274 LLVM_DEBUG(dbgs() << R.getNumSubtrees() << " subtrees:\n");
1275 for (unsigned Idx = 0, End = R.DFSNodeData.size(); Idx != End; ++Idx) {
1276 R.DFSNodeData[Idx].SubtreeID = SubtreeClasses[Idx];
1277 LLVM_DEBUG(dbgs() << " SU(" << Idx << ") in tree "
1278 << R.DFSNodeData[Idx].SubtreeID << '\n');
1279 }
1280 for (const std::pair<const SUnit*, const SUnit*> &P : ConnectionPairs) {
1281 unsigned PredTree = SubtreeClasses[P.first->NodeNum];
1282 unsigned SuccTree = SubtreeClasses[P.second->NodeNum];
1283 if (PredTree == SuccTree)
1284 continue;
1285 unsigned Depth = P.first->getDepth();
1286 addConnection(PredTree, SuccTree, Depth);
1287 addConnection(SuccTree, PredTree, Depth);
1288 }
1289 }
1290
1291 protected:
1292 /// Joins the predecessor subtree with the successor that is its DFS parent.
1293 /// Applies some heuristics before joining.
joinPredSubtree(const SDep & PredDep,const SUnit * Succ,bool CheckLimit=true)1294 bool joinPredSubtree(const SDep &PredDep, const SUnit *Succ,
1295 bool CheckLimit = true) {
1296 assert(PredDep.getKind() == SDep::Data && "Subtrees are for data edges");
1297
1298 // Check if the predecessor is already joined.
1299 const SUnit *PredSU = PredDep.getSUnit();
1300 unsigned PredNum = PredSU->NodeNum;
1301 if (R.DFSNodeData[PredNum].SubtreeID != PredNum)
1302 return false;
1303
1304 // Four is the magic number of successors before a node is considered a
1305 // pinch point.
1306 unsigned NumDataSucs = 0;
1307 for (const SDep &SuccDep : PredSU->Succs) {
1308 if (SuccDep.getKind() == SDep::Data) {
1309 if (++NumDataSucs >= 4)
1310 return false;
1311 }
1312 }
1313 if (CheckLimit && R.DFSNodeData[PredNum].InstrCount > R.SubtreeLimit)
1314 return false;
1315 R.DFSNodeData[PredNum].SubtreeID = Succ->NodeNum;
1316 SubtreeClasses.join(Succ->NodeNum, PredNum);
1317 return true;
1318 }
1319
1320 /// Called by finalize() to record a connection between trees.
addConnection(unsigned FromTree,unsigned ToTree,unsigned Depth)1321 void addConnection(unsigned FromTree, unsigned ToTree, unsigned Depth) {
1322 if (!Depth)
1323 return;
1324
1325 do {
1326 SmallVectorImpl<SchedDFSResult::Connection> &Connections =
1327 R.SubtreeConnections[FromTree];
1328 for (SchedDFSResult::Connection &C : Connections) {
1329 if (C.TreeID == ToTree) {
1330 C.Level = std::max(C.Level, Depth);
1331 return;
1332 }
1333 }
1334 Connections.push_back(SchedDFSResult::Connection(ToTree, Depth));
1335 FromTree = R.DFSTreeData[FromTree].ParentTreeID;
1336 } while (FromTree != SchedDFSResult::InvalidSubtreeID);
1337 }
1338 };
1339
1340 } // end namespace llvm
1341
1342 namespace {
1343
1344 /// Manage the stack used by a reverse depth-first search over the DAG.
1345 class SchedDAGReverseDFS {
1346 std::vector<std::pair<const SUnit *, SUnit::const_pred_iterator>> DFSStack;
1347
1348 public:
isComplete() const1349 bool isComplete() const { return DFSStack.empty(); }
1350
follow(const SUnit * SU)1351 void follow(const SUnit *SU) {
1352 DFSStack.push_back(std::make_pair(SU, SU->Preds.begin()));
1353 }
advance()1354 void advance() { ++DFSStack.back().second; }
1355
backtrack()1356 const SDep *backtrack() {
1357 DFSStack.pop_back();
1358 return DFSStack.empty() ? nullptr : std::prev(DFSStack.back().second);
1359 }
1360
getCurr() const1361 const SUnit *getCurr() const { return DFSStack.back().first; }
1362
getPred() const1363 SUnit::const_pred_iterator getPred() const { return DFSStack.back().second; }
1364
getPredEnd() const1365 SUnit::const_pred_iterator getPredEnd() const {
1366 return getCurr()->Preds.end();
1367 }
1368 };
1369
1370 } // end anonymous namespace
1371
hasDataSucc(const SUnit * SU)1372 static bool hasDataSucc(const SUnit *SU) {
1373 for (const SDep &SuccDep : SU->Succs) {
1374 if (SuccDep.getKind() == SDep::Data &&
1375 !SuccDep.getSUnit()->isBoundaryNode())
1376 return true;
1377 }
1378 return false;
1379 }
1380
1381 /// Computes an ILP metric for all nodes in the subDAG reachable via depth-first
1382 /// search from this root.
compute(ArrayRef<SUnit> SUnits)1383 void SchedDFSResult::compute(ArrayRef<SUnit> SUnits) {
1384 if (!IsBottomUp)
1385 llvm_unreachable("Top-down ILP metric is unimplemented");
1386
1387 SchedDFSImpl Impl(*this);
1388 for (const SUnit &SU : SUnits) {
1389 if (Impl.isVisited(&SU) || hasDataSucc(&SU))
1390 continue;
1391
1392 SchedDAGReverseDFS DFS;
1393 Impl.visitPreorder(&SU);
1394 DFS.follow(&SU);
1395 while (true) {
1396 // Traverse the leftmost path as far as possible.
1397 while (DFS.getPred() != DFS.getPredEnd()) {
1398 const SDep &PredDep = *DFS.getPred();
1399 DFS.advance();
1400 // Ignore non-data edges.
1401 if (PredDep.getKind() != SDep::Data
1402 || PredDep.getSUnit()->isBoundaryNode()) {
1403 continue;
1404 }
1405 // An already visited edge is a cross edge, assuming an acyclic DAG.
1406 if (Impl.isVisited(PredDep.getSUnit())) {
1407 Impl.visitCrossEdge(PredDep, DFS.getCurr());
1408 continue;
1409 }
1410 Impl.visitPreorder(PredDep.getSUnit());
1411 DFS.follow(PredDep.getSUnit());
1412 }
1413 // Visit the top of the stack in postorder and backtrack.
1414 const SUnit *Child = DFS.getCurr();
1415 const SDep *PredDep = DFS.backtrack();
1416 Impl.visitPostorderNode(Child);
1417 if (PredDep)
1418 Impl.visitPostorderEdge(*PredDep, DFS.getCurr());
1419 if (DFS.isComplete())
1420 break;
1421 }
1422 }
1423 Impl.finalize();
1424 }
1425
1426 /// The root of the given SubtreeID was just scheduled. For all subtrees
1427 /// connected to this tree, record the depth of the connection so that the
1428 /// nearest connected subtrees can be prioritized.
scheduleTree(unsigned SubtreeID)1429 void SchedDFSResult::scheduleTree(unsigned SubtreeID) {
1430 for (const Connection &C : SubtreeConnections[SubtreeID]) {
1431 SubtreeConnectLevels[C.TreeID] =
1432 std::max(SubtreeConnectLevels[C.TreeID], C.Level);
1433 LLVM_DEBUG(dbgs() << " Tree: " << C.TreeID << " @"
1434 << SubtreeConnectLevels[C.TreeID] << '\n');
1435 }
1436 }
1437
1438 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
print(raw_ostream & OS) const1439 LLVM_DUMP_METHOD void ILPValue::print(raw_ostream &OS) const {
1440 OS << InstrCount << " / " << Length << " = ";
1441 if (!Length)
1442 OS << "BADILP";
1443 else
1444 OS << format("%g", ((double)InstrCount / Length));
1445 }
1446
dump() const1447 LLVM_DUMP_METHOD void ILPValue::dump() const {
1448 dbgs() << *this << '\n';
1449 }
1450
1451 namespace llvm {
1452
1453 LLVM_DUMP_METHOD
operator <<(raw_ostream & OS,const ILPValue & Val)1454 raw_ostream &operator<<(raw_ostream &OS, const ILPValue &Val) {
1455 Val.print(OS);
1456 return OS;
1457 }
1458
1459 } // end namespace llvm
1460
1461 #endif
1462