1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
17 // targets).
18 //
19 //===----------------------------------------------------------------------===//
20
21 #include "LegalizeTypes.h"
22 #include "llvm/IR/DerivedTypes.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/KnownBits.h"
25 #include "llvm/Support/raw_ostream.h"
26 using namespace llvm;
27
28 #define DEBUG_TYPE "legalize-types"
29
30 //===----------------------------------------------------------------------===//
31 // Integer Result Promotion
32 //===----------------------------------------------------------------------===//
33
34 /// PromoteIntegerResult - This method is called when a result of a node is
35 /// found to be in need of promotion to a larger type. At this point, the node
36 /// may also have invalid operands or may have other results that need
37 /// expansion, we just know that (at least) one result needs promotion.
PromoteIntegerResult(SDNode * N,unsigned ResNo)38 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
39 LLVM_DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG);
40 dbgs() << "\n");
41 SDValue Res = SDValue();
42
43 // See if the target wants to custom expand this node.
44 if (CustomLowerNode(N, N->getValueType(ResNo), true)) {
45 LLVM_DEBUG(dbgs() << "Node has been custom expanded, done\n");
46 return;
47 }
48
49 switch (N->getOpcode()) {
50 default:
51 #ifndef NDEBUG
52 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
53 N->dump(&DAG); dbgs() << "\n";
54 #endif
55 llvm_unreachable("Do not know how to promote this operator!");
56 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
57 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
58 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
59 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
60 case ISD::BITREVERSE: Res = PromoteIntRes_BITREVERSE(N); break;
61 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
62 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
63 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
64 case ISD::CTLZ_ZERO_UNDEF:
65 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
66 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
67 case ISD::CTTZ_ZERO_UNDEF:
68 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
69 case ISD::EXTRACT_VECTOR_ELT:
70 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
71 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N)); break;
72 case ISD::MLOAD: Res = PromoteIntRes_MLOAD(cast<MaskedLoadSDNode>(N));
73 break;
74 case ISD::MGATHER: Res = PromoteIntRes_MGATHER(cast<MaskedGatherSDNode>(N));
75 break;
76 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
77 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break;
78 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
79 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
80 case ISD::SMIN:
81 case ISD::SMAX: Res = PromoteIntRes_SExtIntBinOp(N); break;
82 case ISD::UMIN:
83 case ISD::UMAX: Res = PromoteIntRes_ZExtIntBinOp(N); break;
84
85 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
86 case ISD::SIGN_EXTEND_INREG:
87 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
88 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
89 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
90 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
91 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
92 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
93
94 case ISD::EXTRACT_SUBVECTOR:
95 Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break;
96 case ISD::VECTOR_SHUFFLE:
97 Res = PromoteIntRes_VECTOR_SHUFFLE(N); break;
98 case ISD::INSERT_VECTOR_ELT:
99 Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break;
100 case ISD::BUILD_VECTOR:
101 Res = PromoteIntRes_BUILD_VECTOR(N); break;
102 case ISD::SCALAR_TO_VECTOR:
103 Res = PromoteIntRes_SCALAR_TO_VECTOR(N); break;
104 case ISD::CONCAT_VECTORS:
105 Res = PromoteIntRes_CONCAT_VECTORS(N); break;
106
107 case ISD::ANY_EXTEND_VECTOR_INREG:
108 case ISD::SIGN_EXTEND_VECTOR_INREG:
109 case ISD::ZERO_EXTEND_VECTOR_INREG:
110 Res = PromoteIntRes_EXTEND_VECTOR_INREG(N); break;
111
112 case ISD::SIGN_EXTEND:
113 case ISD::ZERO_EXTEND:
114 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
115
116 case ISD::FP_TO_SINT:
117 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
118
119 case ISD::FP_TO_FP16: Res = PromoteIntRes_FP_TO_FP16(N); break;
120
121 case ISD::FLT_ROUNDS_: Res = PromoteIntRes_FLT_ROUNDS(N); break;
122
123 case ISD::AND:
124 case ISD::OR:
125 case ISD::XOR:
126 case ISD::ADD:
127 case ISD::SUB:
128 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
129
130 case ISD::SDIV:
131 case ISD::SREM: Res = PromoteIntRes_SExtIntBinOp(N); break;
132
133 case ISD::UDIV:
134 case ISD::UREM: Res = PromoteIntRes_ZExtIntBinOp(N); break;
135
136 case ISD::SADDO:
137 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
138 case ISD::UADDO:
139 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
140 case ISD::SMULO:
141 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
142
143 case ISD::ADDE:
144 case ISD::SUBE:
145 case ISD::ADDCARRY:
146 case ISD::SUBCARRY: Res = PromoteIntRes_ADDSUBCARRY(N, ResNo); break;
147
148 case ISD::SADDSAT:
149 case ISD::UADDSAT:
150 case ISD::SSUBSAT:
151 case ISD::USUBSAT: Res = PromoteIntRes_ADDSUBSAT(N); break;
152 case ISD::SMULFIX: Res = PromoteIntRes_SMULFIX(N); break;
153
154 case ISD::ATOMIC_LOAD:
155 Res = PromoteIntRes_Atomic0(cast<AtomicSDNode>(N)); break;
156
157 case ISD::ATOMIC_LOAD_ADD:
158 case ISD::ATOMIC_LOAD_SUB:
159 case ISD::ATOMIC_LOAD_AND:
160 case ISD::ATOMIC_LOAD_CLR:
161 case ISD::ATOMIC_LOAD_OR:
162 case ISD::ATOMIC_LOAD_XOR:
163 case ISD::ATOMIC_LOAD_NAND:
164 case ISD::ATOMIC_LOAD_MIN:
165 case ISD::ATOMIC_LOAD_MAX:
166 case ISD::ATOMIC_LOAD_UMIN:
167 case ISD::ATOMIC_LOAD_UMAX:
168 case ISD::ATOMIC_SWAP:
169 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
170
171 case ISD::ATOMIC_CMP_SWAP:
172 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
173 Res = PromoteIntRes_AtomicCmpSwap(cast<AtomicSDNode>(N), ResNo);
174 break;
175 }
176
177 // If the result is null then the sub-method took care of registering it.
178 if (Res.getNode())
179 SetPromotedInteger(SDValue(N, ResNo), Res);
180 }
181
PromoteIntRes_MERGE_VALUES(SDNode * N,unsigned ResNo)182 SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
183 unsigned ResNo) {
184 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
185 return GetPromotedInteger(Op);
186 }
187
PromoteIntRes_AssertSext(SDNode * N)188 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
189 // Sign-extend the new bits, and continue the assertion.
190 SDValue Op = SExtPromotedInteger(N->getOperand(0));
191 return DAG.getNode(ISD::AssertSext, SDLoc(N),
192 Op.getValueType(), Op, N->getOperand(1));
193 }
194
PromoteIntRes_AssertZext(SDNode * N)195 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
196 // Zero the new bits, and continue the assertion.
197 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
198 return DAG.getNode(ISD::AssertZext, SDLoc(N),
199 Op.getValueType(), Op, N->getOperand(1));
200 }
201
PromoteIntRes_Atomic0(AtomicSDNode * N)202 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N) {
203 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
204 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
205 N->getMemoryVT(), ResVT,
206 N->getChain(), N->getBasePtr(),
207 N->getMemOperand());
208 // Legalize the chain result - switch anything that used the old chain to
209 // use the new one.
210 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
211 return Res;
212 }
213
PromoteIntRes_Atomic1(AtomicSDNode * N)214 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
215 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
216 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
217 N->getMemoryVT(),
218 N->getChain(), N->getBasePtr(),
219 Op2, N->getMemOperand());
220 // Legalize the chain result - switch anything that used the old chain to
221 // use the new one.
222 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
223 return Res;
224 }
225
PromoteIntRes_AtomicCmpSwap(AtomicSDNode * N,unsigned ResNo)226 SDValue DAGTypeLegalizer::PromoteIntRes_AtomicCmpSwap(AtomicSDNode *N,
227 unsigned ResNo) {
228 if (ResNo == 1) {
229 assert(N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
230 EVT SVT = getSetCCResultType(N->getOperand(2).getValueType());
231 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
232
233 // Only use the result of getSetCCResultType if it is legal,
234 // otherwise just use the promoted result type (NVT).
235 if (!TLI.isTypeLegal(SVT))
236 SVT = NVT;
237
238 SDVTList VTs = DAG.getVTList(N->getValueType(0), SVT, MVT::Other);
239 SDValue Res = DAG.getAtomicCmpSwap(
240 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, SDLoc(N), N->getMemoryVT(), VTs,
241 N->getChain(), N->getBasePtr(), N->getOperand(2), N->getOperand(3),
242 N->getMemOperand());
243 ReplaceValueWith(SDValue(N, 0), Res.getValue(0));
244 ReplaceValueWith(SDValue(N, 2), Res.getValue(2));
245 return Res.getValue(1);
246 }
247
248 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
249 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
250 SDVTList VTs =
251 DAG.getVTList(Op2.getValueType(), N->getValueType(1), MVT::Other);
252 SDValue Res = DAG.getAtomicCmpSwap(
253 N->getOpcode(), SDLoc(N), N->getMemoryVT(), VTs, N->getChain(),
254 N->getBasePtr(), Op2, Op3, N->getMemOperand());
255 // Update the use to N with the newly created Res.
256 for (unsigned i = 1, NumResults = N->getNumValues(); i < NumResults; ++i)
257 ReplaceValueWith(SDValue(N, i), Res.getValue(i));
258 return Res;
259 }
260
PromoteIntRes_BITCAST(SDNode * N)261 SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
262 SDValue InOp = N->getOperand(0);
263 EVT InVT = InOp.getValueType();
264 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
265 EVT OutVT = N->getValueType(0);
266 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
267 SDLoc dl(N);
268
269 switch (getTypeAction(InVT)) {
270 case TargetLowering::TypeLegal:
271 break;
272 case TargetLowering::TypePromoteInteger:
273 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector() && !NInVT.isVector())
274 // The input promotes to the same size. Convert the promoted value.
275 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
276 break;
277 case TargetLowering::TypeSoftenFloat:
278 // Promote the integer operand by hand.
279 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
280 case TargetLowering::TypePromoteFloat: {
281 // Convert the promoted float by hand.
282 if (!NOutVT.isVector())
283 return DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, GetPromotedFloat(InOp));
284 break;
285 }
286 case TargetLowering::TypeExpandInteger:
287 case TargetLowering::TypeExpandFloat:
288 break;
289 case TargetLowering::TypeScalarizeVector:
290 // Convert the element to an integer and promote it by hand.
291 if (!NOutVT.isVector())
292 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
293 BitConvertToInteger(GetScalarizedVector(InOp)));
294 break;
295 case TargetLowering::TypeSplitVector: {
296 // For example, i32 = BITCAST v2i16 on alpha. Convert the split
297 // pieces of the input into integers and reassemble in the final type.
298 SDValue Lo, Hi;
299 GetSplitVector(N->getOperand(0), Lo, Hi);
300 Lo = BitConvertToInteger(Lo);
301 Hi = BitConvertToInteger(Hi);
302
303 if (DAG.getDataLayout().isBigEndian())
304 std::swap(Lo, Hi);
305
306 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
307 EVT::getIntegerVT(*DAG.getContext(),
308 NOutVT.getSizeInBits()),
309 JoinIntegers(Lo, Hi));
310 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
311 }
312 case TargetLowering::TypeWidenVector:
313 // The input is widened to the same size. Convert to the widened value.
314 // Make sure that the outgoing value is not a vector, because this would
315 // make us bitcast between two vectors which are legalized in different ways.
316 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector())
317 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp));
318 // If the output type is also a vector and widening it to the same size
319 // as the widened input type would be a legal type, we can widen the bitcast
320 // and handle the promotion after.
321 if (NOutVT.isVector()) {
322 unsigned WidenInSize = NInVT.getSizeInBits();
323 unsigned OutSize = OutVT.getSizeInBits();
324 if (WidenInSize % OutSize == 0) {
325 unsigned Scale = WidenInSize / OutSize;
326 EVT WideOutVT = EVT::getVectorVT(*DAG.getContext(),
327 OutVT.getVectorElementType(),
328 OutVT.getVectorNumElements() * Scale);
329 if (isTypeLegal(WideOutVT)) {
330 InOp = DAG.getBitcast(WideOutVT, GetWidenedVector(InOp));
331 MVT IdxTy = TLI.getVectorIdxTy(DAG.getDataLayout());
332 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, InOp,
333 DAG.getConstant(0, dl, IdxTy));
334 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, InOp);
335 }
336 }
337 }
338 }
339
340 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
341 CreateStackStoreLoad(InOp, OutVT));
342 }
343
344 // Helper for BSWAP/BITREVERSE promotion to ensure we can fit the shift amount
345 // in the VT returned by getShiftAmountTy and to return a safe VT if we can't.
getShiftAmountTyForConstant(unsigned Val,EVT VT,const TargetLowering & TLI,SelectionDAG & DAG)346 static EVT getShiftAmountTyForConstant(unsigned Val, EVT VT,
347 const TargetLowering &TLI,
348 SelectionDAG &DAG) {
349 EVT ShiftVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
350 // If the value won't fit in the prefered type, just use something safe. It
351 // will be legalized when the shift is expanded.
352 if ((Log2_32(Val) + 1) > ShiftVT.getScalarSizeInBits())
353 ShiftVT = MVT::i32;
354 return ShiftVT;
355 }
356
PromoteIntRes_BSWAP(SDNode * N)357 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
358 SDValue Op = GetPromotedInteger(N->getOperand(0));
359 EVT OVT = N->getValueType(0);
360 EVT NVT = Op.getValueType();
361 SDLoc dl(N);
362
363 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
364 EVT ShiftVT = getShiftAmountTyForConstant(DiffBits, NVT, TLI, DAG);
365 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
366 DAG.getConstant(DiffBits, dl, ShiftVT));
367 }
368
PromoteIntRes_BITREVERSE(SDNode * N)369 SDValue DAGTypeLegalizer::PromoteIntRes_BITREVERSE(SDNode *N) {
370 SDValue Op = GetPromotedInteger(N->getOperand(0));
371 EVT OVT = N->getValueType(0);
372 EVT NVT = Op.getValueType();
373 SDLoc dl(N);
374
375 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
376 EVT ShiftVT = getShiftAmountTyForConstant(DiffBits, NVT, TLI, DAG);
377 return DAG.getNode(ISD::SRL, dl, NVT,
378 DAG.getNode(ISD::BITREVERSE, dl, NVT, Op),
379 DAG.getConstant(DiffBits, dl, ShiftVT));
380 }
381
PromoteIntRes_BUILD_PAIR(SDNode * N)382 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
383 // The pair element type may be legal, or may not promote to the same type as
384 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
385 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N),
386 TLI.getTypeToTransformTo(*DAG.getContext(),
387 N->getValueType(0)), JoinIntegers(N->getOperand(0),
388 N->getOperand(1)));
389 }
390
PromoteIntRes_Constant(SDNode * N)391 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
392 EVT VT = N->getValueType(0);
393 // FIXME there is no actual debug info here
394 SDLoc dl(N);
395 // Zero extend things like i1, sign extend everything else. It shouldn't
396 // matter in theory which one we pick, but this tends to give better code?
397 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
398 SDValue Result = DAG.getNode(Opc, dl,
399 TLI.getTypeToTransformTo(*DAG.getContext(), VT),
400 SDValue(N, 0));
401 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
402 return Result;
403 }
404
PromoteIntRes_CTLZ(SDNode * N)405 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
406 // Zero extend to the promoted type and do the count there.
407 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
408 SDLoc dl(N);
409 EVT OVT = N->getValueType(0);
410 EVT NVT = Op.getValueType();
411 Op = DAG.getNode(N->getOpcode(), dl, NVT, Op);
412 // Subtract off the extra leading bits in the bigger type.
413 return DAG.getNode(
414 ISD::SUB, dl, NVT, Op,
415 DAG.getConstant(NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits(), dl,
416 NVT));
417 }
418
PromoteIntRes_CTPOP(SDNode * N)419 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
420 // Zero extend to the promoted type and do the count there.
421 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
422 return DAG.getNode(ISD::CTPOP, SDLoc(N), Op.getValueType(), Op);
423 }
424
PromoteIntRes_CTTZ(SDNode * N)425 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
426 SDValue Op = GetPromotedInteger(N->getOperand(0));
427 EVT OVT = N->getValueType(0);
428 EVT NVT = Op.getValueType();
429 SDLoc dl(N);
430 if (N->getOpcode() == ISD::CTTZ) {
431 // The count is the same in the promoted type except if the original
432 // value was zero. This can be handled by setting the bit just off
433 // the top of the original type.
434 auto TopBit = APInt::getOneBitSet(NVT.getScalarSizeInBits(),
435 OVT.getScalarSizeInBits());
436 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, dl, NVT));
437 }
438 return DAG.getNode(N->getOpcode(), dl, NVT, Op);
439 }
440
PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode * N)441 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
442 SDLoc dl(N);
443 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
444
445 SDValue Op0 = N->getOperand(0);
446 SDValue Op1 = N->getOperand(1);
447
448 // If the input also needs to be promoted, do that first so we can get a
449 // get a good idea for the output type.
450 if (TLI.getTypeAction(*DAG.getContext(), Op0.getValueType())
451 == TargetLowering::TypePromoteInteger) {
452 SDValue In = GetPromotedInteger(Op0);
453
454 // If the new type is larger than NVT, use it. We probably won't need to
455 // promote it again.
456 EVT SVT = In.getValueType().getScalarType();
457 if (SVT.bitsGE(NVT)) {
458 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, In, Op1);
459 return DAG.getAnyExtOrTrunc(Ext, dl, NVT);
460 }
461 }
462
463 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, Op0, Op1);
464 }
465
PromoteIntRes_FP_TO_XINT(SDNode * N)466 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
467 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
468 unsigned NewOpc = N->getOpcode();
469 SDLoc dl(N);
470
471 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
472 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
473 // and SINT conversions are Custom, there is no way to tell which is
474 // preferable. We choose SINT because that's the right thing on PPC.)
475 if (N->getOpcode() == ISD::FP_TO_UINT &&
476 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
477 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
478 NewOpc = ISD::FP_TO_SINT;
479
480 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
481
482 // Assert that the converted value fits in the original type. If it doesn't
483 // (eg: because the value being converted is too big), then the result of the
484 // original operation was undefined anyway, so the assert is still correct.
485 //
486 // NOTE: fp-to-uint to fp-to-sint promotion guarantees zero extend. For example:
487 // before legalization: fp-to-uint16, 65534. -> 0xfffe
488 // after legalization: fp-to-sint32, 65534. -> 0x0000fffe
489 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
490 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res,
491 DAG.getValueType(N->getValueType(0).getScalarType()));
492 }
493
PromoteIntRes_FP_TO_FP16(SDNode * N)494 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_FP16(SDNode *N) {
495 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
496 SDLoc dl(N);
497
498 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
499 }
500
PromoteIntRes_FLT_ROUNDS(SDNode * N)501 SDValue DAGTypeLegalizer::PromoteIntRes_FLT_ROUNDS(SDNode *N) {
502 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
503 SDLoc dl(N);
504
505 return DAG.getNode(N->getOpcode(), dl, NVT);
506 }
507
PromoteIntRes_INT_EXTEND(SDNode * N)508 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
509 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
510 SDLoc dl(N);
511
512 if (getTypeAction(N->getOperand(0).getValueType())
513 == TargetLowering::TypePromoteInteger) {
514 SDValue Res = GetPromotedInteger(N->getOperand(0));
515 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
516
517 // If the result and operand types are the same after promotion, simplify
518 // to an in-register extension.
519 if (NVT == Res.getValueType()) {
520 // The high bits are not guaranteed to be anything. Insert an extend.
521 if (N->getOpcode() == ISD::SIGN_EXTEND)
522 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
523 DAG.getValueType(N->getOperand(0).getValueType()));
524 if (N->getOpcode() == ISD::ZERO_EXTEND)
525 return DAG.getZeroExtendInReg(Res, dl,
526 N->getOperand(0).getValueType().getScalarType());
527 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
528 return Res;
529 }
530 }
531
532 // Otherwise, just extend the original operand all the way to the larger type.
533 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
534 }
535
PromoteIntRes_LOAD(LoadSDNode * N)536 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
537 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
538 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
539 ISD::LoadExtType ExtType =
540 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
541 SDLoc dl(N);
542 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
543 N->getMemoryVT(), N->getMemOperand());
544
545 // Legalize the chain result - switch anything that used the old chain to
546 // use the new one.
547 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
548 return Res;
549 }
550
PromoteIntRes_MLOAD(MaskedLoadSDNode * N)551 SDValue DAGTypeLegalizer::PromoteIntRes_MLOAD(MaskedLoadSDNode *N) {
552 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
553 SDValue ExtPassThru = GetPromotedInteger(N->getPassThru());
554
555 SDLoc dl(N);
556 SDValue Res = DAG.getMaskedLoad(NVT, dl, N->getChain(), N->getBasePtr(),
557 N->getMask(), ExtPassThru, N->getMemoryVT(),
558 N->getMemOperand(), ISD::SEXTLOAD);
559 // Legalize the chain result - switch anything that used the old chain to
560 // use the new one.
561 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
562 return Res;
563 }
564
PromoteIntRes_MGATHER(MaskedGatherSDNode * N)565 SDValue DAGTypeLegalizer::PromoteIntRes_MGATHER(MaskedGatherSDNode *N) {
566 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
567 SDValue ExtPassThru = GetPromotedInteger(N->getPassThru());
568 assert(NVT == ExtPassThru.getValueType() &&
569 "Gather result type and the passThru agrument type should be the same");
570
571 SDLoc dl(N);
572 SDValue Ops[] = {N->getChain(), ExtPassThru, N->getMask(), N->getBasePtr(),
573 N->getIndex(), N->getScale() };
574 SDValue Res = DAG.getMaskedGather(DAG.getVTList(NVT, MVT::Other),
575 N->getMemoryVT(), dl, Ops,
576 N->getMemOperand());
577 // Legalize the chain result - switch anything that used the old chain to
578 // use the new one.
579 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
580 return Res;
581 }
582
583 /// Promote the overflow flag of an overflowing arithmetic node.
PromoteIntRes_Overflow(SDNode * N)584 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
585 // Simply change the return type of the boolean result.
586 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
587 EVT ValueVTs[] = { N->getValueType(0), NVT };
588 SDValue Ops[3] = { N->getOperand(0), N->getOperand(1) };
589 unsigned NumOps = N->getNumOperands();
590 assert(NumOps <= 3 && "Too many operands");
591 if (NumOps == 3)
592 Ops[2] = N->getOperand(2);
593
594 SDValue Res = DAG.getNode(N->getOpcode(), SDLoc(N),
595 DAG.getVTList(ValueVTs), makeArrayRef(Ops, NumOps));
596
597 // Modified the sum result - switch anything that used the old sum to use
598 // the new one.
599 ReplaceValueWith(SDValue(N, 0), Res);
600
601 return SDValue(Res.getNode(), 1);
602 }
603
PromoteIntRes_ADDSUBSAT(SDNode * N)604 SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBSAT(SDNode *N) {
605 // For promoting iN -> iM, this can be expanded by
606 // 1. ANY_EXTEND iN to iM
607 // 2. SHL by M-N
608 // 3. [US][ADD|SUB]SAT
609 // 4. L/ASHR by M-N
610 SDLoc dl(N);
611 SDValue Op1 = N->getOperand(0);
612 SDValue Op2 = N->getOperand(1);
613 unsigned OldBits = Op1.getScalarValueSizeInBits();
614
615 unsigned Opcode = N->getOpcode();
616 unsigned ShiftOp;
617 switch (Opcode) {
618 case ISD::SADDSAT:
619 case ISD::SSUBSAT:
620 ShiftOp = ISD::SRA;
621 break;
622 case ISD::UADDSAT:
623 case ISD::USUBSAT:
624 ShiftOp = ISD::SRL;
625 break;
626 default:
627 llvm_unreachable("Expected opcode to be signed or unsigned saturation "
628 "addition or subtraction");
629 }
630
631 SDValue Op1Promoted = GetPromotedInteger(Op1);
632 SDValue Op2Promoted = GetPromotedInteger(Op2);
633
634 EVT PromotedType = Op1Promoted.getValueType();
635 unsigned NewBits = PromotedType.getScalarSizeInBits();
636 unsigned SHLAmount = NewBits - OldBits;
637 EVT SHVT = TLI.getShiftAmountTy(PromotedType, DAG.getDataLayout());
638 SDValue ShiftAmount = DAG.getConstant(SHLAmount, dl, SHVT);
639 Op1Promoted =
640 DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted, ShiftAmount);
641 Op2Promoted =
642 DAG.getNode(ISD::SHL, dl, PromotedType, Op2Promoted, ShiftAmount);
643
644 SDValue Result =
645 DAG.getNode(Opcode, dl, PromotedType, Op1Promoted, Op2Promoted);
646 return DAG.getNode(ShiftOp, dl, PromotedType, Result, ShiftAmount);
647 }
648
PromoteIntRes_SMULFIX(SDNode * N)649 SDValue DAGTypeLegalizer::PromoteIntRes_SMULFIX(SDNode *N) {
650 // Can just promote the operands then continue with operation.
651 SDLoc dl(N);
652 SDValue Op1Promoted = SExtPromotedInteger(N->getOperand(0));
653 SDValue Op2Promoted = SExtPromotedInteger(N->getOperand(1));
654 EVT PromotedType = Op1Promoted.getValueType();
655 return DAG.getNode(N->getOpcode(), dl, PromotedType, Op1Promoted, Op2Promoted,
656 N->getOperand(2));
657 }
658
PromoteIntRes_SADDSUBO(SDNode * N,unsigned ResNo)659 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
660 if (ResNo == 1)
661 return PromoteIntRes_Overflow(N);
662
663 // The operation overflowed iff the result in the larger type is not the
664 // sign extension of its truncation to the original type.
665 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
666 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
667 EVT OVT = N->getOperand(0).getValueType();
668 EVT NVT = LHS.getValueType();
669 SDLoc dl(N);
670
671 // Do the arithmetic in the larger type.
672 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
673 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
674
675 // Calculate the overflow flag: sign extend the arithmetic result from
676 // the original type.
677 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
678 DAG.getValueType(OVT));
679 // Overflowed if and only if this is not equal to Res.
680 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
681
682 // Use the calculated overflow everywhere.
683 ReplaceValueWith(SDValue(N, 1), Ofl);
684
685 return Res;
686 }
687
PromoteIntRes_SELECT(SDNode * N)688 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
689 SDValue LHS = GetPromotedInteger(N->getOperand(1));
690 SDValue RHS = GetPromotedInteger(N->getOperand(2));
691 return DAG.getSelect(SDLoc(N),
692 LHS.getValueType(), N->getOperand(0), LHS, RHS);
693 }
694
PromoteIntRes_VSELECT(SDNode * N)695 SDValue DAGTypeLegalizer::PromoteIntRes_VSELECT(SDNode *N) {
696 SDValue Mask = N->getOperand(0);
697
698 SDValue LHS = GetPromotedInteger(N->getOperand(1));
699 SDValue RHS = GetPromotedInteger(N->getOperand(2));
700 return DAG.getNode(ISD::VSELECT, SDLoc(N),
701 LHS.getValueType(), Mask, LHS, RHS);
702 }
703
PromoteIntRes_SELECT_CC(SDNode * N)704 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
705 SDValue LHS = GetPromotedInteger(N->getOperand(2));
706 SDValue RHS = GetPromotedInteger(N->getOperand(3));
707 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
708 LHS.getValueType(), N->getOperand(0),
709 N->getOperand(1), LHS, RHS, N->getOperand(4));
710 }
711
PromoteIntRes_SETCC(SDNode * N)712 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
713 EVT InVT = N->getOperand(0).getValueType();
714 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
715
716 EVT SVT = getSetCCResultType(InVT);
717
718 // If we got back a type that needs to be promoted, this likely means the
719 // the input type also needs to be promoted. So get the promoted type for
720 // the input and try the query again.
721 if (getTypeAction(SVT) == TargetLowering::TypePromoteInteger) {
722 if (getTypeAction(InVT) == TargetLowering::TypePromoteInteger) {
723 InVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
724 SVT = getSetCCResultType(InVT);
725 } else {
726 // Input type isn't promoted, just use the default promoted type.
727 SVT = NVT;
728 }
729 }
730
731 SDLoc dl(N);
732 assert(SVT.isVector() == N->getOperand(0).getValueType().isVector() &&
733 "Vector compare must return a vector result!");
734
735 // Get the SETCC result using the canonical SETCC type.
736 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, N->getOperand(0),
737 N->getOperand(1), N->getOperand(2));
738
739 // Convert to the expected type.
740 return DAG.getSExtOrTrunc(SetCC, dl, NVT);
741 }
742
PromoteIntRes_SHL(SDNode * N)743 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
744 SDValue LHS = GetPromotedInteger(N->getOperand(0));
745 SDValue RHS = N->getOperand(1);
746 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
747 RHS = ZExtPromotedInteger(RHS);
748 return DAG.getNode(ISD::SHL, SDLoc(N), LHS.getValueType(), LHS, RHS);
749 }
750
PromoteIntRes_SIGN_EXTEND_INREG(SDNode * N)751 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
752 SDValue Op = GetPromotedInteger(N->getOperand(0));
753 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N),
754 Op.getValueType(), Op, N->getOperand(1));
755 }
756
PromoteIntRes_SimpleIntBinOp(SDNode * N)757 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
758 // The input may have strange things in the top bits of the registers, but
759 // these operations don't care. They may have weird bits going out, but
760 // that too is okay if they are integer operations.
761 SDValue LHS = GetPromotedInteger(N->getOperand(0));
762 SDValue RHS = GetPromotedInteger(N->getOperand(1));
763 return DAG.getNode(N->getOpcode(), SDLoc(N),
764 LHS.getValueType(), LHS, RHS);
765 }
766
PromoteIntRes_SExtIntBinOp(SDNode * N)767 SDValue DAGTypeLegalizer::PromoteIntRes_SExtIntBinOp(SDNode *N) {
768 // Sign extend the input.
769 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
770 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
771 return DAG.getNode(N->getOpcode(), SDLoc(N),
772 LHS.getValueType(), LHS, RHS);
773 }
774
PromoteIntRes_ZExtIntBinOp(SDNode * N)775 SDValue DAGTypeLegalizer::PromoteIntRes_ZExtIntBinOp(SDNode *N) {
776 // Zero extend the input.
777 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
778 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
779 return DAG.getNode(N->getOpcode(), SDLoc(N),
780 LHS.getValueType(), LHS, RHS);
781 }
782
PromoteIntRes_SRA(SDNode * N)783 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
784 // The input value must be properly sign extended.
785 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
786 SDValue RHS = N->getOperand(1);
787 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
788 RHS = ZExtPromotedInteger(RHS);
789 return DAG.getNode(ISD::SRA, SDLoc(N), LHS.getValueType(), LHS, RHS);
790 }
791
PromoteIntRes_SRL(SDNode * N)792 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
793 // The input value must be properly zero extended.
794 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
795 SDValue RHS = N->getOperand(1);
796 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
797 RHS = ZExtPromotedInteger(RHS);
798 return DAG.getNode(ISD::SRL, SDLoc(N), LHS.getValueType(), LHS, RHS);
799 }
800
PromoteIntRes_TRUNCATE(SDNode * N)801 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
802 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
803 SDValue Res;
804 SDValue InOp = N->getOperand(0);
805 SDLoc dl(N);
806
807 switch (getTypeAction(InOp.getValueType())) {
808 default: llvm_unreachable("Unknown type action!");
809 case TargetLowering::TypeLegal:
810 case TargetLowering::TypeExpandInteger:
811 Res = InOp;
812 break;
813 case TargetLowering::TypePromoteInteger:
814 Res = GetPromotedInteger(InOp);
815 break;
816 case TargetLowering::TypeSplitVector: {
817 EVT InVT = InOp.getValueType();
818 assert(InVT.isVector() && "Cannot split scalar types");
819 unsigned NumElts = InVT.getVectorNumElements();
820 assert(NumElts == NVT.getVectorNumElements() &&
821 "Dst and Src must have the same number of elements");
822 assert(isPowerOf2_32(NumElts) &&
823 "Promoted vector type must be a power of two");
824
825 SDValue EOp1, EOp2;
826 GetSplitVector(InOp, EOp1, EOp2);
827
828 EVT HalfNVT = EVT::getVectorVT(*DAG.getContext(), NVT.getScalarType(),
829 NumElts/2);
830 EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1);
831 EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2);
832
833 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2);
834 }
835 case TargetLowering::TypeWidenVector: {
836 SDValue WideInOp = GetWidenedVector(InOp);
837
838 // Truncate widened InOp.
839 unsigned NumElem = WideInOp.getValueType().getVectorNumElements();
840 EVT TruncVT = EVT::getVectorVT(*DAG.getContext(),
841 N->getValueType(0).getScalarType(), NumElem);
842 SDValue WideTrunc = DAG.getNode(ISD::TRUNCATE, dl, TruncVT, WideInOp);
843
844 // Zero extend so that the elements are of same type as those of NVT
845 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(), NVT.getVectorElementType(),
846 NumElem);
847 SDValue WideExt = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, WideTrunc);
848
849 // Extract the low NVT subvector.
850 MVT IdxTy = TLI.getVectorIdxTy(DAG.getDataLayout());
851 SDValue ZeroIdx = DAG.getConstant(0, dl, IdxTy);
852 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, WideExt, ZeroIdx);
853 }
854 }
855
856 // Truncate to NVT instead of VT
857 return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res);
858 }
859
PromoteIntRes_UADDSUBO(SDNode * N,unsigned ResNo)860 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
861 if (ResNo == 1)
862 return PromoteIntRes_Overflow(N);
863
864 // The operation overflowed iff the result in the larger type is not the
865 // zero extension of its truncation to the original type.
866 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
867 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
868 EVT OVT = N->getOperand(0).getValueType();
869 EVT NVT = LHS.getValueType();
870 SDLoc dl(N);
871
872 // Do the arithmetic in the larger type.
873 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
874 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
875
876 // Calculate the overflow flag: zero extend the arithmetic result from
877 // the original type.
878 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
879 // Overflowed if and only if this is not equal to Res.
880 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
881
882 // Use the calculated overflow everywhere.
883 ReplaceValueWith(SDValue(N, 1), Ofl);
884
885 return Res;
886 }
887
888 // Handle promotion for the ADDE/SUBE/ADDCARRY/SUBCARRY nodes. Notice that
889 // the third operand of ADDE/SUBE nodes is carry flag, which differs from
890 // the ADDCARRY/SUBCARRY nodes in that the third operand is carry Boolean.
PromoteIntRes_ADDSUBCARRY(SDNode * N,unsigned ResNo)891 SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBCARRY(SDNode *N, unsigned ResNo) {
892 if (ResNo == 1)
893 return PromoteIntRes_Overflow(N);
894
895 // We need to sign-extend the operands so the carry value computed by the
896 // wide operation will be equivalent to the carry value computed by the
897 // narrow operation.
898 // An ADDCARRY can generate carry only if any of the operands has its
899 // most significant bit set. Sign extension propagates the most significant
900 // bit into the higher bits which means the extra bit that the narrow
901 // addition would need (i.e. the carry) will be propagated through the higher
902 // bits of the wide addition.
903 // A SUBCARRY can generate borrow only if LHS < RHS and this property will be
904 // preserved by sign extension.
905 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
906 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
907
908 EVT ValueVTs[] = {LHS.getValueType(), N->getValueType(1)};
909
910 // Do the arithmetic in the wide type.
911 SDValue Res = DAG.getNode(N->getOpcode(), SDLoc(N), DAG.getVTList(ValueVTs),
912 LHS, RHS, N->getOperand(2));
913
914 // Update the users of the original carry/borrow value.
915 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
916
917 return SDValue(Res.getNode(), 0);
918 }
919
PromoteIntRes_XMULO(SDNode * N,unsigned ResNo)920 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
921 // Promote the overflow bit trivially.
922 if (ResNo == 1)
923 return PromoteIntRes_Overflow(N);
924
925 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
926 SDLoc DL(N);
927 EVT SmallVT = LHS.getValueType();
928
929 // To determine if the result overflowed in a larger type, we extend the
930 // input to the larger type, do the multiply (checking if it overflows),
931 // then also check the high bits of the result to see if overflow happened
932 // there.
933 if (N->getOpcode() == ISD::SMULO) {
934 LHS = SExtPromotedInteger(LHS);
935 RHS = SExtPromotedInteger(RHS);
936 } else {
937 LHS = ZExtPromotedInteger(LHS);
938 RHS = ZExtPromotedInteger(RHS);
939 }
940 SDVTList VTs = DAG.getVTList(LHS.getValueType(), N->getValueType(1));
941 SDValue Mul = DAG.getNode(N->getOpcode(), DL, VTs, LHS, RHS);
942
943 // Overflow occurred if it occurred in the larger type, or if the high part
944 // of the result does not zero/sign-extend the low part. Check this second
945 // possibility first.
946 SDValue Overflow;
947 if (N->getOpcode() == ISD::UMULO) {
948 // Unsigned overflow occurred if the high part is non-zero.
949 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
950 DAG.getIntPtrConstant(SmallVT.getSizeInBits(),
951 DL));
952 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi,
953 DAG.getConstant(0, DL, Hi.getValueType()),
954 ISD::SETNE);
955 } else {
956 // Signed overflow occurred if the high part does not sign extend the low.
957 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(),
958 Mul, DAG.getValueType(SmallVT));
959 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE);
960 }
961
962 // The only other way for overflow to occur is if the multiplication in the
963 // larger type itself overflowed.
964 Overflow = DAG.getNode(ISD::OR, DL, N->getValueType(1), Overflow,
965 SDValue(Mul.getNode(), 1));
966
967 // Use the calculated overflow everywhere.
968 ReplaceValueWith(SDValue(N, 1), Overflow);
969 return Mul;
970 }
971
PromoteIntRes_UNDEF(SDNode * N)972 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
973 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
974 N->getValueType(0)));
975 }
976
PromoteIntRes_VAARG(SDNode * N)977 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
978 SDValue Chain = N->getOperand(0); // Get the chain.
979 SDValue Ptr = N->getOperand(1); // Get the pointer.
980 EVT VT = N->getValueType(0);
981 SDLoc dl(N);
982
983 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
984 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
985 // The argument is passed as NumRegs registers of type RegVT.
986
987 SmallVector<SDValue, 8> Parts(NumRegs);
988 for (unsigned i = 0; i < NumRegs; ++i) {
989 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
990 N->getConstantOperandVal(3));
991 Chain = Parts[i].getValue(1);
992 }
993
994 // Handle endianness of the load.
995 if (DAG.getDataLayout().isBigEndian())
996 std::reverse(Parts.begin(), Parts.end());
997
998 // Assemble the parts in the promoted type.
999 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1000 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
1001 for (unsigned i = 1; i < NumRegs; ++i) {
1002 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
1003 // Shift it to the right position and "or" it in.
1004 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
1005 DAG.getConstant(i * RegVT.getSizeInBits(), dl,
1006 TLI.getPointerTy(DAG.getDataLayout())));
1007 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
1008 }
1009
1010 // Modified the chain result - switch anything that used the old chain to
1011 // use the new one.
1012 ReplaceValueWith(SDValue(N, 1), Chain);
1013
1014 return Res;
1015 }
1016
1017 //===----------------------------------------------------------------------===//
1018 // Integer Operand Promotion
1019 //===----------------------------------------------------------------------===//
1020
1021 /// PromoteIntegerOperand - This method is called when the specified operand of
1022 /// the specified node is found to need promotion. At this point, all of the
1023 /// result types of the node are known to be legal, but other operands of the
1024 /// node may need promotion or expansion as well as the specified one.
PromoteIntegerOperand(SDNode * N,unsigned OpNo)1025 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
1026 LLVM_DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG);
1027 dbgs() << "\n");
1028 SDValue Res = SDValue();
1029
1030 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) {
1031 LLVM_DEBUG(dbgs() << "Node has been custom lowered, done\n");
1032 return false;
1033 }
1034
1035 switch (N->getOpcode()) {
1036 default:
1037 #ifndef NDEBUG
1038 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
1039 N->dump(&DAG); dbgs() << "\n";
1040 #endif
1041 llvm_unreachable("Do not know how to promote this operator's operand!");
1042
1043 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
1044 case ISD::ATOMIC_STORE:
1045 Res = PromoteIntOp_ATOMIC_STORE(cast<AtomicSDNode>(N));
1046 break;
1047 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
1048 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
1049 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
1050 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
1051 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
1052 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
1053 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break;
1054 case ISD::INSERT_VECTOR_ELT:
1055 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
1056 case ISD::SCALAR_TO_VECTOR:
1057 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
1058 case ISD::VSELECT:
1059 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
1060 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
1061 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
1062 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
1063 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
1064 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
1065 OpNo); break;
1066 case ISD::MSTORE: Res = PromoteIntOp_MSTORE(cast<MaskedStoreSDNode>(N),
1067 OpNo); break;
1068 case ISD::MLOAD: Res = PromoteIntOp_MLOAD(cast<MaskedLoadSDNode>(N),
1069 OpNo); break;
1070 case ISD::MGATHER: Res = PromoteIntOp_MGATHER(cast<MaskedGatherSDNode>(N),
1071 OpNo); break;
1072 case ISD::MSCATTER: Res = PromoteIntOp_MSCATTER(cast<MaskedScatterSDNode>(N),
1073 OpNo); break;
1074 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
1075 case ISD::FP16_TO_FP:
1076 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
1077 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
1078 case ISD::EXTRACT_SUBVECTOR: Res = PromoteIntOp_EXTRACT_SUBVECTOR(N); break;
1079
1080 case ISD::SHL:
1081 case ISD::SRA:
1082 case ISD::SRL:
1083 case ISD::ROTL:
1084 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
1085
1086 case ISD::ADDCARRY:
1087 case ISD::SUBCARRY: Res = PromoteIntOp_ADDSUBCARRY(N, OpNo); break;
1088
1089 case ISD::FRAMEADDR:
1090 case ISD::RETURNADDR: Res = PromoteIntOp_FRAMERETURNADDR(N); break;
1091
1092 case ISD::PREFETCH: Res = PromoteIntOp_PREFETCH(N, OpNo); break;
1093
1094 case ISD::SMULFIX: Res = PromoteIntOp_SMULFIX(N); break;
1095 }
1096
1097 // If the result is null, the sub-method took care of registering results etc.
1098 if (!Res.getNode()) return false;
1099
1100 // If the result is N, the sub-method updated N in place. Tell the legalizer
1101 // core about this.
1102 if (Res.getNode() == N)
1103 return true;
1104
1105 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1106 "Invalid operand expansion");
1107
1108 ReplaceValueWith(SDValue(N, 0), Res);
1109 return false;
1110 }
1111
1112 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
1113 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
PromoteSetCCOperands(SDValue & NewLHS,SDValue & NewRHS,ISD::CondCode CCCode)1114 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
1115 ISD::CondCode CCCode) {
1116 // We have to insert explicit sign or zero extends. Note that we could
1117 // insert sign extends for ALL conditions. For those operations where either
1118 // zero or sign extension would be valid, use SExtOrZExtPromotedInteger
1119 // which will choose the cheapest for the target.
1120 switch (CCCode) {
1121 default: llvm_unreachable("Unknown integer comparison!");
1122 case ISD::SETEQ:
1123 case ISD::SETNE: {
1124 SDValue OpL = GetPromotedInteger(NewLHS);
1125 SDValue OpR = GetPromotedInteger(NewRHS);
1126
1127 // We would prefer to promote the comparison operand with sign extension.
1128 // If the width of OpL/OpR excluding the duplicated sign bits is no greater
1129 // than the width of NewLHS/NewRH, we can avoid inserting real truncate
1130 // instruction, which is redundant eventually.
1131 unsigned OpLEffectiveBits =
1132 OpL.getScalarValueSizeInBits() - DAG.ComputeNumSignBits(OpL) + 1;
1133 unsigned OpREffectiveBits =
1134 OpR.getScalarValueSizeInBits() - DAG.ComputeNumSignBits(OpR) + 1;
1135 if (OpLEffectiveBits <= NewLHS.getScalarValueSizeInBits() &&
1136 OpREffectiveBits <= NewRHS.getScalarValueSizeInBits()) {
1137 NewLHS = OpL;
1138 NewRHS = OpR;
1139 } else {
1140 NewLHS = SExtOrZExtPromotedInteger(NewLHS);
1141 NewRHS = SExtOrZExtPromotedInteger(NewRHS);
1142 }
1143 break;
1144 }
1145 case ISD::SETUGE:
1146 case ISD::SETUGT:
1147 case ISD::SETULE:
1148 case ISD::SETULT:
1149 NewLHS = SExtOrZExtPromotedInteger(NewLHS);
1150 NewRHS = SExtOrZExtPromotedInteger(NewRHS);
1151 break;
1152 case ISD::SETGE:
1153 case ISD::SETGT:
1154 case ISD::SETLT:
1155 case ISD::SETLE:
1156 NewLHS = SExtPromotedInteger(NewLHS);
1157 NewRHS = SExtPromotedInteger(NewRHS);
1158 break;
1159 }
1160 }
1161
PromoteIntOp_ANY_EXTEND(SDNode * N)1162 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
1163 SDValue Op = GetPromotedInteger(N->getOperand(0));
1164 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), Op);
1165 }
1166
PromoteIntOp_ATOMIC_STORE(AtomicSDNode * N)1167 SDValue DAGTypeLegalizer::PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N) {
1168 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
1169 return DAG.getAtomic(N->getOpcode(), SDLoc(N), N->getMemoryVT(),
1170 N->getChain(), N->getBasePtr(), Op2, N->getMemOperand());
1171 }
1172
PromoteIntOp_BITCAST(SDNode * N)1173 SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
1174 // This should only occur in unusual situations like bitcasting to an
1175 // x86_fp80, so just turn it into a store+load
1176 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
1177 }
1178
PromoteIntOp_BR_CC(SDNode * N,unsigned OpNo)1179 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
1180 assert(OpNo == 2 && "Don't know how to promote this operand!");
1181
1182 SDValue LHS = N->getOperand(2);
1183 SDValue RHS = N->getOperand(3);
1184 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
1185
1186 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
1187 // legal types.
1188 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1189 N->getOperand(1), LHS, RHS, N->getOperand(4)),
1190 0);
1191 }
1192
PromoteIntOp_BRCOND(SDNode * N,unsigned OpNo)1193 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
1194 assert(OpNo == 1 && "only know how to promote condition");
1195
1196 // Promote all the way up to the canonical SetCC type.
1197 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), MVT::Other);
1198
1199 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
1200 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond,
1201 N->getOperand(2)), 0);
1202 }
1203
PromoteIntOp_BUILD_PAIR(SDNode * N)1204 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
1205 // Since the result type is legal, the operands must promote to it.
1206 EVT OVT = N->getOperand(0).getValueType();
1207 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
1208 SDValue Hi = GetPromotedInteger(N->getOperand(1));
1209 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
1210 SDLoc dl(N);
1211
1212 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
1213 DAG.getConstant(OVT.getSizeInBits(), dl,
1214 TLI.getPointerTy(DAG.getDataLayout())));
1215 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
1216 }
1217
PromoteIntOp_BUILD_VECTOR(SDNode * N)1218 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
1219 // The vector type is legal but the element type is not. This implies
1220 // that the vector is a power-of-two in length and that the element
1221 // type does not have a strange size (eg: it is not i1).
1222 EVT VecVT = N->getValueType(0);
1223 unsigned NumElts = VecVT.getVectorNumElements();
1224 assert(!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&
1225 "Legal vector of one illegal element?");
1226
1227 // Promote the inserted value. The type does not need to match the
1228 // vector element type. Check that any extra bits introduced will be
1229 // truncated away.
1230 assert(N->getOperand(0).getValueSizeInBits() >=
1231 N->getValueType(0).getScalarSizeInBits() &&
1232 "Type of inserted value narrower than vector element type!");
1233
1234 SmallVector<SDValue, 16> NewOps;
1235 for (unsigned i = 0; i < NumElts; ++i)
1236 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
1237
1238 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1239 }
1240
PromoteIntOp_INSERT_VECTOR_ELT(SDNode * N,unsigned OpNo)1241 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
1242 unsigned OpNo) {
1243 if (OpNo == 1) {
1244 // Promote the inserted value. This is valid because the type does not
1245 // have to match the vector element type.
1246
1247 // Check that any extra bits introduced will be truncated away.
1248 assert(N->getOperand(1).getValueSizeInBits() >=
1249 N->getValueType(0).getScalarSizeInBits() &&
1250 "Type of inserted value narrower than vector element type!");
1251 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1252 GetPromotedInteger(N->getOperand(1)),
1253 N->getOperand(2)),
1254 0);
1255 }
1256
1257 assert(OpNo == 2 && "Different operand and result vector types?");
1258
1259 // Promote the index.
1260 SDValue Idx = DAG.getZExtOrTrunc(N->getOperand(2), SDLoc(N),
1261 TLI.getVectorIdxTy(DAG.getDataLayout()));
1262 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1263 N->getOperand(1), Idx), 0);
1264 }
1265
PromoteIntOp_SCALAR_TO_VECTOR(SDNode * N)1266 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
1267 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
1268 // the operand in place.
1269 return SDValue(DAG.UpdateNodeOperands(N,
1270 GetPromotedInteger(N->getOperand(0))), 0);
1271 }
1272
PromoteIntOp_SELECT(SDNode * N,unsigned OpNo)1273 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
1274 assert(OpNo == 0 && "Only know how to promote the condition!");
1275 SDValue Cond = N->getOperand(0);
1276 EVT OpTy = N->getOperand(1).getValueType();
1277
1278 if (N->getOpcode() == ISD::VSELECT)
1279 if (SDValue Res = WidenVSELECTAndMask(N))
1280 return Res;
1281
1282 // Promote all the way up to the canonical SetCC type.
1283 EVT OpVT = N->getOpcode() == ISD::SELECT ? OpTy.getScalarType() : OpTy;
1284 Cond = PromoteTargetBoolean(Cond, OpVT);
1285
1286 return SDValue(DAG.UpdateNodeOperands(N, Cond, N->getOperand(1),
1287 N->getOperand(2)), 0);
1288 }
1289
PromoteIntOp_SELECT_CC(SDNode * N,unsigned OpNo)1290 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
1291 assert(OpNo == 0 && "Don't know how to promote this operand!");
1292
1293 SDValue LHS = N->getOperand(0);
1294 SDValue RHS = N->getOperand(1);
1295 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
1296
1297 // The CC (#4) and the possible return values (#2 and #3) have legal types.
1298 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2),
1299 N->getOperand(3), N->getOperand(4)), 0);
1300 }
1301
PromoteIntOp_SETCC(SDNode * N,unsigned OpNo)1302 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
1303 assert(OpNo == 0 && "Don't know how to promote this operand!");
1304
1305 SDValue LHS = N->getOperand(0);
1306 SDValue RHS = N->getOperand(1);
1307 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
1308
1309 // The CC (#2) is always legal.
1310 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0);
1311 }
1312
PromoteIntOp_Shift(SDNode * N)1313 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
1314 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1315 ZExtPromotedInteger(N->getOperand(1))), 0);
1316 }
1317
PromoteIntOp_SIGN_EXTEND(SDNode * N)1318 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
1319 SDValue Op = GetPromotedInteger(N->getOperand(0));
1320 SDLoc dl(N);
1321 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1322 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
1323 Op, DAG.getValueType(N->getOperand(0).getValueType()));
1324 }
1325
PromoteIntOp_SINT_TO_FP(SDNode * N)1326 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
1327 return SDValue(DAG.UpdateNodeOperands(N,
1328 SExtPromotedInteger(N->getOperand(0))), 0);
1329 }
1330
PromoteIntOp_STORE(StoreSDNode * N,unsigned OpNo)1331 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
1332 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
1333 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
1334 SDLoc dl(N);
1335
1336 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
1337
1338 // Truncate the value and store the result.
1339 return DAG.getTruncStore(Ch, dl, Val, Ptr,
1340 N->getMemoryVT(), N->getMemOperand());
1341 }
1342
PromoteIntOp_MSTORE(MaskedStoreSDNode * N,unsigned OpNo)1343 SDValue DAGTypeLegalizer::PromoteIntOp_MSTORE(MaskedStoreSDNode *N,
1344 unsigned OpNo) {
1345
1346 SDValue DataOp = N->getValue();
1347 EVT DataVT = DataOp.getValueType();
1348 SDValue Mask = N->getMask();
1349 SDLoc dl(N);
1350
1351 bool TruncateStore = false;
1352 if (OpNo == 3) {
1353 Mask = PromoteTargetBoolean(Mask, DataVT);
1354 // Update in place.
1355 SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
1356 NewOps[3] = Mask;
1357 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1358 } else { // Data operand
1359 assert(OpNo == 1 && "Unexpected operand for promotion");
1360 DataOp = GetPromotedInteger(DataOp);
1361 TruncateStore = true;
1362 }
1363
1364 return DAG.getMaskedStore(N->getChain(), dl, DataOp, N->getBasePtr(), Mask,
1365 N->getMemoryVT(), N->getMemOperand(),
1366 TruncateStore, N->isCompressingStore());
1367 }
1368
PromoteIntOp_MLOAD(MaskedLoadSDNode * N,unsigned OpNo)1369 SDValue DAGTypeLegalizer::PromoteIntOp_MLOAD(MaskedLoadSDNode *N,
1370 unsigned OpNo) {
1371 assert(OpNo == 2 && "Only know how to promote the mask!");
1372 EVT DataVT = N->getValueType(0);
1373 SDValue Mask = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
1374 SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
1375 NewOps[OpNo] = Mask;
1376 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1377 }
1378
PromoteIntOp_MGATHER(MaskedGatherSDNode * N,unsigned OpNo)1379 SDValue DAGTypeLegalizer::PromoteIntOp_MGATHER(MaskedGatherSDNode *N,
1380 unsigned OpNo) {
1381
1382 SmallVector<SDValue, 5> NewOps(N->op_begin(), N->op_end());
1383 if (OpNo == 2) {
1384 // The Mask
1385 EVT DataVT = N->getValueType(0);
1386 NewOps[OpNo] = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
1387 } else if (OpNo == 4) {
1388 // Need to sign extend the index since the bits will likely be used.
1389 NewOps[OpNo] = SExtPromotedInteger(N->getOperand(OpNo));
1390 } else
1391 NewOps[OpNo] = GetPromotedInteger(N->getOperand(OpNo));
1392
1393 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1394 }
1395
PromoteIntOp_MSCATTER(MaskedScatterSDNode * N,unsigned OpNo)1396 SDValue DAGTypeLegalizer::PromoteIntOp_MSCATTER(MaskedScatterSDNode *N,
1397 unsigned OpNo) {
1398 SmallVector<SDValue, 5> NewOps(N->op_begin(), N->op_end());
1399 if (OpNo == 2) {
1400 // The Mask
1401 EVT DataVT = N->getValue().getValueType();
1402 NewOps[OpNo] = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
1403 } else if (OpNo == 4) {
1404 // Need to sign extend the index since the bits will likely be used.
1405 NewOps[OpNo] = SExtPromotedInteger(N->getOperand(OpNo));
1406 } else
1407 NewOps[OpNo] = GetPromotedInteger(N->getOperand(OpNo));
1408 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1409 }
1410
PromoteIntOp_TRUNCATE(SDNode * N)1411 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
1412 SDValue Op = GetPromotedInteger(N->getOperand(0));
1413 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), Op);
1414 }
1415
PromoteIntOp_UINT_TO_FP(SDNode * N)1416 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
1417 return SDValue(DAG.UpdateNodeOperands(N,
1418 ZExtPromotedInteger(N->getOperand(0))), 0);
1419 }
1420
PromoteIntOp_ZERO_EXTEND(SDNode * N)1421 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
1422 SDLoc dl(N);
1423 SDValue Op = GetPromotedInteger(N->getOperand(0));
1424 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1425 return DAG.getZeroExtendInReg(Op, dl,
1426 N->getOperand(0).getValueType().getScalarType());
1427 }
1428
PromoteIntOp_ADDSUBCARRY(SDNode * N,unsigned OpNo)1429 SDValue DAGTypeLegalizer::PromoteIntOp_ADDSUBCARRY(SDNode *N, unsigned OpNo) {
1430 assert(OpNo == 2 && "Don't know how to promote this operand!");
1431
1432 SDValue LHS = N->getOperand(0);
1433 SDValue RHS = N->getOperand(1);
1434 SDValue Carry = N->getOperand(2);
1435 SDLoc DL(N);
1436
1437 auto VT = getSetCCResultType(LHS.getValueType());
1438 TargetLoweringBase::BooleanContent BoolType = TLI.getBooleanContents(VT);
1439 switch (BoolType) {
1440 case TargetLoweringBase::UndefinedBooleanContent:
1441 Carry = DAG.getAnyExtOrTrunc(Carry, DL, VT);
1442 break;
1443 case TargetLoweringBase::ZeroOrOneBooleanContent:
1444 Carry = DAG.getZExtOrTrunc(Carry, DL, VT);
1445 break;
1446 case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
1447 Carry = DAG.getSExtOrTrunc(Carry, DL, VT);
1448 break;
1449 }
1450
1451 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, Carry), 0);
1452 }
1453
PromoteIntOp_SMULFIX(SDNode * N)1454 SDValue DAGTypeLegalizer::PromoteIntOp_SMULFIX(SDNode *N) {
1455 SDValue Op2 = ZExtPromotedInteger(N->getOperand(2));
1456 return SDValue(
1457 DAG.UpdateNodeOperands(N, N->getOperand(0), N->getOperand(1), Op2), 0);
1458 }
1459
PromoteIntOp_FRAMERETURNADDR(SDNode * N)1460 SDValue DAGTypeLegalizer::PromoteIntOp_FRAMERETURNADDR(SDNode *N) {
1461 // Promote the RETURNADDR/FRAMEADDR argument to a supported integer width.
1462 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
1463 return SDValue(DAG.UpdateNodeOperands(N, Op), 0);
1464 }
1465
PromoteIntOp_PREFETCH(SDNode * N,unsigned OpNo)1466 SDValue DAGTypeLegalizer::PromoteIntOp_PREFETCH(SDNode *N, unsigned OpNo) {
1467 assert(OpNo > 1 && "Don't know how to promote this operand!");
1468 // Promote the rw, locality, and cache type arguments to a supported integer
1469 // width.
1470 SDValue Op2 = ZExtPromotedInteger(N->getOperand(2));
1471 SDValue Op3 = ZExtPromotedInteger(N->getOperand(3));
1472 SDValue Op4 = ZExtPromotedInteger(N->getOperand(4));
1473 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), N->getOperand(1),
1474 Op2, Op3, Op4),
1475 0);
1476 }
1477
1478 //===----------------------------------------------------------------------===//
1479 // Integer Result Expansion
1480 //===----------------------------------------------------------------------===//
1481
1482 /// ExpandIntegerResult - This method is called when the specified result of the
1483 /// specified node is found to need expansion. At this point, the node may also
1484 /// have invalid operands or may have other results that need promotion, we just
1485 /// know that (at least) one result needs expansion.
ExpandIntegerResult(SDNode * N,unsigned ResNo)1486 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
1487 LLVM_DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG);
1488 dbgs() << "\n");
1489 SDValue Lo, Hi;
1490 Lo = Hi = SDValue();
1491
1492 // See if the target wants to custom expand this node.
1493 if (CustomLowerNode(N, N->getValueType(ResNo), true))
1494 return;
1495
1496 switch (N->getOpcode()) {
1497 default:
1498 #ifndef NDEBUG
1499 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
1500 N->dump(&DAG); dbgs() << "\n";
1501 #endif
1502 llvm_unreachable("Do not know how to expand the result of this operator!");
1503
1504 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
1505 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
1506 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
1507 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
1508
1509 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
1510 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
1511 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
1512 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
1513 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
1514
1515 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
1516 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
1517 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
1518 case ISD::BITREVERSE: ExpandIntRes_BITREVERSE(N, Lo, Hi); break;
1519 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
1520 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
1521 case ISD::CTLZ_ZERO_UNDEF:
1522 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
1523 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
1524 case ISD::CTTZ_ZERO_UNDEF:
1525 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
1526 case ISD::FLT_ROUNDS_: ExpandIntRes_FLT_ROUNDS(N, Lo, Hi); break;
1527 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
1528 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
1529 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
1530 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
1531 case ISD::READCYCLECOUNTER: ExpandIntRes_READCYCLECOUNTER(N, Lo, Hi); break;
1532 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
1533 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
1534 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
1535 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
1536 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
1537 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
1538 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
1539 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
1540 case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
1541
1542 case ISD::ATOMIC_LOAD_ADD:
1543 case ISD::ATOMIC_LOAD_SUB:
1544 case ISD::ATOMIC_LOAD_AND:
1545 case ISD::ATOMIC_LOAD_CLR:
1546 case ISD::ATOMIC_LOAD_OR:
1547 case ISD::ATOMIC_LOAD_XOR:
1548 case ISD::ATOMIC_LOAD_NAND:
1549 case ISD::ATOMIC_LOAD_MIN:
1550 case ISD::ATOMIC_LOAD_MAX:
1551 case ISD::ATOMIC_LOAD_UMIN:
1552 case ISD::ATOMIC_LOAD_UMAX:
1553 case ISD::ATOMIC_SWAP:
1554 case ISD::ATOMIC_CMP_SWAP: {
1555 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(N);
1556 SplitInteger(Tmp.first, Lo, Hi);
1557 ReplaceValueWith(SDValue(N, 1), Tmp.second);
1558 break;
1559 }
1560 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
1561 AtomicSDNode *AN = cast<AtomicSDNode>(N);
1562 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::Other);
1563 SDValue Tmp = DAG.getAtomicCmpSwap(
1564 ISD::ATOMIC_CMP_SWAP, SDLoc(N), AN->getMemoryVT(), VTs,
1565 N->getOperand(0), N->getOperand(1), N->getOperand(2), N->getOperand(3),
1566 AN->getMemOperand());
1567
1568 // Expanding to the strong ATOMIC_CMP_SWAP node means we can determine
1569 // success simply by comparing the loaded value against the ingoing
1570 // comparison.
1571 SDValue Success = DAG.getSetCC(SDLoc(N), N->getValueType(1), Tmp,
1572 N->getOperand(2), ISD::SETEQ);
1573
1574 SplitInteger(Tmp, Lo, Hi);
1575 ReplaceValueWith(SDValue(N, 1), Success);
1576 ReplaceValueWith(SDValue(N, 2), Tmp.getValue(1));
1577 break;
1578 }
1579
1580 case ISD::AND:
1581 case ISD::OR:
1582 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
1583
1584 case ISD::UMAX:
1585 case ISD::SMAX:
1586 case ISD::UMIN:
1587 case ISD::SMIN: ExpandIntRes_MINMAX(N, Lo, Hi); break;
1588
1589 case ISD::ADD:
1590 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
1591
1592 case ISD::ADDC:
1593 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
1594
1595 case ISD::ADDE:
1596 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1597
1598 case ISD::ADDCARRY:
1599 case ISD::SUBCARRY: ExpandIntRes_ADDSUBCARRY(N, Lo, Hi); break;
1600
1601 case ISD::SHL:
1602 case ISD::SRA:
1603 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
1604
1605 case ISD::SADDO:
1606 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
1607 case ISD::UADDO:
1608 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
1609 case ISD::UMULO:
1610 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
1611
1612 case ISD::SADDSAT:
1613 case ISD::UADDSAT:
1614 case ISD::SSUBSAT:
1615 case ISD::USUBSAT: ExpandIntRes_ADDSUBSAT(N, Lo, Hi); break;
1616 case ISD::SMULFIX: ExpandIntRes_SMULFIX(N, Lo, Hi); break;
1617 }
1618
1619 // If Lo/Hi is null, the sub-method took care of registering results etc.
1620 if (Lo.getNode())
1621 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1622 }
1623
1624 /// Lower an atomic node to the appropriate builtin call.
ExpandAtomic(SDNode * Node)1625 std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
1626 unsigned Opc = Node->getOpcode();
1627 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
1628 RTLIB::Libcall LC = RTLIB::getSYNC(Opc, VT);
1629 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected atomic op or value type!");
1630
1631 return ExpandChainLibCall(LC, Node, false);
1632 }
1633
1634 /// N is a shift by a value that needs to be expanded,
1635 /// and the shift amount is a constant 'Amt'. Expand the operation.
ExpandShiftByConstant(SDNode * N,const APInt & Amt,SDValue & Lo,SDValue & Hi)1636 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, const APInt &Amt,
1637 SDValue &Lo, SDValue &Hi) {
1638 SDLoc DL(N);
1639 // Expand the incoming operand to be shifted, so that we have its parts
1640 SDValue InL, InH;
1641 GetExpandedInteger(N->getOperand(0), InL, InH);
1642
1643 // Though Amt shouldn't usually be 0, it's possible. E.g. when legalization
1644 // splitted a vector shift, like this: <op1, op2> SHL <0, 2>.
1645 if (!Amt) {
1646 Lo = InL;
1647 Hi = InH;
1648 return;
1649 }
1650
1651 EVT NVT = InL.getValueType();
1652 unsigned VTBits = N->getValueType(0).getSizeInBits();
1653 unsigned NVTBits = NVT.getSizeInBits();
1654 EVT ShTy = N->getOperand(1).getValueType();
1655
1656 if (N->getOpcode() == ISD::SHL) {
1657 if (Amt.ugt(VTBits)) {
1658 Lo = Hi = DAG.getConstant(0, DL, NVT);
1659 } else if (Amt.ugt(NVTBits)) {
1660 Lo = DAG.getConstant(0, DL, NVT);
1661 Hi = DAG.getNode(ISD::SHL, DL,
1662 NVT, InL, DAG.getConstant(Amt - NVTBits, DL, ShTy));
1663 } else if (Amt == NVTBits) {
1664 Lo = DAG.getConstant(0, DL, NVT);
1665 Hi = InL;
1666 } else {
1667 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, DL, ShTy));
1668 Hi = DAG.getNode(ISD::OR, DL, NVT,
1669 DAG.getNode(ISD::SHL, DL, NVT, InH,
1670 DAG.getConstant(Amt, DL, ShTy)),
1671 DAG.getNode(ISD::SRL, DL, NVT, InL,
1672 DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
1673 }
1674 return;
1675 }
1676
1677 if (N->getOpcode() == ISD::SRL) {
1678 if (Amt.ugt(VTBits)) {
1679 Lo = Hi = DAG.getConstant(0, DL, NVT);
1680 } else if (Amt.ugt(NVTBits)) {
1681 Lo = DAG.getNode(ISD::SRL, DL,
1682 NVT, InH, DAG.getConstant(Amt - NVTBits, DL, ShTy));
1683 Hi = DAG.getConstant(0, DL, NVT);
1684 } else if (Amt == NVTBits) {
1685 Lo = InH;
1686 Hi = DAG.getConstant(0, DL, NVT);
1687 } else {
1688 Lo = DAG.getNode(ISD::OR, DL, NVT,
1689 DAG.getNode(ISD::SRL, DL, NVT, InL,
1690 DAG.getConstant(Amt, DL, ShTy)),
1691 DAG.getNode(ISD::SHL, DL, NVT, InH,
1692 DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
1693 Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
1694 }
1695 return;
1696 }
1697
1698 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1699 if (Amt.ugt(VTBits)) {
1700 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1701 DAG.getConstant(NVTBits - 1, DL, ShTy));
1702 } else if (Amt.ugt(NVTBits)) {
1703 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1704 DAG.getConstant(Amt - NVTBits, DL, ShTy));
1705 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1706 DAG.getConstant(NVTBits - 1, DL, ShTy));
1707 } else if (Amt == NVTBits) {
1708 Lo = InH;
1709 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1710 DAG.getConstant(NVTBits - 1, DL, ShTy));
1711 } else {
1712 Lo = DAG.getNode(ISD::OR, DL, NVT,
1713 DAG.getNode(ISD::SRL, DL, NVT, InL,
1714 DAG.getConstant(Amt, DL, ShTy)),
1715 DAG.getNode(ISD::SHL, DL, NVT, InH,
1716 DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
1717 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
1718 }
1719 }
1720
1721 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1722 /// this shift based on knowledge of the high bit of the shift amount. If we
1723 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1724 /// shift amount.
1725 bool DAGTypeLegalizer::
ExpandShiftWithKnownAmountBit(SDNode * N,SDValue & Lo,SDValue & Hi)1726 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1727 SDValue Amt = N->getOperand(1);
1728 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1729 EVT ShTy = Amt.getValueType();
1730 unsigned ShBits = ShTy.getScalarSizeInBits();
1731 unsigned NVTBits = NVT.getScalarSizeInBits();
1732 assert(isPowerOf2_32(NVTBits) &&
1733 "Expanded integer type size not a power of two!");
1734 SDLoc dl(N);
1735
1736 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1737 KnownBits Known = DAG.computeKnownBits(N->getOperand(1));
1738
1739 // If we don't know anything about the high bits, exit.
1740 if (((Known.Zero|Known.One) & HighBitMask) == 0)
1741 return false;
1742
1743 // Get the incoming operand to be shifted.
1744 SDValue InL, InH;
1745 GetExpandedInteger(N->getOperand(0), InL, InH);
1746
1747 // If we know that any of the high bits of the shift amount are one, then we
1748 // can do this as a couple of simple shifts.
1749 if (Known.One.intersects(HighBitMask)) {
1750 // Mask out the high bit, which we know is set.
1751 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1752 DAG.getConstant(~HighBitMask, dl, ShTy));
1753
1754 switch (N->getOpcode()) {
1755 default: llvm_unreachable("Unknown shift");
1756 case ISD::SHL:
1757 Lo = DAG.getConstant(0, dl, NVT); // Low part is zero.
1758 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1759 return true;
1760 case ISD::SRL:
1761 Hi = DAG.getConstant(0, dl, NVT); // Hi part is zero.
1762 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1763 return true;
1764 case ISD::SRA:
1765 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1766 DAG.getConstant(NVTBits - 1, dl, ShTy));
1767 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1768 return true;
1769 }
1770 }
1771
1772 // If we know that all of the high bits of the shift amount are zero, then we
1773 // can do this as a couple of simple shifts.
1774 if (HighBitMask.isSubsetOf(Known.Zero)) {
1775 // Calculate 31-x. 31 is used instead of 32 to avoid creating an undefined
1776 // shift if x is zero. We can use XOR here because x is known to be smaller
1777 // than 32.
1778 SDValue Amt2 = DAG.getNode(ISD::XOR, dl, ShTy, Amt,
1779 DAG.getConstant(NVTBits - 1, dl, ShTy));
1780
1781 unsigned Op1, Op2;
1782 switch (N->getOpcode()) {
1783 default: llvm_unreachable("Unknown shift");
1784 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1785 case ISD::SRL:
1786 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1787 }
1788
1789 // When shifting right the arithmetic for Lo and Hi is swapped.
1790 if (N->getOpcode() != ISD::SHL)
1791 std::swap(InL, InH);
1792
1793 // Use a little trick to get the bits that move from Lo to Hi. First
1794 // shift by one bit.
1795 SDValue Sh1 = DAG.getNode(Op2, dl, NVT, InL, DAG.getConstant(1, dl, ShTy));
1796 // Then compute the remaining shift with amount-1.
1797 SDValue Sh2 = DAG.getNode(Op2, dl, NVT, Sh1, Amt2);
1798
1799 Lo = DAG.getNode(N->getOpcode(), dl, NVT, InL, Amt);
1800 Hi = DAG.getNode(ISD::OR, dl, NVT, DAG.getNode(Op1, dl, NVT, InH, Amt),Sh2);
1801
1802 if (N->getOpcode() != ISD::SHL)
1803 std::swap(Hi, Lo);
1804 return true;
1805 }
1806
1807 return false;
1808 }
1809
1810 /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
1811 /// of any size.
1812 bool DAGTypeLegalizer::
ExpandShiftWithUnknownAmountBit(SDNode * N,SDValue & Lo,SDValue & Hi)1813 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1814 SDValue Amt = N->getOperand(1);
1815 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1816 EVT ShTy = Amt.getValueType();
1817 unsigned NVTBits = NVT.getSizeInBits();
1818 assert(isPowerOf2_32(NVTBits) &&
1819 "Expanded integer type size not a power of two!");
1820 SDLoc dl(N);
1821
1822 // Get the incoming operand to be shifted.
1823 SDValue InL, InH;
1824 GetExpandedInteger(N->getOperand(0), InL, InH);
1825
1826 SDValue NVBitsNode = DAG.getConstant(NVTBits, dl, ShTy);
1827 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
1828 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
1829 SDValue isShort = DAG.getSetCC(dl, getSetCCResultType(ShTy),
1830 Amt, NVBitsNode, ISD::SETULT);
1831 SDValue isZero = DAG.getSetCC(dl, getSetCCResultType(ShTy),
1832 Amt, DAG.getConstant(0, dl, ShTy),
1833 ISD::SETEQ);
1834
1835 SDValue LoS, HiS, LoL, HiL;
1836 switch (N->getOpcode()) {
1837 default: llvm_unreachable("Unknown shift");
1838 case ISD::SHL:
1839 // Short: ShAmt < NVTBits
1840 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
1841 HiS = DAG.getNode(ISD::OR, dl, NVT,
1842 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
1843 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
1844
1845 // Long: ShAmt >= NVTBits
1846 LoL = DAG.getConstant(0, dl, NVT); // Lo part is zero.
1847 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
1848
1849 Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL);
1850 Hi = DAG.getSelect(dl, NVT, isZero, InH,
1851 DAG.getSelect(dl, NVT, isShort, HiS, HiL));
1852 return true;
1853 case ISD::SRL:
1854 // Short: ShAmt < NVTBits
1855 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
1856 LoS = DAG.getNode(ISD::OR, dl, NVT,
1857 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1858 // FIXME: If Amt is zero, the following shift generates an undefined result
1859 // on some architectures.
1860 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1861
1862 // Long: ShAmt >= NVTBits
1863 HiL = DAG.getConstant(0, dl, NVT); // Hi part is zero.
1864 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1865
1866 Lo = DAG.getSelect(dl, NVT, isZero, InL,
1867 DAG.getSelect(dl, NVT, isShort, LoS, LoL));
1868 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
1869 return true;
1870 case ISD::SRA:
1871 // Short: ShAmt < NVTBits
1872 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1873 LoS = DAG.getNode(ISD::OR, dl, NVT,
1874 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1875 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1876
1877 // Long: ShAmt >= NVTBits
1878 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
1879 DAG.getConstant(NVTBits - 1, dl, ShTy));
1880 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1881
1882 Lo = DAG.getSelect(dl, NVT, isZero, InL,
1883 DAG.getSelect(dl, NVT, isShort, LoS, LoL));
1884 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
1885 return true;
1886 }
1887 }
1888
getExpandedMinMaxOps(int Op)1889 static std::pair<ISD::CondCode, ISD::NodeType> getExpandedMinMaxOps(int Op) {
1890
1891 switch (Op) {
1892 default: llvm_unreachable("invalid min/max opcode");
1893 case ISD::SMAX:
1894 return std::make_pair(ISD::SETGT, ISD::UMAX);
1895 case ISD::UMAX:
1896 return std::make_pair(ISD::SETUGT, ISD::UMAX);
1897 case ISD::SMIN:
1898 return std::make_pair(ISD::SETLT, ISD::UMIN);
1899 case ISD::UMIN:
1900 return std::make_pair(ISD::SETULT, ISD::UMIN);
1901 }
1902 }
1903
ExpandIntRes_MINMAX(SDNode * N,SDValue & Lo,SDValue & Hi)1904 void DAGTypeLegalizer::ExpandIntRes_MINMAX(SDNode *N,
1905 SDValue &Lo, SDValue &Hi) {
1906 SDLoc DL(N);
1907 ISD::NodeType LoOpc;
1908 ISD::CondCode CondC;
1909 std::tie(CondC, LoOpc) = getExpandedMinMaxOps(N->getOpcode());
1910
1911 // Expand the subcomponents.
1912 SDValue LHSL, LHSH, RHSL, RHSH;
1913 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1914 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1915
1916 // Value types
1917 EVT NVT = LHSL.getValueType();
1918 EVT CCT = getSetCCResultType(NVT);
1919
1920 // Hi part is always the same op
1921 Hi = DAG.getNode(N->getOpcode(), DL, NVT, {LHSH, RHSH});
1922
1923 // We need to know whether to select Lo part that corresponds to 'winning'
1924 // Hi part or if Hi parts are equal.
1925 SDValue IsHiLeft = DAG.getSetCC(DL, CCT, LHSH, RHSH, CondC);
1926 SDValue IsHiEq = DAG.getSetCC(DL, CCT, LHSH, RHSH, ISD::SETEQ);
1927
1928 // Lo part corresponding to the 'winning' Hi part
1929 SDValue LoCmp = DAG.getSelect(DL, NVT, IsHiLeft, LHSL, RHSL);
1930
1931 // Recursed Lo part if Hi parts are equal, this uses unsigned version
1932 SDValue LoMinMax = DAG.getNode(LoOpc, DL, NVT, {LHSL, RHSL});
1933
1934 Lo = DAG.getSelect(DL, NVT, IsHiEq, LoMinMax, LoCmp);
1935 }
1936
ExpandIntRes_ADDSUB(SDNode * N,SDValue & Lo,SDValue & Hi)1937 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1938 SDValue &Lo, SDValue &Hi) {
1939 SDLoc dl(N);
1940 // Expand the subcomponents.
1941 SDValue LHSL, LHSH, RHSL, RHSH;
1942 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1943 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1944
1945 EVT NVT = LHSL.getValueType();
1946 SDValue LoOps[2] = { LHSL, RHSL };
1947 SDValue HiOps[3] = { LHSH, RHSH };
1948
1949 bool HasOpCarry = TLI.isOperationLegalOrCustom(
1950 N->getOpcode() == ISD::ADD ? ISD::ADDCARRY : ISD::SUBCARRY,
1951 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1952 if (HasOpCarry) {
1953 SDVTList VTList = DAG.getVTList(NVT, getSetCCResultType(NVT));
1954 if (N->getOpcode() == ISD::ADD) {
1955 Lo = DAG.getNode(ISD::UADDO, dl, VTList, LoOps);
1956 HiOps[2] = Lo.getValue(1);
1957 Hi = DAG.getNode(ISD::ADDCARRY, dl, VTList, HiOps);
1958 } else {
1959 Lo = DAG.getNode(ISD::USUBO, dl, VTList, LoOps);
1960 HiOps[2] = Lo.getValue(1);
1961 Hi = DAG.getNode(ISD::SUBCARRY, dl, VTList, HiOps);
1962 }
1963 return;
1964 }
1965
1966 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1967 // them. TODO: Teach operation legalization how to expand unsupported
1968 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1969 // a carry of type MVT::Glue, but there doesn't seem to be any way to
1970 // generate a value of this type in the expanded code sequence.
1971 bool hasCarry =
1972 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1973 ISD::ADDC : ISD::SUBC,
1974 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1975
1976 if (hasCarry) {
1977 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1978 if (N->getOpcode() == ISD::ADD) {
1979 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
1980 HiOps[2] = Lo.getValue(1);
1981 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
1982 } else {
1983 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
1984 HiOps[2] = Lo.getValue(1);
1985 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
1986 }
1987 return;
1988 }
1989
1990 bool hasOVF =
1991 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1992 ISD::UADDO : ISD::USUBO,
1993 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1994 TargetLoweringBase::BooleanContent BoolType = TLI.getBooleanContents(NVT);
1995
1996 if (hasOVF) {
1997 EVT OvfVT = getSetCCResultType(NVT);
1998 SDVTList VTList = DAG.getVTList(NVT, OvfVT);
1999 int RevOpc;
2000 if (N->getOpcode() == ISD::ADD) {
2001 RevOpc = ISD::SUB;
2002 Lo = DAG.getNode(ISD::UADDO, dl, VTList, LoOps);
2003 Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
2004 } else {
2005 RevOpc = ISD::ADD;
2006 Lo = DAG.getNode(ISD::USUBO, dl, VTList, LoOps);
2007 Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
2008 }
2009 SDValue OVF = Lo.getValue(1);
2010
2011 switch (BoolType) {
2012 case TargetLoweringBase::UndefinedBooleanContent:
2013 OVF = DAG.getNode(ISD::AND, dl, OvfVT, DAG.getConstant(1, dl, OvfVT), OVF);
2014 LLVM_FALLTHROUGH;
2015 case TargetLoweringBase::ZeroOrOneBooleanContent:
2016 OVF = DAG.getZExtOrTrunc(OVF, dl, NVT);
2017 Hi = DAG.getNode(N->getOpcode(), dl, NVT, Hi, OVF);
2018 break;
2019 case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
2020 OVF = DAG.getSExtOrTrunc(OVF, dl, NVT);
2021 Hi = DAG.getNode(RevOpc, dl, NVT, Hi, OVF);
2022 }
2023 return;
2024 }
2025
2026 if (N->getOpcode() == ISD::ADD) {
2027 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps);
2028 Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
2029 SDValue Cmp1 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0],
2030 ISD::SETULT);
2031
2032 if (BoolType == TargetLoweringBase::ZeroOrOneBooleanContent) {
2033 SDValue Carry = DAG.getZExtOrTrunc(Cmp1, dl, NVT);
2034 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry);
2035 return;
2036 }
2037
2038 SDValue Carry1 = DAG.getSelect(dl, NVT, Cmp1,
2039 DAG.getConstant(1, dl, NVT),
2040 DAG.getConstant(0, dl, NVT));
2041 SDValue Cmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[1],
2042 ISD::SETULT);
2043 SDValue Carry2 = DAG.getSelect(dl, NVT, Cmp2,
2044 DAG.getConstant(1, dl, NVT), Carry1);
2045 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
2046 } else {
2047 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps);
2048 Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
2049 SDValue Cmp =
2050 DAG.getSetCC(dl, getSetCCResultType(LoOps[0].getValueType()),
2051 LoOps[0], LoOps[1], ISD::SETULT);
2052
2053 SDValue Borrow;
2054 if (BoolType == TargetLoweringBase::ZeroOrOneBooleanContent)
2055 Borrow = DAG.getZExtOrTrunc(Cmp, dl, NVT);
2056 else
2057 Borrow = DAG.getSelect(dl, NVT, Cmp, DAG.getConstant(1, dl, NVT),
2058 DAG.getConstant(0, dl, NVT));
2059
2060 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
2061 }
2062 }
2063
ExpandIntRes_ADDSUBC(SDNode * N,SDValue & Lo,SDValue & Hi)2064 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
2065 SDValue &Lo, SDValue &Hi) {
2066 // Expand the subcomponents.
2067 SDValue LHSL, LHSH, RHSL, RHSH;
2068 SDLoc dl(N);
2069 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2070 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
2071 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
2072 SDValue LoOps[2] = { LHSL, RHSL };
2073 SDValue HiOps[3] = { LHSH, RHSH };
2074
2075 if (N->getOpcode() == ISD::ADDC) {
2076 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
2077 HiOps[2] = Lo.getValue(1);
2078 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
2079 } else {
2080 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
2081 HiOps[2] = Lo.getValue(1);
2082 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
2083 }
2084
2085 // Legalized the flag result - switch anything that used the old flag to
2086 // use the new one.
2087 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
2088 }
2089
ExpandIntRes_ADDSUBE(SDNode * N,SDValue & Lo,SDValue & Hi)2090 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
2091 SDValue &Lo, SDValue &Hi) {
2092 // Expand the subcomponents.
2093 SDValue LHSL, LHSH, RHSL, RHSH;
2094 SDLoc dl(N);
2095 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2096 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
2097 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
2098 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
2099 SDValue HiOps[3] = { LHSH, RHSH };
2100
2101 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
2102 HiOps[2] = Lo.getValue(1);
2103 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps);
2104
2105 // Legalized the flag result - switch anything that used the old flag to
2106 // use the new one.
2107 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
2108 }
2109
ExpandIntRes_UADDSUBO(SDNode * N,SDValue & Lo,SDValue & Hi)2110 void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
2111 SDValue &Lo, SDValue &Hi) {
2112 SDValue LHS = N->getOperand(0);
2113 SDValue RHS = N->getOperand(1);
2114 SDLoc dl(N);
2115
2116 SDValue Ovf;
2117
2118 bool HasOpCarry = TLI.isOperationLegalOrCustom(
2119 N->getOpcode() == ISD::ADD ? ISD::ADDCARRY : ISD::SUBCARRY,
2120 TLI.getTypeToExpandTo(*DAG.getContext(), LHS.getValueType()));
2121
2122 if (HasOpCarry) {
2123 // Expand the subcomponents.
2124 SDValue LHSL, LHSH, RHSL, RHSH;
2125 GetExpandedInteger(LHS, LHSL, LHSH);
2126 GetExpandedInteger(RHS, RHSL, RHSH);
2127 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), N->getValueType(1));
2128 SDValue LoOps[2] = { LHSL, RHSL };
2129 SDValue HiOps[3] = { LHSH, RHSH };
2130
2131 unsigned Opc = N->getOpcode() == ISD::UADDO ? ISD::ADDCARRY : ISD::SUBCARRY;
2132 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
2133 HiOps[2] = Lo.getValue(1);
2134 Hi = DAG.getNode(Opc, dl, VTList, HiOps);
2135
2136 Ovf = Hi.getValue(1);
2137 } else {
2138 // Expand the result by simply replacing it with the equivalent
2139 // non-overflow-checking operation.
2140 auto Opc = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
2141 SDValue Sum = DAG.getNode(Opc, dl, LHS.getValueType(), LHS, RHS);
2142 SplitInteger(Sum, Lo, Hi);
2143
2144 // Calculate the overflow: addition overflows iff a + b < a, and subtraction
2145 // overflows iff a - b > a.
2146 auto Cond = N->getOpcode() == ISD::UADDO ? ISD::SETULT : ISD::SETUGT;
2147 Ovf = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS, Cond);
2148 }
2149
2150 // Legalized the flag result - switch anything that used the old flag to
2151 // use the new one.
2152 ReplaceValueWith(SDValue(N, 1), Ovf);
2153 }
2154
ExpandIntRes_ADDSUBCARRY(SDNode * N,SDValue & Lo,SDValue & Hi)2155 void DAGTypeLegalizer::ExpandIntRes_ADDSUBCARRY(SDNode *N,
2156 SDValue &Lo, SDValue &Hi) {
2157 // Expand the subcomponents.
2158 SDValue LHSL, LHSH, RHSL, RHSH;
2159 SDLoc dl(N);
2160 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2161 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
2162 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), N->getValueType(1));
2163 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
2164 SDValue HiOps[3] = { LHSH, RHSH, SDValue() };
2165
2166 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
2167 HiOps[2] = Lo.getValue(1);
2168 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps);
2169
2170 // Legalized the flag result - switch anything that used the old flag to
2171 // use the new one.
2172 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
2173 }
2174
ExpandIntRes_ANY_EXTEND(SDNode * N,SDValue & Lo,SDValue & Hi)2175 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
2176 SDValue &Lo, SDValue &Hi) {
2177 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2178 SDLoc dl(N);
2179 SDValue Op = N->getOperand(0);
2180 if (Op.getValueType().bitsLE(NVT)) {
2181 // The low part is any extension of the input (which degenerates to a copy).
2182 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
2183 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
2184 } else {
2185 // For example, extension of an i48 to an i64. The operand type necessarily
2186 // promotes to the result type, so will end up being expanded too.
2187 assert(getTypeAction(Op.getValueType()) ==
2188 TargetLowering::TypePromoteInteger &&
2189 "Only know how to promote this result!");
2190 SDValue Res = GetPromotedInteger(Op);
2191 assert(Res.getValueType() == N->getValueType(0) &&
2192 "Operand over promoted?");
2193 // Split the promoted operand. This will simplify when it is expanded.
2194 SplitInteger(Res, Lo, Hi);
2195 }
2196 }
2197
ExpandIntRes_AssertSext(SDNode * N,SDValue & Lo,SDValue & Hi)2198 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
2199 SDValue &Lo, SDValue &Hi) {
2200 SDLoc dl(N);
2201 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2202 EVT NVT = Lo.getValueType();
2203 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2204 unsigned NVTBits = NVT.getSizeInBits();
2205 unsigned EVTBits = EVT.getSizeInBits();
2206
2207 if (NVTBits < EVTBits) {
2208 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
2209 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2210 EVTBits - NVTBits)));
2211 } else {
2212 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
2213 // The high part replicates the sign bit of Lo, make it explicit.
2214 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2215 DAG.getConstant(NVTBits - 1, dl,
2216 TLI.getPointerTy(DAG.getDataLayout())));
2217 }
2218 }
2219
ExpandIntRes_AssertZext(SDNode * N,SDValue & Lo,SDValue & Hi)2220 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
2221 SDValue &Lo, SDValue &Hi) {
2222 SDLoc dl(N);
2223 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2224 EVT NVT = Lo.getValueType();
2225 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2226 unsigned NVTBits = NVT.getSizeInBits();
2227 unsigned EVTBits = EVT.getSizeInBits();
2228
2229 if (NVTBits < EVTBits) {
2230 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
2231 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2232 EVTBits - NVTBits)));
2233 } else {
2234 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
2235 // The high part must be zero, make it explicit.
2236 Hi = DAG.getConstant(0, dl, NVT);
2237 }
2238 }
2239
ExpandIntRes_BITREVERSE(SDNode * N,SDValue & Lo,SDValue & Hi)2240 void DAGTypeLegalizer::ExpandIntRes_BITREVERSE(SDNode *N,
2241 SDValue &Lo, SDValue &Hi) {
2242 SDLoc dl(N);
2243 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
2244 Lo = DAG.getNode(ISD::BITREVERSE, dl, Lo.getValueType(), Lo);
2245 Hi = DAG.getNode(ISD::BITREVERSE, dl, Hi.getValueType(), Hi);
2246 }
2247
ExpandIntRes_BSWAP(SDNode * N,SDValue & Lo,SDValue & Hi)2248 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
2249 SDValue &Lo, SDValue &Hi) {
2250 SDLoc dl(N);
2251 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
2252 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
2253 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
2254 }
2255
ExpandIntRes_Constant(SDNode * N,SDValue & Lo,SDValue & Hi)2256 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
2257 SDValue &Lo, SDValue &Hi) {
2258 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2259 unsigned NBitWidth = NVT.getSizeInBits();
2260 auto Constant = cast<ConstantSDNode>(N);
2261 const APInt &Cst = Constant->getAPIntValue();
2262 bool IsTarget = Constant->isTargetOpcode();
2263 bool IsOpaque = Constant->isOpaque();
2264 SDLoc dl(N);
2265 Lo = DAG.getConstant(Cst.trunc(NBitWidth), dl, NVT, IsTarget, IsOpaque);
2266 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), dl, NVT, IsTarget,
2267 IsOpaque);
2268 }
2269
ExpandIntRes_CTLZ(SDNode * N,SDValue & Lo,SDValue & Hi)2270 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
2271 SDValue &Lo, SDValue &Hi) {
2272 SDLoc dl(N);
2273 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
2274 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2275 EVT NVT = Lo.getValueType();
2276
2277 SDValue HiNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Hi,
2278 DAG.getConstant(0, dl, NVT), ISD::SETNE);
2279
2280 SDValue LoLZ = DAG.getNode(N->getOpcode(), dl, NVT, Lo);
2281 SDValue HiLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, NVT, Hi);
2282
2283 Lo = DAG.getSelect(dl, NVT, HiNotZero, HiLZ,
2284 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
2285 DAG.getConstant(NVT.getSizeInBits(), dl,
2286 NVT)));
2287 Hi = DAG.getConstant(0, dl, NVT);
2288 }
2289
ExpandIntRes_CTPOP(SDNode * N,SDValue & Lo,SDValue & Hi)2290 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
2291 SDValue &Lo, SDValue &Hi) {
2292 SDLoc dl(N);
2293 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
2294 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2295 EVT NVT = Lo.getValueType();
2296 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
2297 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
2298 Hi = DAG.getConstant(0, dl, NVT);
2299 }
2300
ExpandIntRes_CTTZ(SDNode * N,SDValue & Lo,SDValue & Hi)2301 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
2302 SDValue &Lo, SDValue &Hi) {
2303 SDLoc dl(N);
2304 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
2305 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2306 EVT NVT = Lo.getValueType();
2307
2308 SDValue LoNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo,
2309 DAG.getConstant(0, dl, NVT), ISD::SETNE);
2310
2311 SDValue LoLZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, NVT, Lo);
2312 SDValue HiLZ = DAG.getNode(N->getOpcode(), dl, NVT, Hi);
2313
2314 Lo = DAG.getSelect(dl, NVT, LoNotZero, LoLZ,
2315 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
2316 DAG.getConstant(NVT.getSizeInBits(), dl,
2317 NVT)));
2318 Hi = DAG.getConstant(0, dl, NVT);
2319 }
2320
ExpandIntRes_FLT_ROUNDS(SDNode * N,SDValue & Lo,SDValue & Hi)2321 void DAGTypeLegalizer::ExpandIntRes_FLT_ROUNDS(SDNode *N, SDValue &Lo,
2322 SDValue &Hi) {
2323 SDLoc dl(N);
2324 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2325 unsigned NBitWidth = NVT.getSizeInBits();
2326
2327 EVT ShiftAmtTy = TLI.getShiftAmountTy(NVT, DAG.getDataLayout());
2328 Lo = DAG.getNode(ISD::FLT_ROUNDS_, dl, NVT);
2329 // The high part is the sign of Lo, as -1 is a valid value for FLT_ROUNDS
2330 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2331 DAG.getConstant(NBitWidth - 1, dl, ShiftAmtTy));
2332 }
2333
ExpandIntRes_FP_TO_SINT(SDNode * N,SDValue & Lo,SDValue & Hi)2334 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
2335 SDValue &Hi) {
2336 SDLoc dl(N);
2337 EVT VT = N->getValueType(0);
2338
2339 SDValue Op = N->getOperand(0);
2340 if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
2341 Op = GetPromotedFloat(Op);
2342
2343 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
2344 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
2345 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Op, true/*irrelevant*/, dl).first,
2346 Lo, Hi);
2347 }
2348
ExpandIntRes_FP_TO_UINT(SDNode * N,SDValue & Lo,SDValue & Hi)2349 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
2350 SDValue &Hi) {
2351 SDLoc dl(N);
2352 EVT VT = N->getValueType(0);
2353
2354 SDValue Op = N->getOperand(0);
2355 if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
2356 Op = GetPromotedFloat(Op);
2357
2358 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
2359 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
2360 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Op, false/*irrelevant*/, dl).first,
2361 Lo, Hi);
2362 }
2363
ExpandIntRes_LOAD(LoadSDNode * N,SDValue & Lo,SDValue & Hi)2364 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
2365 SDValue &Lo, SDValue &Hi) {
2366 if (ISD::isNormalLoad(N)) {
2367 ExpandRes_NormalLoad(N, Lo, Hi);
2368 return;
2369 }
2370
2371 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
2372
2373 EVT VT = N->getValueType(0);
2374 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2375 SDValue Ch = N->getChain();
2376 SDValue Ptr = N->getBasePtr();
2377 ISD::LoadExtType ExtType = N->getExtensionType();
2378 unsigned Alignment = N->getAlignment();
2379 MachineMemOperand::Flags MMOFlags = N->getMemOperand()->getFlags();
2380 AAMDNodes AAInfo = N->getAAInfo();
2381 SDLoc dl(N);
2382
2383 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2384
2385 if (N->getMemoryVT().bitsLE(NVT)) {
2386 EVT MemVT = N->getMemoryVT();
2387
2388 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(), MemVT,
2389 Alignment, MMOFlags, AAInfo);
2390
2391 // Remember the chain.
2392 Ch = Lo.getValue(1);
2393
2394 if (ExtType == ISD::SEXTLOAD) {
2395 // The high part is obtained by SRA'ing all but one of the bits of the
2396 // lo part.
2397 unsigned LoSize = Lo.getValueSizeInBits();
2398 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2399 DAG.getConstant(LoSize - 1, dl,
2400 TLI.getPointerTy(DAG.getDataLayout())));
2401 } else if (ExtType == ISD::ZEXTLOAD) {
2402 // The high part is just a zero.
2403 Hi = DAG.getConstant(0, dl, NVT);
2404 } else {
2405 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
2406 // The high part is undefined.
2407 Hi = DAG.getUNDEF(NVT);
2408 }
2409 } else if (DAG.getDataLayout().isLittleEndian()) {
2410 // Little-endian - low bits are at low addresses.
2411 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(), Alignment, MMOFlags,
2412 AAInfo);
2413
2414 unsigned ExcessBits =
2415 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2416 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2417
2418 // Increment the pointer to the other half.
2419 unsigned IncrementSize = NVT.getSizeInBits()/8;
2420 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2421 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
2422 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr,
2423 N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
2424 MinAlign(Alignment, IncrementSize), MMOFlags, AAInfo);
2425
2426 // Build a factor node to remember that this load is independent of the
2427 // other one.
2428 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2429 Hi.getValue(1));
2430 } else {
2431 // Big-endian - high bits are at low addresses. Favor aligned loads at
2432 // the cost of some bit-fiddling.
2433 EVT MemVT = N->getMemoryVT();
2434 unsigned EBytes = MemVT.getStoreSize();
2435 unsigned IncrementSize = NVT.getSizeInBits()/8;
2436 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2437
2438 // Load both the high bits and maybe some of the low bits.
2439 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
2440 EVT::getIntegerVT(*DAG.getContext(),
2441 MemVT.getSizeInBits() - ExcessBits),
2442 Alignment, MMOFlags, AAInfo);
2443
2444 // Increment the pointer to the other half.
2445 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2446 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
2447 // Load the rest of the low bits.
2448 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr,
2449 N->getPointerInfo().getWithOffset(IncrementSize),
2450 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2451 MinAlign(Alignment, IncrementSize), MMOFlags, AAInfo);
2452
2453 // Build a factor node to remember that this load is independent of the
2454 // other one.
2455 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2456 Hi.getValue(1));
2457
2458 if (ExcessBits < NVT.getSizeInBits()) {
2459 // Transfer low bits from the bottom of Hi to the top of Lo.
2460 Lo = DAG.getNode(
2461 ISD::OR, dl, NVT, Lo,
2462 DAG.getNode(ISD::SHL, dl, NVT, Hi,
2463 DAG.getConstant(ExcessBits, dl,
2464 TLI.getPointerTy(DAG.getDataLayout()))));
2465 // Move high bits to the right position in Hi.
2466 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, NVT,
2467 Hi,
2468 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, dl,
2469 TLI.getPointerTy(DAG.getDataLayout())));
2470 }
2471 }
2472
2473 // Legalize the chain result - switch anything that used the old chain to
2474 // use the new one.
2475 ReplaceValueWith(SDValue(N, 1), Ch);
2476 }
2477
ExpandIntRes_Logical(SDNode * N,SDValue & Lo,SDValue & Hi)2478 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
2479 SDValue &Lo, SDValue &Hi) {
2480 SDLoc dl(N);
2481 SDValue LL, LH, RL, RH;
2482 GetExpandedInteger(N->getOperand(0), LL, LH);
2483 GetExpandedInteger(N->getOperand(1), RL, RH);
2484 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
2485 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
2486 }
2487
ExpandIntRes_MUL(SDNode * N,SDValue & Lo,SDValue & Hi)2488 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
2489 SDValue &Lo, SDValue &Hi) {
2490 EVT VT = N->getValueType(0);
2491 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2492 SDLoc dl(N);
2493
2494 SDValue LL, LH, RL, RH;
2495 GetExpandedInteger(N->getOperand(0), LL, LH);
2496 GetExpandedInteger(N->getOperand(1), RL, RH);
2497
2498 if (TLI.expandMUL(N, Lo, Hi, NVT, DAG,
2499 TargetLowering::MulExpansionKind::OnlyLegalOrCustom,
2500 LL, LH, RL, RH))
2501 return;
2502
2503 // If nothing else, we can make a libcall.
2504 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2505 if (VT == MVT::i16)
2506 LC = RTLIB::MUL_I16;
2507 else if (VT == MVT::i32)
2508 LC = RTLIB::MUL_I32;
2509 else if (VT == MVT::i64)
2510 LC = RTLIB::MUL_I64;
2511 else if (VT == MVT::i128)
2512 LC = RTLIB::MUL_I128;
2513
2514 if (LC == RTLIB::UNKNOWN_LIBCALL || !TLI.getLibcallName(LC)) {
2515 // We'll expand the multiplication by brute force because we have no other
2516 // options. This is a trivially-generalized version of the code from
2517 // Hacker's Delight (itself derived from Knuth's Algorithm M from section
2518 // 4.3.1).
2519 unsigned Bits = NVT.getSizeInBits();
2520 unsigned HalfBits = Bits >> 1;
2521 SDValue Mask = DAG.getConstant(APInt::getLowBitsSet(Bits, HalfBits), dl,
2522 NVT);
2523 SDValue LLL = DAG.getNode(ISD::AND, dl, NVT, LL, Mask);
2524 SDValue RLL = DAG.getNode(ISD::AND, dl, NVT, RL, Mask);
2525
2526 SDValue T = DAG.getNode(ISD::MUL, dl, NVT, LLL, RLL);
2527 SDValue TL = DAG.getNode(ISD::AND, dl, NVT, T, Mask);
2528
2529 EVT ShiftAmtTy = TLI.getShiftAmountTy(NVT, DAG.getDataLayout());
2530 if (APInt::getMaxValue(ShiftAmtTy.getSizeInBits()).ult(HalfBits)) {
2531 // The type from TLI is too small to fit the shift amount we want.
2532 // Override it with i32. The shift will have to be legalized.
2533 ShiftAmtTy = MVT::i32;
2534 }
2535 SDValue Shift = DAG.getConstant(HalfBits, dl, ShiftAmtTy);
2536 SDValue TH = DAG.getNode(ISD::SRL, dl, NVT, T, Shift);
2537 SDValue LLH = DAG.getNode(ISD::SRL, dl, NVT, LL, Shift);
2538 SDValue RLH = DAG.getNode(ISD::SRL, dl, NVT, RL, Shift);
2539
2540 SDValue U = DAG.getNode(ISD::ADD, dl, NVT,
2541 DAG.getNode(ISD::MUL, dl, NVT, LLH, RLL), TH);
2542 SDValue UL = DAG.getNode(ISD::AND, dl, NVT, U, Mask);
2543 SDValue UH = DAG.getNode(ISD::SRL, dl, NVT, U, Shift);
2544
2545 SDValue V = DAG.getNode(ISD::ADD, dl, NVT,
2546 DAG.getNode(ISD::MUL, dl, NVT, LLL, RLH), UL);
2547 SDValue VH = DAG.getNode(ISD::SRL, dl, NVT, V, Shift);
2548
2549 SDValue W = DAG.getNode(ISD::ADD, dl, NVT,
2550 DAG.getNode(ISD::MUL, dl, NVT, LLH, RLH),
2551 DAG.getNode(ISD::ADD, dl, NVT, UH, VH));
2552 Lo = DAG.getNode(ISD::ADD, dl, NVT, TL,
2553 DAG.getNode(ISD::SHL, dl, NVT, V, Shift));
2554
2555 Hi = DAG.getNode(ISD::ADD, dl, NVT, W,
2556 DAG.getNode(ISD::ADD, dl, NVT,
2557 DAG.getNode(ISD::MUL, dl, NVT, RH, LL),
2558 DAG.getNode(ISD::MUL, dl, NVT, RL, LH)));
2559 return;
2560 }
2561
2562 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2563 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, true/*irrelevant*/, dl).first,
2564 Lo, Hi);
2565 }
2566
ExpandIntRes_READCYCLECOUNTER(SDNode * N,SDValue & Lo,SDValue & Hi)2567 void DAGTypeLegalizer::ExpandIntRes_READCYCLECOUNTER(SDNode *N, SDValue &Lo,
2568 SDValue &Hi) {
2569 SDLoc DL(N);
2570 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2571 SDVTList VTs = DAG.getVTList(NVT, NVT, MVT::Other);
2572 SDValue R = DAG.getNode(N->getOpcode(), DL, VTs, N->getOperand(0));
2573 Lo = R.getValue(0);
2574 Hi = R.getValue(1);
2575 ReplaceValueWith(SDValue(N, 1), R.getValue(2));
2576 }
2577
ExpandIntRes_ADDSUBSAT(SDNode * N,SDValue & Lo,SDValue & Hi)2578 void DAGTypeLegalizer::ExpandIntRes_ADDSUBSAT(SDNode *N, SDValue &Lo,
2579 SDValue &Hi) {
2580 SDValue Result = TLI.expandAddSubSat(N, DAG);
2581 SplitInteger(Result, Lo, Hi);
2582 }
2583
ExpandIntRes_SMULFIX(SDNode * N,SDValue & Lo,SDValue & Hi)2584 void DAGTypeLegalizer::ExpandIntRes_SMULFIX(SDNode *N, SDValue &Lo,
2585 SDValue &Hi) {
2586 SDLoc dl(N);
2587 EVT VT = N->getValueType(0);
2588 SDValue LHS = N->getOperand(0);
2589 SDValue RHS = N->getOperand(1);
2590 uint64_t Scale = N->getConstantOperandVal(2);
2591 if (!Scale) {
2592 SDValue Result = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
2593 SplitInteger(Result, Lo, Hi);
2594 return;
2595 }
2596
2597 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2598 SDValue LL, LH, RL, RH;
2599 GetExpandedInteger(LHS, LL, LH);
2600 GetExpandedInteger(RHS, RL, RH);
2601 SmallVector<SDValue, 4> Result;
2602
2603 if (!TLI.expandMUL_LOHI(ISD::SMUL_LOHI, VT, dl, LHS, RHS, Result, NVT, DAG,
2604 TargetLowering::MulExpansionKind::OnlyLegalOrCustom,
2605 LL, LH, RL, RH)) {
2606 report_fatal_error("Unable to expand SMUL_FIX using SMUL_LOHI.");
2607 return;
2608 }
2609
2610 unsigned VTSize = VT.getScalarSizeInBits();
2611 unsigned NVTSize = NVT.getScalarSizeInBits();
2612 EVT ShiftTy = TLI.getShiftAmountTy(NVT, DAG.getDataLayout());
2613
2614 // Shift whole amount by scale.
2615 SDValue ResultLL = Result[0];
2616 SDValue ResultLH = Result[1];
2617 SDValue ResultHL = Result[2];
2618 SDValue ResultHH = Result[3];
2619
2620 // After getting the multplication result in 4 parts, we need to perform a
2621 // shift right by the amount of the scale to get the result in that scale.
2622 // Let's say we multiply 2 64 bit numbers. The resulting value can be held in
2623 // 128 bits that are cut into 4 32-bit parts:
2624 //
2625 // HH HL LH LL
2626 // |---32---|---32---|---32---|---32---|
2627 // 128 96 64 32 0
2628 //
2629 // |------VTSize-----|
2630 //
2631 // |NVTSize-|
2632 //
2633 // The resulting Lo and Hi will only need to be one of these 32-bit parts
2634 // after shifting.
2635 if (Scale < NVTSize) {
2636 // If the scale is less than the size of the VT we expand to, the Hi and
2637 // Lo of the result will be in the first 2 parts of the result after
2638 // shifting right. This only requires shifting by the scale as far as the
2639 // third part in the result (ResultHL).
2640 SDValue SRLAmnt = DAG.getConstant(Scale, dl, ShiftTy);
2641 SDValue SHLAmnt = DAG.getConstant(NVTSize - Scale, dl, ShiftTy);
2642 Lo = DAG.getNode(ISD::SRL, dl, NVT, ResultLL, SRLAmnt);
2643 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo,
2644 DAG.getNode(ISD::SHL, dl, NVT, ResultLH, SHLAmnt));
2645 Hi = DAG.getNode(ISD::SRL, dl, NVT, ResultLH, SRLAmnt);
2646 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
2647 DAG.getNode(ISD::SHL, dl, NVT, ResultHL, SHLAmnt));
2648 } else if (Scale == NVTSize) {
2649 // If the scales are equal, Lo and Hi are ResultLH and Result HL,
2650 // respectively. Avoid shifting to prevent undefined behavior.
2651 Lo = ResultLH;
2652 Hi = ResultHL;
2653 } else if (Scale < VTSize) {
2654 // If the scale is instead less than the old VT size, but greater than or
2655 // equal to the expanded VT size, the first part of the result (ResultLL) is
2656 // no longer a part of Lo because it would be scaled out anyway. Instead we
2657 // can start shifting right from the fourth part (ResultHH) to the second
2658 // part (ResultLH), and Result LH will be the new Lo.
2659 SDValue SRLAmnt = DAG.getConstant(Scale - NVTSize, dl, ShiftTy);
2660 SDValue SHLAmnt = DAG.getConstant(VTSize - Scale, dl, ShiftTy);
2661 Lo = DAG.getNode(ISD::SRL, dl, NVT, ResultLH, SRLAmnt);
2662 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo,
2663 DAG.getNode(ISD::SHL, dl, NVT, ResultHL, SHLAmnt));
2664 Hi = DAG.getNode(ISD::SRL, dl, NVT, ResultHL, SRLAmnt);
2665 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
2666 DAG.getNode(ISD::SHL, dl, NVT, ResultHH, SHLAmnt));
2667 } else {
2668 llvm_unreachable(
2669 "Expected the scale to be less than the width of the operands");
2670 }
2671 }
2672
ExpandIntRes_SADDSUBO(SDNode * Node,SDValue & Lo,SDValue & Hi)2673 void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
2674 SDValue &Lo, SDValue &Hi) {
2675 SDValue LHS = Node->getOperand(0);
2676 SDValue RHS = Node->getOperand(1);
2677 SDLoc dl(Node);
2678
2679 // Expand the result by simply replacing it with the equivalent
2680 // non-overflow-checking operation.
2681 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
2682 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2683 LHS, RHS);
2684 SplitInteger(Sum, Lo, Hi);
2685
2686 // Compute the overflow.
2687 //
2688 // LHSSign -> LHS >= 0
2689 // RHSSign -> RHS >= 0
2690 // SumSign -> Sum >= 0
2691 //
2692 // Add:
2693 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
2694 // Sub:
2695 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
2696 //
2697 EVT OType = Node->getValueType(1);
2698 SDValue Zero = DAG.getConstant(0, dl, LHS.getValueType());
2699
2700 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
2701 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
2702 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
2703 Node->getOpcode() == ISD::SADDO ?
2704 ISD::SETEQ : ISD::SETNE);
2705
2706 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
2707 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
2708
2709 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
2710
2711 // Use the calculated overflow everywhere.
2712 ReplaceValueWith(SDValue(Node, 1), Cmp);
2713 }
2714
ExpandIntRes_SDIV(SDNode * N,SDValue & Lo,SDValue & Hi)2715 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
2716 SDValue &Lo, SDValue &Hi) {
2717 EVT VT = N->getValueType(0);
2718 SDLoc dl(N);
2719 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2720
2721 if (TLI.getOperationAction(ISD::SDIVREM, VT) == TargetLowering::Custom) {
2722 SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops);
2723 SplitInteger(Res.getValue(0), Lo, Hi);
2724 return;
2725 }
2726
2727 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2728 if (VT == MVT::i16)
2729 LC = RTLIB::SDIV_I16;
2730 else if (VT == MVT::i32)
2731 LC = RTLIB::SDIV_I32;
2732 else if (VT == MVT::i64)
2733 LC = RTLIB::SDIV_I64;
2734 else if (VT == MVT::i128)
2735 LC = RTLIB::SDIV_I128;
2736 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
2737
2738 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, true, dl).first, Lo, Hi);
2739 }
2740
ExpandIntRes_Shift(SDNode * N,SDValue & Lo,SDValue & Hi)2741 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
2742 SDValue &Lo, SDValue &Hi) {
2743 EVT VT = N->getValueType(0);
2744 SDLoc dl(N);
2745
2746 // If we can emit an efficient shift operation, do so now. Check to see if
2747 // the RHS is a constant.
2748 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2749 return ExpandShiftByConstant(N, CN->getAPIntValue(), Lo, Hi);
2750
2751 // If we can determine that the high bit of the shift is zero or one, even if
2752 // the low bits are variable, emit this shift in an optimized form.
2753 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
2754 return;
2755
2756 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
2757 unsigned PartsOpc;
2758 if (N->getOpcode() == ISD::SHL) {
2759 PartsOpc = ISD::SHL_PARTS;
2760 } else if (N->getOpcode() == ISD::SRL) {
2761 PartsOpc = ISD::SRL_PARTS;
2762 } else {
2763 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2764 PartsOpc = ISD::SRA_PARTS;
2765 }
2766
2767 // Next check to see if the target supports this SHL_PARTS operation or if it
2768 // will custom expand it.
2769 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2770 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
2771 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
2772 Action == TargetLowering::Custom) {
2773 // Expand the subcomponents.
2774 SDValue LHSL, LHSH;
2775 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2776 EVT VT = LHSL.getValueType();
2777
2778 // If the shift amount operand is coming from a vector legalization it may
2779 // have an illegal type. Fix that first by casting the operand, otherwise
2780 // the new SHL_PARTS operation would need further legalization.
2781 SDValue ShiftOp = N->getOperand(1);
2782 EVT ShiftTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2783 assert(ShiftTy.getScalarSizeInBits() >=
2784 Log2_32_Ceil(VT.getScalarSizeInBits()) &&
2785 "ShiftAmountTy is too small to cover the range of this type!");
2786 if (ShiftOp.getValueType() != ShiftTy)
2787 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy);
2788
2789 SDValue Ops[] = { LHSL, LHSH, ShiftOp };
2790 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops);
2791 Hi = Lo.getValue(1);
2792 return;
2793 }
2794
2795 // Otherwise, emit a libcall.
2796 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2797 bool isSigned;
2798 if (N->getOpcode() == ISD::SHL) {
2799 isSigned = false; /*sign irrelevant*/
2800 if (VT == MVT::i16)
2801 LC = RTLIB::SHL_I16;
2802 else if (VT == MVT::i32)
2803 LC = RTLIB::SHL_I32;
2804 else if (VT == MVT::i64)
2805 LC = RTLIB::SHL_I64;
2806 else if (VT == MVT::i128)
2807 LC = RTLIB::SHL_I128;
2808 } else if (N->getOpcode() == ISD::SRL) {
2809 isSigned = false;
2810 if (VT == MVT::i16)
2811 LC = RTLIB::SRL_I16;
2812 else if (VT == MVT::i32)
2813 LC = RTLIB::SRL_I32;
2814 else if (VT == MVT::i64)
2815 LC = RTLIB::SRL_I64;
2816 else if (VT == MVT::i128)
2817 LC = RTLIB::SRL_I128;
2818 } else {
2819 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2820 isSigned = true;
2821 if (VT == MVT::i16)
2822 LC = RTLIB::SRA_I16;
2823 else if (VT == MVT::i32)
2824 LC = RTLIB::SRA_I32;
2825 else if (VT == MVT::i64)
2826 LC = RTLIB::SRA_I64;
2827 else if (VT == MVT::i128)
2828 LC = RTLIB::SRA_I128;
2829 }
2830
2831 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
2832 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2833 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, isSigned, dl).first, Lo, Hi);
2834 return;
2835 }
2836
2837 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
2838 llvm_unreachable("Unsupported shift!");
2839 }
2840
ExpandIntRes_SIGN_EXTEND(SDNode * N,SDValue & Lo,SDValue & Hi)2841 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
2842 SDValue &Lo, SDValue &Hi) {
2843 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2844 SDLoc dl(N);
2845 SDValue Op = N->getOperand(0);
2846 if (Op.getValueType().bitsLE(NVT)) {
2847 // The low part is sign extension of the input (degenerates to a copy).
2848 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
2849 // The high part is obtained by SRA'ing all but one of the bits of low part.
2850 unsigned LoSize = NVT.getSizeInBits();
2851 Hi = DAG.getNode(
2852 ISD::SRA, dl, NVT, Lo,
2853 DAG.getConstant(LoSize - 1, dl, TLI.getPointerTy(DAG.getDataLayout())));
2854 } else {
2855 // For example, extension of an i48 to an i64. The operand type necessarily
2856 // promotes to the result type, so will end up being expanded too.
2857 assert(getTypeAction(Op.getValueType()) ==
2858 TargetLowering::TypePromoteInteger &&
2859 "Only know how to promote this result!");
2860 SDValue Res = GetPromotedInteger(Op);
2861 assert(Res.getValueType() == N->getValueType(0) &&
2862 "Operand over promoted?");
2863 // Split the promoted operand. This will simplify when it is expanded.
2864 SplitInteger(Res, Lo, Hi);
2865 unsigned ExcessBits = Op.getValueSizeInBits() - NVT.getSizeInBits();
2866 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2867 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2868 ExcessBits)));
2869 }
2870 }
2871
2872 void DAGTypeLegalizer::
ExpandIntRes_SIGN_EXTEND_INREG(SDNode * N,SDValue & Lo,SDValue & Hi)2873 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
2874 SDLoc dl(N);
2875 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2876 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2877
2878 if (EVT.bitsLE(Lo.getValueType())) {
2879 // sext_inreg the low part if needed.
2880 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
2881 N->getOperand(1));
2882
2883 // The high part gets the sign extension from the lo-part. This handles
2884 // things like sextinreg V:i64 from i8.
2885 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
2886 DAG.getConstant(Hi.getValueSizeInBits() - 1, dl,
2887 TLI.getPointerTy(DAG.getDataLayout())));
2888 } else {
2889 // For example, extension of an i48 to an i64. Leave the low part alone,
2890 // sext_inreg the high part.
2891 unsigned ExcessBits = EVT.getSizeInBits() - Lo.getValueSizeInBits();
2892 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2893 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2894 ExcessBits)));
2895 }
2896 }
2897
ExpandIntRes_SREM(SDNode * N,SDValue & Lo,SDValue & Hi)2898 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
2899 SDValue &Lo, SDValue &Hi) {
2900 EVT VT = N->getValueType(0);
2901 SDLoc dl(N);
2902 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2903
2904 if (TLI.getOperationAction(ISD::SDIVREM, VT) == TargetLowering::Custom) {
2905 SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops);
2906 SplitInteger(Res.getValue(1), Lo, Hi);
2907 return;
2908 }
2909
2910 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2911 if (VT == MVT::i16)
2912 LC = RTLIB::SREM_I16;
2913 else if (VT == MVT::i32)
2914 LC = RTLIB::SREM_I32;
2915 else if (VT == MVT::i64)
2916 LC = RTLIB::SREM_I64;
2917 else if (VT == MVT::i128)
2918 LC = RTLIB::SREM_I128;
2919 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
2920
2921 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, true, dl).first, Lo, Hi);
2922 }
2923
ExpandIntRes_TRUNCATE(SDNode * N,SDValue & Lo,SDValue & Hi)2924 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
2925 SDValue &Lo, SDValue &Hi) {
2926 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2927 SDLoc dl(N);
2928 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
2929 Hi = DAG.getNode(ISD::SRL, dl, N->getOperand(0).getValueType(),
2930 N->getOperand(0),
2931 DAG.getConstant(NVT.getSizeInBits(), dl,
2932 TLI.getPointerTy(DAG.getDataLayout())));
2933 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
2934 }
2935
ExpandIntRes_XMULO(SDNode * N,SDValue & Lo,SDValue & Hi)2936 void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
2937 SDValue &Lo, SDValue &Hi) {
2938 EVT VT = N->getValueType(0);
2939 SDLoc dl(N);
2940
2941 if (N->getOpcode() == ISD::UMULO) {
2942 // This section expands the operation into the following sequence of
2943 // instructions. `iNh` here refers to a type which has half the bit width of
2944 // the type the original operation operated on.
2945 //
2946 // %0 = %LHS.HI != 0 && %RHS.HI != 0
2947 // %1 = { iNh, i1 } @umul.with.overflow.iNh(iNh %LHS.HI, iNh %RHS.LO)
2948 // %2 = { iNh, i1 } @umul.with.overflow.iNh(iNh %RHS.HI, iNh %LHS.LO)
2949 // %3 = mul nuw iN (%LHS.LOW as iN), (%RHS.LOW as iN)
2950 // %4 = add iN (%1.0 as iN) << Nh, (%2.0 as iN) << Nh
2951 // %5 = { iN, i1 } @uadd.with.overflow.iN( %4, %3 )
2952 //
2953 // %res = { %5.0, %0 || %1.1 || %2.1 || %5.1 }
2954 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
2955 SDValue LHSHigh, LHSLow, RHSHigh, RHSLow;
2956 SplitInteger(LHS, LHSLow, LHSHigh);
2957 SplitInteger(RHS, RHSLow, RHSHigh);
2958 EVT HalfVT = LHSLow.getValueType()
2959 , BitVT = N->getValueType(1);
2960 SDVTList VTHalfMulO = DAG.getVTList(HalfVT, BitVT);
2961 SDVTList VTFullAddO = DAG.getVTList(VT, BitVT);
2962
2963 SDValue HalfZero = DAG.getConstant(0, dl, HalfVT);
2964 SDValue Overflow = DAG.getNode(ISD::AND, dl, BitVT,
2965 DAG.getSetCC(dl, BitVT, LHSHigh, HalfZero, ISD::SETNE),
2966 DAG.getSetCC(dl, BitVT, RHSHigh, HalfZero, ISD::SETNE));
2967
2968 SDValue One = DAG.getNode(ISD::UMULO, dl, VTHalfMulO, LHSHigh, RHSLow);
2969 Overflow = DAG.getNode(ISD::OR, dl, BitVT, Overflow, One.getValue(1));
2970 SDValue OneInHigh = DAG.getNode(ISD::BUILD_PAIR, dl, VT, HalfZero,
2971 One.getValue(0));
2972
2973 SDValue Two = DAG.getNode(ISD::UMULO, dl, VTHalfMulO, RHSHigh, LHSLow);
2974 Overflow = DAG.getNode(ISD::OR, dl, BitVT, Overflow, Two.getValue(1));
2975 SDValue TwoInHigh = DAG.getNode(ISD::BUILD_PAIR, dl, VT, HalfZero,
2976 Two.getValue(0));
2977
2978 // Cannot use `UMUL_LOHI` directly, because some 32-bit targets (ARM) do not
2979 // know how to expand `i64,i64 = umul_lohi a, b` and abort (why isn’t this
2980 // operation recursively legalized?).
2981 //
2982 // Many backends understand this pattern and will convert into LOHI
2983 // themselves, if applicable.
2984 SDValue Three = DAG.getNode(ISD::MUL, dl, VT,
2985 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, LHSLow),
2986 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, RHSLow));
2987 SDValue Four = DAG.getNode(ISD::ADD, dl, VT, OneInHigh, TwoInHigh);
2988 SDValue Five = DAG.getNode(ISD::UADDO, dl, VTFullAddO, Three, Four);
2989 Overflow = DAG.getNode(ISD::OR, dl, BitVT, Overflow, Five.getValue(1));
2990 SplitInteger(Five, Lo, Hi);
2991 ReplaceValueWith(SDValue(N, 1), Overflow);
2992 return;
2993 }
2994
2995 Type *RetTy = VT.getTypeForEVT(*DAG.getContext());
2996 EVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
2997 Type *PtrTy = PtrVT.getTypeForEVT(*DAG.getContext());
2998
2999 // Replace this with a libcall that will check overflow.
3000 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3001 if (VT == MVT::i32)
3002 LC = RTLIB::MULO_I32;
3003 else if (VT == MVT::i64)
3004 LC = RTLIB::MULO_I64;
3005 else if (VT == MVT::i128)
3006 LC = RTLIB::MULO_I128;
3007 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XMULO!");
3008
3009 SDValue Temp = DAG.CreateStackTemporary(PtrVT);
3010 // Temporary for the overflow value, default it to zero.
3011 SDValue Chain =
3012 DAG.getStore(DAG.getEntryNode(), dl, DAG.getConstant(0, dl, PtrVT), Temp,
3013 MachinePointerInfo());
3014
3015 TargetLowering::ArgListTy Args;
3016 TargetLowering::ArgListEntry Entry;
3017 for (const SDValue &Op : N->op_values()) {
3018 EVT ArgVT = Op.getValueType();
3019 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
3020 Entry.Node = Op;
3021 Entry.Ty = ArgTy;
3022 Entry.IsSExt = true;
3023 Entry.IsZExt = false;
3024 Args.push_back(Entry);
3025 }
3026
3027 // Also pass the address of the overflow check.
3028 Entry.Node = Temp;
3029 Entry.Ty = PtrTy->getPointerTo();
3030 Entry.IsSExt = true;
3031 Entry.IsZExt = false;
3032 Args.push_back(Entry);
3033
3034 SDValue Func = DAG.getExternalSymbol(TLI.getLibcallName(LC), PtrVT);
3035
3036 TargetLowering::CallLoweringInfo CLI(DAG);
3037 CLI.setDebugLoc(dl)
3038 .setChain(Chain)
3039 .setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Func, std::move(Args))
3040 .setSExtResult();
3041
3042 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
3043
3044 SplitInteger(CallInfo.first, Lo, Hi);
3045 SDValue Temp2 =
3046 DAG.getLoad(PtrVT, dl, CallInfo.second, Temp, MachinePointerInfo());
3047 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Temp2,
3048 DAG.getConstant(0, dl, PtrVT),
3049 ISD::SETNE);
3050 // Use the overflow from the libcall everywhere.
3051 ReplaceValueWith(SDValue(N, 1), Ofl);
3052 }
3053
ExpandIntRes_UDIV(SDNode * N,SDValue & Lo,SDValue & Hi)3054 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
3055 SDValue &Lo, SDValue &Hi) {
3056 EVT VT = N->getValueType(0);
3057 SDLoc dl(N);
3058 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
3059
3060 if (TLI.getOperationAction(ISD::UDIVREM, VT) == TargetLowering::Custom) {
3061 SDValue Res = DAG.getNode(ISD::UDIVREM, dl, DAG.getVTList(VT, VT), Ops);
3062 SplitInteger(Res.getValue(0), Lo, Hi);
3063 return;
3064 }
3065
3066 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3067 if (VT == MVT::i16)
3068 LC = RTLIB::UDIV_I16;
3069 else if (VT == MVT::i32)
3070 LC = RTLIB::UDIV_I32;
3071 else if (VT == MVT::i64)
3072 LC = RTLIB::UDIV_I64;
3073 else if (VT == MVT::i128)
3074 LC = RTLIB::UDIV_I128;
3075 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
3076
3077 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, false, dl).first, Lo, Hi);
3078 }
3079
ExpandIntRes_UREM(SDNode * N,SDValue & Lo,SDValue & Hi)3080 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
3081 SDValue &Lo, SDValue &Hi) {
3082 EVT VT = N->getValueType(0);
3083 SDLoc dl(N);
3084 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
3085
3086 if (TLI.getOperationAction(ISD::UDIVREM, VT) == TargetLowering::Custom) {
3087 SDValue Res = DAG.getNode(ISD::UDIVREM, dl, DAG.getVTList(VT, VT), Ops);
3088 SplitInteger(Res.getValue(1), Lo, Hi);
3089 return;
3090 }
3091
3092 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3093 if (VT == MVT::i16)
3094 LC = RTLIB::UREM_I16;
3095 else if (VT == MVT::i32)
3096 LC = RTLIB::UREM_I32;
3097 else if (VT == MVT::i64)
3098 LC = RTLIB::UREM_I64;
3099 else if (VT == MVT::i128)
3100 LC = RTLIB::UREM_I128;
3101 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
3102
3103 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, false, dl).first, Lo, Hi);
3104 }
3105
ExpandIntRes_ZERO_EXTEND(SDNode * N,SDValue & Lo,SDValue & Hi)3106 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
3107 SDValue &Lo, SDValue &Hi) {
3108 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3109 SDLoc dl(N);
3110 SDValue Op = N->getOperand(0);
3111 if (Op.getValueType().bitsLE(NVT)) {
3112 // The low part is zero extension of the input (degenerates to a copy).
3113 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
3114 Hi = DAG.getConstant(0, dl, NVT); // The high part is just a zero.
3115 } else {
3116 // For example, extension of an i48 to an i64. The operand type necessarily
3117 // promotes to the result type, so will end up being expanded too.
3118 assert(getTypeAction(Op.getValueType()) ==
3119 TargetLowering::TypePromoteInteger &&
3120 "Only know how to promote this result!");
3121 SDValue Res = GetPromotedInteger(Op);
3122 assert(Res.getValueType() == N->getValueType(0) &&
3123 "Operand over promoted?");
3124 // Split the promoted operand. This will simplify when it is expanded.
3125 SplitInteger(Res, Lo, Hi);
3126 unsigned ExcessBits = Op.getValueSizeInBits() - NVT.getSizeInBits();
3127 Hi = DAG.getZeroExtendInReg(Hi, dl,
3128 EVT::getIntegerVT(*DAG.getContext(),
3129 ExcessBits));
3130 }
3131 }
3132
ExpandIntRes_ATOMIC_LOAD(SDNode * N,SDValue & Lo,SDValue & Hi)3133 void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(SDNode *N,
3134 SDValue &Lo, SDValue &Hi) {
3135 SDLoc dl(N);
3136 EVT VT = cast<AtomicSDNode>(N)->getMemoryVT();
3137 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
3138 SDValue Zero = DAG.getConstant(0, dl, VT);
3139 SDValue Swap = DAG.getAtomicCmpSwap(
3140 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl,
3141 cast<AtomicSDNode>(N)->getMemoryVT(), VTs, N->getOperand(0),
3142 N->getOperand(1), Zero, Zero, cast<AtomicSDNode>(N)->getMemOperand());
3143
3144 ReplaceValueWith(SDValue(N, 0), Swap.getValue(0));
3145 ReplaceValueWith(SDValue(N, 1), Swap.getValue(2));
3146 }
3147
3148 //===----------------------------------------------------------------------===//
3149 // Integer Operand Expansion
3150 //===----------------------------------------------------------------------===//
3151
3152 /// ExpandIntegerOperand - This method is called when the specified operand of
3153 /// the specified node is found to need expansion. At this point, all of the
3154 /// result types of the node are known to be legal, but other operands of the
3155 /// node may need promotion or expansion as well as the specified one.
ExpandIntegerOperand(SDNode * N,unsigned OpNo)3156 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
3157 LLVM_DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG);
3158 dbgs() << "\n");
3159 SDValue Res = SDValue();
3160
3161 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
3162 return false;
3163
3164 switch (N->getOpcode()) {
3165 default:
3166 #ifndef NDEBUG
3167 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
3168 N->dump(&DAG); dbgs() << "\n";
3169 #endif
3170 llvm_unreachable("Do not know how to expand this operator's operand!");
3171
3172 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
3173 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
3174 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
3175 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
3176 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
3177 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
3178 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
3179 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
3180 case ISD::SETCCCARRY: Res = ExpandIntOp_SETCCCARRY(N); break;
3181 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
3182 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
3183 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
3184 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
3185
3186 case ISD::SHL:
3187 case ISD::SRA:
3188 case ISD::SRL:
3189 case ISD::ROTL:
3190 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
3191 case ISD::RETURNADDR:
3192 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
3193
3194 case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
3195 }
3196
3197 // If the result is null, the sub-method took care of registering results etc.
3198 if (!Res.getNode()) return false;
3199
3200 // If the result is N, the sub-method updated N in place. Tell the legalizer
3201 // core about this.
3202 if (Res.getNode() == N)
3203 return true;
3204
3205 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
3206 "Invalid operand expansion");
3207
3208 ReplaceValueWith(SDValue(N, 0), Res);
3209 return false;
3210 }
3211
3212 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
3213 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
IntegerExpandSetCCOperands(SDValue & NewLHS,SDValue & NewRHS,ISD::CondCode & CCCode,const SDLoc & dl)3214 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
3215 SDValue &NewRHS,
3216 ISD::CondCode &CCCode,
3217 const SDLoc &dl) {
3218 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
3219 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
3220 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
3221
3222 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
3223 if (RHSLo == RHSHi) {
3224 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
3225 if (RHSCST->isAllOnesValue()) {
3226 // Equality comparison to -1.
3227 NewLHS = DAG.getNode(ISD::AND, dl,
3228 LHSLo.getValueType(), LHSLo, LHSHi);
3229 NewRHS = RHSLo;
3230 return;
3231 }
3232 }
3233 }
3234
3235 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
3236 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
3237 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
3238 NewRHS = DAG.getConstant(0, dl, NewLHS.getValueType());
3239 return;
3240 }
3241
3242 // If this is a comparison of the sign bit, just look at the top part.
3243 // X > -1, x < 0
3244 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
3245 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
3246 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
3247 NewLHS = LHSHi;
3248 NewRHS = RHSHi;
3249 return;
3250 }
3251
3252 // FIXME: This generated code sucks.
3253 ISD::CondCode LowCC;
3254 switch (CCCode) {
3255 default: llvm_unreachable("Unknown integer setcc!");
3256 case ISD::SETLT:
3257 case ISD::SETULT: LowCC = ISD::SETULT; break;
3258 case ISD::SETGT:
3259 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
3260 case ISD::SETLE:
3261 case ISD::SETULE: LowCC = ISD::SETULE; break;
3262 case ISD::SETGE:
3263 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
3264 }
3265
3266 // LoCmp = lo(op1) < lo(op2) // Always unsigned comparison
3267 // HiCmp = hi(op1) < hi(op2) // Signedness depends on operands
3268 // dest = hi(op1) == hi(op2) ? LoCmp : HiCmp;
3269
3270 // NOTE: on targets without efficient SELECT of bools, we can always use
3271 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
3272 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, AfterLegalizeTypes, true,
3273 nullptr);
3274 SDValue LoCmp, HiCmp;
3275 if (TLI.isTypeLegal(LHSLo.getValueType()) &&
3276 TLI.isTypeLegal(RHSLo.getValueType()))
3277 LoCmp = TLI.SimplifySetCC(getSetCCResultType(LHSLo.getValueType()), LHSLo,
3278 RHSLo, LowCC, false, DagCombineInfo, dl);
3279 if (!LoCmp.getNode())
3280 LoCmp = DAG.getSetCC(dl, getSetCCResultType(LHSLo.getValueType()), LHSLo,
3281 RHSLo, LowCC);
3282 if (TLI.isTypeLegal(LHSHi.getValueType()) &&
3283 TLI.isTypeLegal(RHSHi.getValueType()))
3284 HiCmp = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()), LHSHi,
3285 RHSHi, CCCode, false, DagCombineInfo, dl);
3286 if (!HiCmp.getNode())
3287 HiCmp =
3288 DAG.getNode(ISD::SETCC, dl, getSetCCResultType(LHSHi.getValueType()),
3289 LHSHi, RHSHi, DAG.getCondCode(CCCode));
3290
3291 ConstantSDNode *LoCmpC = dyn_cast<ConstantSDNode>(LoCmp.getNode());
3292 ConstantSDNode *HiCmpC = dyn_cast<ConstantSDNode>(HiCmp.getNode());
3293
3294 bool EqAllowed = (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
3295 CCCode == ISD::SETUGE || CCCode == ISD::SETULE);
3296
3297 if ((EqAllowed && (HiCmpC && HiCmpC->isNullValue())) ||
3298 (!EqAllowed && ((HiCmpC && (HiCmpC->getAPIntValue() == 1)) ||
3299 (LoCmpC && LoCmpC->isNullValue())))) {
3300 // For LE / GE, if high part is known false, ignore the low part.
3301 // For LT / GT: if low part is known false, return the high part.
3302 // if high part is known true, ignore the low part.
3303 NewLHS = HiCmp;
3304 NewRHS = SDValue();
3305 return;
3306 }
3307
3308 if (LHSHi == RHSHi) {
3309 // Comparing the low bits is enough.
3310 NewLHS = LoCmp;
3311 NewRHS = SDValue();
3312 return;
3313 }
3314
3315 // Lower with SETCCCARRY if the target supports it.
3316 EVT HiVT = LHSHi.getValueType();
3317 EVT ExpandVT = TLI.getTypeToExpandTo(*DAG.getContext(), HiVT);
3318 bool HasSETCCCARRY = TLI.isOperationLegalOrCustom(ISD::SETCCCARRY, ExpandVT);
3319
3320 // FIXME: Make all targets support this, then remove the other lowering.
3321 if (HasSETCCCARRY) {
3322 // SETCCCARRY can detect < and >= directly. For > and <=, flip
3323 // operands and condition code.
3324 bool FlipOperands = false;
3325 switch (CCCode) {
3326 case ISD::SETGT: CCCode = ISD::SETLT; FlipOperands = true; break;
3327 case ISD::SETUGT: CCCode = ISD::SETULT; FlipOperands = true; break;
3328 case ISD::SETLE: CCCode = ISD::SETGE; FlipOperands = true; break;
3329 case ISD::SETULE: CCCode = ISD::SETUGE; FlipOperands = true; break;
3330 default: break;
3331 }
3332 if (FlipOperands) {
3333 std::swap(LHSLo, RHSLo);
3334 std::swap(LHSHi, RHSHi);
3335 }
3336 // Perform a wide subtraction, feeding the carry from the low part into
3337 // SETCCCARRY. The SETCCCARRY operation is essentially looking at the high
3338 // part of the result of LHS - RHS. It is negative iff LHS < RHS. It is
3339 // zero or positive iff LHS >= RHS.
3340 EVT LoVT = LHSLo.getValueType();
3341 SDVTList VTList = DAG.getVTList(LoVT, getSetCCResultType(LoVT));
3342 SDValue LowCmp = DAG.getNode(ISD::USUBO, dl, VTList, LHSLo, RHSLo);
3343 SDValue Res = DAG.getNode(ISD::SETCCCARRY, dl, getSetCCResultType(HiVT),
3344 LHSHi, RHSHi, LowCmp.getValue(1),
3345 DAG.getCondCode(CCCode));
3346 NewLHS = Res;
3347 NewRHS = SDValue();
3348 return;
3349 }
3350
3351 NewLHS = TLI.SimplifySetCC(getSetCCResultType(HiVT), LHSHi, RHSHi, ISD::SETEQ,
3352 false, DagCombineInfo, dl);
3353 if (!NewLHS.getNode())
3354 NewLHS =
3355 DAG.getSetCC(dl, getSetCCResultType(HiVT), LHSHi, RHSHi, ISD::SETEQ);
3356 NewLHS = DAG.getSelect(dl, LoCmp.getValueType(), NewLHS, LoCmp, HiCmp);
3357 NewRHS = SDValue();
3358 }
3359
ExpandIntOp_BR_CC(SDNode * N)3360 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
3361 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
3362 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
3363 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
3364
3365 // If ExpandSetCCOperands returned a scalar, we need to compare the result
3366 // against zero to select between true and false values.
3367 if (!NewRHS.getNode()) {
3368 NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
3369 CCCode = ISD::SETNE;
3370 }
3371
3372 // Update N to have the operands specified.
3373 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
3374 DAG.getCondCode(CCCode), NewLHS, NewRHS,
3375 N->getOperand(4)), 0);
3376 }
3377
ExpandIntOp_SELECT_CC(SDNode * N)3378 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
3379 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
3380 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
3381 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
3382
3383 // If ExpandSetCCOperands returned a scalar, we need to compare the result
3384 // against zero to select between true and false values.
3385 if (!NewRHS.getNode()) {
3386 NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
3387 CCCode = ISD::SETNE;
3388 }
3389
3390 // Update N to have the operands specified.
3391 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
3392 N->getOperand(2), N->getOperand(3),
3393 DAG.getCondCode(CCCode)), 0);
3394 }
3395
ExpandIntOp_SETCC(SDNode * N)3396 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
3397 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
3398 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
3399 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
3400
3401 // If ExpandSetCCOperands returned a scalar, use it.
3402 if (!NewRHS.getNode()) {
3403 assert(NewLHS.getValueType() == N->getValueType(0) &&
3404 "Unexpected setcc expansion!");
3405 return NewLHS;
3406 }
3407
3408 // Otherwise, update N to have the operands specified.
3409 return SDValue(
3410 DAG.UpdateNodeOperands(N, NewLHS, NewRHS, DAG.getCondCode(CCCode)), 0);
3411 }
3412
ExpandIntOp_SETCCCARRY(SDNode * N)3413 SDValue DAGTypeLegalizer::ExpandIntOp_SETCCCARRY(SDNode *N) {
3414 SDValue LHS = N->getOperand(0);
3415 SDValue RHS = N->getOperand(1);
3416 SDValue Carry = N->getOperand(2);
3417 SDValue Cond = N->getOperand(3);
3418 SDLoc dl = SDLoc(N);
3419
3420 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
3421 GetExpandedInteger(LHS, LHSLo, LHSHi);
3422 GetExpandedInteger(RHS, RHSLo, RHSHi);
3423
3424 // Expand to a SUBE for the low part and a smaller SETCCCARRY for the high.
3425 SDVTList VTList = DAG.getVTList(LHSLo.getValueType(), Carry.getValueType());
3426 SDValue LowCmp = DAG.getNode(ISD::SUBCARRY, dl, VTList, LHSLo, RHSLo, Carry);
3427 return DAG.getNode(ISD::SETCCCARRY, dl, N->getValueType(0), LHSHi, RHSHi,
3428 LowCmp.getValue(1), Cond);
3429 }
3430
ExpandIntOp_Shift(SDNode * N)3431 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
3432 // The value being shifted is legal, but the shift amount is too big.
3433 // It follows that either the result of the shift is undefined, or the
3434 // upper half of the shift amount is zero. Just use the lower half.
3435 SDValue Lo, Hi;
3436 GetExpandedInteger(N->getOperand(1), Lo, Hi);
3437 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0);
3438 }
3439
ExpandIntOp_RETURNADDR(SDNode * N)3440 SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
3441 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
3442 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
3443 // constant to valid type.
3444 SDValue Lo, Hi;
3445 GetExpandedInteger(N->getOperand(0), Lo, Hi);
3446 return SDValue(DAG.UpdateNodeOperands(N, Lo), 0);
3447 }
3448
ExpandIntOp_SINT_TO_FP(SDNode * N)3449 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
3450 SDValue Op = N->getOperand(0);
3451 EVT DstVT = N->getValueType(0);
3452 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
3453 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
3454 "Don't know how to expand this SINT_TO_FP!");
3455 return TLI.makeLibCall(DAG, LC, DstVT, Op, true, SDLoc(N)).first;
3456 }
3457
ExpandIntOp_STORE(StoreSDNode * N,unsigned OpNo)3458 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
3459 if (ISD::isNormalStore(N))
3460 return ExpandOp_NormalStore(N, OpNo);
3461
3462 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
3463 assert(OpNo == 1 && "Can only expand the stored value so far");
3464
3465 EVT VT = N->getOperand(1).getValueType();
3466 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
3467 SDValue Ch = N->getChain();
3468 SDValue Ptr = N->getBasePtr();
3469 unsigned Alignment = N->getAlignment();
3470 MachineMemOperand::Flags MMOFlags = N->getMemOperand()->getFlags();
3471 AAMDNodes AAInfo = N->getAAInfo();
3472 SDLoc dl(N);
3473 SDValue Lo, Hi;
3474
3475 assert(NVT.isByteSized() && "Expanded type not byte sized!");
3476
3477 if (N->getMemoryVT().bitsLE(NVT)) {
3478 GetExpandedInteger(N->getValue(), Lo, Hi);
3479 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
3480 N->getMemoryVT(), Alignment, MMOFlags, AAInfo);
3481 }
3482
3483 if (DAG.getDataLayout().isLittleEndian()) {
3484 // Little-endian - low bits are at low addresses.
3485 GetExpandedInteger(N->getValue(), Lo, Hi);
3486
3487 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(), Alignment, MMOFlags,
3488 AAInfo);
3489
3490 unsigned ExcessBits =
3491 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
3492 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
3493
3494 // Increment the pointer to the other half.
3495 unsigned IncrementSize = NVT.getSizeInBits()/8;
3496 Ptr = DAG.getObjectPtrOffset(dl, Ptr, IncrementSize);
3497 Hi = DAG.getTruncStore(
3498 Ch, dl, Hi, Ptr, N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
3499 MinAlign(Alignment, IncrementSize), MMOFlags, AAInfo);
3500 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
3501 }
3502
3503 // Big-endian - high bits are at low addresses. Favor aligned stores at
3504 // the cost of some bit-fiddling.
3505 GetExpandedInteger(N->getValue(), Lo, Hi);
3506
3507 EVT ExtVT = N->getMemoryVT();
3508 unsigned EBytes = ExtVT.getStoreSize();
3509 unsigned IncrementSize = NVT.getSizeInBits()/8;
3510 unsigned ExcessBits = (EBytes - IncrementSize)*8;
3511 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(),
3512 ExtVT.getSizeInBits() - ExcessBits);
3513
3514 if (ExcessBits < NVT.getSizeInBits()) {
3515 // Transfer high bits from the top of Lo to the bottom of Hi.
3516 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
3517 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, dl,
3518 TLI.getPointerTy(DAG.getDataLayout())));
3519 Hi = DAG.getNode(
3520 ISD::OR, dl, NVT, Hi,
3521 DAG.getNode(ISD::SRL, dl, NVT, Lo,
3522 DAG.getConstant(ExcessBits, dl,
3523 TLI.getPointerTy(DAG.getDataLayout()))));
3524 }
3525
3526 // Store both the high bits and maybe some of the low bits.
3527 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getPointerInfo(), HiVT, Alignment,
3528 MMOFlags, AAInfo);
3529
3530 // Increment the pointer to the other half.
3531 Ptr = DAG.getObjectPtrOffset(dl, Ptr, IncrementSize);
3532 // Store the lowest ExcessBits bits in the second half.
3533 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr,
3534 N->getPointerInfo().getWithOffset(IncrementSize),
3535 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
3536 MinAlign(Alignment, IncrementSize), MMOFlags, AAInfo);
3537 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
3538 }
3539
ExpandIntOp_TRUNCATE(SDNode * N)3540 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
3541 SDValue InL, InH;
3542 GetExpandedInteger(N->getOperand(0), InL, InH);
3543 // Just truncate the low part of the source.
3544 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), InL);
3545 }
3546
ExpandIntOp_UINT_TO_FP(SDNode * N)3547 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
3548 SDValue Op = N->getOperand(0);
3549 EVT SrcVT = Op.getValueType();
3550 EVT DstVT = N->getValueType(0);
3551 SDLoc dl(N);
3552
3553 // The following optimization is valid only if every value in SrcVT (when
3554 // treated as signed) is representable in DstVT. Check that the mantissa
3555 // size of DstVT is >= than the number of bits in SrcVT -1.
3556 const fltSemantics &sem = DAG.EVTToAPFloatSemantics(DstVT);
3557 if (APFloat::semanticsPrecision(sem) >= SrcVT.getSizeInBits()-1 &&
3558 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
3559 // Do a signed conversion then adjust the result.
3560 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
3561 SignedConv = TLI.LowerOperation(SignedConv, DAG);
3562
3563 // The result of the signed conversion needs adjusting if the 'sign bit' of
3564 // the incoming integer was set. To handle this, we dynamically test to see
3565 // if it is set, and, if so, add a fudge factor.
3566
3567 const uint64_t F32TwoE32 = 0x4F800000ULL;
3568 const uint64_t F32TwoE64 = 0x5F800000ULL;
3569 const uint64_t F32TwoE128 = 0x7F800000ULL;
3570
3571 APInt FF(32, 0);
3572 if (SrcVT == MVT::i32)
3573 FF = APInt(32, F32TwoE32);
3574 else if (SrcVT == MVT::i64)
3575 FF = APInt(32, F32TwoE64);
3576 else if (SrcVT == MVT::i128)
3577 FF = APInt(32, F32TwoE128);
3578 else
3579 llvm_unreachable("Unsupported UINT_TO_FP!");
3580
3581 // Check whether the sign bit is set.
3582 SDValue Lo, Hi;
3583 GetExpandedInteger(Op, Lo, Hi);
3584 SDValue SignSet = DAG.getSetCC(dl,
3585 getSetCCResultType(Hi.getValueType()),
3586 Hi,
3587 DAG.getConstant(0, dl, Hi.getValueType()),
3588 ISD::SETLT);
3589
3590 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
3591 SDValue FudgePtr =
3592 DAG.getConstantPool(ConstantInt::get(*DAG.getContext(), FF.zext(64)),
3593 TLI.getPointerTy(DAG.getDataLayout()));
3594
3595 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
3596 SDValue Zero = DAG.getIntPtrConstant(0, dl);
3597 SDValue Four = DAG.getIntPtrConstant(4, dl);
3598 if (DAG.getDataLayout().isBigEndian())
3599 std::swap(Zero, Four);
3600 SDValue Offset = DAG.getSelect(dl, Zero.getValueType(), SignSet,
3601 Zero, Four);
3602 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
3603 FudgePtr = DAG.getNode(ISD::ADD, dl, FudgePtr.getValueType(),
3604 FudgePtr, Offset);
3605 Alignment = std::min(Alignment, 4u);
3606
3607 // Load the value out, extending it from f32 to the destination float type.
3608 // FIXME: Avoid the extend by constructing the right constant pool?
3609 SDValue Fudge = DAG.getExtLoad(
3610 ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(), FudgePtr,
3611 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
3612 Alignment);
3613 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
3614 }
3615
3616 // Otherwise, use a libcall.
3617 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
3618 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
3619 "Don't know how to expand this UINT_TO_FP!");
3620 return TLI.makeLibCall(DAG, LC, DstVT, Op, true, dl).first;
3621 }
3622
ExpandIntOp_ATOMIC_STORE(SDNode * N)3623 SDValue DAGTypeLegalizer::ExpandIntOp_ATOMIC_STORE(SDNode *N) {
3624 SDLoc dl(N);
3625 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
3626 cast<AtomicSDNode>(N)->getMemoryVT(),
3627 N->getOperand(0),
3628 N->getOperand(1), N->getOperand(2),
3629 cast<AtomicSDNode>(N)->getMemOperand());
3630 return Swap.getValue(1);
3631 }
3632
3633
PromoteIntRes_EXTRACT_SUBVECTOR(SDNode * N)3634 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
3635 SDValue InOp0 = N->getOperand(0);
3636 EVT InVT = InOp0.getValueType();
3637
3638 EVT OutVT = N->getValueType(0);
3639 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3640 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3641 unsigned OutNumElems = OutVT.getVectorNumElements();
3642 EVT NOutVTElem = NOutVT.getVectorElementType();
3643
3644 SDLoc dl(N);
3645 SDValue BaseIdx = N->getOperand(1);
3646
3647 SmallVector<SDValue, 8> Ops;
3648 Ops.reserve(OutNumElems);
3649 for (unsigned i = 0; i != OutNumElems; ++i) {
3650
3651 // Extract the element from the original vector.
3652 SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(),
3653 BaseIdx, DAG.getConstant(i, dl, BaseIdx.getValueType()));
3654 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3655 InVT.getVectorElementType(), N->getOperand(0), Index);
3656
3657 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, Ext);
3658 // Insert the converted element to the new vector.
3659 Ops.push_back(Op);
3660 }
3661
3662 return DAG.getBuildVector(NOutVT, dl, Ops);
3663 }
3664
3665
PromoteIntRes_VECTOR_SHUFFLE(SDNode * N)3666 SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) {
3667 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N);
3668 EVT VT = N->getValueType(0);
3669 SDLoc dl(N);
3670
3671 ArrayRef<int> NewMask = SV->getMask().slice(0, VT.getVectorNumElements());
3672
3673 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3674 SDValue V1 = GetPromotedInteger(N->getOperand(1));
3675 EVT OutVT = V0.getValueType();
3676
3677 return DAG.getVectorShuffle(OutVT, dl, V0, V1, NewMask);
3678 }
3679
3680
PromoteIntRes_BUILD_VECTOR(SDNode * N)3681 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) {
3682 EVT OutVT = N->getValueType(0);
3683 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3684 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3685 unsigned NumElems = N->getNumOperands();
3686 EVT NOutVTElem = NOutVT.getVectorElementType();
3687
3688 SDLoc dl(N);
3689
3690 SmallVector<SDValue, 8> Ops;
3691 Ops.reserve(NumElems);
3692 for (unsigned i = 0; i != NumElems; ++i) {
3693 SDValue Op;
3694 // BUILD_VECTOR integer operand types are allowed to be larger than the
3695 // result's element type. This may still be true after the promotion. For
3696 // example, we might be promoting (<v?i1> = BV <i32>, <i32>, ...) to
3697 // (v?i16 = BV <i32>, <i32>, ...), and we can't any_extend <i32> to <i16>.
3698 if (N->getOperand(i).getValueType().bitsLT(NOutVTElem))
3699 Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(i));
3700 else
3701 Op = N->getOperand(i);
3702 Ops.push_back(Op);
3703 }
3704
3705 return DAG.getBuildVector(NOutVT, dl, Ops);
3706 }
3707
PromoteIntRes_SCALAR_TO_VECTOR(SDNode * N)3708 SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N) {
3709
3710 SDLoc dl(N);
3711
3712 assert(!N->getOperand(0).getValueType().isVector() &&
3713 "Input must be a scalar");
3714
3715 EVT OutVT = N->getValueType(0);
3716 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3717 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3718 EVT NOutVTElem = NOutVT.getVectorElementType();
3719
3720 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(0));
3721
3722 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op);
3723 }
3724
PromoteIntRes_CONCAT_VECTORS(SDNode * N)3725 SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(SDNode *N) {
3726 SDLoc dl(N);
3727
3728 EVT OutVT = N->getValueType(0);
3729 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3730 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3731
3732 EVT OutElemTy = NOutVT.getVectorElementType();
3733
3734 unsigned NumElem = N->getOperand(0).getValueType().getVectorNumElements();
3735 unsigned NumOutElem = NOutVT.getVectorNumElements();
3736 unsigned NumOperands = N->getNumOperands();
3737 assert(NumElem * NumOperands == NumOutElem &&
3738 "Unexpected number of elements");
3739
3740 // Take the elements from the first vector.
3741 SmallVector<SDValue, 8> Ops(NumOutElem);
3742 for (unsigned i = 0; i < NumOperands; ++i) {
3743 SDValue Op = N->getOperand(i);
3744 if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger)
3745 Op = GetPromotedInteger(Op);
3746 EVT SclrTy = Op.getValueType().getVectorElementType();
3747 assert(NumElem == Op.getValueType().getVectorNumElements() &&
3748 "Unexpected number of elements");
3749
3750 for (unsigned j = 0; j < NumElem; ++j) {
3751 SDValue Ext = DAG.getNode(
3752 ISD::EXTRACT_VECTOR_ELT, dl, SclrTy, Op,
3753 DAG.getConstant(j, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3754 Ops[i * NumElem + j] = DAG.getAnyExtOrTrunc(Ext, dl, OutElemTy);
3755 }
3756 }
3757
3758 return DAG.getBuildVector(NOutVT, dl, Ops);
3759 }
3760
PromoteIntRes_EXTEND_VECTOR_INREG(SDNode * N)3761 SDValue DAGTypeLegalizer::PromoteIntRes_EXTEND_VECTOR_INREG(SDNode *N) {
3762 EVT VT = N->getValueType(0);
3763 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
3764 assert(NVT.isVector() && "This type must be promoted to a vector type");
3765
3766 SDLoc dl(N);
3767
3768 // For operands whose TypeAction is to promote, extend the promoted node
3769 // appropriately (ZERO_EXTEND or SIGN_EXTEND) from the original pre-promotion
3770 // type, and then construct a new *_EXTEND_VECTOR_INREG node to the promote-to
3771 // type..
3772 if (getTypeAction(N->getOperand(0).getValueType())
3773 == TargetLowering::TypePromoteInteger) {
3774 SDValue Promoted;
3775
3776 switch(N->getOpcode()) {
3777 case ISD::SIGN_EXTEND_VECTOR_INREG:
3778 Promoted = SExtPromotedInteger(N->getOperand(0));
3779 break;
3780 case ISD::ZERO_EXTEND_VECTOR_INREG:
3781 Promoted = ZExtPromotedInteger(N->getOperand(0));
3782 break;
3783 case ISD::ANY_EXTEND_VECTOR_INREG:
3784 Promoted = GetPromotedInteger(N->getOperand(0));
3785 break;
3786 default:
3787 llvm_unreachable("Node has unexpected Opcode");
3788 }
3789 return DAG.getNode(N->getOpcode(), dl, NVT, Promoted);
3790 }
3791
3792 // Directly extend to the appropriate transform-to type.
3793 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
3794 }
3795
PromoteIntRes_INSERT_VECTOR_ELT(SDNode * N)3796 SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
3797 EVT OutVT = N->getValueType(0);
3798 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3799 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3800
3801 EVT NOutVTElem = NOutVT.getVectorElementType();
3802
3803 SDLoc dl(N);
3804 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3805
3806 SDValue ConvElem = DAG.getNode(ISD::ANY_EXTEND, dl,
3807 NOutVTElem, N->getOperand(1));
3808 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT,
3809 V0, ConvElem, N->getOperand(2));
3810 }
3811
PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode * N)3812 SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) {
3813 SDLoc dl(N);
3814 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3815 SDValue V1 = DAG.getZExtOrTrunc(N->getOperand(1), dl,
3816 TLI.getVectorIdxTy(DAG.getDataLayout()));
3817 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3818 V0->getValueType(0).getScalarType(), V0, V1);
3819
3820 // EXTRACT_VECTOR_ELT can return types which are wider than the incoming
3821 // element types. If this is the case then we need to expand the outgoing
3822 // value and not truncate it.
3823 return DAG.getAnyExtOrTrunc(Ext, dl, N->getValueType(0));
3824 }
3825
PromoteIntOp_EXTRACT_SUBVECTOR(SDNode * N)3826 SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_SUBVECTOR(SDNode *N) {
3827 SDLoc dl(N);
3828 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3829 MVT InVT = V0.getValueType().getSimpleVT();
3830 MVT OutVT = MVT::getVectorVT(InVT.getVectorElementType(),
3831 N->getValueType(0).getVectorNumElements());
3832 SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, V0, N->getOperand(1));
3833 return DAG.getNode(ISD::TRUNCATE, dl, N->getValueType(0), Ext);
3834 }
3835
PromoteIntOp_CONCAT_VECTORS(SDNode * N)3836 SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
3837 SDLoc dl(N);
3838 unsigned NumElems = N->getNumOperands();
3839
3840 EVT RetSclrTy = N->getValueType(0).getVectorElementType();
3841
3842 SmallVector<SDValue, 8> NewOps;
3843 NewOps.reserve(NumElems);
3844
3845 // For each incoming vector
3846 for (unsigned VecIdx = 0; VecIdx != NumElems; ++VecIdx) {
3847 SDValue Incoming = GetPromotedInteger(N->getOperand(VecIdx));
3848 EVT SclrTy = Incoming->getValueType(0).getVectorElementType();
3849 unsigned NumElem = Incoming->getValueType(0).getVectorNumElements();
3850
3851 for (unsigned i=0; i<NumElem; ++i) {
3852 // Extract element from incoming vector
3853 SDValue Ex = DAG.getNode(
3854 ISD::EXTRACT_VECTOR_ELT, dl, SclrTy, Incoming,
3855 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3856 SDValue Tr = DAG.getNode(ISD::TRUNCATE, dl, RetSclrTy, Ex);
3857 NewOps.push_back(Tr);
3858 }
3859 }
3860
3861 return DAG.getBuildVector(N->getValueType(0), dl, NewOps);
3862 }
3863