1 //===- AArch64TargetTransformInfo.h - AArch64 specific TTI ------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file a TargetTransformInfo::Concept conforming object specific to the
11 /// AArch64 target machine. It uses the target's detailed information to
12 /// provide more precise answers to certain TTI queries, while letting the
13 /// target independent and default TTI implementations handle the rest.
14 ///
15 //===----------------------------------------------------------------------===//
16 
17 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H
18 #define LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H
19 
20 #include "AArch64.h"
21 #include "AArch64Subtarget.h"
22 #include "AArch64TargetMachine.h"
23 #include "llvm/ADT/ArrayRef.h"
24 #include "llvm/Analysis/TargetTransformInfo.h"
25 #include "llvm/CodeGen/BasicTTIImpl.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/Intrinsics.h"
28 #include <cstdint>
29 
30 namespace llvm {
31 
32 class APInt;
33 class Instruction;
34 class IntrinsicInst;
35 class Loop;
36 class SCEV;
37 class ScalarEvolution;
38 class Type;
39 class Value;
40 class VectorType;
41 
42 class AArch64TTIImpl : public BasicTTIImplBase<AArch64TTIImpl> {
43   using BaseT = BasicTTIImplBase<AArch64TTIImpl>;
44   using TTI = TargetTransformInfo;
45 
46   friend BaseT;
47 
48   const AArch64Subtarget *ST;
49   const AArch64TargetLowering *TLI;
50 
getST()51   const AArch64Subtarget *getST() const { return ST; }
getTLI()52   const AArch64TargetLowering *getTLI() const { return TLI; }
53 
54   enum MemIntrinsicType {
55     VECTOR_LDST_TWO_ELEMENTS,
56     VECTOR_LDST_THREE_ELEMENTS,
57     VECTOR_LDST_FOUR_ELEMENTS
58   };
59 
60   bool isWideningInstruction(Type *Ty, unsigned Opcode,
61                              ArrayRef<const Value *> Args);
62 
63 public:
AArch64TTIImpl(const AArch64TargetMachine * TM,const Function & F)64   explicit AArch64TTIImpl(const AArch64TargetMachine *TM, const Function &F)
65       : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
66         TLI(ST->getTargetLowering()) {}
67 
68   bool areInlineCompatible(const Function *Caller,
69                            const Function *Callee) const;
70 
71   /// \name Scalar TTI Implementations
72   /// @{
73 
74   using BaseT::getIntImmCost;
75   int getIntImmCost(int64_t Val);
76   int getIntImmCost(const APInt &Imm, Type *Ty);
77   int getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty);
78   int getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
79                     Type *Ty);
80   TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth);
81 
82   /// @}
83 
84   /// \name Vector TTI Implementations
85   /// @{
86 
enableInterleavedAccessVectorization()87   bool enableInterleavedAccessVectorization() { return true; }
88 
getNumberOfRegisters(bool Vector)89   unsigned getNumberOfRegisters(bool Vector) {
90     if (Vector) {
91       if (ST->hasNEON())
92         return 32;
93       return 0;
94     }
95     return 31;
96   }
97 
getRegisterBitWidth(bool Vector)98   unsigned getRegisterBitWidth(bool Vector) const {
99     if (Vector) {
100       if (ST->hasNEON())
101         return 128;
102       return 0;
103     }
104     return 64;
105   }
106 
getMinVectorRegisterBitWidth()107   unsigned getMinVectorRegisterBitWidth() {
108     return ST->getMinVectorRegisterBitWidth();
109   }
110 
111   unsigned getMaxInterleaveFactor(unsigned VF);
112 
113   int getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
114                        const Instruction *I = nullptr);
115 
116   int getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy,
117                                unsigned Index);
118 
119   int getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index);
120 
121   int getArithmeticInstrCost(
122       unsigned Opcode, Type *Ty,
123       TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,
124       TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
125       TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
126       TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None,
127       ArrayRef<const Value *> Args = ArrayRef<const Value *>());
128 
129   int getAddressComputationCost(Type *Ty, ScalarEvolution *SE, const SCEV *Ptr);
130 
131   int getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
132                          const Instruction *I = nullptr);
133 
134   int getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
135                       unsigned AddressSpace, const Instruction *I = nullptr);
136 
137   int getCostOfKeepingLiveOverCall(ArrayRef<Type *> Tys);
138 
139   void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
140                                TTI::UnrollingPreferences &UP);
141 
142   Value *getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst,
143                                            Type *ExpectedType);
144 
145   bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info);
146 
147   int getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor,
148                                  ArrayRef<unsigned> Indices, unsigned Alignment,
149                                  unsigned AddressSpace,
150                                  bool UseMaskForCond = false,
151                                  bool UseMaskForGaps = false);
152 
153   bool
154   shouldConsiderAddressTypePromotion(const Instruction &I,
155                                      bool &AllowPromotionWithoutCommonHeader);
156 
157   unsigned getCacheLineSize();
158 
159   unsigned getPrefetchDistance();
160 
161   unsigned getMinPrefetchStride();
162 
163   unsigned getMaxPrefetchIterationsAhead();
164 
shouldExpandReduction(const IntrinsicInst * II)165   bool shouldExpandReduction(const IntrinsicInst *II) const {
166     return false;
167   }
168 
169   bool useReductionIntrinsic(unsigned Opcode, Type *Ty,
170                              TTI::ReductionFlags Flags) const;
171 
172   int getArithmeticReductionCost(unsigned Opcode, Type *Ty,
173                                  bool IsPairwiseForm);
174 
175   int getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, Type *SubTp);
176   /// @}
177 };
178 
179 } // end namespace llvm
180 
181 #endif // LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H
182