1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9
10 #include "MCTargetDesc/PPCMCExpr.h"
11 #include "MCTargetDesc/PPCMCTargetDesc.h"
12 #include "PPCTargetStreamer.h"
13 #include "llvm/ADT/STLExtras.h"
14 #include "llvm/ADT/StringSwitch.h"
15 #include "llvm/ADT/Twine.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCParser/MCAsmLexer.h"
21 #include "llvm/MC/MCParser/MCAsmParser.h"
22 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
23 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
DialogExtraControls(QWidget * parent)24 #include "llvm/MC/MCStreamer.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/MC/MCSymbolELF.h"
27 #include "llvm/Support/SourceMgr.h"
28 #include "llvm/Support/TargetRegistry.h"
29 #include "llvm/Support/raw_ostream.h"
30
31 using namespace llvm;
32
33 DEFINE_PPC_REGCLASSES;
34
35 // Evaluate an expression containing condition register
36 // or condition register field symbols. Returns positive
37 // value on success, or -1 on error.
38 static int64_t
39 EvaluateCRExpr(const MCExpr *E) {
40 switch (E->getKind()) {
41 case MCExpr::Target:
42 return -1;
43
44 case MCExpr::Constant: {
45 int64_t Res = cast<MCConstantExpr>(E)->getValue();
46 return Res < 0 ? -1 : Res;
47 }
48
49 case MCExpr::SymbolRef: {
50 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
51 StringRef Name = SRE->getSymbol().getName();
52
53 if (Name == "lt") return 0;
54 if (Name == "gt") return 1;
55 if (Name == "eq") return 2;
56 if (Name == "so") return 3;
57 if (Name == "un") return 3;
58
59 if (Name == "cr0") return 0;
60 if (Name == "cr1") return 1;
61 if (Name == "cr2") return 2;
62 if (Name == "cr3") return 3;
63 if (Name == "cr4") return 4;
64 if (Name == "cr5") return 5;
65 if (Name == "cr6") return 6;
~DialogExtraControls()66 if (Name == "cr7") return 7;
67
68 return -1;
69 }
70
addControl()71 case MCExpr::Unary:
72 return -1;
73
74 case MCExpr::Binary: {
75 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
76 int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
77 int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
removeControl()78 int64_t Res;
79
80 if (LHSVal < 0 || RHSVal < 0)
81 return -1;
82
83 switch (BE->getOpcode()) {
84 default: return -1;
controlUp()85 case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
86 case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
87 }
88
89 return Res < 0 ? -1 : Res;
90 }
91 }
92
93 llvm_unreachable("Invalid expression kind!");
94 }
controlDown()95
96 namespace {
97
98 struct PPCOperand;
99
100 class PPCAsmParser : public MCTargetAsmParser {
101 bool IsPPC64;
102 bool IsDarwin;
103
104 void Warning(SMLoc L, const Twine &Msg) { getParser().Warning(L, Msg); }
105
106 bool isPPC64() const { return IsPPC64; }
107 bool isDarwin() const { return IsDarwin; }
108
109 bool MatchRegisterName(unsigned &RegNo, int64_t &IntVal);
110
111 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
112
113 const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
114 PPCMCExpr::VariantKind &Variant);
115 const MCExpr *FixupVariantKind(const MCExpr *E);
116 bool ParseExpression(const MCExpr *&EVal);
117 bool ParseDarwinExpression(const MCExpr *&EVal);
118
119 bool ParseOperand(OperandVector &Operands);
120
121 bool ParseDirectiveWord(unsigned Size, AsmToken ID);
122 bool ParseDirectiveTC(unsigned Size, AsmToken ID);
123 bool ParseDirectiveMachine(SMLoc L);
124 bool ParseDarwinDirectiveMachine(SMLoc L);
125 bool ParseDirectiveAbiVersion(SMLoc L);
126 bool ParseDirectiveLocalEntry(SMLoc L);
127
128 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
129 OperandVector &Operands, MCStreamer &Out,
130 uint64_t &ErrorInfo,
131 bool MatchingInlineAsm) override;
132
133 void ProcessInstruction(MCInst &Inst, const OperandVector &Ops);
134
135 /// @name Auto-generated Match Functions
136 /// {
137
138 #define GET_ASSEMBLER_HEADER
139 #include "PPCGenAsmMatcher.inc"
140
141 /// }
142
143
144 public:
145 PPCAsmParser(const MCSubtargetInfo &STI, MCAsmParser &,
146 const MCInstrInfo &MII, const MCTargetOptions &Options)
147 : MCTargetAsmParser(Options, STI, MII) {
148 // Check for 64-bit vs. 32-bit pointer mode.
149 const Triple &TheTriple = STI.getTargetTriple();
150 IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
151 TheTriple.getArch() == Triple::ppc64le);
152 IsDarwin = TheTriple.isMacOSX();
153 // Initialize the set of available features.
154 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
155 }
156
157 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
158 SMLoc NameLoc, OperandVector &Operands) override;
159
160 bool ParseDirective(AsmToken DirectiveID) override;
161
162 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
163 unsigned Kind) override;
164
165 const MCExpr *applyModifierToExpr(const MCExpr *E,
166 MCSymbolRefExpr::VariantKind,
167 MCContext &Ctx) override;
168 };
169
170 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
171 /// instruction.
172 struct PPCOperand : public MCParsedAsmOperand {
173 enum KindTy {
174 Token,
175 Immediate,
176 ContextImmediate,
177 Expression,
178 TLSRegister
179 } Kind;
180
181 SMLoc StartLoc, EndLoc;
182 bool IsPPC64;
183
184 struct TokOp {
185 const char *Data;
186 unsigned Length;
187 };
188
189 struct ImmOp {
190 int64_t Val;
191 };
192
193 struct ExprOp {
194 const MCExpr *Val;
195 int64_t CRVal; // Cached result of EvaluateCRExpr(Val)
196 };
197
198 struct TLSRegOp {
199 const MCSymbolRefExpr *Sym;
200 };
201
202 union {
203 struct TokOp Tok;
204 struct ImmOp Imm;
205 struct ExprOp Expr;
206 struct TLSRegOp TLSReg;
207 };
208
209 PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
210 public:
211 PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
212 Kind = o.Kind;
213 StartLoc = o.StartLoc;
214 EndLoc = o.EndLoc;
215 IsPPC64 = o.IsPPC64;
216 switch (Kind) {
217 case Token:
218 Tok = o.Tok;
219 break;
220 case Immediate:
221 case ContextImmediate:
222 Imm = o.Imm;
223 break;
224 case Expression:
225 Expr = o.Expr;
226 break;
227 case TLSRegister:
228 TLSReg = o.TLSReg;
229 break;
230 }
231 }
232
233 // Disable use of sized deallocation due to overallocation of PPCOperand
234 // objects in CreateTokenWithStringCopy.
235 void operator delete(void *p) { ::operator delete(p); }
236
237 /// getStartLoc - Get the location of the first token of this operand.
238 SMLoc getStartLoc() const override { return StartLoc; }
239
240 /// getEndLoc - Get the location of the last token of this operand.
241 SMLoc getEndLoc() const override { return EndLoc; }
242
243 /// getLocRange - Get the range between the first and last token of this
244 /// operand.
245 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
246
247 /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
248 bool isPPC64() const { return IsPPC64; }
249
250 int64_t getImm() const {
251 assert(Kind == Immediate && "Invalid access!");
252 return Imm.Val;
253 }
254 int64_t getImmS16Context() const {
255 assert((Kind == Immediate || Kind == ContextImmediate) &&
256 "Invalid access!");
257 if (Kind == Immediate)
258 return Imm.Val;
259 return static_cast<int16_t>(Imm.Val);
260 }
261 int64_t getImmU16Context() const {
262 assert((Kind == Immediate || Kind == ContextImmediate) &&
263 "Invalid access!");
264 return Imm.Val;
265 }
266
267 const MCExpr *getExpr() const {
268 assert(Kind == Expression && "Invalid access!");
269 return Expr.Val;
270 }
271
272 int64_t getExprCRVal() const {
273 assert(Kind == Expression && "Invalid access!");
274 return Expr.CRVal;
275 }
276
277 const MCExpr *getTLSReg() const {
278 assert(Kind == TLSRegister && "Invalid access!");
279 return TLSReg.Sym;
280 }
281
282 unsigned getReg() const override {
283 assert(isRegNumber() && "Invalid access!");
284 return (unsigned) Imm.Val;
285 }
286
287 unsigned getVSReg() const {
288 assert(isVSRegNumber() && "Invalid access!");
289 return (unsigned) Imm.Val;
290 }
291
292 unsigned getCCReg() const {
293 assert(isCCRegNumber() && "Invalid access!");
294 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
295 }
296
297 unsigned getCRBit() const {
298 assert(isCRBitNumber() && "Invalid access!");
299 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
300 }
301
302 unsigned getCRBitMask() const {
303 assert(isCRBitMask() && "Invalid access!");
304 return 7 - countTrailingZeros<uint64_t>(Imm.Val);
305 }
306
307 bool isToken() const override { return Kind == Token; }
308 bool isImm() const override {
309 return Kind == Immediate || Kind == Expression;
310 }
311 bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); }
312 bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
313 bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); }
314 bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); }
315 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
316 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
317 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
318 bool isU6ImmX2() const { return Kind == Immediate &&
319 isUInt<6>(getImm()) &&
320 (getImm() & 1) == 0; }
321 bool isU7Imm() const { return Kind == Immediate && isUInt<7>(getImm()); }
322 bool isU7ImmX4() const { return Kind == Immediate &&
323 isUInt<7>(getImm()) &&
324 (getImm() & 3) == 0; }
325 bool isU8Imm() const { return Kind == Immediate && isUInt<8>(getImm()); }
326 bool isU8ImmX8() const { return Kind == Immediate &&
327 isUInt<8>(getImm()) &&
328 (getImm() & 7) == 0; }
329
330 bool isU10Imm() const { return Kind == Immediate && isUInt<10>(getImm()); }
331 bool isU12Imm() const { return Kind == Immediate && isUInt<12>(getImm()); }
332 bool isU16Imm() const {
333 switch (Kind) {
334 case Expression:
335 return true;
336 case Immediate:
337 case ContextImmediate:
338 return isUInt<16>(getImmU16Context());
339 default:
340 return false;
341 }
342 }
343 bool isS16Imm() const {
344 switch (Kind) {
345 case Expression:
346 return true;
347 case Immediate:
348 case ContextImmediate:
349 return isInt<16>(getImmS16Context());
350 default:
351 return false;
352 }
353 }
354 bool isS16ImmX4() const { return Kind == Expression ||
355 (Kind == Immediate && isInt<16>(getImm()) &&
356 (getImm() & 3) == 0); }
357 bool isS16ImmX16() const { return Kind == Expression ||
358 (Kind == Immediate && isInt<16>(getImm()) &&
359 (getImm() & 15) == 0); }
360 bool isS17Imm() const {
361 switch (Kind) {
362 case Expression:
363 return true;
364 case Immediate:
365 case ContextImmediate:
366 return isInt<17>(getImmS16Context());
367 default:
368 return false;
369 }
370 }
371 bool isTLSReg() const { return Kind == TLSRegister; }
372 bool isDirectBr() const {
373 if (Kind == Expression)
374 return true;
375 if (Kind != Immediate)
376 return false;
377 // Operand must be 64-bit aligned, signed 27-bit immediate.
378 if ((getImm() & 3) != 0)
379 return false;
380 if (isInt<26>(getImm()))
381 return true;
382 if (!IsPPC64) {
383 // In 32-bit mode, large 32-bit quantities wrap around.
384 if (isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm())))
385 return true;
386 }
387 return false;
388 }
389 bool isCondBr() const { return Kind == Expression ||
390 (Kind == Immediate && isInt<16>(getImm()) &&
391 (getImm() & 3) == 0); }
392 bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
393 bool isVSRegNumber() const {
394 return Kind == Immediate && isUInt<6>(getImm());
395 }
396 bool isCCRegNumber() const { return (Kind == Expression
397 && isUInt<3>(getExprCRVal())) ||
398 (Kind == Immediate
399 && isUInt<3>(getImm())); }
400 bool isCRBitNumber() const { return (Kind == Expression
401 && isUInt<5>(getExprCRVal())) ||
402 (Kind == Immediate
403 && isUInt<5>(getImm())); }
404 bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
405 isPowerOf2_32(getImm()); }
406 bool isATBitsAsHint() const { return false; }
407 bool isMem() const override { return false; }
408 bool isReg() const override { return false; }
409
410 void addRegOperands(MCInst &Inst, unsigned N) const {
411 llvm_unreachable("addRegOperands");
412 }
413
414 void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
415 assert(N == 1 && "Invalid number of operands!");
416 Inst.addOperand(MCOperand::createReg(RRegs[getReg()]));
417 }
418
419 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
420 assert(N == 1 && "Invalid number of operands!");
421 Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()]));
422 }
423
424 void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
425 assert(N == 1 && "Invalid number of operands!");
426 Inst.addOperand(MCOperand::createReg(XRegs[getReg()]));
427 }
428
429 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
430 assert(N == 1 && "Invalid number of operands!");
431 Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()]));
432 }
433
434 void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
435 if (isPPC64())
436 addRegG8RCOperands(Inst, N);
437 else
438 addRegGPRCOperands(Inst, N);
439 }
440
441 void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
442 if (isPPC64())
443 addRegG8RCNoX0Operands(Inst, N);
444 else
445 addRegGPRCNoR0Operands(Inst, N);
446 }
447
448 void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
449 assert(N == 1 && "Invalid number of operands!");
450 Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
451 }
452
453 void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
454 assert(N == 1 && "Invalid number of operands!");
455 Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
456 }
457
458 void addRegVFRCOperands(MCInst &Inst, unsigned N) const {
459 assert(N == 1 && "Invalid number of operands!");
460 Inst.addOperand(MCOperand::createReg(VFRegs[getReg()]));
461 }
462
463 void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
464 assert(N == 1 && "Invalid number of operands!");
465 Inst.addOperand(MCOperand::createReg(VRegs[getReg()]));
466 }
467
468 void addRegVSRCOperands(MCInst &Inst, unsigned N) const {
469 assert(N == 1 && "Invalid number of operands!");
470 Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()]));
471 }
472
473 void addRegVSFRCOperands(MCInst &Inst, unsigned N) const {
474 assert(N == 1 && "Invalid number of operands!");
475 Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()]));
476 }
477
478 void addRegVSSRCOperands(MCInst &Inst, unsigned N) const {
479 assert(N == 1 && "Invalid number of operands!");
480 Inst.addOperand(MCOperand::createReg(VSSRegs[getVSReg()]));
481 }
482
483 void addRegQFRCOperands(MCInst &Inst, unsigned N) const {
484 assert(N == 1 && "Invalid number of operands!");
485 Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
486 }
487
488 void addRegQSRCOperands(MCInst &Inst, unsigned N) const {
489 assert(N == 1 && "Invalid number of operands!");
490 Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
491 }
492
493 void addRegQBRCOperands(MCInst &Inst, unsigned N) const {
494 assert(N == 1 && "Invalid number of operands!");
495 Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
496 }
497
498 void addRegSPE4RCOperands(MCInst &Inst, unsigned N) const {
499 assert(N == 1 && "Invalid number of operands!");
500 Inst.addOperand(MCOperand::createReg(RRegs[getReg()]));
501 }
502
503 void addRegSPERCOperands(MCInst &Inst, unsigned N) const {
504 assert(N == 1 && "Invalid number of operands!");
505 Inst.addOperand(MCOperand::createReg(SPERegs[getReg()]));
506 }
507
508 void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
509 assert(N == 1 && "Invalid number of operands!");
510 Inst.addOperand(MCOperand::createReg(CRBITRegs[getCRBit()]));
511 }
512
513 void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
514 assert(N == 1 && "Invalid number of operands!");
515 Inst.addOperand(MCOperand::createReg(CRRegs[getCCReg()]));
516 }
517
518 void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
519 assert(N == 1 && "Invalid number of operands!");
520 Inst.addOperand(MCOperand::createReg(CRRegs[getCRBitMask()]));
521 }
522
523 void addImmOperands(MCInst &Inst, unsigned N) const {
524 assert(N == 1 && "Invalid number of operands!");
525 if (Kind == Immediate)
526 Inst.addOperand(MCOperand::createImm(getImm()));
527 else
528 Inst.addOperand(MCOperand::createExpr(getExpr()));
529 }
530
531 void addS16ImmOperands(MCInst &Inst, unsigned N) const {
532 assert(N == 1 && "Invalid number of operands!");
533 switch (Kind) {
534 case Immediate:
535 Inst.addOperand(MCOperand::createImm(getImm()));
536 break;
537 case ContextImmediate:
538 Inst.addOperand(MCOperand::createImm(getImmS16Context()));
539 break;
540 default:
541 Inst.addOperand(MCOperand::createExpr(getExpr()));
542 break;
543 }
544 }
545
546 void addU16ImmOperands(MCInst &Inst, unsigned N) const {
547 assert(N == 1 && "Invalid number of operands!");
548 switch (Kind) {
549 case Immediate:
550 Inst.addOperand(MCOperand::createImm(getImm()));
551 break;
552 case ContextImmediate:
553 Inst.addOperand(MCOperand::createImm(getImmU16Context()));
554 break;
555 default:
556 Inst.addOperand(MCOperand::createExpr(getExpr()));
557 break;
558 }
559 }
560
561 void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
562 assert(N == 1 && "Invalid number of operands!");
563 if (Kind == Immediate)
564 Inst.addOperand(MCOperand::createImm(getImm() / 4));
565 else
566 Inst.addOperand(MCOperand::createExpr(getExpr()));
567 }
568
569 void addTLSRegOperands(MCInst &Inst, unsigned N) const {
570 assert(N == 1 && "Invalid number of operands!");
571 Inst.addOperand(MCOperand::createExpr(getTLSReg()));
572 }
573
574 StringRef getToken() const {
575 assert(Kind == Token && "Invalid access!");
576 return StringRef(Tok.Data, Tok.Length);
577 }
578
579 void print(raw_ostream &OS) const override;
580
581 static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S,
582 bool IsPPC64) {
583 auto Op = make_unique<PPCOperand>(Token);
584 Op->Tok.Data = Str.data();
585 Op->Tok.Length = Str.size();
586 Op->StartLoc = S;
587 Op->EndLoc = S;
588 Op->IsPPC64 = IsPPC64;
589 return Op;
590 }
591
592 static std::unique_ptr<PPCOperand>
593 CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) {
594 // Allocate extra memory for the string and copy it.
595 // FIXME: This is incorrect, Operands are owned by unique_ptr with a default
596 // deleter which will destroy them by simply using "delete", not correctly
597 // calling operator delete on this extra memory after calling the dtor
598 // explicitly.
599 void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
600 std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token));
601 Op->Tok.Data = reinterpret_cast<const char *>(Op.get() + 1);
602 Op->Tok.Length = Str.size();
603 std::memcpy(const_cast<char *>(Op->Tok.Data), Str.data(), Str.size());
604 Op->StartLoc = S;
605 Op->EndLoc = S;
606 Op->IsPPC64 = IsPPC64;
607 return Op;
608 }
609
610 static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E,
611 bool IsPPC64) {
612 auto Op = make_unique<PPCOperand>(Immediate);
613 Op->Imm.Val = Val;
614 Op->StartLoc = S;
615 Op->EndLoc = E;
616 Op->IsPPC64 = IsPPC64;
617 return Op;
618 }
619
620 static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S,
621 SMLoc E, bool IsPPC64) {
622 auto Op = make_unique<PPCOperand>(Expression);
623 Op->Expr.Val = Val;
624 Op->Expr.CRVal = EvaluateCRExpr(Val);
625 Op->StartLoc = S;
626 Op->EndLoc = E;
627 Op->IsPPC64 = IsPPC64;
628 return Op;
629 }
630
631 static std::unique_ptr<PPCOperand>
632 CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) {
633 auto Op = make_unique<PPCOperand>(TLSRegister);
634 Op->TLSReg.Sym = Sym;
635 Op->StartLoc = S;
636 Op->EndLoc = E;
637 Op->IsPPC64 = IsPPC64;
638 return Op;
639 }
640
641 static std::unique_ptr<PPCOperand>
642 CreateContextImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
643 auto Op = make_unique<PPCOperand>(ContextImmediate);
644 Op->Imm.Val = Val;
645 Op->StartLoc = S;
646 Op->EndLoc = E;
647 Op->IsPPC64 = IsPPC64;
648 return Op;
649 }
650
651 static std::unique_ptr<PPCOperand>
652 CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) {
653 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
654 return CreateImm(CE->getValue(), S, E, IsPPC64);
655
656 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
657 if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
658 return CreateTLSReg(SRE, S, E, IsPPC64);
659
660 if (const PPCMCExpr *TE = dyn_cast<PPCMCExpr>(Val)) {
661 int64_t Res;
662 if (TE->evaluateAsConstant(Res))
663 return CreateContextImm(Res, S, E, IsPPC64);
664 }
665
666 return CreateExpr(Val, S, E, IsPPC64);
667 }
668 };
669
670 } // end anonymous namespace.
671
672 void PPCOperand::print(raw_ostream &OS) const {
673 switch (Kind) {
674 case Token:
675 OS << "'" << getToken() << "'";
676 break;
677 case Immediate:
678 case ContextImmediate:
679 OS << getImm();
680 break;
681 case Expression:
682 OS << *getExpr();
683 break;
684 case TLSRegister:
685 OS << *getTLSReg();
686 break;
687 }
688 }
689
690 static void
691 addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx) {
692 if (Op.isImm()) {
693 Inst.addOperand(MCOperand::createImm(-Op.getImm()));
694 return;
695 }
696 const MCExpr *Expr = Op.getExpr();
697 if (const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) {
698 if (UnExpr->getOpcode() == MCUnaryExpr::Minus) {
699 Inst.addOperand(MCOperand::createExpr(UnExpr->getSubExpr()));
700 return;
701 }
702 } else if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) {
703 if (BinExpr->getOpcode() == MCBinaryExpr::Sub) {
704 const MCExpr *NE = MCBinaryExpr::createSub(BinExpr->getRHS(),
705 BinExpr->getLHS(), Ctx);
706 Inst.addOperand(MCOperand::createExpr(NE));
707 return;
708 }
709 }
710 Inst.addOperand(MCOperand::createExpr(MCUnaryExpr::createMinus(Expr, Ctx)));
711 }
712
713 void PPCAsmParser::ProcessInstruction(MCInst &Inst,
714 const OperandVector &Operands) {
715 int Opcode = Inst.getOpcode();
716 switch (Opcode) {
717 case PPC::DCBTx:
718 case PPC::DCBTT:
719 case PPC::DCBTSTx:
720 case PPC::DCBTSTT: {
721 MCInst TmpInst;
722 TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ?
723 PPC::DCBT : PPC::DCBTST);
724 TmpInst.addOperand(MCOperand::createImm(
725 (Opcode == PPC::DCBTx || Opcode == PPC::DCBTSTx) ? 0 : 16));
726 TmpInst.addOperand(Inst.getOperand(0));
727 TmpInst.addOperand(Inst.getOperand(1));
728 Inst = TmpInst;
729 break;
730 }
731 case PPC::DCBTCT:
732 case PPC::DCBTDS: {
733 MCInst TmpInst;
734 TmpInst.setOpcode(PPC::DCBT);
735 TmpInst.addOperand(Inst.getOperand(2));
736 TmpInst.addOperand(Inst.getOperand(0));
737 TmpInst.addOperand(Inst.getOperand(1));
738 Inst = TmpInst;
739 break;
740 }
741 case PPC::DCBTSTCT:
742 case PPC::DCBTSTDS: {
743 MCInst TmpInst;
744 TmpInst.setOpcode(PPC::DCBTST);
745 TmpInst.addOperand(Inst.getOperand(2));
746 TmpInst.addOperand(Inst.getOperand(0));
747 TmpInst.addOperand(Inst.getOperand(1));
748 Inst = TmpInst;
749 break;
750 }
751 case PPC::DCBFx:
752 case PPC::DCBFL:
753 case PPC::DCBFLP: {
754 int L = 0;
755 if (Opcode == PPC::DCBFL)
756 L = 1;
757 else if (Opcode == PPC::DCBFLP)
758 L = 3;
759
760 MCInst TmpInst;
761 TmpInst.setOpcode(PPC::DCBF);
762 TmpInst.addOperand(MCOperand::createImm(L));
763 TmpInst.addOperand(Inst.getOperand(0));
764 TmpInst.addOperand(Inst.getOperand(1));
765 Inst = TmpInst;
766 break;
767 }
768 case PPC::LAx: {
769 MCInst TmpInst;
770 TmpInst.setOpcode(PPC::LA);
771 TmpInst.addOperand(Inst.getOperand(0));
772 TmpInst.addOperand(Inst.getOperand(2));
773 TmpInst.addOperand(Inst.getOperand(1));
774 Inst = TmpInst;
775 break;
776 }
777 case PPC::SUBI: {
778 MCInst TmpInst;
779 TmpInst.setOpcode(PPC::ADDI);
780 TmpInst.addOperand(Inst.getOperand(0));
781 TmpInst.addOperand(Inst.getOperand(1));
782 addNegOperand(TmpInst, Inst.getOperand(2), getContext());
783 Inst = TmpInst;
784 break;
785 }
786 case PPC::SUBIS: {
787 MCInst TmpInst;
788 TmpInst.setOpcode(PPC::ADDIS);
789 TmpInst.addOperand(Inst.getOperand(0));
790 TmpInst.addOperand(Inst.getOperand(1));
791 addNegOperand(TmpInst, Inst.getOperand(2), getContext());
792 Inst = TmpInst;
793 break;
794 }
795 case PPC::SUBIC: {
796 MCInst TmpInst;
797 TmpInst.setOpcode(PPC::ADDIC);
798 TmpInst.addOperand(Inst.getOperand(0));
799 TmpInst.addOperand(Inst.getOperand(1));
800 addNegOperand(TmpInst, Inst.getOperand(2), getContext());
801 Inst = TmpInst;
802 break;
803 }
804 case PPC::SUBICo: {
805 MCInst TmpInst;
806 TmpInst.setOpcode(PPC::ADDICo);
807 TmpInst.addOperand(Inst.getOperand(0));
808 TmpInst.addOperand(Inst.getOperand(1));
809 addNegOperand(TmpInst, Inst.getOperand(2), getContext());
810 Inst = TmpInst;
811 break;
812 }
813 case PPC::EXTLWI:
814 case PPC::EXTLWIo: {
815 MCInst TmpInst;
816 int64_t N = Inst.getOperand(2).getImm();
817 int64_t B = Inst.getOperand(3).getImm();
818 TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
819 TmpInst.addOperand(Inst.getOperand(0));
820 TmpInst.addOperand(Inst.getOperand(1));
821 TmpInst.addOperand(MCOperand::createImm(B));
822 TmpInst.addOperand(MCOperand::createImm(0));
823 TmpInst.addOperand(MCOperand::createImm(N - 1));
824 Inst = TmpInst;
825 break;
826 }
827 case PPC::EXTRWI:
828 case PPC::EXTRWIo: {
829 MCInst TmpInst;
830 int64_t N = Inst.getOperand(2).getImm();
831 int64_t B = Inst.getOperand(3).getImm();
832 TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
833 TmpInst.addOperand(Inst.getOperand(0));
834 TmpInst.addOperand(Inst.getOperand(1));
835 TmpInst.addOperand(MCOperand::createImm(B + N));
836 TmpInst.addOperand(MCOperand::createImm(32 - N));
837 TmpInst.addOperand(MCOperand::createImm(31));
838 Inst = TmpInst;
839 break;
840 }
841 case PPC::INSLWI:
842 case PPC::INSLWIo: {
843 MCInst TmpInst;
844 int64_t N = Inst.getOperand(2).getImm();
845 int64_t B = Inst.getOperand(3).getImm();
846 TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
847 TmpInst.addOperand(Inst.getOperand(0));
848 TmpInst.addOperand(Inst.getOperand(0));
849 TmpInst.addOperand(Inst.getOperand(1));
850 TmpInst.addOperand(MCOperand::createImm(32 - B));
851 TmpInst.addOperand(MCOperand::createImm(B));
852 TmpInst.addOperand(MCOperand::createImm((B + N) - 1));
853 Inst = TmpInst;
854 break;
855 }
856 case PPC::INSRWI:
857 case PPC::INSRWIo: {
858 MCInst TmpInst;
859 int64_t N = Inst.getOperand(2).getImm();
860 int64_t B = Inst.getOperand(3).getImm();
861 TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
862 TmpInst.addOperand(Inst.getOperand(0));
863 TmpInst.addOperand(Inst.getOperand(0));
864 TmpInst.addOperand(Inst.getOperand(1));
865 TmpInst.addOperand(MCOperand::createImm(32 - (B + N)));
866 TmpInst.addOperand(MCOperand::createImm(B));
867 TmpInst.addOperand(MCOperand::createImm((B + N) - 1));
868 Inst = TmpInst;
869 break;
870 }
871 case PPC::ROTRWI:
872 case PPC::ROTRWIo: {
873 MCInst TmpInst;
874 int64_t N = Inst.getOperand(2).getImm();
875 TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
876 TmpInst.addOperand(Inst.getOperand(0));
877 TmpInst.addOperand(Inst.getOperand(1));
878 TmpInst.addOperand(MCOperand::createImm(32 - N));
879 TmpInst.addOperand(MCOperand::createImm(0));
880 TmpInst.addOperand(MCOperand::createImm(31));
881 Inst = TmpInst;
882 break;
883 }
884 case PPC::SLWI:
885 case PPC::SLWIo: {
886 MCInst TmpInst;
887 int64_t N = Inst.getOperand(2).getImm();
888 TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
889 TmpInst.addOperand(Inst.getOperand(0));
890 TmpInst.addOperand(Inst.getOperand(1));
891 TmpInst.addOperand(MCOperand::createImm(N));
892 TmpInst.addOperand(MCOperand::createImm(0));
893 TmpInst.addOperand(MCOperand::createImm(31 - N));
894 Inst = TmpInst;
895 break;
896 }
897 case PPC::SRWI:
898 case PPC::SRWIo: {
899 MCInst TmpInst;
900 int64_t N = Inst.getOperand(2).getImm();
901 TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
902 TmpInst.addOperand(Inst.getOperand(0));
903 TmpInst.addOperand(Inst.getOperand(1));
904 TmpInst.addOperand(MCOperand::createImm(32 - N));
905 TmpInst.addOperand(MCOperand::createImm(N));
906 TmpInst.addOperand(MCOperand::createImm(31));
907 Inst = TmpInst;
908 break;
909 }
910 case PPC::CLRRWI:
911 case PPC::CLRRWIo: {
912 MCInst TmpInst;
913 int64_t N = Inst.getOperand(2).getImm();
914 TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
915 TmpInst.addOperand(Inst.getOperand(0));
916 TmpInst.addOperand(Inst.getOperand(1));
917 TmpInst.addOperand(MCOperand::createImm(0));
918 TmpInst.addOperand(MCOperand::createImm(0));
919 TmpInst.addOperand(MCOperand::createImm(31 - N));
920 Inst = TmpInst;
921 break;
922 }
923 case PPC::CLRLSLWI:
924 case PPC::CLRLSLWIo: {
925 MCInst TmpInst;
926 int64_t B = Inst.getOperand(2).getImm();
927 int64_t N = Inst.getOperand(3).getImm();
928 TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
929 TmpInst.addOperand(Inst.getOperand(0));
930 TmpInst.addOperand(Inst.getOperand(1));
931 TmpInst.addOperand(MCOperand::createImm(N));
932 TmpInst.addOperand(MCOperand::createImm(B - N));
933 TmpInst.addOperand(MCOperand::createImm(31 - N));
934 Inst = TmpInst;
935 break;
936 }
937 case PPC::EXTLDI:
938 case PPC::EXTLDIo: {
939 MCInst TmpInst;
940 int64_t N = Inst.getOperand(2).getImm();
941 int64_t B = Inst.getOperand(3).getImm();
942 TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
943 TmpInst.addOperand(Inst.getOperand(0));
944 TmpInst.addOperand(Inst.getOperand(1));
945 TmpInst.addOperand(MCOperand::createImm(B));
946 TmpInst.addOperand(MCOperand::createImm(N - 1));
947 Inst = TmpInst;
948 break;
949 }
950 case PPC::EXTRDI:
951 case PPC::EXTRDIo: {
952 MCInst TmpInst;
953 int64_t N = Inst.getOperand(2).getImm();
954 int64_t B = Inst.getOperand(3).getImm();
955 TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
956 TmpInst.addOperand(Inst.getOperand(0));
957 TmpInst.addOperand(Inst.getOperand(1));
958 TmpInst.addOperand(MCOperand::createImm(B + N));
959 TmpInst.addOperand(MCOperand::createImm(64 - N));
960 Inst = TmpInst;
961 break;
962 }
963 case PPC::INSRDI:
964 case PPC::INSRDIo: {
965 MCInst TmpInst;
966 int64_t N = Inst.getOperand(2).getImm();
967 int64_t B = Inst.getOperand(3).getImm();
968 TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
969 TmpInst.addOperand(Inst.getOperand(0));
970 TmpInst.addOperand(Inst.getOperand(0));
971 TmpInst.addOperand(Inst.getOperand(1));
972 TmpInst.addOperand(MCOperand::createImm(64 - (B + N)));
973 TmpInst.addOperand(MCOperand::createImm(B));
974 Inst = TmpInst;
975 break;
976 }
977 case PPC::ROTRDI:
978 case PPC::ROTRDIo: {
979 MCInst TmpInst;
980 int64_t N = Inst.getOperand(2).getImm();
981 TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
982 TmpInst.addOperand(Inst.getOperand(0));
983 TmpInst.addOperand(Inst.getOperand(1));
984 TmpInst.addOperand(MCOperand::createImm(64 - N));
985 TmpInst.addOperand(MCOperand::createImm(0));
986 Inst = TmpInst;
987 break;
988 }
989 case PPC::SLDI:
990 case PPC::SLDIo: {
991 MCInst TmpInst;
992 int64_t N = Inst.getOperand(2).getImm();
993 TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
994 TmpInst.addOperand(Inst.getOperand(0));
995 TmpInst.addOperand(Inst.getOperand(1));
996 TmpInst.addOperand(MCOperand::createImm(N));
997 TmpInst.addOperand(MCOperand::createImm(63 - N));
998 Inst = TmpInst;
999 break;
1000 }
1001 case PPC::SUBPCIS: {
1002 MCInst TmpInst;
1003 int64_t N = Inst.getOperand(1).getImm();
1004 TmpInst.setOpcode(PPC::ADDPCIS);
1005 TmpInst.addOperand(Inst.getOperand(0));
1006 TmpInst.addOperand(MCOperand::createImm(-N));
1007 Inst = TmpInst;
1008 break;
1009 }
1010 case PPC::SRDI:
1011 case PPC::SRDIo: {
1012 MCInst TmpInst;
1013 int64_t N = Inst.getOperand(2).getImm();
1014 TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
1015 TmpInst.addOperand(Inst.getOperand(0));
1016 TmpInst.addOperand(Inst.getOperand(1));
1017 TmpInst.addOperand(MCOperand::createImm(64 - N));
1018 TmpInst.addOperand(MCOperand::createImm(N));
1019 Inst = TmpInst;
1020 break;
1021 }
1022 case PPC::CLRRDI:
1023 case PPC::CLRRDIo: {
1024 MCInst TmpInst;
1025 int64_t N = Inst.getOperand(2).getImm();
1026 TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
1027 TmpInst.addOperand(Inst.getOperand(0));
1028 TmpInst.addOperand(Inst.getOperand(1));
1029 TmpInst.addOperand(MCOperand::createImm(0));
1030 TmpInst.addOperand(MCOperand::createImm(63 - N));
1031 Inst = TmpInst;
1032 break;
1033 }
1034 case PPC::CLRLSLDI:
1035 case PPC::CLRLSLDIo: {
1036 MCInst TmpInst;
1037 int64_t B = Inst.getOperand(2).getImm();
1038 int64_t N = Inst.getOperand(3).getImm();
1039 TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
1040 TmpInst.addOperand(Inst.getOperand(0));
1041 TmpInst.addOperand(Inst.getOperand(1));
1042 TmpInst.addOperand(MCOperand::createImm(N));
1043 TmpInst.addOperand(MCOperand::createImm(B - N));
1044 Inst = TmpInst;
1045 break;
1046 }
1047 case PPC::RLWINMbm:
1048 case PPC::RLWINMobm: {
1049 unsigned MB, ME;
1050 int64_t BM = Inst.getOperand(3).getImm();
1051 if (!isRunOfOnes(BM, MB, ME))
1052 break;
1053
1054 MCInst TmpInst;
1055 TmpInst.setOpcode(Opcode == PPC::RLWINMbm ? PPC::RLWINM : PPC::RLWINMo);
1056 TmpInst.addOperand(Inst.getOperand(0));
1057 TmpInst.addOperand(Inst.getOperand(1));
1058 TmpInst.addOperand(Inst.getOperand(2));
1059 TmpInst.addOperand(MCOperand::createImm(MB));
1060 TmpInst.addOperand(MCOperand::createImm(ME));
1061 Inst = TmpInst;
1062 break;
1063 }
1064 case PPC::RLWIMIbm:
1065 case PPC::RLWIMIobm: {
1066 unsigned MB, ME;
1067 int64_t BM = Inst.getOperand(3).getImm();
1068 if (!isRunOfOnes(BM, MB, ME))
1069 break;
1070
1071 MCInst TmpInst;
1072 TmpInst.setOpcode(Opcode == PPC::RLWIMIbm ? PPC::RLWIMI : PPC::RLWIMIo);
1073 TmpInst.addOperand(Inst.getOperand(0));
1074 TmpInst.addOperand(Inst.getOperand(0)); // The tied operand.
1075 TmpInst.addOperand(Inst.getOperand(1));
1076 TmpInst.addOperand(Inst.getOperand(2));
1077 TmpInst.addOperand(MCOperand::createImm(MB));
1078 TmpInst.addOperand(MCOperand::createImm(ME));
1079 Inst = TmpInst;
1080 break;
1081 }
1082 case PPC::RLWNMbm:
1083 case PPC::RLWNMobm: {
1084 unsigned MB, ME;
1085 int64_t BM = Inst.getOperand(3).getImm();
1086 if (!isRunOfOnes(BM, MB, ME))
1087 break;
1088
1089 MCInst TmpInst;
1090 TmpInst.setOpcode(Opcode == PPC::RLWNMbm ? PPC::RLWNM : PPC::RLWNMo);
1091 TmpInst.addOperand(Inst.getOperand(0));
1092 TmpInst.addOperand(Inst.getOperand(1));
1093 TmpInst.addOperand(Inst.getOperand(2));
1094 TmpInst.addOperand(MCOperand::createImm(MB));
1095 TmpInst.addOperand(MCOperand::createImm(ME));
1096 Inst = TmpInst;
1097 break;
1098 }
1099 case PPC::MFTB: {
1100 if (getSTI().getFeatureBits()[PPC::FeatureMFTB]) {
1101 assert(Inst.getNumOperands() == 2 && "Expecting two operands");
1102 Inst.setOpcode(PPC::MFSPR);
1103 }
1104 break;
1105 }
1106 case PPC::CP_COPYx:
1107 case PPC::CP_COPY_FIRST: {
1108 MCInst TmpInst;
1109 TmpInst.setOpcode(PPC::CP_COPY);
1110 TmpInst.addOperand(Inst.getOperand(0));
1111 TmpInst.addOperand(Inst.getOperand(1));
1112 TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_COPYx ? 0 : 1));
1113
1114 Inst = TmpInst;
1115 break;
1116 }
1117 case PPC::CP_PASTEx :
1118 case PPC::CP_PASTE_LAST: {
1119 MCInst TmpInst;
1120 TmpInst.setOpcode(Opcode == PPC::CP_PASTEx ?
1121 PPC::CP_PASTE : PPC::CP_PASTEo);
1122 TmpInst.addOperand(Inst.getOperand(0));
1123 TmpInst.addOperand(Inst.getOperand(1));
1124 TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_PASTEx ? 0 : 1));
1125
1126 Inst = TmpInst;
1127 break;
1128 }
1129 }
1130 }
1131
1132 static std::string PPCMnemonicSpellCheck(StringRef S, uint64_t FBS,
1133 unsigned VariantID = 0);
1134
1135 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1136 OperandVector &Operands,
1137 MCStreamer &Out, uint64_t &ErrorInfo,
1138 bool MatchingInlineAsm) {
1139 MCInst Inst;
1140
1141 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
1142 case Match_Success:
1143 // Post-process instructions (typically extended mnemonics)
1144 ProcessInstruction(Inst, Operands);
1145 Inst.setLoc(IDLoc);
1146 Out.EmitInstruction(Inst, getSTI());
1147 return false;
1148 case Match_MissingFeature:
1149 return Error(IDLoc, "instruction use requires an option to be enabled");
1150 case Match_MnemonicFail: {
1151 uint64_t FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
1152 std::string Suggestion = PPCMnemonicSpellCheck(
1153 ((PPCOperand &)*Operands[0]).getToken(), FBS);
1154 return Error(IDLoc, "invalid instruction" + Suggestion,
1155 ((PPCOperand &)*Operands[0]).getLocRange());
1156 }
1157 case Match_InvalidOperand: {
1158 SMLoc ErrorLoc = IDLoc;
1159 if (ErrorInfo != ~0ULL) {
1160 if (ErrorInfo >= Operands.size())
1161 return Error(IDLoc, "too few operands for instruction");
1162
1163 ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc();
1164 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
1165 }
1166
1167 return Error(ErrorLoc, "invalid operand for instruction");
1168 }
1169 }
1170
1171 llvm_unreachable("Implement any new match types added!");
1172 }
1173
1174 bool PPCAsmParser::MatchRegisterName(unsigned &RegNo, int64_t &IntVal) {
1175 if (getParser().getTok().is(AsmToken::Identifier)) {
1176 StringRef Name = getParser().getTok().getString();
1177 if (Name.equals_lower("lr")) {
1178 RegNo = isPPC64()? PPC::LR8 : PPC::LR;
1179 IntVal = 8;
1180 } else if (Name.equals_lower("ctr")) {
1181 RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
1182 IntVal = 9;
1183 } else if (Name.equals_lower("vrsave")) {
1184 RegNo = PPC::VRSAVE;
1185 IntVal = 256;
1186 } else if (Name.startswith_lower("r") &&
1187 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1188 RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
1189 } else if (Name.startswith_lower("f") &&
1190 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1191 RegNo = FRegs[IntVal];
1192 } else if (Name.startswith_lower("vs") &&
1193 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 64) {
1194 RegNo = VSRegs[IntVal];
1195 } else if (Name.startswith_lower("v") &&
1196 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1197 RegNo = VRegs[IntVal];
1198 } else if (Name.startswith_lower("q") &&
1199 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1200 RegNo = QFRegs[IntVal];
1201 } else if (Name.startswith_lower("cr") &&
1202 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
1203 RegNo = CRRegs[IntVal];
1204 } else
1205 return true;
1206 getParser().Lex();
1207 return false;
1208 }
1209 return true;
1210 }
1211
1212 bool PPCAsmParser::
1213 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
1214 const AsmToken &Tok = getParser().getTok();
1215 StartLoc = Tok.getLoc();
1216 EndLoc = Tok.getEndLoc();
1217 RegNo = 0;
1218 int64_t IntVal;
1219 if (MatchRegisterName(RegNo, IntVal))
1220 return TokError("invalid register name");
1221 return false;
1222 }
1223
1224 /// Extract \code @l/@ha \endcode modifier from expression. Recursively scan
1225 /// the expression and check for VK_PPC_LO/HI/HA
1226 /// symbol variants. If all symbols with modifier use the same
1227 /// variant, return the corresponding PPCMCExpr::VariantKind,
1228 /// and a modified expression using the default symbol variant.
1229 /// Otherwise, return NULL.
1230 const MCExpr *PPCAsmParser::
1231 ExtractModifierFromExpr(const MCExpr *E,
1232 PPCMCExpr::VariantKind &Variant) {
1233 MCContext &Context = getParser().getContext();
1234 Variant = PPCMCExpr::VK_PPC_None;
1235
1236 switch (E->getKind()) {
1237 case MCExpr::Target:
1238 case MCExpr::Constant:
1239 return nullptr;
1240
1241 case MCExpr::SymbolRef: {
1242 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1243
1244 switch (SRE->getKind()) {
1245 case MCSymbolRefExpr::VK_PPC_LO:
1246 Variant = PPCMCExpr::VK_PPC_LO;
1247 break;
1248 case MCSymbolRefExpr::VK_PPC_HI:
1249 Variant = PPCMCExpr::VK_PPC_HI;
1250 break;
1251 case MCSymbolRefExpr::VK_PPC_HA:
1252 Variant = PPCMCExpr::VK_PPC_HA;
1253 break;
1254 case MCSymbolRefExpr::VK_PPC_HIGH:
1255 Variant = PPCMCExpr::VK_PPC_HIGH;
1256 break;
1257 case MCSymbolRefExpr::VK_PPC_HIGHA:
1258 Variant = PPCMCExpr::VK_PPC_HIGHA;
1259 break;
1260 case MCSymbolRefExpr::VK_PPC_HIGHER:
1261 Variant = PPCMCExpr::VK_PPC_HIGHER;
1262 break;
1263 case MCSymbolRefExpr::VK_PPC_HIGHERA:
1264 Variant = PPCMCExpr::VK_PPC_HIGHERA;
1265 break;
1266 case MCSymbolRefExpr::VK_PPC_HIGHEST:
1267 Variant = PPCMCExpr::VK_PPC_HIGHEST;
1268 break;
1269 case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1270 Variant = PPCMCExpr::VK_PPC_HIGHESTA;
1271 break;
1272 default:
1273 return nullptr;
1274 }
1275
1276 return MCSymbolRefExpr::create(&SRE->getSymbol(), Context);
1277 }
1278
1279 case MCExpr::Unary: {
1280 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1281 const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
1282 if (!Sub)
1283 return nullptr;
1284 return MCUnaryExpr::create(UE->getOpcode(), Sub, Context);
1285 }
1286
1287 case MCExpr::Binary: {
1288 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1289 PPCMCExpr::VariantKind LHSVariant, RHSVariant;
1290 const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
1291 const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
1292
1293 if (!LHS && !RHS)
1294 return nullptr;
1295
1296 if (!LHS) LHS = BE->getLHS();
1297 if (!RHS) RHS = BE->getRHS();
1298
1299 if (LHSVariant == PPCMCExpr::VK_PPC_None)
1300 Variant = RHSVariant;
1301 else if (RHSVariant == PPCMCExpr::VK_PPC_None)
1302 Variant = LHSVariant;
1303 else if (LHSVariant == RHSVariant)
1304 Variant = LHSVariant;
1305 else
1306 return nullptr;
1307
1308 return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context);
1309 }
1310 }
1311
1312 llvm_unreachable("Invalid expression kind!");
1313 }
1314
1315 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1316 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD. This is necessary to avoid having
1317 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1318 /// FIXME: This is a hack.
1319 const MCExpr *PPCAsmParser::
1320 FixupVariantKind(const MCExpr *E) {
1321 MCContext &Context = getParser().getContext();
1322
1323 switch (E->getKind()) {
1324 case MCExpr::Target:
1325 case MCExpr::Constant:
1326 return E;
1327
1328 case MCExpr::SymbolRef: {
1329 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1330 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1331
1332 switch (SRE->getKind()) {
1333 case MCSymbolRefExpr::VK_TLSGD:
1334 Variant = MCSymbolRefExpr::VK_PPC_TLSGD;
1335 break;
1336 case MCSymbolRefExpr::VK_TLSLD:
1337 Variant = MCSymbolRefExpr::VK_PPC_TLSLD;
1338 break;
1339 default:
1340 return E;
1341 }
1342 return MCSymbolRefExpr::create(&SRE->getSymbol(), Variant, Context);
1343 }
1344
1345 case MCExpr::Unary: {
1346 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1347 const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1348 if (Sub == UE->getSubExpr())
1349 return E;
1350 return MCUnaryExpr::create(UE->getOpcode(), Sub, Context);
1351 }
1352
1353 case MCExpr::Binary: {
1354 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1355 const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1356 const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1357 if (LHS == BE->getLHS() && RHS == BE->getRHS())
1358 return E;
1359 return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context);
1360 }
1361 }
1362
1363 llvm_unreachable("Invalid expression kind!");
1364 }
1365
1366 /// ParseExpression. This differs from the default "parseExpression" in that
1367 /// it handles modifiers.
1368 bool PPCAsmParser::
1369 ParseExpression(const MCExpr *&EVal) {
1370
1371 if (isDarwin())
1372 return ParseDarwinExpression(EVal);
1373
1374 // (ELF Platforms)
1375 // Handle \code @l/@ha \endcode
1376 if (getParser().parseExpression(EVal))
1377 return true;
1378
1379 EVal = FixupVariantKind(EVal);
1380
1381 PPCMCExpr::VariantKind Variant;
1382 const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1383 if (E)
1384 EVal = PPCMCExpr::create(Variant, E, false, getParser().getContext());
1385
1386 return false;
1387 }
1388
1389 /// ParseDarwinExpression. (MachO Platforms)
1390 /// This differs from the default "parseExpression" in that it handles detection
1391 /// of the \code hi16(), ha16() and lo16() \endcode modifiers. At present,
1392 /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO
1393 /// syntax form so it is done here. TODO: Determine if there is merit in
1394 /// arranging for this to be done at a higher level.
1395 bool PPCAsmParser::
1396 ParseDarwinExpression(const MCExpr *&EVal) {
1397 MCAsmParser &Parser = getParser();
1398 PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None;
1399 switch (getLexer().getKind()) {
1400 default:
1401 break;
1402 case AsmToken::Identifier:
1403 // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus
1404 // something starting with any other char should be part of the
1405 // asm syntax. If handwritten asm includes an identifier like lo16,
1406 // then all bets are off - but no-one would do that, right?
1407 StringRef poss = Parser.getTok().getString();
1408 if (poss.equals_lower("lo16")) {
1409 Variant = PPCMCExpr::VK_PPC_LO;
1410 } else if (poss.equals_lower("hi16")) {
1411 Variant = PPCMCExpr::VK_PPC_HI;
1412 } else if (poss.equals_lower("ha16")) {
1413 Variant = PPCMCExpr::VK_PPC_HA;
1414 }
1415 if (Variant != PPCMCExpr::VK_PPC_None) {
1416 Parser.Lex(); // Eat the xx16
1417 if (getLexer().isNot(AsmToken::LParen))
1418 return Error(Parser.getTok().getLoc(), "expected '('");
1419 Parser.Lex(); // Eat the '('
1420 }
1421 break;
1422 }
1423
1424 if (getParser().parseExpression(EVal))
1425 return true;
1426
1427 if (Variant != PPCMCExpr::VK_PPC_None) {
1428 if (getLexer().isNot(AsmToken::RParen))
1429 return Error(Parser.getTok().getLoc(), "expected ')'");
1430 Parser.Lex(); // Eat the ')'
1431 EVal = PPCMCExpr::create(Variant, EVal, false, getParser().getContext());
1432 }
1433 return false;
1434 }
1435
1436 /// ParseOperand
1437 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and
1438 /// rNN for MachO.
1439 bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
1440 MCAsmParser &Parser = getParser();
1441 SMLoc S = Parser.getTok().getLoc();
1442 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1443 const MCExpr *EVal;
1444
1445 // Attempt to parse the next token as an immediate
1446 switch (getLexer().getKind()) {
1447 // Special handling for register names. These are interpreted
1448 // as immediates corresponding to the register number.
1449 case AsmToken::Percent:
1450 Parser.Lex(); // Eat the '%'.
1451 unsigned RegNo;
1452 int64_t IntVal;
1453 if (MatchRegisterName(RegNo, IntVal))
1454 return Error(S, "invalid register name");
1455
1456 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1457 return false;
1458
1459 case AsmToken::Identifier:
1460 case AsmToken::LParen:
1461 case AsmToken::Plus:
1462 case AsmToken::Minus:
1463 case AsmToken::Integer:
1464 case AsmToken::Dot:
1465 case AsmToken::Dollar:
1466 case AsmToken::Exclaim:
1467 case AsmToken::Tilde:
1468 // Note that non-register-name identifiers from the compiler will begin
1469 // with '_', 'L'/'l' or '"'. Of course, handwritten asm could include
1470 // identifiers like r31foo - so we fall through in the event that parsing
1471 // a register name fails.
1472 if (isDarwin()) {
1473 unsigned RegNo;
1474 int64_t IntVal;
1475 if (!MatchRegisterName(RegNo, IntVal)) {
1476 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1477 return false;
1478 }
1479 }
1480 // All other expressions
1481
1482 if (!ParseExpression(EVal))
1483 break;
1484 // Fall-through
1485 LLVM_FALLTHROUGH;
1486 default:
1487 return Error(S, "unknown operand");
1488 }
1489
1490 // Push the parsed operand into the list of operands
1491 Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64()));
1492
1493 // Check whether this is a TLS call expression
1494 bool TLSCall = false;
1495 if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1496 TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1497
1498 if (TLSCall && getLexer().is(AsmToken::LParen)) {
1499 const MCExpr *TLSSym;
1500
1501 Parser.Lex(); // Eat the '('.
1502 S = Parser.getTok().getLoc();
1503 if (ParseExpression(TLSSym))
1504 return Error(S, "invalid TLS call expression");
1505 if (getLexer().isNot(AsmToken::RParen))
1506 return Error(Parser.getTok().getLoc(), "missing ')'");
1507 E = Parser.getTok().getLoc();
1508 Parser.Lex(); // Eat the ')'.
1509
1510 Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64()));
1511 }
1512
1513 // Otherwise, check for D-form memory operands
1514 if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1515 Parser.Lex(); // Eat the '('.
1516 S = Parser.getTok().getLoc();
1517
1518 int64_t IntVal;
1519 switch (getLexer().getKind()) {
1520 case AsmToken::Percent:
1521 Parser.Lex(); // Eat the '%'.
1522 unsigned RegNo;
1523 if (MatchRegisterName(RegNo, IntVal))
1524 return Error(S, "invalid register name");
1525 break;
1526
1527 case AsmToken::Integer:
1528 if (isDarwin())
1529 return Error(S, "unexpected integer value");
1530 else if (getParser().parseAbsoluteExpression(IntVal) || IntVal < 0 ||
1531 IntVal > 31)
1532 return Error(S, "invalid register number");
1533 break;
1534 case AsmToken::Identifier:
1535 if (isDarwin()) {
1536 unsigned RegNo;
1537 if (!MatchRegisterName(RegNo, IntVal)) {
1538 break;
1539 }
1540 }
1541 LLVM_FALLTHROUGH;
1542
1543 default:
1544 return Error(S, "invalid memory operand");
1545 }
1546
1547 E = Parser.getTok().getLoc();
1548 if (parseToken(AsmToken::RParen, "missing ')'"))
1549 return true;
1550 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1551 }
1552
1553 return false;
1554 }
1555
1556 /// Parse an instruction mnemonic followed by its operands.
1557 bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
1558 SMLoc NameLoc, OperandVector &Operands) {
1559 // The first operand is the token for the instruction name.
1560 // If the next character is a '+' or '-', we need to add it to the
1561 // instruction name, to match what TableGen is doing.
1562 std::string NewOpcode;
1563 if (parseOptionalToken(AsmToken::Plus)) {
1564 NewOpcode = Name;
1565 NewOpcode += '+';
1566 Name = NewOpcode;
1567 }
1568 if (parseOptionalToken(AsmToken::Minus)) {
1569 NewOpcode = Name;
1570 NewOpcode += '-';
1571 Name = NewOpcode;
1572 }
1573 // If the instruction ends in a '.', we need to create a separate
1574 // token for it, to match what TableGen is doing.
1575 size_t Dot = Name.find('.');
1576 StringRef Mnemonic = Name.slice(0, Dot);
1577 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1578 Operands.push_back(
1579 PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1580 else
1581 Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1582 if (Dot != StringRef::npos) {
1583 SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1584 StringRef DotStr = Name.slice(Dot, StringRef::npos);
1585 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1586 Operands.push_back(
1587 PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1588 else
1589 Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1590 }
1591
1592 // If there are no more operands then finish
1593 if (parseOptionalToken(AsmToken::EndOfStatement))
1594 return false;
1595
1596 // Parse the first operand
1597 if (ParseOperand(Operands))
1598 return true;
1599
1600 while (!parseOptionalToken(AsmToken::EndOfStatement)) {
1601 if (parseToken(AsmToken::Comma) || ParseOperand(Operands))
1602 return true;
1603 }
1604
1605 // We'll now deal with an unfortunate special case: the syntax for the dcbt
1606 // and dcbtst instructions differs for server vs. embedded cores.
1607 // The syntax for dcbt is:
1608 // dcbt ra, rb, th [server]
1609 // dcbt th, ra, rb [embedded]
1610 // where th can be omitted when it is 0. dcbtst is the same. We take the
1611 // server form to be the default, so swap the operands if we're parsing for
1612 // an embedded core (they'll be swapped again upon printing).
1613 if (getSTI().getFeatureBits()[PPC::FeatureBookE] &&
1614 Operands.size() == 4 &&
1615 (Name == "dcbt" || Name == "dcbtst")) {
1616 std::swap(Operands[1], Operands[3]);
1617 std::swap(Operands[2], Operands[1]);
1618 }
1619
1620 return false;
1621 }
1622
1623 /// ParseDirective parses the PPC specific directives
1624 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1625 StringRef IDVal = DirectiveID.getIdentifier();
1626 if (isDarwin()) {
1627 if (IDVal == ".machine")
1628 ParseDarwinDirectiveMachine(DirectiveID.getLoc());
1629 else
1630 return true;
1631 } else if (IDVal == ".word")
1632 ParseDirectiveWord(2, DirectiveID);
1633 else if (IDVal == ".llong")
1634 ParseDirectiveWord(8, DirectiveID);
1635 else if (IDVal == ".tc")
1636 ParseDirectiveTC(isPPC64() ? 8 : 4, DirectiveID);
1637 else if (IDVal == ".machine")
1638 ParseDirectiveMachine(DirectiveID.getLoc());
1639 else if (IDVal == ".abiversion")
1640 ParseDirectiveAbiVersion(DirectiveID.getLoc());
1641 else if (IDVal == ".localentry")
1642 ParseDirectiveLocalEntry(DirectiveID.getLoc());
1643 else
1644 return true;
1645 return false;
1646 }
1647
1648 /// ParseDirectiveWord
1649 /// ::= .word [ expression (, expression)* ]
1650 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, AsmToken ID) {
1651 auto parseOp = [&]() -> bool {
1652 const MCExpr *Value;
1653 SMLoc ExprLoc = getParser().getTok().getLoc();
1654 if (getParser().parseExpression(Value))
1655 return true;
1656 if (const auto *MCE = dyn_cast<MCConstantExpr>(Value)) {
1657 assert(Size <= 8 && "Invalid size");
1658 uint64_t IntValue = MCE->getValue();
1659 if (!isUIntN(8 * Size, IntValue) && !isIntN(8 * Size, IntValue))
1660 return Error(ExprLoc, "literal value out of range for '" +
1661 ID.getIdentifier() + "' directive");
1662 getStreamer().EmitIntValue(IntValue, Size);
1663 } else
1664 getStreamer().EmitValue(Value, Size, ExprLoc);
1665 return false;
1666 };
1667
1668 if (parseMany(parseOp))
1669 return addErrorSuffix(" in '" + ID.getIdentifier() + "' directive");
1670 return false;
1671 }
1672
1673 /// ParseDirectiveTC
1674 /// ::= .tc [ symbol (, expression)* ]
1675 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, AsmToken ID) {
1676 MCAsmParser &Parser = getParser();
1677 // Skip TC symbol, which is only used with XCOFF.
1678 while (getLexer().isNot(AsmToken::EndOfStatement)
1679 && getLexer().isNot(AsmToken::Comma))
1680 Parser.Lex();
1681 if (parseToken(AsmToken::Comma))
1682 return addErrorSuffix(" in '.tc' directive");
1683
1684 // Align to word size.
1685 getParser().getStreamer().EmitValueToAlignment(Size);
1686
1687 // Emit expressions.
1688 return ParseDirectiveWord(Size, ID);
1689 }
1690
1691 /// ParseDirectiveMachine (ELF platforms)
1692 /// ::= .machine [ cpu | "push" | "pop" ]
1693 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1694 MCAsmParser &Parser = getParser();
1695 if (Parser.getTok().isNot(AsmToken::Identifier) &&
1696 Parser.getTok().isNot(AsmToken::String))
1697 return Error(L, "unexpected token in '.machine' directive");
1698
1699 StringRef CPU = Parser.getTok().getIdentifier();
1700
1701 // FIXME: Right now, the parser always allows any available
1702 // instruction, so the .machine directive is not useful.
1703 // Implement ".machine any" (by doing nothing) for the benefit
1704 // of existing assembler code. Likewise, we can then implement
1705 // ".machine push" and ".machine pop" as no-op.
1706 if (CPU != "any" && CPU != "push" && CPU != "pop")
1707 return TokError("unrecognized machine type");
1708
1709 Parser.Lex();
1710
1711 if (parseToken(AsmToken::EndOfStatement))
1712 return addErrorSuffix(" in '.machine' directive");
1713
1714 PPCTargetStreamer &TStreamer =
1715 *static_cast<PPCTargetStreamer *>(
1716 getParser().getStreamer().getTargetStreamer());
1717 TStreamer.emitMachine(CPU);
1718
1719 return false;
1720 }
1721
1722 /// ParseDarwinDirectiveMachine (Mach-o platforms)
1723 /// ::= .machine cpu-identifier
1724 bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) {
1725 MCAsmParser &Parser = getParser();
1726 if (Parser.getTok().isNot(AsmToken::Identifier) &&
1727 Parser.getTok().isNot(AsmToken::String))
1728 return Error(L, "unexpected token in directive");
1729
1730 StringRef CPU = Parser.getTok().getIdentifier();
1731 Parser.Lex();
1732
1733 // FIXME: this is only the 'default' set of cpu variants.
1734 // However we don't act on this information at present, this is simply
1735 // allowing parsing to proceed with minimal sanity checking.
1736 if (check(CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64", L,
1737 "unrecognized cpu type") ||
1738 check(isPPC64() && (CPU == "ppc7400" || CPU == "ppc"), L,
1739 "wrong cpu type specified for 64bit") ||
1740 check(!isPPC64() && CPU == "ppc64", L,
1741 "wrong cpu type specified for 32bit") ||
1742 parseToken(AsmToken::EndOfStatement))
1743 return addErrorSuffix(" in '.machine' directive");
1744 return false;
1745 }
1746
1747 /// ParseDirectiveAbiVersion
1748 /// ::= .abiversion constant-expression
1749 bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) {
1750 int64_t AbiVersion;
1751 if (check(getParser().parseAbsoluteExpression(AbiVersion), L,
1752 "expected constant expression") ||
1753 parseToken(AsmToken::EndOfStatement))
1754 return addErrorSuffix(" in '.abiversion' directive");
1755
1756 PPCTargetStreamer &TStreamer =
1757 *static_cast<PPCTargetStreamer *>(
1758 getParser().getStreamer().getTargetStreamer());
1759 TStreamer.emitAbiVersion(AbiVersion);
1760
1761 return false;
1762 }
1763
1764 /// ParseDirectiveLocalEntry
1765 /// ::= .localentry symbol, expression
1766 bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) {
1767 StringRef Name;
1768 if (getParser().parseIdentifier(Name))
1769 return Error(L, "expected identifier in '.localentry' directive");
1770
1771 MCSymbolELF *Sym = cast<MCSymbolELF>(getContext().getOrCreateSymbol(Name));
1772 const MCExpr *Expr;
1773
1774 if (parseToken(AsmToken::Comma) ||
1775 check(getParser().parseExpression(Expr), L, "expected expression") ||
1776 parseToken(AsmToken::EndOfStatement))
1777 return addErrorSuffix(" in '.localentry' directive");
1778
1779 PPCTargetStreamer &TStreamer =
1780 *static_cast<PPCTargetStreamer *>(
1781 getParser().getStreamer().getTargetStreamer());
1782 TStreamer.emitLocalEntry(Sym, Expr);
1783
1784 return false;
1785 }
1786
1787
1788
1789 /// Force static initialization.
1790 extern "C" void LLVMInitializePowerPCAsmParser() {
1791 RegisterMCAsmParser<PPCAsmParser> A(getThePPC32Target());
1792 RegisterMCAsmParser<PPCAsmParser> B(getThePPC64Target());
1793 RegisterMCAsmParser<PPCAsmParser> C(getThePPC64LETarget());
1794 }
1795
1796 #define GET_REGISTER_MATCHER
1797 #define GET_MATCHER_IMPLEMENTATION
1798 #define GET_MNEMONIC_SPELL_CHECKER
1799 #include "PPCGenAsmMatcher.inc"
1800
1801 // Define this matcher function after the auto-generated include so we
1802 // have the match class enum definitions.
1803 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
1804 unsigned Kind) {
1805 // If the kind is a token for a literal immediate, check if our asm
1806 // operand matches. This is for InstAliases which have a fixed-value
1807 // immediate in the syntax.
1808 int64_t ImmVal;
1809 switch (Kind) {
1810 case MCK_0: ImmVal = 0; break;
1811 case MCK_1: ImmVal = 1; break;
1812 case MCK_2: ImmVal = 2; break;
1813 case MCK_3: ImmVal = 3; break;
1814 case MCK_4: ImmVal = 4; break;
1815 case MCK_5: ImmVal = 5; break;
1816 case MCK_6: ImmVal = 6; break;
1817 case MCK_7: ImmVal = 7; break;
1818 default: return Match_InvalidOperand;
1819 }
1820
1821 PPCOperand &Op = static_cast<PPCOperand &>(AsmOp);
1822 if (Op.isImm() && Op.getImm() == ImmVal)
1823 return Match_Success;
1824
1825 return Match_InvalidOperand;
1826 }
1827
1828 const MCExpr *
1829 PPCAsmParser::applyModifierToExpr(const MCExpr *E,
1830 MCSymbolRefExpr::VariantKind Variant,
1831 MCContext &Ctx) {
1832 switch (Variant) {
1833 case MCSymbolRefExpr::VK_PPC_LO:
1834 return PPCMCExpr::create(PPCMCExpr::VK_PPC_LO, E, false, Ctx);
1835 case MCSymbolRefExpr::VK_PPC_HI:
1836 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HI, E, false, Ctx);
1837 case MCSymbolRefExpr::VK_PPC_HA:
1838 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HA, E, false, Ctx);
1839 case MCSymbolRefExpr::VK_PPC_HIGH:
1840 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGH, E, false, Ctx);
1841 case MCSymbolRefExpr::VK_PPC_HIGHA:
1842 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHA, E, false, Ctx);
1843 case MCSymbolRefExpr::VK_PPC_HIGHER:
1844 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx);
1845 case MCSymbolRefExpr::VK_PPC_HIGHERA:
1846 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx);
1847 case MCSymbolRefExpr::VK_PPC_HIGHEST:
1848 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx);
1849 case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1850 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx);
1851 default:
1852 return nullptr;
1853 }
1854 }
1855