1; RUN: llc -march=hexagon < %s | FileCheck %s
2
3; --- and
4
5; CHECK-LABEL: andb_64:
6; CHECK: vand(v0,v1)
7define <64 x i8> @andb_64(<64 x i8> %v0, <64 x i8> %v1) #0 {
8  %p = and <64 x i8> %v0, %v1
9  ret <64 x i8> %p
10}
11
12; CHECK-LABEL: andb_128:
13; CHECK: vand(v0,v1)
14define <128 x i8> @andb_128(<128 x i8> %v0, <128 x i8> %v1) #1 {
15  %p = and <128 x i8> %v0, %v1
16  ret <128 x i8> %p
17}
18
19; CHECK-LABEL: andh_64:
20; CHECK: vand(v0,v1)
21define <32 x i16> @andh_64(<32 x i16> %v0, <32 x i16> %v1) #0 {
22  %p = and <32 x i16> %v0, %v1
23  ret <32 x i16> %p
24}
25
26; CHECK-LABEL: andh_128:
27; CHECK: vand(v0,v1)
28define <64 x i16> @andh_128(<64 x i16> %v0, <64 x i16> %v1) #1 {
29  %p = and <64 x i16> %v0, %v1
30  ret <64 x i16> %p
31}
32
33; CHECK-LABEL: andw_64:
34; CHECK: vand(v0,v1)
35define <16 x i32> @andw_64(<16 x i32> %v0, <16 x i32> %v1) #0 {
36  %p = and <16 x i32> %v0, %v1
37  ret <16 x i32> %p
38}
39
40; CHECK-LABEL: andw_128:
41; CHECK: vand(v0,v1)
42define <32 x i32> @andw_128(<32 x i32> %v0, <32 x i32> %v1) #1 {
43  %p = and <32 x i32> %v0, %v1
44  ret <32 x i32> %p
45}
46
47; --- or
48
49; CHECK-LABEL: orb_64:
50; CHECK: vor(v0,v1)
51define <64 x i8> @orb_64(<64 x i8> %v0, <64 x i8> %v1) #0 {
52  %p = or <64 x i8> %v0, %v1
53  ret <64 x i8> %p
54}
55
56; CHECK-LABEL: orb_128:
57; CHECK: vor(v0,v1)
58define <128 x i8> @orb_128(<128 x i8> %v0, <128 x i8> %v1) #1 {
59  %p = or <128 x i8> %v0, %v1
60  ret <128 x i8> %p
61}
62
63; CHECK-LABEL: orh_64:
64; CHECK: vor(v0,v1)
65define <32 x i16> @orh_64(<32 x i16> %v0, <32 x i16> %v1) #0 {
66  %p = or <32 x i16> %v0, %v1
67  ret <32 x i16> %p
68}
69
70; CHECK-LABEL: orh_128:
71; CHECK: vor(v0,v1)
72define <64 x i16> @orh_128(<64 x i16> %v0, <64 x i16> %v1) #1 {
73  %p = or <64 x i16> %v0, %v1
74  ret <64 x i16> %p
75}
76
77; CHECK-LABEL: orw_64:
78; CHECK: vor(v0,v1)
79define <16 x i32> @orw_64(<16 x i32> %v0, <16 x i32> %v1) #0 {
80  %p = or <16 x i32> %v0, %v1
81  ret <16 x i32> %p
82}
83
84; CHECK-LABEL: orw_128:
85; CHECK: vor(v0,v1)
86define <32 x i32> @orw_128(<32 x i32> %v0, <32 x i32> %v1) #1 {
87  %p = or <32 x i32> %v0, %v1
88  ret <32 x i32> %p
89}
90
91; --- xor
92
93; CHECK-LABEL: xorb_64:
94; CHECK: vxor(v0,v1)
95define <64 x i8> @xorb_64(<64 x i8> %v0, <64 x i8> %v1) #0 {
96  %p = xor <64 x i8> %v0, %v1
97  ret <64 x i8> %p
98}
99
100; CHECK-LABEL: xorb_128:
101; CHECK: vxor(v0,v1)
102define <128 x i8> @xorb_128(<128 x i8> %v0, <128 x i8> %v1) #1 {
103  %p = xor <128 x i8> %v0, %v1
104  ret <128 x i8> %p
105}
106
107; CHECK-LABEL: xorh_64:
108; CHECK: vxor(v0,v1)
109define <32 x i16> @xorh_64(<32 x i16> %v0, <32 x i16> %v1) #0 {
110  %p = xor <32 x i16> %v0, %v1
111  ret <32 x i16> %p
112}
113
114; CHECK-LABEL: xorh_128:
115; CHECK: vxor(v0,v1)
116define <64 x i16> @xorh_128(<64 x i16> %v0, <64 x i16> %v1) #1 {
117  %p = xor <64 x i16> %v0, %v1
118  ret <64 x i16> %p
119}
120
121; CHECK-LABEL: xorw_64:
122; CHECK: vxor(v0,v1)
123define <16 x i32> @xorw_64(<16 x i32> %v0, <16 x i32> %v1) #0 {
124  %p = xor <16 x i32> %v0, %v1
125  ret <16 x i32> %p
126}
127
128; CHECK-LABEL: xorw_128:
129; CHECK: vxor(v0,v1)
130define <32 x i32> @xorw_128(<32 x i32> %v0, <32 x i32> %v1) #1 {
131  %p = xor <32 x i32> %v0, %v1
132  ret <32 x i32> %p
133}
134
135; --- add
136
137; CHECK-LABEL: addb_64:
138; CHECK: vadd(v0.b,v1.b)
139define <64 x i8> @addb_64(<64 x i8> %v0, <64 x i8> %v1) #0 {
140  %p = add <64 x i8> %v0, %v1
141  ret <64 x i8> %p
142}
143
144; CHECK-LABEL: addb_128:
145; CHECK: vadd(v0.b,v1.b)
146define <128 x i8> @addb_128(<128 x i8> %v0, <128 x i8> %v1) #1 {
147  %p = add <128 x i8> %v0, %v1
148  ret <128 x i8> %p
149}
150
151; CHECK-LABEL: addh_64:
152; CHECK: vadd(v0.h,v1.h)
153define <32 x i16> @addh_64(<32 x i16> %v0, <32 x i16> %v1) #0 {
154  %p = add <32 x i16> %v0, %v1
155  ret <32 x i16> %p
156}
157
158; CHECK-LABEL: addh_128:
159; CHECK: vadd(v0.h,v1.h)
160define <64 x i16> @addh_128(<64 x i16> %v0, <64 x i16> %v1) #1 {
161  %p = add <64 x i16> %v0, %v1
162  ret <64 x i16> %p
163}
164
165; CHECK-LABEL: addw_64:
166; CHECK: vadd(v0.w,v1.w)
167define <16 x i32> @addw_64(<16 x i32> %v0, <16 x i32> %v1) #0 {
168  %p = add <16 x i32> %v0, %v1
169  ret <16 x i32> %p
170}
171
172; CHECK-LABEL: addw_128:
173; CHECK: vadd(v0.w,v1.w)
174define <32 x i32> @addw_128(<32 x i32> %v0, <32 x i32> %v1) #1 {
175  %p = add <32 x i32> %v0, %v1
176  ret <32 x i32> %p
177}
178
179; --- sub
180
181; CHECK-LABEL: subb_64:
182; CHECK: vsub(v0.b,v1.b)
183define <64 x i8> @subb_64(<64 x i8> %v0, <64 x i8> %v1) #0 {
184  %p = sub <64 x i8> %v0, %v1
185  ret <64 x i8> %p
186}
187
188; CHECK-LABEL: subb_128:
189; CHECK: vsub(v0.b,v1.b)
190define <128 x i8> @subb_128(<128 x i8> %v0, <128 x i8> %v1) #1 {
191  %p = sub <128 x i8> %v0, %v1
192  ret <128 x i8> %p
193}
194
195; CHECK-LABEL: subh_64:
196; CHECK: vsub(v0.h,v1.h)
197define <32 x i16> @subh_64(<32 x i16> %v0, <32 x i16> %v1) #0 {
198  %p = sub <32 x i16> %v0, %v1
199  ret <32 x i16> %p
200}
201
202; CHECK-LABEL: subh_128:
203; CHECK: vsub(v0.h,v1.h)
204define <64 x i16> @subh_128(<64 x i16> %v0, <64 x i16> %v1) #1 {
205  %p = sub <64 x i16> %v0, %v1
206  ret <64 x i16> %p
207}
208
209; CHECK-LABEL: subw_64:
210; CHECK: vsub(v0.w,v1.w)
211define <16 x i32> @subw_64(<16 x i32> %v0, <16 x i32> %v1) #0 {
212  %p = sub <16 x i32> %v0, %v1
213  ret <16 x i32> %p
214}
215
216; CHECK-LABEL: subw_128:
217; CHECK: vsub(v0.w,v1.w)
218define <32 x i32> @subw_128(<32 x i32> %v0, <32 x i32> %v1) #1 {
219  %p = sub <32 x i32> %v0, %v1
220  ret <32 x i32> %p
221}
222
223; --- mul
224
225; CHECK-LABEL: mpyb_64:
226; CHECK: v[[H00:[0-9]+]]:[[L00:[0-9]+]].h = vmpy(v0.b,v1.b)
227; CHECK: vshuffe(v[[H00]].b,v[[L00]].b)
228define <64 x i8> @mpyb_64(<64 x i8> %v0, <64 x i8> %v1) #0 {
229  %p = mul <64 x i8> %v0, %v1
230  ret <64 x i8> %p
231}
232
233; CHECK-LABEL: mpyb_128:
234; CHECK: v[[H10:[0-9]+]]:[[L10:[0-9]+]].h = vmpy(v0.b,v1.b)
235; CHECK: vshuffe(v[[H10]].b,v[[L10]].b)
236define <128 x i8> @mpyb_128(<128 x i8> %v0, <128 x i8> %v1) #1 {
237  %p = mul <128 x i8> %v0, %v1
238  ret <128 x i8> %p
239}
240
241; CHECK-LABEL: mpyh_64:
242; CHECK: vmpyi(v0.h,v1.h)
243define <32 x i16> @mpyh_64(<32 x i16> %v0, <32 x i16> %v1) #0 {
244  %p = mul <32 x i16> %v0, %v1
245  ret <32 x i16> %p
246}
247
248; CHECK-LABEL: mpyh_128:
249; CHECK: vmpyi(v0.h,v1.h)
250define <64 x i16> @mpyh_128(<64 x i16> %v0, <64 x i16> %v1) #1 {
251  %p = mul <64 x i16> %v0, %v1
252  ret <64 x i16> %p
253}
254
255; CHECK-LABEL: mpyw_64:
256; CHECK-DAG: r[[T00:[0-9]+]] = #16
257; CHECK-DAG: v[[T01:[0-9]+]].w = vmpyio(v0.w,v1.h)
258; CHECK:     v[[T02:[0-9]+]].w = vasl(v[[T01]].w,r[[T00]])
259; CHECK:     v[[T02]].w += vmpyie(v0.w,v1.uh)
260define <16 x i32> @mpyw_64(<16 x i32> %v0, <16 x i32> %v1) #0 {
261  %p = mul <16 x i32> %v0, %v1
262  ret <16 x i32> %p
263}
264
265; CHECK-LABEL: mpyw_128:
266; CHECK-DAG: r[[T10:[0-9]+]] = #16
267; CHECK-DAG: v[[T11:[0-9]+]].w = vmpyio(v0.w,v1.h)
268; CHECK:     v[[T12:[0-9]+]].w = vasl(v[[T11]].w,r[[T10]])
269; CHECK:     v[[T12]].w += vmpyie(v0.w,v1.uh)
270define <32 x i32> @mpyw_128(<32 x i32> %v0, <32 x i32> %v1) #1 {
271  %p = mul <32 x i32> %v0, %v1
272  ret <32 x i32> %p
273}
274
275attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }
276attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }
277