1; RUN: llc -march=hexagon < %s | FileCheck %s 2 3; Check that both functions compile successfully. 4 5 6target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" 7target triple = "hexagon" 8 9; CHECK-LABEL: danny: 10; CHECK: vmem 11define void @danny(i16* %a0) #0 { 12b0: 13 %v1 = load i16, i16* %a0, align 2 14 %v2 = insertelement <8 x i16> undef, i16 %v1, i32 6 15 %v3 = insertelement <8 x i16> %v2, i16 undef, i32 7 16 %v4 = sext <8 x i16> %v3 to <8 x i32> 17 %v5 = mul <8 x i32> %v4, <i32 -36410, i32 -36410, i32 -36410, i32 -36410, i32 -36410, i32 -36410, i32 -36410, i32 -36410> 18 %v6 = add <8 x i32> %v5, <i32 32768, i32 32768, i32 32768, i32 32768, i32 32768, i32 32768, i32 32768, i32 32768> 19 %v7 = add <8 x i32> %v6, zeroinitializer 20 %v8 = ashr <8 x i32> %v7, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16> 21 %v9 = add nsw <8 x i32> zeroinitializer, %v8 22 %v10 = shl <8 x i32> %v9, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16> 23 %v11 = ashr exact <8 x i32> %v10, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16> 24 %v12 = sub nsw <8 x i32> zeroinitializer, %v11 25 %v13 = trunc <8 x i32> %v12 to <8 x i16> 26 %v14 = extractelement <8 x i16> %v13, i32 7 27 store i16 %v14, i16* %a0, align 2 28 ret void 29} 30 31; CHECK-LABEL: sammy: 32; CHECK: vmem 33define void @sammy(i16* %a0) #1 { 34b0: 35 %v1 = load i16, i16* %a0, align 2 36 %v2 = insertelement <16 x i16> undef, i16 %v1, i32 14 37 %v3 = insertelement <16 x i16> %v2, i16 undef, i32 15 38 %v4 = sext <16 x i16> %v3 to <16 x i32> 39 %v5 = mul <16 x i32> %v4, <i32 -36410, i32 -36410, i32 -36410, i32 -36410, i32 -36410, i32 -36410, i32 -36410, i32 -36410, i32 -36410, i32 -36410, i32 -36410, i32 -36410, i32 -36410, i32 -36410, i32 -36410, i32 -36410> 40 %v6 = add <16 x i32> %v5, <i32 32768, i32 32768, i32 32768, i32 32768, i32 32768, i32 32768, i32 32768, i32 32768, i32 32768, i32 32768, i32 32768, i32 32768, i32 32768, i32 32768, i32 32768, i32 32768> 41 %v7 = add <16 x i32> %v6, zeroinitializer 42 %v8 = ashr <16 x i32> %v7, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16> 43 %v9 = add nsw <16 x i32> zeroinitializer, %v8 44 %v10 = shl <16 x i32> %v9, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16> 45 %v11 = ashr exact <16 x i32> %v10, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16> 46 %v12 = sub nsw <16 x i32> zeroinitializer, %v11 47 %v13 = trunc <16 x i32> %v12 to <16 x i16> 48 %v14 = extractelement <16 x i16> %v13, i32 15 49 store i16 %v14, i16* %a0, align 2 50 ret void 51} 52 53attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-length64b,+hvxv60" } 54attributes #1 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-length128b,+hvxv60" } 55