1//===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the PowerPC 64-bit instructions. These patterns are used 10// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// 64-bit operands. 16// 17def s16imm64 : Operand<i64> { 18 let PrintMethod = "printS16ImmOperand"; 19 let EncoderMethod = "getImm16Encoding"; 20 let ParserMatchClass = PPCS16ImmAsmOperand; 21 let DecoderMethod = "decodeSImmOperand<16>"; 22} 23def u16imm64 : Operand<i64> { 24 let PrintMethod = "printU16ImmOperand"; 25 let EncoderMethod = "getImm16Encoding"; 26 let ParserMatchClass = PPCU16ImmAsmOperand; 27 let DecoderMethod = "decodeUImmOperand<16>"; 28} 29def s17imm64 : Operand<i64> { 30 // This operand type is used for addis/lis to allow the assembler parser 31 // to accept immediates in the range -65536..65535 for compatibility with 32 // the GNU assembler. The operand is treated as 16-bit otherwise. 33 let PrintMethod = "printS16ImmOperand"; 34 let EncoderMethod = "getImm16Encoding"; 35 let ParserMatchClass = PPCS17ImmAsmOperand; 36 let DecoderMethod = "decodeSImmOperand<16>"; 37} 38def tocentry : Operand<iPTR> { 39 let MIOperandInfo = (ops i64imm:$imm); 40} 41def tlsreg : Operand<i64> { 42 let EncoderMethod = "getTLSRegEncoding"; 43 let ParserMatchClass = PPCTLSRegOperand; 44} 45def tlsgd : Operand<i64> {} 46def tlscall : Operand<i64> { 47 let PrintMethod = "printTLSCall"; 48 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym); 49 let EncoderMethod = "getTLSCallEncoding"; 50} 51 52//===----------------------------------------------------------------------===// 53// 64-bit transformation functions. 54// 55 56def SHL64 : SDNodeXForm<imm, [{ 57 // Transformation function: 63 - imm 58 return getI32Imm(63 - N->getZExtValue(), SDLoc(N)); 59}]>; 60 61def SRL64 : SDNodeXForm<imm, [{ 62 // Transformation function: 64 - imm 63 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue(), SDLoc(N)) 64 : getI32Imm(0, SDLoc(N)); 65}]>; 66 67 68//===----------------------------------------------------------------------===// 69// Calls. 70// 71 72let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 73let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 74 let isReturn = 1, Uses = [LR8, RM] in 75 def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 76 [(retflag)]>, Requires<[In64BitMode]>; 77 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in { 78 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 79 []>, 80 Requires<[In64BitMode]>; 81 def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 82 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 83 []>, 84 Requires<[In64BitMode]>; 85 86 def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi), 87 "bcctr 12, $bi, 0", IIC_BrB, []>, 88 Requires<[In64BitMode]>; 89 def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi), 90 "bcctr 4, $bi, 0", IIC_BrB, []>, 91 Requires<[In64BitMode]>; 92 } 93} 94 95let Defs = [LR8] in 96 def MovePCtoLR8 : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR8", []>, 97 PPC970_Unit_BRU; 98 99let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 100 let Defs = [CTR8], Uses = [CTR8] in { 101 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 102 "bdz $dst">; 103 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 104 "bdnz $dst">; 105 } 106 107 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in { 108 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 109 "bdzlr", IIC_BrB, []>; 110 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 111 "bdnzlr", IIC_BrB, []>; 112 } 113} 114 115 116 117let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 118 // Convenient aliases for call instructions 119 let Uses = [RM] in { 120 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func), 121 "bl $func", IIC_BrB, []>; // See Pat patterns below. 122 123 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func), 124 "bl $func", IIC_BrB, []>; 125 126 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 127 "bla $func", IIC_BrB, [(PPCcall (i64 imm:$func))]>; 128 } 129 let Uses = [RM], isCodeGenOnly = 1 in { 130 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 131 (outs), (ins calltarget:$func), 132 "bl $func\n\tnop", IIC_BrB, []>; 133 134 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24, 135 (outs), (ins tlscall:$func), 136 "bl $func\n\tnop", IIC_BrB, []>; 137 138 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24, 139 (outs), (ins abscalltarget:$func), 140 "bla $func\n\tnop", IIC_BrB, 141 [(PPCcall_nop (i64 imm:$func))]>; 142 } 143 let Uses = [CTR8, RM] in { 144 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 145 "bctrl", IIC_BrB, [(PPCbctrl)]>, 146 Requires<[In64BitMode]>; 147 148 let isCodeGenOnly = 1 in { 149 def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 150 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 151 []>, 152 Requires<[In64BitMode]>; 153 154 def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi), 155 "bcctrl 12, $bi, 0", IIC_BrB, []>, 156 Requires<[In64BitMode]>; 157 def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi), 158 "bcctrl 4, $bi, 0", IIC_BrB, []>, 159 Requires<[In64BitMode]>; 160 } 161 } 162} 163 164let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 165 Defs = [LR8, X2], Uses = [CTR8, RM], RST = 2 in { 166 def BCTRL8_LDinto_toc : 167 XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs), 168 (ins memrix:$src), 169 "bctrl\n\tld 2, $src", IIC_BrB, 170 [(PPCbctrl_load_toc iaddrX4:$src)]>, 171 Requires<[In64BitMode]>; 172} 173 174} // Interpretation64Bit 175 176// FIXME: Duplicating this for the asm parser should be unnecessary, but the 177// previous definition must be marked as CodeGen only to prevent decoding 178// conflicts. 179let Interpretation64Bit = 1, isAsmParserOnly = 1 in 180let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in 181def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$func), 182 "bl $func", IIC_BrB, []>; 183 184// Calls 185def : Pat<(PPCcall (i64 tglobaladdr:$dst)), 186 (BL8 tglobaladdr:$dst)>; 187def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)), 188 (BL8_NOP tglobaladdr:$dst)>; 189 190def : Pat<(PPCcall (i64 texternalsym:$dst)), 191 (BL8 texternalsym:$dst)>; 192def : Pat<(PPCcall_nop (i64 texternalsym:$dst)), 193 (BL8_NOP texternalsym:$dst)>; 194 195// Calls for AIX 196def : Pat<(PPCcall (i64 mcsym:$dst)), 197 (BL8 mcsym:$dst)>; 198def : Pat<(PPCcall_nop (i64 mcsym:$dst)), 199 (BL8_NOP mcsym:$dst)>; 200 201// Atomic operations 202// FIXME: some of these might be used with constant operands. This will result 203// in constant materialization instructions that may be redundant. We currently 204// clean this up in PPCMIPeephole with calls to 205// PPCInstrInfo::convertToImmediateForm() but we should probably not emit them 206// in the first place. 207let Defs = [CR0] in { 208 def ATOMIC_LOAD_ADD_I64 : PPCCustomInserterPseudo< 209 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64", 210 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>; 211 def ATOMIC_LOAD_SUB_I64 : PPCCustomInserterPseudo< 212 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64", 213 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>; 214 def ATOMIC_LOAD_OR_I64 : PPCCustomInserterPseudo< 215 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64", 216 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>; 217 def ATOMIC_LOAD_XOR_I64 : PPCCustomInserterPseudo< 218 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64", 219 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>; 220 def ATOMIC_LOAD_AND_I64 : PPCCustomInserterPseudo< 221 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64", 222 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>; 223 def ATOMIC_LOAD_NAND_I64 : PPCCustomInserterPseudo< 224 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64", 225 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>; 226 def ATOMIC_LOAD_MIN_I64 : PPCCustomInserterPseudo< 227 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MIN_I64", 228 [(set i64:$dst, (atomic_load_min_64 xoaddr:$ptr, i64:$incr))]>; 229 def ATOMIC_LOAD_MAX_I64 : PPCCustomInserterPseudo< 230 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MAX_I64", 231 [(set i64:$dst, (atomic_load_max_64 xoaddr:$ptr, i64:$incr))]>; 232 def ATOMIC_LOAD_UMIN_I64 : PPCCustomInserterPseudo< 233 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMIN_I64", 234 [(set i64:$dst, (atomic_load_umin_64 xoaddr:$ptr, i64:$incr))]>; 235 def ATOMIC_LOAD_UMAX_I64 : PPCCustomInserterPseudo< 236 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMAX_I64", 237 [(set i64:$dst, (atomic_load_umax_64 xoaddr:$ptr, i64:$incr))]>; 238 239 def ATOMIC_CMP_SWAP_I64 : PPCCustomInserterPseudo< 240 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64", 241 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>; 242 243 def ATOMIC_SWAP_I64 : PPCCustomInserterPseudo< 244 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64", 245 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>; 246} 247 248// Instructions to support atomic operations 249let mayLoad = 1, hasSideEffects = 0 in { 250def LDARX : XForm_1_memOp<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 251 "ldarx $rD, $ptr", IIC_LdStLDARX, []>; 252 253// Instruction to support lock versions of atomics 254// (EH=1 - see Power ISA 2.07 Book II 4.4.2) 255def LDARXL : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 256 "ldarx $rD, $ptr, 1", IIC_LdStLDARX, []>, isDOT; 257 258let hasExtraDefRegAllocReq = 1 in 259def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$rD), (ins g8rc:$rA, u5imm:$FC), 260 "ldat $rD, $rA, $FC", IIC_LdStLoad>, isPPC64, 261 Requires<[IsISA3_0]>; 262} 263 264let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 265def STDCX : XForm_1_memOp<31, 214, (outs), (ins g8rc:$rS, memrr:$dst), 266 "stdcx. $rS, $dst", IIC_LdStSTDCX, []>, isDOT; 267 268let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 269def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$rS, g8rc:$rA, u5imm:$FC), 270 "stdat $rS, $rA, $FC", IIC_LdStStore>, isPPC64, 271 Requires<[IsISA3_0]>; 272 273let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 274let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 275def TCRETURNdi8 :PPCEmitTimePseudo< (outs), 276 (ins calltarget:$dst, i32imm:$offset), 277 "#TC_RETURNd8 $dst $offset", 278 []>; 279 280let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 281def TCRETURNai8 :PPCEmitTimePseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 282 "#TC_RETURNa8 $func $offset", 283 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 284 285let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 286def TCRETURNri8 : PPCEmitTimePseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset), 287 "#TC_RETURNr8 $dst $offset", 288 []>; 289 290let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 291 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in 292def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 293 []>, 294 Requires<[In64BitMode]>; 295 296let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 297 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 298def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 299 "b $dst", IIC_BrB, 300 []>; 301 302let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 303 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 304def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), 305 "ba $dst", IIC_BrB, 306 []>; 307} // Interpretation64Bit 308 309def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 310 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 311 312def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 313 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 314 315def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 316 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 317 318 319// 64-bit CR instructions 320let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 321let hasSideEffects = 0 in { 322// mtocrf's input needs to be prepared by shifting by an amount dependent 323// on the cr register selected. Thus, post-ra anti-dep breaking must not 324// later change that register assignment. 325let hasExtraDefRegAllocReq = 1 in { 326def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST), 327 "mtocrf $FXM, $ST", IIC_BrMCRX>, 328 PPC970_DGroup_First, PPC970_Unit_CRU; 329 330// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that 331// is dependent on the cr fields being set. 332def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS), 333 "mtcrf $FXM, $rS", IIC_BrMCRX>, 334 PPC970_MicroCode, PPC970_Unit_CRU; 335} // hasExtraDefRegAllocReq = 1 336 337// mfocrf's input needs to be prepared by shifting by an amount dependent 338// on the cr register selected. Thus, post-ra anti-dep breaking must not 339// later change that register assignment. 340let hasExtraSrcRegAllocReq = 1 in { 341def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM), 342 "mfocrf $rT, $FXM", IIC_SprMFCRF>, 343 PPC970_DGroup_First, PPC970_Unit_CRU; 344 345// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that 346// is dependent on the cr fields being copied. 347def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins), 348 "mfcr $rT", IIC_SprMFCR>, 349 PPC970_MicroCode, PPC970_Unit_CRU; 350} // hasExtraSrcRegAllocReq = 1 351} // hasSideEffects = 0 352 353// While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp 354// is not. 355let hasSideEffects = 1 in { 356 let Defs = [CTR8] in 357 def EH_SjLj_SetJmp64 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf), 358 "#EH_SJLJ_SETJMP64", 359 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 360 Requires<[In64BitMode]>; 361} 362 363let hasSideEffects = 1, isBarrier = 1 in { 364 let isTerminator = 1 in 365 def EH_SjLj_LongJmp64 : PPCCustomInserterPseudo<(outs), (ins memr:$buf), 366 "#EH_SJLJ_LONGJMP64", 367 [(PPCeh_sjlj_longjmp addr:$buf)]>, 368 Requires<[In64BitMode]>; 369} 370 371def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RT), (ins i32imm:$SPR), 372 "mfspr $RT, $SPR", IIC_SprMFSPR>; 373def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RT), 374 "mtspr $SPR, $RT", IIC_SprMTSPR>; 375 376 377//===----------------------------------------------------------------------===// 378// 64-bit SPR manipulation instrs. 379 380let Uses = [CTR8] in { 381def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins), 382 "mfctr $rT", IIC_SprMFSPR>, 383 PPC970_DGroup_First, PPC970_Unit_FXU; 384} 385let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in { 386def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 387 "mtctr $rS", IIC_SprMTSPR>, 388 PPC970_DGroup_First, PPC970_Unit_FXU; 389} 390let hasSideEffects = 1, Defs = [CTR8] in { 391let Pattern = [(int_set_loop_iterations i64:$rS)] in 392def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 393 "mtctr $rS", IIC_SprMTSPR>, 394 PPC970_DGroup_First, PPC970_Unit_FXU; 395} 396 397let Pattern = [(set i64:$rT, readcyclecounter)] in 398def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins), 399 "mfspr $rT, 268", IIC_SprMFTB>, 400 PPC970_DGroup_First, PPC970_Unit_FXU; 401// Note that encoding mftb using mfspr is now the preferred form, 402// and has been since at least ISA v2.03. The mftb instruction has 403// now been phased out. Using mfspr, however, is known not to work on 404// the POWER3. 405 406let Defs = [X1], Uses = [X1] in 407def DYNALLOC8 : PPCEmitTimePseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8", 408 [(set i64:$result, 409 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>; 410def DYNAREAOFFSET8 : PPCEmitTimePseudo<(outs i64imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET8", 411 [(set i64:$result, (PPCdynareaoffset iaddr:$fpsi))]>; 412 413let Defs = [LR8] in { 414def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS), 415 "mtlr $rS", IIC_SprMTSPR>, 416 PPC970_DGroup_First, PPC970_Unit_FXU; 417} 418let Uses = [LR8] in { 419def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins), 420 "mflr $rT", IIC_SprMFSPR>, 421 PPC970_DGroup_First, PPC970_Unit_FXU; 422} 423} // Interpretation64Bit 424 425//===----------------------------------------------------------------------===// 426// Fixed point instructions. 427// 428 429let PPC970_Unit = 1 in { // FXU Operations. 430let Interpretation64Bit = 1 in { 431let hasSideEffects = 0 in { 432let isCodeGenOnly = 1 in { 433 434let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 435def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm), 436 "li $rD, $imm", IIC_IntSimple, 437 [(set i64:$rD, imm64SExt16:$imm)]>; 438def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm), 439 "lis $rD, $imm", IIC_IntSimple, 440 [(set i64:$rD, imm16ShiftedSExt:$imm)]>; 441} 442 443// Logical ops. 444let isCommutable = 1 in { 445defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 446 "nand", "$rA, $rS, $rB", IIC_IntSimple, 447 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>; 448defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 449 "and", "$rA, $rS, $rB", IIC_IntSimple, 450 [(set i64:$rA, (and i64:$rS, i64:$rB))]>; 451} // isCommutable 452defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 453 "andc", "$rA, $rS, $rB", IIC_IntSimple, 454 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>; 455let isCommutable = 1 in { 456defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 457 "or", "$rA, $rS, $rB", IIC_IntSimple, 458 [(set i64:$rA, (or i64:$rS, i64:$rB))]>; 459defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 460 "nor", "$rA, $rS, $rB", IIC_IntSimple, 461 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>; 462} // isCommutable 463defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 464 "orc", "$rA, $rS, $rB", IIC_IntSimple, 465 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>; 466let isCommutable = 1 in { 467defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 468 "eqv", "$rA, $rS, $rB", IIC_IntSimple, 469 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>; 470defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 471 "xor", "$rA, $rS, $rB", IIC_IntSimple, 472 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>; 473} // let isCommutable = 1 474 475// Logical ops with immediate. 476let Defs = [CR0] in { 477def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 478 "andi. $dst, $src1, $src2", IIC_IntGeneral, 479 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>, 480 isDOT; 481def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 482 "andis. $dst, $src1, $src2", IIC_IntGeneral, 483 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>, 484 isDOT; 485} 486def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 487 "ori $dst, $src1, $src2", IIC_IntSimple, 488 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>; 489def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 490 "oris $dst, $src1, $src2", IIC_IntSimple, 491 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>; 492def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 493 "xori $dst, $src1, $src2", IIC_IntSimple, 494 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>; 495def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 496 "xoris $dst, $src1, $src2", IIC_IntSimple, 497 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>; 498 499let isCommutable = 1 in 500defm ADD8 : XOForm_1rx<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 501 "add", "$rT, $rA, $rB", IIC_IntSimple, 502 [(set i64:$rT, (add i64:$rA, i64:$rB))]>; 503// ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the 504// initial-exec thread-local storage model. We need to forbid r0 here - 505// while it works for add just fine, the linker can relax this to local-exec 506// addi, which won't work for r0. 507def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc_nox0:$rA, tlsreg:$rB), 508 "add $rT, $rA, $rB", IIC_IntSimple, 509 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>; 510let mayLoad = 1 in { 511def LBZXTLS : XForm_1<31, 87, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 512 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 513def LHZXTLS : XForm_1<31, 279, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 514 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 515def LWZXTLS : XForm_1<31, 23, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 516 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 517def LDXTLS : XForm_1<31, 21, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 518 "ldx $rD, $rA, $rB", IIC_LdStLD, []>, isPPC64; 519def LBZXTLS_32 : XForm_1<31, 87, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 520 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 521def LHZXTLS_32 : XForm_1<31, 279, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 522 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 523def LWZXTLS_32 : XForm_1<31, 23, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 524 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 525 526} 527 528let mayStore = 1 in { 529def STBXTLS : XForm_8<31, 215, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 530 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 531 PPC970_DGroup_Cracked; 532def STHXTLS : XForm_8<31, 407, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 533 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 534 PPC970_DGroup_Cracked; 535def STWXTLS : XForm_8<31, 151, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 536 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 537 PPC970_DGroup_Cracked; 538def STDXTLS : XForm_8<31, 149, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 539 "stdx $rS, $rA, $rB", IIC_LdStSTD, []>, isPPC64, 540 PPC970_DGroup_Cracked; 541def STBXTLS_32 : XForm_8<31, 215, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 542 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 543 PPC970_DGroup_Cracked; 544def STHXTLS_32 : XForm_8<31, 407, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 545 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 546 PPC970_DGroup_Cracked; 547def STWXTLS_32 : XForm_8<31, 151, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 548 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 549 PPC970_DGroup_Cracked; 550 551} 552 553let isCommutable = 1 in 554defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 555 "addc", "$rT, $rA, $rB", IIC_IntGeneral, 556 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>, 557 PPC970_DGroup_Cracked; 558 559let Defs = [CARRY] in 560def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 561 "addic $rD, $rA, $imm", IIC_IntGeneral, 562 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>; 563def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm), 564 "addi $rD, $rA, $imm", IIC_IntSimple, 565 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>; 566def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm), 567 "addis $rD, $rA, $imm", IIC_IntSimple, 568 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>; 569 570let Defs = [CARRY] in { 571def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 572 "subfic $rD, $rA, $imm", IIC_IntGeneral, 573 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>; 574} 575defm SUBFC8 : XOForm_1rc<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 576 "subfc", "$rT, $rA, $rB", IIC_IntGeneral, 577 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>, 578 PPC970_DGroup_Cracked; 579defm SUBF8 : XOForm_1rx<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 580 "subf", "$rT, $rA, $rB", IIC_IntGeneral, 581 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>; 582defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA), 583 "neg", "$rT, $rA", IIC_IntSimple, 584 [(set i64:$rT, (ineg i64:$rA))]>; 585let Uses = [CARRY] in { 586let isCommutable = 1 in 587defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 588 "adde", "$rT, $rA, $rB", IIC_IntGeneral, 589 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>; 590defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA), 591 "addme", "$rT, $rA", IIC_IntGeneral, 592 [(set i64:$rT, (adde i64:$rA, -1))]>; 593defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA), 594 "addze", "$rT, $rA", IIC_IntGeneral, 595 [(set i64:$rT, (adde i64:$rA, 0))]>; 596defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 597 "subfe", "$rT, $rA, $rB", IIC_IntGeneral, 598 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>; 599defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA), 600 "subfme", "$rT, $rA", IIC_IntGeneral, 601 [(set i64:$rT, (sube -1, i64:$rA))]>; 602defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA), 603 "subfze", "$rT, $rA", IIC_IntGeneral, 604 [(set i64:$rT, (sube 0, i64:$rA))]>; 605} 606} // isCodeGenOnly 607 608// FIXME: Duplicating this for the asm parser should be unnecessary, but the 609// previous definition must be marked as CodeGen only to prevent decoding 610// conflicts. 611let isAsmParserOnly = 1 in { 612def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB), 613 "add $rT, $rA, $rB", IIC_IntSimple, []>; 614 615let mayLoad = 1 in { 616def LBZXTLS_ : XForm_1<31, 87, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 617 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 618def LHZXTLS_ : XForm_1<31, 279, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 619 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 620def LWZXTLS_ : XForm_1<31, 23, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 621 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 622def LDXTLS_ : XForm_1<31, 21, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 623 "ldx $rD, $rA, $rB", IIC_LdStLD, []>, isPPC64; 624} 625 626let mayStore = 1 in { 627def STBXTLS_ : XForm_8<31, 215, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 628 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 629 PPC970_DGroup_Cracked; 630def STHXTLS_ : XForm_8<31, 407, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 631 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 632 PPC970_DGroup_Cracked; 633def STWXTLS_ : XForm_8<31, 151, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 634 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 635 PPC970_DGroup_Cracked; 636def STDXTLS_ : XForm_8<31, 149, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 637 "stdx $rS, $rA, $rB", IIC_LdStSTD, []>, isPPC64, 638 PPC970_DGroup_Cracked; 639} 640} 641 642let isCommutable = 1 in { 643defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 644 "mulhd", "$rT, $rA, $rB", IIC_IntMulHW, 645 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>; 646defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 647 "mulhdu", "$rT, $rA, $rB", IIC_IntMulHWU, 648 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>; 649} // isCommutable 650} 651} // Interpretation64Bit 652 653let isCompare = 1, hasSideEffects = 0 in { 654 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 655 "cmpd $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 656 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 657 "cmpld $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 658 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm64:$imm), 659 "cmpdi $crD, $rA, $imm", IIC_IntCompare>, isPPC64; 660 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm64:$src2), 661 "cmpldi $dst, $src1, $src2", 662 IIC_IntCompare>, isPPC64; 663 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 664 def CMPRB8 : X_BF3_L1_RS5_RS5<31, 192, (outs crbitrc:$BF), 665 (ins u1imm:$L, g8rc:$rA, g8rc:$rB), 666 "cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>, 667 Requires<[IsISA3_0]>; 668 def CMPEQB : X_BF3_RS5_RS5<31, 224, (outs crbitrc:$BF), 669 (ins g8rc:$rA, g8rc:$rB), "cmpeqb $BF, $rA, $rB", 670 IIC_IntCompare, []>, Requires<[IsISA3_0]>; 671} 672 673let hasSideEffects = 0 in { 674defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 675 "sld", "$rA, $rS, $rB", IIC_IntRotateD, 676 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64; 677defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 678 "srd", "$rA, $rS, $rB", IIC_IntRotateD, 679 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64; 680defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 681 "srad", "$rA, $rS, $rB", IIC_IntRotateD, 682 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64; 683 684let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 685defm CNTLZW8 : XForm_11r<31, 26, (outs g8rc:$rA), (ins g8rc:$rS), 686 "cntlzw", "$rA, $rS", IIC_IntGeneral, []>; 687defm CNTTZW8 : XForm_11r<31, 538, (outs g8rc:$rA), (ins g8rc:$rS), 688 "cnttzw", "$rA, $rS", IIC_IntGeneral, []>, 689 Requires<[IsISA3_0]>; 690 691defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS), 692 "extsb", "$rA, $rS", IIC_IntSimple, 693 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>; 694defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS), 695 "extsh", "$rA, $rS", IIC_IntSimple, 696 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>; 697 698defm SLW8 : XForm_6r<31, 24, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 699 "slw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 700defm SRW8 : XForm_6r<31, 536, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 701 "srw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 702} // Interpretation64Bit 703 704// For fast-isel: 705let isCodeGenOnly = 1 in { 706def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS), 707 "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64; 708def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS), 709 "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64; 710} // isCodeGenOnly for fast-isel 711 712defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS), 713 "extsw", "$rA, $rS", IIC_IntSimple, 714 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64; 715let Interpretation64Bit = 1, isCodeGenOnly = 1 in 716defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS), 717 "extsw", "$rA, $rS", IIC_IntSimple, 718 [(set i64:$rA, (sext i32:$rS))]>, isPPC64; 719let isCodeGenOnly = 1 in 720def EXTSW_32 : XForm_11<31, 986, (outs gprc:$rA), (ins gprc:$rS), 721 "extsw $rA, $rS", IIC_IntSimple, 722 []>, isPPC64; 723 724defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 725 "sradi", "$rA, $rS, $SH", IIC_IntRotateDI, 726 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64; 727 728let Interpretation64Bit = 1, isCodeGenOnly = 1 in 729defm EXTSWSLI_32_64 : XSForm_1r<31, 445, (outs g8rc:$rA), 730 (ins gprc:$rS, u6imm:$SH), 731 "extswsli", "$rA, $rS, $SH", IIC_IntRotateDI, 732 [(set i64:$rA, 733 (PPCextswsli i32:$rS, (i32 imm:$SH)))]>, 734 isPPC64, Requires<[IsISA3_0]>; 735 736defm EXTSWSLI : XSForm_1rc<31, 445, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 737 "extswsli", "$rA, $rS, $SH", IIC_IntRotateDI, 738 []>, isPPC64, Requires<[IsISA3_0]>; 739 740// For fast-isel: 741let isCodeGenOnly = 1, Defs = [CARRY] in 742def SRADI_32 : XSForm_1<31, 413, (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH), 743 "sradi $rA, $rS, $SH", IIC_IntRotateDI, []>, isPPC64; 744 745defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS), 746 "cntlzd", "$rA, $rS", IIC_IntGeneral, 747 [(set i64:$rA, (ctlz i64:$rS))]>; 748defm CNTTZD : XForm_11r<31, 570, (outs g8rc:$rA), (ins g8rc:$rS), 749 "cnttzd", "$rA, $rS", IIC_IntGeneral, 750 [(set i64:$rA, (cttz i64:$rS))]>, Requires<[IsISA3_0]>; 751def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS), 752 "popcntd $rA, $rS", IIC_IntGeneral, 753 [(set i64:$rA, (ctpop i64:$rS))]>; 754def BPERMD : XForm_6<31, 252, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 755 "bpermd $rA, $rS, $rB", IIC_IntGeneral, 756 [(set i64:$rA, (int_ppc_bpermd g8rc:$rS, g8rc:$rB))]>, 757 isPPC64, Requires<[HasBPERMD]>; 758 759let isCodeGenOnly = 1, isCommutable = 1 in 760def CMPB8 : XForm_6<31, 508, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 761 "cmpb $rA, $rS, $rB", IIC_IntGeneral, 762 [(set i64:$rA, (PPCcmpb i64:$rS, i64:$rB))]>; 763 764// popcntw also does a population count on the high 32 bits (storing the 765// results in the high 32-bits of the output). We'll ignore that here (which is 766// safe because we never separately use the high part of the 64-bit registers). 767def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS), 768 "popcntw $rA, $rS", IIC_IntGeneral, 769 [(set i32:$rA, (ctpop i32:$rS))]>; 770 771def POPCNTB : XForm_11<31, 122, (outs gprc:$rA), (ins gprc:$rS), 772 "popcntb $rA, $rS", IIC_IntGeneral, []>; 773 774defm DIVD : XOForm_1rcr<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 775 "divd", "$rT, $rA, $rB", IIC_IntDivD, 776 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64; 777defm DIVDU : XOForm_1rcr<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 778 "divdu", "$rT, $rA, $rB", IIC_IntDivD, 779 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64; 780defm DIVDE : XOForm_1rcr<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 781 "divde", "$rT, $rA, $rB", IIC_IntDivD, 782 [(set i64:$rT, (int_ppc_divde g8rc:$rA, g8rc:$rB))]>, 783 isPPC64, Requires<[HasExtDiv]>; 784 785let Predicates = [IsISA3_0] in { 786def MADDHD : VAForm_1a<48, (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 787 "maddhd $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; 788def MADDHDU : VAForm_1a<49, 789 (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 790 "maddhdu $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; 791def MADDLD : VAForm_1a<51, (outs gprc :$RT), (ins gprc:$RA, gprc:$RB, gprc:$RC), 792 "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, 793 [(set i32:$RT, (add_without_simm16 (mul_without_simm16 i32:$RA, i32:$RB), i32:$RC))]>, 794 isPPC64; 795def SETB : XForm_44<31, 128, (outs gprc:$RT), (ins crrc:$BFA), 796 "setb $RT, $BFA", IIC_IntGeneral>, isPPC64; 797let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 798 def MADDLD8 : VAForm_1a<51, 799 (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 800 "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, 801 [(set i64:$RT, (add_without_simm16 (mul_without_simm16 i64:$RA, i64:$RB), i64:$RC))]>, 802 isPPC64; 803 def SETB8 : XForm_44<31, 128, (outs g8rc:$RT), (ins crrc:$BFA), 804 "setb $RT, $BFA", IIC_IntGeneral>, isPPC64; 805} 806def DARN : XForm_45<31, 755, (outs g8rc:$RT), (ins i32imm:$L), 807 "darn $RT, $L", IIC_LdStLD>, isPPC64; 808def ADDPCIS : DXForm<19, 2, (outs g8rc:$RT), (ins i32imm:$D), 809 "addpcis $RT, $D", IIC_BrB, []>, isPPC64; 810def MODSD : XForm_8<31, 777, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 811 "modsd $rT, $rA, $rB", IIC_IntDivW, 812 [(set i64:$rT, (srem i64:$rA, i64:$rB))]>; 813def MODUD : XForm_8<31, 265, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 814 "modud $rT, $rA, $rB", IIC_IntDivW, 815 [(set i64:$rT, (urem i64:$rA, i64:$rB))]>; 816} 817 818defm DIVDEU : XOForm_1rcr<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 819 "divdeu", "$rT, $rA, $rB", IIC_IntDivD, 820 [(set i64:$rT, (int_ppc_divdeu g8rc:$rA, g8rc:$rB))]>, 821 isPPC64, Requires<[HasExtDiv]>; 822let isCommutable = 1 in 823defm MULLD : XOForm_1rx<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 824 "mulld", "$rT, $rA, $rB", IIC_IntMulHD, 825 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64; 826let Interpretation64Bit = 1, isCodeGenOnly = 1 in 827def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 828 "mulli $rD, $rA, $imm", IIC_IntMulLI, 829 [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>; 830} 831 832let hasSideEffects = 0 in { 833defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA), 834 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE), 835 "rldimi", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 836 []>, isPPC64, RegConstraint<"$rSi = $rA">, 837 NoEncode<"$rSi">; 838 839// Rotate instructions. 840defm RLDCL : MDSForm_1r<30, 8, 841 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 842 "rldcl", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 843 []>, isPPC64; 844defm RLDCR : MDSForm_1r<30, 9, 845 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 846 "rldcr", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 847 []>, isPPC64; 848defm RLDICL : MDForm_1r<30, 0, 849 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 850 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 851 []>, isPPC64; 852// For fast-isel: 853let isCodeGenOnly = 1 in 854def RLDICL_32_64 : MDForm_1<30, 0, 855 (outs g8rc:$rA), 856 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 857 "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 858 []>, isPPC64; 859// End fast-isel. 860let Interpretation64Bit = 1, isCodeGenOnly = 1 in 861defm RLDICL_32 : MDForm_1r<30, 0, 862 (outs gprc:$rA), 863 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 864 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 865 []>, isPPC64; 866defm RLDICR : MDForm_1r<30, 1, 867 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 868 "rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 869 []>, isPPC64; 870let isCodeGenOnly = 1 in 871def RLDICR_32 : MDForm_1<30, 1, 872 (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 873 "rldicr $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 874 []>, isPPC64; 875defm RLDIC : MDForm_1r<30, 2, 876 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 877 "rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 878 []>, isPPC64; 879 880let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 881defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA), 882 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 883 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 884 []>; 885 886defm RLWNM8 : MForm_2r<23, (outs g8rc:$rA), 887 (ins g8rc:$rS, g8rc:$rB, u5imm:$MB, u5imm:$ME), 888 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral, 889 []>; 890 891// RLWIMI can be commuted if the rotate amount is zero. 892let Interpretation64Bit = 1, isCodeGenOnly = 1 in 893defm RLWIMI8 : MForm_2r<20, (outs g8rc:$rA), 894 (ins g8rc:$rSi, g8rc:$rS, u5imm:$SH, u5imm:$MB, 895 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", 896 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 897 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; 898 899let isSelect = 1 in 900def ISEL8 : AForm_4<31, 15, 901 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond), 902 "isel $rT, $rA, $rB, $cond", IIC_IntISEL, 903 []>; 904} // Interpretation64Bit 905} // hasSideEffects = 0 906} // End FXU Operations. 907 908 909//===----------------------------------------------------------------------===// 910// Load/Store instructions. 911// 912 913 914// Sign extending loads. 915let PPC970_Unit = 2 in { 916let Interpretation64Bit = 1, isCodeGenOnly = 1 in 917def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src), 918 "lha $rD, $src", IIC_LdStLHA, 919 [(set i64:$rD, (sextloadi16 iaddr:$src))]>, 920 PPC970_DGroup_Cracked; 921def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src), 922 "lwa $rD, $src", IIC_LdStLWA, 923 [(set i64:$rD, 924 (aligned4sextloadi32 iaddrX4:$src))]>, isPPC64, 925 PPC970_DGroup_Cracked; 926let Interpretation64Bit = 1, isCodeGenOnly = 1 in 927def LHAX8: XForm_1_memOp<31, 343, (outs g8rc:$rD), (ins memrr:$src), 928 "lhax $rD, $src", IIC_LdStLHA, 929 [(set i64:$rD, (sextloadi16 xaddr:$src))]>, 930 PPC970_DGroup_Cracked; 931def LWAX : XForm_1_memOp<31, 341, (outs g8rc:$rD), (ins memrr:$src), 932 "lwax $rD, $src", IIC_LdStLHA, 933 [(set i64:$rD, (sextloadi32 xaddrX4:$src))]>, isPPC64, 934 PPC970_DGroup_Cracked; 935// For fast-isel: 936let isCodeGenOnly = 1, mayLoad = 1 in { 937def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src), 938 "lwa $rD, $src", IIC_LdStLWA, []>, isPPC64, 939 PPC970_DGroup_Cracked; 940def LWAX_32 : XForm_1_memOp<31, 341, (outs gprc:$rD), (ins memrr:$src), 941 "lwax $rD, $src", IIC_LdStLHA, []>, isPPC64, 942 PPC970_DGroup_Cracked; 943} // end fast-isel isCodeGenOnly 944 945// Update forms. 946let mayLoad = 1, hasSideEffects = 0 in { 947let Interpretation64Bit = 1, isCodeGenOnly = 1 in 948def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 949 (ins memri:$addr), 950 "lhau $rD, $addr", IIC_LdStLHAU, 951 []>, RegConstraint<"$addr.reg = $ea_result">, 952 NoEncode<"$ea_result">; 953// NO LWAU! 954 955let Interpretation64Bit = 1, isCodeGenOnly = 1 in 956def LHAUX8 : XForm_1_memOp<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 957 (ins memrr:$addr), 958 "lhaux $rD, $addr", IIC_LdStLHAUX, 959 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 960 NoEncode<"$ea_result">; 961def LWAUX : XForm_1_memOp<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 962 (ins memrr:$addr), 963 "lwaux $rD, $addr", IIC_LdStLHAUX, 964 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 965 NoEncode<"$ea_result">, isPPC64; 966} 967} 968 969let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 970// Zero extending loads. 971let PPC970_Unit = 2 in { 972def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src), 973 "lbz $rD, $src", IIC_LdStLoad, 974 [(set i64:$rD, (zextloadi8 iaddr:$src))]>; 975def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src), 976 "lhz $rD, $src", IIC_LdStLoad, 977 [(set i64:$rD, (zextloadi16 iaddr:$src))]>; 978def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src), 979 "lwz $rD, $src", IIC_LdStLoad, 980 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; 981 982def LBZX8 : XForm_1_memOp<31, 87, (outs g8rc:$rD), (ins memrr:$src), 983 "lbzx $rD, $src", IIC_LdStLoad, 984 [(set i64:$rD, (zextloadi8 xaddr:$src))]>; 985def LHZX8 : XForm_1_memOp<31, 279, (outs g8rc:$rD), (ins memrr:$src), 986 "lhzx $rD, $src", IIC_LdStLoad, 987 [(set i64:$rD, (zextloadi16 xaddr:$src))]>; 988def LWZX8 : XForm_1_memOp<31, 23, (outs g8rc:$rD), (ins memrr:$src), 989 "lwzx $rD, $src", IIC_LdStLoad, 990 [(set i64:$rD, (zextloadi32 xaddr:$src))]>; 991 992 993// Update forms. 994let mayLoad = 1, hasSideEffects = 0 in { 995def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 996 (ins memri:$addr), 997 "lbzu $rD, $addr", IIC_LdStLoadUpd, 998 []>, RegConstraint<"$addr.reg = $ea_result">, 999 NoEncode<"$ea_result">; 1000def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1001 (ins memri:$addr), 1002 "lhzu $rD, $addr", IIC_LdStLoadUpd, 1003 []>, RegConstraint<"$addr.reg = $ea_result">, 1004 NoEncode<"$ea_result">; 1005def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1006 (ins memri:$addr), 1007 "lwzu $rD, $addr", IIC_LdStLoadUpd, 1008 []>, RegConstraint<"$addr.reg = $ea_result">, 1009 NoEncode<"$ea_result">; 1010 1011def LBZUX8 : XForm_1_memOp<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1012 (ins memrr:$addr), 1013 "lbzux $rD, $addr", IIC_LdStLoadUpdX, 1014 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1015 NoEncode<"$ea_result">; 1016def LHZUX8 : XForm_1_memOp<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1017 (ins memrr:$addr), 1018 "lhzux $rD, $addr", IIC_LdStLoadUpdX, 1019 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1020 NoEncode<"$ea_result">; 1021def LWZUX8 : XForm_1_memOp<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1022 (ins memrr:$addr), 1023 "lwzux $rD, $addr", IIC_LdStLoadUpdX, 1024 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1025 NoEncode<"$ea_result">; 1026} 1027} 1028} // Interpretation64Bit 1029 1030 1031// Full 8-byte loads. 1032let PPC970_Unit = 2 in { 1033def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src), 1034 "ld $rD, $src", IIC_LdStLD, 1035 [(set i64:$rD, (aligned4load iaddrX4:$src))]>, isPPC64; 1036// The following four definitions are selected for small code model only. 1037// Otherwise, we need to create two instructions to form a 32-bit offset, 1038// so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). 1039def LDtoc: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1040 "#LDtoc", 1041 [(set i64:$rD, 1042 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64; 1043def LDtocJTI: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1044 "#LDtocJTI", 1045 [(set i64:$rD, 1046 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64; 1047def LDtocCPT: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1048 "#LDtocCPT", 1049 [(set i64:$rD, 1050 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64; 1051def LDtocBA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1052 "#LDtocCPT", 1053 [(set i64:$rD, 1054 (PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64; 1055 1056def LDX : XForm_1_memOp<31, 21, (outs g8rc:$rD), (ins memrr:$src), 1057 "ldx $rD, $src", IIC_LdStLD, 1058 [(set i64:$rD, (load xaddrX4:$src))]>, isPPC64; 1059def LDBRX : XForm_1_memOp<31, 532, (outs g8rc:$rD), (ins memrr:$src), 1060 "ldbrx $rD, $src", IIC_LdStLoad, 1061 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64; 1062 1063let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in { 1064def LHBRX8 : XForm_1_memOp<31, 790, (outs g8rc:$rD), (ins memrr:$src), 1065 "lhbrx $rD, $src", IIC_LdStLoad, []>; 1066def LWBRX8 : XForm_1_memOp<31, 534, (outs g8rc:$rD), (ins memrr:$src), 1067 "lwbrx $rD, $src", IIC_LdStLoad, []>; 1068} 1069 1070let mayLoad = 1, hasSideEffects = 0 in { 1071def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1072 (ins memrix:$addr), 1073 "ldu $rD, $addr", IIC_LdStLDU, 1074 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 1075 NoEncode<"$ea_result">; 1076 1077def LDUX : XForm_1_memOp<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1078 (ins memrr:$addr), 1079 "ldux $rD, $addr", IIC_LdStLDUX, 1080 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1081 NoEncode<"$ea_result">, isPPC64; 1082 1083def LDMX : XForm_1<31, 309, (outs g8rc:$rD), (ins memrr:$src), 1084 "ldmx $rD, $src", IIC_LdStLD, []>, isPPC64, 1085 Requires<[IsISA3_0]>; 1086} 1087} 1088 1089// Support for medium and large code model. 1090let hasSideEffects = 0 in { 1091let isReMaterializable = 1 in { 1092def ADDIStocHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 1093 "#ADDIStocHA", []>, isPPC64; 1094def ADDItocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 1095 "#ADDItocL", []>, isPPC64; 1096} 1097let mayLoad = 1 in 1098def LDtocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg), 1099 "#LDtocL", []>, isPPC64; 1100} 1101 1102// Support for thread-local storage. 1103def ADDISgotTprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1104 "#ADDISgotTprelHA", 1105 [(set i64:$rD, 1106 (PPCaddisGotTprelHA i64:$reg, 1107 tglobaltlsaddr:$disp))]>, 1108 isPPC64; 1109def LDgotTprelL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg), 1110 "#LDgotTprelL", 1111 [(set i64:$rD, 1112 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>, 1113 isPPC64; 1114 1115let Defs = [CR7], Itinerary = IIC_LdStSync in 1116def CFENCE8 : PPCPostRAExpPseudo<(outs), (ins g8rc:$cr), "#CFENCE8", []>; 1117 1118def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g), 1119 (ADD8TLS $in, tglobaltlsaddr:$g)>; 1120def ADDIStlsgdHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1121 "#ADDIStlsgdHA", 1122 [(set i64:$rD, 1123 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>, 1124 isPPC64; 1125def ADDItlsgdL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1126 "#ADDItlsgdL", 1127 [(set i64:$rD, 1128 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>, 1129 isPPC64; 1130// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 1131// explicitly defined when this op is created, so not mentioned here. 1132// This is lowered to BL8_NOP_TLS by the assembly printer, so the size must be 1133// correct because the branch select pass is relying on it. 1134let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, Size = 8, 1135 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1136def GETtlsADDR : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 1137 "#GETtlsADDR", 1138 [(set i64:$rD, 1139 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>, 1140 isPPC64; 1141// Combined op for ADDItlsgdL and GETtlsADDR, late expanded. X3 and LR8 1142// are true defines while the rest of the Defs are clobbers. 1143let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1144 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1145 in 1146def ADDItlsgdLADDR : PPCEmitTimePseudo<(outs g8rc:$rD), 1147 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 1148 "#ADDItlsgdLADDR", 1149 [(set i64:$rD, 1150 (PPCaddiTlsgdLAddr i64:$reg, 1151 tglobaltlsaddr:$disp, 1152 tglobaltlsaddr:$sym))]>, 1153 isPPC64; 1154def ADDIStlsldHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1155 "#ADDIStlsldHA", 1156 [(set i64:$rD, 1157 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>, 1158 isPPC64; 1159def ADDItlsldL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1160 "#ADDItlsldL", 1161 [(set i64:$rD, 1162 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>, 1163 isPPC64; 1164// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 1165// explicitly defined when this op is created, so not mentioned here. 1166let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1167 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1168def GETtlsldADDR : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 1169 "#GETtlsldADDR", 1170 [(set i64:$rD, 1171 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>, 1172 isPPC64; 1173// Combined op for ADDItlsldL and GETtlsADDR, late expanded. X3 and LR8 1174// are true defines, while the rest of the Defs are clobbers. 1175let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1176 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1177 in 1178def ADDItlsldLADDR : PPCEmitTimePseudo<(outs g8rc:$rD), 1179 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 1180 "#ADDItlsldLADDR", 1181 [(set i64:$rD, 1182 (PPCaddiTlsldLAddr i64:$reg, 1183 tglobaltlsaddr:$disp, 1184 tglobaltlsaddr:$sym))]>, 1185 isPPC64; 1186def ADDISdtprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1187 "#ADDISdtprelHA", 1188 [(set i64:$rD, 1189 (PPCaddisDtprelHA i64:$reg, 1190 tglobaltlsaddr:$disp))]>, 1191 isPPC64; 1192def ADDIdtprelL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1193 "#ADDIdtprelL", 1194 [(set i64:$rD, 1195 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>, 1196 isPPC64; 1197 1198let PPC970_Unit = 2 in { 1199let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1200// Truncating stores. 1201def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src), 1202 "stb $rS, $src", IIC_LdStStore, 1203 [(truncstorei8 i64:$rS, iaddr:$src)]>; 1204def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src), 1205 "sth $rS, $src", IIC_LdStStore, 1206 [(truncstorei16 i64:$rS, iaddr:$src)]>; 1207def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src), 1208 "stw $rS, $src", IIC_LdStStore, 1209 [(truncstorei32 i64:$rS, iaddr:$src)]>; 1210def STBX8 : XForm_8_memOp<31, 215, (outs), (ins g8rc:$rS, memrr:$dst), 1211 "stbx $rS, $dst", IIC_LdStStore, 1212 [(truncstorei8 i64:$rS, xaddr:$dst)]>, 1213 PPC970_DGroup_Cracked; 1214def STHX8 : XForm_8_memOp<31, 407, (outs), (ins g8rc:$rS, memrr:$dst), 1215 "sthx $rS, $dst", IIC_LdStStore, 1216 [(truncstorei16 i64:$rS, xaddr:$dst)]>, 1217 PPC970_DGroup_Cracked; 1218def STWX8 : XForm_8_memOp<31, 151, (outs), (ins g8rc:$rS, memrr:$dst), 1219 "stwx $rS, $dst", IIC_LdStStore, 1220 [(truncstorei32 i64:$rS, xaddr:$dst)]>, 1221 PPC970_DGroup_Cracked; 1222} // Interpretation64Bit 1223 1224// Normal 8-byte stores. 1225def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst), 1226 "std $rS, $dst", IIC_LdStSTD, 1227 [(aligned4store i64:$rS, iaddrX4:$dst)]>, isPPC64; 1228def STDX : XForm_8_memOp<31, 149, (outs), (ins g8rc:$rS, memrr:$dst), 1229 "stdx $rS, $dst", IIC_LdStSTD, 1230 [(store i64:$rS, xaddrX4:$dst)]>, isPPC64, 1231 PPC970_DGroup_Cracked; 1232def STDBRX: XForm_8_memOp<31, 660, (outs), (ins g8rc:$rS, memrr:$dst), 1233 "stdbrx $rS, $dst", IIC_LdStStore, 1234 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64, 1235 PPC970_DGroup_Cracked; 1236} 1237 1238// Stores with Update (pre-inc). 1239let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 1240let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1241def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1242 "stbu $rS, $dst", IIC_LdStSTU, []>, 1243 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1244def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1245 "sthu $rS, $dst", IIC_LdStSTU, []>, 1246 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1247def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1248 "stwu $rS, $dst", IIC_LdStSTU, []>, 1249 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1250 1251def STBUX8: XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res), 1252 (ins g8rc:$rS, memrr:$dst), 1253 "stbux $rS, $dst", IIC_LdStSTUX, []>, 1254 RegConstraint<"$dst.ptrreg = $ea_res">, 1255 NoEncode<"$ea_res">, 1256 PPC970_DGroup_Cracked; 1257def STHUX8: XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res), 1258 (ins g8rc:$rS, memrr:$dst), 1259 "sthux $rS, $dst", IIC_LdStSTUX, []>, 1260 RegConstraint<"$dst.ptrreg = $ea_res">, 1261 NoEncode<"$ea_res">, 1262 PPC970_DGroup_Cracked; 1263def STWUX8: XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res), 1264 (ins g8rc:$rS, memrr:$dst), 1265 "stwux $rS, $dst", IIC_LdStSTUX, []>, 1266 RegConstraint<"$dst.ptrreg = $ea_res">, 1267 NoEncode<"$ea_res">, 1268 PPC970_DGroup_Cracked; 1269} // Interpretation64Bit 1270 1271def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), 1272 (ins g8rc:$rS, memrix:$dst), 1273 "stdu $rS, $dst", IIC_LdStSTU, []>, 1274 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">, 1275 isPPC64; 1276 1277def STDUX : XForm_8_memOp<31, 181, (outs ptr_rc_nor0:$ea_res), 1278 (ins g8rc:$rS, memrr:$dst), 1279 "stdux $rS, $dst", IIC_LdStSTUX, []>, 1280 RegConstraint<"$dst.ptrreg = $ea_res">, 1281 NoEncode<"$ea_res">, 1282 PPC970_DGroup_Cracked, isPPC64; 1283} 1284 1285// Patterns to match the pre-inc stores. We can't put the patterns on 1286// the instruction definitions directly as ISel wants the address base 1287// and offset to be separate operands, not a single complex operand. 1288def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1289 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1290def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1291 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1292def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1293 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1294def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1295 (STDU $rS, iaddroff:$ptroff, $ptrreg)>; 1296 1297def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1298 (STBUX8 $rS, $ptrreg, $ptroff)>; 1299def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1300 (STHUX8 $rS, $ptrreg, $ptroff)>; 1301def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1302 (STWUX8 $rS, $ptrreg, $ptroff)>; 1303def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1304 (STDUX $rS, $ptrreg, $ptroff)>; 1305 1306 1307//===----------------------------------------------------------------------===// 1308// Floating point instructions. 1309// 1310 1311 1312let PPC970_Unit = 3, hasSideEffects = 0, 1313 Uses = [RM] in { // FPU Operations. 1314defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB), 1315 "fcfid", "$frD, $frB", IIC_FPGeneral, 1316 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64; 1317defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB), 1318 "fctid", "$frD, $frB", IIC_FPGeneral, 1319 []>, isPPC64; 1320defm FCTIDU : XForm_26r<63, 942, (outs f8rc:$frD), (ins f8rc:$frB), 1321 "fctidu", "$frD, $frB", IIC_FPGeneral, 1322 []>, isPPC64; 1323defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB), 1324 "fctidz", "$frD, $frB", IIC_FPGeneral, 1325 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64; 1326 1327defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB), 1328 "fcfidu", "$frD, $frB", IIC_FPGeneral, 1329 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64; 1330defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB), 1331 "fcfids", "$frD, $frB", IIC_FPGeneral, 1332 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64; 1333defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB), 1334 "fcfidus", "$frD, $frB", IIC_FPGeneral, 1335 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64; 1336defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB), 1337 "fctiduz", "$frD, $frB", IIC_FPGeneral, 1338 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64; 1339defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB), 1340 "fctiwuz", "$frD, $frB", IIC_FPGeneral, 1341 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64; 1342} 1343 1344 1345//===----------------------------------------------------------------------===// 1346// Instruction Patterns 1347// 1348 1349// Extensions and truncates to/from 32-bit regs. 1350def : Pat<(i64 (zext i32:$in)), 1351 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32), 1352 0, 32)>; 1353def : Pat<(i64 (anyext i32:$in)), 1354 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>; 1355def : Pat<(i32 (trunc i64:$in)), 1356 (EXTRACT_SUBREG $in, sub_32)>; 1357 1358// Implement the 'not' operation with the NOR instruction. 1359// (we could use the default xori pattern, but nor has lower latency on some 1360// cores (such as the A2)). 1361def i64not : OutPatFrag<(ops node:$in), 1362 (NOR8 $in, $in)>; 1363def : Pat<(not i64:$in), 1364 (i64not $in)>; 1365 1366// Extending loads with i64 targets. 1367def : Pat<(zextloadi1 iaddr:$src), 1368 (LBZ8 iaddr:$src)>; 1369def : Pat<(zextloadi1 xaddr:$src), 1370 (LBZX8 xaddr:$src)>; 1371def : Pat<(extloadi1 iaddr:$src), 1372 (LBZ8 iaddr:$src)>; 1373def : Pat<(extloadi1 xaddr:$src), 1374 (LBZX8 xaddr:$src)>; 1375def : Pat<(extloadi8 iaddr:$src), 1376 (LBZ8 iaddr:$src)>; 1377def : Pat<(extloadi8 xaddr:$src), 1378 (LBZX8 xaddr:$src)>; 1379def : Pat<(extloadi16 iaddr:$src), 1380 (LHZ8 iaddr:$src)>; 1381def : Pat<(extloadi16 xaddr:$src), 1382 (LHZX8 xaddr:$src)>; 1383def : Pat<(extloadi32 iaddr:$src), 1384 (LWZ8 iaddr:$src)>; 1385def : Pat<(extloadi32 xaddr:$src), 1386 (LWZX8 xaddr:$src)>; 1387 1388// Standard shifts. These are represented separately from the real shifts above 1389// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 1390// amounts. 1391def : Pat<(sra i64:$rS, i32:$rB), 1392 (SRAD $rS, $rB)>; 1393def : Pat<(srl i64:$rS, i32:$rB), 1394 (SRD $rS, $rB)>; 1395def : Pat<(shl i64:$rS, i32:$rB), 1396 (SLD $rS, $rB)>; 1397 1398// SUBFIC 1399def : Pat<(sub imm64SExt16:$imm, i64:$in), 1400 (SUBFIC8 $in, imm:$imm)>; 1401 1402// SHL/SRL 1403def : Pat<(shl i64:$in, (i32 imm:$imm)), 1404 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>; 1405def : Pat<(srl i64:$in, (i32 imm:$imm)), 1406 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>; 1407 1408// ROTL 1409def : Pat<(rotl i64:$in, i32:$sh), 1410 (RLDCL $in, $sh, 0)>; 1411def : Pat<(rotl i64:$in, (i32 imm:$imm)), 1412 (RLDICL $in, imm:$imm, 0)>; 1413 1414// Hi and Lo for Darwin Global Addresses. 1415def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 1416def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 1417def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 1418def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 1419def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 1420def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 1421def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 1422def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 1423def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in), 1424 (ADDIS8 $in, tglobaltlsaddr:$g)>; 1425def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in), 1426 (ADDI8 $in, tglobaltlsaddr:$g)>; 1427def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)), 1428 (ADDIS8 $in, tglobaladdr:$g)>; 1429def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)), 1430 (ADDIS8 $in, tconstpool:$g)>; 1431def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)), 1432 (ADDIS8 $in, tjumptable:$g)>; 1433def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)), 1434 (ADDIS8 $in, tblockaddress:$g)>; 1435 1436// Patterns to match r+r indexed loads and stores for 1437// addresses without at least 4-byte alignment. 1438def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)), 1439 (LWAX xoaddr:$src)>; 1440def : Pat<(i64 (unaligned4load xoaddr:$src)), 1441 (LDX xoaddr:$src)>; 1442def : Pat<(unaligned4store i64:$rS, xoaddr:$dst), 1443 (STDX $rS, xoaddr:$dst)>; 1444 1445// 64-bits atomic loads and stores 1446def : Pat<(atomic_load_64 iaddrX4:$src), (LD memrix:$src)>; 1447def : Pat<(atomic_load_64 xaddrX4:$src), (LDX memrr:$src)>; 1448 1449def : Pat<(atomic_store_64 iaddrX4:$ptr, i64:$val), (STD g8rc:$val, memrix:$ptr)>; 1450def : Pat<(atomic_store_64 xaddrX4:$ptr, i64:$val), (STDX g8rc:$val, memrr:$ptr)>; 1451 1452let Predicates = [IsISA3_0] in { 1453 1454class X_L1_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty, 1455 InstrItinClass itin, list<dag> pattern> 1456 : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L), 1457 !strconcat(opc, " $rA, $rB, $L"), itin, pattern>; 1458 1459let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1460def CP_COPY8 : X_L1_RA5_RB5<31, 774, "copy" , g8rc, IIC_LdStCOPY, []>; 1461def CP_PASTE8 : X_L1_RA5_RB5<31, 902, "paste" , g8rc, IIC_LdStPASTE, []>; 1462def CP_PASTE8o : X_L1_RA5_RB5<31, 902, "paste.", g8rc, IIC_LdStPASTE, []>,isDOT; 1463} 1464 1465// SLB Invalidate Entry Global 1466def SLBIEG : XForm_26<31, 466, (outs), (ins gprc:$RS, gprc:$RB), 1467 "slbieg $RS, $RB", IIC_SprSLBIEG, []>; 1468// SLB Synchronize 1469def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>; 1470 1471} // IsISA3_0 1472