1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt -instcombine -S < %s | FileCheck %s
3
4target datalayout = "e-m:e-i64:64-n8:16:32:64"
5
6declare i32 @llvm.cttz.i32(i32, i1) nounwind readnone
7declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone
8declare i32 @llvm.ctpop.i32(i32) nounwind readnone
9declare <2 x i8> @llvm.cttz.v2i8(<2 x i8>, i1) nounwind readnone
10declare <2 x i8> @llvm.ctlz.v2i8(<2 x i8>, i1) nounwind readnone
11declare <2 x i8> @llvm.ctpop.v2i8(<2 x i8>) nounwind readnone
12
13define i32 @lshr_ctlz_zero_is_not_undef(i32 %x) {
14; CHECK-LABEL: @lshr_ctlz_zero_is_not_undef(
15; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i32 %x, 0
16; CHECK-NEXT:    [[SH:%.*]] = zext i1 [[TMP1]] to i32
17; CHECK-NEXT:    ret i32 [[SH]]
18;
19  %ct = call i32 @llvm.ctlz.i32(i32 %x, i1 false)
20  %sh = lshr i32 %ct, 5
21  ret i32 %sh
22}
23
24define i32 @lshr_cttz_zero_is_not_undef(i32 %x) {
25; CHECK-LABEL: @lshr_cttz_zero_is_not_undef(
26; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i32 %x, 0
27; CHECK-NEXT:    [[SH:%.*]] = zext i1 [[TMP1]] to i32
28; CHECK-NEXT:    ret i32 [[SH]]
29;
30  %ct = call i32 @llvm.cttz.i32(i32 %x, i1 false)
31  %sh = lshr i32 %ct, 5
32  ret i32 %sh
33}
34
35define i32 @lshr_ctpop(i32 %x) {
36; CHECK-LABEL: @lshr_ctpop(
37; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i32 %x, -1
38; CHECK-NEXT:    [[SH:%.*]] = zext i1 [[TMP1]] to i32
39; CHECK-NEXT:    ret i32 [[SH]]
40;
41  %ct = call i32 @llvm.ctpop.i32(i32 %x)
42  %sh = lshr i32 %ct, 5
43  ret i32 %sh
44}
45
46define <2 x i8> @lshr_ctlz_zero_is_not_undef_splat_vec(<2 x i8> %x) {
47; CHECK-LABEL: @lshr_ctlz_zero_is_not_undef_splat_vec(
48; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq <2 x i8> %x, zeroinitializer
49; CHECK-NEXT:    [[SH:%.*]] = zext <2 x i1> [[TMP1]] to <2 x i8>
50; CHECK-NEXT:    ret <2 x i8> [[SH]]
51;
52  %ct = call <2 x i8> @llvm.ctlz.v2i8(<2 x i8> %x, i1 false)
53  %sh = lshr <2 x i8> %ct, <i8 3, i8 3>
54  ret <2 x i8> %sh
55}
56
57define <2 x i8> @lshr_cttz_zero_is_not_undef_splat_vec(<2 x i8> %x) {
58; CHECK-LABEL: @lshr_cttz_zero_is_not_undef_splat_vec(
59; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq <2 x i8> %x, zeroinitializer
60; CHECK-NEXT:    [[SH:%.*]] = zext <2 x i1> [[TMP1]] to <2 x i8>
61; CHECK-NEXT:    ret <2 x i8> [[SH]]
62;
63  %ct = call <2 x i8> @llvm.cttz.v2i8(<2 x i8> %x, i1 false)
64  %sh = lshr <2 x i8> %ct, <i8 3, i8 3>
65  ret <2 x i8> %sh
66}
67
68define <2 x i8> @lshr_ctpop_splat_vec(<2 x i8> %x) {
69; CHECK-LABEL: @lshr_ctpop_splat_vec(
70; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq <2 x i8> %x, <i8 -1, i8 -1>
71; CHECK-NEXT:    [[SH:%.*]] = zext <2 x i1> [[TMP1]] to <2 x i8>
72; CHECK-NEXT:    ret <2 x i8> [[SH]]
73;
74  %ct = call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> %x)
75  %sh = lshr <2 x i8> %ct, <i8 3, i8 3>
76  ret <2 x i8> %sh
77}
78
79define i8 @lshr_exact(i8 %x) {
80; CHECK-LABEL: @lshr_exact(
81; CHECK-NEXT:    [[SHL:%.*]] = shl i8 %x, 2
82; CHECK-NEXT:    [[ADD:%.*]] = add i8 [[SHL]], 4
83; CHECK-NEXT:    [[LSHR:%.*]] = lshr exact i8 [[ADD]], 2
84; CHECK-NEXT:    ret i8 [[LSHR]]
85;
86  %shl = shl i8 %x, 2
87  %add = add i8 %shl, 4
88  %lshr = lshr i8 %add, 2
89  ret i8 %lshr
90}
91
92define <2 x i8> @lshr_exact_splat_vec(<2 x i8> %x) {
93; CHECK-LABEL: @lshr_exact_splat_vec(
94; CHECK-NEXT:    [[SHL:%.*]] = shl <2 x i8> %x, <i8 2, i8 2>
95; CHECK-NEXT:    [[ADD:%.*]] = add <2 x i8> [[SHL]], <i8 4, i8 4>
96; CHECK-NEXT:    [[LSHR:%.*]] = lshr exact <2 x i8> [[ADD]], <i8 2, i8 2>
97; CHECK-NEXT:    ret <2 x i8> [[LSHR]]
98;
99  %shl = shl <2 x i8> %x, <i8 2, i8 2>
100  %add = add <2 x i8> %shl, <i8 4, i8 4>
101  %lshr = lshr <2 x i8> %add, <i8 2, i8 2>
102  ret <2 x i8> %lshr
103}
104
105define i16 @bool_zext(i1 %x) {
106; CHECK-LABEL: @bool_zext(
107; CHECK-NEXT:    [[HIBIT:%.*]] = zext i1 %x to i16
108; CHECK-NEXT:    ret i16 [[HIBIT]]
109;
110  %sext = sext i1 %x to i16
111  %hibit = lshr i16 %sext, 15
112  ret i16 %hibit
113}
114
115define <2 x i8> @bool_zext_splat(<2 x i1> %x) {
116; CHECK-LABEL: @bool_zext_splat(
117; CHECK-NEXT:    [[HIBIT:%.*]] = zext <2 x i1> %x to <2 x i8>
118; CHECK-NEXT:    ret <2 x i8> [[HIBIT]]
119;
120  %sext = sext <2 x i1> %x to <2 x i8>
121  %hibit = lshr <2 x i8> %sext, <i8 7, i8 7>
122  ret <2 x i8> %hibit
123}
124
125define i32 @smear_sign_and_widen(i8 %x) {
126; CHECK-LABEL: @smear_sign_and_widen(
127; CHECK-NEXT:    [[TMP1:%.*]] = ashr i8 %x, 7
128; CHECK-NEXT:    [[HIBIT:%.*]] = zext i8 [[TMP1]] to i32
129; CHECK-NEXT:    ret i32 [[HIBIT]]
130;
131  %sext = sext i8 %x to i32
132  %hibit = lshr i32 %sext, 24
133  ret i32 %hibit
134}
135
136define i16 @smear_sign_and_widen_should_not_change_type(i4 %x) {
137; CHECK-LABEL: @smear_sign_and_widen_should_not_change_type(
138; CHECK-NEXT:    [[SEXT:%.*]] = sext i4 %x to i16
139; CHECK-NEXT:    [[HIBIT:%.*]] = lshr i16 [[SEXT]], 12
140; CHECK-NEXT:    ret i16 [[HIBIT]]
141;
142  %sext = sext i4 %x to i16
143  %hibit = lshr i16 %sext, 12
144  ret i16 %hibit
145}
146
147define <2 x i8> @smear_sign_and_widen_splat(<2 x i6> %x) {
148; CHECK-LABEL: @smear_sign_and_widen_splat(
149; CHECK-NEXT:    [[TMP1:%.*]] = ashr <2 x i6> %x, <i6 2, i6 2>
150; CHECK-NEXT:    [[HIBIT:%.*]] = zext <2 x i6> [[TMP1]] to <2 x i8>
151; CHECK-NEXT:    ret <2 x i8> [[HIBIT]]
152;
153  %sext = sext <2 x i6> %x to <2 x i8>
154  %hibit = lshr <2 x i8> %sext, <i8 2, i8 2>
155  ret <2 x i8> %hibit
156}
157
158define i18 @fake_sext(i3 %x) {
159; CHECK-LABEL: @fake_sext(
160; CHECK-NEXT:    [[TMP1:%.*]] = lshr i3 %x, 2
161; CHECK-NEXT:    [[SH:%.*]] = zext i3 [[TMP1]] to i18
162; CHECK-NEXT:    ret i18 [[SH]]
163;
164  %sext = sext i3 %x to i18
165  %sh = lshr i18 %sext, 17
166  ret i18 %sh
167}
168
169; Avoid the transform if it would change the shift from a legal to illegal type.
170
171define i32 @fake_sext_but_should_not_change_type(i3 %x) {
172; CHECK-LABEL: @fake_sext_but_should_not_change_type(
173; CHECK-NEXT:    [[SEXT:%.*]] = sext i3 %x to i32
174; CHECK-NEXT:    [[SH:%.*]] = lshr i32 [[SEXT]], 31
175; CHECK-NEXT:    ret i32 [[SH]]
176;
177  %sext = sext i3 %x to i32
178  %sh = lshr i32 %sext, 31
179  ret i32 %sh
180}
181
182define <2 x i8> @fake_sext_splat(<2 x i3> %x) {
183; CHECK-LABEL: @fake_sext_splat(
184; CHECK-NEXT:    [[TMP1:%.*]] = lshr <2 x i3> %x, <i3 2, i3 2>
185; CHECK-NEXT:    [[SH:%.*]] = zext <2 x i3> [[TMP1]] to <2 x i8>
186; CHECK-NEXT:    ret <2 x i8> [[SH]]
187;
188  %sext = sext <2 x i3> %x to <2 x i8>
189  %sh = lshr <2 x i8> %sext, <i8 7, i8 7>
190  ret <2 x i8> %sh
191}
192
193; Use a narrow shift: lshr (zext iM X to iN), C --> zext (lshr X, C) to iN
194
195define <2 x i32> @narrow_lshr_constant(<2 x i8> %x, <2 x i8> %y) {
196; CHECK-LABEL: @narrow_lshr_constant(
197; CHECK-NEXT:    [[TMP1:%.*]] = lshr <2 x i8> %x, <i8 3, i8 3>
198; CHECK-NEXT:    [[SH:%.*]] = zext <2 x i8> [[TMP1]] to <2 x i32>
199; CHECK-NEXT:    ret <2 x i32> [[SH]]
200;
201  %zx = zext <2 x i8> %x to <2 x i32>
202  %sh = lshr <2 x i32> %zx, <i32 3, i32 3>
203  ret <2 x i32> %sh
204}
205
206