1 /* Subroutines used for code generation on IBM RS/6000.
2    Copyright (C) 1991-2013 Free Software Foundation, Inc.
3    Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
4 
5    This file is part of GCC.
6 
7    GCC is free software; you can redistribute it and/or modify it
8    under the terms of the GNU General Public License as published
9    by the Free Software Foundation; either version 3, or (at your
10    option) any later version.
11 
12    GCC is distributed in the hope that it will be useful, but WITHOUT
13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15    License for more details.
16 
17    You should have received a copy of the GNU General Public License
18    along with GCC; see the file COPYING3.  If not see
19    <http://www.gnu.org/licenses/>.  */
20 
21 #include "config.h"
22 #include "system.h"
23 #include "coretypes.h"
24 #include "tm.h"
25 #include "rtl.h"
26 #include "regs.h"
27 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-attr.h"
31 #include "flags.h"
32 #include "recog.h"
33 #include "obstack.h"
34 #include "tree.h"
35 #include "expr.h"
36 #include "optabs.h"
37 #include "except.h"
38 #include "function.h"
39 #include "output.h"
40 #include "dbxout.h"
41 #include "basic-block.h"
42 #include "diagnostic-core.h"
43 #include "toplev.h"
44 #include "ggc.h"
45 #include "hashtab.h"
46 #include "tm_p.h"
47 #include "target.h"
48 #include "target-def.h"
49 #include "common/common-target.h"
50 #include "langhooks.h"
51 #include "reload.h"
52 #include "cfgloop.h"
53 #include "sched-int.h"
54 #include "gimple.h"
55 #include "tree-flow.h"
56 #include "intl.h"
57 #include "params.h"
58 #include "tm-constrs.h"
59 #include "opts.h"
60 #include "tree-vectorizer.h"
61 #include "dumpfile.h"
62 #if TARGET_XCOFF
63 #include "xcoffout.h"  /* get declarations of xcoff_*_section_name */
64 #endif
65 #if TARGET_MACHO
66 #include "gstab.h"  /* for N_SLINE */
67 #endif
68 
69 #ifndef TARGET_NO_PROTOTYPE
70 #define TARGET_NO_PROTOTYPE 0
71 #endif
72 
73 #define min(A,B)	((A) < (B) ? (A) : (B))
74 #define max(A,B)	((A) > (B) ? (A) : (B))
75 
76 /* Structure used to define the rs6000 stack */
77 typedef struct rs6000_stack {
78   int reload_completed;		/* stack info won't change from here on */
79   int first_gp_reg_save;	/* first callee saved GP register used */
80   int first_fp_reg_save;	/* first callee saved FP register used */
81   int first_altivec_reg_save;	/* first callee saved AltiVec register used */
82   int lr_save_p;		/* true if the link reg needs to be saved */
83   int cr_save_p;		/* true if the CR reg needs to be saved */
84   unsigned int vrsave_mask;	/* mask of vec registers to save */
85   int push_p;			/* true if we need to allocate stack space */
86   int calls_p;			/* true if the function makes any calls */
87   int world_save_p;		/* true if we're saving *everything*:
88 				   r13-r31, cr, f14-f31, vrsave, v20-v31  */
89   enum rs6000_abi abi;		/* which ABI to use */
90   int gp_save_offset;		/* offset to save GP regs from initial SP */
91   int fp_save_offset;		/* offset to save FP regs from initial SP */
92   int altivec_save_offset;	/* offset to save AltiVec regs from initial SP */
93   int lr_save_offset;		/* offset to save LR from initial SP */
94   int cr_save_offset;		/* offset to save CR from initial SP */
95   int vrsave_save_offset;	/* offset to save VRSAVE from initial SP */
96   int spe_gp_save_offset;	/* offset to save spe 64-bit gprs  */
97   int varargs_save_offset;	/* offset to save the varargs registers */
98   int ehrd_offset;		/* offset to EH return data */
99   int reg_size;			/* register size (4 or 8) */
100   HOST_WIDE_INT vars_size;	/* variable save area size */
101   int parm_size;		/* outgoing parameter size */
102   int save_size;		/* save area size */
103   int fixed_size;		/* fixed size of stack frame */
104   int gp_size;			/* size of saved GP registers */
105   int fp_size;			/* size of saved FP registers */
106   int altivec_size;		/* size of saved AltiVec registers */
107   int cr_size;			/* size to hold CR if not in save_size */
108   int vrsave_size;		/* size to hold VRSAVE if not in save_size */
109   int altivec_padding_size;	/* size of altivec alignment padding if
110 				   not in save_size */
111   int spe_gp_size;		/* size of 64-bit GPR save size for SPE */
112   int spe_padding_size;
113   HOST_WIDE_INT total_size;	/* total bytes allocated for stack */
114   int spe_64bit_regs_used;
115   int savres_strategy;
116 } rs6000_stack_t;
117 
118 /* A C structure for machine-specific, per-function data.
119    This is added to the cfun structure.  */
120 typedef struct GTY(()) machine_function
121 {
122   /* Some local-dynamic symbol.  */
123   const char *some_ld_name;
124   /* Whether the instruction chain has been scanned already.  */
125   int insn_chain_scanned_p;
126   /* Flags if __builtin_return_address (n) with n >= 1 was used.  */
127   int ra_needs_full_frame;
128   /* Flags if __builtin_return_address (0) was used.  */
129   int ra_need_lr;
130   /* Cache lr_save_p after expansion of builtin_eh_return.  */
131   int lr_save_state;
132   /* Whether we need to save the TOC to the reserved stack location in the
133      function prologue.  */
134   bool save_toc_in_prologue;
135   /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
136      varargs save area.  */
137   HOST_WIDE_INT varargs_save_offset;
138   /* Temporary stack slot to use for SDmode copies.  This slot is
139      64-bits wide and is allocated early enough so that the offset
140      does not overflow the 16-bit load/store offset field.  */
141   rtx sdmode_stack_slot;
142 } machine_function;
143 
144 /* Support targetm.vectorize.builtin_mask_for_load.  */
145 static GTY(()) tree altivec_builtin_mask_for_load;
146 
147 /* Set to nonzero once AIX common-mode calls have been defined.  */
148 static GTY(()) int common_mode_defined;
149 
150 /* Label number of label created for -mrelocatable, to call to so we can
151    get the address of the GOT section */
152 static int rs6000_pic_labelno;
153 
154 #ifdef USING_ELFOS_H
155 /* Counter for labels which are to be placed in .fixup.  */
156 int fixuplabelno = 0;
157 #endif
158 
159 /* Whether to use variant of AIX ABI for PowerPC64 Linux.  */
160 int dot_symbols;
161 
162 /* Specify the machine mode that pointers have.  After generation of rtl, the
163    compiler makes no further distinction between pointers and any other objects
164    of this machine mode.  The type is unsigned since not all things that
165    include rs6000.h also include machmode.h.  */
166 unsigned rs6000_pmode;
167 
168 /* Width in bits of a pointer.  */
169 unsigned rs6000_pointer_size;
170 
171 #ifdef HAVE_AS_GNU_ATTRIBUTE
172 /* Flag whether floating point values have been passed/returned.  */
173 static bool rs6000_passes_float;
174 /* Flag whether vector values have been passed/returned.  */
175 static bool rs6000_passes_vector;
176 /* Flag whether small (<= 8 byte) structures have been returned.  */
177 static bool rs6000_returns_struct;
178 #endif
179 
180 /* Value is TRUE if register/mode pair is acceptable.  */
181 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
182 
183 /* Maximum number of registers needed for a given register class and mode.  */
184 unsigned char rs6000_class_max_nregs[NUM_MACHINE_MODES][LIM_REG_CLASSES];
185 
186 /* How many registers are needed for a given register and mode.  */
187 unsigned char rs6000_hard_regno_nregs[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
188 
189 /* Map register number to register class.  */
190 enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER];
191 
192 /* Reload functions based on the type and the vector unit.  */
193 static enum insn_code rs6000_vector_reload[NUM_MACHINE_MODES][2];
194 
195 static int dbg_cost_ctrl;
196 
197 /* Built in types.  */
198 tree rs6000_builtin_types[RS6000_BTI_MAX];
199 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
200 
201 /* Flag to say the TOC is initialized */
202 int toc_initialized;
203 char toc_label_name[10];
204 
205 /* Cached value of rs6000_variable_issue. This is cached in
206    rs6000_variable_issue hook and returned from rs6000_sched_reorder2.  */
207 static short cached_can_issue_more;
208 
209 static GTY(()) section *read_only_data_section;
210 static GTY(()) section *private_data_section;
211 static GTY(()) section *tls_data_section;
212 static GTY(()) section *tls_private_data_section;
213 static GTY(()) section *read_only_private_data_section;
214 static GTY(()) section *sdata2_section;
215 static GTY(()) section *toc_section;
216 
217 struct builtin_description
218 {
219   const HOST_WIDE_INT mask;
220   const enum insn_code icode;
221   const char *const name;
222   const enum rs6000_builtins code;
223 };
224 
225 /* Describe the vector unit used for modes.  */
226 enum rs6000_vector rs6000_vector_unit[NUM_MACHINE_MODES];
227 enum rs6000_vector rs6000_vector_mem[NUM_MACHINE_MODES];
228 
229 /* Register classes for various constraints that are based on the target
230    switches.  */
231 enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
232 
233 /* Describe the alignment of a vector.  */
234 int rs6000_vector_align[NUM_MACHINE_MODES];
235 
236 /* Map selected modes to types for builtins.  */
237 static GTY(()) tree builtin_mode_to_type[MAX_MACHINE_MODE][2];
238 
239 /* What modes to automatically generate reciprocal divide estimate (fre) and
240    reciprocal sqrt (frsqrte) for.  */
241 unsigned char rs6000_recip_bits[MAX_MACHINE_MODE];
242 
243 /* Masks to determine which reciprocal esitmate instructions to generate
244    automatically.  */
245 enum rs6000_recip_mask {
246   RECIP_SF_DIV		= 0x001,	/* Use divide estimate */
247   RECIP_DF_DIV		= 0x002,
248   RECIP_V4SF_DIV	= 0x004,
249   RECIP_V2DF_DIV	= 0x008,
250 
251   RECIP_SF_RSQRT	= 0x010,	/* Use reciprocal sqrt estimate.  */
252   RECIP_DF_RSQRT	= 0x020,
253   RECIP_V4SF_RSQRT	= 0x040,
254   RECIP_V2DF_RSQRT	= 0x080,
255 
256   /* Various combination of flags for -mrecip=xxx.  */
257   RECIP_NONE		= 0,
258   RECIP_ALL		= (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
259 			   | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
260 			   | RECIP_V4SF_RSQRT | RECIP_V2DF_RSQRT),
261 
262   RECIP_HIGH_PRECISION	= RECIP_ALL,
263 
264   /* On low precision machines like the power5, don't enable double precision
265      reciprocal square root estimate, since it isn't accurate enough.  */
266   RECIP_LOW_PRECISION	= (RECIP_ALL & ~(RECIP_DF_RSQRT | RECIP_V2DF_RSQRT))
267 };
268 
269 /* -mrecip options.  */
270 static struct
271 {
272   const char *string;		/* option name */
273   unsigned int mask;		/* mask bits to set */
274 } recip_options[] = {
275   { "all",	 RECIP_ALL },
276   { "none",	 RECIP_NONE },
277   { "div",	 (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
278 		  | RECIP_V2DF_DIV) },
279   { "divf",	 (RECIP_SF_DIV | RECIP_V4SF_DIV) },
280   { "divd",	 (RECIP_DF_DIV | RECIP_V2DF_DIV) },
281   { "rsqrt",	 (RECIP_SF_RSQRT | RECIP_DF_RSQRT | RECIP_V4SF_RSQRT
282 		  | RECIP_V2DF_RSQRT) },
283   { "rsqrtf",	 (RECIP_SF_RSQRT | RECIP_V4SF_RSQRT) },
284   { "rsqrtd",	 (RECIP_DF_RSQRT | RECIP_V2DF_RSQRT) },
285 };
286 
287 /* 2 argument gen function typedef.  */
288 typedef rtx (*gen_2arg_fn_t) (rtx, rtx, rtx);
289 
290 /* Pointer to function (in rs6000-c.c) that can define or undefine target
291    macros that have changed.  Languages that don't support the preprocessor
292    don't link in rs6000-c.c, so we can't call it directly.  */
293 void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT, HOST_WIDE_INT);
294 
295 
296 /* Target cpu costs.  */
297 
298 struct processor_costs {
299   const int mulsi;	  /* cost of SImode multiplication.  */
300   const int mulsi_const;  /* cost of SImode multiplication by constant.  */
301   const int mulsi_const9; /* cost of SImode mult by short constant.  */
302   const int muldi;	  /* cost of DImode multiplication.  */
303   const int divsi;	  /* cost of SImode division.  */
304   const int divdi;	  /* cost of DImode division.  */
305   const int fp;		  /* cost of simple SFmode and DFmode insns.  */
306   const int dmul;	  /* cost of DFmode multiplication (and fmadd).  */
307   const int sdiv;	  /* cost of SFmode division (fdivs).  */
308   const int ddiv;	  /* cost of DFmode division (fdiv).  */
309   const int cache_line_size;    /* cache line size in bytes. */
310   const int l1_cache_size;	/* size of l1 cache, in kilobytes.  */
311   const int l2_cache_size;	/* size of l2 cache, in kilobytes.  */
312   const int simultaneous_prefetches; /* number of parallel prefetch
313 					operations.  */
314 };
315 
316 const struct processor_costs *rs6000_cost;
317 
318 /* Processor costs (relative to an add) */
319 
320 /* Instruction size costs on 32bit processors.  */
321 static const
322 struct processor_costs size32_cost = {
323   COSTS_N_INSNS (1),    /* mulsi */
324   COSTS_N_INSNS (1),    /* mulsi_const */
325   COSTS_N_INSNS (1),    /* mulsi_const9 */
326   COSTS_N_INSNS (1),    /* muldi */
327   COSTS_N_INSNS (1),    /* divsi */
328   COSTS_N_INSNS (1),    /* divdi */
329   COSTS_N_INSNS (1),    /* fp */
330   COSTS_N_INSNS (1),    /* dmul */
331   COSTS_N_INSNS (1),    /* sdiv */
332   COSTS_N_INSNS (1),    /* ddiv */
333   32,
334   0,
335   0,
336   0,
337 };
338 
339 /* Instruction size costs on 64bit processors.  */
340 static const
341 struct processor_costs size64_cost = {
342   COSTS_N_INSNS (1),    /* mulsi */
343   COSTS_N_INSNS (1),    /* mulsi_const */
344   COSTS_N_INSNS (1),    /* mulsi_const9 */
345   COSTS_N_INSNS (1),    /* muldi */
346   COSTS_N_INSNS (1),    /* divsi */
347   COSTS_N_INSNS (1),    /* divdi */
348   COSTS_N_INSNS (1),    /* fp */
349   COSTS_N_INSNS (1),    /* dmul */
350   COSTS_N_INSNS (1),    /* sdiv */
351   COSTS_N_INSNS (1),    /* ddiv */
352   128,
353   0,
354   0,
355   0,
356 };
357 
358 /* Instruction costs on RS64A processors.  */
359 static const
360 struct processor_costs rs64a_cost = {
361   COSTS_N_INSNS (20),   /* mulsi */
362   COSTS_N_INSNS (12),   /* mulsi_const */
363   COSTS_N_INSNS (8),    /* mulsi_const9 */
364   COSTS_N_INSNS (34),   /* muldi */
365   COSTS_N_INSNS (65),   /* divsi */
366   COSTS_N_INSNS (67),   /* divdi */
367   COSTS_N_INSNS (4),    /* fp */
368   COSTS_N_INSNS (4),    /* dmul */
369   COSTS_N_INSNS (31),   /* sdiv */
370   COSTS_N_INSNS (31),   /* ddiv */
371   128,			/* cache line size */
372   128,			/* l1 cache */
373   2048,			/* l2 cache */
374   1,			/* streams */
375 };
376 
377 /* Instruction costs on MPCCORE processors.  */
378 static const
379 struct processor_costs mpccore_cost = {
380   COSTS_N_INSNS (2),    /* mulsi */
381   COSTS_N_INSNS (2),    /* mulsi_const */
382   COSTS_N_INSNS (2),    /* mulsi_const9 */
383   COSTS_N_INSNS (2),    /* muldi */
384   COSTS_N_INSNS (6),    /* divsi */
385   COSTS_N_INSNS (6),    /* divdi */
386   COSTS_N_INSNS (4),    /* fp */
387   COSTS_N_INSNS (5),    /* dmul */
388   COSTS_N_INSNS (10),   /* sdiv */
389   COSTS_N_INSNS (17),   /* ddiv */
390   32,			/* cache line size */
391   4,			/* l1 cache */
392   16,			/* l2 cache */
393   1,			/* streams */
394 };
395 
396 /* Instruction costs on PPC403 processors.  */
397 static const
398 struct processor_costs ppc403_cost = {
399   COSTS_N_INSNS (4),    /* mulsi */
400   COSTS_N_INSNS (4),    /* mulsi_const */
401   COSTS_N_INSNS (4),    /* mulsi_const9 */
402   COSTS_N_INSNS (4),    /* muldi */
403   COSTS_N_INSNS (33),   /* divsi */
404   COSTS_N_INSNS (33),   /* divdi */
405   COSTS_N_INSNS (11),   /* fp */
406   COSTS_N_INSNS (11),   /* dmul */
407   COSTS_N_INSNS (11),   /* sdiv */
408   COSTS_N_INSNS (11),   /* ddiv */
409   32,			/* cache line size */
410   4,			/* l1 cache */
411   16,			/* l2 cache */
412   1,			/* streams */
413 };
414 
415 /* Instruction costs on PPC405 processors.  */
416 static const
417 struct processor_costs ppc405_cost = {
418   COSTS_N_INSNS (5),    /* mulsi */
419   COSTS_N_INSNS (4),    /* mulsi_const */
420   COSTS_N_INSNS (3),    /* mulsi_const9 */
421   COSTS_N_INSNS (5),    /* muldi */
422   COSTS_N_INSNS (35),   /* divsi */
423   COSTS_N_INSNS (35),   /* divdi */
424   COSTS_N_INSNS (11),   /* fp */
425   COSTS_N_INSNS (11),   /* dmul */
426   COSTS_N_INSNS (11),   /* sdiv */
427   COSTS_N_INSNS (11),   /* ddiv */
428   32,			/* cache line size */
429   16,			/* l1 cache */
430   128,			/* l2 cache */
431   1,			/* streams */
432 };
433 
434 /* Instruction costs on PPC440 processors.  */
435 static const
436 struct processor_costs ppc440_cost = {
437   COSTS_N_INSNS (3),    /* mulsi */
438   COSTS_N_INSNS (2),    /* mulsi_const */
439   COSTS_N_INSNS (2),    /* mulsi_const9 */
440   COSTS_N_INSNS (3),    /* muldi */
441   COSTS_N_INSNS (34),   /* divsi */
442   COSTS_N_INSNS (34),   /* divdi */
443   COSTS_N_INSNS (5),    /* fp */
444   COSTS_N_INSNS (5),    /* dmul */
445   COSTS_N_INSNS (19),   /* sdiv */
446   COSTS_N_INSNS (33),   /* ddiv */
447   32,			/* cache line size */
448   32,			/* l1 cache */
449   256,			/* l2 cache */
450   1,			/* streams */
451 };
452 
453 /* Instruction costs on PPC476 processors.  */
454 static const
455 struct processor_costs ppc476_cost = {
456   COSTS_N_INSNS (4),    /* mulsi */
457   COSTS_N_INSNS (4),    /* mulsi_const */
458   COSTS_N_INSNS (4),    /* mulsi_const9 */
459   COSTS_N_INSNS (4),    /* muldi */
460   COSTS_N_INSNS (11),   /* divsi */
461   COSTS_N_INSNS (11),   /* divdi */
462   COSTS_N_INSNS (6),    /* fp */
463   COSTS_N_INSNS (6),    /* dmul */
464   COSTS_N_INSNS (19),   /* sdiv */
465   COSTS_N_INSNS (33),   /* ddiv */
466   32,			/* l1 cache line size */
467   32,			/* l1 cache */
468   512,			/* l2 cache */
469   1,			/* streams */
470 };
471 
472 /* Instruction costs on PPC601 processors.  */
473 static const
474 struct processor_costs ppc601_cost = {
475   COSTS_N_INSNS (5),    /* mulsi */
476   COSTS_N_INSNS (5),    /* mulsi_const */
477   COSTS_N_INSNS (5),    /* mulsi_const9 */
478   COSTS_N_INSNS (5),    /* muldi */
479   COSTS_N_INSNS (36),   /* divsi */
480   COSTS_N_INSNS (36),   /* divdi */
481   COSTS_N_INSNS (4),    /* fp */
482   COSTS_N_INSNS (5),    /* dmul */
483   COSTS_N_INSNS (17),   /* sdiv */
484   COSTS_N_INSNS (31),   /* ddiv */
485   32,			/* cache line size */
486   32,			/* l1 cache */
487   256,			/* l2 cache */
488   1,			/* streams */
489 };
490 
491 /* Instruction costs on PPC603 processors.  */
492 static const
493 struct processor_costs ppc603_cost = {
494   COSTS_N_INSNS (5),    /* mulsi */
495   COSTS_N_INSNS (3),    /* mulsi_const */
496   COSTS_N_INSNS (2),    /* mulsi_const9 */
497   COSTS_N_INSNS (5),    /* muldi */
498   COSTS_N_INSNS (37),   /* divsi */
499   COSTS_N_INSNS (37),   /* divdi */
500   COSTS_N_INSNS (3),    /* fp */
501   COSTS_N_INSNS (4),    /* dmul */
502   COSTS_N_INSNS (18),   /* sdiv */
503   COSTS_N_INSNS (33),   /* ddiv */
504   32,			/* cache line size */
505   8,			/* l1 cache */
506   64,			/* l2 cache */
507   1,			/* streams */
508 };
509 
510 /* Instruction costs on PPC604 processors.  */
511 static const
512 struct processor_costs ppc604_cost = {
513   COSTS_N_INSNS (4),    /* mulsi */
514   COSTS_N_INSNS (4),    /* mulsi_const */
515   COSTS_N_INSNS (4),    /* mulsi_const9 */
516   COSTS_N_INSNS (4),    /* muldi */
517   COSTS_N_INSNS (20),   /* divsi */
518   COSTS_N_INSNS (20),   /* divdi */
519   COSTS_N_INSNS (3),    /* fp */
520   COSTS_N_INSNS (3),    /* dmul */
521   COSTS_N_INSNS (18),   /* sdiv */
522   COSTS_N_INSNS (32),   /* ddiv */
523   32,			/* cache line size */
524   16,			/* l1 cache */
525   512,			/* l2 cache */
526   1,			/* streams */
527 };
528 
529 /* Instruction costs on PPC604e processors.  */
530 static const
531 struct processor_costs ppc604e_cost = {
532   COSTS_N_INSNS (2),    /* mulsi */
533   COSTS_N_INSNS (2),    /* mulsi_const */
534   COSTS_N_INSNS (2),    /* mulsi_const9 */
535   COSTS_N_INSNS (2),    /* muldi */
536   COSTS_N_INSNS (20),   /* divsi */
537   COSTS_N_INSNS (20),   /* divdi */
538   COSTS_N_INSNS (3),    /* fp */
539   COSTS_N_INSNS (3),    /* dmul */
540   COSTS_N_INSNS (18),   /* sdiv */
541   COSTS_N_INSNS (32),   /* ddiv */
542   32,			/* cache line size */
543   32,			/* l1 cache */
544   1024,			/* l2 cache */
545   1,			/* streams */
546 };
547 
548 /* Instruction costs on PPC620 processors.  */
549 static const
550 struct processor_costs ppc620_cost = {
551   COSTS_N_INSNS (5),    /* mulsi */
552   COSTS_N_INSNS (4),    /* mulsi_const */
553   COSTS_N_INSNS (3),    /* mulsi_const9 */
554   COSTS_N_INSNS (7),    /* muldi */
555   COSTS_N_INSNS (21),   /* divsi */
556   COSTS_N_INSNS (37),   /* divdi */
557   COSTS_N_INSNS (3),    /* fp */
558   COSTS_N_INSNS (3),    /* dmul */
559   COSTS_N_INSNS (18),   /* sdiv */
560   COSTS_N_INSNS (32),   /* ddiv */
561   128,			/* cache line size */
562   32,			/* l1 cache */
563   1024,			/* l2 cache */
564   1,			/* streams */
565 };
566 
567 /* Instruction costs on PPC630 processors.  */
568 static const
569 struct processor_costs ppc630_cost = {
570   COSTS_N_INSNS (5),    /* mulsi */
571   COSTS_N_INSNS (4),    /* mulsi_const */
572   COSTS_N_INSNS (3),    /* mulsi_const9 */
573   COSTS_N_INSNS (7),    /* muldi */
574   COSTS_N_INSNS (21),   /* divsi */
575   COSTS_N_INSNS (37),   /* divdi */
576   COSTS_N_INSNS (3),    /* fp */
577   COSTS_N_INSNS (3),    /* dmul */
578   COSTS_N_INSNS (17),   /* sdiv */
579   COSTS_N_INSNS (21),   /* ddiv */
580   128,			/* cache line size */
581   64,			/* l1 cache */
582   1024,			/* l2 cache */
583   1,			/* streams */
584 };
585 
586 /* Instruction costs on Cell processor.  */
587 /* COSTS_N_INSNS (1) ~ one add.  */
588 static const
589 struct processor_costs ppccell_cost = {
590   COSTS_N_INSNS (9/2)+2,    /* mulsi */
591   COSTS_N_INSNS (6/2),    /* mulsi_const */
592   COSTS_N_INSNS (6/2),    /* mulsi_const9 */
593   COSTS_N_INSNS (15/2)+2,   /* muldi */
594   COSTS_N_INSNS (38/2),   /* divsi */
595   COSTS_N_INSNS (70/2),   /* divdi */
596   COSTS_N_INSNS (10/2),   /* fp */
597   COSTS_N_INSNS (10/2),   /* dmul */
598   COSTS_N_INSNS (74/2),   /* sdiv */
599   COSTS_N_INSNS (74/2),   /* ddiv */
600   128,			/* cache line size */
601   32,			/* l1 cache */
602   512,			/* l2 cache */
603   6,			/* streams */
604 };
605 
606 /* Instruction costs on PPC750 and PPC7400 processors.  */
607 static const
608 struct processor_costs ppc750_cost = {
609   COSTS_N_INSNS (5),    /* mulsi */
610   COSTS_N_INSNS (3),    /* mulsi_const */
611   COSTS_N_INSNS (2),    /* mulsi_const9 */
612   COSTS_N_INSNS (5),    /* muldi */
613   COSTS_N_INSNS (17),   /* divsi */
614   COSTS_N_INSNS (17),   /* divdi */
615   COSTS_N_INSNS (3),    /* fp */
616   COSTS_N_INSNS (3),    /* dmul */
617   COSTS_N_INSNS (17),   /* sdiv */
618   COSTS_N_INSNS (31),   /* ddiv */
619   32,			/* cache line size */
620   32,			/* l1 cache */
621   512,			/* l2 cache */
622   1,			/* streams */
623 };
624 
625 /* Instruction costs on PPC7450 processors.  */
626 static const
627 struct processor_costs ppc7450_cost = {
628   COSTS_N_INSNS (4),    /* mulsi */
629   COSTS_N_INSNS (3),    /* mulsi_const */
630   COSTS_N_INSNS (3),    /* mulsi_const9 */
631   COSTS_N_INSNS (4),    /* muldi */
632   COSTS_N_INSNS (23),   /* divsi */
633   COSTS_N_INSNS (23),   /* divdi */
634   COSTS_N_INSNS (5),    /* fp */
635   COSTS_N_INSNS (5),    /* dmul */
636   COSTS_N_INSNS (21),   /* sdiv */
637   COSTS_N_INSNS (35),   /* ddiv */
638   32,			/* cache line size */
639   32,			/* l1 cache */
640   1024,			/* l2 cache */
641   1,			/* streams */
642 };
643 
644 /* Instruction costs on PPC8540 processors.  */
645 static const
646 struct processor_costs ppc8540_cost = {
647   COSTS_N_INSNS (4),    /* mulsi */
648   COSTS_N_INSNS (4),    /* mulsi_const */
649   COSTS_N_INSNS (4),    /* mulsi_const9 */
650   COSTS_N_INSNS (4),    /* muldi */
651   COSTS_N_INSNS (19),   /* divsi */
652   COSTS_N_INSNS (19),   /* divdi */
653   COSTS_N_INSNS (4),    /* fp */
654   COSTS_N_INSNS (4),    /* dmul */
655   COSTS_N_INSNS (29),   /* sdiv */
656   COSTS_N_INSNS (29),   /* ddiv */
657   32,			/* cache line size */
658   32,			/* l1 cache */
659   256,			/* l2 cache */
660   1,			/* prefetch streams /*/
661 };
662 
663 /* Instruction costs on E300C2 and E300C3 cores.  */
664 static const
665 struct processor_costs ppce300c2c3_cost = {
666   COSTS_N_INSNS (4),    /* mulsi */
667   COSTS_N_INSNS (4),    /* mulsi_const */
668   COSTS_N_INSNS (4),    /* mulsi_const9 */
669   COSTS_N_INSNS (4),    /* muldi */
670   COSTS_N_INSNS (19),   /* divsi */
671   COSTS_N_INSNS (19),   /* divdi */
672   COSTS_N_INSNS (3),    /* fp */
673   COSTS_N_INSNS (4),    /* dmul */
674   COSTS_N_INSNS (18),   /* sdiv */
675   COSTS_N_INSNS (33),   /* ddiv */
676   32,
677   16,			/* l1 cache */
678   16,			/* l2 cache */
679   1,			/* prefetch streams /*/
680 };
681 
682 /* Instruction costs on PPCE500MC processors.  */
683 static const
684 struct processor_costs ppce500mc_cost = {
685   COSTS_N_INSNS (4),    /* mulsi */
686   COSTS_N_INSNS (4),    /* mulsi_const */
687   COSTS_N_INSNS (4),    /* mulsi_const9 */
688   COSTS_N_INSNS (4),    /* muldi */
689   COSTS_N_INSNS (14),   /* divsi */
690   COSTS_N_INSNS (14),   /* divdi */
691   COSTS_N_INSNS (8),    /* fp */
692   COSTS_N_INSNS (10),   /* dmul */
693   COSTS_N_INSNS (36),   /* sdiv */
694   COSTS_N_INSNS (66),   /* ddiv */
695   64,			/* cache line size */
696   32,			/* l1 cache */
697   128,			/* l2 cache */
698   1,			/* prefetch streams /*/
699 };
700 
701 /* Instruction costs on PPCE500MC64 processors.  */
702 static const
703 struct processor_costs ppce500mc64_cost = {
704   COSTS_N_INSNS (4),    /* mulsi */
705   COSTS_N_INSNS (4),    /* mulsi_const */
706   COSTS_N_INSNS (4),    /* mulsi_const9 */
707   COSTS_N_INSNS (4),    /* muldi */
708   COSTS_N_INSNS (14),   /* divsi */
709   COSTS_N_INSNS (14),   /* divdi */
710   COSTS_N_INSNS (4),    /* fp */
711   COSTS_N_INSNS (10),   /* dmul */
712   COSTS_N_INSNS (36),   /* sdiv */
713   COSTS_N_INSNS (66),   /* ddiv */
714   64,			/* cache line size */
715   32,			/* l1 cache */
716   128,			/* l2 cache */
717   1,			/* prefetch streams /*/
718 };
719 
720 /* Instruction costs on PPCE5500 processors.  */
721 static const
722 struct processor_costs ppce5500_cost = {
723   COSTS_N_INSNS (5),    /* mulsi */
724   COSTS_N_INSNS (5),    /* mulsi_const */
725   COSTS_N_INSNS (4),    /* mulsi_const9 */
726   COSTS_N_INSNS (5),    /* muldi */
727   COSTS_N_INSNS (14),   /* divsi */
728   COSTS_N_INSNS (14),   /* divdi */
729   COSTS_N_INSNS (7),    /* fp */
730   COSTS_N_INSNS (10),   /* dmul */
731   COSTS_N_INSNS (36),   /* sdiv */
732   COSTS_N_INSNS (66),   /* ddiv */
733   64,			/* cache line size */
734   32,			/* l1 cache */
735   128,			/* l2 cache */
736   1,			/* prefetch streams /*/
737 };
738 
739 /* Instruction costs on PPCE6500 processors.  */
740 static const
741 struct processor_costs ppce6500_cost = {
742   COSTS_N_INSNS (5),    /* mulsi */
743   COSTS_N_INSNS (5),    /* mulsi_const */
744   COSTS_N_INSNS (4),    /* mulsi_const9 */
745   COSTS_N_INSNS (5),    /* muldi */
746   COSTS_N_INSNS (14),   /* divsi */
747   COSTS_N_INSNS (14),   /* divdi */
748   COSTS_N_INSNS (7),    /* fp */
749   COSTS_N_INSNS (10),   /* dmul */
750   COSTS_N_INSNS (36),   /* sdiv */
751   COSTS_N_INSNS (66),   /* ddiv */
752   64,			/* cache line size */
753   32,			/* l1 cache */
754   128,			/* l2 cache */
755   1,			/* prefetch streams /*/
756 };
757 
758 /* Instruction costs on AppliedMicro Titan processors.  */
759 static const
760 struct processor_costs titan_cost = {
761   COSTS_N_INSNS (5),    /* mulsi */
762   COSTS_N_INSNS (5),    /* mulsi_const */
763   COSTS_N_INSNS (5),    /* mulsi_const9 */
764   COSTS_N_INSNS (5),    /* muldi */
765   COSTS_N_INSNS (18),   /* divsi */
766   COSTS_N_INSNS (18),   /* divdi */
767   COSTS_N_INSNS (10),   /* fp */
768   COSTS_N_INSNS (10),   /* dmul */
769   COSTS_N_INSNS (46),   /* sdiv */
770   COSTS_N_INSNS (72),   /* ddiv */
771   32,			/* cache line size */
772   32,			/* l1 cache */
773   512,			/* l2 cache */
774   1,			/* prefetch streams /*/
775 };
776 
777 /* Instruction costs on POWER4 and POWER5 processors.  */
778 static const
779 struct processor_costs power4_cost = {
780   COSTS_N_INSNS (3),    /* mulsi */
781   COSTS_N_INSNS (2),    /* mulsi_const */
782   COSTS_N_INSNS (2),    /* mulsi_const9 */
783   COSTS_N_INSNS (4),    /* muldi */
784   COSTS_N_INSNS (18),   /* divsi */
785   COSTS_N_INSNS (34),   /* divdi */
786   COSTS_N_INSNS (3),    /* fp */
787   COSTS_N_INSNS (3),    /* dmul */
788   COSTS_N_INSNS (17),   /* sdiv */
789   COSTS_N_INSNS (17),   /* ddiv */
790   128,			/* cache line size */
791   32,			/* l1 cache */
792   1024,			/* l2 cache */
793   8,			/* prefetch streams /*/
794 };
795 
796 /* Instruction costs on POWER6 processors.  */
797 static const
798 struct processor_costs power6_cost = {
799   COSTS_N_INSNS (8),    /* mulsi */
800   COSTS_N_INSNS (8),    /* mulsi_const */
801   COSTS_N_INSNS (8),    /* mulsi_const9 */
802   COSTS_N_INSNS (8),    /* muldi */
803   COSTS_N_INSNS (22),   /* divsi */
804   COSTS_N_INSNS (28),   /* divdi */
805   COSTS_N_INSNS (3),    /* fp */
806   COSTS_N_INSNS (3),    /* dmul */
807   COSTS_N_INSNS (13),   /* sdiv */
808   COSTS_N_INSNS (16),   /* ddiv */
809   128,			/* cache line size */
810   64,			/* l1 cache */
811   2048,			/* l2 cache */
812   16,			/* prefetch streams */
813 };
814 
815 /* Instruction costs on POWER7 processors.  */
816 static const
817 struct processor_costs power7_cost = {
818   COSTS_N_INSNS (2),	/* mulsi */
819   COSTS_N_INSNS (2),	/* mulsi_const */
820   COSTS_N_INSNS (2),	/* mulsi_const9 */
821   COSTS_N_INSNS (2),	/* muldi */
822   COSTS_N_INSNS (18),	/* divsi */
823   COSTS_N_INSNS (34),	/* divdi */
824   COSTS_N_INSNS (3),	/* fp */
825   COSTS_N_INSNS (3),	/* dmul */
826   COSTS_N_INSNS (13),	/* sdiv */
827   COSTS_N_INSNS (16),	/* ddiv */
828   128,			/* cache line size */
829   32,			/* l1 cache */
830   256,			/* l2 cache */
831   12,			/* prefetch streams */
832 };
833 
834 /* Instruction costs on POWER A2 processors.  */
835 static const
836 struct processor_costs ppca2_cost = {
837   COSTS_N_INSNS (16),    /* mulsi */
838   COSTS_N_INSNS (16),    /* mulsi_const */
839   COSTS_N_INSNS (16),    /* mulsi_const9 */
840   COSTS_N_INSNS (16),   /* muldi */
841   COSTS_N_INSNS (22),   /* divsi */
842   COSTS_N_INSNS (28),   /* divdi */
843   COSTS_N_INSNS (3),    /* fp */
844   COSTS_N_INSNS (3),    /* dmul */
845   COSTS_N_INSNS (59),   /* sdiv */
846   COSTS_N_INSNS (72),   /* ddiv */
847   64,
848   16,			/* l1 cache */
849   2048,			/* l2 cache */
850   16,			/* prefetch streams */
851 };
852 
853 
854 /* Table that classifies rs6000 builtin functions (pure, const, etc.).  */
855 #undef RS6000_BUILTIN_1
856 #undef RS6000_BUILTIN_2
857 #undef RS6000_BUILTIN_3
858 #undef RS6000_BUILTIN_A
859 #undef RS6000_BUILTIN_D
860 #undef RS6000_BUILTIN_E
861 #undef RS6000_BUILTIN_P
862 #undef RS6000_BUILTIN_Q
863 #undef RS6000_BUILTIN_S
864 #undef RS6000_BUILTIN_X
865 
866 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
867   { NAME, ICODE, MASK, ATTR },
868 
869 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)  \
870   { NAME, ICODE, MASK, ATTR },
871 
872 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)  \
873   { NAME, ICODE, MASK, ATTR },
874 
875 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)  \
876   { NAME, ICODE, MASK, ATTR },
877 
878 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)  \
879   { NAME, ICODE, MASK, ATTR },
880 
881 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)  \
882   { NAME, ICODE, MASK, ATTR },
883 
884 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)  \
885   { NAME, ICODE, MASK, ATTR },
886 
887 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)  \
888   { NAME, ICODE, MASK, ATTR },
889 
890 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)  \
891   { NAME, ICODE, MASK, ATTR },
892 
893 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)  \
894   { NAME, ICODE, MASK, ATTR },
895 
896 struct rs6000_builtin_info_type {
897   const char *name;
898   const enum insn_code icode;
899   const HOST_WIDE_INT mask;
900   const unsigned attr;
901 };
902 
903 static const struct rs6000_builtin_info_type rs6000_builtin_info[] =
904 {
905 #include "rs6000-builtin.def"
906 };
907 
908 #undef RS6000_BUILTIN_1
909 #undef RS6000_BUILTIN_2
910 #undef RS6000_BUILTIN_3
911 #undef RS6000_BUILTIN_A
912 #undef RS6000_BUILTIN_D
913 #undef RS6000_BUILTIN_E
914 #undef RS6000_BUILTIN_P
915 #undef RS6000_BUILTIN_Q
916 #undef RS6000_BUILTIN_S
917 #undef RS6000_BUILTIN_X
918 
919 /* Support for -mveclibabi=<xxx> to control which vector library to use.  */
920 static tree (*rs6000_veclib_handler) (tree, tree, tree);
921 
922 
923 static bool rs6000_debug_legitimate_address_p (enum machine_mode, rtx, bool);
924 static bool spe_func_has_64bit_regs_p (void);
925 static struct machine_function * rs6000_init_machine_status (void);
926 static int rs6000_ra_ever_killed (void);
927 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
928 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
929 static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
930 static tree rs6000_builtin_vectorized_libmass (tree, tree, tree);
931 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
932 static int rs6000_memory_move_cost (enum machine_mode, reg_class_t, bool);
933 static bool rs6000_debug_rtx_costs (rtx, int, int, int, int *, bool);
934 static int rs6000_debug_address_cost (rtx, enum machine_mode, addr_space_t,
935 				      bool);
936 static int rs6000_debug_adjust_cost (rtx, rtx, rtx, int);
937 static bool is_microcoded_insn (rtx);
938 static bool is_nonpipeline_insn (rtx);
939 static bool is_cracked_insn (rtx);
940 static bool is_load_insn (rtx, rtx *);
941 static bool is_store_insn (rtx, rtx *);
942 static bool set_to_load_agen (rtx,rtx);
943 static bool insn_terminates_group_p (rtx , enum group_termination);
944 static bool insn_must_be_first_in_group (rtx);
945 static bool insn_must_be_last_in_group (rtx);
946 static void altivec_init_builtins (void);
947 static tree builtin_function_type (enum machine_mode, enum machine_mode,
948 				   enum machine_mode, enum machine_mode,
949 				   enum rs6000_builtins, const char *name);
950 static void rs6000_common_init_builtins (void);
951 static void paired_init_builtins (void);
952 static rtx paired_expand_predicate_builtin (enum insn_code, tree, rtx);
953 static void spe_init_builtins (void);
954 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
955 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
956 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
957 static rs6000_stack_t *rs6000_stack_info (void);
958 static void is_altivec_return_reg (rtx, void *);
959 int easy_vector_constant (rtx, enum machine_mode);
960 static rtx rs6000_debug_legitimize_address (rtx, rtx, enum machine_mode);
961 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
962 static int rs6000_tls_symbol_ref_1 (rtx *, void *);
963 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
964 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, const_tree,
965 				       bool, bool);
966 #if TARGET_MACHO
967 static void macho_branch_islands (void);
968 #endif
969 static rtx rs6000_legitimize_reload_address (rtx, enum machine_mode, int, int,
970 					     int, int *);
971 static rtx rs6000_debug_legitimize_reload_address (rtx, enum machine_mode, int,
972 						   int, int, int *);
973 static bool rs6000_mode_dependent_address (const_rtx);
974 static bool rs6000_debug_mode_dependent_address (const_rtx);
975 static enum reg_class rs6000_secondary_reload_class (enum reg_class,
976 						     enum machine_mode, rtx);
977 static enum reg_class rs6000_debug_secondary_reload_class (enum reg_class,
978 							   enum machine_mode,
979 							   rtx);
980 static enum reg_class rs6000_preferred_reload_class (rtx, enum reg_class);
981 static enum reg_class rs6000_debug_preferred_reload_class (rtx,
982 							   enum reg_class);
983 static bool rs6000_secondary_memory_needed (enum reg_class, enum reg_class,
984 					    enum machine_mode);
985 static bool rs6000_debug_secondary_memory_needed (enum reg_class,
986 						  enum reg_class,
987 						  enum machine_mode);
988 static bool rs6000_cannot_change_mode_class (enum machine_mode,
989 					     enum machine_mode,
990 					     enum reg_class);
991 static bool rs6000_debug_cannot_change_mode_class (enum machine_mode,
992 						   enum machine_mode,
993 						   enum reg_class);
994 static bool rs6000_save_toc_in_prologue_p (void);
995 
996 rtx (*rs6000_legitimize_reload_address_ptr) (rtx, enum machine_mode, int, int,
997 					     int, int *)
998   = rs6000_legitimize_reload_address;
999 
1000 static bool (*rs6000_mode_dependent_address_ptr) (const_rtx)
1001   = rs6000_mode_dependent_address;
1002 
1003 enum reg_class (*rs6000_secondary_reload_class_ptr) (enum reg_class,
1004 						     enum machine_mode, rtx)
1005   = rs6000_secondary_reload_class;
1006 
1007 enum reg_class (*rs6000_preferred_reload_class_ptr) (rtx, enum reg_class)
1008   = rs6000_preferred_reload_class;
1009 
1010 bool (*rs6000_secondary_memory_needed_ptr) (enum reg_class, enum reg_class,
1011 					    enum machine_mode)
1012   = rs6000_secondary_memory_needed;
1013 
1014 bool (*rs6000_cannot_change_mode_class_ptr) (enum machine_mode,
1015 					     enum machine_mode,
1016 					     enum reg_class)
1017   = rs6000_cannot_change_mode_class;
1018 
1019 const int INSN_NOT_AVAILABLE = -1;
1020 
1021 static void rs6000_print_isa_options (FILE *, int, const char *,
1022 				      HOST_WIDE_INT);
1023 static void rs6000_print_builtin_options (FILE *, int, const char *,
1024 					  HOST_WIDE_INT);
1025 
1026 /* Hash table stuff for keeping track of TOC entries.  */
1027 
1028 struct GTY(()) toc_hash_struct
1029 {
1030   /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1031      ASM_OUTPUT_SPECIAL_POOL_ENTRY_P.  */
1032   rtx key;
1033   enum machine_mode key_mode;
1034   int labelno;
1035 };
1036 
1037 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
1038 
1039 /* Hash table to keep track of the argument types for builtin functions.  */
1040 
1041 struct GTY(()) builtin_hash_struct
1042 {
1043   tree type;
1044   enum machine_mode mode[4];	/* return value + 3 arguments.  */
1045   unsigned char uns_p[4];	/* and whether the types are unsigned.  */
1046 };
1047 
1048 static GTY ((param_is (struct builtin_hash_struct))) htab_t builtin_hash_table;
1049 
1050 
1051 /* Default register names.  */
1052 char rs6000_reg_names[][8] =
1053 {
1054       "0",  "1",  "2",  "3",  "4",  "5",  "6",  "7",
1055       "8",  "9", "10", "11", "12", "13", "14", "15",
1056      "16", "17", "18", "19", "20", "21", "22", "23",
1057      "24", "25", "26", "27", "28", "29", "30", "31",
1058       "0",  "1",  "2",  "3",  "4",  "5",  "6",  "7",
1059       "8",  "9", "10", "11", "12", "13", "14", "15",
1060      "16", "17", "18", "19", "20", "21", "22", "23",
1061      "24", "25", "26", "27", "28", "29", "30", "31",
1062      "mq", "lr", "ctr","ap",
1063       "0",  "1",  "2",  "3",  "4",  "5",  "6",  "7",
1064       "ca",
1065       /* AltiVec registers.  */
1066       "0",  "1",  "2",  "3",  "4",  "5",  "6", "7",
1067       "8",  "9",  "10", "11", "12", "13", "14", "15",
1068       "16", "17", "18", "19", "20", "21", "22", "23",
1069       "24", "25", "26", "27", "28", "29", "30", "31",
1070       "vrsave", "vscr",
1071       /* SPE registers.  */
1072       "spe_acc", "spefscr",
1073       /* Soft frame pointer.  */
1074       "sfp"
1075 };
1076 
1077 #ifdef TARGET_REGNAMES
1078 static const char alt_reg_names[][8] =
1079 {
1080    "%r0",   "%r1",  "%r2",  "%r3",  "%r4",  "%r5",  "%r6",  "%r7",
1081    "%r8",   "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1082   "%r16",  "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1083   "%r24",  "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1084    "%f0",   "%f1",  "%f2",  "%f3",  "%f4",  "%f5",  "%f6",  "%f7",
1085    "%f8",   "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1086   "%f16",  "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1087   "%f24",  "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1088     "mq",    "lr",  "ctr",   "ap",
1089   "%cr0",  "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1090    "ca",
1091   /* AltiVec registers.  */
1092    "%v0",  "%v1",  "%v2",  "%v3",  "%v4",  "%v5",  "%v6", "%v7",
1093    "%v8",  "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1094   "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1095   "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1096   "vrsave", "vscr",
1097   /* SPE registers.  */
1098   "spe_acc", "spefscr",
1099   /* Soft frame pointer.  */
1100   "sfp"
1101 };
1102 #endif
1103 
1104 /* Table of valid machine attributes.  */
1105 
1106 static const struct attribute_spec rs6000_attribute_table[] =
1107 {
1108   /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
1109        affects_type_identity } */
1110   { "altivec",   1, 1, false, true,  false, rs6000_handle_altivec_attribute,
1111     false },
1112   { "longcall",  0, 0, false, true,  true,  rs6000_handle_longcall_attribute,
1113     false },
1114   { "shortcall", 0, 0, false, true,  true,  rs6000_handle_longcall_attribute,
1115     false },
1116   { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute,
1117     false },
1118   { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute,
1119     false },
1120 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1121   SUBTARGET_ATTRIBUTE_TABLE,
1122 #endif
1123   { NULL,        0, 0, false, false, false, NULL, false }
1124 };
1125 
1126 #ifndef TARGET_PROFILE_KERNEL
1127 #define TARGET_PROFILE_KERNEL 0
1128 #endif
1129 
1130 /* The VRSAVE bitmask puts bit %v0 as the most significant bit.  */
1131 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1132 
1133 /* Initialize the GCC target structure.  */
1134 #undef TARGET_ATTRIBUTE_TABLE
1135 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1136 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1137 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1138 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1139 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1140 
1141 #undef TARGET_ASM_ALIGNED_DI_OP
1142 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1143 
1144 /* Default unaligned ops are only provided for ELF.  Find the ops needed
1145    for non-ELF systems.  */
1146 #ifndef OBJECT_FORMAT_ELF
1147 #if TARGET_XCOFF
1148 /* For XCOFF.  rs6000_assemble_integer will handle unaligned DIs on
1149    64-bit targets.  */
1150 #undef TARGET_ASM_UNALIGNED_HI_OP
1151 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1152 #undef TARGET_ASM_UNALIGNED_SI_OP
1153 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1154 #undef TARGET_ASM_UNALIGNED_DI_OP
1155 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1156 #else
1157 /* For Darwin.  */
1158 #undef TARGET_ASM_UNALIGNED_HI_OP
1159 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1160 #undef TARGET_ASM_UNALIGNED_SI_OP
1161 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1162 #undef TARGET_ASM_UNALIGNED_DI_OP
1163 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1164 #undef TARGET_ASM_ALIGNED_DI_OP
1165 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1166 #endif
1167 #endif
1168 
1169 /* This hook deals with fixups for relocatable code and DI-mode objects
1170    in 64-bit code.  */
1171 #undef TARGET_ASM_INTEGER
1172 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1173 
1174 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
1175 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1176 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1177 #endif
1178 
1179 #undef TARGET_SET_UP_BY_PROLOGUE
1180 #define TARGET_SET_UP_BY_PROLOGUE rs6000_set_up_by_prologue
1181 
1182 #undef TARGET_HAVE_TLS
1183 #define TARGET_HAVE_TLS HAVE_AS_TLS
1184 
1185 #undef TARGET_CANNOT_FORCE_CONST_MEM
1186 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1187 
1188 #undef TARGET_DELEGITIMIZE_ADDRESS
1189 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1190 
1191 #undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
1192 #define TARGET_CONST_NOT_OK_FOR_DEBUG_P rs6000_const_not_ok_for_debug_p
1193 
1194 #undef TARGET_ASM_FUNCTION_PROLOGUE
1195 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1196 #undef TARGET_ASM_FUNCTION_EPILOGUE
1197 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1198 
1199 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1200 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1201 
1202 #undef TARGET_LEGITIMIZE_ADDRESS
1203 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1204 
1205 #undef  TARGET_SCHED_VARIABLE_ISSUE
1206 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1207 
1208 #undef TARGET_SCHED_ISSUE_RATE
1209 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1210 #undef TARGET_SCHED_ADJUST_COST
1211 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1212 #undef TARGET_SCHED_ADJUST_PRIORITY
1213 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1214 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1215 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1216 #undef TARGET_SCHED_INIT
1217 #define TARGET_SCHED_INIT rs6000_sched_init
1218 #undef TARGET_SCHED_FINISH
1219 #define TARGET_SCHED_FINISH rs6000_sched_finish
1220 #undef TARGET_SCHED_REORDER
1221 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1222 #undef TARGET_SCHED_REORDER2
1223 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1224 
1225 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1226 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1227 
1228 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1229 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1230 
1231 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1232 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1233 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1234 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1235 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1236 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1237 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1238 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1239 
1240 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1241 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1242 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1243 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT		\
1244   rs6000_builtin_support_vector_misalignment
1245 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1246 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1247 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1248 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1249   rs6000_builtin_vectorization_cost
1250 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1251 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1252   rs6000_preferred_simd_mode
1253 #undef TARGET_VECTORIZE_INIT_COST
1254 #define TARGET_VECTORIZE_INIT_COST rs6000_init_cost
1255 #undef TARGET_VECTORIZE_ADD_STMT_COST
1256 #define TARGET_VECTORIZE_ADD_STMT_COST rs6000_add_stmt_cost
1257 #undef TARGET_VECTORIZE_FINISH_COST
1258 #define TARGET_VECTORIZE_FINISH_COST rs6000_finish_cost
1259 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
1260 #define TARGET_VECTORIZE_DESTROY_COST_DATA rs6000_destroy_cost_data
1261 
1262 #undef TARGET_INIT_BUILTINS
1263 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1264 #undef TARGET_BUILTIN_DECL
1265 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1266 
1267 #undef TARGET_EXPAND_BUILTIN
1268 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1269 
1270 #undef TARGET_MANGLE_TYPE
1271 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1272 
1273 #undef TARGET_INIT_LIBFUNCS
1274 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1275 
1276 #if TARGET_MACHO
1277 #undef TARGET_BINDS_LOCAL_P
1278 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1279 #endif
1280 
1281 #undef TARGET_MS_BITFIELD_LAYOUT_P
1282 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1283 
1284 #undef TARGET_ASM_OUTPUT_MI_THUNK
1285 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1286 
1287 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1288 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1289 
1290 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1291 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1292 
1293 #undef TARGET_INVALID_WITHIN_DOLOOP
1294 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
1295 
1296 #undef TARGET_REGISTER_MOVE_COST
1297 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1298 #undef TARGET_MEMORY_MOVE_COST
1299 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1300 #undef TARGET_RTX_COSTS
1301 #define TARGET_RTX_COSTS rs6000_rtx_costs
1302 #undef TARGET_ADDRESS_COST
1303 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
1304 
1305 #undef TARGET_DWARF_REGISTER_SPAN
1306 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1307 
1308 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1309 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1310 
1311 #undef TARGET_MEMBER_TYPE_FORCES_BLK
1312 #define TARGET_MEMBER_TYPE_FORCES_BLK rs6000_member_type_forces_blk
1313 
1314 /* On rs6000, function arguments are promoted, as are function return
1315    values.  */
1316 #undef TARGET_PROMOTE_FUNCTION_MODE
1317 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
1318 
1319 #undef TARGET_RETURN_IN_MEMORY
1320 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1321 
1322 #undef TARGET_SETUP_INCOMING_VARARGS
1323 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1324 
1325 /* Always strict argument naming on rs6000.  */
1326 #undef TARGET_STRICT_ARGUMENT_NAMING
1327 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1328 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1329 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1330 #undef TARGET_SPLIT_COMPLEX_ARG
1331 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1332 #undef TARGET_MUST_PASS_IN_STACK
1333 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1334 #undef TARGET_PASS_BY_REFERENCE
1335 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1336 #undef TARGET_ARG_PARTIAL_BYTES
1337 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1338 #undef TARGET_FUNCTION_ARG_ADVANCE
1339 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1340 #undef TARGET_FUNCTION_ARG
1341 #define TARGET_FUNCTION_ARG rs6000_function_arg
1342 #undef TARGET_FUNCTION_ARG_BOUNDARY
1343 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1344 
1345 #undef TARGET_BUILD_BUILTIN_VA_LIST
1346 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1347 
1348 #undef TARGET_EXPAND_BUILTIN_VA_START
1349 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1350 
1351 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1352 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1353 
1354 #undef TARGET_EH_RETURN_FILTER_MODE
1355 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1356 
1357 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1358 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1359 
1360 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1361 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1362 
1363 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1364 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1365 
1366 #undef TARGET_ASM_LOOP_ALIGN_MAX_SKIP
1367 #define TARGET_ASM_LOOP_ALIGN_MAX_SKIP rs6000_loop_align_max_skip
1368 
1369 #undef TARGET_OPTION_OVERRIDE
1370 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1371 
1372 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1373 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1374   rs6000_builtin_vectorized_function
1375 
1376 #if !TARGET_MACHO
1377 #undef TARGET_STACK_PROTECT_FAIL
1378 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1379 #endif
1380 
1381 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1382    The PowerPC architecture requires only weak consistency among
1383    processors--that is, memory accesses between processors need not be
1384    sequentially consistent and memory accesses among processors can occur
1385    in any order. The ability to order memory accesses weakly provides
1386    opportunities for more efficient use of the system bus. Unless a
1387    dependency exists, the 604e allows read operations to precede store
1388    operations.  */
1389 #undef TARGET_RELAXED_ORDERING
1390 #define TARGET_RELAXED_ORDERING true
1391 
1392 #ifdef HAVE_AS_TLS
1393 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1394 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1395 #endif
1396 
1397 /* Use a 32-bit anchor range.  This leads to sequences like:
1398 
1399 	addis	tmp,anchor,high
1400 	add	dest,tmp,low
1401 
1402    where tmp itself acts as an anchor, and can be shared between
1403    accesses to the same 64k page.  */
1404 #undef TARGET_MIN_ANCHOR_OFFSET
1405 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1406 #undef TARGET_MAX_ANCHOR_OFFSET
1407 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1408 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1409 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1410 #undef TARGET_USE_BLOCKS_FOR_DECL_P
1411 #define TARGET_USE_BLOCKS_FOR_DECL_P rs6000_use_blocks_for_decl_p
1412 
1413 #undef TARGET_BUILTIN_RECIPROCAL
1414 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1415 
1416 #undef TARGET_EXPAND_TO_RTL_HOOK
1417 #define TARGET_EXPAND_TO_RTL_HOOK rs6000_alloc_sdmode_stack_slot
1418 
1419 #undef TARGET_INSTANTIATE_DECLS
1420 #define TARGET_INSTANTIATE_DECLS rs6000_instantiate_decls
1421 
1422 #undef TARGET_SECONDARY_RELOAD
1423 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1424 
1425 #undef TARGET_LEGITIMATE_ADDRESS_P
1426 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1427 
1428 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1429 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1430 
1431 #undef TARGET_CAN_ELIMINATE
1432 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1433 
1434 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1435 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1436 
1437 #undef TARGET_TRAMPOLINE_INIT
1438 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1439 
1440 #undef TARGET_FUNCTION_VALUE
1441 #define TARGET_FUNCTION_VALUE rs6000_function_value
1442 
1443 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1444 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1445 
1446 #undef TARGET_OPTION_SAVE
1447 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1448 
1449 #undef TARGET_OPTION_RESTORE
1450 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1451 
1452 #undef TARGET_OPTION_PRINT
1453 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1454 
1455 #undef TARGET_CAN_INLINE_P
1456 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1457 
1458 #undef TARGET_SET_CURRENT_FUNCTION
1459 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1460 
1461 #undef TARGET_LEGITIMATE_CONSTANT_P
1462 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1463 
1464 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
1465 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK rs6000_vectorize_vec_perm_const_ok
1466 
1467 
1468 /* Processor table.  */
1469 struct rs6000_ptt
1470 {
1471   const char *const name;		/* Canonical processor name.  */
1472   const enum processor_type processor;	/* Processor type enum value.  */
1473   const HOST_WIDE_INT target_enable;	/* Target flags to enable.  */
1474 };
1475 
1476 static struct rs6000_ptt const processor_target_table[] =
1477 {
1478 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
1479 #include "rs6000-cpus.def"
1480 #undef RS6000_CPU
1481 };
1482 
1483 /* Look up a processor name for -mcpu=xxx and -mtune=xxx.  Return -1 if the
1484    name is invalid.  */
1485 
1486 static int
rs6000_cpu_name_lookup(const char * name)1487 rs6000_cpu_name_lookup (const char *name)
1488 {
1489   size_t i;
1490 
1491   if (name != NULL)
1492     {
1493       for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
1494 	if (! strcmp (name, processor_target_table[i].name))
1495 	  return (int)i;
1496     }
1497 
1498   return -1;
1499 }
1500 
1501 
1502 /* Return number of consecutive hard regs needed starting at reg REGNO
1503    to hold something of mode MODE.
1504    This is ordinarily the length in words of a value of mode MODE
1505    but can be less for certain modes in special long registers.
1506 
1507    For the SPE, GPRs are 64 bits but only 32 bits are visible in
1508    scalar instructions.  The upper 32 bits are only available to the
1509    SIMD instructions.
1510 
1511    POWER and PowerPC GPRs hold 32 bits worth;
1512    PowerPC64 GPRs and FPRs point register holds 64 bits worth.  */
1513 
1514 static int
rs6000_hard_regno_nregs_internal(int regno,enum machine_mode mode)1515 rs6000_hard_regno_nregs_internal (int regno, enum machine_mode mode)
1516 {
1517   unsigned HOST_WIDE_INT reg_size;
1518 
1519   if (FP_REGNO_P (regno))
1520     reg_size = (VECTOR_MEM_VSX_P (mode)
1521 		? UNITS_PER_VSX_WORD
1522 		: UNITS_PER_FP_WORD);
1523 
1524   else if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1525     reg_size = UNITS_PER_SPE_WORD;
1526 
1527   else if (ALTIVEC_REGNO_P (regno))
1528     reg_size = UNITS_PER_ALTIVEC_WORD;
1529 
1530   /* The value returned for SCmode in the E500 double case is 2 for
1531      ABI compatibility; storing an SCmode value in a single register
1532      would require function_arg and rs6000_spe_function_arg to handle
1533      SCmode so as to pass the value correctly in a pair of
1534      registers.  */
1535   else if (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode) && mode != SCmode
1536 	   && !DECIMAL_FLOAT_MODE_P (mode))
1537     reg_size = UNITS_PER_FP_WORD;
1538 
1539   else
1540     reg_size = UNITS_PER_WORD;
1541 
1542   return (GET_MODE_SIZE (mode) + reg_size - 1) / reg_size;
1543 }
1544 
1545 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1546    MODE.  */
1547 static int
rs6000_hard_regno_mode_ok(int regno,enum machine_mode mode)1548 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1549 {
1550   int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;
1551 
1552   /* VSX registers that overlap the FPR registers are larger than for non-VSX
1553      implementations.  Don't allow an item to be split between a FP register
1554      and an Altivec register.  */
1555   if (VECTOR_MEM_VSX_P (mode))
1556     {
1557       if (FP_REGNO_P (regno))
1558 	return FP_REGNO_P (last_regno);
1559 
1560       if (ALTIVEC_REGNO_P (regno))
1561 	return ALTIVEC_REGNO_P (last_regno);
1562     }
1563 
1564   /* The GPRs can hold any mode, but values bigger than one register
1565      cannot go past R31.  */
1566   if (INT_REGNO_P (regno))
1567     return INT_REGNO_P (last_regno);
1568 
1569   /* The float registers (except for VSX vector modes) can only hold floating
1570      modes and DImode.  This excludes the 32-bit decimal float mode for
1571      now.  */
1572   if (FP_REGNO_P (regno))
1573     {
1574       if (SCALAR_FLOAT_MODE_P (mode)
1575 	  && (mode != TDmode || (regno % 2) == 0)
1576 	  && FP_REGNO_P (last_regno))
1577 	return 1;
1578 
1579       if (GET_MODE_CLASS (mode) == MODE_INT
1580 	  && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
1581 	return 1;
1582 
1583       if (PAIRED_SIMD_REGNO_P (regno) && TARGET_PAIRED_FLOAT
1584 	  && PAIRED_VECTOR_MODE (mode))
1585 	return 1;
1586 
1587       return 0;
1588     }
1589 
1590   /* The CR register can only hold CC modes.  */
1591   if (CR_REGNO_P (regno))
1592     return GET_MODE_CLASS (mode) == MODE_CC;
1593 
1594   if (CA_REGNO_P (regno))
1595     return mode == BImode;
1596 
1597   /* AltiVec only in AldyVec registers.  */
1598   if (ALTIVEC_REGNO_P (regno))
1599     return VECTOR_MEM_ALTIVEC_OR_VSX_P (mode);
1600 
1601   /* ...but GPRs can hold SIMD data on the SPE in one register.  */
1602   if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1603     return 1;
1604 
1605   /* We cannot put TImode anywhere except general register and it must be able
1606      to fit within the register set.  In the future, allow TImode in the
1607      Altivec or VSX registers.  */
1608 
1609   return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1610 }
1611 
1612 /* Print interesting facts about registers.  */
1613 static void
rs6000_debug_reg_print(int first_regno,int last_regno,const char * reg_name)1614 rs6000_debug_reg_print (int first_regno, int last_regno, const char *reg_name)
1615 {
1616   int r, m;
1617 
1618   for (r = first_regno; r <= last_regno; ++r)
1619     {
1620       const char *comma = "";
1621       int len;
1622 
1623       if (first_regno == last_regno)
1624 	fprintf (stderr, "%s:\t", reg_name);
1625       else
1626 	fprintf (stderr, "%s%d:\t", reg_name, r - first_regno);
1627 
1628       len = 8;
1629       for (m = 0; m < NUM_MACHINE_MODES; ++m)
1630 	if (rs6000_hard_regno_mode_ok_p[m][r] && rs6000_hard_regno_nregs[m][r])
1631 	  {
1632 	    if (len > 70)
1633 	      {
1634 		fprintf (stderr, ",\n\t");
1635 		len = 8;
1636 		comma = "";
1637 	      }
1638 
1639 	    if (rs6000_hard_regno_nregs[m][r] > 1)
1640 	      len += fprintf (stderr, "%s%s/%d", comma, GET_MODE_NAME (m),
1641 			     rs6000_hard_regno_nregs[m][r]);
1642 	    else
1643 	      len += fprintf (stderr, "%s%s", comma, GET_MODE_NAME (m));
1644 
1645 	    comma = ", ";
1646 	  }
1647 
1648       if (call_used_regs[r])
1649 	{
1650 	  if (len > 70)
1651 	    {
1652 	      fprintf (stderr, ",\n\t");
1653 	      len = 8;
1654 	      comma = "";
1655 	    }
1656 
1657 	  len += fprintf (stderr, "%s%s", comma, "call-used");
1658 	  comma = ", ";
1659 	}
1660 
1661       if (fixed_regs[r])
1662 	{
1663 	  if (len > 70)
1664 	    {
1665 	      fprintf (stderr, ",\n\t");
1666 	      len = 8;
1667 	      comma = "";
1668 	    }
1669 
1670 	  len += fprintf (stderr, "%s%s", comma, "fixed");
1671 	  comma = ", ";
1672 	}
1673 
1674       if (len > 70)
1675 	{
1676 	  fprintf (stderr, ",\n\t");
1677 	  comma = "";
1678 	}
1679 
1680       fprintf (stderr, "%sregno = %d\n", comma, r);
1681     }
1682 }
1683 
1684 #define DEBUG_FMT_ID "%-32s= "
1685 #define DEBUG_FMT_D   DEBUG_FMT_ID "%d\n"
1686 #define DEBUG_FMT_WX  DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "
1687 #define DEBUG_FMT_S   DEBUG_FMT_ID "%s\n"
1688 
1689 /* Print various interesting information with -mdebug=reg.  */
1690 static void
rs6000_debug_reg_global(void)1691 rs6000_debug_reg_global (void)
1692 {
1693   static const char *const tf[2] = { "false", "true" };
1694   const char *nl = (const char *)0;
1695   int m;
1696   char costly_num[20];
1697   char nop_num[20];
1698   char flags_buffer[40];
1699   const char *costly_str;
1700   const char *nop_str;
1701   const char *trace_str;
1702   const char *abi_str;
1703   const char *cmodel_str;
1704   struct cl_target_option cl_opts;
1705 
1706   /* Map enum rs6000_vector to string.  */
1707   static const char *rs6000_debug_vector_unit[] = {
1708     "none",
1709     "altivec",
1710     "vsx",
1711     "paired",
1712     "spe",
1713     "other"
1714   };
1715 
1716   fprintf (stderr, "Register information: (last virtual reg = %d)\n",
1717 	   LAST_VIRTUAL_REGISTER);
1718   rs6000_debug_reg_print (0, 31, "gr");
1719   rs6000_debug_reg_print (32, 63, "fp");
1720   rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO,
1721 			  LAST_ALTIVEC_REGNO,
1722 			  "vs");
1723   rs6000_debug_reg_print (LR_REGNO, LR_REGNO, "lr");
1724   rs6000_debug_reg_print (CTR_REGNO, CTR_REGNO, "ctr");
1725   rs6000_debug_reg_print (CR0_REGNO, CR7_REGNO, "cr");
1726   rs6000_debug_reg_print (CA_REGNO, CA_REGNO, "ca");
1727   rs6000_debug_reg_print (VRSAVE_REGNO, VRSAVE_REGNO, "vrsave");
1728   rs6000_debug_reg_print (VSCR_REGNO, VSCR_REGNO, "vscr");
1729   rs6000_debug_reg_print (SPE_ACC_REGNO, SPE_ACC_REGNO, "spe_a");
1730   rs6000_debug_reg_print (SPEFSCR_REGNO, SPEFSCR_REGNO, "spe_f");
1731 
1732   fprintf (stderr,
1733 	   "\n"
1734 	   "d  reg_class = %s\n"
1735 	   "f  reg_class = %s\n"
1736 	   "v  reg_class = %s\n"
1737 	   "wa reg_class = %s\n"
1738 	   "wd reg_class = %s\n"
1739 	   "wf reg_class = %s\n"
1740 	   "ws reg_class = %s\n\n",
1741 	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]],
1742 	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_f]],
1743 	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]],
1744 	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wa]],
1745 	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wd]],
1746 	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]],
1747 	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ws]]);
1748 
1749   for (m = 0; m < NUM_MACHINE_MODES; ++m)
1750     if (rs6000_vector_unit[m] || rs6000_vector_mem[m])
1751       {
1752 	nl = "\n";
1753 	fprintf (stderr, "Vector mode: %-5s arithmetic: %-8s move: %-8s\n",
1754 		 GET_MODE_NAME (m),
1755 		 rs6000_debug_vector_unit[ rs6000_vector_unit[m] ],
1756 		 rs6000_debug_vector_unit[ rs6000_vector_mem[m] ]);
1757       }
1758 
1759   if (nl)
1760     fputs (nl, stderr);
1761 
1762   if (rs6000_recip_control)
1763     {
1764       fprintf (stderr, "\nReciprocal mask = 0x%x\n", rs6000_recip_control);
1765 
1766       for (m = 0; m < NUM_MACHINE_MODES; ++m)
1767 	if (rs6000_recip_bits[m])
1768 	  {
1769 	    fprintf (stderr,
1770 		     "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
1771 		     GET_MODE_NAME (m),
1772 		     (RS6000_RECIP_AUTO_RE_P (m)
1773 		      ? "auto"
1774 		      : (RS6000_RECIP_HAVE_RE_P (m) ? "have" : "none")),
1775 		     (RS6000_RECIP_AUTO_RSQRTE_P (m)
1776 		      ? "auto"
1777 		      : (RS6000_RECIP_HAVE_RSQRTE_P (m) ? "have" : "none")));
1778 	  }
1779 
1780       fputs ("\n", stderr);
1781     }
1782 
1783   if (rs6000_cpu_index >= 0)
1784     {
1785       const char *name = processor_target_table[rs6000_cpu_index].name;
1786       HOST_WIDE_INT flags
1787 	= processor_target_table[rs6000_cpu_index].target_enable;
1788 
1789       sprintf (flags_buffer, "-mcpu=%s flags", name);
1790       rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
1791     }
1792   else
1793     fprintf (stderr, DEBUG_FMT_S, "cpu", "<none>");
1794 
1795   if (rs6000_tune_index >= 0)
1796     {
1797       const char *name = processor_target_table[rs6000_tune_index].name;
1798       HOST_WIDE_INT flags
1799 	= processor_target_table[rs6000_tune_index].target_enable;
1800 
1801       sprintf (flags_buffer, "-mtune=%s flags", name);
1802       rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
1803     }
1804   else
1805     fprintf (stderr, DEBUG_FMT_S, "tune", "<none>");
1806 
1807   cl_target_option_save (&cl_opts, &global_options);
1808   rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags",
1809 			    rs6000_isa_flags);
1810 
1811   rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags_explicit",
1812 			    rs6000_isa_flags_explicit);
1813 
1814   rs6000_print_builtin_options (stderr, 0, "rs6000_builtin_mask",
1815 				rs6000_builtin_mask);
1816 
1817   rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT);
1818 
1819   fprintf (stderr, DEBUG_FMT_S, "--with-cpu default",
1820 	   OPTION_TARGET_CPU_DEFAULT ? OPTION_TARGET_CPU_DEFAULT : "<none>");
1821 
1822   switch (rs6000_sched_costly_dep)
1823     {
1824     case max_dep_latency:
1825       costly_str = "max_dep_latency";
1826       break;
1827 
1828     case no_dep_costly:
1829       costly_str = "no_dep_costly";
1830       break;
1831 
1832     case all_deps_costly:
1833       costly_str = "all_deps_costly";
1834       break;
1835 
1836     case true_store_to_load_dep_costly:
1837       costly_str = "true_store_to_load_dep_costly";
1838       break;
1839 
1840     case store_to_load_dep_costly:
1841       costly_str = "store_to_load_dep_costly";
1842       break;
1843 
1844     default:
1845       costly_str = costly_num;
1846       sprintf (costly_num, "%d", (int)rs6000_sched_costly_dep);
1847       break;
1848     }
1849 
1850   fprintf (stderr, DEBUG_FMT_S, "sched_costly_dep", costly_str);
1851 
1852   switch (rs6000_sched_insert_nops)
1853     {
1854     case sched_finish_regroup_exact:
1855       nop_str = "sched_finish_regroup_exact";
1856       break;
1857 
1858     case sched_finish_pad_groups:
1859       nop_str = "sched_finish_pad_groups";
1860       break;
1861 
1862     case sched_finish_none:
1863       nop_str = "sched_finish_none";
1864       break;
1865 
1866     default:
1867       nop_str = nop_num;
1868       sprintf (nop_num, "%d", (int)rs6000_sched_insert_nops);
1869       break;
1870     }
1871 
1872   fprintf (stderr, DEBUG_FMT_S, "sched_insert_nops", nop_str);
1873 
1874   switch (rs6000_sdata)
1875     {
1876     default:
1877     case SDATA_NONE:
1878       break;
1879 
1880     case SDATA_DATA:
1881       fprintf (stderr, DEBUG_FMT_S, "sdata", "data");
1882       break;
1883 
1884     case SDATA_SYSV:
1885       fprintf (stderr, DEBUG_FMT_S, "sdata", "sysv");
1886       break;
1887 
1888     case SDATA_EABI:
1889       fprintf (stderr, DEBUG_FMT_S, "sdata", "eabi");
1890       break;
1891 
1892     }
1893 
1894   switch (rs6000_traceback)
1895     {
1896     case traceback_default:	trace_str = "default";	break;
1897     case traceback_none:	trace_str = "none";	break;
1898     case traceback_part:	trace_str = "part";	break;
1899     case traceback_full:	trace_str = "full";	break;
1900     default:			trace_str = "unknown";	break;
1901     }
1902 
1903   fprintf (stderr, DEBUG_FMT_S, "traceback", trace_str);
1904 
1905   switch (rs6000_current_cmodel)
1906     {
1907     case CMODEL_SMALL:	cmodel_str = "small";	break;
1908     case CMODEL_MEDIUM:	cmodel_str = "medium";	break;
1909     case CMODEL_LARGE:	cmodel_str = "large";	break;
1910     default:		cmodel_str = "unknown";	break;
1911     }
1912 
1913   fprintf (stderr, DEBUG_FMT_S, "cmodel", cmodel_str);
1914 
1915   switch (rs6000_current_abi)
1916     {
1917     case ABI_NONE:	abi_str = "none";	break;
1918     case ABI_AIX:	abi_str = "aix";	break;
1919     case ABI_V4:	abi_str = "V4";		break;
1920     case ABI_DARWIN:	abi_str = "darwin";	break;
1921     default:		abi_str = "unknown";	break;
1922     }
1923 
1924   fprintf (stderr, DEBUG_FMT_S, "abi", abi_str);
1925 
1926   if (rs6000_altivec_abi)
1927     fprintf (stderr, DEBUG_FMT_S, "altivec_abi", "true");
1928 
1929   if (rs6000_spe_abi)
1930     fprintf (stderr, DEBUG_FMT_S, "spe_abi", "true");
1931 
1932   if (rs6000_darwin64_abi)
1933     fprintf (stderr, DEBUG_FMT_S, "darwin64_abi", "true");
1934 
1935   if (rs6000_float_gprs)
1936     fprintf (stderr, DEBUG_FMT_S, "float_gprs", "true");
1937 
1938   if (TARGET_LINK_STACK)
1939     fprintf (stderr, DEBUG_FMT_S, "link_stack", "true");
1940 
1941   fprintf (stderr, DEBUG_FMT_S, "plt-format",
1942 	   TARGET_SECURE_PLT ? "secure" : "bss");
1943   fprintf (stderr, DEBUG_FMT_S, "struct-return",
1944 	   aix_struct_return ? "aix" : "sysv");
1945   fprintf (stderr, DEBUG_FMT_S, "always_hint", tf[!!rs6000_always_hint]);
1946   fprintf (stderr, DEBUG_FMT_S, "sched_groups", tf[!!rs6000_sched_groups]);
1947   fprintf (stderr, DEBUG_FMT_S, "align_branch",
1948 	   tf[!!rs6000_align_branch_targets]);
1949   fprintf (stderr, DEBUG_FMT_D, "tls_size", rs6000_tls_size);
1950   fprintf (stderr, DEBUG_FMT_D, "long_double_size",
1951 	   rs6000_long_double_type_size);
1952   fprintf (stderr, DEBUG_FMT_D, "sched_restricted_insns_priority",
1953 	   (int)rs6000_sched_restricted_insns_priority);
1954   fprintf (stderr, DEBUG_FMT_D, "Number of standard builtins",
1955 	   (int)END_BUILTINS);
1956   fprintf (stderr, DEBUG_FMT_D, "Number of rs6000 builtins",
1957 	   (int)RS6000_BUILTIN_COUNT);
1958 }
1959 
1960 /* Initialize the various global tables that are based on register size.  */
1961 static void
rs6000_init_hard_regno_mode_ok(bool global_init_p)1962 rs6000_init_hard_regno_mode_ok (bool global_init_p)
1963 {
1964   int r, m, c;
1965   int align64;
1966   int align32;
1967 
1968   /* Precalculate REGNO_REG_CLASS.  */
1969   rs6000_regno_regclass[0] = GENERAL_REGS;
1970   for (r = 1; r < 32; ++r)
1971     rs6000_regno_regclass[r] = BASE_REGS;
1972 
1973   for (r = 32; r < 64; ++r)
1974     rs6000_regno_regclass[r] = FLOAT_REGS;
1975 
1976   for (r = 64; r < FIRST_PSEUDO_REGISTER; ++r)
1977     rs6000_regno_regclass[r] = NO_REGS;
1978 
1979   for (r = FIRST_ALTIVEC_REGNO; r <= LAST_ALTIVEC_REGNO; ++r)
1980     rs6000_regno_regclass[r] = ALTIVEC_REGS;
1981 
1982   rs6000_regno_regclass[CR0_REGNO] = CR0_REGS;
1983   for (r = CR1_REGNO; r <= CR7_REGNO; ++r)
1984     rs6000_regno_regclass[r] = CR_REGS;
1985 
1986   rs6000_regno_regclass[LR_REGNO] = LINK_REGS;
1987   rs6000_regno_regclass[CTR_REGNO] = CTR_REGS;
1988   rs6000_regno_regclass[CA_REGNO] = CA_REGS;
1989   rs6000_regno_regclass[VRSAVE_REGNO] = VRSAVE_REGS;
1990   rs6000_regno_regclass[VSCR_REGNO] = VRSAVE_REGS;
1991   rs6000_regno_regclass[SPE_ACC_REGNO] = SPE_ACC_REGS;
1992   rs6000_regno_regclass[SPEFSCR_REGNO] = SPEFSCR_REGS;
1993   rs6000_regno_regclass[ARG_POINTER_REGNUM] = BASE_REGS;
1994   rs6000_regno_regclass[FRAME_POINTER_REGNUM] = BASE_REGS;
1995 
1996   /* Precalculate vector information, this must be set up before the
1997      rs6000_hard_regno_nregs_internal below.  */
1998   for (m = 0; m < NUM_MACHINE_MODES; ++m)
1999     {
2000       rs6000_vector_unit[m] = rs6000_vector_mem[m] = VECTOR_NONE;
2001       rs6000_vector_reload[m][0] = CODE_FOR_nothing;
2002       rs6000_vector_reload[m][1] = CODE_FOR_nothing;
2003     }
2004 
2005   for (c = 0; c < (int)(int)RS6000_CONSTRAINT_MAX; c++)
2006     rs6000_constraints[c] = NO_REGS;
2007 
2008   /* The VSX hardware allows native alignment for vectors, but control whether the compiler
2009      believes it can use native alignment or still uses 128-bit alignment.  */
2010   if (TARGET_VSX && !TARGET_VSX_ALIGN_128)
2011     {
2012       align64 = 64;
2013       align32 = 32;
2014     }
2015   else
2016     {
2017       align64 = 128;
2018       align32 = 128;
2019     }
2020 
2021   /* V2DF mode, VSX only.  */
2022   if (TARGET_VSX)
2023     {
2024       rs6000_vector_unit[V2DFmode] = VECTOR_VSX;
2025       rs6000_vector_mem[V2DFmode] = VECTOR_VSX;
2026       rs6000_vector_align[V2DFmode] = align64;
2027     }
2028 
2029   /* V4SF mode, either VSX or Altivec.  */
2030   if (TARGET_VSX)
2031     {
2032       rs6000_vector_unit[V4SFmode] = VECTOR_VSX;
2033       rs6000_vector_mem[V4SFmode] = VECTOR_VSX;
2034       rs6000_vector_align[V4SFmode] = align32;
2035     }
2036   else if (TARGET_ALTIVEC)
2037     {
2038       rs6000_vector_unit[V4SFmode] = VECTOR_ALTIVEC;
2039       rs6000_vector_mem[V4SFmode] = VECTOR_ALTIVEC;
2040       rs6000_vector_align[V4SFmode] = align32;
2041     }
2042 
2043   /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
2044      and stores. */
2045   if (TARGET_ALTIVEC)
2046     {
2047       rs6000_vector_unit[V4SImode] = VECTOR_ALTIVEC;
2048       rs6000_vector_unit[V8HImode] = VECTOR_ALTIVEC;
2049       rs6000_vector_unit[V16QImode] = VECTOR_ALTIVEC;
2050       rs6000_vector_align[V4SImode] = align32;
2051       rs6000_vector_align[V8HImode] = align32;
2052       rs6000_vector_align[V16QImode] = align32;
2053 
2054       if (TARGET_VSX)
2055 	{
2056 	  rs6000_vector_mem[V4SImode] = VECTOR_VSX;
2057 	  rs6000_vector_mem[V8HImode] = VECTOR_VSX;
2058 	  rs6000_vector_mem[V16QImode] = VECTOR_VSX;
2059 	}
2060       else
2061 	{
2062 	  rs6000_vector_mem[V4SImode] = VECTOR_ALTIVEC;
2063 	  rs6000_vector_mem[V8HImode] = VECTOR_ALTIVEC;
2064 	  rs6000_vector_mem[V16QImode] = VECTOR_ALTIVEC;
2065 	}
2066     }
2067 
2068   /* V2DImode, only allow under VSX, which can do V2DI insert/splat/extract.
2069      Altivec doesn't have 64-bit support.  */
2070   if (TARGET_VSX)
2071     {
2072       rs6000_vector_mem[V2DImode] = VECTOR_VSX;
2073       rs6000_vector_unit[V2DImode] = VECTOR_NONE;
2074       rs6000_vector_align[V2DImode] = align64;
2075     }
2076 
2077   /* DFmode, see if we want to use the VSX unit.  */
2078   if (TARGET_VSX && TARGET_VSX_SCALAR_DOUBLE)
2079     {
2080       rs6000_vector_unit[DFmode] = VECTOR_VSX;
2081       rs6000_vector_mem[DFmode]
2082 	= (TARGET_VSX_SCALAR_MEMORY ? VECTOR_VSX : VECTOR_NONE);
2083       rs6000_vector_align[DFmode] = align64;
2084     }
2085 
2086   /* TODO add SPE and paired floating point vector support.  */
2087 
2088   /* Register class constraints for the constraints that depend on compile
2089      switches.  */
2090   if (TARGET_HARD_FLOAT && TARGET_FPRS)
2091     rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS;
2092 
2093   if (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
2094     rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS;
2095 
2096   if (TARGET_VSX)
2097     {
2098       /* At present, we just use VSX_REGS, but we have different constraints
2099 	 based on the use, in case we want to fine tune the default register
2100 	 class used.  wa = any VSX register, wf = register class to use for
2101 	 V4SF, wd = register class to use for V2DF, and ws = register classs to
2102 	 use for DF scalars.  */
2103       rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
2104       rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS;
2105       rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS;
2106       rs6000_constraints[RS6000_CONSTRAINT_ws] = (TARGET_VSX_SCALAR_MEMORY
2107 						  ? VSX_REGS
2108 						  : FLOAT_REGS);
2109     }
2110 
2111   if (TARGET_ALTIVEC)
2112     rs6000_constraints[RS6000_CONSTRAINT_v] = ALTIVEC_REGS;
2113 
2114   /* Set up the reload helper functions.  */
2115   if (TARGET_VSX || TARGET_ALTIVEC)
2116     {
2117       if (TARGET_64BIT)
2118 	{
2119 	  rs6000_vector_reload[V16QImode][0] = CODE_FOR_reload_v16qi_di_store;
2120 	  rs6000_vector_reload[V16QImode][1] = CODE_FOR_reload_v16qi_di_load;
2121 	  rs6000_vector_reload[V8HImode][0]  = CODE_FOR_reload_v8hi_di_store;
2122 	  rs6000_vector_reload[V8HImode][1]  = CODE_FOR_reload_v8hi_di_load;
2123 	  rs6000_vector_reload[V4SImode][0]  = CODE_FOR_reload_v4si_di_store;
2124 	  rs6000_vector_reload[V4SImode][1]  = CODE_FOR_reload_v4si_di_load;
2125 	  rs6000_vector_reload[V2DImode][0]  = CODE_FOR_reload_v2di_di_store;
2126 	  rs6000_vector_reload[V2DImode][1]  = CODE_FOR_reload_v2di_di_load;
2127 	  rs6000_vector_reload[V4SFmode][0]  = CODE_FOR_reload_v4sf_di_store;
2128 	  rs6000_vector_reload[V4SFmode][1]  = CODE_FOR_reload_v4sf_di_load;
2129 	  rs6000_vector_reload[V2DFmode][0]  = CODE_FOR_reload_v2df_di_store;
2130 	  rs6000_vector_reload[V2DFmode][1]  = CODE_FOR_reload_v2df_di_load;
2131 	  if (TARGET_VSX && TARGET_VSX_SCALAR_MEMORY)
2132 	    {
2133 	      rs6000_vector_reload[DFmode][0]  = CODE_FOR_reload_df_di_store;
2134 	      rs6000_vector_reload[DFmode][1]  = CODE_FOR_reload_df_di_load;
2135 	    }
2136 	}
2137       else
2138 	{
2139 	  rs6000_vector_reload[V16QImode][0] = CODE_FOR_reload_v16qi_si_store;
2140 	  rs6000_vector_reload[V16QImode][1] = CODE_FOR_reload_v16qi_si_load;
2141 	  rs6000_vector_reload[V8HImode][0]  = CODE_FOR_reload_v8hi_si_store;
2142 	  rs6000_vector_reload[V8HImode][1]  = CODE_FOR_reload_v8hi_si_load;
2143 	  rs6000_vector_reload[V4SImode][0]  = CODE_FOR_reload_v4si_si_store;
2144 	  rs6000_vector_reload[V4SImode][1]  = CODE_FOR_reload_v4si_si_load;
2145 	  rs6000_vector_reload[V2DImode][0]  = CODE_FOR_reload_v2di_si_store;
2146 	  rs6000_vector_reload[V2DImode][1]  = CODE_FOR_reload_v2di_si_load;
2147 	  rs6000_vector_reload[V4SFmode][0]  = CODE_FOR_reload_v4sf_si_store;
2148 	  rs6000_vector_reload[V4SFmode][1]  = CODE_FOR_reload_v4sf_si_load;
2149 	  rs6000_vector_reload[V2DFmode][0]  = CODE_FOR_reload_v2df_si_store;
2150 	  rs6000_vector_reload[V2DFmode][1]  = CODE_FOR_reload_v2df_si_load;
2151 	  if (TARGET_VSX && TARGET_VSX_SCALAR_MEMORY)
2152 	    {
2153 	      rs6000_vector_reload[DFmode][0]  = CODE_FOR_reload_df_si_store;
2154 	      rs6000_vector_reload[DFmode][1]  = CODE_FOR_reload_df_si_load;
2155 	    }
2156 	}
2157     }
2158 
2159   /* Precalculate HARD_REGNO_NREGS.  */
2160   for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
2161     for (m = 0; m < NUM_MACHINE_MODES; ++m)
2162       rs6000_hard_regno_nregs[m][r]
2163 	= rs6000_hard_regno_nregs_internal (r, (enum machine_mode)m);
2164 
2165   /* Precalculate HARD_REGNO_MODE_OK.  */
2166   for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
2167     for (m = 0; m < NUM_MACHINE_MODES; ++m)
2168       if (rs6000_hard_regno_mode_ok (r, (enum machine_mode)m))
2169 	rs6000_hard_regno_mode_ok_p[m][r] = true;
2170 
2171   /* Precalculate CLASS_MAX_NREGS sizes.  */
2172   for (c = 0; c < LIM_REG_CLASSES; ++c)
2173     {
2174       int reg_size;
2175 
2176       if (TARGET_VSX && VSX_REG_CLASS_P (c))
2177 	reg_size = UNITS_PER_VSX_WORD;
2178 
2179       else if (c == ALTIVEC_REGS)
2180 	reg_size = UNITS_PER_ALTIVEC_WORD;
2181 
2182       else if (c == FLOAT_REGS)
2183 	reg_size = UNITS_PER_FP_WORD;
2184 
2185       else
2186 	reg_size = UNITS_PER_WORD;
2187 
2188       for (m = 0; m < NUM_MACHINE_MODES; ++m)
2189 	{
2190 	  int reg_size2 = reg_size;
2191 
2192 	  /* TFmode/TDmode always takes 2 registers, even in VSX.  */
2193 	  if (m == TDmode || m == TFmode)
2194 	    reg_size2 = UNITS_PER_FP_WORD;
2195 
2196 	  rs6000_class_max_nregs[m][c]
2197 	    = (GET_MODE_SIZE (m) + reg_size2 - 1) / reg_size2;
2198 	}
2199     }
2200 
2201   if (TARGET_E500_DOUBLE)
2202     rs6000_class_max_nregs[DFmode][GENERAL_REGS] = 1;
2203 
2204   /* Calculate which modes to automatically generate code to use a the
2205      reciprocal divide and square root instructions.  In the future, possibly
2206      automatically generate the instructions even if the user did not specify
2207      -mrecip.  The older machines double precision reciprocal sqrt estimate is
2208      not accurate enough.  */
2209   memset (rs6000_recip_bits, 0, sizeof (rs6000_recip_bits));
2210   if (TARGET_FRES)
2211     rs6000_recip_bits[SFmode] = RS6000_RECIP_MASK_HAVE_RE;
2212   if (TARGET_FRE)
2213     rs6000_recip_bits[DFmode] = RS6000_RECIP_MASK_HAVE_RE;
2214   if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
2215     rs6000_recip_bits[V4SFmode] = RS6000_RECIP_MASK_HAVE_RE;
2216   if (VECTOR_UNIT_VSX_P (V2DFmode))
2217     rs6000_recip_bits[V2DFmode] = RS6000_RECIP_MASK_HAVE_RE;
2218 
2219   if (TARGET_FRSQRTES)
2220     rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
2221   if (TARGET_FRSQRTE)
2222     rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
2223   if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
2224     rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
2225   if (VECTOR_UNIT_VSX_P (V2DFmode))
2226     rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
2227 
2228   if (rs6000_recip_control)
2229     {
2230       if (!flag_finite_math_only)
2231 	warning (0, "-mrecip requires -ffinite-math or -ffast-math");
2232       if (flag_trapping_math)
2233 	warning (0, "-mrecip requires -fno-trapping-math or -ffast-math");
2234       if (!flag_reciprocal_math)
2235 	warning (0, "-mrecip requires -freciprocal-math or -ffast-math");
2236       if (flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math)
2237 	{
2238 	  if (RS6000_RECIP_HAVE_RE_P (SFmode)
2239 	      && (rs6000_recip_control & RECIP_SF_DIV) != 0)
2240 	    rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
2241 
2242 	  if (RS6000_RECIP_HAVE_RE_P (DFmode)
2243 	      && (rs6000_recip_control & RECIP_DF_DIV) != 0)
2244 	    rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
2245 
2246 	  if (RS6000_RECIP_HAVE_RE_P (V4SFmode)
2247 	      && (rs6000_recip_control & RECIP_V4SF_DIV) != 0)
2248 	    rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
2249 
2250 	  if (RS6000_RECIP_HAVE_RE_P (V2DFmode)
2251 	      && (rs6000_recip_control & RECIP_V2DF_DIV) != 0)
2252 	    rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
2253 
2254 	  if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode)
2255 	      && (rs6000_recip_control & RECIP_SF_RSQRT) != 0)
2256 	    rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
2257 
2258 	  if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode)
2259 	      && (rs6000_recip_control & RECIP_DF_RSQRT) != 0)
2260 	    rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
2261 
2262 	  if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode)
2263 	      && (rs6000_recip_control & RECIP_V4SF_RSQRT) != 0)
2264 	    rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
2265 
2266 	  if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode)
2267 	      && (rs6000_recip_control & RECIP_V2DF_RSQRT) != 0)
2268 	    rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
2269 	}
2270     }
2271 
2272   if (global_init_p || TARGET_DEBUG_TARGET)
2273     {
2274       if (TARGET_DEBUG_REG)
2275 	rs6000_debug_reg_global ();
2276 
2277       if (TARGET_DEBUG_COST || TARGET_DEBUG_REG)
2278 	fprintf (stderr,
2279 		 "SImode variable mult cost       = %d\n"
2280 		 "SImode constant mult cost       = %d\n"
2281 		 "SImode short constant mult cost = %d\n"
2282 		 "DImode multipliciation cost     = %d\n"
2283 		 "SImode division cost            = %d\n"
2284 		 "DImode division cost            = %d\n"
2285 		 "Simple fp operation cost        = %d\n"
2286 		 "DFmode multiplication cost      = %d\n"
2287 		 "SFmode division cost            = %d\n"
2288 		 "DFmode division cost            = %d\n"
2289 		 "cache line size                 = %d\n"
2290 		 "l1 cache size                   = %d\n"
2291 		 "l2 cache size                   = %d\n"
2292 		 "simultaneous prefetches         = %d\n"
2293 		 "\n",
2294 		 rs6000_cost->mulsi,
2295 		 rs6000_cost->mulsi_const,
2296 		 rs6000_cost->mulsi_const9,
2297 		 rs6000_cost->muldi,
2298 		 rs6000_cost->divsi,
2299 		 rs6000_cost->divdi,
2300 		 rs6000_cost->fp,
2301 		 rs6000_cost->dmul,
2302 		 rs6000_cost->sdiv,
2303 		 rs6000_cost->ddiv,
2304 		 rs6000_cost->cache_line_size,
2305 		 rs6000_cost->l1_cache_size,
2306 		 rs6000_cost->l2_cache_size,
2307 		 rs6000_cost->simultaneous_prefetches);
2308     }
2309 }
2310 
2311 #if TARGET_MACHO
2312 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS.  */
2313 
2314 static void
darwin_rs6000_override_options(void)2315 darwin_rs6000_override_options (void)
2316 {
2317   /* The Darwin ABI always includes AltiVec, can't be (validly) turned
2318      off.  */
2319   rs6000_altivec_abi = 1;
2320   TARGET_ALTIVEC_VRSAVE = 1;
2321   rs6000_current_abi = ABI_DARWIN;
2322 
2323   if (DEFAULT_ABI == ABI_DARWIN
2324       && TARGET_64BIT)
2325       darwin_one_byte_bool = 1;
2326 
2327   if (TARGET_64BIT && ! TARGET_POWERPC64)
2328     {
2329       rs6000_isa_flags |= OPTION_MASK_POWERPC64;
2330       warning (0, "-m64 requires PowerPC64 architecture, enabling");
2331     }
2332   if (flag_mkernel)
2333     {
2334       rs6000_default_long_calls = 1;
2335       rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
2336     }
2337 
2338   /* Make -m64 imply -maltivec.  Darwin's 64-bit ABI includes
2339      Altivec.  */
2340   if (!flag_mkernel && !flag_apple_kext
2341       && TARGET_64BIT
2342       && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC))
2343     rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
2344 
2345   /* Unless the user (not the configurer) has explicitly overridden
2346      it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
2347      G4 unless targeting the kernel.  */
2348   if (!flag_mkernel
2349       && !flag_apple_kext
2350       && strverscmp (darwin_macosx_version_min, "10.5") >= 0
2351       && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC)
2352       && ! global_options_set.x_rs6000_cpu_index)
2353     {
2354       rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
2355     }
2356 }
2357 #endif
2358 
2359 /* If not otherwise specified by a target, make 'long double' equivalent to
2360    'double'.  */
2361 
2362 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
2363 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
2364 #endif
2365 
2366 /* Return the builtin mask of the various options used that could affect which
2367    builtins were used.  In the past we used target_flags, but we've run out of
2368    bits, and some options like SPE and PAIRED are no longer in
2369    target_flags.  */
2370 
2371 HOST_WIDE_INT
rs6000_builtin_mask_calculate(void)2372 rs6000_builtin_mask_calculate (void)
2373 {
2374   return (((TARGET_ALTIVEC)		    ? RS6000_BTM_ALTIVEC  : 0)
2375 	  | ((TARGET_VSX)		    ? RS6000_BTM_VSX	  : 0)
2376 	  | ((TARGET_SPE)		    ? RS6000_BTM_SPE	  : 0)
2377 	  | ((TARGET_PAIRED_FLOAT)	    ? RS6000_BTM_PAIRED	  : 0)
2378 	  | ((TARGET_FRE)		    ? RS6000_BTM_FRE	  : 0)
2379 	  | ((TARGET_FRES)		    ? RS6000_BTM_FRES	  : 0)
2380 	  | ((TARGET_FRSQRTE)		    ? RS6000_BTM_FRSQRTE  : 0)
2381 	  | ((TARGET_FRSQRTES)		    ? RS6000_BTM_FRSQRTES : 0)
2382 	  | ((TARGET_POPCNTD)		    ? RS6000_BTM_POPCNTD  : 0)
2383 	  | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL     : 0));
2384 }
2385 
2386 /* Override command line options.  Mostly we process the processor type and
2387    sometimes adjust other TARGET_ options.  */
2388 
2389 static bool
rs6000_option_override_internal(bool global_init_p)2390 rs6000_option_override_internal (bool global_init_p)
2391 {
2392   bool ret = true;
2393   bool have_cpu = false;
2394 
2395   /* The default cpu requested at configure time, if any.  */
2396   const char *implicit_cpu = OPTION_TARGET_CPU_DEFAULT;
2397 
2398   HOST_WIDE_INT set_masks;
2399   int cpu_index;
2400   int tune_index;
2401   struct cl_target_option *main_target_opt
2402     = ((global_init_p || target_option_default_node == NULL)
2403        ? NULL : TREE_TARGET_OPTION (target_option_default_node));
2404 
2405   /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
2406      library functions, so warn about it. The flag may be useful for
2407      performance studies from time to time though, so don't disable it
2408      entirely.  */
2409   if (global_options_set.x_rs6000_alignment_flags
2410       && rs6000_alignment_flags == MASK_ALIGN_POWER
2411       && DEFAULT_ABI == ABI_DARWIN
2412       && TARGET_64BIT)
2413     warning (0, "-malign-power is not supported for 64-bit Darwin;"
2414 	     " it is incompatible with the installed C and C++ libraries");
2415 
2416   /* Numerous experiment shows that IRA based loop pressure
2417      calculation works better for RTL loop invariant motion on targets
2418      with enough (>= 32) registers.  It is an expensive optimization.
2419      So it is on only for peak performance.  */
2420   if (optimize >= 3 && global_init_p)
2421     flag_ira_loop_pressure = 1;
2422 
2423   /* Set the pointer size.  */
2424   if (TARGET_64BIT)
2425     {
2426       rs6000_pmode = (int)DImode;
2427       rs6000_pointer_size = 64;
2428     }
2429   else
2430     {
2431       rs6000_pmode = (int)SImode;
2432       rs6000_pointer_size = 32;
2433     }
2434 
2435   /* Some OSs don't support saving the high part of 64-bit registers on context
2436      switch.  Other OSs don't support saving Altivec registers.  On those OSs,
2437      we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings;
2438      if the user wants either, the user must explicitly specify them and we
2439      won't interfere with the user's specification.  */
2440 
2441   set_masks = POWERPC_MASKS;
2442 #ifdef OS_MISSING_POWERPC64
2443   if (OS_MISSING_POWERPC64)
2444     set_masks &= ~OPTION_MASK_POWERPC64;
2445 #endif
2446 #ifdef OS_MISSING_ALTIVEC
2447   if (OS_MISSING_ALTIVEC)
2448     set_masks &= ~(OPTION_MASK_ALTIVEC | OPTION_MASK_VSX);
2449 #endif
2450 
2451   /* Don't override by the processor default if given explicitly.  */
2452   set_masks &= ~rs6000_isa_flags_explicit;
2453 
2454   /* Process the -mcpu=<xxx> and -mtune=<xxx> argument.  If the user changed
2455      the cpu in a target attribute or pragma, but did not specify a tuning
2456      option, use the cpu for the tuning option rather than the option specified
2457      with -mtune on the command line.  Process a '--with-cpu' configuration
2458      request as an implicit --cpu.  */
2459   if (rs6000_cpu_index >= 0)
2460     {
2461       cpu_index = rs6000_cpu_index;
2462       have_cpu = true;
2463     }
2464   else if (main_target_opt != NULL && main_target_opt->x_rs6000_cpu_index >= 0)
2465     {
2466       rs6000_cpu_index = cpu_index = main_target_opt->x_rs6000_cpu_index;
2467       have_cpu = true;
2468     }
2469   else if (implicit_cpu)
2470     {
2471       rs6000_cpu_index = cpu_index = rs6000_cpu_name_lookup (implicit_cpu);
2472       have_cpu = true;
2473     }
2474   else
2475     {
2476       const char *default_cpu = (TARGET_POWERPC64 ? "powerpc64" : "powerpc");
2477       rs6000_cpu_index = cpu_index = rs6000_cpu_name_lookup (default_cpu);
2478       have_cpu = false;
2479     }
2480 
2481   gcc_assert (cpu_index >= 0);
2482 
2483   /* If we have a cpu, either through an explicit -mcpu=<xxx> or if the
2484      compiler was configured with --with-cpu=<xxx>, replace all of the ISA bits
2485      with those from the cpu, except for options that were explicitly set.  If
2486      we don't have a cpu, do not override the target bits set in
2487      TARGET_DEFAULT.  */
2488   if (have_cpu)
2489     {
2490       rs6000_isa_flags &= ~set_masks;
2491       rs6000_isa_flags |= (processor_target_table[cpu_index].target_enable
2492 			   & set_masks);
2493     }
2494   else
2495     rs6000_isa_flags |= (processor_target_table[cpu_index].target_enable
2496 			 & ~rs6000_isa_flags_explicit);
2497 
2498   /* If no -mcpu=<xxx>, inherit any default options that were cleared via
2499      POWERPC_MASKS.  Originally, TARGET_DEFAULT was used to initialize
2500      target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook.  When we switched
2501      to using rs6000_isa_flags, we need to do the initialization here.  */
2502   if (!have_cpu)
2503     rs6000_isa_flags |= (TARGET_DEFAULT & ~rs6000_isa_flags_explicit);
2504 
2505   if (rs6000_tune_index >= 0)
2506     tune_index = rs6000_tune_index;
2507   else if (have_cpu)
2508     rs6000_tune_index = tune_index = cpu_index;
2509   else
2510     {
2511       size_t i;
2512       enum processor_type tune_proc
2513 	= (TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT);
2514 
2515       tune_index = -1;
2516       for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
2517 	if (processor_target_table[i].processor == tune_proc)
2518 	  {
2519 	    rs6000_tune_index = tune_index = i;
2520 	    break;
2521 	  }
2522     }
2523 
2524   gcc_assert (tune_index >= 0);
2525   rs6000_cpu = processor_target_table[tune_index].processor;
2526 
2527   /* Pick defaults for SPE related control flags.  Do this early to make sure
2528      that the TARGET_ macros are representative ASAP.  */
2529   {
2530     int spe_capable_cpu =
2531       (rs6000_cpu == PROCESSOR_PPC8540
2532        || rs6000_cpu == PROCESSOR_PPC8548);
2533 
2534     if (!global_options_set.x_rs6000_spe_abi)
2535       rs6000_spe_abi = spe_capable_cpu;
2536 
2537     if (!global_options_set.x_rs6000_spe)
2538       rs6000_spe = spe_capable_cpu;
2539 
2540     if (!global_options_set.x_rs6000_float_gprs)
2541       rs6000_float_gprs =
2542         (rs6000_cpu == PROCESSOR_PPC8540 ? 1
2543          : rs6000_cpu == PROCESSOR_PPC8548 ? 2
2544          : 0);
2545   }
2546 
2547   if (global_options_set.x_rs6000_spe_abi
2548       && rs6000_spe_abi
2549       && !TARGET_SPE_ABI)
2550     error ("not configured for SPE ABI");
2551 
2552   if (global_options_set.x_rs6000_spe
2553       && rs6000_spe
2554       && !TARGET_SPE)
2555     error ("not configured for SPE instruction set");
2556 
2557   if (main_target_opt != NULL
2558       && ((main_target_opt->x_rs6000_spe_abi != rs6000_spe_abi)
2559           || (main_target_opt->x_rs6000_spe != rs6000_spe)
2560           || (main_target_opt->x_rs6000_float_gprs != rs6000_float_gprs)))
2561     error ("target attribute or pragma changes SPE ABI");
2562 
2563   if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3
2564       || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64
2565       || rs6000_cpu == PROCESSOR_PPCE5500)
2566     {
2567       if (TARGET_ALTIVEC)
2568 	error ("AltiVec not supported in this target");
2569       if (TARGET_SPE)
2570 	error ("SPE not supported in this target");
2571     }
2572   if (rs6000_cpu == PROCESSOR_PPCE6500)
2573     {
2574       if (TARGET_SPE)
2575 	error ("SPE not supported in this target");
2576     }
2577 
2578   /* Disable Cell microcode if we are optimizing for the Cell
2579      and not optimizing for size.  */
2580   if (rs6000_gen_cell_microcode == -1)
2581     rs6000_gen_cell_microcode = !(rs6000_cpu == PROCESSOR_CELL
2582                                   && !optimize_size);
2583 
2584   /* If we are optimizing big endian systems for space and it's OK to
2585      use instructions that would be microcoded on the Cell, use the
2586      load/store multiple and string instructions.  */
2587   if (BYTES_BIG_ENDIAN && optimize_size && rs6000_gen_cell_microcode)
2588     rs6000_isa_flags |= ~rs6000_isa_flags_explicit & (OPTION_MASK_MULTIPLE
2589 						      | OPTION_MASK_STRING);
2590 
2591   /* Don't allow -mmultiple or -mstring on little endian systems
2592      unless the cpu is a 750, because the hardware doesn't support the
2593      instructions used in little endian mode, and causes an alignment
2594      trap.  The 750 does not cause an alignment trap (except when the
2595      target is unaligned).  */
2596 
2597   if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
2598     {
2599       if (TARGET_MULTIPLE)
2600 	{
2601 	  rs6000_isa_flags &= ~OPTION_MASK_MULTIPLE;
2602 	  if ((rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE) != 0)
2603 	    warning (0, "-mmultiple is not supported on little endian systems");
2604 	}
2605 
2606       if (TARGET_STRING)
2607 	{
2608 	  rs6000_isa_flags &= ~OPTION_MASK_STRING;
2609 	  if ((rs6000_isa_flags_explicit & OPTION_MASK_STRING) != 0)
2610 	    warning (0, "-mstring is not supported on little endian systems");
2611 	}
2612     }
2613 
2614   /* Add some warnings for VSX.  */
2615   if (TARGET_VSX)
2616     {
2617       const char *msg = NULL;
2618       if (!TARGET_HARD_FLOAT || !TARGET_FPRS
2619 	  || !TARGET_SINGLE_FLOAT || !TARGET_DOUBLE_FLOAT)
2620 	{
2621 	  if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
2622 	    msg = N_("-mvsx requires hardware floating point");
2623 	  else
2624 	    rs6000_isa_flags &= ~ OPTION_MASK_VSX;
2625 	}
2626       else if (TARGET_PAIRED_FLOAT)
2627 	msg = N_("-mvsx and -mpaired are incompatible");
2628       /* The hardware will allow VSX and little endian, but until we make sure
2629 	 things like vector select, etc. work don't allow VSX on little endian
2630 	 systems at this point.  */
2631       else if (!BYTES_BIG_ENDIAN)
2632 	msg = N_("-mvsx used with little endian code");
2633       else if (TARGET_AVOID_XFORM > 0)
2634 	msg = N_("-mvsx needs indexed addressing");
2635       else if (!TARGET_ALTIVEC && (rs6000_isa_flags_explicit
2636 				   & OPTION_MASK_ALTIVEC))
2637         {
2638 	  if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
2639 	    msg = N_("-mvsx and -mno-altivec are incompatible");
2640 	  else
2641 	    msg = N_("-mno-altivec disables vsx");
2642         }
2643 
2644       if (msg)
2645 	{
2646 	  warning (0, msg);
2647 	  rs6000_isa_flags &= ~ OPTION_MASK_VSX;
2648 	  rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
2649 	}
2650     }
2651 
2652   /* For the newer switches (vsx, dfp, etc.) set some of the older options,
2653      unless the user explicitly used the -mno-<option> to disable the code.  */
2654   if (TARGET_VSX)
2655     rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~rs6000_isa_flags_explicit);
2656   else if (TARGET_POPCNTD)
2657     rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~rs6000_isa_flags_explicit);
2658   else if (TARGET_DFP)
2659     rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~rs6000_isa_flags_explicit);
2660   else if (TARGET_CMPB)
2661     rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~rs6000_isa_flags_explicit);
2662   else if (TARGET_FPRND)
2663     rs6000_isa_flags |= (ISA_2_4_MASKS & ~rs6000_isa_flags_explicit);
2664   else if (TARGET_POPCNTB)
2665     rs6000_isa_flags |= (ISA_2_2_MASKS & ~rs6000_isa_flags_explicit);
2666   else if (TARGET_ALTIVEC)
2667     rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~rs6000_isa_flags_explicit);
2668 
2669   /* E500mc does "better" if we inline more aggressively.  Respect the
2670      user's opinion, though.  */
2671   if (rs6000_block_move_inline_limit == 0
2672       && (rs6000_cpu == PROCESSOR_PPCE500MC
2673 	  || rs6000_cpu == PROCESSOR_PPCE500MC64
2674 	  || rs6000_cpu == PROCESSOR_PPCE5500
2675 	  || rs6000_cpu == PROCESSOR_PPCE6500))
2676     rs6000_block_move_inline_limit = 128;
2677 
2678   /* store_one_arg depends on expand_block_move to handle at least the
2679      size of reg_parm_stack_space.  */
2680   if (rs6000_block_move_inline_limit < (TARGET_POWERPC64 ? 64 : 32))
2681     rs6000_block_move_inline_limit = (TARGET_POWERPC64 ? 64 : 32);
2682 
2683   if (global_init_p)
2684     {
2685       /* If the appropriate debug option is enabled, replace the target hooks
2686 	 with debug versions that call the real version and then prints
2687 	 debugging information.  */
2688       if (TARGET_DEBUG_COST)
2689 	{
2690 	  targetm.rtx_costs = rs6000_debug_rtx_costs;
2691 	  targetm.address_cost = rs6000_debug_address_cost;
2692 	  targetm.sched.adjust_cost = rs6000_debug_adjust_cost;
2693 	}
2694 
2695       if (TARGET_DEBUG_ADDR)
2696 	{
2697 	  targetm.legitimate_address_p = rs6000_debug_legitimate_address_p;
2698 	  targetm.legitimize_address = rs6000_debug_legitimize_address;
2699 	  rs6000_secondary_reload_class_ptr
2700 	    = rs6000_debug_secondary_reload_class;
2701 	  rs6000_secondary_memory_needed_ptr
2702 	    = rs6000_debug_secondary_memory_needed;
2703 	  rs6000_cannot_change_mode_class_ptr
2704 	    = rs6000_debug_cannot_change_mode_class;
2705 	  rs6000_preferred_reload_class_ptr
2706 	    = rs6000_debug_preferred_reload_class;
2707 	  rs6000_legitimize_reload_address_ptr
2708 	    = rs6000_debug_legitimize_reload_address;
2709 	  rs6000_mode_dependent_address_ptr
2710 	    = rs6000_debug_mode_dependent_address;
2711 	}
2712 
2713       if (rs6000_veclibabi_name)
2714 	{
2715 	  if (strcmp (rs6000_veclibabi_name, "mass") == 0)
2716 	    rs6000_veclib_handler = rs6000_builtin_vectorized_libmass;
2717 	  else
2718 	    {
2719 	      error ("unknown vectorization library ABI type (%s) for "
2720 		     "-mveclibabi= switch", rs6000_veclibabi_name);
2721 	      ret = false;
2722 	    }
2723 	}
2724     }
2725 
2726   if (!global_options_set.x_rs6000_long_double_type_size)
2727     {
2728       if (main_target_opt != NULL
2729 	  && (main_target_opt->x_rs6000_long_double_type_size
2730 	      != RS6000_DEFAULT_LONG_DOUBLE_SIZE))
2731 	error ("target attribute or pragma changes long double size");
2732       else
2733 	rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
2734     }
2735 
2736 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
2737   if (!global_options_set.x_rs6000_ieeequad)
2738     rs6000_ieeequad = 1;
2739 #endif
2740 
2741   /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
2742      target attribute or pragma which automatically enables both options,
2743      unless the altivec ABI was set.  This is set by default for 64-bit, but
2744      not for 32-bit.  */
2745   if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
2746     rs6000_isa_flags &= ~((OPTION_MASK_VSX | OPTION_MASK_ALTIVEC)
2747 			  & ~rs6000_isa_flags_explicit);
2748 
2749   /* Enable Altivec ABI for AIX -maltivec.  */
2750   if (TARGET_XCOFF && (TARGET_ALTIVEC || TARGET_VSX))
2751     {
2752       if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
2753 	error ("target attribute or pragma changes AltiVec ABI");
2754       else
2755 	rs6000_altivec_abi = 1;
2756     }
2757 
2758   /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux.  For
2759      PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI.  It can
2760      be explicitly overridden in either case.  */
2761   if (TARGET_ELF)
2762     {
2763       if (!global_options_set.x_rs6000_altivec_abi
2764 	  && (TARGET_64BIT || TARGET_ALTIVEC || TARGET_VSX))
2765 	{
2766 	  if (main_target_opt != NULL &&
2767 	      !main_target_opt->x_rs6000_altivec_abi)
2768 	    error ("target attribute or pragma changes AltiVec ABI");
2769 	  else
2770 	    rs6000_altivec_abi = 1;
2771 	}
2772     }
2773 
2774   /* Set the Darwin64 ABI as default for 64-bit Darwin.
2775      So far, the only darwin64 targets are also MACH-O.  */
2776   if (TARGET_MACHO
2777       && DEFAULT_ABI == ABI_DARWIN
2778       && TARGET_64BIT)
2779     {
2780       if (main_target_opt != NULL && !main_target_opt->x_rs6000_darwin64_abi)
2781 	error ("target attribute or pragma changes darwin64 ABI");
2782       else
2783 	{
2784 	  rs6000_darwin64_abi = 1;
2785 	  /* Default to natural alignment, for better performance.  */
2786 	  rs6000_alignment_flags = MASK_ALIGN_NATURAL;
2787 	}
2788     }
2789 
2790   /* Place FP constants in the constant pool instead of TOC
2791      if section anchors enabled.  */
2792   if (flag_section_anchors)
2793     TARGET_NO_FP_IN_TOC = 1;
2794 
2795 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2796   SUBTARGET_OVERRIDE_OPTIONS;
2797 #endif
2798 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2799   SUBSUBTARGET_OVERRIDE_OPTIONS;
2800 #endif
2801 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
2802   SUB3TARGET_OVERRIDE_OPTIONS;
2803 #endif
2804 
2805   /* For the E500 family of cores, reset the single/double FP flags to let us
2806      check that they remain constant across attributes or pragmas.  Also,
2807      clear a possible request for string instructions, not supported and which
2808      we might have silently queried above for -Os.
2809 
2810      For other families, clear ISEL in case it was set implicitly.
2811   */
2812 
2813   switch (rs6000_cpu)
2814     {
2815     case PROCESSOR_PPC8540:
2816     case PROCESSOR_PPC8548:
2817     case PROCESSOR_PPCE500MC:
2818     case PROCESSOR_PPCE500MC64:
2819     case PROCESSOR_PPCE5500:
2820     case PROCESSOR_PPCE6500:
2821 
2822       rs6000_single_float = TARGET_E500_SINGLE || TARGET_E500_DOUBLE;
2823       rs6000_double_float = TARGET_E500_DOUBLE;
2824 
2825       rs6000_isa_flags &= ~OPTION_MASK_STRING;
2826 
2827       break;
2828 
2829     default:
2830 
2831       if (have_cpu && !(rs6000_isa_flags_explicit & OPTION_MASK_ISEL))
2832 	rs6000_isa_flags &= ~OPTION_MASK_ISEL;
2833 
2834       break;
2835     }
2836 
2837   if (main_target_opt)
2838     {
2839       if (main_target_opt->x_rs6000_single_float != rs6000_single_float)
2840 	error ("target attribute or pragma changes single precision floating "
2841 	       "point");
2842       if (main_target_opt->x_rs6000_double_float != rs6000_double_float)
2843 	error ("target attribute or pragma changes double precision floating "
2844 	       "point");
2845     }
2846 
2847   /* Detect invalid option combinations with E500.  */
2848   CHECK_E500_OPTIONS;
2849 
2850   rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
2851 			&& rs6000_cpu != PROCESSOR_POWER5
2852 			&& rs6000_cpu != PROCESSOR_POWER6
2853 			&& rs6000_cpu != PROCESSOR_POWER7
2854 			&& rs6000_cpu != PROCESSOR_PPCA2
2855 			&& rs6000_cpu != PROCESSOR_CELL
2856 			&& rs6000_cpu != PROCESSOR_PPC476);
2857   rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
2858 			 || rs6000_cpu == PROCESSOR_POWER5
2859 			 || rs6000_cpu == PROCESSOR_POWER7);
2860   rs6000_align_branch_targets = (rs6000_cpu == PROCESSOR_POWER4
2861 				 || rs6000_cpu == PROCESSOR_POWER5
2862 				 || rs6000_cpu == PROCESSOR_POWER6
2863 				 || rs6000_cpu == PROCESSOR_POWER7
2864 				 || rs6000_cpu == PROCESSOR_PPCE500MC
2865 				 || rs6000_cpu == PROCESSOR_PPCE500MC64
2866 				 || rs6000_cpu == PROCESSOR_PPCE5500
2867 				 || rs6000_cpu == PROCESSOR_PPCE6500);
2868 
2869   /* Allow debug switches to override the above settings.  These are set to -1
2870      in rs6000.opt to indicate the user hasn't directly set the switch.  */
2871   if (TARGET_ALWAYS_HINT >= 0)
2872     rs6000_always_hint = TARGET_ALWAYS_HINT;
2873 
2874   if (TARGET_SCHED_GROUPS >= 0)
2875     rs6000_sched_groups = TARGET_SCHED_GROUPS;
2876 
2877   if (TARGET_ALIGN_BRANCH_TARGETS >= 0)
2878     rs6000_align_branch_targets = TARGET_ALIGN_BRANCH_TARGETS;
2879 
2880   rs6000_sched_restricted_insns_priority
2881     = (rs6000_sched_groups ? 1 : 0);
2882 
2883   /* Handle -msched-costly-dep option.  */
2884   rs6000_sched_costly_dep
2885     = (rs6000_sched_groups ? true_store_to_load_dep_costly : no_dep_costly);
2886 
2887   if (rs6000_sched_costly_dep_str)
2888     {
2889       if (! strcmp (rs6000_sched_costly_dep_str, "no"))
2890 	rs6000_sched_costly_dep = no_dep_costly;
2891       else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
2892 	rs6000_sched_costly_dep = all_deps_costly;
2893       else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
2894 	rs6000_sched_costly_dep = true_store_to_load_dep_costly;
2895       else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
2896 	rs6000_sched_costly_dep = store_to_load_dep_costly;
2897       else
2898 	rs6000_sched_costly_dep = ((enum rs6000_dependence_cost)
2899 				   atoi (rs6000_sched_costly_dep_str));
2900     }
2901 
2902   /* Handle -minsert-sched-nops option.  */
2903   rs6000_sched_insert_nops
2904     = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
2905 
2906   if (rs6000_sched_insert_nops_str)
2907     {
2908       if (! strcmp (rs6000_sched_insert_nops_str, "no"))
2909 	rs6000_sched_insert_nops = sched_finish_none;
2910       else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
2911 	rs6000_sched_insert_nops = sched_finish_pad_groups;
2912       else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
2913 	rs6000_sched_insert_nops = sched_finish_regroup_exact;
2914       else
2915 	rs6000_sched_insert_nops = ((enum rs6000_nop_insertion)
2916 				    atoi (rs6000_sched_insert_nops_str));
2917     }
2918 
2919   if (global_init_p)
2920     {
2921 #ifdef TARGET_REGNAMES
2922       /* If the user desires alternate register names, copy in the
2923 	 alternate names now.  */
2924       if (TARGET_REGNAMES)
2925 	memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
2926 #endif
2927 
2928       /* Set aix_struct_return last, after the ABI is determined.
2929 	 If -maix-struct-return or -msvr4-struct-return was explicitly
2930 	 used, don't override with the ABI default.  */
2931       if (!global_options_set.x_aix_struct_return)
2932 	aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
2933 
2934 #if 0
2935       /* IBM XL compiler defaults to unsigned bitfields.  */
2936       if (TARGET_XL_COMPAT)
2937 	flag_signed_bitfields = 0;
2938 #endif
2939 
2940       if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
2941 	REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
2942 
2943       if (TARGET_TOC)
2944 	ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
2945 
2946       /* We can only guarantee the availability of DI pseudo-ops when
2947 	 assembling for 64-bit targets.  */
2948       if (!TARGET_64BIT)
2949 	{
2950 	  targetm.asm_out.aligned_op.di = NULL;
2951 	  targetm.asm_out.unaligned_op.di = NULL;
2952 	}
2953 
2954 
2955       /* Set branch target alignment, if not optimizing for size.  */
2956       if (!optimize_size)
2957 	{
2958 	  /* Cell wants to be aligned 8byte for dual issue.  Titan wants to be
2959 	     aligned 8byte to avoid misprediction by the branch predictor.  */
2960 	  if (rs6000_cpu == PROCESSOR_TITAN
2961 	      || rs6000_cpu == PROCESSOR_CELL)
2962 	    {
2963 	      if (align_functions <= 0)
2964 		align_functions = 8;
2965 	      if (align_jumps <= 0)
2966 		align_jumps = 8;
2967 	      if (align_loops <= 0)
2968 		align_loops = 8;
2969 	    }
2970 	  if (rs6000_align_branch_targets)
2971 	    {
2972 	      if (align_functions <= 0)
2973 		align_functions = 16;
2974 	      if (align_jumps <= 0)
2975 		align_jumps = 16;
2976 	      if (align_loops <= 0)
2977 		{
2978 		  can_override_loop_align = 1;
2979 		  align_loops = 16;
2980 		}
2981 	    }
2982 	  if (align_jumps_max_skip <= 0)
2983 	    align_jumps_max_skip = 15;
2984 	  if (align_loops_max_skip <= 0)
2985 	    align_loops_max_skip = 15;
2986 	}
2987 
2988       /* Arrange to save and restore machine status around nested functions.  */
2989       init_machine_status = rs6000_init_machine_status;
2990 
2991       /* We should always be splitting complex arguments, but we can't break
2992 	 Linux and Darwin ABIs at the moment.  For now, only AIX is fixed.  */
2993       if (DEFAULT_ABI != ABI_AIX)
2994 	targetm.calls.split_complex_arg = NULL;
2995     }
2996 
2997   /* Initialize rs6000_cost with the appropriate target costs.  */
2998   if (optimize_size)
2999     rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
3000   else
3001     switch (rs6000_cpu)
3002       {
3003       case PROCESSOR_RS64A:
3004 	rs6000_cost = &rs64a_cost;
3005 	break;
3006 
3007       case PROCESSOR_MPCCORE:
3008 	rs6000_cost = &mpccore_cost;
3009 	break;
3010 
3011       case PROCESSOR_PPC403:
3012 	rs6000_cost = &ppc403_cost;
3013 	break;
3014 
3015       case PROCESSOR_PPC405:
3016 	rs6000_cost = &ppc405_cost;
3017 	break;
3018 
3019       case PROCESSOR_PPC440:
3020 	rs6000_cost = &ppc440_cost;
3021 	break;
3022 
3023       case PROCESSOR_PPC476:
3024 	rs6000_cost = &ppc476_cost;
3025 	break;
3026 
3027       case PROCESSOR_PPC601:
3028 	rs6000_cost = &ppc601_cost;
3029 	break;
3030 
3031       case PROCESSOR_PPC603:
3032 	rs6000_cost = &ppc603_cost;
3033 	break;
3034 
3035       case PROCESSOR_PPC604:
3036 	rs6000_cost = &ppc604_cost;
3037 	break;
3038 
3039       case PROCESSOR_PPC604e:
3040 	rs6000_cost = &ppc604e_cost;
3041 	break;
3042 
3043       case PROCESSOR_PPC620:
3044 	rs6000_cost = &ppc620_cost;
3045 	break;
3046 
3047       case PROCESSOR_PPC630:
3048 	rs6000_cost = &ppc630_cost;
3049 	break;
3050 
3051       case PROCESSOR_CELL:
3052 	rs6000_cost = &ppccell_cost;
3053 	break;
3054 
3055       case PROCESSOR_PPC750:
3056       case PROCESSOR_PPC7400:
3057 	rs6000_cost = &ppc750_cost;
3058 	break;
3059 
3060       case PROCESSOR_PPC7450:
3061 	rs6000_cost = &ppc7450_cost;
3062 	break;
3063 
3064       case PROCESSOR_PPC8540:
3065       case PROCESSOR_PPC8548:
3066 	rs6000_cost = &ppc8540_cost;
3067 	break;
3068 
3069       case PROCESSOR_PPCE300C2:
3070       case PROCESSOR_PPCE300C3:
3071 	rs6000_cost = &ppce300c2c3_cost;
3072 	break;
3073 
3074       case PROCESSOR_PPCE500MC:
3075 	rs6000_cost = &ppce500mc_cost;
3076 	break;
3077 
3078       case PROCESSOR_PPCE500MC64:
3079 	rs6000_cost = &ppce500mc64_cost;
3080 	break;
3081 
3082       case PROCESSOR_PPCE5500:
3083 	rs6000_cost = &ppce5500_cost;
3084 	break;
3085 
3086       case PROCESSOR_PPCE6500:
3087 	rs6000_cost = &ppce6500_cost;
3088 	break;
3089 
3090       case PROCESSOR_TITAN:
3091 	rs6000_cost = &titan_cost;
3092 	break;
3093 
3094       case PROCESSOR_POWER4:
3095       case PROCESSOR_POWER5:
3096 	rs6000_cost = &power4_cost;
3097 	break;
3098 
3099       case PROCESSOR_POWER6:
3100 	rs6000_cost = &power6_cost;
3101 	break;
3102 
3103       case PROCESSOR_POWER7:
3104 	rs6000_cost = &power7_cost;
3105 	break;
3106 
3107       case PROCESSOR_PPCA2:
3108 	rs6000_cost = &ppca2_cost;
3109 	break;
3110 
3111       default:
3112 	gcc_unreachable ();
3113       }
3114 
3115   if (global_init_p)
3116     {
3117       maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES,
3118 			     rs6000_cost->simultaneous_prefetches,
3119 			     global_options.x_param_values,
3120 			     global_options_set.x_param_values);
3121       maybe_set_param_value (PARAM_L1_CACHE_SIZE, rs6000_cost->l1_cache_size,
3122 			     global_options.x_param_values,
3123 			     global_options_set.x_param_values);
3124       maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE,
3125 			     rs6000_cost->cache_line_size,
3126 			     global_options.x_param_values,
3127 			     global_options_set.x_param_values);
3128       maybe_set_param_value (PARAM_L2_CACHE_SIZE, rs6000_cost->l2_cache_size,
3129 			     global_options.x_param_values,
3130 			     global_options_set.x_param_values);
3131 
3132       /* Increase loop peeling limits based on performance analysis. */
3133       maybe_set_param_value (PARAM_MAX_PEELED_INSNS, 400,
3134 			     global_options.x_param_values,
3135 			     global_options_set.x_param_values);
3136       maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS, 400,
3137 			     global_options.x_param_values,
3138 			     global_options_set.x_param_values);
3139 
3140       /* If using typedef char *va_list, signal that
3141 	 __builtin_va_start (&ap, 0) can be optimized to
3142 	 ap = __builtin_next_arg (0).  */
3143       if (DEFAULT_ABI != ABI_V4)
3144 	targetm.expand_builtin_va_start = NULL;
3145     }
3146 
3147   /* Set up single/double float flags.
3148      If TARGET_HARD_FLOAT is set, but neither single or double is set,
3149      then set both flags. */
3150   if (TARGET_HARD_FLOAT && TARGET_FPRS
3151       && rs6000_single_float == 0 && rs6000_double_float == 0)
3152     rs6000_single_float = rs6000_double_float = 1;
3153 
3154   /* If not explicitly specified via option, decide whether to generate indexed
3155      load/store instructions.  */
3156   if (TARGET_AVOID_XFORM == -1)
3157     /* Avoid indexed addressing when targeting Power6 in order to avoid the
3158      DERAT mispredict penalty.  However the LVE and STVE altivec instructions
3159      need indexed accesses and the type used is the scalar type of the element
3160      being loaded or stored.  */
3161     TARGET_AVOID_XFORM = (rs6000_cpu == PROCESSOR_POWER6 && TARGET_CMPB
3162 			  && !TARGET_ALTIVEC);
3163 
3164   /* Set the -mrecip options.  */
3165   if (rs6000_recip_name)
3166     {
3167       char *p = ASTRDUP (rs6000_recip_name);
3168       char *q;
3169       unsigned int mask, i;
3170       bool invert;
3171 
3172       while ((q = strtok (p, ",")) != NULL)
3173 	{
3174 	  p = NULL;
3175 	  if (*q == '!')
3176 	    {
3177 	      invert = true;
3178 	      q++;
3179 	    }
3180 	  else
3181 	    invert = false;
3182 
3183 	  if (!strcmp (q, "default"))
3184 	    mask = ((TARGET_RECIP_PRECISION)
3185 		    ? RECIP_HIGH_PRECISION : RECIP_LOW_PRECISION);
3186 	  else
3187 	    {
3188 	      for (i = 0; i < ARRAY_SIZE (recip_options); i++)
3189 		if (!strcmp (q, recip_options[i].string))
3190 		  {
3191 		    mask = recip_options[i].mask;
3192 		    break;
3193 		  }
3194 
3195 	      if (i == ARRAY_SIZE (recip_options))
3196 		{
3197 		  error ("unknown option for -mrecip=%s", q);
3198 		  invert = false;
3199 		  mask = 0;
3200 		  ret = false;
3201 		}
3202 	    }
3203 
3204 	  if (invert)
3205 	    rs6000_recip_control &= ~mask;
3206 	  else
3207 	    rs6000_recip_control |= mask;
3208 	}
3209     }
3210 
3211   /* Set the builtin mask of the various options used that could affect which
3212      builtins were used.  In the past we used target_flags, but we've run out
3213      of bits, and some options like SPE and PAIRED are no longer in
3214      target_flags.  */
3215   rs6000_builtin_mask = rs6000_builtin_mask_calculate ();
3216   if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
3217     {
3218       fprintf (stderr,
3219 	       "new builtin mask = " HOST_WIDE_INT_PRINT_HEX ", ",
3220 	       rs6000_builtin_mask);
3221       rs6000_print_builtin_options (stderr, 0, NULL, rs6000_builtin_mask);
3222     }
3223 
3224   /* Initialize all of the registers.  */
3225   rs6000_init_hard_regno_mode_ok (global_init_p);
3226 
3227   /* Save the initial options in case the user does function specific options */
3228   if (global_init_p)
3229     target_option_default_node = target_option_current_node
3230       = build_target_option_node ();
3231 
3232   /* If not explicitly specified via option, decide whether to generate the
3233      extra blr's required to preserve the link stack on some cpus (eg, 476).  */
3234   if (TARGET_LINK_STACK == -1)
3235     SET_TARGET_LINK_STACK (rs6000_cpu == PROCESSOR_PPC476 && flag_pic);
3236 
3237   return ret;
3238 }
3239 
3240 /* Implement TARGET_OPTION_OVERRIDE.  On the RS/6000 this is used to
3241    define the target cpu type.  */
3242 
3243 static void
rs6000_option_override(void)3244 rs6000_option_override (void)
3245 {
3246   (void) rs6000_option_override_internal (true);
3247 }
3248 
3249 
3250 /* Implement targetm.vectorize.builtin_mask_for_load.  */
3251 static tree
rs6000_builtin_mask_for_load(void)3252 rs6000_builtin_mask_for_load (void)
3253 {
3254   if (TARGET_ALTIVEC || TARGET_VSX)
3255     return altivec_builtin_mask_for_load;
3256   else
3257     return 0;
3258 }
3259 
3260 /* Implement LOOP_ALIGN. */
3261 int
rs6000_loop_align(rtx label)3262 rs6000_loop_align (rtx label)
3263 {
3264   basic_block bb;
3265   int ninsns;
3266 
3267   /* Don't override loop alignment if -falign-loops was specified. */
3268   if (!can_override_loop_align)
3269     return align_loops_log;
3270 
3271   bb = BLOCK_FOR_INSN (label);
3272   ninsns = num_loop_insns(bb->loop_father);
3273 
3274   /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
3275   if (ninsns > 4 && ninsns <= 8
3276       && (rs6000_cpu == PROCESSOR_POWER4
3277 	  || rs6000_cpu == PROCESSOR_POWER5
3278 	  || rs6000_cpu == PROCESSOR_POWER6
3279 	  || rs6000_cpu == PROCESSOR_POWER7))
3280     return 5;
3281   else
3282     return align_loops_log;
3283 }
3284 
3285 /* Implement TARGET_LOOP_ALIGN_MAX_SKIP. */
3286 static int
rs6000_loop_align_max_skip(rtx label)3287 rs6000_loop_align_max_skip (rtx label)
3288 {
3289   return (1 << rs6000_loop_align (label)) - 1;
3290 }
3291 
3292 /* Return true iff, data reference of TYPE can reach vector alignment (16)
3293    after applying N number of iterations.  This routine does not determine
3294    how may iterations are required to reach desired alignment.  */
3295 
3296 static bool
rs6000_vector_alignment_reachable(const_tree type ATTRIBUTE_UNUSED,bool is_packed)3297 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED, bool is_packed)
3298 {
3299   if (is_packed)
3300     return false;
3301 
3302   if (TARGET_32BIT)
3303     {
3304       if (rs6000_alignment_flags == MASK_ALIGN_NATURAL)
3305         return true;
3306 
3307       if (rs6000_alignment_flags ==  MASK_ALIGN_POWER)
3308         return true;
3309 
3310       return false;
3311     }
3312   else
3313     {
3314       if (TARGET_MACHO)
3315         return false;
3316 
3317       /* Assuming that all other types are naturally aligned. CHECKME!  */
3318       return true;
3319     }
3320 }
3321 
3322 /* Return true if the vector misalignment factor is supported by the
3323    target.  */
3324 static bool
rs6000_builtin_support_vector_misalignment(enum machine_mode mode,const_tree type,int misalignment,bool is_packed)3325 rs6000_builtin_support_vector_misalignment (enum machine_mode mode,
3326 					    const_tree type,
3327 					    int misalignment,
3328 					    bool is_packed)
3329 {
3330   if (TARGET_VSX)
3331     {
3332       /* Return if movmisalign pattern is not supported for this mode.  */
3333       if (optab_handler (movmisalign_optab, mode) == CODE_FOR_nothing)
3334         return false;
3335 
3336       if (misalignment == -1)
3337 	{
3338 	  /* Misalignment factor is unknown at compile time but we know
3339 	     it's word aligned.  */
3340 	  if (rs6000_vector_alignment_reachable (type, is_packed))
3341             {
3342               int element_size = TREE_INT_CST_LOW (TYPE_SIZE (type));
3343 
3344               if (element_size == 64 || element_size == 32)
3345                return true;
3346             }
3347 
3348 	  return false;
3349 	}
3350 
3351       /* VSX supports word-aligned vector.  */
3352       if (misalignment % 4 == 0)
3353 	return true;
3354     }
3355   return false;
3356 }
3357 
3358 /* Implement targetm.vectorize.builtin_vectorization_cost.  */
3359 static int
rs6000_builtin_vectorization_cost(enum vect_cost_for_stmt type_of_cost,tree vectype,int misalign)3360 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost,
3361                                    tree vectype, int misalign)
3362 {
3363   unsigned elements;
3364   tree elem_type;
3365 
3366   switch (type_of_cost)
3367     {
3368       case scalar_stmt:
3369       case scalar_load:
3370       case scalar_store:
3371       case vector_stmt:
3372       case vector_load:
3373       case vector_store:
3374       case vec_to_scalar:
3375       case scalar_to_vec:
3376       case cond_branch_not_taken:
3377         return 1;
3378 
3379       case vec_perm:
3380 	if (TARGET_VSX)
3381 	  return 3;
3382 	else
3383 	  return 1;
3384 
3385       case vec_promote_demote:
3386         if (TARGET_VSX)
3387           return 4;
3388         else
3389           return 1;
3390 
3391       case cond_branch_taken:
3392         return 3;
3393 
3394       case unaligned_load:
3395         if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
3396           {
3397             elements = TYPE_VECTOR_SUBPARTS (vectype);
3398             if (elements == 2)
3399               /* Double word aligned.  */
3400               return 2;
3401 
3402             if (elements == 4)
3403               {
3404                 switch (misalign)
3405                   {
3406                     case 8:
3407                       /* Double word aligned.  */
3408                       return 2;
3409 
3410                     case -1:
3411                       /* Unknown misalignment.  */
3412                     case 4:
3413                     case 12:
3414                       /* Word aligned.  */
3415                       return 22;
3416 
3417                     default:
3418                       gcc_unreachable ();
3419                   }
3420               }
3421           }
3422 
3423         if (TARGET_ALTIVEC)
3424           /* Misaligned loads are not supported.  */
3425           gcc_unreachable ();
3426 
3427         return 2;
3428 
3429       case unaligned_store:
3430         if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
3431           {
3432             elements = TYPE_VECTOR_SUBPARTS (vectype);
3433             if (elements == 2)
3434               /* Double word aligned.  */
3435               return 2;
3436 
3437             if (elements == 4)
3438               {
3439                 switch (misalign)
3440                   {
3441                     case 8:
3442                       /* Double word aligned.  */
3443                       return 2;
3444 
3445                     case -1:
3446                       /* Unknown misalignment.  */
3447                     case 4:
3448                     case 12:
3449                       /* Word aligned.  */
3450                       return 23;
3451 
3452                     default:
3453                       gcc_unreachable ();
3454                   }
3455               }
3456           }
3457 
3458         if (TARGET_ALTIVEC)
3459           /* Misaligned stores are not supported.  */
3460           gcc_unreachable ();
3461 
3462         return 2;
3463 
3464       case vec_construct:
3465 	elements = TYPE_VECTOR_SUBPARTS (vectype);
3466 	elem_type = TREE_TYPE (vectype);
3467 	/* 32-bit vectors loaded into registers are stored as double
3468 	   precision, so we need n/2 converts in addition to the usual
3469 	   n/2 merges to construct a vector of short floats from them.  */
3470 	if (SCALAR_FLOAT_TYPE_P (elem_type)
3471 	    && TYPE_PRECISION (elem_type) == 32)
3472 	  return elements + 1;
3473 	else
3474 	  return elements / 2 + 1;
3475 
3476       default:
3477         gcc_unreachable ();
3478     }
3479 }
3480 
3481 /* Implement targetm.vectorize.preferred_simd_mode.  */
3482 
3483 static enum machine_mode
rs6000_preferred_simd_mode(enum machine_mode mode)3484 rs6000_preferred_simd_mode (enum machine_mode mode)
3485 {
3486   if (TARGET_VSX)
3487     switch (mode)
3488       {
3489       case DFmode:
3490 	return V2DFmode;
3491       default:;
3492       }
3493   if (TARGET_ALTIVEC || TARGET_VSX)
3494     switch (mode)
3495       {
3496       case SFmode:
3497 	return V4SFmode;
3498       case DImode:
3499 	return V2DImode;
3500       case SImode:
3501 	return V4SImode;
3502       case HImode:
3503 	return V8HImode;
3504       case QImode:
3505 	return V16QImode;
3506       default:;
3507       }
3508   if (TARGET_SPE)
3509     switch (mode)
3510       {
3511       case SFmode:
3512 	return V2SFmode;
3513       case SImode:
3514 	return V2SImode;
3515       default:;
3516       }
3517   if (TARGET_PAIRED_FLOAT
3518       && mode == SFmode)
3519     return V2SFmode;
3520   return word_mode;
3521 }
3522 
3523 typedef struct _rs6000_cost_data
3524 {
3525   struct loop *loop_info;
3526   unsigned cost[3];
3527 } rs6000_cost_data;
3528 
3529 /* Test for likely overcommitment of vector hardware resources.  If a
3530    loop iteration is relatively large, and too large a percentage of
3531    instructions in the loop are vectorized, the cost model may not
3532    adequately reflect delays from unavailable vector resources.
3533    Penalize the loop body cost for this case.  */
3534 
3535 static void
rs6000_density_test(rs6000_cost_data * data)3536 rs6000_density_test (rs6000_cost_data *data)
3537 {
3538   const int DENSITY_PCT_THRESHOLD = 85;
3539   const int DENSITY_SIZE_THRESHOLD = 70;
3540   const int DENSITY_PENALTY = 10;
3541   struct loop *loop = data->loop_info;
3542   basic_block *bbs = get_loop_body (loop);
3543   int nbbs = loop->num_nodes;
3544   int vec_cost = data->cost[vect_body], not_vec_cost = 0;
3545   int i, density_pct;
3546 
3547   for (i = 0; i < nbbs; i++)
3548     {
3549       basic_block bb = bbs[i];
3550       gimple_stmt_iterator gsi;
3551 
3552       for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
3553 	{
3554 	  gimple stmt = gsi_stmt (gsi);
3555 	  stmt_vec_info stmt_info = vinfo_for_stmt (stmt);
3556 
3557 	  if (!STMT_VINFO_RELEVANT_P (stmt_info)
3558 	      && !STMT_VINFO_IN_PATTERN_P (stmt_info))
3559 	    not_vec_cost++;
3560 	}
3561     }
3562 
3563   free (bbs);
3564   density_pct = (vec_cost * 100) / (vec_cost + not_vec_cost);
3565 
3566   if (density_pct > DENSITY_PCT_THRESHOLD
3567       && vec_cost + not_vec_cost > DENSITY_SIZE_THRESHOLD)
3568     {
3569       data->cost[vect_body] = vec_cost * (100 + DENSITY_PENALTY) / 100;
3570       if (dump_enabled_p ())
3571 	dump_printf_loc (MSG_NOTE, vect_location,
3572 			 "density %d%%, cost %d exceeds threshold, penalizing "
3573 			 "loop body cost by %d%%", density_pct,
3574 			 vec_cost + not_vec_cost, DENSITY_PENALTY);
3575     }
3576 }
3577 
3578 /* Implement targetm.vectorize.init_cost.  */
3579 
3580 static void *
rs6000_init_cost(struct loop * loop_info)3581 rs6000_init_cost (struct loop *loop_info)
3582 {
3583   rs6000_cost_data *data = XNEW (struct _rs6000_cost_data);
3584   data->loop_info = loop_info;
3585   data->cost[vect_prologue] = 0;
3586   data->cost[vect_body]     = 0;
3587   data->cost[vect_epilogue] = 0;
3588   return data;
3589 }
3590 
3591 /* Implement targetm.vectorize.add_stmt_cost.  */
3592 
3593 static unsigned
rs6000_add_stmt_cost(void * data,int count,enum vect_cost_for_stmt kind,struct _stmt_vec_info * stmt_info,int misalign,enum vect_cost_model_location where)3594 rs6000_add_stmt_cost (void *data, int count, enum vect_cost_for_stmt kind,
3595 		      struct _stmt_vec_info *stmt_info, int misalign,
3596 		      enum vect_cost_model_location where)
3597 {
3598   rs6000_cost_data *cost_data = (rs6000_cost_data*) data;
3599   unsigned retval = 0;
3600 
3601   if (flag_vect_cost_model)
3602     {
3603       tree vectype = stmt_info ? stmt_vectype (stmt_info) : NULL_TREE;
3604       int stmt_cost = rs6000_builtin_vectorization_cost (kind, vectype,
3605 							 misalign);
3606       /* Statements in an inner loop relative to the loop being
3607 	 vectorized are weighted more heavily.  The value here is
3608 	 arbitrary and could potentially be improved with analysis.  */
3609       if (where == vect_body && stmt_info && stmt_in_inner_loop_p (stmt_info))
3610 	count *= 50;  /* FIXME.  */
3611 
3612       retval = (unsigned) (count * stmt_cost);
3613       cost_data->cost[where] += retval;
3614     }
3615 
3616   return retval;
3617 }
3618 
3619 /* Implement targetm.vectorize.finish_cost.  */
3620 
3621 static void
rs6000_finish_cost(void * data,unsigned * prologue_cost,unsigned * body_cost,unsigned * epilogue_cost)3622 rs6000_finish_cost (void *data, unsigned *prologue_cost,
3623 		    unsigned *body_cost, unsigned *epilogue_cost)
3624 {
3625   rs6000_cost_data *cost_data = (rs6000_cost_data*) data;
3626 
3627   if (cost_data->loop_info)
3628     rs6000_density_test (cost_data);
3629 
3630   *prologue_cost = cost_data->cost[vect_prologue];
3631   *body_cost     = cost_data->cost[vect_body];
3632   *epilogue_cost = cost_data->cost[vect_epilogue];
3633 }
3634 
3635 /* Implement targetm.vectorize.destroy_cost_data.  */
3636 
3637 static void
rs6000_destroy_cost_data(void * data)3638 rs6000_destroy_cost_data (void *data)
3639 {
3640   free (data);
3641 }
3642 
3643 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
3644    library with vectorized intrinsics.  */
3645 
3646 static tree
rs6000_builtin_vectorized_libmass(tree fndecl,tree type_out,tree type_in)3647 rs6000_builtin_vectorized_libmass (tree fndecl, tree type_out, tree type_in)
3648 {
3649   char name[32];
3650   const char *suffix = NULL;
3651   tree fntype, new_fndecl, bdecl = NULL_TREE;
3652   int n_args = 1;
3653   const char *bname;
3654   enum machine_mode el_mode, in_mode;
3655   int n, in_n;
3656 
3657   /* Libmass is suitable for unsafe math only as it does not correctly support
3658      parts of IEEE with the required precision such as denormals.  Only support
3659      it if we have VSX to use the simd d2 or f4 functions.
3660      XXX: Add variable length support.  */
3661   if (!flag_unsafe_math_optimizations || !TARGET_VSX)
3662     return NULL_TREE;
3663 
3664   el_mode = TYPE_MODE (TREE_TYPE (type_out));
3665   n = TYPE_VECTOR_SUBPARTS (type_out);
3666   in_mode = TYPE_MODE (TREE_TYPE (type_in));
3667   in_n = TYPE_VECTOR_SUBPARTS (type_in);
3668   if (el_mode != in_mode
3669       || n != in_n)
3670     return NULL_TREE;
3671 
3672   if (DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_NORMAL)
3673     {
3674       enum built_in_function fn = DECL_FUNCTION_CODE (fndecl);
3675       switch (fn)
3676 	{
3677 	case BUILT_IN_ATAN2:
3678 	case BUILT_IN_HYPOT:
3679 	case BUILT_IN_POW:
3680 	  n_args = 2;
3681 	  /* fall through */
3682 
3683 	case BUILT_IN_ACOS:
3684 	case BUILT_IN_ACOSH:
3685 	case BUILT_IN_ASIN:
3686 	case BUILT_IN_ASINH:
3687 	case BUILT_IN_ATAN:
3688 	case BUILT_IN_ATANH:
3689 	case BUILT_IN_CBRT:
3690 	case BUILT_IN_COS:
3691 	case BUILT_IN_COSH:
3692 	case BUILT_IN_ERF:
3693 	case BUILT_IN_ERFC:
3694 	case BUILT_IN_EXP2:
3695 	case BUILT_IN_EXP:
3696 	case BUILT_IN_EXPM1:
3697 	case BUILT_IN_LGAMMA:
3698 	case BUILT_IN_LOG10:
3699 	case BUILT_IN_LOG1P:
3700 	case BUILT_IN_LOG2:
3701 	case BUILT_IN_LOG:
3702 	case BUILT_IN_SIN:
3703 	case BUILT_IN_SINH:
3704 	case BUILT_IN_SQRT:
3705 	case BUILT_IN_TAN:
3706 	case BUILT_IN_TANH:
3707 	  bdecl = builtin_decl_implicit (fn);
3708 	  suffix = "d2";				/* pow -> powd2 */
3709 	  if (el_mode != DFmode
3710 	      || n != 2
3711 	      || !bdecl)
3712 	    return NULL_TREE;
3713 	  break;
3714 
3715 	case BUILT_IN_ATAN2F:
3716 	case BUILT_IN_HYPOTF:
3717 	case BUILT_IN_POWF:
3718 	  n_args = 2;
3719 	  /* fall through */
3720 
3721 	case BUILT_IN_ACOSF:
3722 	case BUILT_IN_ACOSHF:
3723 	case BUILT_IN_ASINF:
3724 	case BUILT_IN_ASINHF:
3725 	case BUILT_IN_ATANF:
3726 	case BUILT_IN_ATANHF:
3727 	case BUILT_IN_CBRTF:
3728 	case BUILT_IN_COSF:
3729 	case BUILT_IN_COSHF:
3730 	case BUILT_IN_ERFF:
3731 	case BUILT_IN_ERFCF:
3732 	case BUILT_IN_EXP2F:
3733 	case BUILT_IN_EXPF:
3734 	case BUILT_IN_EXPM1F:
3735 	case BUILT_IN_LGAMMAF:
3736 	case BUILT_IN_LOG10F:
3737 	case BUILT_IN_LOG1PF:
3738 	case BUILT_IN_LOG2F:
3739 	case BUILT_IN_LOGF:
3740 	case BUILT_IN_SINF:
3741 	case BUILT_IN_SINHF:
3742 	case BUILT_IN_SQRTF:
3743 	case BUILT_IN_TANF:
3744 	case BUILT_IN_TANHF:
3745 	  bdecl = builtin_decl_implicit (fn);
3746 	  suffix = "4";					/* powf -> powf4 */
3747 	  if (el_mode != SFmode
3748 	      || n != 4
3749 	      || !bdecl)
3750 	    return NULL_TREE;
3751 	  break;
3752 
3753 	default:
3754 	  return NULL_TREE;
3755 	}
3756     }
3757   else
3758     return NULL_TREE;
3759 
3760   gcc_assert (suffix != NULL);
3761   bname = IDENTIFIER_POINTER (DECL_NAME (bdecl));
3762   if (!bname)
3763     return NULL_TREE;
3764 
3765   strcpy (name, bname + sizeof ("__builtin_") - 1);
3766   strcat (name, suffix);
3767 
3768   if (n_args == 1)
3769     fntype = build_function_type_list (type_out, type_in, NULL);
3770   else if (n_args == 2)
3771     fntype = build_function_type_list (type_out, type_in, type_in, NULL);
3772   else
3773     gcc_unreachable ();
3774 
3775   /* Build a function declaration for the vectorized function.  */
3776   new_fndecl = build_decl (BUILTINS_LOCATION,
3777 			   FUNCTION_DECL, get_identifier (name), fntype);
3778   TREE_PUBLIC (new_fndecl) = 1;
3779   DECL_EXTERNAL (new_fndecl) = 1;
3780   DECL_IS_NOVOPS (new_fndecl) = 1;
3781   TREE_READONLY (new_fndecl) = 1;
3782 
3783   return new_fndecl;
3784 }
3785 
3786 /* Returns a function decl for a vectorized version of the builtin function
3787    with builtin function code FN and the result vector type TYPE, or NULL_TREE
3788    if it is not available.  */
3789 
3790 static tree
rs6000_builtin_vectorized_function(tree fndecl,tree type_out,tree type_in)3791 rs6000_builtin_vectorized_function (tree fndecl, tree type_out,
3792 				    tree type_in)
3793 {
3794   enum machine_mode in_mode, out_mode;
3795   int in_n, out_n;
3796 
3797   if (TARGET_DEBUG_BUILTIN)
3798     fprintf (stderr, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
3799 	     IDENTIFIER_POINTER (DECL_NAME (fndecl)),
3800 	     GET_MODE_NAME (TYPE_MODE (type_out)),
3801 	     GET_MODE_NAME (TYPE_MODE (type_in)));
3802 
3803   if (TREE_CODE (type_out) != VECTOR_TYPE
3804       || TREE_CODE (type_in) != VECTOR_TYPE
3805       || !TARGET_VECTORIZE_BUILTINS)
3806     return NULL_TREE;
3807 
3808   out_mode = TYPE_MODE (TREE_TYPE (type_out));
3809   out_n = TYPE_VECTOR_SUBPARTS (type_out);
3810   in_mode = TYPE_MODE (TREE_TYPE (type_in));
3811   in_n = TYPE_VECTOR_SUBPARTS (type_in);
3812 
3813   if (DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_NORMAL)
3814     {
3815       enum built_in_function fn = DECL_FUNCTION_CODE (fndecl);
3816       switch (fn)
3817 	{
3818 	case BUILT_IN_COPYSIGN:
3819 	  if (VECTOR_UNIT_VSX_P (V2DFmode)
3820 	      && out_mode == DFmode && out_n == 2
3821 	      && in_mode == DFmode && in_n == 2)
3822 	    return rs6000_builtin_decls[VSX_BUILTIN_CPSGNDP];
3823 	  break;
3824 	case BUILT_IN_COPYSIGNF:
3825 	  if (out_mode != SFmode || out_n != 4
3826 	      || in_mode != SFmode || in_n != 4)
3827 	    break;
3828 	  if (VECTOR_UNIT_VSX_P (V4SFmode))
3829 	    return rs6000_builtin_decls[VSX_BUILTIN_CPSGNSP];
3830 	  if (VECTOR_UNIT_ALTIVEC_P (V4SFmode))
3831 	    return rs6000_builtin_decls[ALTIVEC_BUILTIN_COPYSIGN_V4SF];
3832 	  break;
3833 	case BUILT_IN_SQRT:
3834 	  if (VECTOR_UNIT_VSX_P (V2DFmode)
3835 	      && out_mode == DFmode && out_n == 2
3836 	      && in_mode == DFmode && in_n == 2)
3837 	    return rs6000_builtin_decls[VSX_BUILTIN_XVSQRTDP];
3838 	  break;
3839 	case BUILT_IN_SQRTF:
3840 	  if (VECTOR_UNIT_VSX_P (V4SFmode)
3841 	      && out_mode == SFmode && out_n == 4
3842 	      && in_mode == SFmode && in_n == 4)
3843 	    return rs6000_builtin_decls[VSX_BUILTIN_XVSQRTSP];
3844 	  break;
3845 	case BUILT_IN_CEIL:
3846 	  if (VECTOR_UNIT_VSX_P (V2DFmode)
3847 	      && out_mode == DFmode && out_n == 2
3848 	      && in_mode == DFmode && in_n == 2)
3849 	    return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIP];
3850 	  break;
3851 	case BUILT_IN_CEILF:
3852 	  if (out_mode != SFmode || out_n != 4
3853 	      || in_mode != SFmode || in_n != 4)
3854 	    break;
3855 	  if (VECTOR_UNIT_VSX_P (V4SFmode))
3856 	    return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIP];
3857 	  if (VECTOR_UNIT_ALTIVEC_P (V4SFmode))
3858 	    return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIP];
3859 	  break;
3860 	case BUILT_IN_FLOOR:
3861 	  if (VECTOR_UNIT_VSX_P (V2DFmode)
3862 	      && out_mode == DFmode && out_n == 2
3863 	      && in_mode == DFmode && in_n == 2)
3864 	    return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIM];
3865 	  break;
3866 	case BUILT_IN_FLOORF:
3867 	  if (out_mode != SFmode || out_n != 4
3868 	      || in_mode != SFmode || in_n != 4)
3869 	    break;
3870 	  if (VECTOR_UNIT_VSX_P (V4SFmode))
3871 	    return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIM];
3872 	  if (VECTOR_UNIT_ALTIVEC_P (V4SFmode))
3873 	    return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIM];
3874 	  break;
3875 	case BUILT_IN_FMA:
3876 	  if (VECTOR_UNIT_VSX_P (V2DFmode)
3877 	      && out_mode == DFmode && out_n == 2
3878 	      && in_mode == DFmode && in_n == 2)
3879 	    return rs6000_builtin_decls[VSX_BUILTIN_XVMADDDP];
3880 	  break;
3881 	case BUILT_IN_FMAF:
3882 	  if (VECTOR_UNIT_VSX_P (V4SFmode)
3883 	      && out_mode == SFmode && out_n == 4
3884 	      && in_mode == SFmode && in_n == 4)
3885 	    return rs6000_builtin_decls[VSX_BUILTIN_XVMADDSP];
3886 	  else if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
3887 	      && out_mode == SFmode && out_n == 4
3888 	      && in_mode == SFmode && in_n == 4)
3889 	    return rs6000_builtin_decls[ALTIVEC_BUILTIN_VMADDFP];
3890 	  break;
3891 	case BUILT_IN_TRUNC:
3892 	  if (VECTOR_UNIT_VSX_P (V2DFmode)
3893 	      && out_mode == DFmode && out_n == 2
3894 	      && in_mode == DFmode && in_n == 2)
3895 	    return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIZ];
3896 	  break;
3897 	case BUILT_IN_TRUNCF:
3898 	  if (out_mode != SFmode || out_n != 4
3899 	      || in_mode != SFmode || in_n != 4)
3900 	    break;
3901 	  if (VECTOR_UNIT_VSX_P (V4SFmode))
3902 	    return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIZ];
3903 	  if (VECTOR_UNIT_ALTIVEC_P (V4SFmode))
3904 	    return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIZ];
3905 	  break;
3906 	case BUILT_IN_NEARBYINT:
3907 	  if (VECTOR_UNIT_VSX_P (V2DFmode)
3908 	      && flag_unsafe_math_optimizations
3909 	      && out_mode == DFmode && out_n == 2
3910 	      && in_mode == DFmode && in_n == 2)
3911 	    return rs6000_builtin_decls[VSX_BUILTIN_XVRDPI];
3912 	  break;
3913 	case BUILT_IN_NEARBYINTF:
3914 	  if (VECTOR_UNIT_VSX_P (V4SFmode)
3915 	      && flag_unsafe_math_optimizations
3916 	      && out_mode == SFmode && out_n == 4
3917 	      && in_mode == SFmode && in_n == 4)
3918 	    return rs6000_builtin_decls[VSX_BUILTIN_XVRSPI];
3919 	  break;
3920 	case BUILT_IN_RINT:
3921 	  if (VECTOR_UNIT_VSX_P (V2DFmode)
3922 	      && !flag_trapping_math
3923 	      && out_mode == DFmode && out_n == 2
3924 	      && in_mode == DFmode && in_n == 2)
3925 	    return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIC];
3926 	  break;
3927 	case BUILT_IN_RINTF:
3928 	  if (VECTOR_UNIT_VSX_P (V4SFmode)
3929 	      && !flag_trapping_math
3930 	      && out_mode == SFmode && out_n == 4
3931 	      && in_mode == SFmode && in_n == 4)
3932 	    return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIC];
3933 	  break;
3934 	default:
3935 	  break;
3936 	}
3937     }
3938 
3939   else if (DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_MD)
3940     {
3941       enum rs6000_builtins fn
3942 	= (enum rs6000_builtins)DECL_FUNCTION_CODE (fndecl);
3943       switch (fn)
3944 	{
3945 	case RS6000_BUILTIN_RSQRTF:
3946 	  if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
3947 	      && out_mode == SFmode && out_n == 4
3948 	      && in_mode == SFmode && in_n == 4)
3949 	    return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRSQRTFP];
3950 	  break;
3951 	case RS6000_BUILTIN_RSQRT:
3952 	  if (VECTOR_UNIT_VSX_P (V2DFmode)
3953 	      && out_mode == DFmode && out_n == 2
3954 	      && in_mode == DFmode && in_n == 2)
3955 	    return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
3956 	  break;
3957 	case RS6000_BUILTIN_RECIPF:
3958 	  if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
3959 	      && out_mode == SFmode && out_n == 4
3960 	      && in_mode == SFmode && in_n == 4)
3961 	    return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRECIPFP];
3962 	  break;
3963 	case RS6000_BUILTIN_RECIP:
3964 	  if (VECTOR_UNIT_VSX_P (V2DFmode)
3965 	      && out_mode == DFmode && out_n == 2
3966 	      && in_mode == DFmode && in_n == 2)
3967 	    return rs6000_builtin_decls[VSX_BUILTIN_RECIP_V2DF];
3968 	  break;
3969 	default:
3970 	  break;
3971 	}
3972     }
3973 
3974   /* Generate calls to libmass if appropriate.  */
3975   if (rs6000_veclib_handler)
3976     return rs6000_veclib_handler (fndecl, type_out, type_in);
3977 
3978   return NULL_TREE;
3979 }
3980 
3981 /* Default CPU string for rs6000*_file_start functions.  */
3982 static const char *rs6000_default_cpu;
3983 
3984 /* Do anything needed at the start of the asm file.  */
3985 
3986 static void
rs6000_file_start(void)3987 rs6000_file_start (void)
3988 {
3989   char buffer[80];
3990   const char *start = buffer;
3991   FILE *file = asm_out_file;
3992 
3993   rs6000_default_cpu = TARGET_CPU_DEFAULT;
3994 
3995   default_file_start ();
3996 
3997   if (flag_verbose_asm)
3998     {
3999       sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
4000 
4001       if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
4002 	{
4003 	  fprintf (file, "%s --with-cpu=%s", start, rs6000_default_cpu);
4004 	  start = "";
4005 	}
4006 
4007       if (global_options_set.x_rs6000_cpu_index)
4008 	{
4009 	  fprintf (file, "%s -mcpu=%s", start,
4010 		   processor_target_table[rs6000_cpu_index].name);
4011 	  start = "";
4012 	}
4013 
4014       if (global_options_set.x_rs6000_tune_index)
4015 	{
4016 	  fprintf (file, "%s -mtune=%s", start,
4017 		   processor_target_table[rs6000_tune_index].name);
4018 	  start = "";
4019 	}
4020 
4021       if (PPC405_ERRATUM77)
4022 	{
4023 	  fprintf (file, "%s PPC405CR_ERRATUM77", start);
4024 	  start = "";
4025 	}
4026 
4027 #ifdef USING_ELFOS_H
4028       switch (rs6000_sdata)
4029 	{
4030 	case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
4031 	case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
4032 	case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
4033 	case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
4034 	}
4035 
4036       if (rs6000_sdata && g_switch_value)
4037 	{
4038 	  fprintf (file, "%s -G %d", start,
4039 		   g_switch_value);
4040 	  start = "";
4041 	}
4042 #endif
4043 
4044       if (*start == '\0')
4045 	putc ('\n', file);
4046     }
4047 
4048   if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
4049     {
4050       switch_to_section (toc_section);
4051       switch_to_section (text_section);
4052     }
4053 }
4054 
4055 
4056 /* Return nonzero if this function is known to have a null epilogue.  */
4057 
4058 int
direct_return(void)4059 direct_return (void)
4060 {
4061   if (reload_completed)
4062     {
4063       rs6000_stack_t *info = rs6000_stack_info ();
4064 
4065       if (info->first_gp_reg_save == 32
4066 	  && info->first_fp_reg_save == 64
4067 	  && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
4068 	  && ! info->lr_save_p
4069 	  && ! info->cr_save_p
4070 	  && info->vrsave_mask == 0
4071 	  && ! info->push_p)
4072 	return 1;
4073     }
4074 
4075   return 0;
4076 }
4077 
4078 /* Return the number of instructions it takes to form a constant in an
4079    integer register.  */
4080 
4081 int
num_insns_constant_wide(HOST_WIDE_INT value)4082 num_insns_constant_wide (HOST_WIDE_INT value)
4083 {
4084   /* signed constant loadable with addi */
4085   if ((unsigned HOST_WIDE_INT) (value + 0x8000) < 0x10000)
4086     return 1;
4087 
4088   /* constant loadable with addis */
4089   else if ((value & 0xffff) == 0
4090 	   && (value >> 31 == -1 || value >> 31 == 0))
4091     return 1;
4092 
4093 #if HOST_BITS_PER_WIDE_INT == 64
4094   else if (TARGET_POWERPC64)
4095     {
4096       HOST_WIDE_INT low  = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
4097       HOST_WIDE_INT high = value >> 31;
4098 
4099       if (high == 0 || high == -1)
4100 	return 2;
4101 
4102       high >>= 1;
4103 
4104       if (low == 0)
4105 	return num_insns_constant_wide (high) + 1;
4106       else if (high == 0)
4107 	return num_insns_constant_wide (low) + 1;
4108       else
4109 	return (num_insns_constant_wide (high)
4110 		+ num_insns_constant_wide (low) + 1);
4111     }
4112 #endif
4113 
4114   else
4115     return 2;
4116 }
4117 
4118 int
num_insns_constant(rtx op,enum machine_mode mode)4119 num_insns_constant (rtx op, enum machine_mode mode)
4120 {
4121   HOST_WIDE_INT low, high;
4122 
4123   switch (GET_CODE (op))
4124     {
4125     case CONST_INT:
4126 #if HOST_BITS_PER_WIDE_INT == 64
4127       if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
4128 	  && mask64_operand (op, mode))
4129 	return 2;
4130       else
4131 #endif
4132 	return num_insns_constant_wide (INTVAL (op));
4133 
4134       case CONST_DOUBLE:
4135 	if (mode == SFmode || mode == SDmode)
4136 	  {
4137 	    long l;
4138 	    REAL_VALUE_TYPE rv;
4139 
4140 	    REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
4141 	    if (DECIMAL_FLOAT_MODE_P (mode))
4142 	      REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
4143 	    else
4144 	      REAL_VALUE_TO_TARGET_SINGLE (rv, l);
4145 	    return num_insns_constant_wide ((HOST_WIDE_INT) l);
4146 	  }
4147 
4148 	if (mode == VOIDmode || mode == DImode)
4149 	  {
4150 	    high = CONST_DOUBLE_HIGH (op);
4151 	    low  = CONST_DOUBLE_LOW (op);
4152 	  }
4153 	else
4154 	  {
4155 	    long l[2];
4156 	    REAL_VALUE_TYPE rv;
4157 
4158 	    REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
4159 	    if (DECIMAL_FLOAT_MODE_P (mode))
4160 	      REAL_VALUE_TO_TARGET_DECIMAL64 (rv, l);
4161 	    else
4162 	      REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
4163 	    high = l[WORDS_BIG_ENDIAN == 0];
4164 	    low  = l[WORDS_BIG_ENDIAN != 0];
4165 	  }
4166 
4167 	if (TARGET_32BIT)
4168 	  return (num_insns_constant_wide (low)
4169 		  + num_insns_constant_wide (high));
4170 	else
4171 	  {
4172 	    if ((high == 0 && low >= 0)
4173 		|| (high == -1 && low < 0))
4174 	      return num_insns_constant_wide (low);
4175 
4176 	    else if (mask64_operand (op, mode))
4177 	      return 2;
4178 
4179 	    else if (low == 0)
4180 	      return num_insns_constant_wide (high) + 1;
4181 
4182 	    else
4183 	      return (num_insns_constant_wide (high)
4184 		      + num_insns_constant_wide (low) + 1);
4185 	  }
4186 
4187     default:
4188       gcc_unreachable ();
4189     }
4190 }
4191 
4192 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
4193    If the mode of OP is MODE_VECTOR_INT, this simply returns the
4194    corresponding element of the vector, but for V4SFmode and V2SFmode,
4195    the corresponding "float" is interpreted as an SImode integer.  */
4196 
4197 HOST_WIDE_INT
const_vector_elt_as_int(rtx op,unsigned int elt)4198 const_vector_elt_as_int (rtx op, unsigned int elt)
4199 {
4200   rtx tmp;
4201 
4202   /* We can't handle V2DImode and V2DFmode vector constants here yet.  */
4203   gcc_assert (GET_MODE (op) != V2DImode
4204 	      && GET_MODE (op) != V2DFmode);
4205 
4206   tmp = CONST_VECTOR_ELT (op, elt);
4207   if (GET_MODE (op) == V4SFmode
4208       || GET_MODE (op) == V2SFmode)
4209     tmp = gen_lowpart (SImode, tmp);
4210   return INTVAL (tmp);
4211 }
4212 
4213 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
4214    or vspltisw instruction.  OP is a CONST_VECTOR.  Which instruction is used
4215    depends on STEP and COPIES, one of which will be 1.  If COPIES > 1,
4216    all items are set to the same value and contain COPIES replicas of the
4217    vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
4218    operand and the others are set to the value of the operand's msb.  */
4219 
4220 static bool
vspltis_constant(rtx op,unsigned step,unsigned copies)4221 vspltis_constant (rtx op, unsigned step, unsigned copies)
4222 {
4223   enum machine_mode mode = GET_MODE (op);
4224   enum machine_mode inner = GET_MODE_INNER (mode);
4225 
4226   unsigned i;
4227   unsigned nunits;
4228   unsigned bitsize;
4229   unsigned mask;
4230 
4231   HOST_WIDE_INT val;
4232   HOST_WIDE_INT splat_val;
4233   HOST_WIDE_INT msb_val;
4234 
4235   if (mode == V2DImode || mode == V2DFmode)
4236     return false;
4237 
4238   nunits = GET_MODE_NUNITS (mode);
4239   bitsize = GET_MODE_BITSIZE (inner);
4240   mask = GET_MODE_MASK (inner);
4241 
4242   val = const_vector_elt_as_int (op, nunits - 1);
4243   splat_val = val;
4244   msb_val = val > 0 ? 0 : -1;
4245 
4246   /* Construct the value to be splatted, if possible.  If not, return 0.  */
4247   for (i = 2; i <= copies; i *= 2)
4248     {
4249       HOST_WIDE_INT small_val;
4250       bitsize /= 2;
4251       small_val = splat_val >> bitsize;
4252       mask >>= bitsize;
4253       if (splat_val != ((small_val << bitsize) | (small_val & mask)))
4254 	return false;
4255       splat_val = small_val;
4256     }
4257 
4258   /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw].  */
4259   if (EASY_VECTOR_15 (splat_val))
4260     ;
4261 
4262   /* Also check if we can splat, and then add the result to itself.  Do so if
4263      the value is positive, of if the splat instruction is using OP's mode;
4264      for splat_val < 0, the splat and the add should use the same mode.  */
4265   else if (EASY_VECTOR_15_ADD_SELF (splat_val)
4266            && (splat_val >= 0 || (step == 1 && copies == 1)))
4267     ;
4268 
4269   /* Also check if are loading up the most significant bit which can be done by
4270      loading up -1 and shifting the value left by -1.  */
4271   else if (EASY_VECTOR_MSB (splat_val, inner))
4272     ;
4273 
4274   else
4275     return false;
4276 
4277   /* Check if VAL is present in every STEP-th element, and the
4278      other elements are filled with its most significant bit.  */
4279   for (i = 0; i < nunits - 1; ++i)
4280     {
4281       HOST_WIDE_INT desired_val;
4282       if (((i + 1) & (step - 1)) == 0)
4283 	desired_val = val;
4284       else
4285 	desired_val = msb_val;
4286 
4287       if (desired_val != const_vector_elt_as_int (op, i))
4288 	return false;
4289     }
4290 
4291   return true;
4292 }
4293 
4294 
4295 /* Return true if OP is of the given MODE and can be synthesized
4296    with a vspltisb, vspltish or vspltisw.  */
4297 
4298 bool
easy_altivec_constant(rtx op,enum machine_mode mode)4299 easy_altivec_constant (rtx op, enum machine_mode mode)
4300 {
4301   unsigned step, copies;
4302 
4303   if (mode == VOIDmode)
4304     mode = GET_MODE (op);
4305   else if (mode != GET_MODE (op))
4306     return false;
4307 
4308   /* V2DI/V2DF was added with VSX.  Only allow 0 and all 1's as easy
4309      constants.  */
4310   if (mode == V2DFmode)
4311     return zero_constant (op, mode);
4312 
4313   if (mode == V2DImode)
4314     {
4315       /* In case the compiler is built 32-bit, CONST_DOUBLE constants are not
4316 	 easy.  */
4317       if (GET_CODE (CONST_VECTOR_ELT (op, 0)) != CONST_INT
4318 	  || GET_CODE (CONST_VECTOR_ELT (op, 1)) != CONST_INT)
4319 	return false;
4320 
4321       if (zero_constant (op, mode))
4322 	return true;
4323 
4324       if (INTVAL (CONST_VECTOR_ELT (op, 0)) == -1
4325 	  && INTVAL (CONST_VECTOR_ELT (op, 1)) == -1)
4326 	return true;
4327 
4328       return false;
4329     }
4330 
4331   /* Start with a vspltisw.  */
4332   step = GET_MODE_NUNITS (mode) / 4;
4333   copies = 1;
4334 
4335   if (vspltis_constant (op, step, copies))
4336     return true;
4337 
4338   /* Then try with a vspltish.  */
4339   if (step == 1)
4340     copies <<= 1;
4341   else
4342     step >>= 1;
4343 
4344   if (vspltis_constant (op, step, copies))
4345     return true;
4346 
4347   /* And finally a vspltisb.  */
4348   if (step == 1)
4349     copies <<= 1;
4350   else
4351     step >>= 1;
4352 
4353   if (vspltis_constant (op, step, copies))
4354     return true;
4355 
4356   return false;
4357 }
4358 
4359 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
4360    result is OP.  Abort if it is not possible.  */
4361 
4362 rtx
gen_easy_altivec_constant(rtx op)4363 gen_easy_altivec_constant (rtx op)
4364 {
4365   enum machine_mode mode = GET_MODE (op);
4366   int nunits = GET_MODE_NUNITS (mode);
4367   rtx last = CONST_VECTOR_ELT (op, nunits - 1);
4368   unsigned step = nunits / 4;
4369   unsigned copies = 1;
4370 
4371   /* Start with a vspltisw.  */
4372   if (vspltis_constant (op, step, copies))
4373     return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, last));
4374 
4375   /* Then try with a vspltish.  */
4376   if (step == 1)
4377     copies <<= 1;
4378   else
4379     step >>= 1;
4380 
4381   if (vspltis_constant (op, step, copies))
4382     return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, last));
4383 
4384   /* And finally a vspltisb.  */
4385   if (step == 1)
4386     copies <<= 1;
4387   else
4388     step >>= 1;
4389 
4390   if (vspltis_constant (op, step, copies))
4391     return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, last));
4392 
4393   gcc_unreachable ();
4394 }
4395 
4396 const char *
output_vec_const_move(rtx * operands)4397 output_vec_const_move (rtx *operands)
4398 {
4399   int cst, cst2;
4400   enum machine_mode mode;
4401   rtx dest, vec;
4402 
4403   dest = operands[0];
4404   vec = operands[1];
4405   mode = GET_MODE (dest);
4406 
4407   if (TARGET_VSX)
4408     {
4409       if (zero_constant (vec, mode))
4410 	return "xxlxor %x0,%x0,%x0";
4411 
4412       if (mode == V2DImode
4413 	  && INTVAL (CONST_VECTOR_ELT (vec, 0)) == -1
4414 	  && INTVAL (CONST_VECTOR_ELT (vec, 1)) == -1)
4415 	return "vspltisw %0,-1";
4416     }
4417 
4418   if (TARGET_ALTIVEC)
4419     {
4420       rtx splat_vec;
4421       if (zero_constant (vec, mode))
4422 	return "vxor %0,%0,%0";
4423 
4424       splat_vec = gen_easy_altivec_constant (vec);
4425       gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
4426       operands[1] = XEXP (splat_vec, 0);
4427       if (!EASY_VECTOR_15 (INTVAL (operands[1])))
4428 	return "#";
4429 
4430       switch (GET_MODE (splat_vec))
4431 	{
4432 	case V4SImode:
4433 	  return "vspltisw %0,%1";
4434 
4435 	case V8HImode:
4436 	  return "vspltish %0,%1";
4437 
4438 	case V16QImode:
4439 	  return "vspltisb %0,%1";
4440 
4441 	default:
4442 	  gcc_unreachable ();
4443 	}
4444     }
4445 
4446   gcc_assert (TARGET_SPE);
4447 
4448   /* Vector constant 0 is handled as a splitter of V2SI, and in the
4449      pattern of V1DI, V4HI, and V2SF.
4450 
4451      FIXME: We should probably return # and add post reload
4452      splitters for these, but this way is so easy ;-).  */
4453   cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
4454   cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
4455   operands[1] = CONST_VECTOR_ELT (vec, 0);
4456   operands[2] = CONST_VECTOR_ELT (vec, 1);
4457   if (cst == cst2)
4458     return "li %0,%1\n\tevmergelo %0,%0,%0";
4459   else
4460     return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
4461 }
4462 
4463 /* Initialize TARGET of vector PAIRED to VALS.  */
4464 
4465 void
paired_expand_vector_init(rtx target,rtx vals)4466 paired_expand_vector_init (rtx target, rtx vals)
4467 {
4468   enum machine_mode mode = GET_MODE (target);
4469   int n_elts = GET_MODE_NUNITS (mode);
4470   int n_var = 0;
4471   rtx x, new_rtx, tmp, constant_op, op1, op2;
4472   int i;
4473 
4474   for (i = 0; i < n_elts; ++i)
4475     {
4476       x = XVECEXP (vals, 0, i);
4477       if (!(CONST_INT_P (x)
4478 	    || GET_CODE (x) == CONST_DOUBLE
4479 	    || GET_CODE (x) == CONST_FIXED))
4480 	++n_var;
4481     }
4482   if (n_var == 0)
4483     {
4484       /* Load from constant pool.  */
4485       emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
4486       return;
4487     }
4488 
4489   if (n_var == 2)
4490     {
4491       /* The vector is initialized only with non-constants.  */
4492       new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, XVECEXP (vals, 0, 0),
4493 				XVECEXP (vals, 0, 1));
4494 
4495       emit_move_insn (target, new_rtx);
4496       return;
4497     }
4498 
4499   /* One field is non-constant and the other one is a constant.  Load the
4500      constant from the constant pool and use ps_merge instruction to
4501      construct the whole vector.  */
4502   op1 = XVECEXP (vals, 0, 0);
4503   op2 = XVECEXP (vals, 0, 1);
4504 
4505   constant_op = (CONSTANT_P (op1)) ? op1 : op2;
4506 
4507   tmp = gen_reg_rtx (GET_MODE (constant_op));
4508   emit_move_insn (tmp, constant_op);
4509 
4510   if (CONSTANT_P (op1))
4511     new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, tmp, op2);
4512   else
4513     new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, op1, tmp);
4514 
4515   emit_move_insn (target, new_rtx);
4516 }
4517 
4518 void
paired_expand_vector_move(rtx operands[])4519 paired_expand_vector_move (rtx operands[])
4520 {
4521   rtx op0 = operands[0], op1 = operands[1];
4522 
4523   emit_move_insn (op0, op1);
4524 }
4525 
4526 /* Emit vector compare for code RCODE.  DEST is destination, OP1 and
4527    OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two
4528    operands for the relation operation COND.  This is a recursive
4529    function.  */
4530 
4531 static void
paired_emit_vector_compare(enum rtx_code rcode,rtx dest,rtx op0,rtx op1,rtx cc_op0,rtx cc_op1)4532 paired_emit_vector_compare (enum rtx_code rcode,
4533                             rtx dest, rtx op0, rtx op1,
4534                             rtx cc_op0, rtx cc_op1)
4535 {
4536   rtx tmp = gen_reg_rtx (V2SFmode);
4537   rtx tmp1, max, min;
4538 
4539   gcc_assert (TARGET_PAIRED_FLOAT);
4540   gcc_assert (GET_MODE (op0) == GET_MODE (op1));
4541 
4542   switch (rcode)
4543     {
4544     case LT:
4545     case LTU:
4546       paired_emit_vector_compare (GE, dest, op1, op0, cc_op0, cc_op1);
4547       return;
4548     case GE:
4549     case GEU:
4550       emit_insn (gen_subv2sf3 (tmp, cc_op0, cc_op1));
4551       emit_insn (gen_selv2sf4 (dest, tmp, op0, op1, CONST0_RTX (SFmode)));
4552       return;
4553     case LE:
4554     case LEU:
4555       paired_emit_vector_compare (GE, dest, op0, op1, cc_op1, cc_op0);
4556       return;
4557     case GT:
4558       paired_emit_vector_compare (LE, dest, op1, op0, cc_op0, cc_op1);
4559       return;
4560     case EQ:
4561       tmp1 = gen_reg_rtx (V2SFmode);
4562       max = gen_reg_rtx (V2SFmode);
4563       min = gen_reg_rtx (V2SFmode);
4564       gen_reg_rtx (V2SFmode);
4565 
4566       emit_insn (gen_subv2sf3 (tmp, cc_op0, cc_op1));
4567       emit_insn (gen_selv2sf4
4568                  (max, tmp, cc_op0, cc_op1, CONST0_RTX (SFmode)));
4569       emit_insn (gen_subv2sf3 (tmp, cc_op1, cc_op0));
4570       emit_insn (gen_selv2sf4
4571                  (min, tmp, cc_op0, cc_op1, CONST0_RTX (SFmode)));
4572       emit_insn (gen_subv2sf3 (tmp1, min, max));
4573       emit_insn (gen_selv2sf4 (dest, tmp1, op0, op1, CONST0_RTX (SFmode)));
4574       return;
4575     case NE:
4576       paired_emit_vector_compare (EQ, dest, op1, op0, cc_op0, cc_op1);
4577       return;
4578     case UNLE:
4579       paired_emit_vector_compare (LE, dest, op1, op0, cc_op0, cc_op1);
4580       return;
4581     case UNLT:
4582       paired_emit_vector_compare (LT, dest, op1, op0, cc_op0, cc_op1);
4583       return;
4584     case UNGE:
4585       paired_emit_vector_compare (GE, dest, op1, op0, cc_op0, cc_op1);
4586       return;
4587     case UNGT:
4588       paired_emit_vector_compare (GT, dest, op1, op0, cc_op0, cc_op1);
4589       return;
4590     default:
4591       gcc_unreachable ();
4592     }
4593 
4594   return;
4595 }
4596 
4597 /* Emit vector conditional expression.
4598    DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
4599    CC_OP0 and CC_OP1 are the two operands for the relation operation COND.  */
4600 
4601 int
paired_emit_vector_cond_expr(rtx dest,rtx op1,rtx op2,rtx cond,rtx cc_op0,rtx cc_op1)4602 paired_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
4603 			      rtx cond, rtx cc_op0, rtx cc_op1)
4604 {
4605   enum rtx_code rcode = GET_CODE (cond);
4606 
4607   if (!TARGET_PAIRED_FLOAT)
4608     return 0;
4609 
4610   paired_emit_vector_compare (rcode, dest, op1, op2, cc_op0, cc_op1);
4611 
4612   return 1;
4613 }
4614 
4615 /* Initialize vector TARGET to VALS.  */
4616 
4617 void
rs6000_expand_vector_init(rtx target,rtx vals)4618 rs6000_expand_vector_init (rtx target, rtx vals)
4619 {
4620   enum machine_mode mode = GET_MODE (target);
4621   enum machine_mode inner_mode = GET_MODE_INNER (mode);
4622   int n_elts = GET_MODE_NUNITS (mode);
4623   int n_var = 0, one_var = -1;
4624   bool all_same = true, all_const_zero = true;
4625   rtx x, mem;
4626   int i;
4627 
4628   for (i = 0; i < n_elts; ++i)
4629     {
4630       x = XVECEXP (vals, 0, i);
4631       if (!(CONST_INT_P (x)
4632 	    || GET_CODE (x) == CONST_DOUBLE
4633 	    || GET_CODE (x) == CONST_FIXED))
4634 	++n_var, one_var = i;
4635       else if (x != CONST0_RTX (inner_mode))
4636 	all_const_zero = false;
4637 
4638       if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
4639 	all_same = false;
4640     }
4641 
4642   if (n_var == 0)
4643     {
4644       rtx const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0));
4645       bool int_vector_p = (GET_MODE_CLASS (mode) == MODE_VECTOR_INT);
4646       if ((int_vector_p || TARGET_VSX) && all_const_zero)
4647 	{
4648 	  /* Zero register.  */
4649 	  emit_insn (gen_rtx_SET (VOIDmode, target,
4650 				  gen_rtx_XOR (mode, target, target)));
4651 	  return;
4652 	}
4653       else if (int_vector_p && easy_vector_constant (const_vec, mode))
4654 	{
4655 	  /* Splat immediate.  */
4656 	  emit_insn (gen_rtx_SET (VOIDmode, target, const_vec));
4657 	  return;
4658 	}
4659       else
4660 	{
4661 	  /* Load from constant pool.  */
4662 	  emit_move_insn (target, const_vec);
4663 	  return;
4664 	}
4665     }
4666 
4667   /* Double word values on VSX can use xxpermdi or lxvdsx.  */
4668   if (VECTOR_MEM_VSX_P (mode) && (mode == V2DFmode || mode == V2DImode))
4669     {
4670       rtx op0 = XVECEXP (vals, 0, 0);
4671       rtx op1 = XVECEXP (vals, 0, 1);
4672       if (all_same)
4673 	{
4674 	  if (!MEM_P (op0) && !REG_P (op0))
4675 	    op0 = force_reg (inner_mode, op0);
4676 	  if (mode == V2DFmode)
4677 	    emit_insn (gen_vsx_splat_v2df (target, op0));
4678 	  else
4679 	    emit_insn (gen_vsx_splat_v2di (target, op0));
4680 	}
4681       else
4682 	{
4683 	  op0 = force_reg (inner_mode, op0);
4684 	  op1 = force_reg (inner_mode, op1);
4685 	  if (mode == V2DFmode)
4686 	    emit_insn (gen_vsx_concat_v2df (target, op0, op1));
4687 	  else
4688 	    emit_insn (gen_vsx_concat_v2di (target, op0, op1));
4689 	}
4690       return;
4691     }
4692 
4693   /* With single precision floating point on VSX, know that internally single
4694      precision is actually represented as a double, and either make 2 V2DF
4695      vectors, and convert these vectors to single precision, or do one
4696      conversion, and splat the result to the other elements.  */
4697   if (mode == V4SFmode && VECTOR_MEM_VSX_P (mode))
4698     {
4699       if (all_same)
4700 	{
4701 	  rtx freg = gen_reg_rtx (V4SFmode);
4702 	  rtx sreg = force_reg (SFmode, XVECEXP (vals, 0, 0));
4703 
4704 	  emit_insn (gen_vsx_xscvdpsp_scalar (freg, sreg));
4705 	  emit_insn (gen_vsx_xxspltw_v4sf (target, freg, const0_rtx));
4706 	}
4707       else
4708 	{
4709 	  rtx dbl_even = gen_reg_rtx (V2DFmode);
4710 	  rtx dbl_odd  = gen_reg_rtx (V2DFmode);
4711 	  rtx flt_even = gen_reg_rtx (V4SFmode);
4712 	  rtx flt_odd  = gen_reg_rtx (V4SFmode);
4713 	  rtx op0 = force_reg (SFmode, XVECEXP (vals, 0, 0));
4714 	  rtx op1 = force_reg (SFmode, XVECEXP (vals, 0, 1));
4715 	  rtx op2 = force_reg (SFmode, XVECEXP (vals, 0, 2));
4716 	  rtx op3 = force_reg (SFmode, XVECEXP (vals, 0, 3));
4717 
4718 	  emit_insn (gen_vsx_concat_v2sf (dbl_even, op0, op1));
4719 	  emit_insn (gen_vsx_concat_v2sf (dbl_odd, op2, op3));
4720 	  emit_insn (gen_vsx_xvcvdpsp (flt_even, dbl_even));
4721 	  emit_insn (gen_vsx_xvcvdpsp (flt_odd, dbl_odd));
4722 	  rs6000_expand_extract_even (target, flt_even, flt_odd);
4723 	}
4724       return;
4725     }
4726 
4727   /* Store value to stack temp.  Load vector element.  Splat.  However, splat
4728      of 64-bit items is not supported on Altivec.  */
4729   if (all_same && GET_MODE_SIZE (inner_mode) <= 4)
4730     {
4731       mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode));
4732       emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
4733 		      XVECEXP (vals, 0, 0));
4734       x = gen_rtx_UNSPEC (VOIDmode,
4735 			  gen_rtvec (1, const0_rtx), UNSPEC_LVE);
4736       emit_insn (gen_rtx_PARALLEL (VOIDmode,
4737 				   gen_rtvec (2,
4738 					      gen_rtx_SET (VOIDmode,
4739 							   target, mem),
4740 					      x)));
4741       x = gen_rtx_VEC_SELECT (inner_mode, target,
4742 			      gen_rtx_PARALLEL (VOIDmode,
4743 						gen_rtvec (1, const0_rtx)));
4744       emit_insn (gen_rtx_SET (VOIDmode, target,
4745 			      gen_rtx_VEC_DUPLICATE (mode, x)));
4746       return;
4747     }
4748 
4749   /* One field is non-constant.  Load constant then overwrite
4750      varying field.  */
4751   if (n_var == 1)
4752     {
4753       rtx copy = copy_rtx (vals);
4754 
4755       /* Load constant part of vector, substitute neighboring value for
4756 	 varying element.  */
4757       XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
4758       rs6000_expand_vector_init (target, copy);
4759 
4760       /* Insert variable.  */
4761       rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
4762       return;
4763     }
4764 
4765   /* Construct the vector in memory one field at a time
4766      and load the whole vector.  */
4767   mem = assign_stack_temp (mode, GET_MODE_SIZE (mode));
4768   for (i = 0; i < n_elts; i++)
4769     emit_move_insn (adjust_address_nv (mem, inner_mode,
4770 				    i * GET_MODE_SIZE (inner_mode)),
4771 		    XVECEXP (vals, 0, i));
4772   emit_move_insn (target, mem);
4773 }
4774 
4775 /* Set field ELT of TARGET to VAL.  */
4776 
4777 void
rs6000_expand_vector_set(rtx target,rtx val,int elt)4778 rs6000_expand_vector_set (rtx target, rtx val, int elt)
4779 {
4780   enum machine_mode mode = GET_MODE (target);
4781   enum machine_mode inner_mode = GET_MODE_INNER (mode);
4782   rtx reg = gen_reg_rtx (mode);
4783   rtx mask, mem, x;
4784   int width = GET_MODE_SIZE (inner_mode);
4785   int i;
4786 
4787   if (VECTOR_MEM_VSX_P (mode) && (mode == V2DFmode || mode == V2DImode))
4788     {
4789       rtx (*set_func) (rtx, rtx, rtx, rtx)
4790 	= ((mode == V2DFmode) ? gen_vsx_set_v2df : gen_vsx_set_v2di);
4791       emit_insn (set_func (target, target, val, GEN_INT (elt)));
4792       return;
4793     }
4794 
4795   /* Load single variable value.  */
4796   mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode));
4797   emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
4798   x = gen_rtx_UNSPEC (VOIDmode,
4799 		      gen_rtvec (1, const0_rtx), UNSPEC_LVE);
4800   emit_insn (gen_rtx_PARALLEL (VOIDmode,
4801 			       gen_rtvec (2,
4802 					  gen_rtx_SET (VOIDmode,
4803 						       reg, mem),
4804 					  x)));
4805 
4806   /* Linear sequence.  */
4807   mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
4808   for (i = 0; i < 16; ++i)
4809     XVECEXP (mask, 0, i) = GEN_INT (i);
4810 
4811   /* Set permute mask to insert element into target.  */
4812   for (i = 0; i < width; ++i)
4813     XVECEXP (mask, 0, elt*width + i)
4814       = GEN_INT (i + 0x10);
4815   x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
4816   x = gen_rtx_UNSPEC (mode,
4817 		      gen_rtvec (3, target, reg,
4818 				 force_reg (V16QImode, x)),
4819 		      UNSPEC_VPERM);
4820   emit_insn (gen_rtx_SET (VOIDmode, target, x));
4821 }
4822 
4823 /* Extract field ELT from VEC into TARGET.  */
4824 
4825 void
rs6000_expand_vector_extract(rtx target,rtx vec,int elt)4826 rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
4827 {
4828   enum machine_mode mode = GET_MODE (vec);
4829   enum machine_mode inner_mode = GET_MODE_INNER (mode);
4830   rtx mem;
4831 
4832   if (VECTOR_MEM_VSX_P (mode))
4833     {
4834       switch (mode)
4835 	{
4836 	default:
4837 	  break;
4838 	case V2DFmode:
4839 	  emit_insn (gen_vsx_extract_v2df (target, vec, GEN_INT (elt)));
4840 	  return;
4841 	case V2DImode:
4842 	  emit_insn (gen_vsx_extract_v2di (target, vec, GEN_INT (elt)));
4843 	  return;
4844 	case V4SFmode:
4845 	  emit_insn (gen_vsx_extract_v4sf (target, vec, GEN_INT (elt)));
4846 	  return;
4847 	}
4848     }
4849 
4850   /* Allocate mode-sized buffer.  */
4851   mem = assign_stack_temp (mode, GET_MODE_SIZE (mode));
4852 
4853   emit_move_insn (mem, vec);
4854 
4855   /* Add offset to field within buffer matching vector element.  */
4856   mem = adjust_address_nv (mem, inner_mode, elt * GET_MODE_SIZE (inner_mode));
4857 
4858   emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
4859 }
4860 
4861 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
4862    implement ANDing by the mask IN.  */
4863 void
build_mask64_2_operands(rtx in,rtx * out)4864 build_mask64_2_operands (rtx in, rtx *out)
4865 {
4866 #if HOST_BITS_PER_WIDE_INT >= 64
4867   unsigned HOST_WIDE_INT c, lsb, m1, m2;
4868   int shift;
4869 
4870   gcc_assert (GET_CODE (in) == CONST_INT);
4871 
4872   c = INTVAL (in);
4873   if (c & 1)
4874     {
4875       /* Assume c initially something like 0x00fff000000fffff.  The idea
4876 	 is to rotate the word so that the middle ^^^^^^ group of zeros
4877 	 is at the MS end and can be cleared with an rldicl mask.  We then
4878 	 rotate back and clear off the MS    ^^ group of zeros with a
4879 	 second rldicl.  */
4880       c = ~c;			/*   c == 0xff000ffffff00000 */
4881       lsb = c & -c;		/* lsb == 0x0000000000100000 */
4882       m1 = -lsb;		/*  m1 == 0xfffffffffff00000 */
4883       c = ~c;			/*   c == 0x00fff000000fffff */
4884       c &= -lsb;		/*   c == 0x00fff00000000000 */
4885       lsb = c & -c;		/* lsb == 0x0000100000000000 */
4886       c = ~c;			/*   c == 0xff000fffffffffff */
4887       c &= -lsb;		/*   c == 0xff00000000000000 */
4888       shift = 0;
4889       while ((lsb >>= 1) != 0)
4890 	shift++;		/* shift == 44 on exit from loop */
4891       m1 <<= 64 - shift;	/*  m1 == 0xffffff0000000000 */
4892       m1 = ~m1;			/*  m1 == 0x000000ffffffffff */
4893       m2 = ~c;			/*  m2 == 0x00ffffffffffffff */
4894     }
4895   else
4896     {
4897       /* Assume c initially something like 0xff000f0000000000.  The idea
4898 	 is to rotate the word so that the     ^^^  middle group of zeros
4899 	 is at the LS end and can be cleared with an rldicr mask.  We then
4900 	 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
4901 	 a second rldicr.  */
4902       lsb = c & -c;		/* lsb == 0x0000010000000000 */
4903       m2 = -lsb;		/*  m2 == 0xffffff0000000000 */
4904       c = ~c;			/*   c == 0x00fff0ffffffffff */
4905       c &= -lsb;		/*   c == 0x00fff00000000000 */
4906       lsb = c & -c;		/* lsb == 0x0000100000000000 */
4907       c = ~c;			/*   c == 0xff000fffffffffff */
4908       c &= -lsb;		/*   c == 0xff00000000000000 */
4909       shift = 0;
4910       while ((lsb >>= 1) != 0)
4911 	shift++;		/* shift == 44 on exit from loop */
4912       m1 = ~c;			/*  m1 == 0x00ffffffffffffff */
4913       m1 >>= shift;		/*  m1 == 0x0000000000000fff */
4914       m1 = ~m1;			/*  m1 == 0xfffffffffffff000 */
4915     }
4916 
4917   /* Note that when we only have two 0->1 and 1->0 transitions, one of the
4918      masks will be all 1's.  We are guaranteed more than one transition.  */
4919   out[0] = GEN_INT (64 - shift);
4920   out[1] = GEN_INT (m1);
4921   out[2] = GEN_INT (shift);
4922   out[3] = GEN_INT (m2);
4923 #else
4924   (void)in;
4925   (void)out;
4926   gcc_unreachable ();
4927 #endif
4928 }
4929 
4930 /* Return TRUE if OP is an invalid SUBREG operation on the e500.  */
4931 
4932 bool
invalid_e500_subreg(rtx op,enum machine_mode mode)4933 invalid_e500_subreg (rtx op, enum machine_mode mode)
4934 {
4935   if (TARGET_E500_DOUBLE)
4936     {
4937       /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
4938 	 subreg:TI and reg:TF.  Decimal float modes are like integer
4939 	 modes (only low part of each register used) for this
4940 	 purpose.  */
4941       if (GET_CODE (op) == SUBREG
4942 	  && (mode == SImode || mode == DImode || mode == TImode
4943 	      || mode == DDmode || mode == TDmode)
4944 	  && REG_P (SUBREG_REG (op))
4945 	  && (GET_MODE (SUBREG_REG (op)) == DFmode
4946 	      || GET_MODE (SUBREG_REG (op)) == TFmode))
4947 	return true;
4948 
4949       /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
4950 	 reg:TI.  */
4951       if (GET_CODE (op) == SUBREG
4952 	  && (mode == DFmode || mode == TFmode)
4953 	  && REG_P (SUBREG_REG (op))
4954 	  && (GET_MODE (SUBREG_REG (op)) == DImode
4955 	      || GET_MODE (SUBREG_REG (op)) == TImode
4956 	      || GET_MODE (SUBREG_REG (op)) == DDmode
4957 	      || GET_MODE (SUBREG_REG (op)) == TDmode))
4958 	return true;
4959     }
4960 
4961   if (TARGET_SPE
4962       && GET_CODE (op) == SUBREG
4963       && mode == SImode
4964       && REG_P (SUBREG_REG (op))
4965       && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op))))
4966     return true;
4967 
4968   return false;
4969 }
4970 
4971 /* AIX increases natural record alignment to doubleword if the first
4972    field is an FP double while the FP fields remain word aligned.  */
4973 
4974 unsigned int
rs6000_special_round_type_align(tree type,unsigned int computed,unsigned int specified)4975 rs6000_special_round_type_align (tree type, unsigned int computed,
4976 				 unsigned int specified)
4977 {
4978   unsigned int align = MAX (computed, specified);
4979   tree field = TYPE_FIELDS (type);
4980 
4981   /* Skip all non field decls */
4982   while (field != NULL && TREE_CODE (field) != FIELD_DECL)
4983     field = DECL_CHAIN (field);
4984 
4985   if (field != NULL && field != type)
4986     {
4987       type = TREE_TYPE (field);
4988       while (TREE_CODE (type) == ARRAY_TYPE)
4989 	type = TREE_TYPE (type);
4990 
4991       if (type != error_mark_node && TYPE_MODE (type) == DFmode)
4992 	align = MAX (align, 64);
4993     }
4994 
4995   return align;
4996 }
4997 
4998 /* Darwin increases record alignment to the natural alignment of
4999    the first field.  */
5000 
5001 unsigned int
darwin_rs6000_special_round_type_align(tree type,unsigned int computed,unsigned int specified)5002 darwin_rs6000_special_round_type_align (tree type, unsigned int computed,
5003 					unsigned int specified)
5004 {
5005   unsigned int align = MAX (computed, specified);
5006 
5007   if (TYPE_PACKED (type))
5008     return align;
5009 
5010   /* Find the first field, looking down into aggregates.  */
5011   do {
5012     tree field = TYPE_FIELDS (type);
5013     /* Skip all non field decls */
5014     while (field != NULL && TREE_CODE (field) != FIELD_DECL)
5015       field = DECL_CHAIN (field);
5016     if (! field)
5017       break;
5018     /* A packed field does not contribute any extra alignment.  */
5019     if (DECL_PACKED (field))
5020       return align;
5021     type = TREE_TYPE (field);
5022     while (TREE_CODE (type) == ARRAY_TYPE)
5023       type = TREE_TYPE (type);
5024   } while (AGGREGATE_TYPE_P (type));
5025 
5026   if (! AGGREGATE_TYPE_P (type) && type != error_mark_node)
5027     align = MAX (align, TYPE_ALIGN (type));
5028 
5029   return align;
5030 }
5031 
5032 /* Return 1 for an operand in small memory on V.4/eabi.  */
5033 
5034 int
small_data_operand(rtx op ATTRIBUTE_UNUSED,enum machine_mode mode ATTRIBUTE_UNUSED)5035 small_data_operand (rtx op ATTRIBUTE_UNUSED,
5036 		    enum machine_mode mode ATTRIBUTE_UNUSED)
5037 {
5038 #if TARGET_ELF
5039   rtx sym_ref;
5040 
5041   if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
5042     return 0;
5043 
5044   if (DEFAULT_ABI != ABI_V4)
5045     return 0;
5046 
5047   /* Vector and float memory instructions have a limited offset on the
5048      SPE, so using a vector or float variable directly as an operand is
5049      not useful.  */
5050   if (TARGET_SPE
5051       && (SPE_VECTOR_MODE (mode) || FLOAT_MODE_P (mode)))
5052     return 0;
5053 
5054   if (GET_CODE (op) == SYMBOL_REF)
5055     sym_ref = op;
5056 
5057   else if (GET_CODE (op) != CONST
5058 	   || GET_CODE (XEXP (op, 0)) != PLUS
5059 	   || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
5060 	   || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
5061     return 0;
5062 
5063   else
5064     {
5065       rtx sum = XEXP (op, 0);
5066       HOST_WIDE_INT summand;
5067 
5068       /* We have to be careful here, because it is the referenced address
5069 	 that must be 32k from _SDA_BASE_, not just the symbol.  */
5070       summand = INTVAL (XEXP (sum, 1));
5071       if (summand < 0 || summand > g_switch_value)
5072 	return 0;
5073 
5074       sym_ref = XEXP (sum, 0);
5075     }
5076 
5077   return SYMBOL_REF_SMALL_P (sym_ref);
5078 #else
5079   return 0;
5080 #endif
5081 }
5082 
5083 /* Return true if either operand is a general purpose register.  */
5084 
5085 bool
gpr_or_gpr_p(rtx op0,rtx op1)5086 gpr_or_gpr_p (rtx op0, rtx op1)
5087 {
5088   return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
5089 	  || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
5090 }
5091 
5092 /* Given an address, return a constant offset term if one exists.  */
5093 
5094 static rtx
address_offset(rtx op)5095 address_offset (rtx op)
5096 {
5097   if (GET_CODE (op) == PRE_INC
5098       || GET_CODE (op) == PRE_DEC)
5099     op = XEXP (op, 0);
5100   else if (GET_CODE (op) == PRE_MODIFY
5101 	   || GET_CODE (op) == LO_SUM)
5102     op = XEXP (op, 1);
5103 
5104   if (GET_CODE (op) == CONST)
5105     op = XEXP (op, 0);
5106 
5107   if (GET_CODE (op) == PLUS)
5108     op = XEXP (op, 1);
5109 
5110   if (CONST_INT_P (op))
5111     return op;
5112 
5113   return NULL_RTX;
5114 }
5115 
5116 /* Return true if the MEM operand is a memory operand suitable for use
5117    with a (full width, possibly multiple) gpr load/store.  On
5118    powerpc64 this means the offset must be divisible by 4.
5119    Implements 'Y' constraint.
5120 
5121    Accept direct, indexed, offset, lo_sum and tocref.  Since this is
5122    a constraint function we know the operand has satisfied a suitable
5123    memory predicate.  Also accept some odd rtl generated by reload
5124    (see rs6000_legitimize_reload_address for various forms).  It is
5125    important that reload rtl be accepted by appropriate constraints
5126    but not by the operand predicate.
5127 
5128    Offsetting a lo_sum should not be allowed, except where we know by
5129    alignment that a 32k boundary is not crossed, but see the ???
5130    comment in rs6000_legitimize_reload_address.  Note that by
5131    "offsetting" here we mean a further offset to access parts of the
5132    MEM.  It's fine to have a lo_sum where the inner address is offset
5133    from a sym, since the same sym+offset will appear in the high part
5134    of the address calculation.  */
5135 
5136 bool
mem_operand_gpr(rtx op,enum machine_mode mode)5137 mem_operand_gpr (rtx op, enum machine_mode mode)
5138 {
5139   unsigned HOST_WIDE_INT offset;
5140   int extra;
5141   rtx addr = XEXP (op, 0);
5142 
5143   op = address_offset (addr);
5144   if (op == NULL_RTX)
5145     return true;
5146 
5147   offset = INTVAL (op);
5148   if (TARGET_POWERPC64 && (offset & 3) != 0)
5149     return false;
5150 
5151   extra = GET_MODE_SIZE (mode) - UNITS_PER_WORD;
5152   gcc_assert (extra >= 0);
5153 
5154   if (GET_CODE (addr) == LO_SUM)
5155     /* For lo_sum addresses, we must allow any offset except one that
5156        causes a wrap, so test only the low 16 bits.  */
5157     offset = ((offset & 0xffff) ^ 0x8000) - 0x8000;
5158 
5159   return offset + 0x8000 < 0x10000u - extra;
5160 }
5161 
5162 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p.  */
5163 
5164 static bool
reg_offset_addressing_ok_p(enum machine_mode mode)5165 reg_offset_addressing_ok_p (enum machine_mode mode)
5166 {
5167   switch (mode)
5168     {
5169     case V16QImode:
5170     case V8HImode:
5171     case V4SFmode:
5172     case V4SImode:
5173     case V2DFmode:
5174     case V2DImode:
5175       /* AltiVec/VSX vector modes.  Only reg+reg addressing is valid.  */
5176       if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
5177 	return false;
5178       break;
5179 
5180     case V4HImode:
5181     case V2SImode:
5182     case V1DImode:
5183     case V2SFmode:
5184        /* Paired vector modes.  Only reg+reg addressing is valid.  */
5185       if (TARGET_PAIRED_FLOAT)
5186         return false;
5187       break;
5188 
5189     default:
5190       break;
5191     }
5192 
5193   return true;
5194 }
5195 
5196 static bool
virtual_stack_registers_memory_p(rtx op)5197 virtual_stack_registers_memory_p (rtx op)
5198 {
5199   int regnum;
5200 
5201   if (GET_CODE (op) == REG)
5202     regnum = REGNO (op);
5203 
5204   else if (GET_CODE (op) == PLUS
5205 	   && GET_CODE (XEXP (op, 0)) == REG
5206 	   && GET_CODE (XEXP (op, 1)) == CONST_INT)
5207     regnum = REGNO (XEXP (op, 0));
5208 
5209   else
5210     return false;
5211 
5212   return (regnum >= FIRST_VIRTUAL_REGISTER
5213 	  && regnum <= LAST_VIRTUAL_POINTER_REGISTER);
5214 }
5215 
5216 /* Return true if memory accesses to OP are known to never straddle
5217    a 32k boundary.  */
5218 
5219 static bool
offsettable_ok_by_alignment(rtx op,HOST_WIDE_INT offset,enum machine_mode mode)5220 offsettable_ok_by_alignment (rtx op, HOST_WIDE_INT offset,
5221 			     enum machine_mode mode)
5222 {
5223   tree decl, type;
5224   unsigned HOST_WIDE_INT dsize, dalign;
5225 
5226   if (GET_CODE (op) != SYMBOL_REF)
5227     return false;
5228 
5229   decl = SYMBOL_REF_DECL (op);
5230   if (!decl)
5231     {
5232       if (GET_MODE_SIZE (mode) == 0)
5233 	return false;
5234 
5235       /* -fsection-anchors loses the original SYMBOL_REF_DECL when
5236 	 replacing memory addresses with an anchor plus offset.  We
5237 	 could find the decl by rummaging around in the block->objects
5238 	 VEC for the given offset but that seems like too much work.  */
5239       dalign = 1;
5240       if (SYMBOL_REF_HAS_BLOCK_INFO_P (op)
5241 	  && SYMBOL_REF_ANCHOR_P (op)
5242 	  && SYMBOL_REF_BLOCK (op) != NULL)
5243 	{
5244 	  struct object_block *block = SYMBOL_REF_BLOCK (op);
5245 	  HOST_WIDE_INT lsb, mask;
5246 
5247 	  /* Given the alignment of the block..  */
5248 	  dalign = block->alignment;
5249 	  mask = dalign / BITS_PER_UNIT - 1;
5250 
5251 	  /* ..and the combined offset of the anchor and any offset
5252 	     to this block object..  */
5253 	  offset += SYMBOL_REF_BLOCK_OFFSET (op);
5254 	  lsb = offset & -offset;
5255 
5256 	  /* ..find how many bits of the alignment we know for the
5257 	     object.  */
5258 	  mask &= lsb - 1;
5259 	  dalign = mask + 1;
5260 	}
5261       return dalign >= GET_MODE_SIZE (mode);
5262     }
5263 
5264   if (DECL_P (decl))
5265     {
5266       if (TREE_CODE (decl) == FUNCTION_DECL)
5267 	return true;
5268 
5269       if (!DECL_SIZE_UNIT (decl))
5270 	return false;
5271 
5272       if (!host_integerp (DECL_SIZE_UNIT (decl), 1))
5273 	return false;
5274 
5275       dsize = tree_low_cst (DECL_SIZE_UNIT (decl), 1);
5276       if (dsize > 32768)
5277 	return false;
5278 
5279       dalign = DECL_ALIGN_UNIT (decl);
5280       return dalign >= dsize;
5281     }
5282 
5283   type = TREE_TYPE (decl);
5284 
5285   if (TREE_CODE (decl) == STRING_CST)
5286     dsize = TREE_STRING_LENGTH (decl);
5287   else if (TYPE_SIZE_UNIT (type)
5288 	   && host_integerp (TYPE_SIZE_UNIT (type), 1))
5289     dsize = tree_low_cst (TYPE_SIZE_UNIT (type), 1);
5290   else
5291     return false;
5292   if (dsize > 32768)
5293     return false;
5294 
5295   dalign = TYPE_ALIGN (type);
5296   if (CONSTANT_CLASS_P (decl))
5297     dalign = CONSTANT_ALIGNMENT (decl, dalign);
5298   else
5299     dalign = DATA_ALIGNMENT (decl, dalign);
5300   dalign /= BITS_PER_UNIT;
5301   return dalign >= dsize;
5302 }
5303 
5304 static bool
constant_pool_expr_p(rtx op)5305 constant_pool_expr_p (rtx op)
5306 {
5307   rtx base, offset;
5308 
5309   split_const (op, &base, &offset);
5310   return (GET_CODE (base) == SYMBOL_REF
5311 	  && CONSTANT_POOL_ADDRESS_P (base)
5312 	  && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base), Pmode));
5313 }
5314 
5315 static const_rtx tocrel_base, tocrel_offset;
5316 
5317 /* Return true if OP is a toc pointer relative address (the output
5318    of create_TOC_reference).  If STRICT, do not match high part or
5319    non-split -mcmodel=large/medium toc pointer relative addresses.  */
5320 
5321 bool
toc_relative_expr_p(const_rtx op,bool strict)5322 toc_relative_expr_p (const_rtx op, bool strict)
5323 {
5324   if (!TARGET_TOC)
5325     return false;
5326 
5327   if (TARGET_CMODEL != CMODEL_SMALL)
5328     {
5329       /* Only match the low part.  */
5330       if (GET_CODE (op) == LO_SUM
5331 	  && REG_P (XEXP (op, 0))
5332 	  && INT_REG_OK_FOR_BASE_P (XEXP (op, 0), strict))
5333 	op = XEXP (op, 1);
5334       else if (strict)
5335 	return false;
5336     }
5337 
5338   tocrel_base = op;
5339   tocrel_offset = const0_rtx;
5340   if (GET_CODE (op) == PLUS && CONST_INT_P (XEXP (op, 1)))
5341     {
5342       tocrel_base = XEXP (op, 0);
5343       tocrel_offset = XEXP (op, 1);
5344     }
5345 
5346   return (GET_CODE (tocrel_base) == UNSPEC
5347 	  && XINT (tocrel_base, 1) == UNSPEC_TOCREL);
5348 }
5349 
5350 /* Return true if X is a constant pool address, and also for cmodel=medium
5351    if X is a toc-relative address known to be offsettable within MODE.  */
5352 
5353 bool
legitimate_constant_pool_address_p(const_rtx x,enum machine_mode mode,bool strict)5354 legitimate_constant_pool_address_p (const_rtx x, enum machine_mode mode,
5355 				    bool strict)
5356 {
5357   return (toc_relative_expr_p (x, strict)
5358 	  && (TARGET_CMODEL != CMODEL_MEDIUM
5359 	      || constant_pool_expr_p (XVECEXP (tocrel_base, 0, 0))
5360 	      || mode == QImode
5361 	      || offsettable_ok_by_alignment (XVECEXP (tocrel_base, 0, 0),
5362 					      INTVAL (tocrel_offset), mode)));
5363 }
5364 
5365 static bool
legitimate_small_data_p(enum machine_mode mode,rtx x)5366 legitimate_small_data_p (enum machine_mode mode, rtx x)
5367 {
5368   return (DEFAULT_ABI == ABI_V4
5369 	  && !flag_pic && !TARGET_TOC
5370 	  && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
5371 	  && small_data_operand (x, mode));
5372 }
5373 
5374 /* SPE offset addressing is limited to 5-bits worth of double words.  */
5375 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
5376 
5377 bool
rs6000_legitimate_offset_address_p(enum machine_mode mode,rtx x,bool strict,bool worst_case)5378 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x,
5379 				    bool strict, bool worst_case)
5380 {
5381   unsigned HOST_WIDE_INT offset;
5382   unsigned int extra;
5383 
5384   if (GET_CODE (x) != PLUS)
5385     return false;
5386   if (!REG_P (XEXP (x, 0)))
5387     return false;
5388   if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
5389     return false;
5390   if (!reg_offset_addressing_ok_p (mode))
5391     return virtual_stack_registers_memory_p (x);
5392   if (legitimate_constant_pool_address_p (x, mode, strict))
5393     return true;
5394   if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5395     return false;
5396 
5397   offset = INTVAL (XEXP (x, 1));
5398   extra = 0;
5399   switch (mode)
5400     {
5401     case V4HImode:
5402     case V2SImode:
5403     case V1DImode:
5404     case V2SFmode:
5405       /* SPE vector modes.  */
5406       return SPE_CONST_OFFSET_OK (offset);
5407 
5408     case DFmode:
5409     case DDmode:
5410     case DImode:
5411       /* On e500v2, we may have:
5412 
5413 	   (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
5414 
5415          Which gets addressed with evldd instructions.  */
5416       if (TARGET_E500_DOUBLE)
5417 	return SPE_CONST_OFFSET_OK (offset);
5418 
5419       /* If we are using VSX scalar loads, restrict ourselves to reg+reg
5420 	 addressing.  */
5421       if (mode == DFmode && VECTOR_MEM_VSX_P (DFmode))
5422 	return false;
5423 
5424       if (!worst_case)
5425 	break;
5426       if (!TARGET_POWERPC64)
5427 	extra = 4;
5428       else if (offset & 3)
5429 	return false;
5430       break;
5431 
5432     case TFmode:
5433     case TDmode:
5434     case TImode:
5435       if (TARGET_E500_DOUBLE)
5436 	return (SPE_CONST_OFFSET_OK (offset)
5437 		&& SPE_CONST_OFFSET_OK (offset + 8));
5438 
5439       extra = 8;
5440       if (!worst_case)
5441 	break;
5442       if (!TARGET_POWERPC64)
5443 	extra = 12;
5444       else if (offset & 3)
5445 	return false;
5446       break;
5447 
5448     default:
5449       break;
5450     }
5451 
5452   offset += 0x8000;
5453   return offset < 0x10000 - extra;
5454 }
5455 
5456 bool
legitimate_indexed_address_p(rtx x,int strict)5457 legitimate_indexed_address_p (rtx x, int strict)
5458 {
5459   rtx op0, op1;
5460 
5461   if (GET_CODE (x) != PLUS)
5462     return false;
5463 
5464   op0 = XEXP (x, 0);
5465   op1 = XEXP (x, 1);
5466 
5467   /* Recognize the rtl generated by reload which we know will later be
5468      replaced with proper base and index regs.  */
5469   if (!strict
5470       && reload_in_progress
5471       && (REG_P (op0) || GET_CODE (op0) == PLUS)
5472       && REG_P (op1))
5473     return true;
5474 
5475   return (REG_P (op0) && REG_P (op1)
5476 	  && ((INT_REG_OK_FOR_BASE_P (op0, strict)
5477 	       && INT_REG_OK_FOR_INDEX_P (op1, strict))
5478 	      || (INT_REG_OK_FOR_BASE_P (op1, strict)
5479 		  && INT_REG_OK_FOR_INDEX_P (op0, strict))));
5480 }
5481 
5482 bool
avoiding_indexed_address_p(enum machine_mode mode)5483 avoiding_indexed_address_p (enum machine_mode mode)
5484 {
5485   /* Avoid indexed addressing for modes that have non-indexed
5486      load/store instruction forms.  */
5487   return (TARGET_AVOID_XFORM && VECTOR_MEM_NONE_P (mode));
5488 }
5489 
5490 bool
legitimate_indirect_address_p(rtx x,int strict)5491 legitimate_indirect_address_p (rtx x, int strict)
5492 {
5493   return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
5494 }
5495 
5496 bool
macho_lo_sum_memory_operand(rtx x,enum machine_mode mode)5497 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
5498 {
5499   if (!TARGET_MACHO || !flag_pic
5500       || mode != SImode || GET_CODE (x) != MEM)
5501     return false;
5502   x = XEXP (x, 0);
5503 
5504   if (GET_CODE (x) != LO_SUM)
5505     return false;
5506   if (GET_CODE (XEXP (x, 0)) != REG)
5507     return false;
5508   if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
5509     return false;
5510   x = XEXP (x, 1);
5511 
5512   return CONSTANT_P (x);
5513 }
5514 
5515 static bool
legitimate_lo_sum_address_p(enum machine_mode mode,rtx x,int strict)5516 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
5517 {
5518   if (GET_CODE (x) != LO_SUM)
5519     return false;
5520   if (GET_CODE (XEXP (x, 0)) != REG)
5521     return false;
5522   if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
5523     return false;
5524   /* Restrict addressing for DI because of our SUBREG hackery.  */
5525   if (TARGET_E500_DOUBLE && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
5526     return false;
5527   x = XEXP (x, 1);
5528 
5529   if (TARGET_ELF || TARGET_MACHO)
5530     {
5531       if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
5532 	return false;
5533       if (TARGET_TOC)
5534 	return false;
5535       if (GET_MODE_NUNITS (mode) != 1)
5536 	return false;
5537       if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
5538 	  && !(/* ??? Assume floating point reg based on mode?  */
5539 	       TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5540 	       && (mode == DFmode || mode == DDmode)))
5541 	return false;
5542 
5543       return CONSTANT_P (x);
5544     }
5545 
5546   return false;
5547 }
5548 
5549 
5550 /* Try machine-dependent ways of modifying an illegitimate address
5551    to be legitimate.  If we find one, return the new, valid address.
5552    This is used from only one place: `memory_address' in explow.c.
5553 
5554    OLDX is the address as it was before break_out_memory_refs was
5555    called.  In some cases it is useful to look at this to decide what
5556    needs to be done.
5557 
5558    It is always safe for this function to do nothing.  It exists to
5559    recognize opportunities to optimize the output.
5560 
5561    On RS/6000, first check for the sum of a register with a constant
5562    integer that is out of range.  If so, generate code to add the
5563    constant with the low-order 16 bits masked to the register and force
5564    this result into another register (this can be done with `cau').
5565    Then generate an address of REG+(CONST&0xffff), allowing for the
5566    possibility of bit 16 being a one.
5567 
5568    Then check for the sum of a register and something not constant, try to
5569    load the other things into a register and return the sum.  */
5570 
5571 static rtx
rs6000_legitimize_address(rtx x,rtx oldx ATTRIBUTE_UNUSED,enum machine_mode mode)5572 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
5573 			   enum machine_mode mode)
5574 {
5575   unsigned int extra;
5576 
5577   if (!reg_offset_addressing_ok_p (mode))
5578     {
5579       if (virtual_stack_registers_memory_p (x))
5580 	return x;
5581 
5582       /* In theory we should not be seeing addresses of the form reg+0,
5583 	 but just in case it is generated, optimize it away.  */
5584       if (GET_CODE (x) == PLUS && XEXP (x, 1) == const0_rtx)
5585 	return force_reg (Pmode, XEXP (x, 0));
5586 
5587       /* Make sure both operands are registers.  */
5588       else if (GET_CODE (x) == PLUS)
5589 	return gen_rtx_PLUS (Pmode,
5590 			     force_reg (Pmode, XEXP (x, 0)),
5591 			     force_reg (Pmode, XEXP (x, 1)));
5592       else
5593 	return force_reg (Pmode, x);
5594     }
5595   if (GET_CODE (x) == SYMBOL_REF)
5596     {
5597       enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
5598       if (model != 0)
5599 	return rs6000_legitimize_tls_address (x, model);
5600     }
5601 
5602   extra = 0;
5603   switch (mode)
5604     {
5605     case TFmode:
5606     case TDmode:
5607     case TImode:
5608       /* As in legitimate_offset_address_p we do not assume
5609 	 worst-case.  The mode here is just a hint as to the registers
5610 	 used.  A TImode is usually in gprs, but may actually be in
5611 	 fprs.  Leave worst-case scenario for reload to handle via
5612 	 insn constraints.  */
5613       extra = 8;
5614       break;
5615     default:
5616       break;
5617     }
5618 
5619   if (GET_CODE (x) == PLUS
5620       && GET_CODE (XEXP (x, 0)) == REG
5621       && GET_CODE (XEXP (x, 1)) == CONST_INT
5622       && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000)
5623 	  >= 0x10000 - extra)
5624       && !(SPE_VECTOR_MODE (mode)
5625 	   || (TARGET_E500_DOUBLE && GET_MODE_SIZE (mode) > UNITS_PER_WORD)))
5626     {
5627       HOST_WIDE_INT high_int, low_int;
5628       rtx sum;
5629       low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
5630       if (low_int >= 0x8000 - extra)
5631 	low_int = 0;
5632       high_int = INTVAL (XEXP (x, 1)) - low_int;
5633       sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
5634 					 GEN_INT (high_int)), 0);
5635       return plus_constant (Pmode, sum, low_int);
5636     }
5637   else if (GET_CODE (x) == PLUS
5638 	   && GET_CODE (XEXP (x, 0)) == REG
5639 	   && GET_CODE (XEXP (x, 1)) != CONST_INT
5640 	   && GET_MODE_NUNITS (mode) == 1
5641 	   && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
5642 	       || (/* ??? Assume floating point reg based on mode?  */
5643 		   (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
5644 		   && (mode == DFmode || mode == DDmode)))
5645 	   && !avoiding_indexed_address_p (mode))
5646     {
5647       return gen_rtx_PLUS (Pmode, XEXP (x, 0),
5648 			   force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
5649     }
5650   else if (SPE_VECTOR_MODE (mode)
5651 	   || (TARGET_E500_DOUBLE && GET_MODE_SIZE (mode) > UNITS_PER_WORD))
5652     {
5653       if (mode == DImode)
5654 	return x;
5655       /* We accept [reg + reg] and [reg + OFFSET].  */
5656 
5657       if (GET_CODE (x) == PLUS)
5658        {
5659          rtx op1 = XEXP (x, 0);
5660          rtx op2 = XEXP (x, 1);
5661          rtx y;
5662 
5663          op1 = force_reg (Pmode, op1);
5664 
5665          if (GET_CODE (op2) != REG
5666              && (GET_CODE (op2) != CONST_INT
5667                  || !SPE_CONST_OFFSET_OK (INTVAL (op2))
5668                  || (GET_MODE_SIZE (mode) > 8
5669                      && !SPE_CONST_OFFSET_OK (INTVAL (op2) + 8))))
5670            op2 = force_reg (Pmode, op2);
5671 
5672          /* We can't always do [reg + reg] for these, because [reg +
5673             reg + offset] is not a legitimate addressing mode.  */
5674          y = gen_rtx_PLUS (Pmode, op1, op2);
5675 
5676          if ((GET_MODE_SIZE (mode) > 8 || mode == DDmode) && REG_P (op2))
5677            return force_reg (Pmode, y);
5678          else
5679            return y;
5680        }
5681 
5682       return force_reg (Pmode, x);
5683     }
5684   else if ((TARGET_ELF
5685 #if TARGET_MACHO
5686 	    || !MACHO_DYNAMIC_NO_PIC_P
5687 #endif
5688 	    )
5689 	   && TARGET_32BIT
5690 	   && TARGET_NO_TOC
5691 	   && ! flag_pic
5692 	   && GET_CODE (x) != CONST_INT
5693 	   && GET_CODE (x) != CONST_DOUBLE
5694 	   && CONSTANT_P (x)
5695 	   && GET_MODE_NUNITS (mode) == 1
5696 	   && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
5697 	       || (/* ??? Assume floating point reg based on mode?  */
5698 		   (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
5699 		   && (mode == DFmode || mode == DDmode))))
5700     {
5701       rtx reg = gen_reg_rtx (Pmode);
5702       if (TARGET_ELF)
5703 	emit_insn (gen_elf_high (reg, x));
5704       else
5705 	emit_insn (gen_macho_high (reg, x));
5706       return gen_rtx_LO_SUM (Pmode, reg, x);
5707     }
5708   else if (TARGET_TOC
5709 	   && GET_CODE (x) == SYMBOL_REF
5710 	   && constant_pool_expr_p (x)
5711 	   && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
5712     return create_TOC_reference (x, NULL_RTX);
5713   else
5714     return x;
5715 }
5716 
5717 /* Debug version of rs6000_legitimize_address.  */
5718 static rtx
rs6000_debug_legitimize_address(rtx x,rtx oldx,enum machine_mode mode)5719 rs6000_debug_legitimize_address (rtx x, rtx oldx, enum machine_mode mode)
5720 {
5721   rtx ret;
5722   rtx insns;
5723 
5724   start_sequence ();
5725   ret = rs6000_legitimize_address (x, oldx, mode);
5726   insns = get_insns ();
5727   end_sequence ();
5728 
5729   if (ret != x)
5730     {
5731       fprintf (stderr,
5732 	       "\nrs6000_legitimize_address: mode %s, old code %s, "
5733 	       "new code %s, modified\n",
5734 	       GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)),
5735 	       GET_RTX_NAME (GET_CODE (ret)));
5736 
5737       fprintf (stderr, "Original address:\n");
5738       debug_rtx (x);
5739 
5740       fprintf (stderr, "oldx:\n");
5741       debug_rtx (oldx);
5742 
5743       fprintf (stderr, "New address:\n");
5744       debug_rtx (ret);
5745 
5746       if (insns)
5747 	{
5748 	  fprintf (stderr, "Insns added:\n");
5749 	  debug_rtx_list (insns, 20);
5750 	}
5751     }
5752   else
5753     {
5754       fprintf (stderr,
5755 	       "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
5756 	       GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)));
5757 
5758       debug_rtx (x);
5759     }
5760 
5761   if (insns)
5762     emit_insn (insns);
5763 
5764   return ret;
5765 }
5766 
5767 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
5768    We need to emit DTP-relative relocations.  */
5769 
5770 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
5771 static void
rs6000_output_dwarf_dtprel(FILE * file,int size,rtx x)5772 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
5773 {
5774   switch (size)
5775     {
5776     case 4:
5777       fputs ("\t.long\t", file);
5778       break;
5779     case 8:
5780       fputs (DOUBLE_INT_ASM_OP, file);
5781       break;
5782     default:
5783       gcc_unreachable ();
5784     }
5785   output_addr_const (file, x);
5786   fputs ("@dtprel+0x8000", file);
5787 }
5788 
5789 /* In the name of slightly smaller debug output, and to cater to
5790    general assembler lossage, recognize various UNSPEC sequences
5791    and turn them back into a direct symbol reference.  */
5792 
5793 static rtx
rs6000_delegitimize_address(rtx orig_x)5794 rs6000_delegitimize_address (rtx orig_x)
5795 {
5796   rtx x, y, offset;
5797 
5798   orig_x = delegitimize_mem_from_attrs (orig_x);
5799   x = orig_x;
5800   if (MEM_P (x))
5801     x = XEXP (x, 0);
5802 
5803   y = x;
5804   if (TARGET_CMODEL != CMODEL_SMALL
5805       && GET_CODE (y) == LO_SUM)
5806     y = XEXP (y, 1);
5807 
5808   offset = NULL_RTX;
5809   if (GET_CODE (y) == PLUS
5810       && GET_MODE (y) == Pmode
5811       && CONST_INT_P (XEXP (y, 1)))
5812     {
5813       offset = XEXP (y, 1);
5814       y = XEXP (y, 0);
5815     }
5816 
5817   if (GET_CODE (y) == UNSPEC
5818       && XINT (y, 1) == UNSPEC_TOCREL)
5819     {
5820 #ifdef ENABLE_CHECKING
5821       if (REG_P (XVECEXP (y, 0, 1))
5822 	  && REGNO (XVECEXP (y, 0, 1)) == TOC_REGISTER)
5823 	{
5824 	  /* All good.  */
5825 	}
5826       else if (GET_CODE (XVECEXP (y, 0, 1)) == DEBUG_EXPR)
5827 	{
5828 	  /* Weirdness alert.  df_note_compute can replace r2 with a
5829 	     debug_expr when this unspec is in a debug_insn.
5830 	     Seen in gcc.dg/pr51957-1.c  */
5831 	}
5832       else
5833 	{
5834 	  debug_rtx (orig_x);
5835 	  abort ();
5836 	}
5837 #endif
5838       y = XVECEXP (y, 0, 0);
5839 
5840 #ifdef HAVE_AS_TLS
5841       /* Do not associate thread-local symbols with the original
5842 	 constant pool symbol.  */
5843       if (TARGET_XCOFF
5844 	  && GET_CODE (y) == SYMBOL_REF
5845 	  && CONSTANT_POOL_ADDRESS_P (y)
5846 	  && SYMBOL_REF_TLS_MODEL (get_pool_constant (y)) >= TLS_MODEL_REAL)
5847 	return orig_x;
5848 #endif
5849 
5850       if (offset != NULL_RTX)
5851 	y = gen_rtx_PLUS (Pmode, y, offset);
5852       if (!MEM_P (orig_x))
5853 	return y;
5854       else
5855 	return replace_equiv_address_nv (orig_x, y);
5856     }
5857 
5858   if (TARGET_MACHO
5859       && GET_CODE (orig_x) == LO_SUM
5860       && GET_CODE (XEXP (orig_x, 1)) == CONST)
5861     {
5862       y = XEXP (XEXP (orig_x, 1), 0);
5863       if (GET_CODE (y) == UNSPEC
5864 	  && XINT (y, 1) == UNSPEC_MACHOPIC_OFFSET)
5865 	return XVECEXP (y, 0, 0);
5866     }
5867 
5868   return orig_x;
5869 }
5870 
5871 /* Return true if X shouldn't be emitted into the debug info.
5872    The linker doesn't like .toc section references from
5873    .debug_* sections, so reject .toc section symbols.  */
5874 
5875 static bool
rs6000_const_not_ok_for_debug_p(rtx x)5876 rs6000_const_not_ok_for_debug_p (rtx x)
5877 {
5878   if (GET_CODE (x) == SYMBOL_REF
5879       && CONSTANT_POOL_ADDRESS_P (x))
5880     {
5881       rtx c = get_pool_constant (x);
5882       enum machine_mode cmode = get_pool_mode (x);
5883       if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (c, cmode))
5884 	return true;
5885     }
5886 
5887   return false;
5888 }
5889 
5890 /* Construct the SYMBOL_REF for the tls_get_addr function.  */
5891 
5892 static GTY(()) rtx rs6000_tls_symbol;
5893 static rtx
rs6000_tls_get_addr(void)5894 rs6000_tls_get_addr (void)
5895 {
5896   if (!rs6000_tls_symbol)
5897     rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
5898 
5899   return rs6000_tls_symbol;
5900 }
5901 
5902 /* Construct the SYMBOL_REF for TLS GOT references.  */
5903 
5904 static GTY(()) rtx rs6000_got_symbol;
5905 static rtx
rs6000_got_sym(void)5906 rs6000_got_sym (void)
5907 {
5908   if (!rs6000_got_symbol)
5909     {
5910       rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
5911       SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
5912       SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
5913     }
5914 
5915   return rs6000_got_symbol;
5916 }
5917 
5918 /* AIX Thread-Local Address support.  */
5919 
5920 static rtx
rs6000_legitimize_tls_address_aix(rtx addr,enum tls_model model)5921 rs6000_legitimize_tls_address_aix (rtx addr, enum tls_model model)
5922 {
5923   rtx sym, mem, tocref, tlsreg, tmpreg, dest, tlsaddr;
5924   const char *name;
5925   char *tlsname;
5926 
5927   name = XSTR (addr, 0);
5928   /* Append TLS CSECT qualifier, unless the symbol already is qualified
5929      or the symbol will be in TLS private data section.  */
5930   if (name[strlen (name) - 1] != ']'
5931       && (TREE_PUBLIC (SYMBOL_REF_DECL (addr))
5932 	  || bss_initializer_p (SYMBOL_REF_DECL (addr))))
5933     {
5934       tlsname = XALLOCAVEC (char, strlen (name) + 4);
5935       strcpy (tlsname, name);
5936       strcat (tlsname,
5937 	      bss_initializer_p (SYMBOL_REF_DECL (addr)) ? "[UL]" : "[TL]");
5938       tlsaddr = copy_rtx (addr);
5939       XSTR (tlsaddr, 0) = ggc_strdup (tlsname);
5940     }
5941   else
5942     tlsaddr = addr;
5943 
5944   /* Place addr into TOC constant pool.  */
5945   sym = force_const_mem (GET_MODE (tlsaddr), tlsaddr);
5946 
5947   /* Output the TOC entry and create the MEM referencing the value.  */
5948   if (constant_pool_expr_p (XEXP (sym, 0))
5949       && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (XEXP (sym, 0)), Pmode))
5950     {
5951       tocref = create_TOC_reference (XEXP (sym, 0), NULL_RTX);
5952       mem = gen_const_mem (Pmode, tocref);
5953       set_mem_alias_set (mem, get_TOC_alias_set ());
5954     }
5955   else
5956     return sym;
5957 
5958   /* Use global-dynamic for local-dynamic.  */
5959   if (model == TLS_MODEL_GLOBAL_DYNAMIC
5960       || model == TLS_MODEL_LOCAL_DYNAMIC)
5961     {
5962       /* Create new TOC reference for @m symbol.  */
5963       name = XSTR (XVECEXP (XEXP (mem, 0), 0, 0), 0);
5964       tlsname = XALLOCAVEC (char, strlen (name) + 1);
5965       strcpy (tlsname, "*LCM");
5966       strcat (tlsname, name + 3);
5967       rtx modaddr = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tlsname));
5968       SYMBOL_REF_FLAGS (modaddr) |= SYMBOL_FLAG_LOCAL;
5969       tocref = create_TOC_reference (modaddr, NULL_RTX);
5970       rtx modmem = gen_const_mem (Pmode, tocref);
5971       set_mem_alias_set (modmem, get_TOC_alias_set ());
5972 
5973       rtx modreg = gen_reg_rtx (Pmode);
5974       emit_insn (gen_rtx_SET (VOIDmode, modreg, modmem));
5975 
5976       tmpreg = gen_reg_rtx (Pmode);
5977       emit_insn (gen_rtx_SET (VOIDmode, tmpreg, mem));
5978 
5979       dest = gen_reg_rtx (Pmode);
5980       if (TARGET_32BIT)
5981 	emit_insn (gen_tls_get_addrsi (dest, modreg, tmpreg));
5982       else
5983 	emit_insn (gen_tls_get_addrdi (dest, modreg, tmpreg));
5984       return dest;
5985     }
5986   /* Obtain TLS pointer: 32 bit call or 64 bit GPR 13.  */
5987   else if (TARGET_32BIT)
5988     {
5989       tlsreg = gen_reg_rtx (SImode);
5990       emit_insn (gen_tls_get_tpointer (tlsreg));
5991     }
5992   else
5993     tlsreg = gen_rtx_REG (DImode, 13);
5994 
5995   /* Load the TOC value into temporary register.  */
5996   tmpreg = gen_reg_rtx (Pmode);
5997   emit_insn (gen_rtx_SET (VOIDmode, tmpreg, mem));
5998   set_unique_reg_note (get_last_insn (), REG_EQUAL,
5999 		       gen_rtx_MINUS (Pmode, addr, tlsreg));
6000 
6001   /* Add TOC symbol value to TLS pointer.  */
6002   dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tmpreg, tlsreg));
6003 
6004   return dest;
6005 }
6006 
6007 /* ADDR contains a thread-local SYMBOL_REF.  Generate code to compute
6008    this (thread-local) address.  */
6009 
6010 static rtx
rs6000_legitimize_tls_address(rtx addr,enum tls_model model)6011 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
6012 {
6013   rtx dest, insn;
6014 
6015   if (TARGET_XCOFF)
6016     return rs6000_legitimize_tls_address_aix (addr, model);
6017 
6018   dest = gen_reg_rtx (Pmode);
6019   if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
6020     {
6021       rtx tlsreg;
6022 
6023       if (TARGET_64BIT)
6024 	{
6025 	  tlsreg = gen_rtx_REG (Pmode, 13);
6026 	  insn = gen_tls_tprel_64 (dest, tlsreg, addr);
6027 	}
6028       else
6029 	{
6030 	  tlsreg = gen_rtx_REG (Pmode, 2);
6031 	  insn = gen_tls_tprel_32 (dest, tlsreg, addr);
6032 	}
6033       emit_insn (insn);
6034     }
6035   else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
6036     {
6037       rtx tlsreg, tmp;
6038 
6039       tmp = gen_reg_rtx (Pmode);
6040       if (TARGET_64BIT)
6041 	{
6042 	  tlsreg = gen_rtx_REG (Pmode, 13);
6043 	  insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
6044 	}
6045       else
6046 	{
6047 	  tlsreg = gen_rtx_REG (Pmode, 2);
6048 	  insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
6049 	}
6050       emit_insn (insn);
6051       if (TARGET_64BIT)
6052 	insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
6053       else
6054 	insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
6055       emit_insn (insn);
6056     }
6057   else
6058     {
6059       rtx r3, got, tga, tmp1, tmp2, call_insn;
6060 
6061       /* We currently use relocations like @got@tlsgd for tls, which
6062 	 means the linker will handle allocation of tls entries, placing
6063 	 them in the .got section.  So use a pointer to the .got section,
6064 	 not one to secondary TOC sections used by 64-bit -mminimal-toc,
6065 	 or to secondary GOT sections used by 32-bit -fPIC.  */
6066       if (TARGET_64BIT)
6067 	got = gen_rtx_REG (Pmode, 2);
6068       else
6069 	{
6070 	  if (flag_pic == 1)
6071 	    got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
6072 	  else
6073 	    {
6074 	      rtx gsym = rs6000_got_sym ();
6075 	      got = gen_reg_rtx (Pmode);
6076 	      if (flag_pic == 0)
6077 		rs6000_emit_move (got, gsym, Pmode);
6078 	      else
6079 		{
6080 		  rtx mem, lab, last;
6081 
6082 		  tmp1 = gen_reg_rtx (Pmode);
6083 		  tmp2 = gen_reg_rtx (Pmode);
6084 		  mem = gen_const_mem (Pmode, tmp1);
6085 		  lab = gen_label_rtx ();
6086 		  emit_insn (gen_load_toc_v4_PIC_1b (gsym, lab));
6087 		  emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
6088 		  if (TARGET_LINK_STACK)
6089 		    emit_insn (gen_addsi3 (tmp1, tmp1, GEN_INT (4)));
6090 		  emit_move_insn (tmp2, mem);
6091 		  last = emit_insn (gen_addsi3 (got, tmp1, tmp2));
6092 		  set_unique_reg_note (last, REG_EQUAL, gsym);
6093 		}
6094 	    }
6095 	}
6096 
6097       if (model == TLS_MODEL_GLOBAL_DYNAMIC)
6098 	{
6099 	  tga = rs6000_tls_get_addr ();
6100 	  emit_library_call_value (tga, dest, LCT_CONST, Pmode,
6101 				   1, const0_rtx, Pmode);
6102 
6103 	  r3 = gen_rtx_REG (Pmode, 3);
6104 	  if (DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
6105 	    insn = gen_tls_gd_aix64 (r3, got, addr, tga, const0_rtx);
6106 	  else if (DEFAULT_ABI == ABI_AIX && !TARGET_64BIT)
6107 	    insn = gen_tls_gd_aix32 (r3, got, addr, tga, const0_rtx);
6108 	  else if (DEFAULT_ABI == ABI_V4)
6109 	    insn = gen_tls_gd_sysvsi (r3, got, addr, tga, const0_rtx);
6110 	  else
6111 	    gcc_unreachable ();
6112 	  call_insn = last_call_insn ();
6113 	  PATTERN (call_insn) = insn;
6114 	  if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
6115 	    use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
6116 		     pic_offset_table_rtx);
6117 	}
6118       else if (model == TLS_MODEL_LOCAL_DYNAMIC)
6119 	{
6120 	  tga = rs6000_tls_get_addr ();
6121 	  tmp1 = gen_reg_rtx (Pmode);
6122 	  emit_library_call_value (tga, tmp1, LCT_CONST, Pmode,
6123 				   1, const0_rtx, Pmode);
6124 
6125 	  r3 = gen_rtx_REG (Pmode, 3);
6126 	  if (DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
6127 	    insn = gen_tls_ld_aix64 (r3, got, tga, const0_rtx);
6128 	  else if (DEFAULT_ABI == ABI_AIX && !TARGET_64BIT)
6129 	    insn = gen_tls_ld_aix32 (r3, got, tga, const0_rtx);
6130 	  else if (DEFAULT_ABI == ABI_V4)
6131 	    insn = gen_tls_ld_sysvsi (r3, got, tga, const0_rtx);
6132 	  else
6133 	    gcc_unreachable ();
6134 	  call_insn = last_call_insn ();
6135 	  PATTERN (call_insn) = insn;
6136 	  if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
6137 	    use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
6138 		     pic_offset_table_rtx);
6139 
6140 	  if (rs6000_tls_size == 16)
6141 	    {
6142 	      if (TARGET_64BIT)
6143 		insn = gen_tls_dtprel_64 (dest, tmp1, addr);
6144 	      else
6145 		insn = gen_tls_dtprel_32 (dest, tmp1, addr);
6146 	    }
6147 	  else if (rs6000_tls_size == 32)
6148 	    {
6149 	      tmp2 = gen_reg_rtx (Pmode);
6150 	      if (TARGET_64BIT)
6151 		insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
6152 	      else
6153 		insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
6154 	      emit_insn (insn);
6155 	      if (TARGET_64BIT)
6156 		insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
6157 	      else
6158 		insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
6159 	    }
6160 	  else
6161 	    {
6162 	      tmp2 = gen_reg_rtx (Pmode);
6163 	      if (TARGET_64BIT)
6164 		insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
6165 	      else
6166 		insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
6167 	      emit_insn (insn);
6168 	      insn = gen_rtx_SET (Pmode, dest,
6169 				  gen_rtx_PLUS (Pmode, tmp2, tmp1));
6170 	    }
6171 	  emit_insn (insn);
6172 	}
6173       else
6174 	{
6175 	  /* IE, or 64-bit offset LE.  */
6176 	  tmp2 = gen_reg_rtx (Pmode);
6177 	  if (TARGET_64BIT)
6178 	    insn = gen_tls_got_tprel_64 (tmp2, got, addr);
6179 	  else
6180 	    insn = gen_tls_got_tprel_32 (tmp2, got, addr);
6181 	  emit_insn (insn);
6182 	  if (TARGET_64BIT)
6183 	    insn = gen_tls_tls_64 (dest, tmp2, addr);
6184 	  else
6185 	    insn = gen_tls_tls_32 (dest, tmp2, addr);
6186 	  emit_insn (insn);
6187 	}
6188     }
6189 
6190   return dest;
6191 }
6192 
6193 /* Return 1 if X contains a thread-local symbol.  */
6194 
6195 static bool
rs6000_tls_referenced_p(rtx x)6196 rs6000_tls_referenced_p (rtx x)
6197 {
6198   if (! TARGET_HAVE_TLS)
6199     return false;
6200 
6201   return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
6202 }
6203 
6204 /* Implement TARGET_CANNOT_FORCE_CONST_MEM.  */
6205 
6206 static bool
rs6000_cannot_force_const_mem(enum machine_mode mode ATTRIBUTE_UNUSED,rtx x)6207 rs6000_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
6208 {
6209   if (GET_CODE (x) == HIGH
6210       && GET_CODE (XEXP (x, 0)) == UNSPEC)
6211     return true;
6212 
6213   /* A TLS symbol in the TOC cannot contain a sum.  */
6214   if (GET_CODE (x) == CONST
6215       && GET_CODE (XEXP (x, 0)) == PLUS
6216       && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
6217       && SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0)) != 0)
6218     return true;
6219 
6220   /* Do not place an ELF TLS symbol in the constant pool.  */
6221   return TARGET_ELF && rs6000_tls_referenced_p (x);
6222 }
6223 
6224 /* Return 1 if *X is a thread-local symbol.  This is the same as
6225    rs6000_tls_symbol_ref except for the type of the unused argument.  */
6226 
6227 static int
rs6000_tls_symbol_ref_1(rtx * x,void * data ATTRIBUTE_UNUSED)6228 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
6229 {
6230   return RS6000_SYMBOL_REF_TLS_P (*x);
6231 }
6232 
6233 /* Return true iff the given SYMBOL_REF refers to a constant pool entry
6234    that we have put in the TOC, or for cmodel=medium, if the SYMBOL_REF
6235    can be addressed relative to the toc pointer.  */
6236 
6237 static bool
use_toc_relative_ref(rtx sym)6238 use_toc_relative_ref (rtx sym)
6239 {
6240   return ((constant_pool_expr_p (sym)
6241 	   && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym),
6242 					       get_pool_mode (sym)))
6243 	  || (TARGET_CMODEL == CMODEL_MEDIUM
6244 	      && !CONSTANT_POOL_ADDRESS_P (sym)
6245 	      && SYMBOL_REF_LOCAL_P (sym)));
6246 }
6247 
6248 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS.  Returns a value to
6249    replace the input X, or the original X if no replacement is called for.
6250    The output parameter *WIN is 1 if the calling macro should goto WIN,
6251    0 if it should not.
6252 
6253    For RS/6000, we wish to handle large displacements off a base
6254    register by splitting the addend across an addiu/addis and the mem insn.
6255    This cuts number of extra insns needed from 3 to 1.
6256 
6257    On Darwin, we use this to generate code for floating point constants.
6258    A movsf_low is generated so we wind up with 2 instructions rather than 3.
6259    The Darwin code is inside #if TARGET_MACHO because only then are the
6260    machopic_* functions defined.  */
6261 static rtx
rs6000_legitimize_reload_address(rtx x,enum machine_mode mode,int opnum,int type,int ind_levels ATTRIBUTE_UNUSED,int * win)6262 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
6263 				  int opnum, int type,
6264 				  int ind_levels ATTRIBUTE_UNUSED, int *win)
6265 {
6266   bool reg_offset_p = reg_offset_addressing_ok_p (mode);
6267 
6268   /* Nasty hack for vsx_splat_V2DF/V2DI load from mem, which takes a
6269      DFmode/DImode MEM.  */
6270   if (reg_offset_p
6271       && opnum == 1
6272       && ((mode == DFmode && recog_data.operand_mode[0] == V2DFmode)
6273 	  || (mode == DImode && recog_data.operand_mode[0] == V2DImode)))
6274     reg_offset_p = false;
6275 
6276   /* We must recognize output that we have already generated ourselves.  */
6277   if (GET_CODE (x) == PLUS
6278       && GET_CODE (XEXP (x, 0)) == PLUS
6279       && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
6280       && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6281       && GET_CODE (XEXP (x, 1)) == CONST_INT)
6282     {
6283       push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6284 		   BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
6285 		   opnum, (enum reload_type) type);
6286       *win = 1;
6287       return x;
6288     }
6289 
6290   /* Likewise for (lo_sum (high ...) ...) output we have generated.  */
6291   if (GET_CODE (x) == LO_SUM
6292       && GET_CODE (XEXP (x, 0)) == HIGH)
6293     {
6294       push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6295 		   BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
6296 		   opnum, (enum reload_type) type);
6297       *win = 1;
6298       return x;
6299     }
6300 
6301 #if TARGET_MACHO
6302   if (DEFAULT_ABI == ABI_DARWIN && flag_pic
6303       && GET_CODE (x) == LO_SUM
6304       && GET_CODE (XEXP (x, 0)) == PLUS
6305       && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
6306       && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
6307       && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
6308       && machopic_operand_p (XEXP (x, 1)))
6309     {
6310       /* Result of previous invocation of this function on Darwin
6311 	 floating point constant.  */
6312       push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6313 		   BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
6314 		   opnum, (enum reload_type) type);
6315       *win = 1;
6316       return x;
6317     }
6318 #endif
6319 
6320   if (TARGET_CMODEL != CMODEL_SMALL
6321       && reg_offset_p
6322       && small_toc_ref (x, VOIDmode))
6323     {
6324       rtx hi = gen_rtx_HIGH (Pmode, copy_rtx (x));
6325       x = gen_rtx_LO_SUM (Pmode, hi, x);
6326       push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6327 		   BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
6328 		   opnum, (enum reload_type) type);
6329       *win = 1;
6330       return x;
6331     }
6332 
6333   if (GET_CODE (x) == PLUS
6334       && GET_CODE (XEXP (x, 0)) == REG
6335       && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
6336       && INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 1)
6337       && GET_CODE (XEXP (x, 1)) == CONST_INT
6338       && reg_offset_p
6339       && !SPE_VECTOR_MODE (mode)
6340       && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
6341 				  || mode == DDmode || mode == TDmode
6342 				  || mode == DImode))
6343       && VECTOR_MEM_NONE_P (mode))
6344     {
6345       HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
6346       HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
6347       HOST_WIDE_INT high
6348 	= (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
6349 
6350       /* Check for 32-bit overflow.  */
6351       if (high + low != val)
6352 	{
6353 	  *win = 0;
6354 	  return x;
6355 	}
6356 
6357       /* Reload the high part into a base reg; leave the low part
6358 	 in the mem directly.  */
6359 
6360       x = gen_rtx_PLUS (GET_MODE (x),
6361 			gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
6362 				      GEN_INT (high)),
6363 			GEN_INT (low));
6364 
6365       push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6366 		   BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
6367 		   opnum, (enum reload_type) type);
6368       *win = 1;
6369       return x;
6370     }
6371 
6372   if (GET_CODE (x) == SYMBOL_REF
6373       && reg_offset_p
6374       && VECTOR_MEM_NONE_P (mode)
6375       && !SPE_VECTOR_MODE (mode)
6376 #if TARGET_MACHO
6377       && DEFAULT_ABI == ABI_DARWIN
6378       && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
6379       && machopic_symbol_defined_p (x)
6380 #else
6381       && DEFAULT_ABI == ABI_V4
6382       && !flag_pic
6383 #endif
6384       /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
6385 	 The same goes for DImode without 64-bit gprs and DFmode and DDmode
6386 	 without fprs.
6387 	 ??? Assume floating point reg based on mode?  This assumption is
6388 	 violated by eg. powerpc-linux -m32 compile of gcc.dg/pr28796-2.c
6389 	 where reload ends up doing a DFmode load of a constant from
6390 	 mem using two gprs.  Unfortunately, at this point reload
6391 	 hasn't yet selected regs so poking around in reload data
6392 	 won't help and even if we could figure out the regs reliably,
6393 	 we'd still want to allow this transformation when the mem is
6394 	 naturally aligned.  Since we say the address is good here, we
6395 	 can't disable offsets from LO_SUMs in mem_operand_gpr.
6396 	 FIXME: Allow offset from lo_sum for other modes too, when
6397 	 mem is sufficiently aligned.  */
6398       && mode != TFmode
6399       && mode != TDmode
6400       && (mode != DImode || TARGET_POWERPC64)
6401       && ((mode != DFmode && mode != DDmode) || TARGET_POWERPC64
6402 	  || (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)))
6403     {
6404 #if TARGET_MACHO
6405       if (flag_pic)
6406 	{
6407 	  rtx offset = machopic_gen_offset (x);
6408 	  x = gen_rtx_LO_SUM (GET_MODE (x),
6409 		gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
6410 		  gen_rtx_HIGH (Pmode, offset)), offset);
6411 	}
6412       else
6413 #endif
6414 	x = gen_rtx_LO_SUM (GET_MODE (x),
6415 	      gen_rtx_HIGH (Pmode, x), x);
6416 
6417       push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6418 		   BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
6419 		   opnum, (enum reload_type) type);
6420       *win = 1;
6421       return x;
6422     }
6423 
6424   /* Reload an offset address wrapped by an AND that represents the
6425      masking of the lower bits.  Strip the outer AND and let reload
6426      convert the offset address into an indirect address.  For VSX,
6427      force reload to create the address with an AND in a separate
6428      register, because we can't guarantee an altivec register will
6429      be used.  */
6430   if (VECTOR_MEM_ALTIVEC_P (mode)
6431       && GET_CODE (x) == AND
6432       && GET_CODE (XEXP (x, 0)) == PLUS
6433       && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
6434       && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6435       && GET_CODE (XEXP (x, 1)) == CONST_INT
6436       && INTVAL (XEXP (x, 1)) == -16)
6437     {
6438       x = XEXP (x, 0);
6439       *win = 1;
6440       return x;
6441     }
6442 
6443   if (TARGET_TOC
6444       && reg_offset_p
6445       && GET_CODE (x) == SYMBOL_REF
6446       && use_toc_relative_ref (x))
6447     {
6448       x = create_TOC_reference (x, NULL_RTX);
6449       if (TARGET_CMODEL != CMODEL_SMALL)
6450 	push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6451 		     BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
6452 		     opnum, (enum reload_type) type);
6453       *win = 1;
6454       return x;
6455     }
6456   *win = 0;
6457   return x;
6458 }
6459 
6460 /* Debug version of rs6000_legitimize_reload_address.  */
6461 static rtx
rs6000_debug_legitimize_reload_address(rtx x,enum machine_mode mode,int opnum,int type,int ind_levels,int * win)6462 rs6000_debug_legitimize_reload_address (rtx x, enum machine_mode mode,
6463 					int opnum, int type,
6464 					int ind_levels, int *win)
6465 {
6466   rtx ret = rs6000_legitimize_reload_address (x, mode, opnum, type,
6467 					      ind_levels, win);
6468   fprintf (stderr,
6469 	   "\nrs6000_legitimize_reload_address: mode = %s, opnum = %d, "
6470 	   "type = %d, ind_levels = %d, win = %d, original addr:\n",
6471 	   GET_MODE_NAME (mode), opnum, type, ind_levels, *win);
6472   debug_rtx (x);
6473 
6474   if (x == ret)
6475     fprintf (stderr, "Same address returned\n");
6476   else if (!ret)
6477     fprintf (stderr, "NULL returned\n");
6478   else
6479     {
6480       fprintf (stderr, "New address:\n");
6481       debug_rtx (ret);
6482     }
6483 
6484   return ret;
6485 }
6486 
6487 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
6488    that is a valid memory address for an instruction.
6489    The MODE argument is the machine mode for the MEM expression
6490    that wants to use this address.
6491 
6492    On the RS/6000, there are four valid address: a SYMBOL_REF that
6493    refers to a constant pool entry of an address (or the sum of it
6494    plus a constant), a short (16-bit signed) constant plus a register,
6495    the sum of two registers, or a register indirect, possibly with an
6496    auto-increment.  For DFmode, DDmode and DImode with a constant plus
6497    register, we must ensure that both words are addressable or PowerPC64
6498    with offset word aligned.
6499 
6500    For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
6501    32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
6502    because adjacent memory cells are accessed by adding word-sized offsets
6503    during assembly output.  */
6504 static bool
rs6000_legitimate_address_p(enum machine_mode mode,rtx x,bool reg_ok_strict)6505 rs6000_legitimate_address_p (enum machine_mode mode, rtx x, bool reg_ok_strict)
6506 {
6507   bool reg_offset_p = reg_offset_addressing_ok_p (mode);
6508 
6509   /* If this is an unaligned stvx/ldvx type address, discard the outer AND.  */
6510   if (VECTOR_MEM_ALTIVEC_P (mode)
6511       && GET_CODE (x) == AND
6512       && GET_CODE (XEXP (x, 1)) == CONST_INT
6513       && INTVAL (XEXP (x, 1)) == -16)
6514     x = XEXP (x, 0);
6515 
6516   if (TARGET_ELF && RS6000_SYMBOL_REF_TLS_P (x))
6517     return 0;
6518   if (legitimate_indirect_address_p (x, reg_ok_strict))
6519     return 1;
6520   if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
6521       && !VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
6522       && !SPE_VECTOR_MODE (mode)
6523       && mode != TFmode
6524       && mode != TDmode
6525       /* Restrict addressing for DI because of our SUBREG hackery.  */
6526       && !(TARGET_E500_DOUBLE
6527 	   && (mode == DFmode || mode == DDmode || mode == DImode))
6528       && TARGET_UPDATE
6529       && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
6530     return 1;
6531   if (virtual_stack_registers_memory_p (x))
6532     return 1;
6533   if (reg_offset_p && legitimate_small_data_p (mode, x))
6534     return 1;
6535   if (reg_offset_p
6536       && legitimate_constant_pool_address_p (x, mode, reg_ok_strict))
6537     return 1;
6538   /* If not REG_OK_STRICT (before reload) let pass any stack offset.  */
6539   if (! reg_ok_strict
6540       && reg_offset_p
6541       && GET_CODE (x) == PLUS
6542       && GET_CODE (XEXP (x, 0)) == REG
6543       && (XEXP (x, 0) == virtual_stack_vars_rtx
6544 	  || XEXP (x, 0) == arg_pointer_rtx)
6545       && GET_CODE (XEXP (x, 1)) == CONST_INT)
6546     return 1;
6547   if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict, false))
6548     return 1;
6549   if (mode != TImode
6550       && mode != TFmode
6551       && mode != TDmode
6552       && ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
6553 	  || TARGET_POWERPC64
6554 	  || (mode != DFmode && mode != DDmode)
6555 	  || (TARGET_E500_DOUBLE && mode != DDmode))
6556       && (TARGET_POWERPC64 || mode != DImode)
6557       && !avoiding_indexed_address_p (mode)
6558       && legitimate_indexed_address_p (x, reg_ok_strict))
6559     return 1;
6560   if (GET_CODE (x) == PRE_MODIFY
6561       && mode != TImode
6562       && mode != TFmode
6563       && mode != TDmode
6564       && ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
6565 	  || TARGET_POWERPC64
6566 	  || ((mode != DFmode && mode != DDmode) || TARGET_E500_DOUBLE))
6567       && (TARGET_POWERPC64 || mode != DImode)
6568       && !VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
6569       && !SPE_VECTOR_MODE (mode)
6570       /* Restrict addressing for DI because of our SUBREG hackery.  */
6571       && !(TARGET_E500_DOUBLE
6572 	   && (mode == DFmode || mode == DDmode || mode == DImode))
6573       && TARGET_UPDATE
6574       && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)
6575       && (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1),
6576 					      reg_ok_strict, false)
6577 	  || (!avoiding_indexed_address_p (mode)
6578 	      && legitimate_indexed_address_p (XEXP (x, 1), reg_ok_strict)))
6579       && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
6580     return 1;
6581   if (reg_offset_p && legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
6582     return 1;
6583   return 0;
6584 }
6585 
6586 /* Debug version of rs6000_legitimate_address_p.  */
6587 static bool
rs6000_debug_legitimate_address_p(enum machine_mode mode,rtx x,bool reg_ok_strict)6588 rs6000_debug_legitimate_address_p (enum machine_mode mode, rtx x,
6589 				   bool reg_ok_strict)
6590 {
6591   bool ret = rs6000_legitimate_address_p (mode, x, reg_ok_strict);
6592   fprintf (stderr,
6593 	   "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
6594 	   "strict = %d, code = %s\n",
6595 	   ret ? "true" : "false",
6596 	   GET_MODE_NAME (mode),
6597 	   reg_ok_strict,
6598 	   GET_RTX_NAME (GET_CODE (x)));
6599   debug_rtx (x);
6600 
6601   return ret;
6602 }
6603 
6604 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P.  */
6605 
6606 static bool
rs6000_mode_dependent_address_p(const_rtx addr,addr_space_t as ATTRIBUTE_UNUSED)6607 rs6000_mode_dependent_address_p (const_rtx addr,
6608 				 addr_space_t as ATTRIBUTE_UNUSED)
6609 {
6610   return rs6000_mode_dependent_address_ptr (addr);
6611 }
6612 
6613 /* Go to LABEL if ADDR (a legitimate address expression)
6614    has an effect that depends on the machine mode it is used for.
6615 
6616    On the RS/6000 this is true of all integral offsets (since AltiVec
6617    and VSX modes don't allow them) or is a pre-increment or decrement.
6618 
6619    ??? Except that due to conceptual problems in offsettable_address_p
6620    we can't really report the problems of integral offsets.  So leave
6621    this assuming that the adjustable offset must be valid for the
6622    sub-words of a TFmode operand, which is what we had before.  */
6623 
6624 static bool
rs6000_mode_dependent_address(const_rtx addr)6625 rs6000_mode_dependent_address (const_rtx addr)
6626 {
6627   switch (GET_CODE (addr))
6628     {
6629     case PLUS:
6630       /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
6631 	 is considered a legitimate address before reload, so there
6632 	 are no offset restrictions in that case.  Note that this
6633 	 condition is safe in strict mode because any address involving
6634 	 virtual_stack_vars_rtx or arg_pointer_rtx would already have
6635 	 been rejected as illegitimate.  */
6636       if (XEXP (addr, 0) != virtual_stack_vars_rtx
6637 	  && XEXP (addr, 0) != arg_pointer_rtx
6638 	  && GET_CODE (XEXP (addr, 1)) == CONST_INT)
6639 	{
6640 	  unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
6641 	  return val + 0x8000 >= 0x10000 - (TARGET_POWERPC64 ? 8 : 12);
6642 	}
6643       break;
6644 
6645     case LO_SUM:
6646       /* Anything in the constant pool is sufficiently aligned that
6647 	 all bytes have the same high part address.  */
6648       return !legitimate_constant_pool_address_p (addr, QImode, false);
6649 
6650     /* Auto-increment cases are now treated generically in recog.c.  */
6651     case PRE_MODIFY:
6652       return TARGET_UPDATE;
6653 
6654     /* AND is only allowed in Altivec loads.  */
6655     case AND:
6656       return true;
6657 
6658     default:
6659       break;
6660     }
6661 
6662   return false;
6663 }
6664 
6665 /* Debug version of rs6000_mode_dependent_address.  */
6666 static bool
rs6000_debug_mode_dependent_address(const_rtx addr)6667 rs6000_debug_mode_dependent_address (const_rtx addr)
6668 {
6669   bool ret = rs6000_mode_dependent_address (addr);
6670 
6671   fprintf (stderr, "\nrs6000_mode_dependent_address: ret = %s\n",
6672 	   ret ? "true" : "false");
6673   debug_rtx (addr);
6674 
6675   return ret;
6676 }
6677 
6678 /* Implement FIND_BASE_TERM.  */
6679 
6680 rtx
rs6000_find_base_term(rtx op)6681 rs6000_find_base_term (rtx op)
6682 {
6683   rtx base;
6684 
6685   base = op;
6686   if (GET_CODE (base) == CONST)
6687     base = XEXP (base, 0);
6688   if (GET_CODE (base) == PLUS)
6689     base = XEXP (base, 0);
6690   if (GET_CODE (base) == UNSPEC)
6691     switch (XINT (base, 1))
6692       {
6693       case UNSPEC_TOCREL:
6694       case UNSPEC_MACHOPIC_OFFSET:
6695 	/* OP represents SYM [+ OFFSET] - ANCHOR.  SYM is the base term
6696 	   for aliasing purposes.  */
6697 	return XVECEXP (base, 0, 0);
6698       }
6699 
6700   return op;
6701 }
6702 
6703 /* More elaborate version of recog's offsettable_memref_p predicate
6704    that works around the ??? note of rs6000_mode_dependent_address.
6705    In particular it accepts
6706 
6707      (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
6708 
6709    in 32-bit mode, that the recog predicate rejects.  */
6710 
6711 static bool
rs6000_offsettable_memref_p(rtx op,enum machine_mode reg_mode)6712 rs6000_offsettable_memref_p (rtx op, enum machine_mode reg_mode)
6713 {
6714   bool worst_case;
6715 
6716   if (!MEM_P (op))
6717     return false;
6718 
6719   /* First mimic offsettable_memref_p.  */
6720   if (offsettable_address_p (true, GET_MODE (op), XEXP (op, 0)))
6721     return true;
6722 
6723   /* offsettable_address_p invokes rs6000_mode_dependent_address, but
6724      the latter predicate knows nothing about the mode of the memory
6725      reference and, therefore, assumes that it is the largest supported
6726      mode (TFmode).  As a consequence, legitimate offsettable memory
6727      references are rejected.  rs6000_legitimate_offset_address_p contains
6728      the correct logic for the PLUS case of rs6000_mode_dependent_address,
6729      at least with a little bit of help here given that we know the
6730      actual registers used.  */
6731   worst_case = ((TARGET_POWERPC64 && GET_MODE_CLASS (reg_mode) == MODE_INT)
6732 		|| GET_MODE_SIZE (reg_mode) == 4);
6733   return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0),
6734 					     true, worst_case);
6735 }
6736 
6737 /* Change register usage conditional on target flags.  */
6738 static void
rs6000_conditional_register_usage(void)6739 rs6000_conditional_register_usage (void)
6740 {
6741   int i;
6742 
6743   if (TARGET_DEBUG_TARGET)
6744     fprintf (stderr, "rs6000_conditional_register_usage called\n");
6745 
6746   /* Set MQ register fixed (already call_used) so that it will not be
6747      allocated.  */
6748   fixed_regs[64] = 1;
6749 
6750   /* 64-bit AIX and Linux reserve GPR13 for thread-private data.  */
6751   if (TARGET_64BIT)
6752     fixed_regs[13] = call_used_regs[13]
6753       = call_really_used_regs[13] = 1;
6754 
6755   /* Conditionally disable FPRs.  */
6756   if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
6757     for (i = 32; i < 64; i++)
6758       fixed_regs[i] = call_used_regs[i]
6759 	= call_really_used_regs[i] = 1;
6760 
6761   /* The TOC register is not killed across calls in a way that is
6762      visible to the compiler.  */
6763   if (DEFAULT_ABI == ABI_AIX)
6764     call_really_used_regs[2] = 0;
6765 
6766   if (DEFAULT_ABI == ABI_V4
6767       && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
6768       && flag_pic == 2)
6769     fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
6770 
6771   if (DEFAULT_ABI == ABI_V4
6772       && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
6773       && flag_pic == 1)
6774     fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
6775       = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
6776       = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
6777 
6778   if (DEFAULT_ABI == ABI_DARWIN
6779       && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
6780       fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
6781       = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
6782       = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
6783 
6784   if (TARGET_TOC && TARGET_MINIMAL_TOC)
6785     fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
6786       = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
6787 
6788   if (TARGET_SPE)
6789     {
6790       global_regs[SPEFSCR_REGNO] = 1;
6791       /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
6792          registers in prologues and epilogues.  We no longer use r14
6793          for FIXED_SCRATCH, but we're keeping r14 out of the allocation
6794          pool for link-compatibility with older versions of GCC.  Once
6795          "old" code has died out, we can return r14 to the allocation
6796          pool.  */
6797       fixed_regs[14]
6798 	= call_used_regs[14]
6799 	= call_really_used_regs[14] = 1;
6800     }
6801 
6802   if (!TARGET_ALTIVEC && !TARGET_VSX)
6803     {
6804       for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
6805 	fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
6806       call_really_used_regs[VRSAVE_REGNO] = 1;
6807     }
6808 
6809   if (TARGET_ALTIVEC || TARGET_VSX)
6810     global_regs[VSCR_REGNO] = 1;
6811 
6812   if (TARGET_ALTIVEC_ABI)
6813     {
6814       for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
6815 	call_used_regs[i] = call_really_used_regs[i] = 1;
6816 
6817       /* AIX reserves VR20:31 in non-extended ABI mode.  */
6818       if (TARGET_XCOFF)
6819 	for (i = FIRST_ALTIVEC_REGNO + 20; i < FIRST_ALTIVEC_REGNO + 32; ++i)
6820 	  fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
6821     }
6822 }
6823 
6824 /* Try to output insns to set TARGET equal to the constant C if it can
6825    be done in less than N insns.  Do all computations in MODE.
6826    Returns the place where the output has been placed if it can be
6827    done and the insns have been emitted.  If it would take more than N
6828    insns, zero is returned and no insns and emitted.  */
6829 
6830 rtx
rs6000_emit_set_const(rtx dest,enum machine_mode mode,rtx source,int n ATTRIBUTE_UNUSED)6831 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
6832 		       rtx source, int n ATTRIBUTE_UNUSED)
6833 {
6834   rtx result, insn, set;
6835   HOST_WIDE_INT c0, c1;
6836 
6837   switch (mode)
6838     {
6839     case  QImode:
6840     case HImode:
6841       if (dest == NULL)
6842 	dest = gen_reg_rtx (mode);
6843       emit_insn (gen_rtx_SET (VOIDmode, dest, source));
6844       return dest;
6845 
6846     case SImode:
6847       result = !can_create_pseudo_p () ? dest : gen_reg_rtx (SImode);
6848 
6849       emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (result),
6850 			      GEN_INT (INTVAL (source)
6851 				       & (~ (HOST_WIDE_INT) 0xffff))));
6852       emit_insn (gen_rtx_SET (VOIDmode, dest,
6853 			      gen_rtx_IOR (SImode, copy_rtx (result),
6854 					   GEN_INT (INTVAL (source) & 0xffff))));
6855       result = dest;
6856       break;
6857 
6858     case DImode:
6859       switch (GET_CODE (source))
6860 	{
6861 	case CONST_INT:
6862 	  c0 = INTVAL (source);
6863 	  c1 = -(c0 < 0);
6864 	  break;
6865 
6866 	case CONST_DOUBLE:
6867 #if HOST_BITS_PER_WIDE_INT >= 64
6868 	  c0 = CONST_DOUBLE_LOW (source);
6869 	  c1 = -(c0 < 0);
6870 #else
6871 	  c0 = CONST_DOUBLE_LOW (source);
6872 	  c1 = CONST_DOUBLE_HIGH (source);
6873 #endif
6874 	  break;
6875 
6876 	default:
6877 	  gcc_unreachable ();
6878 	}
6879 
6880       result = rs6000_emit_set_long_const (dest, c0, c1);
6881       break;
6882 
6883     default:
6884       gcc_unreachable ();
6885     }
6886 
6887   insn = get_last_insn ();
6888   set = single_set (insn);
6889   if (! CONSTANT_P (SET_SRC (set)))
6890     set_unique_reg_note (insn, REG_EQUAL, source);
6891 
6892   return result;
6893 }
6894 
6895 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
6896    fall back to a straight forward decomposition.  We do this to avoid
6897    exponential run times encountered when looking for longer sequences
6898    with rs6000_emit_set_const.  */
6899 static rtx
rs6000_emit_set_long_const(rtx dest,HOST_WIDE_INT c1,HOST_WIDE_INT c2)6900 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
6901 {
6902   if (!TARGET_POWERPC64)
6903     {
6904       rtx operand1, operand2;
6905 
6906       operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
6907 					DImode);
6908       operand2 = operand_subword_force (copy_rtx (dest), WORDS_BIG_ENDIAN != 0,
6909 					DImode);
6910       emit_move_insn (operand1, GEN_INT (c1));
6911       emit_move_insn (operand2, GEN_INT (c2));
6912     }
6913   else
6914     {
6915       HOST_WIDE_INT ud1, ud2, ud3, ud4;
6916 
6917       ud1 = c1 & 0xffff;
6918       ud2 = (c1 & 0xffff0000) >> 16;
6919 #if HOST_BITS_PER_WIDE_INT >= 64
6920       c2 = c1 >> 32;
6921 #endif
6922       ud3 = c2 & 0xffff;
6923       ud4 = (c2 & 0xffff0000) >> 16;
6924 
6925       if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
6926 	  || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
6927 	{
6928 	  if (ud1 & 0x8000)
6929 	    emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) -  0x8000)));
6930 	  else
6931 	    emit_move_insn (dest, GEN_INT (ud1));
6932 	}
6933 
6934       else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
6935 	       || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
6936 	{
6937 	  if (ud2 & 0x8000)
6938 	    emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
6939 					   - 0x80000000));
6940 	  else
6941 	    emit_move_insn (dest, GEN_INT (ud2 << 16));
6942 	  if (ud1 != 0)
6943 	    emit_move_insn (copy_rtx (dest),
6944 			    gen_rtx_IOR (DImode, copy_rtx (dest),
6945 					 GEN_INT (ud1)));
6946 	}
6947       else if (ud3 == 0 && ud4 == 0)
6948 	{
6949 	  gcc_assert (ud2 & 0x8000);
6950 	  emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
6951 					 - 0x80000000));
6952 	  if (ud1 != 0)
6953 	    emit_move_insn (copy_rtx (dest),
6954 			    gen_rtx_IOR (DImode, copy_rtx (dest),
6955 					 GEN_INT (ud1)));
6956 	  emit_move_insn (copy_rtx (dest),
6957 			  gen_rtx_ZERO_EXTEND (DImode,
6958 					       gen_lowpart (SImode,
6959 							    copy_rtx (dest))));
6960 	}
6961       else if ((ud4 == 0xffff && (ud3 & 0x8000))
6962 	       || (ud4 == 0 && ! (ud3 & 0x8000)))
6963 	{
6964 	  if (ud3 & 0x8000)
6965 	    emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
6966 					   - 0x80000000));
6967 	  else
6968 	    emit_move_insn (dest, GEN_INT (ud3 << 16));
6969 
6970 	  if (ud2 != 0)
6971 	    emit_move_insn (copy_rtx (dest),
6972 			    gen_rtx_IOR (DImode, copy_rtx (dest),
6973 					 GEN_INT (ud2)));
6974 	  emit_move_insn (copy_rtx (dest),
6975 			  gen_rtx_ASHIFT (DImode, copy_rtx (dest),
6976 					  GEN_INT (16)));
6977 	  if (ud1 != 0)
6978 	    emit_move_insn (copy_rtx (dest),
6979 			    gen_rtx_IOR (DImode, copy_rtx (dest),
6980 					 GEN_INT (ud1)));
6981 	}
6982       else
6983 	{
6984 	  if (ud4 & 0x8000)
6985 	    emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
6986 					   - 0x80000000));
6987 	  else
6988 	    emit_move_insn (dest, GEN_INT (ud4 << 16));
6989 
6990 	  if (ud3 != 0)
6991 	    emit_move_insn (copy_rtx (dest),
6992 			    gen_rtx_IOR (DImode, copy_rtx (dest),
6993 					 GEN_INT (ud3)));
6994 
6995 	  emit_move_insn (copy_rtx (dest),
6996 			  gen_rtx_ASHIFT (DImode, copy_rtx (dest),
6997 					  GEN_INT (32)));
6998 	  if (ud2 != 0)
6999 	    emit_move_insn (copy_rtx (dest),
7000 			    gen_rtx_IOR (DImode, copy_rtx (dest),
7001 					 GEN_INT (ud2 << 16)));
7002 	  if (ud1 != 0)
7003 	    emit_move_insn (copy_rtx (dest),
7004 			    gen_rtx_IOR (DImode, copy_rtx (dest), GEN_INT (ud1)));
7005 	}
7006     }
7007   return dest;
7008 }
7009 
7010 /* Helper for the following.  Get rid of [r+r] memory refs
7011    in cases where it won't work (TImode, TFmode, TDmode).  */
7012 
7013 static void
rs6000_eliminate_indexed_memrefs(rtx operands[2])7014 rs6000_eliminate_indexed_memrefs (rtx operands[2])
7015 {
7016   if (reload_in_progress)
7017     return;
7018 
7019   if (GET_CODE (operands[0]) == MEM
7020       && GET_CODE (XEXP (operands[0], 0)) != REG
7021       && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0),
7022 					       GET_MODE (operands[0]), false))
7023     operands[0]
7024       = replace_equiv_address (operands[0],
7025 			       copy_addr_to_reg (XEXP (operands[0], 0)));
7026 
7027   if (GET_CODE (operands[1]) == MEM
7028       && GET_CODE (XEXP (operands[1], 0)) != REG
7029       && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0),
7030 					       GET_MODE (operands[1]), false))
7031     operands[1]
7032       = replace_equiv_address (operands[1],
7033 			       copy_addr_to_reg (XEXP (operands[1], 0)));
7034 }
7035 
7036 /* Emit a move from SOURCE to DEST in mode MODE.  */
7037 void
rs6000_emit_move(rtx dest,rtx source,enum machine_mode mode)7038 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
7039 {
7040   rtx operands[2];
7041   operands[0] = dest;
7042   operands[1] = source;
7043 
7044   if (TARGET_DEBUG_ADDR)
7045     {
7046       fprintf (stderr,
7047 	       "\nrs6000_emit_move: mode = %s, reload_in_progress = %d, "
7048 	       "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
7049 	       GET_MODE_NAME (mode),
7050 	       reload_in_progress,
7051 	       reload_completed,
7052 	       can_create_pseudo_p ());
7053       debug_rtx (dest);
7054       fprintf (stderr, "source:\n");
7055       debug_rtx (source);
7056     }
7057 
7058   /* Sanity checks.  Check that we get CONST_DOUBLE only when we should.  */
7059   if (GET_CODE (operands[1]) == CONST_DOUBLE
7060       && ! FLOAT_MODE_P (mode)
7061       && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
7062     {
7063       /* FIXME.  This should never happen.  */
7064       /* Since it seems that it does, do the safe thing and convert
7065 	 to a CONST_INT.  */
7066       operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
7067     }
7068   gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE
7069 	      || FLOAT_MODE_P (mode)
7070 	      || ((CONST_DOUBLE_HIGH (operands[1]) != 0
7071 		   || CONST_DOUBLE_LOW (operands[1]) < 0)
7072 		  && (CONST_DOUBLE_HIGH (operands[1]) != -1
7073 		      || CONST_DOUBLE_LOW (operands[1]) >= 0)));
7074 
7075   /* Check if GCC is setting up a block move that will end up using FP
7076      registers as temporaries.  We must make sure this is acceptable.  */
7077   if (GET_CODE (operands[0]) == MEM
7078       && GET_CODE (operands[1]) == MEM
7079       && mode == DImode
7080       && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
7081 	  || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
7082       && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
7083 					    ? 32 : MEM_ALIGN (operands[0])))
7084 	    || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
7085 					       ? 32
7086 					       : MEM_ALIGN (operands[1]))))
7087       && ! MEM_VOLATILE_P (operands [0])
7088       && ! MEM_VOLATILE_P (operands [1]))
7089     {
7090       emit_move_insn (adjust_address (operands[0], SImode, 0),
7091 		      adjust_address (operands[1], SImode, 0));
7092       emit_move_insn (adjust_address (copy_rtx (operands[0]), SImode, 4),
7093 		      adjust_address (copy_rtx (operands[1]), SImode, 4));
7094       return;
7095     }
7096 
7097   if (can_create_pseudo_p () && GET_CODE (operands[0]) == MEM
7098       && !gpc_reg_operand (operands[1], mode))
7099     operands[1] = force_reg (mode, operands[1]);
7100 
7101   /* Recognize the case where operand[1] is a reference to thread-local
7102      data and load its address to a register.  */
7103   if (rs6000_tls_referenced_p (operands[1]))
7104     {
7105       enum tls_model model;
7106       rtx tmp = operands[1];
7107       rtx addend = NULL;
7108 
7109       if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
7110 	{
7111           addend = XEXP (XEXP (tmp, 0), 1);
7112 	  tmp = XEXP (XEXP (tmp, 0), 0);
7113 	}
7114 
7115       gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
7116       model = SYMBOL_REF_TLS_MODEL (tmp);
7117       gcc_assert (model != 0);
7118 
7119       tmp = rs6000_legitimize_tls_address (tmp, model);
7120       if (addend)
7121 	{
7122 	  tmp = gen_rtx_PLUS (mode, tmp, addend);
7123 	  tmp = force_operand (tmp, operands[0]);
7124 	}
7125       operands[1] = tmp;
7126     }
7127 
7128   /* Handle the case where reload calls us with an invalid address.  */
7129   if (reload_in_progress && mode == Pmode
7130       && (! general_operand (operands[1], mode)
7131 	  || ! nonimmediate_operand (operands[0], mode)))
7132     goto emit_set;
7133 
7134   /* 128-bit constant floating-point values on Darwin should really be
7135      loaded as two parts.  */
7136   if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128
7137       && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
7138     {
7139       rs6000_emit_move (simplify_gen_subreg (DFmode, operands[0], mode, 0),
7140 			simplify_gen_subreg (DFmode, operands[1], mode, 0),
7141 			DFmode);
7142       rs6000_emit_move (simplify_gen_subreg (DFmode, operands[0], mode,
7143 					     GET_MODE_SIZE (DFmode)),
7144 			simplify_gen_subreg (DFmode, operands[1], mode,
7145 					     GET_MODE_SIZE (DFmode)),
7146 			DFmode);
7147       return;
7148     }
7149 
7150   if (reload_in_progress && cfun->machine->sdmode_stack_slot != NULL_RTX)
7151     cfun->machine->sdmode_stack_slot =
7152       eliminate_regs (cfun->machine->sdmode_stack_slot, VOIDmode, NULL_RTX);
7153 
7154   if (reload_in_progress
7155       && mode == SDmode
7156       && MEM_P (operands[0])
7157       && rtx_equal_p (operands[0], cfun->machine->sdmode_stack_slot)
7158       && REG_P (operands[1]))
7159     {
7160       if (FP_REGNO_P (REGNO (operands[1])))
7161 	{
7162 	  rtx mem = adjust_address_nv (operands[0], DDmode, 0);
7163 	  mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
7164 	  emit_insn (gen_movsd_store (mem, operands[1]));
7165 	}
7166       else if (INT_REGNO_P (REGNO (operands[1])))
7167 	{
7168 	  rtx mem = adjust_address_nv (operands[0], mode, 4);
7169 	  mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
7170 	  emit_insn (gen_movsd_hardfloat (mem, operands[1]));
7171 	}
7172       else
7173 	gcc_unreachable();
7174       return;
7175     }
7176   if (reload_in_progress
7177       && mode == SDmode
7178       && REG_P (operands[0])
7179       && MEM_P (operands[1])
7180       && rtx_equal_p (operands[1], cfun->machine->sdmode_stack_slot))
7181     {
7182       if (FP_REGNO_P (REGNO (operands[0])))
7183 	{
7184 	  rtx mem = adjust_address_nv (operands[1], DDmode, 0);
7185 	  mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
7186 	  emit_insn (gen_movsd_load (operands[0], mem));
7187 	}
7188       else if (INT_REGNO_P (REGNO (operands[0])))
7189 	{
7190 	  rtx mem = adjust_address_nv (operands[1], mode, 4);
7191 	  mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
7192 	  emit_insn (gen_movsd_hardfloat (operands[0], mem));
7193 	}
7194       else
7195 	gcc_unreachable();
7196       return;
7197     }
7198 
7199   /* FIXME:  In the long term, this switch statement should go away
7200      and be replaced by a sequence of tests based on things like
7201      mode == Pmode.  */
7202   switch (mode)
7203     {
7204     case HImode:
7205     case QImode:
7206       if (CONSTANT_P (operands[1])
7207 	  && GET_CODE (operands[1]) != CONST_INT)
7208 	operands[1] = force_const_mem (mode, operands[1]);
7209       break;
7210 
7211     case TFmode:
7212     case TDmode:
7213       rs6000_eliminate_indexed_memrefs (operands);
7214       /* fall through */
7215 
7216     case DFmode:
7217     case DDmode:
7218     case SFmode:
7219     case SDmode:
7220       if (CONSTANT_P (operands[1])
7221 	  && ! easy_fp_constant (operands[1], mode))
7222 	operands[1] = force_const_mem (mode, operands[1]);
7223       break;
7224 
7225     case V16QImode:
7226     case V8HImode:
7227     case V4SFmode:
7228     case V4SImode:
7229     case V4HImode:
7230     case V2SFmode:
7231     case V2SImode:
7232     case V1DImode:
7233     case V2DFmode:
7234     case V2DImode:
7235       if (CONSTANT_P (operands[1])
7236 	  && !easy_vector_constant (operands[1], mode))
7237 	operands[1] = force_const_mem (mode, operands[1]);
7238       break;
7239 
7240     case SImode:
7241     case DImode:
7242       /* Use default pattern for address of ELF small data */
7243       if (TARGET_ELF
7244 	  && mode == Pmode
7245 	  && DEFAULT_ABI == ABI_V4
7246 	  && (GET_CODE (operands[1]) == SYMBOL_REF
7247 	      || GET_CODE (operands[1]) == CONST)
7248 	  && small_data_operand (operands[1], mode))
7249 	{
7250 	  emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
7251 	  return;
7252 	}
7253 
7254       if (DEFAULT_ABI == ABI_V4
7255 	  && mode == Pmode && mode == SImode
7256 	  && flag_pic == 1 && got_operand (operands[1], mode))
7257 	{
7258 	  emit_insn (gen_movsi_got (operands[0], operands[1]));
7259 	  return;
7260 	}
7261 
7262       if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
7263 	  && TARGET_NO_TOC
7264 	  && ! flag_pic
7265 	  && mode == Pmode
7266 	  && CONSTANT_P (operands[1])
7267 	  && GET_CODE (operands[1]) != HIGH
7268 	  && GET_CODE (operands[1]) != CONST_INT)
7269 	{
7270 	  rtx target = (!can_create_pseudo_p ()
7271 			? operands[0]
7272 			: gen_reg_rtx (mode));
7273 
7274 	  /* If this is a function address on -mcall-aixdesc,
7275 	     convert it to the address of the descriptor.  */
7276 	  if (DEFAULT_ABI == ABI_AIX
7277 	      && GET_CODE (operands[1]) == SYMBOL_REF
7278 	      && XSTR (operands[1], 0)[0] == '.')
7279 	    {
7280 	      const char *name = XSTR (operands[1], 0);
7281 	      rtx new_ref;
7282 	      while (*name == '.')
7283 		name++;
7284 	      new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
7285 	      CONSTANT_POOL_ADDRESS_P (new_ref)
7286 		= CONSTANT_POOL_ADDRESS_P (operands[1]);
7287 	      SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
7288 	      SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
7289 	      SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
7290 	      operands[1] = new_ref;
7291 	    }
7292 
7293 	  if (DEFAULT_ABI == ABI_DARWIN)
7294 	    {
7295 #if TARGET_MACHO
7296 	      if (MACHO_DYNAMIC_NO_PIC_P)
7297 		{
7298 		  /* Take care of any required data indirection.  */
7299 		  operands[1] = rs6000_machopic_legitimize_pic_address (
7300 				  operands[1], mode, operands[0]);
7301 		  if (operands[0] != operands[1])
7302 		    emit_insn (gen_rtx_SET (VOIDmode,
7303 					    operands[0], operands[1]));
7304 		  return;
7305 		}
7306 #endif
7307 	      emit_insn (gen_macho_high (target, operands[1]));
7308 	      emit_insn (gen_macho_low (operands[0], target, operands[1]));
7309 	      return;
7310 	    }
7311 
7312 	  emit_insn (gen_elf_high (target, operands[1]));
7313 	  emit_insn (gen_elf_low (operands[0], target, operands[1]));
7314 	  return;
7315 	}
7316 
7317       /* If this is a SYMBOL_REF that refers to a constant pool entry,
7318 	 and we have put it in the TOC, we just need to make a TOC-relative
7319 	 reference to it.  */
7320       if (TARGET_TOC
7321 	  && GET_CODE (operands[1]) == SYMBOL_REF
7322 	  && use_toc_relative_ref (operands[1]))
7323 	operands[1] = create_TOC_reference (operands[1], operands[0]);
7324       else if (mode == Pmode
7325 	       && CONSTANT_P (operands[1])
7326 	       && GET_CODE (operands[1]) != HIGH
7327 	       && ((GET_CODE (operands[1]) != CONST_INT
7328 		    && ! easy_fp_constant (operands[1], mode))
7329 		   || (GET_CODE (operands[1]) == CONST_INT
7330 		       && (num_insns_constant (operands[1], mode)
7331 			   > (TARGET_CMODEL != CMODEL_SMALL ? 3 : 2)))
7332 		   || (GET_CODE (operands[0]) == REG
7333 		       && FP_REGNO_P (REGNO (operands[0]))))
7334 	       && !toc_relative_expr_p (operands[1], false)
7335 	       && (TARGET_CMODEL == CMODEL_SMALL
7336 		   || can_create_pseudo_p ()
7337 		   || (REG_P (operands[0])
7338 		       && INT_REG_OK_FOR_BASE_P (operands[0], true))))
7339 	{
7340 
7341 #if TARGET_MACHO
7342 	  /* Darwin uses a special PIC legitimizer.  */
7343 	  if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
7344 	    {
7345 	      operands[1] =
7346 		rs6000_machopic_legitimize_pic_address (operands[1], mode,
7347 							operands[0]);
7348 	      if (operands[0] != operands[1])
7349 		emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
7350 	      return;
7351 	    }
7352 #endif
7353 
7354 	  /* If we are to limit the number of things we put in the TOC and
7355 	     this is a symbol plus a constant we can add in one insn,
7356 	     just put the symbol in the TOC and add the constant.  Don't do
7357 	     this if reload is in progress.  */
7358 	  if (GET_CODE (operands[1]) == CONST
7359 	      && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
7360 	      && GET_CODE (XEXP (operands[1], 0)) == PLUS
7361 	      && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
7362 	      && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
7363 		  || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
7364 	      && ! side_effects_p (operands[0]))
7365 	    {
7366 	      rtx sym =
7367 		force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
7368 	      rtx other = XEXP (XEXP (operands[1], 0), 1);
7369 
7370 	      sym = force_reg (mode, sym);
7371 	      emit_insn (gen_add3_insn (operands[0], sym, other));
7372 	      return;
7373 	    }
7374 
7375 	  operands[1] = force_const_mem (mode, operands[1]);
7376 
7377 	  if (TARGET_TOC
7378 	      && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
7379 	      && constant_pool_expr_p (XEXP (operands[1], 0))
7380 	      && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
7381 			get_pool_constant (XEXP (operands[1], 0)),
7382 			get_pool_mode (XEXP (operands[1], 0))))
7383 	    {
7384 	      rtx tocref = create_TOC_reference (XEXP (operands[1], 0),
7385 						 operands[0]);
7386 	      operands[1] = gen_const_mem (mode, tocref);
7387 	      set_mem_alias_set (operands[1], get_TOC_alias_set ());
7388 	    }
7389 	}
7390       break;
7391 
7392     case TImode:
7393       rs6000_eliminate_indexed_memrefs (operands);
7394       break;
7395 
7396     default:
7397       fatal_insn ("bad move", gen_rtx_SET (VOIDmode, dest, source));
7398     }
7399 
7400   /* Above, we may have called force_const_mem which may have returned
7401      an invalid address.  If we can, fix this up; otherwise, reload will
7402      have to deal with it.  */
7403   if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
7404     operands[1] = validize_mem (operands[1]);
7405 
7406  emit_set:
7407   emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
7408 }
7409 
7410 /* Return true if a structure, union or array containing FIELD should be
7411    accessed using `BLKMODE'.
7412 
7413    For the SPE, simd types are V2SI, and gcc can be tempted to put the
7414    entire thing in a DI and use subregs to access the internals.
7415    store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
7416    back-end.  Because a single GPR can hold a V2SI, but not a DI, the
7417    best thing to do is set structs to BLKmode and avoid Severe Tire
7418    Damage.
7419 
7420    On e500 v2, DF and DI modes suffer from the same anomaly.  DF can
7421    fit into 1, whereas DI still needs two.  */
7422 
7423 static bool
rs6000_member_type_forces_blk(const_tree field,enum machine_mode mode)7424 rs6000_member_type_forces_blk (const_tree field, enum machine_mode mode)
7425 {
7426   return ((TARGET_SPE && TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
7427 	  || (TARGET_E500_DOUBLE && mode == DFmode));
7428 }
7429 
7430 /* Nonzero if we can use a floating-point register to pass this arg.  */
7431 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE)		\
7432   (SCALAR_FLOAT_MODE_P (MODE)			\
7433    && (CUM)->fregno <= FP_ARG_MAX_REG		\
7434    && TARGET_HARD_FLOAT && TARGET_FPRS)
7435 
7436 /* Nonzero if we can use an AltiVec register to pass this arg.  */
7437 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED)		\
7438   (ALTIVEC_OR_VSX_VECTOR_MODE (MODE)				\
7439    && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG			\
7440    && TARGET_ALTIVEC_ABI					\
7441    && (NAMED))
7442 
7443 /* Return a nonzero value to say to return the function value in
7444    memory, just as large structures are always returned.  TYPE will be
7445    the data type of the value, and FNTYPE will be the type of the
7446    function doing the returning, or @code{NULL} for libcalls.
7447 
7448    The AIX ABI for the RS/6000 specifies that all structures are
7449    returned in memory.  The Darwin ABI does the same.
7450 
7451    For the Darwin 64 Bit ABI, a function result can be returned in
7452    registers or in memory, depending on the size of the return data
7453    type.  If it is returned in registers, the value occupies the same
7454    registers as it would if it were the first and only function
7455    argument.  Otherwise, the function places its result in memory at
7456    the location pointed to by GPR3.
7457 
7458    The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
7459    but a draft put them in memory, and GCC used to implement the draft
7460    instead of the final standard.  Therefore, aix_struct_return
7461    controls this instead of DEFAULT_ABI; V.4 targets needing backward
7462    compatibility can change DRAFT_V4_STRUCT_RET to override the
7463    default, and -m switches get the final word.  See
7464    rs6000_option_override_internal for more details.
7465 
7466    The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
7467    long double support is enabled.  These values are returned in memory.
7468 
7469    int_size_in_bytes returns -1 for variable size objects, which go in
7470    memory always.  The cast to unsigned makes -1 > 8.  */
7471 
7472 static bool
rs6000_return_in_memory(const_tree type,const_tree fntype ATTRIBUTE_UNUSED)7473 rs6000_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
7474 {
7475   /* For the Darwin64 ABI, test if we can fit the return value in regs.  */
7476   if (TARGET_MACHO
7477       && rs6000_darwin64_abi
7478       && TREE_CODE (type) == RECORD_TYPE
7479       && int_size_in_bytes (type) > 0)
7480     {
7481       CUMULATIVE_ARGS valcum;
7482       rtx valret;
7483 
7484       valcum.words = 0;
7485       valcum.fregno = FP_ARG_MIN_REG;
7486       valcum.vregno = ALTIVEC_ARG_MIN_REG;
7487       /* Do a trial code generation as if this were going to be passed
7488 	 as an argument; if any part goes in memory, we return NULL.  */
7489       valret = rs6000_darwin64_record_arg (&valcum, type, true, true);
7490       if (valret)
7491 	return false;
7492       /* Otherwise fall through to more conventional ABI rules.  */
7493     }
7494 
7495   if (AGGREGATE_TYPE_P (type)
7496       && (aix_struct_return
7497 	  || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
7498     return true;
7499 
7500   /* Allow -maltivec -mabi=no-altivec without warning.  Altivec vector
7501      modes only exist for GCC vector types if -maltivec.  */
7502   if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
7503       && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
7504     return false;
7505 
7506   /* Return synthetic vectors in memory.  */
7507   if (TREE_CODE (type) == VECTOR_TYPE
7508       && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
7509     {
7510       static bool warned_for_return_big_vectors = false;
7511       if (!warned_for_return_big_vectors)
7512 	{
7513 	  warning (0, "GCC vector returned by reference: "
7514 		   "non-standard ABI extension with no compatibility guarantee");
7515 	  warned_for_return_big_vectors = true;
7516 	}
7517       return true;
7518     }
7519 
7520   if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && TYPE_MODE (type) == TFmode)
7521     return true;
7522 
7523   return false;
7524 }
7525 
7526 #ifdef HAVE_AS_GNU_ATTRIBUTE
7527 /* Return TRUE if a call to function FNDECL may be one that
7528    potentially affects the function calling ABI of the object file.  */
7529 
7530 static bool
call_ABI_of_interest(tree fndecl)7531 call_ABI_of_interest (tree fndecl)
7532 {
7533   if (cgraph_state == CGRAPH_STATE_EXPANSION)
7534     {
7535       struct cgraph_node *c_node;
7536 
7537       /* Libcalls are always interesting.  */
7538       if (fndecl == NULL_TREE)
7539 	return true;
7540 
7541       /* Any call to an external function is interesting.  */
7542       if (DECL_EXTERNAL (fndecl))
7543 	return true;
7544 
7545       /* Interesting functions that we are emitting in this object file.  */
7546       c_node = cgraph_get_node (fndecl);
7547       c_node = cgraph_function_or_thunk_node (c_node, NULL);
7548       return !cgraph_only_called_directly_p (c_node);
7549     }
7550   return false;
7551 }
7552 #endif
7553 
7554 /* Initialize a variable CUM of type CUMULATIVE_ARGS
7555    for a call to a function whose data type is FNTYPE.
7556    For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
7557 
7558    For incoming args we set the number of arguments in the prototype large
7559    so we never return a PARALLEL.  */
7560 
7561 void
init_cumulative_args(CUMULATIVE_ARGS * cum,tree fntype,rtx libname ATTRIBUTE_UNUSED,int incoming,int libcall,int n_named_args,tree fndecl ATTRIBUTE_UNUSED,enum machine_mode return_mode ATTRIBUTE_UNUSED)7562 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
7563 		      rtx libname ATTRIBUTE_UNUSED, int incoming,
7564 		      int libcall, int n_named_args,
7565 		      tree fndecl ATTRIBUTE_UNUSED,
7566 		      enum machine_mode return_mode ATTRIBUTE_UNUSED)
7567 {
7568   static CUMULATIVE_ARGS zero_cumulative;
7569 
7570   *cum = zero_cumulative;
7571   cum->words = 0;
7572   cum->fregno = FP_ARG_MIN_REG;
7573   cum->vregno = ALTIVEC_ARG_MIN_REG;
7574   cum->prototype = (fntype && prototype_p (fntype));
7575   cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
7576 		      ? CALL_LIBCALL : CALL_NORMAL);
7577   cum->sysv_gregno = GP_ARG_MIN_REG;
7578   cum->stdarg = stdarg_p (fntype);
7579 
7580   cum->nargs_prototype = 0;
7581   if (incoming || cum->prototype)
7582     cum->nargs_prototype = n_named_args;
7583 
7584   /* Check for a longcall attribute.  */
7585   if ((!fntype && rs6000_default_long_calls)
7586       || (fntype
7587 	  && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
7588 	  && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
7589     cum->call_cookie |= CALL_LONG;
7590 
7591   if (TARGET_DEBUG_ARG)
7592     {
7593       fprintf (stderr, "\ninit_cumulative_args:");
7594       if (fntype)
7595 	{
7596 	  tree ret_type = TREE_TYPE (fntype);
7597 	  fprintf (stderr, " ret code = %s,",
7598 		   tree_code_name[ (int)TREE_CODE (ret_type) ]);
7599 	}
7600 
7601       if (cum->call_cookie & CALL_LONG)
7602 	fprintf (stderr, " longcall,");
7603 
7604       fprintf (stderr, " proto = %d, nargs = %d\n",
7605 	       cum->prototype, cum->nargs_prototype);
7606     }
7607 
7608 #ifdef HAVE_AS_GNU_ATTRIBUTE
7609   if (DEFAULT_ABI == ABI_V4)
7610     {
7611       cum->escapes = call_ABI_of_interest (fndecl);
7612       if (cum->escapes)
7613 	{
7614 	  tree return_type;
7615 
7616 	  if (fntype)
7617 	    {
7618 	      return_type = TREE_TYPE (fntype);
7619 	      return_mode = TYPE_MODE (return_type);
7620 	    }
7621 	  else
7622 	    return_type = lang_hooks.types.type_for_mode (return_mode, 0);
7623 
7624 	  if (return_type != NULL)
7625 	    {
7626 	      if (TREE_CODE (return_type) == RECORD_TYPE
7627 		  && TYPE_TRANSPARENT_AGGR (return_type))
7628 		{
7629 		  return_type = TREE_TYPE (first_field (return_type));
7630 		  return_mode = TYPE_MODE (return_type);
7631 		}
7632 	      if (AGGREGATE_TYPE_P (return_type)
7633 		  && ((unsigned HOST_WIDE_INT) int_size_in_bytes (return_type)
7634 		      <= 8))
7635 		rs6000_returns_struct = true;
7636 	    }
7637 	  if (SCALAR_FLOAT_MODE_P (return_mode))
7638 	    rs6000_passes_float = true;
7639 	  else if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode)
7640 		   || SPE_VECTOR_MODE (return_mode))
7641 	    rs6000_passes_vector = true;
7642 	}
7643     }
7644 #endif
7645 
7646   if (fntype
7647       && !TARGET_ALTIVEC
7648       && TARGET_ALTIVEC_ABI
7649       && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
7650     {
7651       error ("cannot return value in vector register because"
7652 	     " altivec instructions are disabled, use -maltivec"
7653 	     " to enable them");
7654     }
7655 }
7656 
7657 /* Return true if TYPE must be passed on the stack and not in registers.  */
7658 
7659 static bool
rs6000_must_pass_in_stack(enum machine_mode mode,const_tree type)7660 rs6000_must_pass_in_stack (enum machine_mode mode, const_tree type)
7661 {
7662   if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
7663     return must_pass_in_stack_var_size (mode, type);
7664   else
7665     return must_pass_in_stack_var_size_or_pad (mode, type);
7666 }
7667 
7668 /* If defined, a C expression which determines whether, and in which
7669    direction, to pad out an argument with extra space.  The value
7670    should be of type `enum direction': either `upward' to pad above
7671    the argument, `downward' to pad below, or `none' to inhibit
7672    padding.
7673 
7674    For the AIX ABI structs are always stored left shifted in their
7675    argument slot.  */
7676 
7677 enum direction
function_arg_padding(enum machine_mode mode,const_tree type)7678 function_arg_padding (enum machine_mode mode, const_tree type)
7679 {
7680 #ifndef AGGREGATE_PADDING_FIXED
7681 #define AGGREGATE_PADDING_FIXED 0
7682 #endif
7683 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
7684 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
7685 #endif
7686 
7687   if (!AGGREGATE_PADDING_FIXED)
7688     {
7689       /* GCC used to pass structures of the same size as integer types as
7690 	 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
7691 	 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
7692 	 passed padded downward, except that -mstrict-align further
7693 	 muddied the water in that multi-component structures of 2 and 4
7694 	 bytes in size were passed padded upward.
7695 
7696 	 The following arranges for best compatibility with previous
7697 	 versions of gcc, but removes the -mstrict-align dependency.  */
7698       if (BYTES_BIG_ENDIAN)
7699 	{
7700 	  HOST_WIDE_INT size = 0;
7701 
7702 	  if (mode == BLKmode)
7703 	    {
7704 	      if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
7705 		size = int_size_in_bytes (type);
7706 	    }
7707 	  else
7708 	    size = GET_MODE_SIZE (mode);
7709 
7710 	  if (size == 1 || size == 2 || size == 4)
7711 	    return downward;
7712 	}
7713       return upward;
7714     }
7715 
7716   if (AGGREGATES_PAD_UPWARD_ALWAYS)
7717     {
7718       if (type != 0 && AGGREGATE_TYPE_P (type))
7719 	return upward;
7720     }
7721 
7722   /* Fall back to the default.  */
7723   return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
7724 }
7725 
7726 /* If defined, a C expression that gives the alignment boundary, in bits,
7727    of an argument with the specified mode and type.  If it is not defined,
7728    PARM_BOUNDARY is used for all arguments.
7729 
7730    V.4 wants long longs and doubles to be double word aligned.  Just
7731    testing the mode size is a boneheaded way to do this as it means
7732    that other types such as complex int are also double word aligned.
7733    However, we're stuck with this because changing the ABI might break
7734    existing library interfaces.
7735 
7736    Doubleword align SPE vectors.
7737    Quadword align Altivec/VSX vectors.
7738    Quadword align large synthetic vector types.   */
7739 
7740 static unsigned int
rs6000_function_arg_boundary(enum machine_mode mode,const_tree type)7741 rs6000_function_arg_boundary (enum machine_mode mode, const_tree type)
7742 {
7743   if (DEFAULT_ABI == ABI_V4
7744       && (GET_MODE_SIZE (mode) == 8
7745 	  || (TARGET_HARD_FLOAT
7746 	      && TARGET_FPRS
7747 	      && (mode == TFmode || mode == TDmode))))
7748     return 64;
7749   else if (SPE_VECTOR_MODE (mode)
7750 	   || (type && TREE_CODE (type) == VECTOR_TYPE
7751 	       && int_size_in_bytes (type) >= 8
7752 	       && int_size_in_bytes (type) < 16))
7753     return 64;
7754   else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
7755 	   || (type && TREE_CODE (type) == VECTOR_TYPE
7756 	       && int_size_in_bytes (type) >= 16))
7757     return 128;
7758   else if (TARGET_MACHO
7759  	   && rs6000_darwin64_abi
7760  	   && mode == BLKmode
7761 	   && type && TYPE_ALIGN (type) > 64)
7762     return 128;
7763   else
7764     return PARM_BOUNDARY;
7765 }
7766 
7767 /* For a function parm of MODE and TYPE, return the starting word in
7768    the parameter area.  NWORDS of the parameter area are already used.  */
7769 
7770 static unsigned int
rs6000_parm_start(enum machine_mode mode,const_tree type,unsigned int nwords)7771 rs6000_parm_start (enum machine_mode mode, const_tree type,
7772 		   unsigned int nwords)
7773 {
7774   unsigned int align;
7775   unsigned int parm_offset;
7776 
7777   align = rs6000_function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
7778   parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
7779   return nwords + (-(parm_offset + nwords) & align);
7780 }
7781 
7782 /* Compute the size (in words) of a function argument.  */
7783 
7784 static unsigned long
rs6000_arg_size(enum machine_mode mode,const_tree type)7785 rs6000_arg_size (enum machine_mode mode, const_tree type)
7786 {
7787   unsigned long size;
7788 
7789   if (mode != BLKmode)
7790     size = GET_MODE_SIZE (mode);
7791   else
7792     size = int_size_in_bytes (type);
7793 
7794   if (TARGET_32BIT)
7795     return (size + 3) >> 2;
7796   else
7797     return (size + 7) >> 3;
7798 }
7799 
7800 /* Use this to flush pending int fields.  */
7801 
7802 static void
rs6000_darwin64_record_arg_advance_flush(CUMULATIVE_ARGS * cum,HOST_WIDE_INT bitpos,int final)7803 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
7804 					  HOST_WIDE_INT bitpos, int final)
7805 {
7806   unsigned int startbit, endbit;
7807   int intregs, intoffset;
7808   enum machine_mode mode;
7809 
7810   /* Handle the situations where a float is taking up the first half
7811      of the GPR, and the other half is empty (typically due to
7812      alignment restrictions). We can detect this by a 8-byte-aligned
7813      int field, or by seeing that this is the final flush for this
7814      argument. Count the word and continue on.  */
7815   if (cum->floats_in_gpr == 1
7816       && (cum->intoffset % 64 == 0
7817 	  || (cum->intoffset == -1 && final)))
7818     {
7819       cum->words++;
7820       cum->floats_in_gpr = 0;
7821     }
7822 
7823   if (cum->intoffset == -1)
7824     return;
7825 
7826   intoffset = cum->intoffset;
7827   cum->intoffset = -1;
7828   cum->floats_in_gpr = 0;
7829 
7830   if (intoffset % BITS_PER_WORD != 0)
7831     {
7832       mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
7833 			    MODE_INT, 0);
7834       if (mode == BLKmode)
7835 	{
7836 	  /* We couldn't find an appropriate mode, which happens,
7837 	     e.g., in packed structs when there are 3 bytes to load.
7838 	     Back intoffset back to the beginning of the word in this
7839 	     case.  */
7840 	  intoffset = intoffset & -BITS_PER_WORD;
7841 	}
7842     }
7843 
7844   startbit = intoffset & -BITS_PER_WORD;
7845   endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
7846   intregs = (endbit - startbit) / BITS_PER_WORD;
7847   cum->words += intregs;
7848   /* words should be unsigned. */
7849   if ((unsigned)cum->words < (endbit/BITS_PER_WORD))
7850     {
7851       int pad = (endbit/BITS_PER_WORD) - cum->words;
7852       cum->words += pad;
7853     }
7854 }
7855 
7856 /* The darwin64 ABI calls for us to recurse down through structs,
7857    looking for elements passed in registers.  Unfortunately, we have
7858    to track int register count here also because of misalignments
7859    in powerpc alignment mode.  */
7860 
7861 static void
rs6000_darwin64_record_arg_advance_recurse(CUMULATIVE_ARGS * cum,const_tree type,HOST_WIDE_INT startbitpos)7862 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
7863 					    const_tree type,
7864 					    HOST_WIDE_INT startbitpos)
7865 {
7866   tree f;
7867 
7868   for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
7869     if (TREE_CODE (f) == FIELD_DECL)
7870       {
7871 	HOST_WIDE_INT bitpos = startbitpos;
7872 	tree ftype = TREE_TYPE (f);
7873 	enum machine_mode mode;
7874 	if (ftype == error_mark_node)
7875 	  continue;
7876 	mode = TYPE_MODE (ftype);
7877 
7878 	if (DECL_SIZE (f) != 0
7879 	    && host_integerp (bit_position (f), 1))
7880 	  bitpos += int_bit_position (f);
7881 
7882 	/* ??? FIXME: else assume zero offset.  */
7883 
7884 	if (TREE_CODE (ftype) == RECORD_TYPE)
7885 	  rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
7886 	else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
7887 	  {
7888 	    unsigned n_fpregs = (GET_MODE_SIZE (mode) + 7) >> 3;
7889 	    rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
7890 	    cum->fregno += n_fpregs;
7891 	    /* Single-precision floats present a special problem for
7892 	       us, because they are smaller than an 8-byte GPR, and so
7893 	       the structure-packing rules combined with the standard
7894 	       varargs behavior mean that we want to pack float/float
7895 	       and float/int combinations into a single register's
7896 	       space. This is complicated by the arg advance flushing,
7897 	       which works on arbitrarily large groups of int-type
7898 	       fields.  */
7899 	    if (mode == SFmode)
7900 	      {
7901 		if (cum->floats_in_gpr == 1)
7902 		  {
7903 		    /* Two floats in a word; count the word and reset
7904 		       the float count.  */
7905 		    cum->words++;
7906 		    cum->floats_in_gpr = 0;
7907 		  }
7908 		else if (bitpos % 64 == 0)
7909 		  {
7910 		    /* A float at the beginning of an 8-byte word;
7911 		       count it and put off adjusting cum->words until
7912 		       we see if a arg advance flush is going to do it
7913 		       for us.  */
7914 		    cum->floats_in_gpr++;
7915 		  }
7916 		else
7917 		  {
7918 		    /* The float is at the end of a word, preceded
7919 		       by integer fields, so the arg advance flush
7920 		       just above has already set cum->words and
7921 		       everything is taken care of.  */
7922 		  }
7923 	      }
7924 	    else
7925 	      cum->words += n_fpregs;
7926 	  }
7927 	else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
7928 	  {
7929 	    rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
7930 	    cum->vregno++;
7931 	    cum->words += 2;
7932 	  }
7933 	else if (cum->intoffset == -1)
7934 	  cum->intoffset = bitpos;
7935       }
7936 }
7937 
7938 /* Check for an item that needs to be considered specially under the darwin 64
7939    bit ABI.  These are record types where the mode is BLK or the structure is
7940    8 bytes in size.  */
7941 static int
rs6000_darwin64_struct_check_p(enum machine_mode mode,const_tree type)7942 rs6000_darwin64_struct_check_p (enum machine_mode mode, const_tree type)
7943 {
7944   return rs6000_darwin64_abi
7945 	 && ((mode == BLKmode
7946 	      && TREE_CODE (type) == RECORD_TYPE
7947 	      && int_size_in_bytes (type) > 0)
7948 	  || (type && TREE_CODE (type) == RECORD_TYPE
7949 	      && int_size_in_bytes (type) == 8)) ? 1 : 0;
7950 }
7951 
7952 /* Update the data in CUM to advance over an argument
7953    of mode MODE and data type TYPE.
7954    (TYPE is null for libcalls where that information may not be available.)
7955 
7956    Note that for args passed by reference, function_arg will be called
7957    with MODE and TYPE set to that of the pointer to the arg, not the arg
7958    itself.  */
7959 
7960 static void
rs6000_function_arg_advance_1(CUMULATIVE_ARGS * cum,enum machine_mode mode,const_tree type,bool named,int depth)7961 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7962 			       const_tree type, bool named, int depth)
7963 {
7964   /* Only tick off an argument if we're not recursing.  */
7965   if (depth == 0)
7966     cum->nargs_prototype--;
7967 
7968 #ifdef HAVE_AS_GNU_ATTRIBUTE
7969   if (DEFAULT_ABI == ABI_V4
7970       && cum->escapes)
7971     {
7972       if (SCALAR_FLOAT_MODE_P (mode))
7973 	rs6000_passes_float = true;
7974       else if (named && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
7975 	rs6000_passes_vector = true;
7976       else if (SPE_VECTOR_MODE (mode)
7977 	       && !cum->stdarg
7978 	       && cum->sysv_gregno <= GP_ARG_MAX_REG)
7979 	rs6000_passes_vector = true;
7980     }
7981 #endif
7982 
7983   if (TARGET_ALTIVEC_ABI
7984       && (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
7985 	  || (type && TREE_CODE (type) == VECTOR_TYPE
7986 	      && int_size_in_bytes (type) == 16)))
7987     {
7988       bool stack = false;
7989 
7990       if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
7991 	{
7992 	  cum->vregno++;
7993 	  if (!TARGET_ALTIVEC)
7994 	    error ("cannot pass argument in vector register because"
7995 		   " altivec instructions are disabled, use -maltivec"
7996 		   " to enable them");
7997 
7998 	  /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
7999 	     even if it is going to be passed in a vector register.
8000 	     Darwin does the same for variable-argument functions.  */
8001 	  if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
8002 	      || (cum->stdarg && DEFAULT_ABI != ABI_V4))
8003 	    stack = true;
8004 	}
8005       else
8006 	stack = true;
8007 
8008       if (stack)
8009 	{
8010 	  int align;
8011 
8012 	  /* Vector parameters must be 16-byte aligned.  This places
8013 	     them at 2 mod 4 in terms of words in 32-bit mode, since
8014 	     the parameter save area starts at offset 24 from the
8015 	     stack.  In 64-bit mode, they just have to start on an
8016 	     even word, since the parameter save area is 16-byte
8017 	     aligned.  Space for GPRs is reserved even if the argument
8018 	     will be passed in memory.  */
8019 	  if (TARGET_32BIT)
8020 	    align = (2 - cum->words) & 3;
8021 	  else
8022 	    align = cum->words & 1;
8023 	  cum->words += align + rs6000_arg_size (mode, type);
8024 
8025 	  if (TARGET_DEBUG_ARG)
8026 	    {
8027 	      fprintf (stderr, "function_adv: words = %2d, align=%d, ",
8028 		       cum->words, align);
8029 	      fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
8030 		       cum->nargs_prototype, cum->prototype,
8031 		       GET_MODE_NAME (mode));
8032 	    }
8033 	}
8034     }
8035   else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
8036 	   && !cum->stdarg
8037 	   && cum->sysv_gregno <= GP_ARG_MAX_REG)
8038     cum->sysv_gregno++;
8039 
8040   else if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
8041     {
8042       int size = int_size_in_bytes (type);
8043       /* Variable sized types have size == -1 and are
8044 	 treated as if consisting entirely of ints.
8045 	 Pad to 16 byte boundary if needed.  */
8046       if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
8047 	  && (cum->words % 2) != 0)
8048 	cum->words++;
8049       /* For varargs, we can just go up by the size of the struct. */
8050       if (!named)
8051 	cum->words += (size + 7) / 8;
8052       else
8053 	{
8054 	  /* It is tempting to say int register count just goes up by
8055 	     sizeof(type)/8, but this is wrong in a case such as
8056 	     { int; double; int; } [powerpc alignment].  We have to
8057 	     grovel through the fields for these too.  */
8058 	  cum->intoffset = 0;
8059 	  cum->floats_in_gpr = 0;
8060 	  rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
8061 	  rs6000_darwin64_record_arg_advance_flush (cum,
8062 						    size * BITS_PER_UNIT, 1);
8063 	}
8064 	  if (TARGET_DEBUG_ARG)
8065 	    {
8066 	      fprintf (stderr, "function_adv: words = %2d, align=%d, size=%d",
8067 		       cum->words, TYPE_ALIGN (type), size);
8068 	      fprintf (stderr,
8069 	           "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
8070 		       cum->nargs_prototype, cum->prototype,
8071 		       GET_MODE_NAME (mode));
8072 	    }
8073     }
8074   else if (DEFAULT_ABI == ABI_V4)
8075     {
8076       if (TARGET_HARD_FLOAT && TARGET_FPRS
8077 	  && ((TARGET_SINGLE_FLOAT && mode == SFmode)
8078 	      || (TARGET_DOUBLE_FLOAT && mode == DFmode)
8079 	      || (mode == TFmode && !TARGET_IEEEQUAD)
8080 	      || mode == SDmode || mode == DDmode || mode == TDmode))
8081 	{
8082 	  /* _Decimal128 must use an even/odd register pair.  This assumes
8083 	     that the register number is odd when fregno is odd.  */
8084 	  if (mode == TDmode && (cum->fregno % 2) == 1)
8085 	    cum->fregno++;
8086 
8087 	  if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
8088 	      <= FP_ARG_V4_MAX_REG)
8089 	    cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
8090 	  else
8091 	    {
8092 	      cum->fregno = FP_ARG_V4_MAX_REG + 1;
8093 	      if (mode == DFmode || mode == TFmode
8094 		  || mode == DDmode || mode == TDmode)
8095 		cum->words += cum->words & 1;
8096 	      cum->words += rs6000_arg_size (mode, type);
8097 	    }
8098 	}
8099       else
8100 	{
8101 	  int n_words = rs6000_arg_size (mode, type);
8102 	  int gregno = cum->sysv_gregno;
8103 
8104 	  /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
8105 	     (r7,r8) or (r9,r10).  As does any other 2 word item such
8106 	     as complex int due to a historical mistake.  */
8107 	  if (n_words == 2)
8108 	    gregno += (1 - gregno) & 1;
8109 
8110 	  /* Multi-reg args are not split between registers and stack.  */
8111 	  if (gregno + n_words - 1 > GP_ARG_MAX_REG)
8112 	    {
8113 	      /* Long long and SPE vectors are aligned on the stack.
8114 		 So are other 2 word items such as complex int due to
8115 		 a historical mistake.  */
8116 	      if (n_words == 2)
8117 		cum->words += cum->words & 1;
8118 	      cum->words += n_words;
8119 	    }
8120 
8121 	  /* Note: continuing to accumulate gregno past when we've started
8122 	     spilling to the stack indicates the fact that we've started
8123 	     spilling to the stack to expand_builtin_saveregs.  */
8124 	  cum->sysv_gregno = gregno + n_words;
8125 	}
8126 
8127       if (TARGET_DEBUG_ARG)
8128 	{
8129 	  fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
8130 		   cum->words, cum->fregno);
8131 	  fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
8132 		   cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
8133 	  fprintf (stderr, "mode = %4s, named = %d\n",
8134 		   GET_MODE_NAME (mode), named);
8135 	}
8136     }
8137   else
8138     {
8139       int n_words = rs6000_arg_size (mode, type);
8140       int start_words = cum->words;
8141       int align_words = rs6000_parm_start (mode, type, start_words);
8142 
8143       cum->words = align_words + n_words;
8144 
8145       if (SCALAR_FLOAT_MODE_P (mode)
8146 	  && TARGET_HARD_FLOAT && TARGET_FPRS)
8147 	{
8148 	  /* _Decimal128 must be passed in an even/odd float register pair.
8149 	     This assumes that the register number is odd when fregno is
8150 	     odd.  */
8151 	  if (mode == TDmode && (cum->fregno % 2) == 1)
8152 	    cum->fregno++;
8153 	  cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
8154 	}
8155 
8156       if (TARGET_DEBUG_ARG)
8157 	{
8158 	  fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
8159 		   cum->words, cum->fregno);
8160 	  fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
8161 		   cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
8162 	  fprintf (stderr, "named = %d, align = %d, depth = %d\n",
8163 		   named, align_words - start_words, depth);
8164 	}
8165     }
8166 }
8167 
8168 static void
rs6000_function_arg_advance(cumulative_args_t cum,enum machine_mode mode,const_tree type,bool named)8169 rs6000_function_arg_advance (cumulative_args_t cum, enum machine_mode mode,
8170 			     const_tree type, bool named)
8171 {
8172   rs6000_function_arg_advance_1 (get_cumulative_args (cum), mode, type, named,
8173 				 0);
8174 }
8175 
8176 static rtx
spe_build_register_parallel(enum machine_mode mode,int gregno)8177 spe_build_register_parallel (enum machine_mode mode, int gregno)
8178 {
8179   rtx r1, r3, r5, r7;
8180 
8181   switch (mode)
8182     {
8183     case DFmode:
8184       r1 = gen_rtx_REG (DImode, gregno);
8185       r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
8186       return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
8187 
8188     case DCmode:
8189     case TFmode:
8190       r1 = gen_rtx_REG (DImode, gregno);
8191       r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
8192       r3 = gen_rtx_REG (DImode, gregno + 2);
8193       r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
8194       return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
8195 
8196     case TCmode:
8197       r1 = gen_rtx_REG (DImode, gregno);
8198       r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
8199       r3 = gen_rtx_REG (DImode, gregno + 2);
8200       r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
8201       r5 = gen_rtx_REG (DImode, gregno + 4);
8202       r5 = gen_rtx_EXPR_LIST (VOIDmode, r5, GEN_INT (16));
8203       r7 = gen_rtx_REG (DImode, gregno + 6);
8204       r7 = gen_rtx_EXPR_LIST (VOIDmode, r7, GEN_INT (24));
8205       return gen_rtx_PARALLEL (mode, gen_rtvec (4, r1, r3, r5, r7));
8206 
8207     default:
8208       gcc_unreachable ();
8209     }
8210 }
8211 
8212 /* Determine where to put a SIMD argument on the SPE.  */
8213 static rtx
rs6000_spe_function_arg(const CUMULATIVE_ARGS * cum,enum machine_mode mode,const_tree type)8214 rs6000_spe_function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
8215 			 const_tree type)
8216 {
8217   int gregno = cum->sysv_gregno;
8218 
8219   /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
8220      are passed and returned in a pair of GPRs for ABI compatibility.  */
8221   if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
8222 			     || mode == DCmode || mode == TCmode))
8223     {
8224       int n_words = rs6000_arg_size (mode, type);
8225 
8226       /* Doubles go in an odd/even register pair (r5/r6, etc).  */
8227       if (mode == DFmode)
8228 	gregno += (1 - gregno) & 1;
8229 
8230       /* Multi-reg args are not split between registers and stack.  */
8231       if (gregno + n_words - 1 > GP_ARG_MAX_REG)
8232 	return NULL_RTX;
8233 
8234       return spe_build_register_parallel (mode, gregno);
8235     }
8236   if (cum->stdarg)
8237     {
8238       int n_words = rs6000_arg_size (mode, type);
8239 
8240       /* SPE vectors are put in odd registers.  */
8241       if (n_words == 2 && (gregno & 1) == 0)
8242 	gregno += 1;
8243 
8244       if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
8245 	{
8246 	  rtx r1, r2;
8247 	  enum machine_mode m = SImode;
8248 
8249 	  r1 = gen_rtx_REG (m, gregno);
8250 	  r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
8251 	  r2 = gen_rtx_REG (m, gregno + 1);
8252 	  r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
8253 	  return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
8254 	}
8255       else
8256 	return NULL_RTX;
8257     }
8258   else
8259     {
8260       if (gregno <= GP_ARG_MAX_REG)
8261 	return gen_rtx_REG (mode, gregno);
8262       else
8263 	return NULL_RTX;
8264     }
8265 }
8266 
8267 /* A subroutine of rs6000_darwin64_record_arg.  Assign the bits of the
8268    structure between cum->intoffset and bitpos to integer registers.  */
8269 
8270 static void
rs6000_darwin64_record_arg_flush(CUMULATIVE_ARGS * cum,HOST_WIDE_INT bitpos,rtx rvec[],int * k)8271 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
8272 				  HOST_WIDE_INT bitpos, rtx rvec[], int *k)
8273 {
8274   enum machine_mode mode;
8275   unsigned int regno;
8276   unsigned int startbit, endbit;
8277   int this_regno, intregs, intoffset;
8278   rtx reg;
8279 
8280   if (cum->intoffset == -1)
8281     return;
8282 
8283   intoffset = cum->intoffset;
8284   cum->intoffset = -1;
8285 
8286   /* If this is the trailing part of a word, try to only load that
8287      much into the register.  Otherwise load the whole register.  Note
8288      that in the latter case we may pick up unwanted bits.  It's not a
8289      problem at the moment but may wish to revisit.  */
8290 
8291   if (intoffset % BITS_PER_WORD != 0)
8292     {
8293       mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
8294 			  MODE_INT, 0);
8295       if (mode == BLKmode)
8296 	{
8297 	  /* We couldn't find an appropriate mode, which happens,
8298 	     e.g., in packed structs when there are 3 bytes to load.
8299 	     Back intoffset back to the beginning of the word in this
8300 	     case.  */
8301 	 intoffset = intoffset & -BITS_PER_WORD;
8302 	 mode = word_mode;
8303 	}
8304     }
8305   else
8306     mode = word_mode;
8307 
8308   startbit = intoffset & -BITS_PER_WORD;
8309   endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
8310   intregs = (endbit - startbit) / BITS_PER_WORD;
8311   this_regno = cum->words + intoffset / BITS_PER_WORD;
8312 
8313   if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
8314     cum->use_stack = 1;
8315 
8316   intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
8317   if (intregs <= 0)
8318     return;
8319 
8320   intoffset /= BITS_PER_UNIT;
8321   do
8322     {
8323       regno = GP_ARG_MIN_REG + this_regno;
8324       reg = gen_rtx_REG (mode, regno);
8325       rvec[(*k)++] =
8326 	gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
8327 
8328       this_regno += 1;
8329       intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
8330       mode = word_mode;
8331       intregs -= 1;
8332     }
8333   while (intregs > 0);
8334 }
8335 
8336 /* Recursive workhorse for the following.  */
8337 
8338 static void
rs6000_darwin64_record_arg_recurse(CUMULATIVE_ARGS * cum,const_tree type,HOST_WIDE_INT startbitpos,rtx rvec[],int * k)8339 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, const_tree type,
8340 				    HOST_WIDE_INT startbitpos, rtx rvec[],
8341 				    int *k)
8342 {
8343   tree f;
8344 
8345   for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
8346     if (TREE_CODE (f) == FIELD_DECL)
8347       {
8348 	HOST_WIDE_INT bitpos = startbitpos;
8349 	tree ftype = TREE_TYPE (f);
8350 	enum machine_mode mode;
8351 	if (ftype == error_mark_node)
8352 	  continue;
8353 	mode = TYPE_MODE (ftype);
8354 
8355 	if (DECL_SIZE (f) != 0
8356 	    && host_integerp (bit_position (f), 1))
8357 	  bitpos += int_bit_position (f);
8358 
8359 	/* ??? FIXME: else assume zero offset.  */
8360 
8361 	if (TREE_CODE (ftype) == RECORD_TYPE)
8362 	  rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
8363 	else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
8364 	  {
8365 	    unsigned n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
8366 #if 0
8367 	    switch (mode)
8368 	      {
8369 	      case SCmode: mode = SFmode; break;
8370 	      case DCmode: mode = DFmode; break;
8371 	      case TCmode: mode = TFmode; break;
8372 	      default: break;
8373 	      }
8374 #endif
8375 	    rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
8376 	    if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
8377 	      {
8378 		gcc_assert (cum->fregno == FP_ARG_MAX_REG
8379 			    && (mode == TFmode || mode == TDmode));
8380 		/* Long double or _Decimal128 split over regs and memory.  */
8381 		mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode;
8382 		cum->use_stack=1;
8383 	      }
8384 	    rvec[(*k)++]
8385 	      = gen_rtx_EXPR_LIST (VOIDmode,
8386 				   gen_rtx_REG (mode, cum->fregno++),
8387 				   GEN_INT (bitpos / BITS_PER_UNIT));
8388 	    if (mode == TFmode || mode == TDmode)
8389 	      cum->fregno++;
8390 	  }
8391 	else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
8392 	  {
8393 	    rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
8394 	    rvec[(*k)++]
8395 	      = gen_rtx_EXPR_LIST (VOIDmode,
8396 				   gen_rtx_REG (mode, cum->vregno++),
8397 				   GEN_INT (bitpos / BITS_PER_UNIT));
8398 	  }
8399 	else if (cum->intoffset == -1)
8400 	  cum->intoffset = bitpos;
8401       }
8402 }
8403 
8404 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
8405    the register(s) to be used for each field and subfield of a struct
8406    being passed by value, along with the offset of where the
8407    register's value may be found in the block.  FP fields go in FP
8408    register, vector fields go in vector registers, and everything
8409    else goes in int registers, packed as in memory.
8410 
8411    This code is also used for function return values.  RETVAL indicates
8412    whether this is the case.
8413 
8414    Much of this is taken from the SPARC V9 port, which has a similar
8415    calling convention.  */
8416 
8417 static rtx
rs6000_darwin64_record_arg(CUMULATIVE_ARGS * orig_cum,const_tree type,bool named,bool retval)8418 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, const_tree type,
8419 			    bool named, bool retval)
8420 {
8421   rtx rvec[FIRST_PSEUDO_REGISTER];
8422   int k = 1, kbase = 1;
8423   HOST_WIDE_INT typesize = int_size_in_bytes (type);
8424   /* This is a copy; modifications are not visible to our caller.  */
8425   CUMULATIVE_ARGS copy_cum = *orig_cum;
8426   CUMULATIVE_ARGS *cum = &copy_cum;
8427 
8428   /* Pad to 16 byte boundary if needed.  */
8429   if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
8430       && (cum->words % 2) != 0)
8431     cum->words++;
8432 
8433   cum->intoffset = 0;
8434   cum->use_stack = 0;
8435   cum->named = named;
8436 
8437   /* Put entries into rvec[] for individual FP and vector fields, and
8438      for the chunks of memory that go in int regs.  Note we start at
8439      element 1; 0 is reserved for an indication of using memory, and
8440      may or may not be filled in below. */
8441   rs6000_darwin64_record_arg_recurse (cum, type, /* startbit pos= */ 0, rvec, &k);
8442   rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
8443 
8444   /* If any part of the struct went on the stack put all of it there.
8445      This hack is because the generic code for
8446      FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
8447      parts of the struct are not at the beginning.  */
8448   if (cum->use_stack)
8449     {
8450       if (retval)
8451 	return NULL_RTX;    /* doesn't go in registers at all */
8452       kbase = 0;
8453       rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
8454     }
8455   if (k > 1 || cum->use_stack)
8456     return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
8457   else
8458     return NULL_RTX;
8459 }
8460 
8461 /* Determine where to place an argument in 64-bit mode with 32-bit ABI.  */
8462 
8463 static rtx
rs6000_mixed_function_arg(enum machine_mode mode,const_tree type,int align_words)8464 rs6000_mixed_function_arg (enum machine_mode mode, const_tree type,
8465 			   int align_words)
8466 {
8467   int n_units;
8468   int i, k;
8469   rtx rvec[GP_ARG_NUM_REG + 1];
8470 
8471   if (align_words >= GP_ARG_NUM_REG)
8472     return NULL_RTX;
8473 
8474   n_units = rs6000_arg_size (mode, type);
8475 
8476   /* Optimize the simple case where the arg fits in one gpr, except in
8477      the case of BLKmode due to assign_parms assuming that registers are
8478      BITS_PER_WORD wide.  */
8479   if (n_units == 0
8480       || (n_units == 1 && mode != BLKmode))
8481     return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
8482 
8483   k = 0;
8484   if (align_words + n_units > GP_ARG_NUM_REG)
8485     /* Not all of the arg fits in gprs.  Say that it goes in memory too,
8486        using a magic NULL_RTX component.
8487        This is not strictly correct.  Only some of the arg belongs in
8488        memory, not all of it.  However, the normal scheme using
8489        function_arg_partial_nregs can result in unusual subregs, eg.
8490        (subreg:SI (reg:DF) 4), which are not handled well.  The code to
8491        store the whole arg to memory is often more efficient than code
8492        to store pieces, and we know that space is available in the right
8493        place for the whole arg.  */
8494     rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
8495 
8496   i = 0;
8497   do
8498     {
8499       rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
8500       rtx off = GEN_INT (i++ * 4);
8501       rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
8502     }
8503   while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
8504 
8505   return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
8506 }
8507 
8508 /* Determine where to put an argument to a function.
8509    Value is zero to push the argument on the stack,
8510    or a hard register in which to store the argument.
8511 
8512    MODE is the argument's machine mode.
8513    TYPE is the data type of the argument (as a tree).
8514     This is null for libcalls where that information may
8515     not be available.
8516    CUM is a variable of type CUMULATIVE_ARGS which gives info about
8517     the preceding args and about the function being called.  It is
8518     not modified in this routine.
8519    NAMED is nonzero if this argument is a named parameter
8520     (otherwise it is an extra parameter matching an ellipsis).
8521 
8522    On RS/6000 the first eight words of non-FP are normally in registers
8523    and the rest are pushed.  Under AIX, the first 13 FP args are in registers.
8524    Under V.4, the first 8 FP args are in registers.
8525 
8526    If this is floating-point and no prototype is specified, we use
8527    both an FP and integer register (or possibly FP reg and stack).  Library
8528    functions (when CALL_LIBCALL is set) always have the proper types for args,
8529    so we can pass the FP value just in one register.  emit_library_function
8530    doesn't support PARALLEL anyway.
8531 
8532    Note that for args passed by reference, function_arg will be called
8533    with MODE and TYPE set to that of the pointer to the arg, not the arg
8534    itself.  */
8535 
8536 static rtx
rs6000_function_arg(cumulative_args_t cum_v,enum machine_mode mode,const_tree type,bool named)8537 rs6000_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
8538 		     const_tree type, bool named)
8539 {
8540   CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
8541   enum rs6000_abi abi = DEFAULT_ABI;
8542 
8543   /* Return a marker to indicate whether CR1 needs to set or clear the
8544      bit that V.4 uses to say fp args were passed in registers.
8545      Assume that we don't need the marker for software floating point,
8546      or compiler generated library calls.  */
8547   if (mode == VOIDmode)
8548     {
8549       if (abi == ABI_V4
8550 	  && (cum->call_cookie & CALL_LIBCALL) == 0
8551 	  && (cum->stdarg
8552 	      || (cum->nargs_prototype < 0
8553 		  && (cum->prototype || TARGET_NO_PROTOTYPE))))
8554 	{
8555 	  /* For the SPE, we need to crxor CR6 always.  */
8556 	  if (TARGET_SPE_ABI)
8557 	    return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
8558 	  else if (TARGET_HARD_FLOAT && TARGET_FPRS)
8559 	    return GEN_INT (cum->call_cookie
8560 			    | ((cum->fregno == FP_ARG_MIN_REG)
8561 			       ? CALL_V4_SET_FP_ARGS
8562 			       : CALL_V4_CLEAR_FP_ARGS));
8563 	}
8564 
8565       return GEN_INT (cum->call_cookie & ~CALL_LIBCALL);
8566     }
8567 
8568   if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
8569     {
8570       rtx rslt = rs6000_darwin64_record_arg (cum, type, named, /*retval= */false);
8571       if (rslt != NULL_RTX)
8572 	return rslt;
8573       /* Else fall through to usual handling.  */
8574     }
8575 
8576   if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
8577     if (TARGET_64BIT && ! cum->prototype)
8578       {
8579 	/* Vector parameters get passed in vector register
8580 	   and also in GPRs or memory, in absence of prototype.  */
8581 	int align_words;
8582 	rtx slot;
8583 	align_words = (cum->words + 1) & ~1;
8584 
8585 	if (align_words >= GP_ARG_NUM_REG)
8586 	  {
8587 	    slot = NULL_RTX;
8588 	  }
8589 	else
8590 	  {
8591 	    slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
8592 	  }
8593 	return gen_rtx_PARALLEL (mode,
8594 		 gen_rtvec (2,
8595 			    gen_rtx_EXPR_LIST (VOIDmode,
8596 					       slot, const0_rtx),
8597 			    gen_rtx_EXPR_LIST (VOIDmode,
8598 					       gen_rtx_REG (mode, cum->vregno),
8599 					       const0_rtx)));
8600       }
8601     else
8602       return gen_rtx_REG (mode, cum->vregno);
8603   else if (TARGET_ALTIVEC_ABI
8604 	   && (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
8605 	       || (type && TREE_CODE (type) == VECTOR_TYPE
8606 		   && int_size_in_bytes (type) == 16)))
8607     {
8608       if (named || abi == ABI_V4)
8609 	return NULL_RTX;
8610       else
8611 	{
8612 	  /* Vector parameters to varargs functions under AIX or Darwin
8613 	     get passed in memory and possibly also in GPRs.  */
8614 	  int align, align_words, n_words;
8615 	  enum machine_mode part_mode;
8616 
8617 	  /* Vector parameters must be 16-byte aligned.  This places them at
8618 	     2 mod 4 in terms of words in 32-bit mode, since the parameter
8619 	     save area starts at offset 24 from the stack.  In 64-bit mode,
8620 	     they just have to start on an even word, since the parameter
8621 	     save area is 16-byte aligned.  */
8622 	  if (TARGET_32BIT)
8623 	    align = (2 - cum->words) & 3;
8624 	  else
8625 	    align = cum->words & 1;
8626 	  align_words = cum->words + align;
8627 
8628 	  /* Out of registers?  Memory, then.  */
8629 	  if (align_words >= GP_ARG_NUM_REG)
8630 	    return NULL_RTX;
8631 
8632 	  if (TARGET_32BIT && TARGET_POWERPC64)
8633 	    return rs6000_mixed_function_arg (mode, type, align_words);
8634 
8635 	  /* The vector value goes in GPRs.  Only the part of the
8636 	     value in GPRs is reported here.  */
8637 	  part_mode = mode;
8638 	  n_words = rs6000_arg_size (mode, type);
8639 	  if (align_words + n_words > GP_ARG_NUM_REG)
8640 	    /* Fortunately, there are only two possibilities, the value
8641 	       is either wholly in GPRs or half in GPRs and half not.  */
8642 	    part_mode = DImode;
8643 
8644 	  return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
8645 	}
8646     }
8647   else if (TARGET_SPE_ABI && TARGET_SPE
8648 	   && (SPE_VECTOR_MODE (mode)
8649 	       || (TARGET_E500_DOUBLE && (mode == DFmode
8650 					  || mode == DCmode
8651 					  || mode == TFmode
8652 					  || mode == TCmode))))
8653     return rs6000_spe_function_arg (cum, mode, type);
8654 
8655   else if (abi == ABI_V4)
8656     {
8657       if (TARGET_HARD_FLOAT && TARGET_FPRS
8658 	  && ((TARGET_SINGLE_FLOAT && mode == SFmode)
8659 	      || (TARGET_DOUBLE_FLOAT && mode == DFmode)
8660 	      || (mode == TFmode && !TARGET_IEEEQUAD)
8661 	      || mode == SDmode || mode == DDmode || mode == TDmode))
8662 	{
8663 	  /* _Decimal128 must use an even/odd register pair.  This assumes
8664 	     that the register number is odd when fregno is odd.  */
8665 	  if (mode == TDmode && (cum->fregno % 2) == 1)
8666 	    cum->fregno++;
8667 
8668 	  if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
8669 	      <= FP_ARG_V4_MAX_REG)
8670 	    return gen_rtx_REG (mode, cum->fregno);
8671 	  else
8672 	    return NULL_RTX;
8673 	}
8674       else
8675 	{
8676 	  int n_words = rs6000_arg_size (mode, type);
8677 	  int gregno = cum->sysv_gregno;
8678 
8679 	  /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
8680 	     (r7,r8) or (r9,r10).  As does any other 2 word item such
8681 	     as complex int due to a historical mistake.  */
8682 	  if (n_words == 2)
8683 	    gregno += (1 - gregno) & 1;
8684 
8685 	  /* Multi-reg args are not split between registers and stack.  */
8686 	  if (gregno + n_words - 1 > GP_ARG_MAX_REG)
8687 	    return NULL_RTX;
8688 
8689 	  if (TARGET_32BIT && TARGET_POWERPC64)
8690 	    return rs6000_mixed_function_arg (mode, type,
8691 					      gregno - GP_ARG_MIN_REG);
8692 	  return gen_rtx_REG (mode, gregno);
8693 	}
8694     }
8695   else
8696     {
8697       int align_words = rs6000_parm_start (mode, type, cum->words);
8698 
8699       /* _Decimal128 must be passed in an even/odd float register pair.
8700 	 This assumes that the register number is odd when fregno is odd.  */
8701       if (mode == TDmode && (cum->fregno % 2) == 1)
8702 	cum->fregno++;
8703 
8704       if (USE_FP_FOR_ARG_P (cum, mode, type))
8705 	{
8706 	  rtx rvec[GP_ARG_NUM_REG + 1];
8707 	  rtx r;
8708 	  int k;
8709 	  bool needs_psave;
8710 	  enum machine_mode fmode = mode;
8711 	  unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
8712 
8713 	  if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
8714 	    {
8715 	      /* Currently, we only ever need one reg here because complex
8716 		 doubles are split.  */
8717 	      gcc_assert (cum->fregno == FP_ARG_MAX_REG
8718 			  && (fmode == TFmode || fmode == TDmode));
8719 
8720 	      /* Long double or _Decimal128 split over regs and memory.  */
8721 	      fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;
8722 	    }
8723 
8724 	  /* Do we also need to pass this arg in the parameter save
8725 	     area?  */
8726 	  needs_psave = (type
8727 			 && (cum->nargs_prototype <= 0
8728 			     || (DEFAULT_ABI == ABI_AIX
8729 				 && TARGET_XL_COMPAT
8730 				 && align_words >= GP_ARG_NUM_REG)));
8731 
8732 	  if (!needs_psave && mode == fmode)
8733 	    return gen_rtx_REG (fmode, cum->fregno);
8734 
8735 	  k = 0;
8736 	  if (needs_psave)
8737 	    {
8738 	      /* Describe the part that goes in gprs or the stack.
8739 		 This piece must come first, before the fprs.  */
8740 	      if (align_words < GP_ARG_NUM_REG)
8741 		{
8742 		  unsigned long n_words = rs6000_arg_size (mode, type);
8743 
8744 		  if (align_words + n_words > GP_ARG_NUM_REG
8745 		      || (TARGET_32BIT && TARGET_POWERPC64))
8746 		    {
8747 		      /* If this is partially on the stack, then we only
8748 			 include the portion actually in registers here.  */
8749 		      enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
8750 		      rtx off;
8751 		      int i = 0;
8752 		      if (align_words + n_words > GP_ARG_NUM_REG)
8753 			/* Not all of the arg fits in gprs.  Say that it
8754 			   goes in memory too, using a magic NULL_RTX
8755 			   component.  Also see comment in
8756 			   rs6000_mixed_function_arg for why the normal
8757 			   function_arg_partial_nregs scheme doesn't work
8758 			   in this case. */
8759 			rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
8760 						       const0_rtx);
8761 		      do
8762 			{
8763 			  r = gen_rtx_REG (rmode,
8764 					   GP_ARG_MIN_REG + align_words);
8765 			  off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
8766 			  rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
8767 			}
8768 		      while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
8769 		    }
8770 		  else
8771 		    {
8772 		      /* The whole arg fits in gprs.  */
8773 		      r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
8774 		      rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
8775 		    }
8776 		}
8777 	      else
8778 		/* It's entirely in memory.  */
8779 		rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
8780 	    }
8781 
8782 	  /* Describe where this piece goes in the fprs.  */
8783 	  r = gen_rtx_REG (fmode, cum->fregno);
8784 	  rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
8785 
8786 	  return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
8787 	}
8788       else if (align_words < GP_ARG_NUM_REG)
8789 	{
8790 	  if (TARGET_32BIT && TARGET_POWERPC64)
8791 	    return rs6000_mixed_function_arg (mode, type, align_words);
8792 
8793 	  if (mode == BLKmode)
8794 	    mode = Pmode;
8795 
8796 	  return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
8797 	}
8798       else
8799 	return NULL_RTX;
8800     }
8801 }
8802 
8803 /* For an arg passed partly in registers and partly in memory, this is
8804    the number of bytes passed in registers.  For args passed entirely in
8805    registers or entirely in memory, zero.  When an arg is described by a
8806    PARALLEL, perhaps using more than one register type, this function
8807    returns the number of bytes used by the first element of the PARALLEL.  */
8808 
8809 static int
rs6000_arg_partial_bytes(cumulative_args_t cum_v,enum machine_mode mode,tree type,bool named)8810 rs6000_arg_partial_bytes (cumulative_args_t cum_v, enum machine_mode mode,
8811 			  tree type, bool named)
8812 {
8813   CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
8814   int ret = 0;
8815   int align_words;
8816 
8817   if (DEFAULT_ABI == ABI_V4)
8818     return 0;
8819 
8820   if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
8821       && cum->nargs_prototype >= 0)
8822     return 0;
8823 
8824   /* In this complicated case we just disable the partial_nregs code.  */
8825   if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
8826     return 0;
8827 
8828   align_words = rs6000_parm_start (mode, type, cum->words);
8829 
8830   if (USE_FP_FOR_ARG_P (cum, mode, type))
8831     {
8832       /* If we are passing this arg in the fixed parameter save area
8833 	 (gprs or memory) as well as fprs, then this function should
8834 	 return the number of partial bytes passed in the parameter
8835 	 save area rather than partial bytes passed in fprs.  */
8836       if (type
8837 	  && (cum->nargs_prototype <= 0
8838 	      || (DEFAULT_ABI == ABI_AIX
8839 		  && TARGET_XL_COMPAT
8840 		  && align_words >= GP_ARG_NUM_REG)))
8841 	return 0;
8842       else if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3)
8843 	       > FP_ARG_MAX_REG + 1)
8844 	ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;
8845       else if (cum->nargs_prototype >= 0)
8846 	return 0;
8847     }
8848 
8849   if (align_words < GP_ARG_NUM_REG
8850       && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
8851     ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
8852 
8853   if (ret != 0 && TARGET_DEBUG_ARG)
8854     fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
8855 
8856   return ret;
8857 }
8858 
8859 /* A C expression that indicates when an argument must be passed by
8860    reference.  If nonzero for an argument, a copy of that argument is
8861    made in memory and a pointer to the argument is passed instead of
8862    the argument itself.  The pointer is passed in whatever way is
8863    appropriate for passing a pointer to that type.
8864 
8865    Under V.4, aggregates and long double are passed by reference.
8866 
8867    As an extension to all 32-bit ABIs, AltiVec vectors are passed by
8868    reference unless the AltiVec vector extension ABI is in force.
8869 
8870    As an extension to all ABIs, variable sized types are passed by
8871    reference.  */
8872 
8873 static bool
rs6000_pass_by_reference(cumulative_args_t cum ATTRIBUTE_UNUSED,enum machine_mode mode,const_tree type,bool named ATTRIBUTE_UNUSED)8874 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
8875 			  enum machine_mode mode, const_tree type,
8876 			  bool named ATTRIBUTE_UNUSED)
8877 {
8878   if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && mode == TFmode)
8879     {
8880       if (TARGET_DEBUG_ARG)
8881 	fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
8882       return 1;
8883     }
8884 
8885   if (!type)
8886     return 0;
8887 
8888   if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
8889     {
8890       if (TARGET_DEBUG_ARG)
8891 	fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
8892       return 1;
8893     }
8894 
8895   if (int_size_in_bytes (type) < 0)
8896     {
8897       if (TARGET_DEBUG_ARG)
8898 	fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
8899       return 1;
8900     }
8901 
8902   /* Allow -maltivec -mabi=no-altivec without warning.  Altivec vector
8903      modes only exist for GCC vector types if -maltivec.  */
8904   if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
8905     {
8906       if (TARGET_DEBUG_ARG)
8907 	fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
8908       return 1;
8909     }
8910 
8911   /* Pass synthetic vectors in memory.  */
8912   if (TREE_CODE (type) == VECTOR_TYPE
8913       && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
8914     {
8915       static bool warned_for_pass_big_vectors = false;
8916       if (TARGET_DEBUG_ARG)
8917 	fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
8918       if (!warned_for_pass_big_vectors)
8919 	{
8920 	  warning (0, "GCC vector passed by reference: "
8921 		   "non-standard ABI extension with no compatibility guarantee");
8922 	  warned_for_pass_big_vectors = true;
8923 	}
8924       return 1;
8925     }
8926 
8927   return 0;
8928 }
8929 
8930 static void
rs6000_move_block_from_reg(int regno,rtx x,int nregs)8931 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
8932 {
8933   int i;
8934   enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
8935 
8936   if (nregs == 0)
8937     return;
8938 
8939   for (i = 0; i < nregs; i++)
8940     {
8941       rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
8942       if (reload_completed)
8943 	{
8944 	  if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
8945 	    tem = NULL_RTX;
8946 	  else
8947 	    tem = simplify_gen_subreg (reg_mode, x, BLKmode,
8948 				       i * GET_MODE_SIZE (reg_mode));
8949 	}
8950       else
8951 	tem = replace_equiv_address (tem, XEXP (tem, 0));
8952 
8953       gcc_assert (tem);
8954 
8955       emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
8956     }
8957 }
8958 
8959 /* Perform any needed actions needed for a function that is receiving a
8960    variable number of arguments.
8961 
8962    CUM is as above.
8963 
8964    MODE and TYPE are the mode and type of the current parameter.
8965 
8966    PRETEND_SIZE is a variable that should be set to the amount of stack
8967    that must be pushed by the prolog to pretend that our caller pushed
8968    it.
8969 
8970    Normally, this macro will push all remaining incoming registers on the
8971    stack and set PRETEND_SIZE to the length of the registers pushed.  */
8972 
8973 static void
setup_incoming_varargs(cumulative_args_t cum,enum machine_mode mode,tree type,int * pretend_size ATTRIBUTE_UNUSED,int no_rtl)8974 setup_incoming_varargs (cumulative_args_t cum, enum machine_mode mode,
8975 			tree type, int *pretend_size ATTRIBUTE_UNUSED,
8976 			int no_rtl)
8977 {
8978   CUMULATIVE_ARGS next_cum;
8979   int reg_size = TARGET_32BIT ? 4 : 8;
8980   rtx save_area = NULL_RTX, mem;
8981   int first_reg_offset;
8982   alias_set_type set;
8983 
8984   /* Skip the last named argument.  */
8985   next_cum = *get_cumulative_args (cum);
8986   rs6000_function_arg_advance_1 (&next_cum, mode, type, true, 0);
8987 
8988   if (DEFAULT_ABI == ABI_V4)
8989     {
8990       first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
8991 
8992       if (! no_rtl)
8993 	{
8994 	  int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
8995 	  HOST_WIDE_INT offset = 0;
8996 
8997 	  /* Try to optimize the size of the varargs save area.
8998 	     The ABI requires that ap.reg_save_area is doubleword
8999 	     aligned, but we don't need to allocate space for all
9000 	     the bytes, only those to which we actually will save
9001 	     anything.  */
9002 	  if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
9003 	    gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
9004 	  if (TARGET_HARD_FLOAT && TARGET_FPRS
9005 	      && next_cum.fregno <= FP_ARG_V4_MAX_REG
9006 	      && cfun->va_list_fpr_size)
9007 	    {
9008 	      if (gpr_reg_num)
9009 		fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
9010 			   * UNITS_PER_FP_WORD;
9011 	      if (cfun->va_list_fpr_size
9012 		  < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
9013 		fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
9014 	      else
9015 		fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
9016 			    * UNITS_PER_FP_WORD;
9017 	    }
9018 	  if (gpr_reg_num)
9019 	    {
9020 	      offset = -((first_reg_offset * reg_size) & ~7);
9021 	      if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
9022 		{
9023 		  gpr_reg_num = cfun->va_list_gpr_size;
9024 		  if (reg_size == 4 && (first_reg_offset & 1))
9025 		    gpr_reg_num++;
9026 		}
9027 	      gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
9028 	    }
9029 	  else if (fpr_size)
9030 	    offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
9031 		       * UNITS_PER_FP_WORD
9032 		     - (int) (GP_ARG_NUM_REG * reg_size);
9033 
9034 	  if (gpr_size + fpr_size)
9035 	    {
9036 	      rtx reg_save_area
9037 		= assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
9038 	      gcc_assert (GET_CODE (reg_save_area) == MEM);
9039 	      reg_save_area = XEXP (reg_save_area, 0);
9040 	      if (GET_CODE (reg_save_area) == PLUS)
9041 		{
9042 		  gcc_assert (XEXP (reg_save_area, 0)
9043 			      == virtual_stack_vars_rtx);
9044 		  gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
9045 		  offset += INTVAL (XEXP (reg_save_area, 1));
9046 		}
9047 	      else
9048 		gcc_assert (reg_save_area == virtual_stack_vars_rtx);
9049 	    }
9050 
9051 	  cfun->machine->varargs_save_offset = offset;
9052 	  save_area = plus_constant (Pmode, virtual_stack_vars_rtx, offset);
9053 	}
9054     }
9055   else
9056     {
9057       first_reg_offset = next_cum.words;
9058       save_area = virtual_incoming_args_rtx;
9059 
9060       if (targetm.calls.must_pass_in_stack (mode, type))
9061 	first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
9062     }
9063 
9064   set = get_varargs_alias_set ();
9065   if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
9066       && cfun->va_list_gpr_size)
9067     {
9068       int nregs = GP_ARG_NUM_REG - first_reg_offset;
9069 
9070       if (va_list_gpr_counter_field)
9071 	{
9072 	  /* V4 va_list_gpr_size counts number of registers needed.  */
9073 	  if (nregs > cfun->va_list_gpr_size)
9074 	    nregs = cfun->va_list_gpr_size;
9075 	}
9076       else
9077 	{
9078 	  /* char * va_list instead counts number of bytes needed.  */
9079 	  if (nregs > cfun->va_list_gpr_size / reg_size)
9080 	    nregs = cfun->va_list_gpr_size / reg_size;
9081 	}
9082 
9083       mem = gen_rtx_MEM (BLKmode,
9084 			 plus_constant (Pmode, save_area,
9085 					first_reg_offset * reg_size));
9086       MEM_NOTRAP_P (mem) = 1;
9087       set_mem_alias_set (mem, set);
9088       set_mem_align (mem, BITS_PER_WORD);
9089 
9090       rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
9091 				  nregs);
9092     }
9093 
9094   /* Save FP registers if needed.  */
9095   if (DEFAULT_ABI == ABI_V4
9096       && TARGET_HARD_FLOAT && TARGET_FPRS
9097       && ! no_rtl
9098       && next_cum.fregno <= FP_ARG_V4_MAX_REG
9099       && cfun->va_list_fpr_size)
9100     {
9101       int fregno = next_cum.fregno, nregs;
9102       rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
9103       rtx lab = gen_label_rtx ();
9104       int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
9105 					       * UNITS_PER_FP_WORD);
9106 
9107       emit_jump_insn
9108 	(gen_rtx_SET (VOIDmode,
9109 		      pc_rtx,
9110 		      gen_rtx_IF_THEN_ELSE (VOIDmode,
9111 					    gen_rtx_NE (VOIDmode, cr1,
9112 							const0_rtx),
9113 					    gen_rtx_LABEL_REF (VOIDmode, lab),
9114 					    pc_rtx)));
9115 
9116       for (nregs = 0;
9117 	   fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
9118 	   fregno++, off += UNITS_PER_FP_WORD, nregs++)
9119 	{
9120 	  mem = gen_rtx_MEM ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
9121 			      ? DFmode : SFmode,
9122                              plus_constant (Pmode, save_area, off));
9123   	  MEM_NOTRAP_P (mem) = 1;
9124   	  set_mem_alias_set (mem, set);
9125 	  set_mem_align (mem, GET_MODE_ALIGNMENT (
9126 			 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
9127 			  ? DFmode : SFmode));
9128 	  emit_move_insn (mem, gen_rtx_REG (
9129                           (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
9130 			   ? DFmode : SFmode, fregno));
9131 	}
9132 
9133       emit_label (lab);
9134     }
9135 }
9136 
9137 /* Create the va_list data type.  */
9138 
9139 static tree
rs6000_build_builtin_va_list(void)9140 rs6000_build_builtin_va_list (void)
9141 {
9142   tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
9143 
9144   /* For AIX, prefer 'char *' because that's what the system
9145      header files like.  */
9146   if (DEFAULT_ABI != ABI_V4)
9147     return build_pointer_type (char_type_node);
9148 
9149   record = (*lang_hooks.types.make_type) (RECORD_TYPE);
9150   type_decl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
9151       			  get_identifier ("__va_list_tag"), record);
9152 
9153   f_gpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("gpr"),
9154 		      unsigned_char_type_node);
9155   f_fpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("fpr"),
9156 		      unsigned_char_type_node);
9157   /* Give the two bytes of padding a name, so that -Wpadded won't warn on
9158      every user file.  */
9159   f_res = build_decl (BUILTINS_LOCATION, FIELD_DECL,
9160       		      get_identifier ("reserved"), short_unsigned_type_node);
9161   f_ovf = build_decl (BUILTINS_LOCATION, FIELD_DECL,
9162       		      get_identifier ("overflow_arg_area"),
9163 		      ptr_type_node);
9164   f_sav = build_decl (BUILTINS_LOCATION, FIELD_DECL,
9165       		      get_identifier ("reg_save_area"),
9166 		      ptr_type_node);
9167 
9168   va_list_gpr_counter_field = f_gpr;
9169   va_list_fpr_counter_field = f_fpr;
9170 
9171   DECL_FIELD_CONTEXT (f_gpr) = record;
9172   DECL_FIELD_CONTEXT (f_fpr) = record;
9173   DECL_FIELD_CONTEXT (f_res) = record;
9174   DECL_FIELD_CONTEXT (f_ovf) = record;
9175   DECL_FIELD_CONTEXT (f_sav) = record;
9176 
9177   TYPE_STUB_DECL (record) = type_decl;
9178   TYPE_NAME (record) = type_decl;
9179   TYPE_FIELDS (record) = f_gpr;
9180   DECL_CHAIN (f_gpr) = f_fpr;
9181   DECL_CHAIN (f_fpr) = f_res;
9182   DECL_CHAIN (f_res) = f_ovf;
9183   DECL_CHAIN (f_ovf) = f_sav;
9184 
9185   layout_type (record);
9186 
9187   /* The correct type is an array type of one element.  */
9188   return build_array_type (record, build_index_type (size_zero_node));
9189 }
9190 
9191 /* Implement va_start.  */
9192 
9193 static void
rs6000_va_start(tree valist,rtx nextarg)9194 rs6000_va_start (tree valist, rtx nextarg)
9195 {
9196   HOST_WIDE_INT words, n_gpr, n_fpr;
9197   tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
9198   tree gpr, fpr, ovf, sav, t;
9199 
9200   /* Only SVR4 needs something special.  */
9201   if (DEFAULT_ABI != ABI_V4)
9202     {
9203       std_expand_builtin_va_start (valist, nextarg);
9204       return;
9205     }
9206 
9207   f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
9208   f_fpr = DECL_CHAIN (f_gpr);
9209   f_res = DECL_CHAIN (f_fpr);
9210   f_ovf = DECL_CHAIN (f_res);
9211   f_sav = DECL_CHAIN (f_ovf);
9212 
9213   valist = build_simple_mem_ref (valist);
9214   gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
9215   fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
9216 		f_fpr, NULL_TREE);
9217   ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
9218 		f_ovf, NULL_TREE);
9219   sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
9220 		f_sav, NULL_TREE);
9221 
9222   /* Count number of gp and fp argument registers used.  */
9223   words = crtl->args.info.words;
9224   n_gpr = MIN (crtl->args.info.sysv_gregno - GP_ARG_MIN_REG,
9225 	       GP_ARG_NUM_REG);
9226   n_fpr = MIN (crtl->args.info.fregno - FP_ARG_MIN_REG,
9227 	       FP_ARG_NUM_REG);
9228 
9229   if (TARGET_DEBUG_ARG)
9230     fprintf (stderr, "va_start: words = " HOST_WIDE_INT_PRINT_DEC ", n_gpr = "
9231 	     HOST_WIDE_INT_PRINT_DEC ", n_fpr = " HOST_WIDE_INT_PRINT_DEC "\n",
9232 	     words, n_gpr, n_fpr);
9233 
9234   if (cfun->va_list_gpr_size)
9235     {
9236       t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
9237 		  build_int_cst (NULL_TREE, n_gpr));
9238       TREE_SIDE_EFFECTS (t) = 1;
9239       expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9240     }
9241 
9242   if (cfun->va_list_fpr_size)
9243     {
9244       t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
9245 		  build_int_cst (NULL_TREE, n_fpr));
9246       TREE_SIDE_EFFECTS (t) = 1;
9247       expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9248 
9249 #ifdef HAVE_AS_GNU_ATTRIBUTE
9250       if (call_ABI_of_interest (cfun->decl))
9251 	rs6000_passes_float = true;
9252 #endif
9253     }
9254 
9255   /* Find the overflow area.  */
9256   t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
9257   if (words != 0)
9258     t = fold_build_pointer_plus_hwi (t, words * UNITS_PER_WORD);
9259   t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
9260   TREE_SIDE_EFFECTS (t) = 1;
9261   expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9262 
9263   /* If there were no va_arg invocations, don't set up the register
9264      save area.  */
9265   if (!cfun->va_list_gpr_size
9266       && !cfun->va_list_fpr_size
9267       && n_gpr < GP_ARG_NUM_REG
9268       && n_fpr < FP_ARG_V4_MAX_REG)
9269     return;
9270 
9271   /* Find the register save area.  */
9272   t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
9273   if (cfun->machine->varargs_save_offset)
9274     t = fold_build_pointer_plus_hwi (t, cfun->machine->varargs_save_offset);
9275   t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
9276   TREE_SIDE_EFFECTS (t) = 1;
9277   expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9278 }
9279 
9280 /* Implement va_arg.  */
9281 
9282 static tree
rs6000_gimplify_va_arg(tree valist,tree type,gimple_seq * pre_p,gimple_seq * post_p)9283 rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
9284 			gimple_seq *post_p)
9285 {
9286   tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
9287   tree gpr, fpr, ovf, sav, reg, t, u;
9288   int size, rsize, n_reg, sav_ofs, sav_scale;
9289   tree lab_false, lab_over, addr;
9290   int align;
9291   tree ptrtype = build_pointer_type_for_mode (type, ptr_mode, true);
9292   int regalign = 0;
9293   gimple stmt;
9294 
9295   if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
9296     {
9297       t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
9298       return build_va_arg_indirect_ref (t);
9299     }
9300 
9301   /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
9302      earlier version of gcc, with the property that it always applied alignment
9303      adjustments to the va-args (even for zero-sized types).  The cheapest way
9304      to deal with this is to replicate the effect of the part of
9305      std_gimplify_va_arg_expr that carries out the align adjust, for the case
9306      of relevance.
9307      We don't need to check for pass-by-reference because of the test above.
9308      We can return a simplifed answer, since we know there's no offset to add.  */
9309 
9310   if (TARGET_MACHO
9311       && rs6000_darwin64_abi
9312       && integer_zerop (TYPE_SIZE (type)))
9313     {
9314       unsigned HOST_WIDE_INT align, boundary;
9315       tree valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
9316       align = PARM_BOUNDARY / BITS_PER_UNIT;
9317       boundary = rs6000_function_arg_boundary (TYPE_MODE (type), type);
9318       if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
9319 	boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
9320       boundary /= BITS_PER_UNIT;
9321       if (boundary > align)
9322 	{
9323 	  tree t ;
9324 	  /* This updates arg ptr by the amount that would be necessary
9325 	     to align the zero-sized (but not zero-alignment) item.  */
9326 	  t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
9327 		      fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
9328 	  gimplify_and_add (t, pre_p);
9329 
9330 	  t = fold_convert (sizetype, valist_tmp);
9331 	  t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
9332 		  fold_convert (TREE_TYPE (valist),
9333 				fold_build2 (BIT_AND_EXPR, sizetype, t,
9334 					     size_int (-boundary))));
9335 	  t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
9336 	  gimplify_and_add (t, pre_p);
9337 	}
9338       /* Since it is zero-sized there's no increment for the item itself. */
9339       valist_tmp = fold_convert (build_pointer_type (type), valist_tmp);
9340       return build_va_arg_indirect_ref (valist_tmp);
9341     }
9342 
9343   if (DEFAULT_ABI != ABI_V4)
9344     {
9345       if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
9346 	{
9347 	  tree elem_type = TREE_TYPE (type);
9348 	  enum machine_mode elem_mode = TYPE_MODE (elem_type);
9349 	  int elem_size = GET_MODE_SIZE (elem_mode);
9350 
9351 	  if (elem_size < UNITS_PER_WORD)
9352 	    {
9353 	      tree real_part, imag_part;
9354 	      gimple_seq post = NULL;
9355 
9356 	      real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
9357 						  &post);
9358 	      /* Copy the value into a temporary, lest the formal temporary
9359 		 be reused out from under us.  */
9360 	      real_part = get_initialized_tmp_var (real_part, pre_p, &post);
9361 	      gimple_seq_add_seq (pre_p, post);
9362 
9363 	      imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
9364 						  post_p);
9365 
9366 	      return build2 (COMPLEX_EXPR, type, real_part, imag_part);
9367 	    }
9368 	}
9369 
9370       return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
9371     }
9372 
9373   f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
9374   f_fpr = DECL_CHAIN (f_gpr);
9375   f_res = DECL_CHAIN (f_fpr);
9376   f_ovf = DECL_CHAIN (f_res);
9377   f_sav = DECL_CHAIN (f_ovf);
9378 
9379   valist = build_va_arg_indirect_ref (valist);
9380   gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
9381   fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
9382 		f_fpr, NULL_TREE);
9383   ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
9384 		f_ovf, NULL_TREE);
9385   sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
9386 		f_sav, NULL_TREE);
9387 
9388   size = int_size_in_bytes (type);
9389   rsize = (size + 3) / 4;
9390   align = 1;
9391 
9392   if (TARGET_HARD_FLOAT && TARGET_FPRS
9393       && ((TARGET_SINGLE_FLOAT && TYPE_MODE (type) == SFmode)
9394           || (TARGET_DOUBLE_FLOAT
9395               && (TYPE_MODE (type) == DFmode
9396  	          || TYPE_MODE (type) == TFmode
9397 	          || TYPE_MODE (type) == SDmode
9398 	          || TYPE_MODE (type) == DDmode
9399 	          || TYPE_MODE (type) == TDmode))))
9400     {
9401       /* FP args go in FP registers, if present.  */
9402       reg = fpr;
9403       n_reg = (size + 7) / 8;
9404       sav_ofs = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4) * 4;
9405       sav_scale = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4);
9406       if (TYPE_MODE (type) != SFmode && TYPE_MODE (type) != SDmode)
9407 	align = 8;
9408     }
9409   else
9410     {
9411       /* Otherwise into GP registers.  */
9412       reg = gpr;
9413       n_reg = rsize;
9414       sav_ofs = 0;
9415       sav_scale = 4;
9416       if (n_reg == 2)
9417 	align = 8;
9418     }
9419 
9420   /* Pull the value out of the saved registers....  */
9421 
9422   lab_over = NULL;
9423   addr = create_tmp_var (ptr_type_node, "addr");
9424 
9425   /*  AltiVec vectors never go in registers when -mabi=altivec.  */
9426   if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
9427     align = 16;
9428   else
9429     {
9430       lab_false = create_artificial_label (input_location);
9431       lab_over = create_artificial_label (input_location);
9432 
9433       /* Long long and SPE vectors are aligned in the registers.
9434 	 As are any other 2 gpr item such as complex int due to a
9435 	 historical mistake.  */
9436       u = reg;
9437       if (n_reg == 2 && reg == gpr)
9438 	{
9439 	  regalign = 1;
9440 	  u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), unshare_expr (reg),
9441 		     build_int_cst (TREE_TYPE (reg), n_reg - 1));
9442 	  u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg),
9443 		      unshare_expr (reg), u);
9444 	}
9445       /* _Decimal128 is passed in even/odd fpr pairs; the stored
9446 	 reg number is 0 for f1, so we want to make it odd.  */
9447       else if (reg == fpr && TYPE_MODE (type) == TDmode)
9448 	{
9449 	  t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), unshare_expr (reg),
9450 		      build_int_cst (TREE_TYPE (reg), 1));
9451 	  u = build2 (MODIFY_EXPR, void_type_node, unshare_expr (reg), t);
9452 	}
9453 
9454       t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
9455       t = build2 (GE_EXPR, boolean_type_node, u, t);
9456       u = build1 (GOTO_EXPR, void_type_node, lab_false);
9457       t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
9458       gimplify_and_add (t, pre_p);
9459 
9460       t = sav;
9461       if (sav_ofs)
9462 	t = fold_build_pointer_plus_hwi (sav, sav_ofs);
9463 
9464       u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), unshare_expr (reg),
9465 		  build_int_cst (TREE_TYPE (reg), n_reg));
9466       u = fold_convert (sizetype, u);
9467       u = build2 (MULT_EXPR, sizetype, u, size_int (sav_scale));
9468       t = fold_build_pointer_plus (t, u);
9469 
9470       /* _Decimal32 varargs are located in the second word of the 64-bit
9471 	 FP register for 32-bit binaries.  */
9472       if (!TARGET_POWERPC64
9473 	  && TARGET_HARD_FLOAT && TARGET_FPRS
9474 	  && TYPE_MODE (type) == SDmode)
9475 	t = fold_build_pointer_plus_hwi (t, size);
9476 
9477       gimplify_assign (addr, t, pre_p);
9478 
9479       gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
9480 
9481       stmt = gimple_build_label (lab_false);
9482       gimple_seq_add_stmt (pre_p, stmt);
9483 
9484       if ((n_reg == 2 && !regalign) || n_reg > 2)
9485 	{
9486 	  /* Ensure that we don't find any more args in regs.
9487 	     Alignment has taken care of for special cases.  */
9488 	  gimplify_assign (reg, build_int_cst (TREE_TYPE (reg), 8), pre_p);
9489 	}
9490     }
9491 
9492   /* ... otherwise out of the overflow area.  */
9493 
9494   /* Care for on-stack alignment if needed.  */
9495   t = ovf;
9496   if (align != 1)
9497     {
9498       t = fold_build_pointer_plus_hwi (t, align - 1);
9499       t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
9500 		  build_int_cst (TREE_TYPE (t), -align));
9501     }
9502   gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
9503 
9504   gimplify_assign (unshare_expr (addr), t, pre_p);
9505 
9506   t = fold_build_pointer_plus_hwi (t, size);
9507   gimplify_assign (unshare_expr (ovf), t, pre_p);
9508 
9509   if (lab_over)
9510     {
9511       stmt = gimple_build_label (lab_over);
9512       gimple_seq_add_stmt (pre_p, stmt);
9513     }
9514 
9515   if (STRICT_ALIGNMENT
9516       && (TYPE_ALIGN (type)
9517 	  > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
9518     {
9519       /* The value (of type complex double, for example) may not be
9520 	 aligned in memory in the saved registers, so copy via a
9521 	 temporary.  (This is the same code as used for SPARC.)  */
9522       tree tmp = create_tmp_var (type, "va_arg_tmp");
9523       tree dest_addr = build_fold_addr_expr (tmp);
9524 
9525       tree copy = build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY),
9526 				   3, dest_addr, addr, size_int (rsize * 4));
9527 
9528       gimplify_and_add (copy, pre_p);
9529       addr = dest_addr;
9530     }
9531 
9532   addr = fold_convert (ptrtype, addr);
9533   return build_va_arg_indirect_ref (addr);
9534 }
9535 
9536 /* Builtins.  */
9537 
9538 static void
def_builtin(const char * name,tree type,enum rs6000_builtins code)9539 def_builtin (const char *name, tree type, enum rs6000_builtins code)
9540 {
9541   tree t;
9542   unsigned classify = rs6000_builtin_info[(int)code].attr;
9543   const char *attr_string = "";
9544 
9545   gcc_assert (name != NULL);
9546   gcc_assert (IN_RANGE ((int)code, 0, (int)RS6000_BUILTIN_COUNT));
9547 
9548   if (rs6000_builtin_decls[(int)code])
9549     fatal_error ("internal error: builtin function %s already processed", name);
9550 
9551   rs6000_builtin_decls[(int)code] = t =
9552     add_builtin_function (name, type, (int)code, BUILT_IN_MD, NULL, NULL_TREE);
9553 
9554   /* Set any special attributes.  */
9555   if ((classify & RS6000_BTC_CONST) != 0)
9556     {
9557       /* const function, function only depends on the inputs.  */
9558       TREE_READONLY (t) = 1;
9559       TREE_NOTHROW (t) = 1;
9560       attr_string = ", pure";
9561     }
9562   else if ((classify & RS6000_BTC_PURE) != 0)
9563     {
9564       /* pure function, function can read global memory, but does not set any
9565 	 external state.  */
9566       DECL_PURE_P (t) = 1;
9567       TREE_NOTHROW (t) = 1;
9568       attr_string = ", const";
9569     }
9570   else if ((classify & RS6000_BTC_FP) != 0)
9571     {
9572       /* Function is a math function.  If rounding mode is on, then treat the
9573 	 function as not reading global memory, but it can have arbitrary side
9574 	 effects.  If it is off, then assume the function is a const function.
9575 	 This mimics the ATTR_MATHFN_FPROUNDING attribute in
9576 	 builtin-attribute.def that is used for the math functions. */
9577       TREE_NOTHROW (t) = 1;
9578       if (flag_rounding_math)
9579 	{
9580 	  DECL_PURE_P (t) = 1;
9581 	  DECL_IS_NOVOPS (t) = 1;
9582 	  attr_string = ", fp, pure";
9583 	}
9584       else
9585 	{
9586 	  TREE_READONLY (t) = 1;
9587 	  attr_string = ", fp, const";
9588 	}
9589     }
9590   else if ((classify & RS6000_BTC_ATTR_MASK) != 0)
9591     gcc_unreachable ();
9592 
9593   if (TARGET_DEBUG_BUILTIN)
9594     fprintf (stderr, "rs6000_builtin, code = %4d, %s%s\n",
9595 	     (int)code, name, attr_string);
9596 }
9597 
9598 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc).  */
9599 
9600 #undef RS6000_BUILTIN_1
9601 #undef RS6000_BUILTIN_2
9602 #undef RS6000_BUILTIN_3
9603 #undef RS6000_BUILTIN_A
9604 #undef RS6000_BUILTIN_D
9605 #undef RS6000_BUILTIN_E
9606 #undef RS6000_BUILTIN_P
9607 #undef RS6000_BUILTIN_Q
9608 #undef RS6000_BUILTIN_S
9609 #undef RS6000_BUILTIN_X
9610 
9611 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9612 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9613 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
9614   { MASK, ICODE, NAME, ENUM },
9615 
9616 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9617 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9618 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9619 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9620 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9621 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9622 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9623 
9624 static const struct builtin_description bdesc_3arg[] =
9625 {
9626 #include "rs6000-builtin.def"
9627 };
9628 
9629 /* DST operations: void foo (void *, const int, const char).  */
9630 
9631 #undef RS6000_BUILTIN_1
9632 #undef RS6000_BUILTIN_2
9633 #undef RS6000_BUILTIN_3
9634 #undef RS6000_BUILTIN_A
9635 #undef RS6000_BUILTIN_D
9636 #undef RS6000_BUILTIN_E
9637 #undef RS6000_BUILTIN_P
9638 #undef RS6000_BUILTIN_Q
9639 #undef RS6000_BUILTIN_S
9640 #undef RS6000_BUILTIN_X
9641 
9642 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9643 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9644 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9645 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9646 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
9647   { MASK, ICODE, NAME, ENUM },
9648 
9649 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9650 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9651 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9652 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9653 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9654 
9655 static const struct builtin_description bdesc_dst[] =
9656 {
9657 #include "rs6000-builtin.def"
9658 };
9659 
9660 /* Simple binary operations: VECc = foo (VECa, VECb).  */
9661 
9662 #undef RS6000_BUILTIN_1
9663 #undef RS6000_BUILTIN_2
9664 #undef RS6000_BUILTIN_3
9665 #undef RS6000_BUILTIN_A
9666 #undef RS6000_BUILTIN_D
9667 #undef RS6000_BUILTIN_E
9668 #undef RS6000_BUILTIN_P
9669 #undef RS6000_BUILTIN_Q
9670 #undef RS6000_BUILTIN_S
9671 #undef RS6000_BUILTIN_X
9672 
9673 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9674 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
9675   { MASK, ICODE, NAME, ENUM },
9676 
9677 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9678 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9679 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9680 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9681 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9682 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9683 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9684 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9685 
9686 static const struct builtin_description bdesc_2arg[] =
9687 {
9688 #include "rs6000-builtin.def"
9689 };
9690 
9691 #undef RS6000_BUILTIN_1
9692 #undef RS6000_BUILTIN_2
9693 #undef RS6000_BUILTIN_3
9694 #undef RS6000_BUILTIN_A
9695 #undef RS6000_BUILTIN_D
9696 #undef RS6000_BUILTIN_E
9697 #undef RS6000_BUILTIN_P
9698 #undef RS6000_BUILTIN_Q
9699 #undef RS6000_BUILTIN_S
9700 #undef RS6000_BUILTIN_X
9701 
9702 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9703 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9704 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9705 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9706 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9707 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9708 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
9709   { MASK, ICODE, NAME, ENUM },
9710 
9711 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9712 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9713 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9714 
9715 /* AltiVec predicates.  */
9716 
9717 static const struct builtin_description bdesc_altivec_preds[] =
9718 {
9719 #include "rs6000-builtin.def"
9720 };
9721 
9722 /* SPE predicates.  */
9723 #undef RS6000_BUILTIN_1
9724 #undef RS6000_BUILTIN_2
9725 #undef RS6000_BUILTIN_3
9726 #undef RS6000_BUILTIN_A
9727 #undef RS6000_BUILTIN_D
9728 #undef RS6000_BUILTIN_E
9729 #undef RS6000_BUILTIN_P
9730 #undef RS6000_BUILTIN_Q
9731 #undef RS6000_BUILTIN_S
9732 #undef RS6000_BUILTIN_X
9733 
9734 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9735 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9736 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9737 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9738 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9739 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9740 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9741 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9742 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
9743   { MASK, ICODE, NAME, ENUM },
9744 
9745 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9746 
9747 static const struct builtin_description bdesc_spe_predicates[] =
9748 {
9749 #include "rs6000-builtin.def"
9750 };
9751 
9752 /* SPE evsel predicates.  */
9753 #undef RS6000_BUILTIN_1
9754 #undef RS6000_BUILTIN_2
9755 #undef RS6000_BUILTIN_3
9756 #undef RS6000_BUILTIN_A
9757 #undef RS6000_BUILTIN_D
9758 #undef RS6000_BUILTIN_E
9759 #undef RS6000_BUILTIN_P
9760 #undef RS6000_BUILTIN_Q
9761 #undef RS6000_BUILTIN_S
9762 #undef RS6000_BUILTIN_X
9763 
9764 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9765 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9766 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9767 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9768 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9769 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
9770   { MASK, ICODE, NAME, ENUM },
9771 
9772 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9773 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9774 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9775 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9776 
9777 static const struct builtin_description bdesc_spe_evsel[] =
9778 {
9779 #include "rs6000-builtin.def"
9780 };
9781 
9782 /* PAIRED predicates.  */
9783 #undef RS6000_BUILTIN_1
9784 #undef RS6000_BUILTIN_2
9785 #undef RS6000_BUILTIN_3
9786 #undef RS6000_BUILTIN_A
9787 #undef RS6000_BUILTIN_D
9788 #undef RS6000_BUILTIN_E
9789 #undef RS6000_BUILTIN_P
9790 #undef RS6000_BUILTIN_Q
9791 #undef RS6000_BUILTIN_S
9792 #undef RS6000_BUILTIN_X
9793 
9794 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9795 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9796 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9797 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9798 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9799 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9800 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9801 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
9802   { MASK, ICODE, NAME, ENUM },
9803 
9804 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9805 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9806 
9807 static const struct builtin_description bdesc_paired_preds[] =
9808 {
9809 #include "rs6000-builtin.def"
9810 };
9811 
9812 /* ABS* operations.  */
9813 
9814 #undef RS6000_BUILTIN_1
9815 #undef RS6000_BUILTIN_2
9816 #undef RS6000_BUILTIN_3
9817 #undef RS6000_BUILTIN_A
9818 #undef RS6000_BUILTIN_D
9819 #undef RS6000_BUILTIN_E
9820 #undef RS6000_BUILTIN_P
9821 #undef RS6000_BUILTIN_Q
9822 #undef RS6000_BUILTIN_S
9823 #undef RS6000_BUILTIN_X
9824 
9825 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9826 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9827 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9828 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
9829   { MASK, ICODE, NAME, ENUM },
9830 
9831 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9832 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9833 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9834 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9835 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9836 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9837 
9838 static const struct builtin_description bdesc_abs[] =
9839 {
9840 #include "rs6000-builtin.def"
9841 };
9842 
9843 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
9844    foo (VECa).  */
9845 
9846 #undef RS6000_BUILTIN_1
9847 #undef RS6000_BUILTIN_2
9848 #undef RS6000_BUILTIN_3
9849 #undef RS6000_BUILTIN_A
9850 #undef RS6000_BUILTIN_E
9851 #undef RS6000_BUILTIN_D
9852 #undef RS6000_BUILTIN_P
9853 #undef RS6000_BUILTIN_Q
9854 #undef RS6000_BUILTIN_S
9855 #undef RS6000_BUILTIN_X
9856 
9857 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
9858   { MASK, ICODE, NAME, ENUM },
9859 
9860 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9861 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9862 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9863 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9864 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9865 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9866 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9867 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9868 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9869 
9870 static const struct builtin_description bdesc_1arg[] =
9871 {
9872 #include "rs6000-builtin.def"
9873 };
9874 
9875 #undef RS6000_BUILTIN_1
9876 #undef RS6000_BUILTIN_2
9877 #undef RS6000_BUILTIN_3
9878 #undef RS6000_BUILTIN_A
9879 #undef RS6000_BUILTIN_D
9880 #undef RS6000_BUILTIN_E
9881 #undef RS6000_BUILTIN_P
9882 #undef RS6000_BUILTIN_Q
9883 #undef RS6000_BUILTIN_S
9884 #undef RS6000_BUILTIN_X
9885 
9886 /* Return true if a builtin function is overloaded.  */
9887 bool
rs6000_overloaded_builtin_p(enum rs6000_builtins fncode)9888 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode)
9889 {
9890   return (rs6000_builtin_info[(int)fncode].attr & RS6000_BTC_OVERLOADED) != 0;
9891 }
9892 
9893 /* Expand an expression EXP that calls a builtin without arguments.  */
9894 static rtx
rs6000_expand_zeroop_builtin(enum insn_code icode,rtx target)9895 rs6000_expand_zeroop_builtin (enum insn_code icode, rtx target)
9896 {
9897   rtx pat;
9898   enum machine_mode tmode = insn_data[icode].operand[0].mode;
9899 
9900   if (icode == CODE_FOR_nothing)
9901     /* Builtin not supported on this processor.  */
9902     return 0;
9903 
9904   if (target == 0
9905       || GET_MODE (target) != tmode
9906       || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9907     target = gen_reg_rtx (tmode);
9908 
9909   pat = GEN_FCN (icode) (target);
9910   if (! pat)
9911     return 0;
9912   emit_insn (pat);
9913 
9914   return target;
9915 }
9916 
9917 
9918 static rtx
rs6000_expand_unop_builtin(enum insn_code icode,tree exp,rtx target)9919 rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
9920 {
9921   rtx pat;
9922   tree arg0 = CALL_EXPR_ARG (exp, 0);
9923   rtx op0 = expand_normal (arg0);
9924   enum machine_mode tmode = insn_data[icode].operand[0].mode;
9925   enum machine_mode mode0 = insn_data[icode].operand[1].mode;
9926 
9927   if (icode == CODE_FOR_nothing)
9928     /* Builtin not supported on this processor.  */
9929     return 0;
9930 
9931   /* If we got invalid arguments bail out before generating bad rtl.  */
9932   if (arg0 == error_mark_node)
9933     return const0_rtx;
9934 
9935   if (icode == CODE_FOR_altivec_vspltisb
9936       || icode == CODE_FOR_altivec_vspltish
9937       || icode == CODE_FOR_altivec_vspltisw
9938       || icode == CODE_FOR_spe_evsplatfi
9939       || icode == CODE_FOR_spe_evsplati)
9940     {
9941       /* Only allow 5-bit *signed* literals.  */
9942       if (GET_CODE (op0) != CONST_INT
9943 	  || INTVAL (op0) > 15
9944 	  || INTVAL (op0) < -16)
9945 	{
9946 	  error ("argument 1 must be a 5-bit signed literal");
9947 	  return const0_rtx;
9948 	}
9949     }
9950 
9951   if (target == 0
9952       || GET_MODE (target) != tmode
9953       || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9954     target = gen_reg_rtx (tmode);
9955 
9956   if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9957     op0 = copy_to_mode_reg (mode0, op0);
9958 
9959   pat = GEN_FCN (icode) (target, op0);
9960   if (! pat)
9961     return 0;
9962   emit_insn (pat);
9963 
9964   return target;
9965 }
9966 
9967 static rtx
altivec_expand_abs_builtin(enum insn_code icode,tree exp,rtx target)9968 altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target)
9969 {
9970   rtx pat, scratch1, scratch2;
9971   tree arg0 = CALL_EXPR_ARG (exp, 0);
9972   rtx op0 = expand_normal (arg0);
9973   enum machine_mode tmode = insn_data[icode].operand[0].mode;
9974   enum machine_mode mode0 = insn_data[icode].operand[1].mode;
9975 
9976   /* If we have invalid arguments, bail out before generating bad rtl.  */
9977   if (arg0 == error_mark_node)
9978     return const0_rtx;
9979 
9980   if (target == 0
9981       || GET_MODE (target) != tmode
9982       || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9983     target = gen_reg_rtx (tmode);
9984 
9985   if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9986     op0 = copy_to_mode_reg (mode0, op0);
9987 
9988   scratch1 = gen_reg_rtx (mode0);
9989   scratch2 = gen_reg_rtx (mode0);
9990 
9991   pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
9992   if (! pat)
9993     return 0;
9994   emit_insn (pat);
9995 
9996   return target;
9997 }
9998 
9999 static rtx
rs6000_expand_binop_builtin(enum insn_code icode,tree exp,rtx target)10000 rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
10001 {
10002   rtx pat;
10003   tree arg0 = CALL_EXPR_ARG (exp, 0);
10004   tree arg1 = CALL_EXPR_ARG (exp, 1);
10005   rtx op0 = expand_normal (arg0);
10006   rtx op1 = expand_normal (arg1);
10007   enum machine_mode tmode = insn_data[icode].operand[0].mode;
10008   enum machine_mode mode0 = insn_data[icode].operand[1].mode;
10009   enum machine_mode mode1 = insn_data[icode].operand[2].mode;
10010 
10011   if (icode == CODE_FOR_nothing)
10012     /* Builtin not supported on this processor.  */
10013     return 0;
10014 
10015   /* If we got invalid arguments bail out before generating bad rtl.  */
10016   if (arg0 == error_mark_node || arg1 == error_mark_node)
10017     return const0_rtx;
10018 
10019   if (icode == CODE_FOR_altivec_vcfux
10020       || icode == CODE_FOR_altivec_vcfsx
10021       || icode == CODE_FOR_altivec_vctsxs
10022       || icode == CODE_FOR_altivec_vctuxs
10023       || icode == CODE_FOR_altivec_vspltb
10024       || icode == CODE_FOR_altivec_vsplth
10025       || icode == CODE_FOR_altivec_vspltw
10026       || icode == CODE_FOR_spe_evaddiw
10027       || icode == CODE_FOR_spe_evldd
10028       || icode == CODE_FOR_spe_evldh
10029       || icode == CODE_FOR_spe_evldw
10030       || icode == CODE_FOR_spe_evlhhesplat
10031       || icode == CODE_FOR_spe_evlhhossplat
10032       || icode == CODE_FOR_spe_evlhhousplat
10033       || icode == CODE_FOR_spe_evlwhe
10034       || icode == CODE_FOR_spe_evlwhos
10035       || icode == CODE_FOR_spe_evlwhou
10036       || icode == CODE_FOR_spe_evlwhsplat
10037       || icode == CODE_FOR_spe_evlwwsplat
10038       || icode == CODE_FOR_spe_evrlwi
10039       || icode == CODE_FOR_spe_evslwi
10040       || icode == CODE_FOR_spe_evsrwis
10041       || icode == CODE_FOR_spe_evsubifw
10042       || icode == CODE_FOR_spe_evsrwiu)
10043     {
10044       /* Only allow 5-bit unsigned literals.  */
10045       STRIP_NOPS (arg1);
10046       if (TREE_CODE (arg1) != INTEGER_CST
10047 	  || TREE_INT_CST_LOW (arg1) & ~0x1f)
10048 	{
10049 	  error ("argument 2 must be a 5-bit unsigned literal");
10050 	  return const0_rtx;
10051 	}
10052     }
10053 
10054   if (target == 0
10055       || GET_MODE (target) != tmode
10056       || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10057     target = gen_reg_rtx (tmode);
10058 
10059   if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
10060     op0 = copy_to_mode_reg (mode0, op0);
10061   if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
10062     op1 = copy_to_mode_reg (mode1, op1);
10063 
10064   pat = GEN_FCN (icode) (target, op0, op1);
10065   if (! pat)
10066     return 0;
10067   emit_insn (pat);
10068 
10069   return target;
10070 }
10071 
10072 static rtx
altivec_expand_predicate_builtin(enum insn_code icode,tree exp,rtx target)10073 altivec_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
10074 {
10075   rtx pat, scratch;
10076   tree cr6_form = CALL_EXPR_ARG (exp, 0);
10077   tree arg0 = CALL_EXPR_ARG (exp, 1);
10078   tree arg1 = CALL_EXPR_ARG (exp, 2);
10079   rtx op0 = expand_normal (arg0);
10080   rtx op1 = expand_normal (arg1);
10081   enum machine_mode tmode = SImode;
10082   enum machine_mode mode0 = insn_data[icode].operand[1].mode;
10083   enum machine_mode mode1 = insn_data[icode].operand[2].mode;
10084   int cr6_form_int;
10085 
10086   if (TREE_CODE (cr6_form) != INTEGER_CST)
10087     {
10088       error ("argument 1 of __builtin_altivec_predicate must be a constant");
10089       return const0_rtx;
10090     }
10091   else
10092     cr6_form_int = TREE_INT_CST_LOW (cr6_form);
10093 
10094   gcc_assert (mode0 == mode1);
10095 
10096   /* If we have invalid arguments, bail out before generating bad rtl.  */
10097   if (arg0 == error_mark_node || arg1 == error_mark_node)
10098     return const0_rtx;
10099 
10100   if (target == 0
10101       || GET_MODE (target) != tmode
10102       || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10103     target = gen_reg_rtx (tmode);
10104 
10105   if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
10106     op0 = copy_to_mode_reg (mode0, op0);
10107   if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
10108     op1 = copy_to_mode_reg (mode1, op1);
10109 
10110   scratch = gen_reg_rtx (mode0);
10111 
10112   pat = GEN_FCN (icode) (scratch, op0, op1);
10113   if (! pat)
10114     return 0;
10115   emit_insn (pat);
10116 
10117   /* The vec_any* and vec_all* predicates use the same opcodes for two
10118      different operations, but the bits in CR6 will be different
10119      depending on what information we want.  So we have to play tricks
10120      with CR6 to get the right bits out.
10121 
10122      If you think this is disgusting, look at the specs for the
10123      AltiVec predicates.  */
10124 
10125   switch (cr6_form_int)
10126     {
10127     case 0:
10128       emit_insn (gen_cr6_test_for_zero (target));
10129       break;
10130     case 1:
10131       emit_insn (gen_cr6_test_for_zero_reverse (target));
10132       break;
10133     case 2:
10134       emit_insn (gen_cr6_test_for_lt (target));
10135       break;
10136     case 3:
10137       emit_insn (gen_cr6_test_for_lt_reverse (target));
10138       break;
10139     default:
10140       error ("argument 1 of __builtin_altivec_predicate is out of range");
10141       break;
10142     }
10143 
10144   return target;
10145 }
10146 
10147 static rtx
paired_expand_lv_builtin(enum insn_code icode,tree exp,rtx target)10148 paired_expand_lv_builtin (enum insn_code icode, tree exp, rtx target)
10149 {
10150   rtx pat, addr;
10151   tree arg0 = CALL_EXPR_ARG (exp, 0);
10152   tree arg1 = CALL_EXPR_ARG (exp, 1);
10153   enum machine_mode tmode = insn_data[icode].operand[0].mode;
10154   enum machine_mode mode0 = Pmode;
10155   enum machine_mode mode1 = Pmode;
10156   rtx op0 = expand_normal (arg0);
10157   rtx op1 = expand_normal (arg1);
10158 
10159   if (icode == CODE_FOR_nothing)
10160     /* Builtin not supported on this processor.  */
10161     return 0;
10162 
10163   /* If we got invalid arguments bail out before generating bad rtl.  */
10164   if (arg0 == error_mark_node || arg1 == error_mark_node)
10165     return const0_rtx;
10166 
10167   if (target == 0
10168       || GET_MODE (target) != tmode
10169       || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10170     target = gen_reg_rtx (tmode);
10171 
10172   op1 = copy_to_mode_reg (mode1, op1);
10173 
10174   if (op0 == const0_rtx)
10175     {
10176       addr = gen_rtx_MEM (tmode, op1);
10177     }
10178   else
10179     {
10180       op0 = copy_to_mode_reg (mode0, op0);
10181       addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
10182     }
10183 
10184   pat = GEN_FCN (icode) (target, addr);
10185 
10186   if (! pat)
10187     return 0;
10188   emit_insn (pat);
10189 
10190   return target;
10191 }
10192 
10193 static rtx
altivec_expand_lv_builtin(enum insn_code icode,tree exp,rtx target,bool blk)10194 altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target, bool blk)
10195 {
10196   rtx pat, addr;
10197   tree arg0 = CALL_EXPR_ARG (exp, 0);
10198   tree arg1 = CALL_EXPR_ARG (exp, 1);
10199   enum machine_mode tmode = insn_data[icode].operand[0].mode;
10200   enum machine_mode mode0 = Pmode;
10201   enum machine_mode mode1 = Pmode;
10202   rtx op0 = expand_normal (arg0);
10203   rtx op1 = expand_normal (arg1);
10204 
10205   if (icode == CODE_FOR_nothing)
10206     /* Builtin not supported on this processor.  */
10207     return 0;
10208 
10209   /* If we got invalid arguments bail out before generating bad rtl.  */
10210   if (arg0 == error_mark_node || arg1 == error_mark_node)
10211     return const0_rtx;
10212 
10213   if (target == 0
10214       || GET_MODE (target) != tmode
10215       || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10216     target = gen_reg_rtx (tmode);
10217 
10218   op1 = copy_to_mode_reg (mode1, op1);
10219 
10220   if (op0 == const0_rtx)
10221     {
10222       addr = gen_rtx_MEM (blk ? BLKmode : tmode, op1);
10223     }
10224   else
10225     {
10226       op0 = copy_to_mode_reg (mode0, op0);
10227       addr = gen_rtx_MEM (blk ? BLKmode : tmode, gen_rtx_PLUS (Pmode, op0, op1));
10228     }
10229 
10230   pat = GEN_FCN (icode) (target, addr);
10231 
10232   if (! pat)
10233     return 0;
10234   emit_insn (pat);
10235 
10236   return target;
10237 }
10238 
10239 static rtx
spe_expand_stv_builtin(enum insn_code icode,tree exp)10240 spe_expand_stv_builtin (enum insn_code icode, tree exp)
10241 {
10242   tree arg0 = CALL_EXPR_ARG (exp, 0);
10243   tree arg1 = CALL_EXPR_ARG (exp, 1);
10244   tree arg2 = CALL_EXPR_ARG (exp, 2);
10245   rtx op0 = expand_normal (arg0);
10246   rtx op1 = expand_normal (arg1);
10247   rtx op2 = expand_normal (arg2);
10248   rtx pat;
10249   enum machine_mode mode0 = insn_data[icode].operand[0].mode;
10250   enum machine_mode mode1 = insn_data[icode].operand[1].mode;
10251   enum machine_mode mode2 = insn_data[icode].operand[2].mode;
10252 
10253   /* Invalid arguments.  Bail before doing anything stoopid!  */
10254   if (arg0 == error_mark_node
10255       || arg1 == error_mark_node
10256       || arg2 == error_mark_node)
10257     return const0_rtx;
10258 
10259   if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
10260     op0 = copy_to_mode_reg (mode2, op0);
10261   if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
10262     op1 = copy_to_mode_reg (mode0, op1);
10263   if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
10264     op2 = copy_to_mode_reg (mode1, op2);
10265 
10266   pat = GEN_FCN (icode) (op1, op2, op0);
10267   if (pat)
10268     emit_insn (pat);
10269   return NULL_RTX;
10270 }
10271 
10272 static rtx
paired_expand_stv_builtin(enum insn_code icode,tree exp)10273 paired_expand_stv_builtin (enum insn_code icode, tree exp)
10274 {
10275   tree arg0 = CALL_EXPR_ARG (exp, 0);
10276   tree arg1 = CALL_EXPR_ARG (exp, 1);
10277   tree arg2 = CALL_EXPR_ARG (exp, 2);
10278   rtx op0 = expand_normal (arg0);
10279   rtx op1 = expand_normal (arg1);
10280   rtx op2 = expand_normal (arg2);
10281   rtx pat, addr;
10282   enum machine_mode tmode = insn_data[icode].operand[0].mode;
10283   enum machine_mode mode1 = Pmode;
10284   enum machine_mode mode2 = Pmode;
10285 
10286   /* Invalid arguments.  Bail before doing anything stoopid!  */
10287   if (arg0 == error_mark_node
10288       || arg1 == error_mark_node
10289       || arg2 == error_mark_node)
10290     return const0_rtx;
10291 
10292   if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
10293     op0 = copy_to_mode_reg (tmode, op0);
10294 
10295   op2 = copy_to_mode_reg (mode2, op2);
10296 
10297   if (op1 == const0_rtx)
10298     {
10299       addr = gen_rtx_MEM (tmode, op2);
10300     }
10301   else
10302     {
10303       op1 = copy_to_mode_reg (mode1, op1);
10304       addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
10305     }
10306 
10307   pat = GEN_FCN (icode) (addr, op0);
10308   if (pat)
10309     emit_insn (pat);
10310   return NULL_RTX;
10311 }
10312 
10313 static rtx
altivec_expand_stv_builtin(enum insn_code icode,tree exp)10314 altivec_expand_stv_builtin (enum insn_code icode, tree exp)
10315 {
10316   tree arg0 = CALL_EXPR_ARG (exp, 0);
10317   tree arg1 = CALL_EXPR_ARG (exp, 1);
10318   tree arg2 = CALL_EXPR_ARG (exp, 2);
10319   rtx op0 = expand_normal (arg0);
10320   rtx op1 = expand_normal (arg1);
10321   rtx op2 = expand_normal (arg2);
10322   rtx pat, addr;
10323   enum machine_mode tmode = insn_data[icode].operand[0].mode;
10324   enum machine_mode smode = insn_data[icode].operand[1].mode;
10325   enum machine_mode mode1 = Pmode;
10326   enum machine_mode mode2 = Pmode;
10327 
10328   /* Invalid arguments.  Bail before doing anything stoopid!  */
10329   if (arg0 == error_mark_node
10330       || arg1 == error_mark_node
10331       || arg2 == error_mark_node)
10332     return const0_rtx;
10333 
10334   if (! (*insn_data[icode].operand[1].predicate) (op0, smode))
10335     op0 = copy_to_mode_reg (smode, op0);
10336 
10337   op2 = copy_to_mode_reg (mode2, op2);
10338 
10339   if (op1 == const0_rtx)
10340     {
10341       addr = gen_rtx_MEM (tmode, op2);
10342     }
10343   else
10344     {
10345       op1 = copy_to_mode_reg (mode1, op1);
10346       addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
10347     }
10348 
10349   pat = GEN_FCN (icode) (addr, op0);
10350   if (pat)
10351     emit_insn (pat);
10352   return NULL_RTX;
10353 }
10354 
10355 static rtx
rs6000_expand_ternop_builtin(enum insn_code icode,tree exp,rtx target)10356 rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
10357 {
10358   rtx pat;
10359   tree arg0 = CALL_EXPR_ARG (exp, 0);
10360   tree arg1 = CALL_EXPR_ARG (exp, 1);
10361   tree arg2 = CALL_EXPR_ARG (exp, 2);
10362   rtx op0 = expand_normal (arg0);
10363   rtx op1 = expand_normal (arg1);
10364   rtx op2 = expand_normal (arg2);
10365   enum machine_mode tmode = insn_data[icode].operand[0].mode;
10366   enum machine_mode mode0 = insn_data[icode].operand[1].mode;
10367   enum machine_mode mode1 = insn_data[icode].operand[2].mode;
10368   enum machine_mode mode2 = insn_data[icode].operand[3].mode;
10369 
10370   if (icode == CODE_FOR_nothing)
10371     /* Builtin not supported on this processor.  */
10372     return 0;
10373 
10374   /* If we got invalid arguments bail out before generating bad rtl.  */
10375   if (arg0 == error_mark_node
10376       || arg1 == error_mark_node
10377       || arg2 == error_mark_node)
10378     return const0_rtx;
10379 
10380   /* Check and prepare argument depending on the instruction code.
10381 
10382      Note that a switch statement instead of the sequence of tests
10383      would be incorrect as many of the CODE_FOR values could be
10384      CODE_FOR_nothing and that would yield multiple alternatives
10385      with identical values.  We'd never reach here at runtime in
10386      this case.  */
10387   if (icode == CODE_FOR_altivec_vsldoi_v4sf
10388       || icode == CODE_FOR_altivec_vsldoi_v4si
10389       || icode == CODE_FOR_altivec_vsldoi_v8hi
10390       || icode == CODE_FOR_altivec_vsldoi_v16qi)
10391     {
10392       /* Only allow 4-bit unsigned literals.  */
10393       STRIP_NOPS (arg2);
10394       if (TREE_CODE (arg2) != INTEGER_CST
10395 	  || TREE_INT_CST_LOW (arg2) & ~0xf)
10396 	{
10397 	  error ("argument 3 must be a 4-bit unsigned literal");
10398 	  return const0_rtx;
10399 	}
10400     }
10401   else if (icode == CODE_FOR_vsx_xxpermdi_v2df
10402            || icode == CODE_FOR_vsx_xxpermdi_v2di
10403            || icode == CODE_FOR_vsx_xxsldwi_v16qi
10404            || icode == CODE_FOR_vsx_xxsldwi_v8hi
10405            || icode == CODE_FOR_vsx_xxsldwi_v4si
10406            || icode == CODE_FOR_vsx_xxsldwi_v4sf
10407            || icode == CODE_FOR_vsx_xxsldwi_v2di
10408            || icode == CODE_FOR_vsx_xxsldwi_v2df)
10409     {
10410       /* Only allow 2-bit unsigned literals.  */
10411       STRIP_NOPS (arg2);
10412       if (TREE_CODE (arg2) != INTEGER_CST
10413 	  || TREE_INT_CST_LOW (arg2) & ~0x3)
10414 	{
10415 	  error ("argument 3 must be a 2-bit unsigned literal");
10416 	  return const0_rtx;
10417 	}
10418     }
10419   else if (icode == CODE_FOR_vsx_set_v2df
10420            || icode == CODE_FOR_vsx_set_v2di)
10421     {
10422       /* Only allow 1-bit unsigned literals.  */
10423       STRIP_NOPS (arg2);
10424       if (TREE_CODE (arg2) != INTEGER_CST
10425 	  || TREE_INT_CST_LOW (arg2) & ~0x1)
10426 	{
10427 	  error ("argument 3 must be a 1-bit unsigned literal");
10428 	  return const0_rtx;
10429 	}
10430     }
10431 
10432   if (target == 0
10433       || GET_MODE (target) != tmode
10434       || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10435     target = gen_reg_rtx (tmode);
10436 
10437   if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
10438     op0 = copy_to_mode_reg (mode0, op0);
10439   if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
10440     op1 = copy_to_mode_reg (mode1, op1);
10441   if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
10442     op2 = copy_to_mode_reg (mode2, op2);
10443 
10444   if (TARGET_PAIRED_FLOAT && icode == CODE_FOR_selv2sf4)
10445     pat = GEN_FCN (icode) (target, op0, op1, op2, CONST0_RTX (SFmode));
10446   else
10447     pat = GEN_FCN (icode) (target, op0, op1, op2);
10448   if (! pat)
10449     return 0;
10450   emit_insn (pat);
10451 
10452   return target;
10453 }
10454 
10455 /* Expand the lvx builtins.  */
10456 static rtx
altivec_expand_ld_builtin(tree exp,rtx target,bool * expandedp)10457 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
10458 {
10459   tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10460   unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10461   tree arg0;
10462   enum machine_mode tmode, mode0;
10463   rtx pat, op0;
10464   enum insn_code icode;
10465 
10466   switch (fcode)
10467     {
10468     case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
10469       icode = CODE_FOR_vector_altivec_load_v16qi;
10470       break;
10471     case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
10472       icode = CODE_FOR_vector_altivec_load_v8hi;
10473       break;
10474     case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
10475       icode = CODE_FOR_vector_altivec_load_v4si;
10476       break;
10477     case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
10478       icode = CODE_FOR_vector_altivec_load_v4sf;
10479       break;
10480     case ALTIVEC_BUILTIN_LD_INTERNAL_2df:
10481       icode = CODE_FOR_vector_altivec_load_v2df;
10482       break;
10483     case ALTIVEC_BUILTIN_LD_INTERNAL_2di:
10484       icode = CODE_FOR_vector_altivec_load_v2di;
10485       break;
10486     default:
10487       *expandedp = false;
10488       return NULL_RTX;
10489     }
10490 
10491   *expandedp = true;
10492 
10493   arg0 = CALL_EXPR_ARG (exp, 0);
10494   op0 = expand_normal (arg0);
10495   tmode = insn_data[icode].operand[0].mode;
10496   mode0 = insn_data[icode].operand[1].mode;
10497 
10498   if (target == 0
10499       || GET_MODE (target) != tmode
10500       || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10501     target = gen_reg_rtx (tmode);
10502 
10503   if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
10504     op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
10505 
10506   pat = GEN_FCN (icode) (target, op0);
10507   if (! pat)
10508     return 0;
10509   emit_insn (pat);
10510   return target;
10511 }
10512 
10513 /* Expand the stvx builtins.  */
10514 static rtx
altivec_expand_st_builtin(tree exp,rtx target ATTRIBUTE_UNUSED,bool * expandedp)10515 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
10516 			   bool *expandedp)
10517 {
10518   tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10519   unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10520   tree arg0, arg1;
10521   enum machine_mode mode0, mode1;
10522   rtx pat, op0, op1;
10523   enum insn_code icode;
10524 
10525   switch (fcode)
10526     {
10527     case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
10528       icode = CODE_FOR_vector_altivec_store_v16qi;
10529       break;
10530     case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
10531       icode = CODE_FOR_vector_altivec_store_v8hi;
10532       break;
10533     case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
10534       icode = CODE_FOR_vector_altivec_store_v4si;
10535       break;
10536     case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
10537       icode = CODE_FOR_vector_altivec_store_v4sf;
10538       break;
10539     case ALTIVEC_BUILTIN_ST_INTERNAL_2df:
10540       icode = CODE_FOR_vector_altivec_store_v2df;
10541       break;
10542     case ALTIVEC_BUILTIN_ST_INTERNAL_2di:
10543       icode = CODE_FOR_vector_altivec_store_v2di;
10544       break;
10545     default:
10546       *expandedp = false;
10547       return NULL_RTX;
10548     }
10549 
10550   arg0 = CALL_EXPR_ARG (exp, 0);
10551   arg1 = CALL_EXPR_ARG (exp, 1);
10552   op0 = expand_normal (arg0);
10553   op1 = expand_normal (arg1);
10554   mode0 = insn_data[icode].operand[0].mode;
10555   mode1 = insn_data[icode].operand[1].mode;
10556 
10557   if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
10558     op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
10559   if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
10560     op1 = copy_to_mode_reg (mode1, op1);
10561 
10562   pat = GEN_FCN (icode) (op0, op1);
10563   if (pat)
10564     emit_insn (pat);
10565 
10566   *expandedp = true;
10567   return NULL_RTX;
10568 }
10569 
10570 /* Expand the dst builtins.  */
10571 static rtx
altivec_expand_dst_builtin(tree exp,rtx target ATTRIBUTE_UNUSED,bool * expandedp)10572 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
10573 			    bool *expandedp)
10574 {
10575   tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10576   enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
10577   tree arg0, arg1, arg2;
10578   enum machine_mode mode0, mode1;
10579   rtx pat, op0, op1, op2;
10580   const struct builtin_description *d;
10581   size_t i;
10582 
10583   *expandedp = false;
10584 
10585   /* Handle DST variants.  */
10586   d = bdesc_dst;
10587   for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
10588     if (d->code == fcode)
10589       {
10590 	arg0 = CALL_EXPR_ARG (exp, 0);
10591 	arg1 = CALL_EXPR_ARG (exp, 1);
10592 	arg2 = CALL_EXPR_ARG (exp, 2);
10593 	op0 = expand_normal (arg0);
10594 	op1 = expand_normal (arg1);
10595 	op2 = expand_normal (arg2);
10596 	mode0 = insn_data[d->icode].operand[0].mode;
10597 	mode1 = insn_data[d->icode].operand[1].mode;
10598 
10599 	/* Invalid arguments, bail out before generating bad rtl.  */
10600 	if (arg0 == error_mark_node
10601 	    || arg1 == error_mark_node
10602 	    || arg2 == error_mark_node)
10603 	  return const0_rtx;
10604 
10605 	*expandedp = true;
10606 	STRIP_NOPS (arg2);
10607 	if (TREE_CODE (arg2) != INTEGER_CST
10608 	    || TREE_INT_CST_LOW (arg2) & ~0x3)
10609 	  {
10610 	    error ("argument to %qs must be a 2-bit unsigned literal", d->name);
10611 	    return const0_rtx;
10612 	  }
10613 
10614 	if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
10615 	  op0 = copy_to_mode_reg (Pmode, op0);
10616 	if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
10617 	  op1 = copy_to_mode_reg (mode1, op1);
10618 
10619 	pat = GEN_FCN (d->icode) (op0, op1, op2);
10620 	if (pat != 0)
10621 	  emit_insn (pat);
10622 
10623 	return NULL_RTX;
10624       }
10625 
10626   return NULL_RTX;
10627 }
10628 
10629 /* Expand vec_init builtin.  */
10630 static rtx
altivec_expand_vec_init_builtin(tree type,tree exp,rtx target)10631 altivec_expand_vec_init_builtin (tree type, tree exp, rtx target)
10632 {
10633   enum machine_mode tmode = TYPE_MODE (type);
10634   enum machine_mode inner_mode = GET_MODE_INNER (tmode);
10635   int i, n_elt = GET_MODE_NUNITS (tmode);
10636   rtvec v = rtvec_alloc (n_elt);
10637 
10638   gcc_assert (VECTOR_MODE_P (tmode));
10639   gcc_assert (n_elt == call_expr_nargs (exp));
10640 
10641   for (i = 0; i < n_elt; ++i)
10642     {
10643       rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
10644       RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
10645     }
10646 
10647   if (!target || !register_operand (target, tmode))
10648     target = gen_reg_rtx (tmode);
10649 
10650   rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
10651   return target;
10652 }
10653 
10654 /* Return the integer constant in ARG.  Constrain it to be in the range
10655    of the subparts of VEC_TYPE; issue an error if not.  */
10656 
10657 static int
get_element_number(tree vec_type,tree arg)10658 get_element_number (tree vec_type, tree arg)
10659 {
10660   unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
10661 
10662   if (!host_integerp (arg, 1)
10663       || (elt = tree_low_cst (arg, 1), elt > max))
10664     {
10665       error ("selector must be an integer constant in the range 0..%wi", max);
10666       return 0;
10667     }
10668 
10669   return elt;
10670 }
10671 
10672 /* Expand vec_set builtin.  */
10673 static rtx
altivec_expand_vec_set_builtin(tree exp)10674 altivec_expand_vec_set_builtin (tree exp)
10675 {
10676   enum machine_mode tmode, mode1;
10677   tree arg0, arg1, arg2;
10678   int elt;
10679   rtx op0, op1;
10680 
10681   arg0 = CALL_EXPR_ARG (exp, 0);
10682   arg1 = CALL_EXPR_ARG (exp, 1);
10683   arg2 = CALL_EXPR_ARG (exp, 2);
10684 
10685   tmode = TYPE_MODE (TREE_TYPE (arg0));
10686   mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
10687   gcc_assert (VECTOR_MODE_P (tmode));
10688 
10689   op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
10690   op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
10691   elt = get_element_number (TREE_TYPE (arg0), arg2);
10692 
10693   if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
10694     op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
10695 
10696   op0 = force_reg (tmode, op0);
10697   op1 = force_reg (mode1, op1);
10698 
10699   rs6000_expand_vector_set (op0, op1, elt);
10700 
10701   return op0;
10702 }
10703 
10704 /* Expand vec_ext builtin.  */
10705 static rtx
altivec_expand_vec_ext_builtin(tree exp,rtx target)10706 altivec_expand_vec_ext_builtin (tree exp, rtx target)
10707 {
10708   enum machine_mode tmode, mode0;
10709   tree arg0, arg1;
10710   int elt;
10711   rtx op0;
10712 
10713   arg0 = CALL_EXPR_ARG (exp, 0);
10714   arg1 = CALL_EXPR_ARG (exp, 1);
10715 
10716   op0 = expand_normal (arg0);
10717   elt = get_element_number (TREE_TYPE (arg0), arg1);
10718 
10719   tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
10720   mode0 = TYPE_MODE (TREE_TYPE (arg0));
10721   gcc_assert (VECTOR_MODE_P (mode0));
10722 
10723   op0 = force_reg (mode0, op0);
10724 
10725   if (optimize || !target || !register_operand (target, tmode))
10726     target = gen_reg_rtx (tmode);
10727 
10728   rs6000_expand_vector_extract (target, op0, elt);
10729 
10730   return target;
10731 }
10732 
10733 /* Expand the builtin in EXP and store the result in TARGET.  Store
10734    true in *EXPANDEDP if we found a builtin to expand.  */
10735 static rtx
altivec_expand_builtin(tree exp,rtx target,bool * expandedp)10736 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
10737 {
10738   const struct builtin_description *d;
10739   size_t i;
10740   enum insn_code icode;
10741   tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10742   tree arg0;
10743   rtx op0, pat;
10744   enum machine_mode tmode, mode0;
10745   enum rs6000_builtins fcode
10746     = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
10747 
10748   if (rs6000_overloaded_builtin_p (fcode))
10749     {
10750       *expandedp = true;
10751       error ("unresolved overload for Altivec builtin %qF", fndecl);
10752 
10753       /* Given it is invalid, just generate a normal call.  */
10754       return expand_call (exp, target, false);
10755     }
10756 
10757   target = altivec_expand_ld_builtin (exp, target, expandedp);
10758   if (*expandedp)
10759     return target;
10760 
10761   target = altivec_expand_st_builtin (exp, target, expandedp);
10762   if (*expandedp)
10763     return target;
10764 
10765   target = altivec_expand_dst_builtin (exp, target, expandedp);
10766   if (*expandedp)
10767     return target;
10768 
10769   *expandedp = true;
10770 
10771   switch (fcode)
10772     {
10773     case ALTIVEC_BUILTIN_STVX:
10774       return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si, exp);
10775     case ALTIVEC_BUILTIN_STVEBX:
10776       return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
10777     case ALTIVEC_BUILTIN_STVEHX:
10778       return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
10779     case ALTIVEC_BUILTIN_STVEWX:
10780       return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
10781     case ALTIVEC_BUILTIN_STVXL:
10782       return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, exp);
10783 
10784     case ALTIVEC_BUILTIN_STVLX:
10785       return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx, exp);
10786     case ALTIVEC_BUILTIN_STVLXL:
10787       return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl, exp);
10788     case ALTIVEC_BUILTIN_STVRX:
10789       return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx, exp);
10790     case ALTIVEC_BUILTIN_STVRXL:
10791       return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl, exp);
10792 
10793     case VSX_BUILTIN_STXVD2X_V2DF:
10794       return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df, exp);
10795     case VSX_BUILTIN_STXVD2X_V2DI:
10796       return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di, exp);
10797     case VSX_BUILTIN_STXVW4X_V4SF:
10798       return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf, exp);
10799     case VSX_BUILTIN_STXVW4X_V4SI:
10800       return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si, exp);
10801     case VSX_BUILTIN_STXVW4X_V8HI:
10802       return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi, exp);
10803     case VSX_BUILTIN_STXVW4X_V16QI:
10804       return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi, exp);
10805 
10806     case ALTIVEC_BUILTIN_MFVSCR:
10807       icode = CODE_FOR_altivec_mfvscr;
10808       tmode = insn_data[icode].operand[0].mode;
10809 
10810       if (target == 0
10811 	  || GET_MODE (target) != tmode
10812 	  || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10813 	target = gen_reg_rtx (tmode);
10814 
10815       pat = GEN_FCN (icode) (target);
10816       if (! pat)
10817 	return 0;
10818       emit_insn (pat);
10819       return target;
10820 
10821     case ALTIVEC_BUILTIN_MTVSCR:
10822       icode = CODE_FOR_altivec_mtvscr;
10823       arg0 = CALL_EXPR_ARG (exp, 0);
10824       op0 = expand_normal (arg0);
10825       mode0 = insn_data[icode].operand[0].mode;
10826 
10827       /* If we got invalid arguments bail out before generating bad rtl.  */
10828       if (arg0 == error_mark_node)
10829 	return const0_rtx;
10830 
10831       if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
10832 	op0 = copy_to_mode_reg (mode0, op0);
10833 
10834       pat = GEN_FCN (icode) (op0);
10835       if (pat)
10836 	emit_insn (pat);
10837       return NULL_RTX;
10838 
10839     case ALTIVEC_BUILTIN_DSSALL:
10840       emit_insn (gen_altivec_dssall ());
10841       return NULL_RTX;
10842 
10843     case ALTIVEC_BUILTIN_DSS:
10844       icode = CODE_FOR_altivec_dss;
10845       arg0 = CALL_EXPR_ARG (exp, 0);
10846       STRIP_NOPS (arg0);
10847       op0 = expand_normal (arg0);
10848       mode0 = insn_data[icode].operand[0].mode;
10849 
10850       /* If we got invalid arguments bail out before generating bad rtl.  */
10851       if (arg0 == error_mark_node)
10852 	return const0_rtx;
10853 
10854       if (TREE_CODE (arg0) != INTEGER_CST
10855 	  || TREE_INT_CST_LOW (arg0) & ~0x3)
10856 	{
10857 	  error ("argument to dss must be a 2-bit unsigned literal");
10858 	  return const0_rtx;
10859 	}
10860 
10861       if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
10862 	op0 = copy_to_mode_reg (mode0, op0);
10863 
10864       emit_insn (gen_altivec_dss (op0));
10865       return NULL_RTX;
10866 
10867     case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
10868     case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
10869     case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
10870     case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
10871     case VSX_BUILTIN_VEC_INIT_V2DF:
10872     case VSX_BUILTIN_VEC_INIT_V2DI:
10873       return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
10874 
10875     case ALTIVEC_BUILTIN_VEC_SET_V4SI:
10876     case ALTIVEC_BUILTIN_VEC_SET_V8HI:
10877     case ALTIVEC_BUILTIN_VEC_SET_V16QI:
10878     case ALTIVEC_BUILTIN_VEC_SET_V4SF:
10879     case VSX_BUILTIN_VEC_SET_V2DF:
10880     case VSX_BUILTIN_VEC_SET_V2DI:
10881       return altivec_expand_vec_set_builtin (exp);
10882 
10883     case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
10884     case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
10885     case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
10886     case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
10887     case VSX_BUILTIN_VEC_EXT_V2DF:
10888     case VSX_BUILTIN_VEC_EXT_V2DI:
10889       return altivec_expand_vec_ext_builtin (exp, target);
10890 
10891     default:
10892       break;
10893       /* Fall through.  */
10894     }
10895 
10896   /* Expand abs* operations.  */
10897   d = bdesc_abs;
10898   for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
10899     if (d->code == fcode)
10900       return altivec_expand_abs_builtin (d->icode, exp, target);
10901 
10902   /* Expand the AltiVec predicates.  */
10903   d = bdesc_altivec_preds;
10904   for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
10905     if (d->code == fcode)
10906       return altivec_expand_predicate_builtin (d->icode, exp, target);
10907 
10908   /* LV* are funky.  We initialized them differently.  */
10909   switch (fcode)
10910     {
10911     case ALTIVEC_BUILTIN_LVSL:
10912       return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
10913 					exp, target, false);
10914     case ALTIVEC_BUILTIN_LVSR:
10915       return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
10916 					exp, target, false);
10917     case ALTIVEC_BUILTIN_LVEBX:
10918       return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
10919 					exp, target, false);
10920     case ALTIVEC_BUILTIN_LVEHX:
10921       return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
10922 					exp, target, false);
10923     case ALTIVEC_BUILTIN_LVEWX:
10924       return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
10925 					exp, target, false);
10926     case ALTIVEC_BUILTIN_LVXL:
10927       return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
10928 					exp, target, false);
10929     case ALTIVEC_BUILTIN_LVX:
10930       return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si,
10931 					exp, target, false);
10932     case ALTIVEC_BUILTIN_LVLX:
10933       return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx,
10934 					exp, target, true);
10935     case ALTIVEC_BUILTIN_LVLXL:
10936       return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl,
10937 					exp, target, true);
10938     case ALTIVEC_BUILTIN_LVRX:
10939       return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx,
10940 					exp, target, true);
10941     case ALTIVEC_BUILTIN_LVRXL:
10942       return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl,
10943 					exp, target, true);
10944     case VSX_BUILTIN_LXVD2X_V2DF:
10945       return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df,
10946 					exp, target, false);
10947     case VSX_BUILTIN_LXVD2X_V2DI:
10948       return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di,
10949 					exp, target, false);
10950     case VSX_BUILTIN_LXVW4X_V4SF:
10951       return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf,
10952 					exp, target, false);
10953     case VSX_BUILTIN_LXVW4X_V4SI:
10954       return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si,
10955 					exp, target, false);
10956     case VSX_BUILTIN_LXVW4X_V8HI:
10957       return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi,
10958 					exp, target, false);
10959     case VSX_BUILTIN_LXVW4X_V16QI:
10960       return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi,
10961 					exp, target, false);
10962       break;
10963     default:
10964       break;
10965       /* Fall through.  */
10966     }
10967 
10968   *expandedp = false;
10969   return NULL_RTX;
10970 }
10971 
10972 /* Expand the builtin in EXP and store the result in TARGET.  Store
10973    true in *EXPANDEDP if we found a builtin to expand.  */
10974 static rtx
paired_expand_builtin(tree exp,rtx target,bool * expandedp)10975 paired_expand_builtin (tree exp, rtx target, bool * expandedp)
10976 {
10977   tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10978   enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
10979   const struct builtin_description *d;
10980   size_t i;
10981 
10982   *expandedp = true;
10983 
10984   switch (fcode)
10985     {
10986     case PAIRED_BUILTIN_STX:
10987       return paired_expand_stv_builtin (CODE_FOR_paired_stx, exp);
10988     case PAIRED_BUILTIN_LX:
10989       return paired_expand_lv_builtin (CODE_FOR_paired_lx, exp, target);
10990     default:
10991       break;
10992       /* Fall through.  */
10993     }
10994 
10995   /* Expand the paired predicates.  */
10996   d = bdesc_paired_preds;
10997   for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); i++, d++)
10998     if (d->code == fcode)
10999       return paired_expand_predicate_builtin (d->icode, exp, target);
11000 
11001   *expandedp = false;
11002   return NULL_RTX;
11003 }
11004 
11005 /* Binops that need to be initialized manually, but can be expanded
11006    automagically by rs6000_expand_binop_builtin.  */
11007 static const struct builtin_description bdesc_2arg_spe[] =
11008 {
11009   { RS6000_BTM_SPE, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
11010   { RS6000_BTM_SPE, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
11011   { RS6000_BTM_SPE, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
11012   { RS6000_BTM_SPE, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
11013   { RS6000_BTM_SPE, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
11014   { RS6000_BTM_SPE, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
11015   { RS6000_BTM_SPE, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
11016   { RS6000_BTM_SPE, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
11017   { RS6000_BTM_SPE, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
11018   { RS6000_BTM_SPE, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
11019   { RS6000_BTM_SPE, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
11020   { RS6000_BTM_SPE, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
11021   { RS6000_BTM_SPE, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
11022   { RS6000_BTM_SPE, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
11023   { RS6000_BTM_SPE, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
11024   { RS6000_BTM_SPE, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
11025   { RS6000_BTM_SPE, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
11026   { RS6000_BTM_SPE, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
11027   { RS6000_BTM_SPE, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
11028   { RS6000_BTM_SPE, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
11029   { RS6000_BTM_SPE, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
11030   { RS6000_BTM_SPE, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
11031 };
11032 
11033 /* Expand the builtin in EXP and store the result in TARGET.  Store
11034    true in *EXPANDEDP if we found a builtin to expand.
11035 
11036    This expands the SPE builtins that are not simple unary and binary
11037    operations.  */
11038 static rtx
spe_expand_builtin(tree exp,rtx target,bool * expandedp)11039 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
11040 {
11041   tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
11042   tree arg1, arg0;
11043   enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
11044   enum insn_code icode;
11045   enum machine_mode tmode, mode0;
11046   rtx pat, op0;
11047   const struct builtin_description *d;
11048   size_t i;
11049 
11050   *expandedp = true;
11051 
11052   /* Syntax check for a 5-bit unsigned immediate.  */
11053   switch (fcode)
11054     {
11055     case SPE_BUILTIN_EVSTDD:
11056     case SPE_BUILTIN_EVSTDH:
11057     case SPE_BUILTIN_EVSTDW:
11058     case SPE_BUILTIN_EVSTWHE:
11059     case SPE_BUILTIN_EVSTWHO:
11060     case SPE_BUILTIN_EVSTWWE:
11061     case SPE_BUILTIN_EVSTWWO:
11062       arg1 = CALL_EXPR_ARG (exp, 2);
11063       if (TREE_CODE (arg1) != INTEGER_CST
11064 	  || TREE_INT_CST_LOW (arg1) & ~0x1f)
11065 	{
11066 	  error ("argument 2 must be a 5-bit unsigned literal");
11067 	  return const0_rtx;
11068 	}
11069       break;
11070     default:
11071       break;
11072     }
11073 
11074   /* The evsplat*i instructions are not quite generic.  */
11075   switch (fcode)
11076     {
11077     case SPE_BUILTIN_EVSPLATFI:
11078       return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
11079 					 exp, target);
11080     case SPE_BUILTIN_EVSPLATI:
11081       return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
11082 					 exp, target);
11083     default:
11084       break;
11085     }
11086 
11087   d = bdesc_2arg_spe;
11088   for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
11089     if (d->code == fcode)
11090       return rs6000_expand_binop_builtin (d->icode, exp, target);
11091 
11092   d = bdesc_spe_predicates;
11093   for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
11094     if (d->code == fcode)
11095       return spe_expand_predicate_builtin (d->icode, exp, target);
11096 
11097   d = bdesc_spe_evsel;
11098   for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
11099     if (d->code == fcode)
11100       return spe_expand_evsel_builtin (d->icode, exp, target);
11101 
11102   switch (fcode)
11103     {
11104     case SPE_BUILTIN_EVSTDDX:
11105       return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, exp);
11106     case SPE_BUILTIN_EVSTDHX:
11107       return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, exp);
11108     case SPE_BUILTIN_EVSTDWX:
11109       return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, exp);
11110     case SPE_BUILTIN_EVSTWHEX:
11111       return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, exp);
11112     case SPE_BUILTIN_EVSTWHOX:
11113       return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, exp);
11114     case SPE_BUILTIN_EVSTWWEX:
11115       return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, exp);
11116     case SPE_BUILTIN_EVSTWWOX:
11117       return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, exp);
11118     case SPE_BUILTIN_EVSTDD:
11119       return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, exp);
11120     case SPE_BUILTIN_EVSTDH:
11121       return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, exp);
11122     case SPE_BUILTIN_EVSTDW:
11123       return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, exp);
11124     case SPE_BUILTIN_EVSTWHE:
11125       return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, exp);
11126     case SPE_BUILTIN_EVSTWHO:
11127       return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, exp);
11128     case SPE_BUILTIN_EVSTWWE:
11129       return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, exp);
11130     case SPE_BUILTIN_EVSTWWO:
11131       return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, exp);
11132     case SPE_BUILTIN_MFSPEFSCR:
11133       icode = CODE_FOR_spe_mfspefscr;
11134       tmode = insn_data[icode].operand[0].mode;
11135 
11136       if (target == 0
11137 	  || GET_MODE (target) != tmode
11138 	  || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11139 	target = gen_reg_rtx (tmode);
11140 
11141       pat = GEN_FCN (icode) (target);
11142       if (! pat)
11143 	return 0;
11144       emit_insn (pat);
11145       return target;
11146     case SPE_BUILTIN_MTSPEFSCR:
11147       icode = CODE_FOR_spe_mtspefscr;
11148       arg0 = CALL_EXPR_ARG (exp, 0);
11149       op0 = expand_normal (arg0);
11150       mode0 = insn_data[icode].operand[0].mode;
11151 
11152       if (arg0 == error_mark_node)
11153 	return const0_rtx;
11154 
11155       if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
11156 	op0 = copy_to_mode_reg (mode0, op0);
11157 
11158       pat = GEN_FCN (icode) (op0);
11159       if (pat)
11160 	emit_insn (pat);
11161       return NULL_RTX;
11162     default:
11163       break;
11164     }
11165 
11166   *expandedp = false;
11167   return NULL_RTX;
11168 }
11169 
11170 static rtx
paired_expand_predicate_builtin(enum insn_code icode,tree exp,rtx target)11171 paired_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
11172 {
11173   rtx pat, scratch, tmp;
11174   tree form = CALL_EXPR_ARG (exp, 0);
11175   tree arg0 = CALL_EXPR_ARG (exp, 1);
11176   tree arg1 = CALL_EXPR_ARG (exp, 2);
11177   rtx op0 = expand_normal (arg0);
11178   rtx op1 = expand_normal (arg1);
11179   enum machine_mode mode0 = insn_data[icode].operand[1].mode;
11180   enum machine_mode mode1 = insn_data[icode].operand[2].mode;
11181   int form_int;
11182   enum rtx_code code;
11183 
11184   if (TREE_CODE (form) != INTEGER_CST)
11185     {
11186       error ("argument 1 of __builtin_paired_predicate must be a constant");
11187       return const0_rtx;
11188     }
11189   else
11190     form_int = TREE_INT_CST_LOW (form);
11191 
11192   gcc_assert (mode0 == mode1);
11193 
11194   if (arg0 == error_mark_node || arg1 == error_mark_node)
11195     return const0_rtx;
11196 
11197   if (target == 0
11198       || GET_MODE (target) != SImode
11199       || !(*insn_data[icode].operand[0].predicate) (target, SImode))
11200     target = gen_reg_rtx (SImode);
11201   if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
11202     op0 = copy_to_mode_reg (mode0, op0);
11203   if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
11204     op1 = copy_to_mode_reg (mode1, op1);
11205 
11206   scratch = gen_reg_rtx (CCFPmode);
11207 
11208   pat = GEN_FCN (icode) (scratch, op0, op1);
11209   if (!pat)
11210     return const0_rtx;
11211 
11212   emit_insn (pat);
11213 
11214   switch (form_int)
11215     {
11216       /* LT bit.  */
11217     case 0:
11218       code = LT;
11219       break;
11220       /* GT bit.  */
11221     case 1:
11222       code = GT;
11223       break;
11224       /* EQ bit.  */
11225     case 2:
11226       code = EQ;
11227       break;
11228       /* UN bit.  */
11229     case 3:
11230       emit_insn (gen_move_from_CR_ov_bit (target, scratch));
11231       return target;
11232     default:
11233       error ("argument 1 of __builtin_paired_predicate is out of range");
11234       return const0_rtx;
11235     }
11236 
11237   tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
11238   emit_move_insn (target, tmp);
11239   return target;
11240 }
11241 
11242 static rtx
spe_expand_predicate_builtin(enum insn_code icode,tree exp,rtx target)11243 spe_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
11244 {
11245   rtx pat, scratch, tmp;
11246   tree form = CALL_EXPR_ARG (exp, 0);
11247   tree arg0 = CALL_EXPR_ARG (exp, 1);
11248   tree arg1 = CALL_EXPR_ARG (exp, 2);
11249   rtx op0 = expand_normal (arg0);
11250   rtx op1 = expand_normal (arg1);
11251   enum machine_mode mode0 = insn_data[icode].operand[1].mode;
11252   enum machine_mode mode1 = insn_data[icode].operand[2].mode;
11253   int form_int;
11254   enum rtx_code code;
11255 
11256   if (TREE_CODE (form) != INTEGER_CST)
11257     {
11258       error ("argument 1 of __builtin_spe_predicate must be a constant");
11259       return const0_rtx;
11260     }
11261   else
11262     form_int = TREE_INT_CST_LOW (form);
11263 
11264   gcc_assert (mode0 == mode1);
11265 
11266   if (arg0 == error_mark_node || arg1 == error_mark_node)
11267     return const0_rtx;
11268 
11269   if (target == 0
11270       || GET_MODE (target) != SImode
11271       || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
11272     target = gen_reg_rtx (SImode);
11273 
11274   if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
11275     op0 = copy_to_mode_reg (mode0, op0);
11276   if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
11277     op1 = copy_to_mode_reg (mode1, op1);
11278 
11279   scratch = gen_reg_rtx (CCmode);
11280 
11281   pat = GEN_FCN (icode) (scratch, op0, op1);
11282   if (! pat)
11283     return const0_rtx;
11284   emit_insn (pat);
11285 
11286   /* There are 4 variants for each predicate: _any_, _all_, _upper_,
11287      _lower_.  We use one compare, but look in different bits of the
11288      CR for each variant.
11289 
11290      There are 2 elements in each SPE simd type (upper/lower).  The CR
11291      bits are set as follows:
11292 
11293      BIT0  | BIT 1  | BIT 2   | BIT 3
11294      U     |   L    | (U | L) | (U & L)
11295 
11296      So, for an "all" relationship, BIT 3 would be set.
11297      For an "any" relationship, BIT 2 would be set.  Etc.
11298 
11299      Following traditional nomenclature, these bits map to:
11300 
11301      BIT0  | BIT 1  | BIT 2   | BIT 3
11302      LT    | GT     | EQ      | OV
11303 
11304      Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
11305   */
11306 
11307   switch (form_int)
11308     {
11309       /* All variant.  OV bit.  */
11310     case 0:
11311       /* We need to get to the OV bit, which is the ORDERED bit.  We
11312 	 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
11313 	 that's ugly and will make validate_condition_mode die.
11314 	 So let's just use another pattern.  */
11315       emit_insn (gen_move_from_CR_ov_bit (target, scratch));
11316       return target;
11317       /* Any variant.  EQ bit.  */
11318     case 1:
11319       code = EQ;
11320       break;
11321       /* Upper variant.  LT bit.  */
11322     case 2:
11323       code = LT;
11324       break;
11325       /* Lower variant.  GT bit.  */
11326     case 3:
11327       code = GT;
11328       break;
11329     default:
11330       error ("argument 1 of __builtin_spe_predicate is out of range");
11331       return const0_rtx;
11332     }
11333 
11334   tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
11335   emit_move_insn (target, tmp);
11336 
11337   return target;
11338 }
11339 
11340 /* The evsel builtins look like this:
11341 
11342      e = __builtin_spe_evsel_OP (a, b, c, d);
11343 
11344    and work like this:
11345 
11346      e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
11347      e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
11348 */
11349 
11350 static rtx
spe_expand_evsel_builtin(enum insn_code icode,tree exp,rtx target)11351 spe_expand_evsel_builtin (enum insn_code icode, tree exp, rtx target)
11352 {
11353   rtx pat, scratch;
11354   tree arg0 = CALL_EXPR_ARG (exp, 0);
11355   tree arg1 = CALL_EXPR_ARG (exp, 1);
11356   tree arg2 = CALL_EXPR_ARG (exp, 2);
11357   tree arg3 = CALL_EXPR_ARG (exp, 3);
11358   rtx op0 = expand_normal (arg0);
11359   rtx op1 = expand_normal (arg1);
11360   rtx op2 = expand_normal (arg2);
11361   rtx op3 = expand_normal (arg3);
11362   enum machine_mode mode0 = insn_data[icode].operand[1].mode;
11363   enum machine_mode mode1 = insn_data[icode].operand[2].mode;
11364 
11365   gcc_assert (mode0 == mode1);
11366 
11367   if (arg0 == error_mark_node || arg1 == error_mark_node
11368       || arg2 == error_mark_node || arg3 == error_mark_node)
11369     return const0_rtx;
11370 
11371   if (target == 0
11372       || GET_MODE (target) != mode0
11373       || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
11374     target = gen_reg_rtx (mode0);
11375 
11376   if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
11377     op0 = copy_to_mode_reg (mode0, op0);
11378   if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
11379     op1 = copy_to_mode_reg (mode0, op1);
11380   if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
11381     op2 = copy_to_mode_reg (mode0, op2);
11382   if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
11383     op3 = copy_to_mode_reg (mode0, op3);
11384 
11385   /* Generate the compare.  */
11386   scratch = gen_reg_rtx (CCmode);
11387   pat = GEN_FCN (icode) (scratch, op0, op1);
11388   if (! pat)
11389     return const0_rtx;
11390   emit_insn (pat);
11391 
11392   if (mode0 == V2SImode)
11393     emit_insn (gen_spe_evsel (target, op2, op3, scratch));
11394   else
11395     emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
11396 
11397   return target;
11398 }
11399 
11400 /* Raise an error message for a builtin function that is called without the
11401    appropriate target options being set.  */
11402 
11403 static void
rs6000_invalid_builtin(enum rs6000_builtins fncode)11404 rs6000_invalid_builtin (enum rs6000_builtins fncode)
11405 {
11406   size_t uns_fncode = (size_t)fncode;
11407   const char *name = rs6000_builtin_info[uns_fncode].name;
11408   HOST_WIDE_INT fnmask = rs6000_builtin_info[uns_fncode].mask;
11409 
11410   gcc_assert (name != NULL);
11411   if ((fnmask & RS6000_BTM_CELL) != 0)
11412     error ("Builtin function %s is only valid for the cell processor", name);
11413   else if ((fnmask & RS6000_BTM_VSX) != 0)
11414     error ("Builtin function %s requires the -mvsx option", name);
11415   else if ((fnmask & RS6000_BTM_ALTIVEC) != 0)
11416     error ("Builtin function %s requires the -maltivec option", name);
11417   else if ((fnmask & RS6000_BTM_PAIRED) != 0)
11418     error ("Builtin function %s requires the -mpaired option", name);
11419   else if ((fnmask & RS6000_BTM_SPE) != 0)
11420     error ("Builtin function %s requires the -mspe option", name);
11421   else
11422     error ("Builtin function %s is not supported with the current options",
11423 	   name);
11424 }
11425 
11426 /* Expand an expression EXP that calls a built-in function,
11427    with result going to TARGET if that's convenient
11428    (and in mode MODE if that's convenient).
11429    SUBTARGET may be used as the target for computing one of EXP's operands.
11430    IGNORE is nonzero if the value is to be ignored.  */
11431 
11432 static rtx
rs6000_expand_builtin(tree exp,rtx target,rtx subtarget ATTRIBUTE_UNUSED,enum machine_mode mode ATTRIBUTE_UNUSED,int ignore ATTRIBUTE_UNUSED)11433 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
11434 		       enum machine_mode mode ATTRIBUTE_UNUSED,
11435 		       int ignore ATTRIBUTE_UNUSED)
11436 {
11437   tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
11438   enum rs6000_builtins fcode
11439     = (enum rs6000_builtins)DECL_FUNCTION_CODE (fndecl);
11440   size_t uns_fcode = (size_t)fcode;
11441   const struct builtin_description *d;
11442   size_t i;
11443   rtx ret;
11444   bool success;
11445   HOST_WIDE_INT mask = rs6000_builtin_info[uns_fcode].mask;
11446   bool func_valid_p = ((rs6000_builtin_mask & mask) == mask);
11447 
11448   if (TARGET_DEBUG_BUILTIN)
11449     {
11450       enum insn_code icode = rs6000_builtin_info[uns_fcode].icode;
11451       const char *name1 = rs6000_builtin_info[uns_fcode].name;
11452       const char *name2 = ((icode != CODE_FOR_nothing)
11453 			   ? get_insn_name ((int)icode)
11454 			   : "nothing");
11455       const char *name3;
11456 
11457       switch (rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK)
11458 	{
11459 	default:		   name3 = "unknown";	break;
11460 	case RS6000_BTC_SPECIAL:   name3 = "special";	break;
11461 	case RS6000_BTC_UNARY:	   name3 = "unary";	break;
11462 	case RS6000_BTC_BINARY:	   name3 = "binary";	break;
11463 	case RS6000_BTC_TERNARY:   name3 = "ternary";	break;
11464 	case RS6000_BTC_PREDICATE: name3 = "predicate";	break;
11465 	case RS6000_BTC_ABS:	   name3 = "abs";	break;
11466 	case RS6000_BTC_EVSEL:	   name3 = "evsel";	break;
11467 	case RS6000_BTC_DST:	   name3 = "dst";	break;
11468 	}
11469 
11470 
11471       fprintf (stderr,
11472 	       "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
11473 	       (name1) ? name1 : "---", fcode,
11474 	       (name2) ? name2 : "---", (int)icode,
11475 	       name3,
11476 	       func_valid_p ? "" : ", not valid");
11477     }
11478 
11479   if (!func_valid_p)
11480     {
11481       rs6000_invalid_builtin (fcode);
11482 
11483       /* Given it is invalid, just generate a normal call.  */
11484       return expand_call (exp, target, ignore);
11485     }
11486 
11487   switch (fcode)
11488     {
11489     case RS6000_BUILTIN_RECIP:
11490       return rs6000_expand_binop_builtin (CODE_FOR_recipdf3, exp, target);
11491 
11492     case RS6000_BUILTIN_RECIPF:
11493       return rs6000_expand_binop_builtin (CODE_FOR_recipsf3, exp, target);
11494 
11495     case RS6000_BUILTIN_RSQRTF:
11496       return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2, exp, target);
11497 
11498     case RS6000_BUILTIN_RSQRT:
11499       return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2, exp, target);
11500 
11501     case POWER7_BUILTIN_BPERMD:
11502       return rs6000_expand_binop_builtin (((TARGET_64BIT)
11503 					   ? CODE_FOR_bpermd_di
11504 					   : CODE_FOR_bpermd_si), exp, target);
11505 
11506     case RS6000_BUILTIN_GET_TB:
11507       return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase,
11508 					   target);
11509 
11510     case RS6000_BUILTIN_MFTB:
11511       return rs6000_expand_zeroop_builtin (((TARGET_64BIT)
11512 					    ? CODE_FOR_rs6000_mftb_di
11513 					    : CODE_FOR_rs6000_mftb_si),
11514 					   target);
11515 
11516     case ALTIVEC_BUILTIN_MASK_FOR_LOAD:
11517     case ALTIVEC_BUILTIN_MASK_FOR_STORE:
11518       {
11519 	int icode = (int) CODE_FOR_altivec_lvsr;
11520 	enum machine_mode tmode = insn_data[icode].operand[0].mode;
11521 	enum machine_mode mode = insn_data[icode].operand[1].mode;
11522 	tree arg;
11523 	rtx op, addr, pat;
11524 
11525 	gcc_assert (TARGET_ALTIVEC);
11526 
11527 	arg = CALL_EXPR_ARG (exp, 0);
11528 	gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg)));
11529 	op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
11530 	addr = memory_address (mode, op);
11531 	if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
11532 	  op = addr;
11533 	else
11534 	  {
11535 	    /* For the load case need to negate the address.  */
11536 	    op = gen_reg_rtx (GET_MODE (addr));
11537 	    emit_insn (gen_rtx_SET (VOIDmode, op,
11538 				    gen_rtx_NEG (GET_MODE (addr), addr)));
11539 	  }
11540 	op = gen_rtx_MEM (mode, op);
11541 
11542 	if (target == 0
11543 	    || GET_MODE (target) != tmode
11544 	    || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11545 	  target = gen_reg_rtx (tmode);
11546 
11547 	/*pat = gen_altivec_lvsr (target, op);*/
11548 	pat = GEN_FCN (icode) (target, op);
11549 	if (!pat)
11550 	  return 0;
11551 	emit_insn (pat);
11552 
11553 	return target;
11554       }
11555 
11556     case ALTIVEC_BUILTIN_VCFUX:
11557     case ALTIVEC_BUILTIN_VCFSX:
11558     case ALTIVEC_BUILTIN_VCTUXS:
11559     case ALTIVEC_BUILTIN_VCTSXS:
11560   /* FIXME: There's got to be a nicer way to handle this case than
11561      constructing a new CALL_EXPR.  */
11562       if (call_expr_nargs (exp) == 1)
11563 	{
11564 	  exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp),
11565 				 2, CALL_EXPR_ARG (exp, 0), integer_zero_node);
11566 	}
11567       break;
11568 
11569     default:
11570       break;
11571     }
11572 
11573   if (TARGET_ALTIVEC)
11574     {
11575       ret = altivec_expand_builtin (exp, target, &success);
11576 
11577       if (success)
11578 	return ret;
11579     }
11580   if (TARGET_SPE)
11581     {
11582       ret = spe_expand_builtin (exp, target, &success);
11583 
11584       if (success)
11585 	return ret;
11586     }
11587   if (TARGET_PAIRED_FLOAT)
11588     {
11589       ret = paired_expand_builtin (exp, target, &success);
11590 
11591       if (success)
11592 	return ret;
11593     }
11594 
11595   gcc_assert (TARGET_ALTIVEC || TARGET_VSX || TARGET_SPE || TARGET_PAIRED_FLOAT);
11596 
11597   /* Handle simple unary operations.  */
11598   d = bdesc_1arg;
11599   for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
11600     if (d->code == fcode)
11601       return rs6000_expand_unop_builtin (d->icode, exp, target);
11602 
11603   /* Handle simple binary operations.  */
11604   d = bdesc_2arg;
11605   for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
11606     if (d->code == fcode)
11607       return rs6000_expand_binop_builtin (d->icode, exp, target);
11608 
11609   /* Handle simple ternary operations.  */
11610   d = bdesc_3arg;
11611   for (i = 0; i < ARRAY_SIZE  (bdesc_3arg); i++, d++)
11612     if (d->code == fcode)
11613       return rs6000_expand_ternop_builtin (d->icode, exp, target);
11614 
11615   gcc_unreachable ();
11616 }
11617 
11618 static void
rs6000_init_builtins(void)11619 rs6000_init_builtins (void)
11620 {
11621   tree tdecl;
11622   tree ftype;
11623   enum machine_mode mode;
11624 
11625   if (TARGET_DEBUG_BUILTIN)
11626     fprintf (stderr, "rs6000_init_builtins%s%s%s%s\n",
11627 	     (TARGET_PAIRED_FLOAT) ? ", paired"	 : "",
11628 	     (TARGET_SPE)	   ? ", spe"	 : "",
11629 	     (TARGET_ALTIVEC)	   ? ", altivec" : "",
11630 	     (TARGET_VSX)	   ? ", vsx"	 : "");
11631 
11632   V2SI_type_node = build_vector_type (intSI_type_node, 2);
11633   V2SF_type_node = build_vector_type (float_type_node, 2);
11634   V2DI_type_node = build_vector_type (intDI_type_node, 2);
11635   V2DF_type_node = build_vector_type (double_type_node, 2);
11636   V4HI_type_node = build_vector_type (intHI_type_node, 4);
11637   V4SI_type_node = build_vector_type (intSI_type_node, 4);
11638   V4SF_type_node = build_vector_type (float_type_node, 4);
11639   V8HI_type_node = build_vector_type (intHI_type_node, 8);
11640   V16QI_type_node = build_vector_type (intQI_type_node, 16);
11641 
11642   unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
11643   unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
11644   unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
11645   unsigned_V2DI_type_node = build_vector_type (unsigned_intDI_type_node, 2);
11646 
11647   opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
11648   opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
11649   opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
11650   opaque_V4SI_type_node = build_opaque_vector_type (intSI_type_node, 4);
11651 
11652   /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
11653      types, especially in C++ land.  Similarly, 'vector pixel' is distinct from
11654      'vector unsigned short'.  */
11655 
11656   bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
11657   bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
11658   bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
11659   bool_long_type_node = build_distinct_type_copy (unsigned_intDI_type_node);
11660   pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
11661 
11662   long_integer_type_internal_node = long_integer_type_node;
11663   long_unsigned_type_internal_node = long_unsigned_type_node;
11664   long_long_integer_type_internal_node = long_long_integer_type_node;
11665   long_long_unsigned_type_internal_node = long_long_unsigned_type_node;
11666   intQI_type_internal_node = intQI_type_node;
11667   uintQI_type_internal_node = unsigned_intQI_type_node;
11668   intHI_type_internal_node = intHI_type_node;
11669   uintHI_type_internal_node = unsigned_intHI_type_node;
11670   intSI_type_internal_node = intSI_type_node;
11671   uintSI_type_internal_node = unsigned_intSI_type_node;
11672   intDI_type_internal_node = intDI_type_node;
11673   uintDI_type_internal_node = unsigned_intDI_type_node;
11674   float_type_internal_node = float_type_node;
11675   double_type_internal_node = double_type_node;
11676   void_type_internal_node = void_type_node;
11677 
11678   /* Initialize the modes for builtin_function_type, mapping a machine mode to
11679      tree type node.  */
11680   builtin_mode_to_type[QImode][0] = integer_type_node;
11681   builtin_mode_to_type[HImode][0] = integer_type_node;
11682   builtin_mode_to_type[SImode][0] = intSI_type_node;
11683   builtin_mode_to_type[SImode][1] = unsigned_intSI_type_node;
11684   builtin_mode_to_type[DImode][0] = intDI_type_node;
11685   builtin_mode_to_type[DImode][1] = unsigned_intDI_type_node;
11686   builtin_mode_to_type[SFmode][0] = float_type_node;
11687   builtin_mode_to_type[DFmode][0] = double_type_node;
11688   builtin_mode_to_type[V2SImode][0] = V2SI_type_node;
11689   builtin_mode_to_type[V2SFmode][0] = V2SF_type_node;
11690   builtin_mode_to_type[V2DImode][0] = V2DI_type_node;
11691   builtin_mode_to_type[V2DImode][1] = unsigned_V2DI_type_node;
11692   builtin_mode_to_type[V2DFmode][0] = V2DF_type_node;
11693   builtin_mode_to_type[V4HImode][0] = V4HI_type_node;
11694   builtin_mode_to_type[V4SImode][0] = V4SI_type_node;
11695   builtin_mode_to_type[V4SImode][1] = unsigned_V4SI_type_node;
11696   builtin_mode_to_type[V4SFmode][0] = V4SF_type_node;
11697   builtin_mode_to_type[V8HImode][0] = V8HI_type_node;
11698   builtin_mode_to_type[V8HImode][1] = unsigned_V8HI_type_node;
11699   builtin_mode_to_type[V16QImode][0] = V16QI_type_node;
11700   builtin_mode_to_type[V16QImode][1] = unsigned_V16QI_type_node;
11701 
11702   tdecl = add_builtin_type ("__bool char", bool_char_type_node);
11703   TYPE_NAME (bool_char_type_node) = tdecl;
11704 
11705   tdecl = add_builtin_type ("__bool short", bool_short_type_node);
11706   TYPE_NAME (bool_short_type_node) = tdecl;
11707 
11708   tdecl = add_builtin_type ("__bool int", bool_int_type_node);
11709   TYPE_NAME (bool_int_type_node) = tdecl;
11710 
11711   tdecl = add_builtin_type ("__pixel", pixel_type_node);
11712   TYPE_NAME (pixel_type_node) = tdecl;
11713 
11714   bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
11715   bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
11716   bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
11717   bool_V2DI_type_node = build_vector_type (bool_long_type_node, 2);
11718   pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
11719 
11720   tdecl = add_builtin_type ("__vector unsigned char", unsigned_V16QI_type_node);
11721   TYPE_NAME (unsigned_V16QI_type_node) = tdecl;
11722 
11723   tdecl = add_builtin_type ("__vector signed char", V16QI_type_node);
11724   TYPE_NAME (V16QI_type_node) = tdecl;
11725 
11726   tdecl = add_builtin_type ("__vector __bool char", bool_V16QI_type_node);
11727   TYPE_NAME ( bool_V16QI_type_node) = tdecl;
11728 
11729   tdecl = add_builtin_type ("__vector unsigned short", unsigned_V8HI_type_node);
11730   TYPE_NAME (unsigned_V8HI_type_node) = tdecl;
11731 
11732   tdecl = add_builtin_type ("__vector signed short", V8HI_type_node);
11733   TYPE_NAME (V8HI_type_node) = tdecl;
11734 
11735   tdecl = add_builtin_type ("__vector __bool short", bool_V8HI_type_node);
11736   TYPE_NAME (bool_V8HI_type_node) = tdecl;
11737 
11738   tdecl = add_builtin_type ("__vector unsigned int", unsigned_V4SI_type_node);
11739   TYPE_NAME (unsigned_V4SI_type_node) = tdecl;
11740 
11741   tdecl = add_builtin_type ("__vector signed int", V4SI_type_node);
11742   TYPE_NAME (V4SI_type_node) = tdecl;
11743 
11744   tdecl = add_builtin_type ("__vector __bool int", bool_V4SI_type_node);
11745   TYPE_NAME (bool_V4SI_type_node) = tdecl;
11746 
11747   tdecl = add_builtin_type ("__vector float", V4SF_type_node);
11748   TYPE_NAME (V4SF_type_node) = tdecl;
11749 
11750   tdecl = add_builtin_type ("__vector __pixel", pixel_V8HI_type_node);
11751   TYPE_NAME (pixel_V8HI_type_node) = tdecl;
11752 
11753   tdecl = add_builtin_type ("__vector double", V2DF_type_node);
11754   TYPE_NAME (V2DF_type_node) = tdecl;
11755 
11756   tdecl = add_builtin_type ("__vector long", V2DI_type_node);
11757   TYPE_NAME (V2DI_type_node) = tdecl;
11758 
11759   tdecl = add_builtin_type ("__vector unsigned long", unsigned_V2DI_type_node);
11760   TYPE_NAME (unsigned_V2DI_type_node) = tdecl;
11761 
11762   tdecl = add_builtin_type ("__vector __bool long", bool_V2DI_type_node);
11763   TYPE_NAME (bool_V2DI_type_node) = tdecl;
11764 
11765   /* Paired and SPE builtins are only available if you build a compiler with
11766      the appropriate options, so only create those builtins with the
11767      appropriate compiler option.  Create Altivec and VSX builtins on machines
11768      with at least the general purpose extensions (970 and newer) to allow the
11769      use of the target attribute.  */
11770   if (TARGET_PAIRED_FLOAT)
11771     paired_init_builtins ();
11772   if (TARGET_SPE)
11773     spe_init_builtins ();
11774   if (TARGET_EXTRA_BUILTINS)
11775     altivec_init_builtins ();
11776   if (TARGET_EXTRA_BUILTINS || TARGET_SPE || TARGET_PAIRED_FLOAT)
11777     rs6000_common_init_builtins ();
11778 
11779   ftype = builtin_function_type (DFmode, DFmode, DFmode, VOIDmode,
11780 				 RS6000_BUILTIN_RECIP, "__builtin_recipdiv");
11781   def_builtin ("__builtin_recipdiv", ftype, RS6000_BUILTIN_RECIP);
11782 
11783   ftype = builtin_function_type (SFmode, SFmode, SFmode, VOIDmode,
11784 				 RS6000_BUILTIN_RECIPF, "__builtin_recipdivf");
11785   def_builtin ("__builtin_recipdivf", ftype, RS6000_BUILTIN_RECIPF);
11786 
11787   ftype = builtin_function_type (DFmode, DFmode, VOIDmode, VOIDmode,
11788 				 RS6000_BUILTIN_RSQRT, "__builtin_rsqrt");
11789   def_builtin ("__builtin_rsqrt", ftype, RS6000_BUILTIN_RSQRT);
11790 
11791   ftype = builtin_function_type (SFmode, SFmode, VOIDmode, VOIDmode,
11792 				 RS6000_BUILTIN_RSQRTF, "__builtin_rsqrtf");
11793   def_builtin ("__builtin_rsqrtf", ftype, RS6000_BUILTIN_RSQRTF);
11794 
11795   mode = (TARGET_64BIT) ? DImode : SImode;
11796   ftype = builtin_function_type (mode, mode, mode, VOIDmode,
11797 				 POWER7_BUILTIN_BPERMD, "__builtin_bpermd");
11798   def_builtin ("__builtin_bpermd", ftype, POWER7_BUILTIN_BPERMD);
11799 
11800   ftype = build_function_type_list (unsigned_intDI_type_node,
11801 				    NULL_TREE);
11802   def_builtin ("__builtin_ppc_get_timebase", ftype, RS6000_BUILTIN_GET_TB);
11803 
11804   if (TARGET_64BIT)
11805     ftype = build_function_type_list (unsigned_intDI_type_node,
11806 				      NULL_TREE);
11807   else
11808     ftype = build_function_type_list (unsigned_intSI_type_node,
11809 				      NULL_TREE);
11810   def_builtin ("__builtin_ppc_mftb", ftype, RS6000_BUILTIN_MFTB);
11811 
11812 #if TARGET_XCOFF
11813   /* AIX libm provides clog as __clog.  */
11814   if ((tdecl = builtin_decl_explicit (BUILT_IN_CLOG)) != NULL_TREE)
11815     set_user_assembler_name (tdecl, "__clog");
11816 #endif
11817 
11818 #ifdef SUBTARGET_INIT_BUILTINS
11819   SUBTARGET_INIT_BUILTINS;
11820 #endif
11821 }
11822 
11823 /* Returns the rs6000 builtin decl for CODE.  */
11824 
11825 static tree
rs6000_builtin_decl(unsigned code,bool initialize_p ATTRIBUTE_UNUSED)11826 rs6000_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
11827 {
11828   HOST_WIDE_INT fnmask;
11829 
11830   if (code >= RS6000_BUILTIN_COUNT)
11831     return error_mark_node;
11832 
11833   fnmask = rs6000_builtin_info[code].mask;
11834   if ((fnmask & rs6000_builtin_mask) != fnmask)
11835     {
11836       rs6000_invalid_builtin ((enum rs6000_builtins)code);
11837       return error_mark_node;
11838     }
11839 
11840   return rs6000_builtin_decls[code];
11841 }
11842 
11843 static void
spe_init_builtins(void)11844 spe_init_builtins (void)
11845 {
11846   tree puint_type_node = build_pointer_type (unsigned_type_node);
11847   tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
11848   const struct builtin_description *d;
11849   size_t i;
11850 
11851   tree v2si_ftype_4_v2si
11852     = build_function_type_list (opaque_V2SI_type_node,
11853                                 opaque_V2SI_type_node,
11854                                 opaque_V2SI_type_node,
11855                                 opaque_V2SI_type_node,
11856                                 opaque_V2SI_type_node,
11857                                 NULL_TREE);
11858 
11859   tree v2sf_ftype_4_v2sf
11860     = build_function_type_list (opaque_V2SF_type_node,
11861                                 opaque_V2SF_type_node,
11862                                 opaque_V2SF_type_node,
11863                                 opaque_V2SF_type_node,
11864                                 opaque_V2SF_type_node,
11865                                 NULL_TREE);
11866 
11867   tree int_ftype_int_v2si_v2si
11868     = build_function_type_list (integer_type_node,
11869                                 integer_type_node,
11870                                 opaque_V2SI_type_node,
11871                                 opaque_V2SI_type_node,
11872                                 NULL_TREE);
11873 
11874   tree int_ftype_int_v2sf_v2sf
11875     = build_function_type_list (integer_type_node,
11876                                 integer_type_node,
11877                                 opaque_V2SF_type_node,
11878                                 opaque_V2SF_type_node,
11879                                 NULL_TREE);
11880 
11881   tree void_ftype_v2si_puint_int
11882     = build_function_type_list (void_type_node,
11883                                 opaque_V2SI_type_node,
11884                                 puint_type_node,
11885                                 integer_type_node,
11886                                 NULL_TREE);
11887 
11888   tree void_ftype_v2si_puint_char
11889     = build_function_type_list (void_type_node,
11890                                 opaque_V2SI_type_node,
11891                                 puint_type_node,
11892                                 char_type_node,
11893                                 NULL_TREE);
11894 
11895   tree void_ftype_v2si_pv2si_int
11896     = build_function_type_list (void_type_node,
11897                                 opaque_V2SI_type_node,
11898                                 opaque_p_V2SI_type_node,
11899                                 integer_type_node,
11900                                 NULL_TREE);
11901 
11902   tree void_ftype_v2si_pv2si_char
11903     = build_function_type_list (void_type_node,
11904                                 opaque_V2SI_type_node,
11905                                 opaque_p_V2SI_type_node,
11906                                 char_type_node,
11907                                 NULL_TREE);
11908 
11909   tree void_ftype_int
11910     = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
11911 
11912   tree int_ftype_void
11913     = build_function_type_list (integer_type_node, NULL_TREE);
11914 
11915   tree v2si_ftype_pv2si_int
11916     = build_function_type_list (opaque_V2SI_type_node,
11917                                 opaque_p_V2SI_type_node,
11918                                 integer_type_node,
11919                                 NULL_TREE);
11920 
11921   tree v2si_ftype_puint_int
11922     = build_function_type_list (opaque_V2SI_type_node,
11923                                 puint_type_node,
11924                                 integer_type_node,
11925                                 NULL_TREE);
11926 
11927   tree v2si_ftype_pushort_int
11928     = build_function_type_list (opaque_V2SI_type_node,
11929                                 pushort_type_node,
11930                                 integer_type_node,
11931                                 NULL_TREE);
11932 
11933   tree v2si_ftype_signed_char
11934     = build_function_type_list (opaque_V2SI_type_node,
11935                                 signed_char_type_node,
11936                                 NULL_TREE);
11937 
11938   add_builtin_type ("__ev64_opaque__", opaque_V2SI_type_node);
11939 
11940   /* Initialize irregular SPE builtins.  */
11941 
11942   def_builtin ("__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
11943   def_builtin ("__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
11944   def_builtin ("__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
11945   def_builtin ("__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
11946   def_builtin ("__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
11947   def_builtin ("__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
11948   def_builtin ("__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
11949   def_builtin ("__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
11950   def_builtin ("__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
11951   def_builtin ("__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
11952   def_builtin ("__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
11953   def_builtin ("__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
11954   def_builtin ("__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
11955   def_builtin ("__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
11956   def_builtin ("__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
11957   def_builtin ("__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
11958   def_builtin ("__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
11959   def_builtin ("__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
11960 
11961   /* Loads.  */
11962   def_builtin ("__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
11963   def_builtin ("__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
11964   def_builtin ("__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
11965   def_builtin ("__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
11966   def_builtin ("__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
11967   def_builtin ("__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
11968   def_builtin ("__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
11969   def_builtin ("__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
11970   def_builtin ("__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
11971   def_builtin ("__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
11972   def_builtin ("__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
11973   def_builtin ("__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
11974   def_builtin ("__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
11975   def_builtin ("__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
11976   def_builtin ("__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
11977   def_builtin ("__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
11978   def_builtin ("__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
11979   def_builtin ("__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
11980   def_builtin ("__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
11981   def_builtin ("__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
11982   def_builtin ("__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
11983   def_builtin ("__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
11984 
11985   /* Predicates.  */
11986   d = bdesc_spe_predicates;
11987   for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
11988     {
11989       tree type;
11990 
11991       switch (insn_data[d->icode].operand[1].mode)
11992 	{
11993 	case V2SImode:
11994 	  type = int_ftype_int_v2si_v2si;
11995 	  break;
11996 	case V2SFmode:
11997 	  type = int_ftype_int_v2sf_v2sf;
11998 	  break;
11999 	default:
12000 	  gcc_unreachable ();
12001 	}
12002 
12003       def_builtin (d->name, type, d->code);
12004     }
12005 
12006   /* Evsel predicates.  */
12007   d = bdesc_spe_evsel;
12008   for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
12009     {
12010       tree type;
12011 
12012       switch (insn_data[d->icode].operand[1].mode)
12013 	{
12014 	case V2SImode:
12015 	  type = v2si_ftype_4_v2si;
12016 	  break;
12017 	case V2SFmode:
12018 	  type = v2sf_ftype_4_v2sf;
12019 	  break;
12020 	default:
12021 	  gcc_unreachable ();
12022 	}
12023 
12024       def_builtin (d->name, type, d->code);
12025     }
12026 }
12027 
12028 static void
paired_init_builtins(void)12029 paired_init_builtins (void)
12030 {
12031   const struct builtin_description *d;
12032   size_t i;
12033 
12034    tree int_ftype_int_v2sf_v2sf
12035     = build_function_type_list (integer_type_node,
12036                                 integer_type_node,
12037                                 V2SF_type_node,
12038                                 V2SF_type_node,
12039                                 NULL_TREE);
12040   tree pcfloat_type_node =
12041     build_pointer_type (build_qualified_type
12042 			(float_type_node, TYPE_QUAL_CONST));
12043 
12044   tree v2sf_ftype_long_pcfloat = build_function_type_list (V2SF_type_node,
12045 							   long_integer_type_node,
12046 							   pcfloat_type_node,
12047 							   NULL_TREE);
12048   tree void_ftype_v2sf_long_pcfloat =
12049     build_function_type_list (void_type_node,
12050 			      V2SF_type_node,
12051 			      long_integer_type_node,
12052 			      pcfloat_type_node,
12053 			      NULL_TREE);
12054 
12055 
12056   def_builtin ("__builtin_paired_lx", v2sf_ftype_long_pcfloat,
12057 	       PAIRED_BUILTIN_LX);
12058 
12059 
12060   def_builtin ("__builtin_paired_stx", void_ftype_v2sf_long_pcfloat,
12061 	       PAIRED_BUILTIN_STX);
12062 
12063   /* Predicates.  */
12064   d = bdesc_paired_preds;
12065   for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); ++i, d++)
12066     {
12067       tree type;
12068 
12069       if (TARGET_DEBUG_BUILTIN)
12070 	fprintf (stderr, "paired pred #%d, insn = %s [%d], mode = %s\n",
12071 		 (int)i, get_insn_name (d->icode), (int)d->icode,
12072 		 GET_MODE_NAME (insn_data[d->icode].operand[1].mode));
12073 
12074       switch (insn_data[d->icode].operand[1].mode)
12075 	{
12076 	case V2SFmode:
12077 	  type = int_ftype_int_v2sf_v2sf;
12078 	  break;
12079 	default:
12080 	  gcc_unreachable ();
12081 	}
12082 
12083       def_builtin (d->name, type, d->code);
12084     }
12085 }
12086 
12087 static void
altivec_init_builtins(void)12088 altivec_init_builtins (void)
12089 {
12090   const struct builtin_description *d;
12091   size_t i;
12092   tree ftype;
12093   tree decl;
12094 
12095   tree pvoid_type_node = build_pointer_type (void_type_node);
12096 
12097   tree pcvoid_type_node
12098     = build_pointer_type (build_qualified_type (void_type_node,
12099 						TYPE_QUAL_CONST));
12100 
12101   tree int_ftype_opaque
12102     = build_function_type_list (integer_type_node,
12103 				opaque_V4SI_type_node, NULL_TREE);
12104   tree opaque_ftype_opaque
12105     = build_function_type_list (integer_type_node, NULL_TREE);
12106   tree opaque_ftype_opaque_int
12107     = build_function_type_list (opaque_V4SI_type_node,
12108 				opaque_V4SI_type_node, integer_type_node, NULL_TREE);
12109   tree opaque_ftype_opaque_opaque_int
12110     = build_function_type_list (opaque_V4SI_type_node,
12111 				opaque_V4SI_type_node, opaque_V4SI_type_node,
12112 				integer_type_node, NULL_TREE);
12113   tree int_ftype_int_opaque_opaque
12114     = build_function_type_list (integer_type_node,
12115                                 integer_type_node, opaque_V4SI_type_node,
12116                                 opaque_V4SI_type_node, NULL_TREE);
12117   tree int_ftype_int_v4si_v4si
12118     = build_function_type_list (integer_type_node,
12119 				integer_type_node, V4SI_type_node,
12120 				V4SI_type_node, NULL_TREE);
12121   tree void_ftype_v4si
12122     = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
12123   tree v8hi_ftype_void
12124     = build_function_type_list (V8HI_type_node, NULL_TREE);
12125   tree void_ftype_void
12126     = build_function_type_list (void_type_node, NULL_TREE);
12127   tree void_ftype_int
12128     = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
12129 
12130   tree opaque_ftype_long_pcvoid
12131     = build_function_type_list (opaque_V4SI_type_node,
12132 				long_integer_type_node, pcvoid_type_node,
12133 				NULL_TREE);
12134   tree v16qi_ftype_long_pcvoid
12135     = build_function_type_list (V16QI_type_node,
12136 				long_integer_type_node, pcvoid_type_node,
12137 				NULL_TREE);
12138   tree v8hi_ftype_long_pcvoid
12139     = build_function_type_list (V8HI_type_node,
12140 				long_integer_type_node, pcvoid_type_node,
12141 				NULL_TREE);
12142   tree v4si_ftype_long_pcvoid
12143     = build_function_type_list (V4SI_type_node,
12144 				long_integer_type_node, pcvoid_type_node,
12145 				NULL_TREE);
12146   tree v4sf_ftype_long_pcvoid
12147     = build_function_type_list (V4SF_type_node,
12148 				long_integer_type_node, pcvoid_type_node,
12149 				NULL_TREE);
12150   tree v2df_ftype_long_pcvoid
12151     = build_function_type_list (V2DF_type_node,
12152 				long_integer_type_node, pcvoid_type_node,
12153 				NULL_TREE);
12154   tree v2di_ftype_long_pcvoid
12155     = build_function_type_list (V2DI_type_node,
12156 				long_integer_type_node, pcvoid_type_node,
12157 				NULL_TREE);
12158 
12159   tree void_ftype_opaque_long_pvoid
12160     = build_function_type_list (void_type_node,
12161 				opaque_V4SI_type_node, long_integer_type_node,
12162 				pvoid_type_node, NULL_TREE);
12163   tree void_ftype_v4si_long_pvoid
12164     = build_function_type_list (void_type_node,
12165 				V4SI_type_node, long_integer_type_node,
12166 				pvoid_type_node, NULL_TREE);
12167   tree void_ftype_v16qi_long_pvoid
12168     = build_function_type_list (void_type_node,
12169 				V16QI_type_node, long_integer_type_node,
12170 				pvoid_type_node, NULL_TREE);
12171   tree void_ftype_v8hi_long_pvoid
12172     = build_function_type_list (void_type_node,
12173 				V8HI_type_node, long_integer_type_node,
12174 				pvoid_type_node, NULL_TREE);
12175   tree void_ftype_v4sf_long_pvoid
12176     = build_function_type_list (void_type_node,
12177 				V4SF_type_node, long_integer_type_node,
12178 				pvoid_type_node, NULL_TREE);
12179   tree void_ftype_v2df_long_pvoid
12180     = build_function_type_list (void_type_node,
12181 				V2DF_type_node, long_integer_type_node,
12182 				pvoid_type_node, NULL_TREE);
12183   tree void_ftype_v2di_long_pvoid
12184     = build_function_type_list (void_type_node,
12185 				V2DI_type_node, long_integer_type_node,
12186 				pvoid_type_node, NULL_TREE);
12187   tree int_ftype_int_v8hi_v8hi
12188     = build_function_type_list (integer_type_node,
12189 				integer_type_node, V8HI_type_node,
12190 				V8HI_type_node, NULL_TREE);
12191   tree int_ftype_int_v16qi_v16qi
12192     = build_function_type_list (integer_type_node,
12193 				integer_type_node, V16QI_type_node,
12194 				V16QI_type_node, NULL_TREE);
12195   tree int_ftype_int_v4sf_v4sf
12196     = build_function_type_list (integer_type_node,
12197 				integer_type_node, V4SF_type_node,
12198 				V4SF_type_node, NULL_TREE);
12199   tree int_ftype_int_v2df_v2df
12200     = build_function_type_list (integer_type_node,
12201 				integer_type_node, V2DF_type_node,
12202 				V2DF_type_node, NULL_TREE);
12203   tree v4si_ftype_v4si
12204     = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
12205   tree v8hi_ftype_v8hi
12206     = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
12207   tree v16qi_ftype_v16qi
12208     = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
12209   tree v4sf_ftype_v4sf
12210     = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
12211   tree v2df_ftype_v2df
12212     = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
12213   tree void_ftype_pcvoid_int_int
12214     = build_function_type_list (void_type_node,
12215 				pcvoid_type_node, integer_type_node,
12216 				integer_type_node, NULL_TREE);
12217 
12218   def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
12219   def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
12220   def_builtin ("__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
12221   def_builtin ("__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
12222   def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
12223   def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
12224   def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
12225   def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
12226   def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
12227   def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
12228   def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
12229   def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
12230   def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
12231   def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
12232   def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
12233   def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
12234   def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
12235   def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
12236   def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
12237   def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
12238   def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
12239   def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
12240   def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
12241   def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
12242   def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
12243   def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
12244   def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
12245   def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
12246   def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
12247   def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
12248 
12249   def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid,
12250 	       VSX_BUILTIN_LXVD2X_V2DF);
12251   def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid,
12252 	       VSX_BUILTIN_LXVD2X_V2DI);
12253   def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid,
12254 	       VSX_BUILTIN_LXVW4X_V4SF);
12255   def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid,
12256 	       VSX_BUILTIN_LXVW4X_V4SI);
12257   def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid,
12258 	       VSX_BUILTIN_LXVW4X_V8HI);
12259   def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid,
12260 	       VSX_BUILTIN_LXVW4X_V16QI);
12261   def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid,
12262 	       VSX_BUILTIN_STXVD2X_V2DF);
12263   def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid,
12264 	       VSX_BUILTIN_STXVD2X_V2DI);
12265   def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid,
12266 	       VSX_BUILTIN_STXVW4X_V4SF);
12267   def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid,
12268 	       VSX_BUILTIN_STXVW4X_V4SI);
12269   def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid,
12270 	       VSX_BUILTIN_STXVW4X_V8HI);
12271   def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid,
12272 	       VSX_BUILTIN_STXVW4X_V16QI);
12273   def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid,
12274 	       VSX_BUILTIN_VEC_LD);
12275   def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid,
12276 	       VSX_BUILTIN_VEC_ST);
12277 
12278   def_builtin ("__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
12279   def_builtin ("__builtin_vec_splats", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_SPLATS);
12280   def_builtin ("__builtin_vec_promote", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_PROMOTE);
12281 
12282   def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
12283   def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
12284   def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_EXTRACT);
12285   def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_INSERT);
12286   def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
12287   def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
12288   def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
12289   def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
12290   def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
12291   def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
12292   def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
12293   def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
12294 
12295   /* Cell builtins.  */
12296   def_builtin ("__builtin_altivec_lvlx",  v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLX);
12297   def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLXL);
12298   def_builtin ("__builtin_altivec_lvrx",  v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRX);
12299   def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRXL);
12300 
12301   def_builtin ("__builtin_vec_lvlx",  v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLX);
12302   def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLXL);
12303   def_builtin ("__builtin_vec_lvrx",  v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRX);
12304   def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRXL);
12305 
12306   def_builtin ("__builtin_altivec_stvlx",  void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLX);
12307   def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLXL);
12308   def_builtin ("__builtin_altivec_stvrx",  void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRX);
12309   def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRXL);
12310 
12311   def_builtin ("__builtin_vec_stvlx",  void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLX);
12312   def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLXL);
12313   def_builtin ("__builtin_vec_stvrx",  void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRX);
12314   def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRXL);
12315 
12316   /* Add the DST variants.  */
12317   d = bdesc_dst;
12318   for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
12319     def_builtin (d->name, void_ftype_pcvoid_int_int, d->code);
12320 
12321   /* Initialize the predicates.  */
12322   d = bdesc_altivec_preds;
12323   for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
12324     {
12325       enum machine_mode mode1;
12326       tree type;
12327 
12328       if (rs6000_overloaded_builtin_p (d->code))
12329 	mode1 = VOIDmode;
12330       else
12331 	mode1 = insn_data[d->icode].operand[1].mode;
12332 
12333       switch (mode1)
12334 	{
12335 	case VOIDmode:
12336 	  type = int_ftype_int_opaque_opaque;
12337 	  break;
12338 	case V4SImode:
12339 	  type = int_ftype_int_v4si_v4si;
12340 	  break;
12341 	case V8HImode:
12342 	  type = int_ftype_int_v8hi_v8hi;
12343 	  break;
12344 	case V16QImode:
12345 	  type = int_ftype_int_v16qi_v16qi;
12346 	  break;
12347 	case V4SFmode:
12348 	  type = int_ftype_int_v4sf_v4sf;
12349 	  break;
12350 	case V2DFmode:
12351 	  type = int_ftype_int_v2df_v2df;
12352 	  break;
12353 	default:
12354 	  gcc_unreachable ();
12355 	}
12356 
12357       def_builtin (d->name, type, d->code);
12358     }
12359 
12360   /* Initialize the abs* operators.  */
12361   d = bdesc_abs;
12362   for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
12363     {
12364       enum machine_mode mode0;
12365       tree type;
12366 
12367       mode0 = insn_data[d->icode].operand[0].mode;
12368 
12369       switch (mode0)
12370 	{
12371 	case V4SImode:
12372 	  type = v4si_ftype_v4si;
12373 	  break;
12374 	case V8HImode:
12375 	  type = v8hi_ftype_v8hi;
12376 	  break;
12377 	case V16QImode:
12378 	  type = v16qi_ftype_v16qi;
12379 	  break;
12380 	case V4SFmode:
12381 	  type = v4sf_ftype_v4sf;
12382 	  break;
12383 	case V2DFmode:
12384 	  type = v2df_ftype_v2df;
12385 	  break;
12386 	default:
12387 	  gcc_unreachable ();
12388 	}
12389 
12390       def_builtin (d->name, type, d->code);
12391     }
12392 
12393   /* Initialize target builtin that implements
12394      targetm.vectorize.builtin_mask_for_load.  */
12395 
12396   decl = add_builtin_function ("__builtin_altivec_mask_for_load",
12397 			       v16qi_ftype_long_pcvoid,
12398 			       ALTIVEC_BUILTIN_MASK_FOR_LOAD,
12399 			       BUILT_IN_MD, NULL, NULL_TREE);
12400   TREE_READONLY (decl) = 1;
12401   /* Record the decl. Will be used by rs6000_builtin_mask_for_load.  */
12402   altivec_builtin_mask_for_load = decl;
12403 
12404   /* Access to the vec_init patterns.  */
12405   ftype = build_function_type_list (V4SI_type_node, integer_type_node,
12406 				    integer_type_node, integer_type_node,
12407 				    integer_type_node, NULL_TREE);
12408   def_builtin ("__builtin_vec_init_v4si", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SI);
12409 
12410   ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
12411 				    short_integer_type_node,
12412 				    short_integer_type_node,
12413 				    short_integer_type_node,
12414 				    short_integer_type_node,
12415 				    short_integer_type_node,
12416 				    short_integer_type_node,
12417 				    short_integer_type_node, NULL_TREE);
12418   def_builtin ("__builtin_vec_init_v8hi", ftype, ALTIVEC_BUILTIN_VEC_INIT_V8HI);
12419 
12420   ftype = build_function_type_list (V16QI_type_node, char_type_node,
12421 				    char_type_node, char_type_node,
12422 				    char_type_node, char_type_node,
12423 				    char_type_node, char_type_node,
12424 				    char_type_node, char_type_node,
12425 				    char_type_node, char_type_node,
12426 				    char_type_node, char_type_node,
12427 				    char_type_node, char_type_node,
12428 				    char_type_node, NULL_TREE);
12429   def_builtin ("__builtin_vec_init_v16qi", ftype,
12430 	       ALTIVEC_BUILTIN_VEC_INIT_V16QI);
12431 
12432   ftype = build_function_type_list (V4SF_type_node, float_type_node,
12433 				    float_type_node, float_type_node,
12434 				    float_type_node, NULL_TREE);
12435   def_builtin ("__builtin_vec_init_v4sf", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SF);
12436 
12437   /* VSX builtins.  */
12438   ftype = build_function_type_list (V2DF_type_node, double_type_node,
12439 				    double_type_node, NULL_TREE);
12440   def_builtin ("__builtin_vec_init_v2df", ftype, VSX_BUILTIN_VEC_INIT_V2DF);
12441 
12442   ftype = build_function_type_list (V2DI_type_node, intDI_type_node,
12443 				    intDI_type_node, NULL_TREE);
12444   def_builtin ("__builtin_vec_init_v2di", ftype, VSX_BUILTIN_VEC_INIT_V2DI);
12445 
12446   /* Access to the vec_set patterns.  */
12447   ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
12448 				    intSI_type_node,
12449 				    integer_type_node, NULL_TREE);
12450   def_builtin ("__builtin_vec_set_v4si", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SI);
12451 
12452   ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
12453 				    intHI_type_node,
12454 				    integer_type_node, NULL_TREE);
12455   def_builtin ("__builtin_vec_set_v8hi", ftype, ALTIVEC_BUILTIN_VEC_SET_V8HI);
12456 
12457   ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
12458 				    intQI_type_node,
12459 				    integer_type_node, NULL_TREE);
12460   def_builtin ("__builtin_vec_set_v16qi", ftype, ALTIVEC_BUILTIN_VEC_SET_V16QI);
12461 
12462   ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
12463 				    float_type_node,
12464 				    integer_type_node, NULL_TREE);
12465   def_builtin ("__builtin_vec_set_v4sf", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SF);
12466 
12467   ftype = build_function_type_list (V2DF_type_node, V2DF_type_node,
12468 				    double_type_node,
12469 				    integer_type_node, NULL_TREE);
12470   def_builtin ("__builtin_vec_set_v2df", ftype, VSX_BUILTIN_VEC_SET_V2DF);
12471 
12472   ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
12473 				    intDI_type_node,
12474 				    integer_type_node, NULL_TREE);
12475   def_builtin ("__builtin_vec_set_v2di", ftype, VSX_BUILTIN_VEC_SET_V2DI);
12476 
12477   /* Access to the vec_extract patterns.  */
12478   ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
12479 				    integer_type_node, NULL_TREE);
12480   def_builtin ("__builtin_vec_ext_v4si", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SI);
12481 
12482   ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
12483 				    integer_type_node, NULL_TREE);
12484   def_builtin ("__builtin_vec_ext_v8hi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V8HI);
12485 
12486   ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
12487 				    integer_type_node, NULL_TREE);
12488   def_builtin ("__builtin_vec_ext_v16qi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V16QI);
12489 
12490   ftype = build_function_type_list (float_type_node, V4SF_type_node,
12491 				    integer_type_node, NULL_TREE);
12492   def_builtin ("__builtin_vec_ext_v4sf", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SF);
12493 
12494   ftype = build_function_type_list (double_type_node, V2DF_type_node,
12495 				    integer_type_node, NULL_TREE);
12496   def_builtin ("__builtin_vec_ext_v2df", ftype, VSX_BUILTIN_VEC_EXT_V2DF);
12497 
12498   ftype = build_function_type_list (intDI_type_node, V2DI_type_node,
12499 				    integer_type_node, NULL_TREE);
12500   def_builtin ("__builtin_vec_ext_v2di", ftype, VSX_BUILTIN_VEC_EXT_V2DI);
12501 }
12502 
12503 /* Hash function for builtin functions with up to 3 arguments and a return
12504    type.  */
12505 static unsigned
builtin_hash_function(const void * hash_entry)12506 builtin_hash_function (const void *hash_entry)
12507 {
12508   unsigned ret = 0;
12509   int i;
12510   const struct builtin_hash_struct *bh =
12511     (const struct builtin_hash_struct *) hash_entry;
12512 
12513   for (i = 0; i < 4; i++)
12514     {
12515       ret = (ret * (unsigned)MAX_MACHINE_MODE) + ((unsigned)bh->mode[i]);
12516       ret = (ret * 2) + bh->uns_p[i];
12517     }
12518 
12519   return ret;
12520 }
12521 
12522 /* Compare builtin hash entries H1 and H2 for equivalence.  */
12523 static int
builtin_hash_eq(const void * h1,const void * h2)12524 builtin_hash_eq (const void *h1, const void *h2)
12525 {
12526   const struct builtin_hash_struct *p1 = (const struct builtin_hash_struct *) h1;
12527   const struct builtin_hash_struct *p2 = (const struct builtin_hash_struct *) h2;
12528 
12529   return ((p1->mode[0] == p2->mode[0])
12530 	  && (p1->mode[1] == p2->mode[1])
12531 	  && (p1->mode[2] == p2->mode[2])
12532 	  && (p1->mode[3] == p2->mode[3])
12533 	  && (p1->uns_p[0] == p2->uns_p[0])
12534 	  && (p1->uns_p[1] == p2->uns_p[1])
12535 	  && (p1->uns_p[2] == p2->uns_p[2])
12536 	  && (p1->uns_p[3] == p2->uns_p[3]));
12537 }
12538 
12539 /* Map types for builtin functions with an explicit return type and up to 3
12540    arguments.  Functions with fewer than 3 arguments use VOIDmode as the type
12541    of the argument.  */
12542 static tree
builtin_function_type(enum machine_mode mode_ret,enum machine_mode mode_arg0,enum machine_mode mode_arg1,enum machine_mode mode_arg2,enum rs6000_builtins builtin,const char * name)12543 builtin_function_type (enum machine_mode mode_ret, enum machine_mode mode_arg0,
12544 		       enum machine_mode mode_arg1, enum machine_mode mode_arg2,
12545 		       enum rs6000_builtins builtin, const char *name)
12546 {
12547   struct builtin_hash_struct h;
12548   struct builtin_hash_struct *h2;
12549   void **found;
12550   int num_args = 3;
12551   int i;
12552   tree ret_type = NULL_TREE;
12553   tree arg_type[3] = { NULL_TREE, NULL_TREE, NULL_TREE };
12554 
12555   /* Create builtin_hash_table.  */
12556   if (builtin_hash_table == NULL)
12557     builtin_hash_table = htab_create_ggc (1500, builtin_hash_function,
12558 					  builtin_hash_eq, NULL);
12559 
12560   h.type = NULL_TREE;
12561   h.mode[0] = mode_ret;
12562   h.mode[1] = mode_arg0;
12563   h.mode[2] = mode_arg1;
12564   h.mode[3] = mode_arg2;
12565   h.uns_p[0] = 0;
12566   h.uns_p[1] = 0;
12567   h.uns_p[2] = 0;
12568   h.uns_p[3] = 0;
12569 
12570   /* If the builtin is a type that produces unsigned results or takes unsigned
12571      arguments, and it is returned as a decl for the vectorizer (such as
12572      widening multiplies, permute), make sure the arguments and return value
12573      are type correct.  */
12574   switch (builtin)
12575     {
12576       /* unsigned 2 argument functions.  */
12577     case ALTIVEC_BUILTIN_VMULEUB_UNS:
12578     case ALTIVEC_BUILTIN_VMULEUH_UNS:
12579     case ALTIVEC_BUILTIN_VMULOUB_UNS:
12580     case ALTIVEC_BUILTIN_VMULOUH_UNS:
12581       h.uns_p[0] = 1;
12582       h.uns_p[1] = 1;
12583       h.uns_p[2] = 1;
12584       break;
12585 
12586       /* unsigned 3 argument functions.  */
12587     case ALTIVEC_BUILTIN_VPERM_16QI_UNS:
12588     case ALTIVEC_BUILTIN_VPERM_8HI_UNS:
12589     case ALTIVEC_BUILTIN_VPERM_4SI_UNS:
12590     case ALTIVEC_BUILTIN_VPERM_2DI_UNS:
12591     case ALTIVEC_BUILTIN_VSEL_16QI_UNS:
12592     case ALTIVEC_BUILTIN_VSEL_8HI_UNS:
12593     case ALTIVEC_BUILTIN_VSEL_4SI_UNS:
12594     case ALTIVEC_BUILTIN_VSEL_2DI_UNS:
12595     case VSX_BUILTIN_VPERM_16QI_UNS:
12596     case VSX_BUILTIN_VPERM_8HI_UNS:
12597     case VSX_BUILTIN_VPERM_4SI_UNS:
12598     case VSX_BUILTIN_VPERM_2DI_UNS:
12599     case VSX_BUILTIN_XXSEL_16QI_UNS:
12600     case VSX_BUILTIN_XXSEL_8HI_UNS:
12601     case VSX_BUILTIN_XXSEL_4SI_UNS:
12602     case VSX_BUILTIN_XXSEL_2DI_UNS:
12603       h.uns_p[0] = 1;
12604       h.uns_p[1] = 1;
12605       h.uns_p[2] = 1;
12606       h.uns_p[3] = 1;
12607       break;
12608 
12609       /* signed permute functions with unsigned char mask.  */
12610     case ALTIVEC_BUILTIN_VPERM_16QI:
12611     case ALTIVEC_BUILTIN_VPERM_8HI:
12612     case ALTIVEC_BUILTIN_VPERM_4SI:
12613     case ALTIVEC_BUILTIN_VPERM_4SF:
12614     case ALTIVEC_BUILTIN_VPERM_2DI:
12615     case ALTIVEC_BUILTIN_VPERM_2DF:
12616     case VSX_BUILTIN_VPERM_16QI:
12617     case VSX_BUILTIN_VPERM_8HI:
12618     case VSX_BUILTIN_VPERM_4SI:
12619     case VSX_BUILTIN_VPERM_4SF:
12620     case VSX_BUILTIN_VPERM_2DI:
12621     case VSX_BUILTIN_VPERM_2DF:
12622       h.uns_p[3] = 1;
12623       break;
12624 
12625       /* unsigned args, signed return.  */
12626     case VSX_BUILTIN_XVCVUXDDP_UNS:
12627     case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF:
12628       h.uns_p[1] = 1;
12629       break;
12630 
12631       /* signed args, unsigned return.  */
12632     case VSX_BUILTIN_XVCVDPUXDS_UNS:
12633     case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI:
12634       h.uns_p[0] = 1;
12635       break;
12636 
12637     default:
12638       break;
12639     }
12640 
12641   /* Figure out how many args are present.  */
12642   while (num_args > 0 && h.mode[num_args] == VOIDmode)
12643     num_args--;
12644 
12645   if (num_args == 0)
12646     fatal_error ("internal error: builtin function %s had no type", name);
12647 
12648   ret_type = builtin_mode_to_type[h.mode[0]][h.uns_p[0]];
12649   if (!ret_type && h.uns_p[0])
12650     ret_type = builtin_mode_to_type[h.mode[0]][0];
12651 
12652   if (!ret_type)
12653     fatal_error ("internal error: builtin function %s had an unexpected "
12654 		 "return type %s", name, GET_MODE_NAME (h.mode[0]));
12655 
12656   for (i = 0; i < (int) ARRAY_SIZE (arg_type); i++)
12657     arg_type[i] = NULL_TREE;
12658 
12659   for (i = 0; i < num_args; i++)
12660     {
12661       int m = (int) h.mode[i+1];
12662       int uns_p = h.uns_p[i+1];
12663 
12664       arg_type[i] = builtin_mode_to_type[m][uns_p];
12665       if (!arg_type[i] && uns_p)
12666 	arg_type[i] = builtin_mode_to_type[m][0];
12667 
12668       if (!arg_type[i])
12669 	fatal_error ("internal error: builtin function %s, argument %d "
12670 		     "had unexpected argument type %s", name, i,
12671 		     GET_MODE_NAME (m));
12672     }
12673 
12674   found = htab_find_slot (builtin_hash_table, &h, INSERT);
12675   if (*found == NULL)
12676     {
12677       h2 = ggc_alloc_builtin_hash_struct ();
12678       *h2 = h;
12679       *found = (void *)h2;
12680 
12681       h2->type = build_function_type_list (ret_type, arg_type[0], arg_type[1],
12682 					   arg_type[2], NULL_TREE);
12683     }
12684 
12685   return ((struct builtin_hash_struct *)(*found))->type;
12686 }
12687 
12688 static void
rs6000_common_init_builtins(void)12689 rs6000_common_init_builtins (void)
12690 {
12691   const struct builtin_description *d;
12692   size_t i;
12693 
12694   tree opaque_ftype_opaque = NULL_TREE;
12695   tree opaque_ftype_opaque_opaque = NULL_TREE;
12696   tree opaque_ftype_opaque_opaque_opaque = NULL_TREE;
12697   tree v2si_ftype_qi = NULL_TREE;
12698   tree v2si_ftype_v2si_qi = NULL_TREE;
12699   tree v2si_ftype_int_qi = NULL_TREE;
12700   HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
12701 
12702   if (!TARGET_PAIRED_FLOAT)
12703     {
12704       builtin_mode_to_type[V2SImode][0] = opaque_V2SI_type_node;
12705       builtin_mode_to_type[V2SFmode][0] = opaque_V2SF_type_node;
12706     }
12707 
12708   /* Paired and SPE builtins are only available if you build a compiler with
12709      the appropriate options, so only create those builtins with the
12710      appropriate compiler option.  Create Altivec and VSX builtins on machines
12711      with at least the general purpose extensions (970 and newer) to allow the
12712      use of the target attribute..  */
12713 
12714   if (TARGET_EXTRA_BUILTINS)
12715     builtin_mask |= RS6000_BTM_COMMON;
12716 
12717   /* Add the ternary operators.  */
12718   d = bdesc_3arg;
12719   for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
12720     {
12721       tree type;
12722       HOST_WIDE_INT mask = d->mask;
12723 
12724       if ((mask & builtin_mask) != mask)
12725 	{
12726 	  if (TARGET_DEBUG_BUILTIN)
12727 	    fprintf (stderr, "rs6000_builtin, skip ternary %s\n", d->name);
12728 	  continue;
12729 	}
12730 
12731       if (rs6000_overloaded_builtin_p (d->code))
12732 	{
12733 	  if (! (type = opaque_ftype_opaque_opaque_opaque))
12734 	    type = opaque_ftype_opaque_opaque_opaque
12735 	      = build_function_type_list (opaque_V4SI_type_node,
12736 					  opaque_V4SI_type_node,
12737 					  opaque_V4SI_type_node,
12738 					  opaque_V4SI_type_node,
12739 					  NULL_TREE);
12740 	}
12741       else
12742 	{
12743 	  enum insn_code icode = d->icode;
12744           if (d->name == 0 || icode == CODE_FOR_nothing)
12745 	    continue;
12746 
12747 	  type = builtin_function_type (insn_data[icode].operand[0].mode,
12748 					insn_data[icode].operand[1].mode,
12749 					insn_data[icode].operand[2].mode,
12750 					insn_data[icode].operand[3].mode,
12751 					d->code, d->name);
12752 	}
12753 
12754       def_builtin (d->name, type, d->code);
12755     }
12756 
12757   /* Add the binary operators.  */
12758   d = bdesc_2arg;
12759   for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
12760     {
12761       enum machine_mode mode0, mode1, mode2;
12762       tree type;
12763       HOST_WIDE_INT mask = d->mask;
12764 
12765       if ((mask & builtin_mask) != mask)
12766 	{
12767 	  if (TARGET_DEBUG_BUILTIN)
12768 	    fprintf (stderr, "rs6000_builtin, skip binary %s\n", d->name);
12769 	  continue;
12770 	}
12771 
12772       if (rs6000_overloaded_builtin_p (d->code))
12773 	{
12774 	  if (! (type = opaque_ftype_opaque_opaque))
12775 	    type = opaque_ftype_opaque_opaque
12776 	      = build_function_type_list (opaque_V4SI_type_node,
12777 					  opaque_V4SI_type_node,
12778 					  opaque_V4SI_type_node,
12779 					  NULL_TREE);
12780 	}
12781       else
12782 	{
12783 	  enum insn_code icode = d->icode;
12784           if (d->name == 0 || icode == CODE_FOR_nothing)
12785 	    continue;
12786 
12787           mode0 = insn_data[icode].operand[0].mode;
12788           mode1 = insn_data[icode].operand[1].mode;
12789           mode2 = insn_data[icode].operand[2].mode;
12790 
12791 	  if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
12792 	    {
12793 	      if (! (type = v2si_ftype_v2si_qi))
12794 		type = v2si_ftype_v2si_qi
12795 		  = build_function_type_list (opaque_V2SI_type_node,
12796 					      opaque_V2SI_type_node,
12797 					      char_type_node,
12798 					      NULL_TREE);
12799 	    }
12800 
12801 	  else if (mode0 == V2SImode && GET_MODE_CLASS (mode1) == MODE_INT
12802 		   && mode2 == QImode)
12803 	    {
12804 	      if (! (type = v2si_ftype_int_qi))
12805 		type = v2si_ftype_int_qi
12806 		  = build_function_type_list (opaque_V2SI_type_node,
12807 					      integer_type_node,
12808 					      char_type_node,
12809 					      NULL_TREE);
12810 	    }
12811 
12812 	  else
12813 	    type = builtin_function_type (mode0, mode1, mode2, VOIDmode,
12814 					  d->code, d->name);
12815 	}
12816 
12817       def_builtin (d->name, type, d->code);
12818     }
12819 
12820   /* Add the simple unary operators.  */
12821   d = bdesc_1arg;
12822   for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
12823     {
12824       enum machine_mode mode0, mode1;
12825       tree type;
12826       HOST_WIDE_INT mask = d->mask;
12827 
12828       if ((mask & builtin_mask) != mask)
12829 	{
12830 	  if (TARGET_DEBUG_BUILTIN)
12831 	    fprintf (stderr, "rs6000_builtin, skip unary %s\n", d->name);
12832 	  continue;
12833 	}
12834 
12835       if (rs6000_overloaded_builtin_p (d->code))
12836 	{
12837 	  if (! (type = opaque_ftype_opaque))
12838 	    type = opaque_ftype_opaque
12839 	      = build_function_type_list (opaque_V4SI_type_node,
12840 					  opaque_V4SI_type_node,
12841 					  NULL_TREE);
12842 	}
12843       else
12844         {
12845 	  enum insn_code icode = d->icode;
12846           if (d->name == 0 || icode == CODE_FOR_nothing)
12847 	    continue;
12848 
12849           mode0 = insn_data[icode].operand[0].mode;
12850           mode1 = insn_data[icode].operand[1].mode;
12851 
12852 	  if (mode0 == V2SImode && mode1 == QImode)
12853 	    {
12854 	      if (! (type = v2si_ftype_qi))
12855 		type = v2si_ftype_qi
12856 		  = build_function_type_list (opaque_V2SI_type_node,
12857 					      char_type_node,
12858 					      NULL_TREE);
12859 	    }
12860 
12861 	  else
12862 	    type = builtin_function_type (mode0, mode1, VOIDmode, VOIDmode,
12863 					  d->code, d->name);
12864 	}
12865 
12866       def_builtin (d->name, type, d->code);
12867     }
12868 }
12869 
12870 static void
rs6000_init_libfuncs(void)12871 rs6000_init_libfuncs (void)
12872 {
12873   if (!TARGET_IEEEQUAD)
12874       /* AIX/Darwin/64-bit Linux quad floating point routines.  */
12875     if (!TARGET_XL_COMPAT)
12876       {
12877 	set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
12878 	set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
12879 	set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
12880 	set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
12881 
12882 	if (!(TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)))
12883 	  {
12884 	    set_optab_libfunc (neg_optab, TFmode, "__gcc_qneg");
12885 	    set_optab_libfunc (eq_optab, TFmode, "__gcc_qeq");
12886 	    set_optab_libfunc (ne_optab, TFmode, "__gcc_qne");
12887 	    set_optab_libfunc (gt_optab, TFmode, "__gcc_qgt");
12888 	    set_optab_libfunc (ge_optab, TFmode, "__gcc_qge");
12889 	    set_optab_libfunc (lt_optab, TFmode, "__gcc_qlt");
12890 	    set_optab_libfunc (le_optab, TFmode, "__gcc_qle");
12891 
12892 	    set_conv_libfunc (sext_optab, TFmode, SFmode, "__gcc_stoq");
12893 	    set_conv_libfunc (sext_optab, TFmode, DFmode, "__gcc_dtoq");
12894 	    set_conv_libfunc (trunc_optab, SFmode, TFmode, "__gcc_qtos");
12895 	    set_conv_libfunc (trunc_optab, DFmode, TFmode, "__gcc_qtod");
12896 	    set_conv_libfunc (sfix_optab, SImode, TFmode, "__gcc_qtoi");
12897 	    set_conv_libfunc (ufix_optab, SImode, TFmode, "__gcc_qtou");
12898 	    set_conv_libfunc (sfloat_optab, TFmode, SImode, "__gcc_itoq");
12899 	    set_conv_libfunc (ufloat_optab, TFmode, SImode, "__gcc_utoq");
12900 	  }
12901 
12902 	if (!(TARGET_HARD_FLOAT && TARGET_FPRS))
12903 	  set_optab_libfunc (unord_optab, TFmode, "__gcc_qunord");
12904       }
12905     else
12906       {
12907 	set_optab_libfunc (add_optab, TFmode, "_xlqadd");
12908 	set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
12909 	set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
12910 	set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
12911       }
12912   else
12913     {
12914       /* 32-bit SVR4 quad floating point routines.  */
12915 
12916       set_optab_libfunc (add_optab, TFmode, "_q_add");
12917       set_optab_libfunc (sub_optab, TFmode, "_q_sub");
12918       set_optab_libfunc (neg_optab, TFmode, "_q_neg");
12919       set_optab_libfunc (smul_optab, TFmode, "_q_mul");
12920       set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
12921       if (TARGET_PPC_GPOPT)
12922 	set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
12923 
12924       set_optab_libfunc (eq_optab, TFmode, "_q_feq");
12925       set_optab_libfunc (ne_optab, TFmode, "_q_fne");
12926       set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
12927       set_optab_libfunc (ge_optab, TFmode, "_q_fge");
12928       set_optab_libfunc (lt_optab, TFmode, "_q_flt");
12929       set_optab_libfunc (le_optab, TFmode, "_q_fle");
12930 
12931       set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
12932       set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
12933       set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
12934       set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
12935       set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
12936       set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
12937       set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
12938       set_conv_libfunc (ufloat_optab, TFmode, SImode, "_q_utoq");
12939     }
12940 }
12941 
12942 
12943 /* Expand a block clear operation, and return 1 if successful.  Return 0
12944    if we should let the compiler generate normal code.
12945 
12946    operands[0] is the destination
12947    operands[1] is the length
12948    operands[3] is the alignment */
12949 
12950 int
expand_block_clear(rtx operands[])12951 expand_block_clear (rtx operands[])
12952 {
12953   rtx orig_dest = operands[0];
12954   rtx bytes_rtx	= operands[1];
12955   rtx align_rtx = operands[3];
12956   bool constp	= (GET_CODE (bytes_rtx) == CONST_INT);
12957   HOST_WIDE_INT align;
12958   HOST_WIDE_INT bytes;
12959   int offset;
12960   int clear_bytes;
12961   int clear_step;
12962 
12963   /* If this is not a fixed size move, just call memcpy */
12964   if (! constp)
12965     return 0;
12966 
12967   /* This must be a fixed size alignment  */
12968   gcc_assert (GET_CODE (align_rtx) == CONST_INT);
12969   align = INTVAL (align_rtx) * BITS_PER_UNIT;
12970 
12971   /* Anything to clear? */
12972   bytes = INTVAL (bytes_rtx);
12973   if (bytes <= 0)
12974     return 1;
12975 
12976   /* Use the builtin memset after a point, to avoid huge code bloat.
12977      When optimize_size, avoid any significant code bloat; calling
12978      memset is about 4 instructions, so allow for one instruction to
12979      load zero and three to do clearing.  */
12980   if (TARGET_ALTIVEC && align >= 128)
12981     clear_step = 16;
12982   else if (TARGET_POWERPC64 && align >= 32)
12983     clear_step = 8;
12984   else if (TARGET_SPE && align >= 64)
12985     clear_step = 8;
12986   else
12987     clear_step = 4;
12988 
12989   if (optimize_size && bytes > 3 * clear_step)
12990     return 0;
12991   if (! optimize_size && bytes > 8 * clear_step)
12992     return 0;
12993 
12994   for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
12995     {
12996       enum machine_mode mode = BLKmode;
12997       rtx dest;
12998 
12999       if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
13000 	{
13001 	  clear_bytes = 16;
13002 	  mode = V4SImode;
13003 	}
13004       else if (bytes >= 8 && TARGET_SPE && align >= 64)
13005         {
13006           clear_bytes = 8;
13007           mode = V2SImode;
13008         }
13009       else if (bytes >= 8 && TARGET_POWERPC64
13010 	       /* 64-bit loads and stores require word-aligned
13011 		  displacements.  */
13012 	       && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
13013 	{
13014 	  clear_bytes = 8;
13015 	  mode = DImode;
13016 	}
13017       else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
13018 	{			/* move 4 bytes */
13019 	  clear_bytes = 4;
13020 	  mode = SImode;
13021 	}
13022       else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
13023 	{			/* move 2 bytes */
13024 	  clear_bytes = 2;
13025 	  mode = HImode;
13026 	}
13027       else /* move 1 byte at a time */
13028 	{
13029 	  clear_bytes = 1;
13030 	  mode = QImode;
13031 	}
13032 
13033       dest = adjust_address (orig_dest, mode, offset);
13034 
13035       emit_move_insn (dest, CONST0_RTX (mode));
13036     }
13037 
13038   return 1;
13039 }
13040 
13041 
13042 /* Expand a block move operation, and return 1 if successful.  Return 0
13043    if we should let the compiler generate normal code.
13044 
13045    operands[0] is the destination
13046    operands[1] is the source
13047    operands[2] is the length
13048    operands[3] is the alignment */
13049 
13050 #define MAX_MOVE_REG 4
13051 
13052 int
expand_block_move(rtx operands[])13053 expand_block_move (rtx operands[])
13054 {
13055   rtx orig_dest = operands[0];
13056   rtx orig_src	= operands[1];
13057   rtx bytes_rtx	= operands[2];
13058   rtx align_rtx = operands[3];
13059   int constp	= (GET_CODE (bytes_rtx) == CONST_INT);
13060   int align;
13061   int bytes;
13062   int offset;
13063   int move_bytes;
13064   rtx stores[MAX_MOVE_REG];
13065   int num_reg = 0;
13066 
13067   /* If this is not a fixed size move, just call memcpy */
13068   if (! constp)
13069     return 0;
13070 
13071   /* This must be a fixed size alignment */
13072   gcc_assert (GET_CODE (align_rtx) == CONST_INT);
13073   align = INTVAL (align_rtx) * BITS_PER_UNIT;
13074 
13075   /* Anything to move? */
13076   bytes = INTVAL (bytes_rtx);
13077   if (bytes <= 0)
13078     return 1;
13079 
13080   if (bytes > rs6000_block_move_inline_limit)
13081     return 0;
13082 
13083   for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
13084     {
13085       union {
13086 	rtx (*movmemsi) (rtx, rtx, rtx, rtx);
13087 	rtx (*mov) (rtx, rtx);
13088       } gen_func;
13089       enum machine_mode mode = BLKmode;
13090       rtx src, dest;
13091 
13092       /* Altivec first, since it will be faster than a string move
13093 	 when it applies, and usually not significantly larger.  */
13094       if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
13095 	{
13096 	  move_bytes = 16;
13097 	  mode = V4SImode;
13098 	  gen_func.mov = gen_movv4si;
13099 	}
13100       else if (TARGET_SPE && bytes >= 8 && align >= 64)
13101         {
13102           move_bytes = 8;
13103           mode = V2SImode;
13104           gen_func.mov = gen_movv2si;
13105         }
13106       else if (TARGET_STRING
13107 	  && bytes > 24		/* move up to 32 bytes at a time */
13108 	  && ! fixed_regs[5]
13109 	  && ! fixed_regs[6]
13110 	  && ! fixed_regs[7]
13111 	  && ! fixed_regs[8]
13112 	  && ! fixed_regs[9]
13113 	  && ! fixed_regs[10]
13114 	  && ! fixed_regs[11]
13115 	  && ! fixed_regs[12])
13116 	{
13117 	  move_bytes = (bytes > 32) ? 32 : bytes;
13118 	  gen_func.movmemsi = gen_movmemsi_8reg;
13119 	}
13120       else if (TARGET_STRING
13121 	       && bytes > 16	/* move up to 24 bytes at a time */
13122 	       && ! fixed_regs[5]
13123 	       && ! fixed_regs[6]
13124 	       && ! fixed_regs[7]
13125 	       && ! fixed_regs[8]
13126 	       && ! fixed_regs[9]
13127 	       && ! fixed_regs[10])
13128 	{
13129 	  move_bytes = (bytes > 24) ? 24 : bytes;
13130 	  gen_func.movmemsi = gen_movmemsi_6reg;
13131 	}
13132       else if (TARGET_STRING
13133 	       && bytes > 8	/* move up to 16 bytes at a time */
13134 	       && ! fixed_regs[5]
13135 	       && ! fixed_regs[6]
13136 	       && ! fixed_regs[7]
13137 	       && ! fixed_regs[8])
13138 	{
13139 	  move_bytes = (bytes > 16) ? 16 : bytes;
13140 	  gen_func.movmemsi = gen_movmemsi_4reg;
13141 	}
13142       else if (bytes >= 8 && TARGET_POWERPC64
13143 	       /* 64-bit loads and stores require word-aligned
13144 		  displacements.  */
13145 	       && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
13146 	{
13147 	  move_bytes = 8;
13148 	  mode = DImode;
13149 	  gen_func.mov = gen_movdi;
13150 	}
13151       else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
13152 	{			/* move up to 8 bytes at a time */
13153 	  move_bytes = (bytes > 8) ? 8 : bytes;
13154 	  gen_func.movmemsi = gen_movmemsi_2reg;
13155 	}
13156       else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
13157 	{			/* move 4 bytes */
13158 	  move_bytes = 4;
13159 	  mode = SImode;
13160 	  gen_func.mov = gen_movsi;
13161 	}
13162       else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
13163 	{			/* move 2 bytes */
13164 	  move_bytes = 2;
13165 	  mode = HImode;
13166 	  gen_func.mov = gen_movhi;
13167 	}
13168       else if (TARGET_STRING && bytes > 1)
13169 	{			/* move up to 4 bytes at a time */
13170 	  move_bytes = (bytes > 4) ? 4 : bytes;
13171 	  gen_func.movmemsi = gen_movmemsi_1reg;
13172 	}
13173       else /* move 1 byte at a time */
13174 	{
13175 	  move_bytes = 1;
13176 	  mode = QImode;
13177 	  gen_func.mov = gen_movqi;
13178 	}
13179 
13180       src = adjust_address (orig_src, mode, offset);
13181       dest = adjust_address (orig_dest, mode, offset);
13182 
13183       if (mode != BLKmode)
13184 	{
13185 	  rtx tmp_reg = gen_reg_rtx (mode);
13186 
13187 	  emit_insn ((*gen_func.mov) (tmp_reg, src));
13188 	  stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
13189 	}
13190 
13191       if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
13192 	{
13193 	  int i;
13194 	  for (i = 0; i < num_reg; i++)
13195 	    emit_insn (stores[i]);
13196 	  num_reg = 0;
13197 	}
13198 
13199       if (mode == BLKmode)
13200 	{
13201 	  /* Move the address into scratch registers.  The movmemsi
13202 	     patterns require zero offset.  */
13203 	  if (!REG_P (XEXP (src, 0)))
13204 	    {
13205 	      rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
13206 	      src = replace_equiv_address (src, src_reg);
13207 	    }
13208 	  set_mem_size (src, move_bytes);
13209 
13210 	  if (!REG_P (XEXP (dest, 0)))
13211 	    {
13212 	      rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
13213 	      dest = replace_equiv_address (dest, dest_reg);
13214 	    }
13215 	  set_mem_size (dest, move_bytes);
13216 
13217 	  emit_insn ((*gen_func.movmemsi) (dest, src,
13218 					   GEN_INT (move_bytes & 31),
13219 					   align_rtx));
13220 	}
13221     }
13222 
13223   return 1;
13224 }
13225 
13226 
13227 /* Return a string to perform a load_multiple operation.
13228    operands[0] is the vector.
13229    operands[1] is the source address.
13230    operands[2] is the first destination register.  */
13231 
13232 const char *
rs6000_output_load_multiple(rtx operands[3])13233 rs6000_output_load_multiple (rtx operands[3])
13234 {
13235   /* We have to handle the case where the pseudo used to contain the address
13236      is assigned to one of the output registers.  */
13237   int i, j;
13238   int words = XVECLEN (operands[0], 0);
13239   rtx xop[10];
13240 
13241   if (XVECLEN (operands[0], 0) == 1)
13242     return "lwz %2,0(%1)";
13243 
13244   for (i = 0; i < words; i++)
13245     if (refers_to_regno_p (REGNO (operands[2]) + i,
13246 			   REGNO (operands[2]) + i + 1, operands[1], 0))
13247       {
13248 	if (i == words-1)
13249 	  {
13250 	    xop[0] = GEN_INT (4 * (words-1));
13251 	    xop[1] = operands[1];
13252 	    xop[2] = operands[2];
13253 	    output_asm_insn ("lswi %2,%1,%0\n\tlwz %1,%0(%1)", xop);
13254 	    return "";
13255 	  }
13256 	else if (i == 0)
13257 	  {
13258 	    xop[0] = GEN_INT (4 * (words-1));
13259 	    xop[1] = operands[1];
13260 	    xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
13261 	    output_asm_insn ("addi %1,%1,4\n\tlswi %2,%1,%0\n\tlwz %1,-4(%1)", xop);
13262 	    return "";
13263 	  }
13264 	else
13265 	  {
13266 	    for (j = 0; j < words; j++)
13267 	      if (j != i)
13268 		{
13269 		  xop[0] = GEN_INT (j * 4);
13270 		  xop[1] = operands[1];
13271 		  xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
13272 		  output_asm_insn ("lwz %2,%0(%1)", xop);
13273 		}
13274 	    xop[0] = GEN_INT (i * 4);
13275 	    xop[1] = operands[1];
13276 	    output_asm_insn ("lwz %1,%0(%1)", xop);
13277 	    return "";
13278 	  }
13279       }
13280 
13281   return "lswi %2,%1,%N0";
13282 }
13283 
13284 
13285 /* A validation routine: say whether CODE, a condition code, and MODE
13286    match.  The other alternatives either don't make sense or should
13287    never be generated.  */
13288 
13289 void
validate_condition_mode(enum rtx_code code,enum machine_mode mode)13290 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
13291 {
13292   gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
13293 	       || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
13294 	      && GET_MODE_CLASS (mode) == MODE_CC);
13295 
13296   /* These don't make sense.  */
13297   gcc_assert ((code != GT && code != LT && code != GE && code != LE)
13298 	      || mode != CCUNSmode);
13299 
13300   gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
13301 	      || mode == CCUNSmode);
13302 
13303   gcc_assert (mode == CCFPmode
13304 	      || (code != ORDERED && code != UNORDERED
13305 		  && code != UNEQ && code != LTGT
13306 		  && code != UNGT && code != UNLT
13307 		  && code != UNGE && code != UNLE));
13308 
13309   /* These should never be generated except for
13310      flag_finite_math_only.  */
13311   gcc_assert (mode != CCFPmode
13312 	      || flag_finite_math_only
13313 	      || (code != LE && code != GE
13314 		  && code != UNEQ && code != LTGT
13315 		  && code != UNGT && code != UNLT));
13316 
13317   /* These are invalid; the information is not there.  */
13318   gcc_assert (mode != CCEQmode || code == EQ || code == NE);
13319 }
13320 
13321 
13322 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
13323    mask required to convert the result of a rotate insn into a shift
13324    left insn of SHIFTOP bits.  Both are known to be SImode CONST_INT.  */
13325 
13326 int
includes_lshift_p(rtx shiftop,rtx andop)13327 includes_lshift_p (rtx shiftop, rtx andop)
13328 {
13329   unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
13330 
13331   shift_mask <<= INTVAL (shiftop);
13332 
13333   return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
13334 }
13335 
13336 /* Similar, but for right shift.  */
13337 
13338 int
includes_rshift_p(rtx shiftop,rtx andop)13339 includes_rshift_p (rtx shiftop, rtx andop)
13340 {
13341   unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
13342 
13343   shift_mask >>= INTVAL (shiftop);
13344 
13345   return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
13346 }
13347 
13348 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
13349    to perform a left shift.  It must have exactly SHIFTOP least
13350    significant 0's, then one or more 1's, then zero or more 0's.  */
13351 
13352 int
includes_rldic_lshift_p(rtx shiftop,rtx andop)13353 includes_rldic_lshift_p (rtx shiftop, rtx andop)
13354 {
13355   if (GET_CODE (andop) == CONST_INT)
13356     {
13357       HOST_WIDE_INT c, lsb, shift_mask;
13358 
13359       c = INTVAL (andop);
13360       if (c == 0 || c == ~0)
13361 	return 0;
13362 
13363       shift_mask = ~0;
13364       shift_mask <<= INTVAL (shiftop);
13365 
13366       /* Find the least significant one bit.  */
13367       lsb = c & -c;
13368 
13369       /* It must coincide with the LSB of the shift mask.  */
13370       if (-lsb != shift_mask)
13371 	return 0;
13372 
13373       /* Invert to look for the next transition (if any).  */
13374       c = ~c;
13375 
13376       /* Remove the low group of ones (originally low group of zeros).  */
13377       c &= -lsb;
13378 
13379       /* Again find the lsb, and check we have all 1's above.  */
13380       lsb = c & -c;
13381       return c == -lsb;
13382     }
13383   else if (GET_CODE (andop) == CONST_DOUBLE
13384 	   && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
13385     {
13386       HOST_WIDE_INT low, high, lsb;
13387       HOST_WIDE_INT shift_mask_low, shift_mask_high;
13388 
13389       low = CONST_DOUBLE_LOW (andop);
13390       if (HOST_BITS_PER_WIDE_INT < 64)
13391 	high = CONST_DOUBLE_HIGH (andop);
13392 
13393       if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
13394 	  || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
13395 	return 0;
13396 
13397       if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
13398 	{
13399 	  shift_mask_high = ~0;
13400 	  if (INTVAL (shiftop) > 32)
13401 	    shift_mask_high <<= INTVAL (shiftop) - 32;
13402 
13403 	  lsb = high & -high;
13404 
13405 	  if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
13406 	    return 0;
13407 
13408 	  high = ~high;
13409 	  high &= -lsb;
13410 
13411 	  lsb = high & -high;
13412 	  return high == -lsb;
13413 	}
13414 
13415       shift_mask_low = ~0;
13416       shift_mask_low <<= INTVAL (shiftop);
13417 
13418       lsb = low & -low;
13419 
13420       if (-lsb != shift_mask_low)
13421 	return 0;
13422 
13423       if (HOST_BITS_PER_WIDE_INT < 64)
13424 	high = ~high;
13425       low = ~low;
13426       low &= -lsb;
13427 
13428       if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
13429 	{
13430 	  lsb = high & -high;
13431 	  return high == -lsb;
13432 	}
13433 
13434       lsb = low & -low;
13435       return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
13436     }
13437   else
13438     return 0;
13439 }
13440 
13441 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
13442    to perform a left shift.  It must have SHIFTOP or more least
13443    significant 0's, with the remainder of the word 1's.  */
13444 
13445 int
includes_rldicr_lshift_p(rtx shiftop,rtx andop)13446 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
13447 {
13448   if (GET_CODE (andop) == CONST_INT)
13449     {
13450       HOST_WIDE_INT c, lsb, shift_mask;
13451 
13452       shift_mask = ~0;
13453       shift_mask <<= INTVAL (shiftop);
13454       c = INTVAL (andop);
13455 
13456       /* Find the least significant one bit.  */
13457       lsb = c & -c;
13458 
13459       /* It must be covered by the shift mask.
13460 	 This test also rejects c == 0.  */
13461       if ((lsb & shift_mask) == 0)
13462 	return 0;
13463 
13464       /* Check we have all 1's above the transition, and reject all 1's.  */
13465       return c == -lsb && lsb != 1;
13466     }
13467   else if (GET_CODE (andop) == CONST_DOUBLE
13468 	   && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
13469     {
13470       HOST_WIDE_INT low, lsb, shift_mask_low;
13471 
13472       low = CONST_DOUBLE_LOW (andop);
13473 
13474       if (HOST_BITS_PER_WIDE_INT < 64)
13475 	{
13476 	  HOST_WIDE_INT high, shift_mask_high;
13477 
13478 	  high = CONST_DOUBLE_HIGH (andop);
13479 
13480 	  if (low == 0)
13481 	    {
13482 	      shift_mask_high = ~0;
13483 	      if (INTVAL (shiftop) > 32)
13484 		shift_mask_high <<= INTVAL (shiftop) - 32;
13485 
13486 	      lsb = high & -high;
13487 
13488 	      if ((lsb & shift_mask_high) == 0)
13489 		return 0;
13490 
13491 	      return high == -lsb;
13492 	    }
13493 	  if (high != ~0)
13494 	    return 0;
13495 	}
13496 
13497       shift_mask_low = ~0;
13498       shift_mask_low <<= INTVAL (shiftop);
13499 
13500       lsb = low & -low;
13501 
13502       if ((lsb & shift_mask_low) == 0)
13503 	return 0;
13504 
13505       return low == -lsb && lsb != 1;
13506     }
13507   else
13508     return 0;
13509 }
13510 
13511 /* Return 1 if operands will generate a valid arguments to rlwimi
13512 instruction for insert with right shift in 64-bit mode.  The mask may
13513 not start on the first bit or stop on the last bit because wrap-around
13514 effects of instruction do not correspond to semantics of RTL insn.  */
13515 
13516 int
insvdi_rshift_rlwimi_p(rtx sizeop,rtx startop,rtx shiftop)13517 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
13518 {
13519   if (INTVAL (startop) > 32
13520       && INTVAL (startop) < 64
13521       && INTVAL (sizeop) > 1
13522       && INTVAL (sizeop) + INTVAL (startop) < 64
13523       && INTVAL (shiftop) > 0
13524       && INTVAL (sizeop) + INTVAL (shiftop) < 32
13525       && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
13526     return 1;
13527 
13528   return 0;
13529 }
13530 
13531 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
13532    for lfq and stfq insns iff the registers are hard registers.   */
13533 
13534 int
registers_ok_for_quad_peep(rtx reg1,rtx reg2)13535 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
13536 {
13537   /* We might have been passed a SUBREG.  */
13538   if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
13539     return 0;
13540 
13541   /* We might have been passed non floating point registers.  */
13542   if (!FP_REGNO_P (REGNO (reg1))
13543       || !FP_REGNO_P (REGNO (reg2)))
13544     return 0;
13545 
13546   return (REGNO (reg1) == REGNO (reg2) - 1);
13547 }
13548 
13549 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
13550    addr1 and addr2 must be in consecutive memory locations
13551    (addr2 == addr1 + 8).  */
13552 
13553 int
mems_ok_for_quad_peep(rtx mem1,rtx mem2)13554 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
13555 {
13556   rtx addr1, addr2;
13557   unsigned int reg1, reg2;
13558   int offset1, offset2;
13559 
13560   /* The mems cannot be volatile.  */
13561   if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
13562     return 0;
13563 
13564   addr1 = XEXP (mem1, 0);
13565   addr2 = XEXP (mem2, 0);
13566 
13567   /* Extract an offset (if used) from the first addr.  */
13568   if (GET_CODE (addr1) == PLUS)
13569     {
13570       /* If not a REG, return zero.  */
13571       if (GET_CODE (XEXP (addr1, 0)) != REG)
13572 	return 0;
13573       else
13574 	{
13575 	  reg1 = REGNO (XEXP (addr1, 0));
13576 	  /* The offset must be constant!  */
13577 	  if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
13578 	    return 0;
13579 	  offset1 = INTVAL (XEXP (addr1, 1));
13580 	}
13581     }
13582   else if (GET_CODE (addr1) != REG)
13583     return 0;
13584   else
13585     {
13586       reg1 = REGNO (addr1);
13587       /* This was a simple (mem (reg)) expression.  Offset is 0.  */
13588       offset1 = 0;
13589     }
13590 
13591   /* And now for the second addr.  */
13592   if (GET_CODE (addr2) == PLUS)
13593     {
13594       /* If not a REG, return zero.  */
13595       if (GET_CODE (XEXP (addr2, 0)) != REG)
13596 	return 0;
13597       else
13598 	{
13599 	  reg2 = REGNO (XEXP (addr2, 0));
13600 	  /* The offset must be constant. */
13601 	  if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
13602 	    return 0;
13603 	  offset2 = INTVAL (XEXP (addr2, 1));
13604 	}
13605     }
13606   else if (GET_CODE (addr2) != REG)
13607     return 0;
13608   else
13609     {
13610       reg2 = REGNO (addr2);
13611       /* This was a simple (mem (reg)) expression.  Offset is 0.  */
13612       offset2 = 0;
13613     }
13614 
13615   /* Both of these must have the same base register.  */
13616   if (reg1 != reg2)
13617     return 0;
13618 
13619   /* The offset for the second addr must be 8 more than the first addr.  */
13620   if (offset2 != offset1 + 8)
13621     return 0;
13622 
13623   /* All the tests passed.  addr1 and addr2 are valid for lfq or stfq
13624      instructions.  */
13625   return 1;
13626 }
13627 
13628 
13629 rtx
rs6000_secondary_memory_needed_rtx(enum machine_mode mode)13630 rs6000_secondary_memory_needed_rtx (enum machine_mode mode)
13631 {
13632   static bool eliminated = false;
13633   rtx ret;
13634 
13635   if (mode != SDmode)
13636     ret = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
13637   else
13638     {
13639       rtx mem = cfun->machine->sdmode_stack_slot;
13640       gcc_assert (mem != NULL_RTX);
13641 
13642       if (!eliminated)
13643 	{
13644 	  mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
13645 	  cfun->machine->sdmode_stack_slot = mem;
13646 	  eliminated = true;
13647 	}
13648       ret = mem;
13649     }
13650 
13651   if (TARGET_DEBUG_ADDR)
13652     {
13653       fprintf (stderr, "\nrs6000_secondary_memory_needed_rtx, mode %s, rtx:\n",
13654 	       GET_MODE_NAME (mode));
13655       if (!ret)
13656 	fprintf (stderr, "\tNULL_RTX\n");
13657       else
13658 	debug_rtx (ret);
13659     }
13660 
13661   return ret;
13662 }
13663 
13664 static tree
rs6000_check_sdmode(tree * tp,int * walk_subtrees,void * data ATTRIBUTE_UNUSED)13665 rs6000_check_sdmode (tree *tp, int *walk_subtrees, void *data ATTRIBUTE_UNUSED)
13666 {
13667   /* Don't walk into types.  */
13668   if (*tp == NULL_TREE || *tp == error_mark_node || TYPE_P (*tp))
13669     {
13670       *walk_subtrees = 0;
13671       return NULL_TREE;
13672     }
13673 
13674   switch (TREE_CODE (*tp))
13675     {
13676     case VAR_DECL:
13677     case PARM_DECL:
13678     case FIELD_DECL:
13679     case RESULT_DECL:
13680     case SSA_NAME:
13681     case REAL_CST:
13682     case MEM_REF:
13683     case VIEW_CONVERT_EXPR:
13684       if (TYPE_MODE (TREE_TYPE (*tp)) == SDmode)
13685 	return *tp;
13686       break;
13687     default:
13688       break;
13689     }
13690 
13691   return NULL_TREE;
13692 }
13693 
13694 enum reload_reg_type {
13695   GPR_REGISTER_TYPE,
13696   VECTOR_REGISTER_TYPE,
13697   OTHER_REGISTER_TYPE
13698 };
13699 
13700 static enum reload_reg_type
rs6000_reload_register_type(enum reg_class rclass)13701 rs6000_reload_register_type (enum reg_class rclass)
13702 {
13703   switch (rclass)
13704     {
13705     case GENERAL_REGS:
13706     case BASE_REGS:
13707       return GPR_REGISTER_TYPE;
13708 
13709     case FLOAT_REGS:
13710     case ALTIVEC_REGS:
13711     case VSX_REGS:
13712       return VECTOR_REGISTER_TYPE;
13713 
13714     default:
13715       return OTHER_REGISTER_TYPE;
13716     }
13717 }
13718 
13719 /* Inform reload about cases where moving X with a mode MODE to a register in
13720    RCLASS requires an extra scratch or immediate register.  Return the class
13721    needed for the immediate register.
13722 
13723    For VSX and Altivec, we may need a register to convert sp+offset into
13724    reg+sp.
13725 
13726    For misaligned 64-bit gpr loads and stores we need a register to
13727    convert an offset address to indirect.  */
13728 
13729 static reg_class_t
rs6000_secondary_reload(bool in_p,rtx x,reg_class_t rclass_i,enum machine_mode mode,secondary_reload_info * sri)13730 rs6000_secondary_reload (bool in_p,
13731 			 rtx x,
13732 			 reg_class_t rclass_i,
13733 			 enum machine_mode mode,
13734 			 secondary_reload_info *sri)
13735 {
13736   enum reg_class rclass = (enum reg_class) rclass_i;
13737   reg_class_t ret = ALL_REGS;
13738   enum insn_code icode;
13739   bool default_p = false;
13740 
13741   sri->icode = CODE_FOR_nothing;
13742 
13743   /* Convert vector loads and stores into gprs to use an additional base
13744      register.  */
13745   icode = rs6000_vector_reload[mode][in_p != false];
13746   if (icode != CODE_FOR_nothing)
13747     {
13748       ret = NO_REGS;
13749       sri->icode = CODE_FOR_nothing;
13750       sri->extra_cost = 0;
13751 
13752       if (GET_CODE (x) == MEM)
13753 	{
13754 	  rtx addr = XEXP (x, 0);
13755 
13756 	  /* Loads to and stores from gprs can do reg+offset, and wouldn't need
13757 	     an extra register in that case, but it would need an extra
13758 	     register if the addressing is reg+reg or (reg+reg)&(-16).  */
13759 	  if (rclass == GENERAL_REGS || rclass == BASE_REGS)
13760 	    {
13761 	      if (!legitimate_indirect_address_p (addr, false)
13762 		  && !rs6000_legitimate_offset_address_p (TImode, addr,
13763 							  false, true))
13764 		{
13765 		  sri->icode = icode;
13766 		  /* account for splitting the loads, and converting the
13767 		     address from reg+reg to reg.  */
13768 		  sri->extra_cost = (((TARGET_64BIT) ? 3 : 5)
13769 				     + ((GET_CODE (addr) == AND) ? 1 : 0));
13770 		}
13771 	    }
13772 	  /* Loads to and stores from vector registers can only do reg+reg
13773 	     addressing.  Altivec registers can also do (reg+reg)&(-16).  */
13774 	  else if (rclass == VSX_REGS || rclass == ALTIVEC_REGS
13775 		   || rclass == FLOAT_REGS || rclass == NO_REGS)
13776 	    {
13777 	      if (!VECTOR_MEM_ALTIVEC_P (mode)
13778 		  && GET_CODE (addr) == AND
13779 		  && GET_CODE (XEXP (addr, 1)) == CONST_INT
13780 		  && INTVAL (XEXP (addr, 1)) == -16
13781 		  && (legitimate_indirect_address_p (XEXP (addr, 0), false)
13782 		      || legitimate_indexed_address_p (XEXP (addr, 0), false)))
13783 		{
13784 		  sri->icode = icode;
13785 		  sri->extra_cost = ((GET_CODE (XEXP (addr, 0)) == PLUS)
13786 				     ? 2 : 1);
13787 		}
13788 	      else if (!legitimate_indirect_address_p (addr, false)
13789 		       && (rclass == NO_REGS
13790 			   || !legitimate_indexed_address_p (addr, false)))
13791 		{
13792 		  sri->icode = icode;
13793 		  sri->extra_cost = 1;
13794 		}
13795 	      else
13796 		icode = CODE_FOR_nothing;
13797 	    }
13798 	  /* Any other loads, including to pseudo registers which haven't been
13799 	     assigned to a register yet, default to require a scratch
13800 	     register.  */
13801 	  else
13802 	    {
13803 	      sri->icode = icode;
13804 	      sri->extra_cost = 2;
13805 	    }
13806 	}
13807       else if (REG_P (x))
13808 	{
13809 	  int regno = true_regnum (x);
13810 
13811 	  icode = CODE_FOR_nothing;
13812 	  if (regno < 0 || regno >= FIRST_PSEUDO_REGISTER)
13813 	    default_p = true;
13814 	  else
13815 	    {
13816 	      enum reg_class xclass = REGNO_REG_CLASS (regno);
13817 	      enum reload_reg_type rtype1 = rs6000_reload_register_type (rclass);
13818 	      enum reload_reg_type rtype2 = rs6000_reload_register_type (xclass);
13819 
13820 	      /* If memory is needed, use default_secondary_reload to create the
13821 		 stack slot.  */
13822 	      if (rtype1 != rtype2 || rtype1 == OTHER_REGISTER_TYPE)
13823 		default_p = true;
13824 	      else
13825 		ret = NO_REGS;
13826 	    }
13827 	}
13828       else
13829 	default_p = true;
13830     }
13831   else if (TARGET_POWERPC64
13832 	   && rs6000_reload_register_type (rclass) == GPR_REGISTER_TYPE
13833 	   && MEM_P (x)
13834 	   && GET_MODE_SIZE (GET_MODE (x)) >= UNITS_PER_WORD)
13835     {
13836       rtx addr = XEXP (x, 0);
13837       rtx off = address_offset (addr);
13838 
13839       if (off != NULL_RTX)
13840 	{
13841 	  unsigned int extra = GET_MODE_SIZE (GET_MODE (x)) - UNITS_PER_WORD;
13842 	  unsigned HOST_WIDE_INT offset = INTVAL (off);
13843 
13844 	  /* We need a secondary reload when our legitimate_address_p
13845 	     says the address is good (as otherwise the entire address
13846 	     will be reloaded), and the offset is not a multiple of
13847 	     four or we have an address wrap.  Address wrap will only
13848 	     occur for LO_SUMs since legitimate_offset_address_p
13849 	     rejects addresses for 16-byte mems that will wrap.  */
13850 	  if (GET_CODE (addr) == LO_SUM
13851 	      ? (1 /* legitimate_address_p allows any offset for lo_sum */
13852 		 && ((offset & 3) != 0
13853 		     || ((offset & 0xffff) ^ 0x8000) >= 0x10000 - extra))
13854 	      : (offset + 0x8000 < 0x10000 - extra /* legitimate_address_p */
13855 		 && (offset & 3) != 0))
13856 	    {
13857 	      if (in_p)
13858 		sri->icode = CODE_FOR_reload_di_load;
13859 	      else
13860 		sri->icode = CODE_FOR_reload_di_store;
13861 	      sri->extra_cost = 2;
13862 	      ret = NO_REGS;
13863 	    }
13864 	  else
13865 	    default_p = true;
13866 	}
13867       else
13868 	default_p = true;
13869     }
13870   else if (!TARGET_POWERPC64
13871 	   && rs6000_reload_register_type (rclass) == GPR_REGISTER_TYPE
13872 	   && MEM_P (x)
13873 	   && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
13874     {
13875       rtx addr = XEXP (x, 0);
13876       rtx off = address_offset (addr);
13877 
13878       if (off != NULL_RTX)
13879 	{
13880 	  unsigned int extra = GET_MODE_SIZE (GET_MODE (x)) - UNITS_PER_WORD;
13881 	  unsigned HOST_WIDE_INT offset = INTVAL (off);
13882 
13883 	  /* We need a secondary reload when our legitimate_address_p
13884 	     says the address is good (as otherwise the entire address
13885 	     will be reloaded), and we have a wrap.
13886 
13887 	     legitimate_lo_sum_address_p allows LO_SUM addresses to
13888 	     have any offset so test for wrap in the low 16 bits.
13889 
13890 	     legitimate_offset_address_p checks for the range
13891 	     [-0x8000,0x7fff] for mode size of 8 and [-0x8000,0x7ff7]
13892 	     for mode size of 16.  We wrap at [0x7ffc,0x7fff] and
13893 	     [0x7ff4,0x7fff] respectively, so test for the
13894 	     intersection of these ranges, [0x7ffc,0x7fff] and
13895 	     [0x7ff4,0x7ff7] respectively.
13896 
13897 	     Note that the address we see here may have been
13898 	     manipulated by legitimize_reload_address.  */
13899 	  if (GET_CODE (addr) == LO_SUM
13900 	      ? ((offset & 0xffff) ^ 0x8000) >= 0x10000 - extra
13901 	      : offset - (0x8000 - extra) < UNITS_PER_WORD)
13902 	    {
13903 	      if (in_p)
13904 		sri->icode = CODE_FOR_reload_si_load;
13905 	      else
13906 		sri->icode = CODE_FOR_reload_si_store;
13907 	      sri->extra_cost = 2;
13908 	      ret = NO_REGS;
13909 	    }
13910 	  else
13911 	    default_p = true;
13912 	}
13913       else
13914 	default_p = true;
13915     }
13916   else
13917     default_p = true;
13918 
13919   if (default_p)
13920     ret = default_secondary_reload (in_p, x, rclass, mode, sri);
13921 
13922   gcc_assert (ret != ALL_REGS);
13923 
13924   if (TARGET_DEBUG_ADDR)
13925     {
13926       fprintf (stderr,
13927 	       "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
13928 	       "mode = %s",
13929 	       reg_class_names[ret],
13930 	       in_p ? "true" : "false",
13931 	       reg_class_names[rclass],
13932 	       GET_MODE_NAME (mode));
13933 
13934       if (default_p)
13935 	fprintf (stderr, ", default secondary reload");
13936 
13937       if (sri->icode != CODE_FOR_nothing)
13938 	fprintf (stderr, ", reload func = %s, extra cost = %d\n",
13939 		 insn_data[sri->icode].name, sri->extra_cost);
13940       else
13941 	fprintf (stderr, "\n");
13942 
13943       debug_rtx (x);
13944     }
13945 
13946   return ret;
13947 }
13948 
13949 /* Fixup reload addresses for Altivec or VSX loads/stores to change SP+offset
13950    to SP+reg addressing.  */
13951 
13952 void
rs6000_secondary_reload_inner(rtx reg,rtx mem,rtx scratch,bool store_p)13953 rs6000_secondary_reload_inner (rtx reg, rtx mem, rtx scratch, bool store_p)
13954 {
13955   int regno = true_regnum (reg);
13956   enum machine_mode mode = GET_MODE (reg);
13957   enum reg_class rclass;
13958   rtx addr;
13959   rtx and_op2 = NULL_RTX;
13960   rtx addr_op1;
13961   rtx addr_op2;
13962   rtx scratch_or_premodify = scratch;
13963   rtx and_rtx;
13964   rtx cc_clobber;
13965 
13966   if (TARGET_DEBUG_ADDR)
13967     {
13968       fprintf (stderr, "\nrs6000_secondary_reload_inner, type = %s\n",
13969 	       store_p ? "store" : "load");
13970       fprintf (stderr, "reg:\n");
13971       debug_rtx (reg);
13972       fprintf (stderr, "mem:\n");
13973       debug_rtx (mem);
13974       fprintf (stderr, "scratch:\n");
13975       debug_rtx (scratch);
13976     }
13977 
13978   gcc_assert (regno >= 0 && regno < FIRST_PSEUDO_REGISTER);
13979   gcc_assert (GET_CODE (mem) == MEM);
13980   rclass = REGNO_REG_CLASS (regno);
13981   addr = XEXP (mem, 0);
13982 
13983   switch (rclass)
13984     {
13985       /* GPRs can handle reg + small constant, all other addresses need to use
13986 	 the scratch register.  */
13987     case GENERAL_REGS:
13988     case BASE_REGS:
13989       if (GET_CODE (addr) == AND)
13990 	{
13991 	  and_op2 = XEXP (addr, 1);
13992 	  addr = XEXP (addr, 0);
13993 	}
13994 
13995       if (GET_CODE (addr) == PRE_MODIFY)
13996 	{
13997 	  scratch_or_premodify = XEXP (addr, 0);
13998 	  gcc_assert (REG_P (scratch_or_premodify));
13999 	  gcc_assert (GET_CODE (XEXP (addr, 1)) == PLUS);
14000 	  addr = XEXP (addr, 1);
14001 	}
14002 
14003       if (GET_CODE (addr) == PLUS
14004 	  && (and_op2 != NULL_RTX
14005 	      || !rs6000_legitimate_offset_address_p (TImode, addr,
14006 						      false, true)))
14007 	{
14008 	  addr_op1 = XEXP (addr, 0);
14009 	  addr_op2 = XEXP (addr, 1);
14010 	  gcc_assert (legitimate_indirect_address_p (addr_op1, false));
14011 
14012 	  if (!REG_P (addr_op2)
14013 	      && (GET_CODE (addr_op2) != CONST_INT
14014 		  || !satisfies_constraint_I (addr_op2)))
14015 	    {
14016 	      if (TARGET_DEBUG_ADDR)
14017 		{
14018 		  fprintf (stderr,
14019 			   "\nMove plus addr to register %s, mode = %s: ",
14020 			   rs6000_reg_names[REGNO (scratch)],
14021 			   GET_MODE_NAME (mode));
14022 		  debug_rtx (addr_op2);
14023 		}
14024 	      rs6000_emit_move (scratch, addr_op2, Pmode);
14025 	      addr_op2 = scratch;
14026 	    }
14027 
14028 	  emit_insn (gen_rtx_SET (VOIDmode,
14029 				  scratch_or_premodify,
14030 				  gen_rtx_PLUS (Pmode,
14031 						addr_op1,
14032 						addr_op2)));
14033 
14034 	  addr = scratch_or_premodify;
14035 	  scratch_or_premodify = scratch;
14036 	}
14037       else if (!legitimate_indirect_address_p (addr, false)
14038 	       && !rs6000_legitimate_offset_address_p (TImode, addr,
14039 						       false, true))
14040 	{
14041 	  if (TARGET_DEBUG_ADDR)
14042 	    {
14043 	      fprintf (stderr, "\nMove addr to register %s, mode = %s: ",
14044 		       rs6000_reg_names[REGNO (scratch_or_premodify)],
14045 		       GET_MODE_NAME (mode));
14046 	      debug_rtx (addr);
14047 	    }
14048 	  rs6000_emit_move (scratch_or_premodify, addr, Pmode);
14049 	  addr = scratch_or_premodify;
14050 	  scratch_or_premodify = scratch;
14051 	}
14052       break;
14053 
14054       /* Float/Altivec registers can only handle reg+reg addressing.  Move
14055 	 other addresses into a scratch register.  */
14056     case FLOAT_REGS:
14057     case VSX_REGS:
14058     case ALTIVEC_REGS:
14059 
14060       /* With float regs, we need to handle the AND ourselves, since we can't
14061 	 use the Altivec instruction with an implicit AND -16.  Allow scalar
14062 	 loads to float registers to use reg+offset even if VSX.  */
14063       if (GET_CODE (addr) == AND
14064 	  && (rclass != ALTIVEC_REGS || GET_MODE_SIZE (mode) != 16
14065 	      || GET_CODE (XEXP (addr, 1)) != CONST_INT
14066 	      || INTVAL (XEXP (addr, 1)) != -16
14067 	      || !VECTOR_MEM_ALTIVEC_P (mode)))
14068 	{
14069 	  and_op2 = XEXP (addr, 1);
14070 	  addr = XEXP (addr, 0);
14071 	}
14072 
14073       /* If we aren't using a VSX load, save the PRE_MODIFY register and use it
14074 	 as the address later.  */
14075       if (GET_CODE (addr) == PRE_MODIFY
14076 	  && (!VECTOR_MEM_VSX_P (mode)
14077 	      || and_op2 != NULL_RTX
14078 	      || !legitimate_indexed_address_p (XEXP (addr, 1), false)))
14079 	{
14080 	  scratch_or_premodify = XEXP (addr, 0);
14081 	  gcc_assert (legitimate_indirect_address_p (scratch_or_premodify,
14082 						     false));
14083 	  gcc_assert (GET_CODE (XEXP (addr, 1)) == PLUS);
14084 	  addr = XEXP (addr, 1);
14085 	}
14086 
14087       if (legitimate_indirect_address_p (addr, false)	/* reg */
14088 	  || legitimate_indexed_address_p (addr, false)	/* reg+reg */
14089 	  || GET_CODE (addr) == PRE_MODIFY		/* VSX pre-modify */
14090 	  || (GET_CODE (addr) == AND			/* Altivec memory */
14091 	      && GET_CODE (XEXP (addr, 1)) == CONST_INT
14092 	      && INTVAL (XEXP (addr, 1)) == -16
14093 	      && VECTOR_MEM_ALTIVEC_P (mode))
14094 	  || (rclass == FLOAT_REGS			/* legacy float mem */
14095 	      && GET_MODE_SIZE (mode) == 8
14096 	      && and_op2 == NULL_RTX
14097 	      && scratch_or_premodify == scratch
14098 	      && rs6000_legitimate_offset_address_p (mode, addr, false, false)))
14099 	;
14100 
14101       else if (GET_CODE (addr) == PLUS)
14102 	{
14103 	  addr_op1 = XEXP (addr, 0);
14104 	  addr_op2 = XEXP (addr, 1);
14105 	  gcc_assert (REG_P (addr_op1));
14106 
14107 	  if (TARGET_DEBUG_ADDR)
14108 	    {
14109 	      fprintf (stderr, "\nMove plus addr to register %s, mode = %s: ",
14110 		       rs6000_reg_names[REGNO (scratch)], GET_MODE_NAME (mode));
14111 	      debug_rtx (addr_op2);
14112 	    }
14113 	  rs6000_emit_move (scratch, addr_op2, Pmode);
14114 	  emit_insn (gen_rtx_SET (VOIDmode,
14115 				  scratch_or_premodify,
14116 				  gen_rtx_PLUS (Pmode,
14117 						addr_op1,
14118 						scratch)));
14119 	  addr = scratch_or_premodify;
14120 	  scratch_or_premodify = scratch;
14121 	}
14122 
14123       else if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == CONST
14124 	       || GET_CODE (addr) == CONST_INT || REG_P (addr))
14125 	{
14126 	  if (TARGET_DEBUG_ADDR)
14127 	    {
14128 	      fprintf (stderr, "\nMove addr to register %s, mode = %s: ",
14129 		       rs6000_reg_names[REGNO (scratch_or_premodify)],
14130 		       GET_MODE_NAME (mode));
14131 	      debug_rtx (addr);
14132 	    }
14133 
14134 	  rs6000_emit_move (scratch_or_premodify, addr, Pmode);
14135 	  addr = scratch_or_premodify;
14136 	  scratch_or_premodify = scratch;
14137 	}
14138 
14139       else
14140 	gcc_unreachable ();
14141 
14142       break;
14143 
14144     default:
14145       gcc_unreachable ();
14146     }
14147 
14148   /* If the original address involved a pre-modify that we couldn't use the VSX
14149      memory instruction with update, and we haven't taken care of already,
14150      store the address in the pre-modify register and use that as the
14151      address.  */
14152   if (scratch_or_premodify != scratch && scratch_or_premodify != addr)
14153     {
14154       emit_insn (gen_rtx_SET (VOIDmode, scratch_or_premodify, addr));
14155       addr = scratch_or_premodify;
14156     }
14157 
14158   /* If the original address involved an AND -16 and we couldn't use an ALTIVEC
14159      memory instruction, recreate the AND now, including the clobber which is
14160      generated by the general ANDSI3/ANDDI3 patterns for the
14161      andi. instruction.  */
14162   if (and_op2 != NULL_RTX)
14163     {
14164       if (! legitimate_indirect_address_p (addr, false))
14165 	{
14166 	  emit_insn (gen_rtx_SET (VOIDmode, scratch, addr));
14167 	  addr = scratch;
14168 	}
14169 
14170       if (TARGET_DEBUG_ADDR)
14171 	{
14172 	  fprintf (stderr, "\nAnd addr to register %s, mode = %s: ",
14173 		   rs6000_reg_names[REGNO (scratch)], GET_MODE_NAME (mode));
14174 	  debug_rtx (and_op2);
14175 	}
14176 
14177       and_rtx = gen_rtx_SET (VOIDmode,
14178 			     scratch,
14179 			     gen_rtx_AND (Pmode,
14180 					  addr,
14181 					  and_op2));
14182 
14183       cc_clobber = gen_rtx_CLOBBER (CCmode, gen_rtx_SCRATCH (CCmode));
14184       emit_insn (gen_rtx_PARALLEL (VOIDmode,
14185 				   gen_rtvec (2, and_rtx, cc_clobber)));
14186       addr = scratch;
14187     }
14188 
14189   /* Adjust the address if it changed.  */
14190   if (addr != XEXP (mem, 0))
14191     {
14192       mem = change_address (mem, mode, addr);
14193       if (TARGET_DEBUG_ADDR)
14194 	fprintf (stderr, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
14195     }
14196 
14197   /* Now create the move.  */
14198   if (store_p)
14199     emit_insn (gen_rtx_SET (VOIDmode, mem, reg));
14200   else
14201     emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
14202 
14203   return;
14204 }
14205 
14206 /* Convert reloads involving 64-bit gprs and misaligned offset
14207    addressing, or multiple 32-bit gprs and offsets that are too large,
14208    to use indirect addressing.  */
14209 
14210 void
rs6000_secondary_reload_gpr(rtx reg,rtx mem,rtx scratch,bool store_p)14211 rs6000_secondary_reload_gpr (rtx reg, rtx mem, rtx scratch, bool store_p)
14212 {
14213   int regno = true_regnum (reg);
14214   enum reg_class rclass;
14215   rtx addr;
14216   rtx scratch_or_premodify = scratch;
14217 
14218   if (TARGET_DEBUG_ADDR)
14219     {
14220       fprintf (stderr, "\nrs6000_secondary_reload_gpr, type = %s\n",
14221 	       store_p ? "store" : "load");
14222       fprintf (stderr, "reg:\n");
14223       debug_rtx (reg);
14224       fprintf (stderr, "mem:\n");
14225       debug_rtx (mem);
14226       fprintf (stderr, "scratch:\n");
14227       debug_rtx (scratch);
14228     }
14229 
14230   gcc_assert (regno >= 0 && regno < FIRST_PSEUDO_REGISTER);
14231   gcc_assert (GET_CODE (mem) == MEM);
14232   rclass = REGNO_REG_CLASS (regno);
14233   gcc_assert (rclass == GENERAL_REGS || rclass == BASE_REGS);
14234   addr = XEXP (mem, 0);
14235 
14236   if (GET_CODE (addr) == PRE_MODIFY)
14237     {
14238       scratch_or_premodify = XEXP (addr, 0);
14239       gcc_assert (REG_P (scratch_or_premodify));
14240       addr = XEXP (addr, 1);
14241     }
14242   gcc_assert (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM);
14243 
14244   rs6000_emit_move (scratch_or_premodify, addr, Pmode);
14245 
14246   mem = replace_equiv_address_nv (mem, scratch_or_premodify);
14247 
14248   /* Now create the move.  */
14249   if (store_p)
14250     emit_insn (gen_rtx_SET (VOIDmode, mem, reg));
14251   else
14252     emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
14253 
14254   return;
14255 }
14256 
14257 /* Allocate a 64-bit stack slot to be used for copying SDmode
14258    values through if this function has any SDmode references.  */
14259 
14260 static void
rs6000_alloc_sdmode_stack_slot(void)14261 rs6000_alloc_sdmode_stack_slot (void)
14262 {
14263   tree t;
14264   basic_block bb;
14265   gimple_stmt_iterator gsi;
14266 
14267   gcc_assert (cfun->machine->sdmode_stack_slot == NULL_RTX);
14268 
14269   FOR_EACH_BB (bb)
14270     for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
14271       {
14272 	tree ret = walk_gimple_op (gsi_stmt (gsi), rs6000_check_sdmode, NULL);
14273 	if (ret)
14274 	  {
14275 	    rtx stack = assign_stack_local (DDmode, GET_MODE_SIZE (DDmode), 0);
14276 	    cfun->machine->sdmode_stack_slot = adjust_address_nv (stack,
14277 								  SDmode, 0);
14278 	    return;
14279 	  }
14280       }
14281 
14282   /* Check for any SDmode parameters of the function.  */
14283   for (t = DECL_ARGUMENTS (cfun->decl); t; t = DECL_CHAIN (t))
14284     {
14285       if (TREE_TYPE (t) == error_mark_node)
14286 	continue;
14287 
14288       if (TYPE_MODE (TREE_TYPE (t)) == SDmode
14289 	  || TYPE_MODE (DECL_ARG_TYPE (t)) == SDmode)
14290 	{
14291 	  rtx stack = assign_stack_local (DDmode, GET_MODE_SIZE (DDmode), 0);
14292 	  cfun->machine->sdmode_stack_slot = adjust_address_nv (stack,
14293 								SDmode, 0);
14294 	  return;
14295 	}
14296     }
14297 }
14298 
14299 static void
rs6000_instantiate_decls(void)14300 rs6000_instantiate_decls (void)
14301 {
14302   if (cfun->machine->sdmode_stack_slot != NULL_RTX)
14303     instantiate_decl_rtl (cfun->machine->sdmode_stack_slot);
14304 }
14305 
14306 /* Given an rtx X being reloaded into a reg required to be
14307    in class CLASS, return the class of reg to actually use.
14308    In general this is just CLASS; but on some machines
14309    in some cases it is preferable to use a more restrictive class.
14310 
14311    On the RS/6000, we have to return NO_REGS when we want to reload a
14312    floating-point CONST_DOUBLE to force it to be copied to memory.
14313 
14314    We also don't want to reload integer values into floating-point
14315    registers if we can at all help it.  In fact, this can
14316    cause reload to die, if it tries to generate a reload of CTR
14317    into a FP register and discovers it doesn't have the memory location
14318    required.
14319 
14320    ??? Would it be a good idea to have reload do the converse, that is
14321    try to reload floating modes into FP registers if possible?
14322  */
14323 
14324 static enum reg_class
rs6000_preferred_reload_class(rtx x,enum reg_class rclass)14325 rs6000_preferred_reload_class (rtx x, enum reg_class rclass)
14326 {
14327   enum machine_mode mode = GET_MODE (x);
14328 
14329   if (VECTOR_UNIT_VSX_P (mode)
14330       && x == CONST0_RTX (mode) && VSX_REG_CLASS_P (rclass))
14331     return rclass;
14332 
14333   if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
14334       && (rclass == ALTIVEC_REGS || rclass == VSX_REGS)
14335       && easy_vector_constant (x, mode))
14336     return ALTIVEC_REGS;
14337 
14338   if (CONSTANT_P (x) && reg_classes_intersect_p (rclass, FLOAT_REGS))
14339     return NO_REGS;
14340 
14341   if (GET_MODE_CLASS (mode) == MODE_INT && rclass == NON_SPECIAL_REGS)
14342     return GENERAL_REGS;
14343 
14344   /* For VSX, prefer the traditional registers for 64-bit values because we can
14345      use the non-VSX loads.  Prefer the Altivec registers if Altivec is
14346      handling the vector operations (i.e. V16QI, V8HI, and V4SI), or if we
14347      prefer Altivec loads..  */
14348   if (rclass == VSX_REGS)
14349     {
14350       if (GET_MODE_SIZE (mode) <= 8)
14351 	return FLOAT_REGS;
14352 
14353       if (VECTOR_UNIT_ALTIVEC_P (mode) || VECTOR_MEM_ALTIVEC_P (mode))
14354 	return ALTIVEC_REGS;
14355 
14356       return rclass;
14357     }
14358 
14359   return rclass;
14360 }
14361 
14362 /* Debug version of rs6000_preferred_reload_class.  */
14363 static enum reg_class
rs6000_debug_preferred_reload_class(rtx x,enum reg_class rclass)14364 rs6000_debug_preferred_reload_class (rtx x, enum reg_class rclass)
14365 {
14366   enum reg_class ret = rs6000_preferred_reload_class (x, rclass);
14367 
14368   fprintf (stderr,
14369 	   "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
14370 	   "mode = %s, x:\n",
14371 	   reg_class_names[ret], reg_class_names[rclass],
14372 	   GET_MODE_NAME (GET_MODE (x)));
14373   debug_rtx (x);
14374 
14375   return ret;
14376 }
14377 
14378 /* If we are copying between FP or AltiVec registers and anything else, we need
14379    a memory location.  The exception is when we are targeting ppc64 and the
14380    move to/from fpr to gpr instructions are available.  Also, under VSX, you
14381    can copy vector registers from the FP register set to the Altivec register
14382    set and vice versa.  */
14383 
14384 static bool
rs6000_secondary_memory_needed(enum reg_class class1,enum reg_class class2,enum machine_mode mode)14385 rs6000_secondary_memory_needed (enum reg_class class1,
14386 				enum reg_class class2,
14387 				enum machine_mode mode)
14388 {
14389   if (class1 == class2)
14390     return false;
14391 
14392   /* Under VSX, there are 3 register classes that values could be in (VSX_REGS,
14393      ALTIVEC_REGS, and FLOAT_REGS).  We don't need to use memory to copy
14394      between these classes.  But we need memory for other things that can go in
14395      FLOAT_REGS like SFmode.  */
14396   if (TARGET_VSX
14397       && (VECTOR_MEM_VSX_P (mode) || VECTOR_UNIT_VSX_P (mode))
14398       && (class1 == VSX_REGS || class1 == ALTIVEC_REGS
14399 	  || class1 == FLOAT_REGS))
14400     return (class2 != VSX_REGS && class2 != ALTIVEC_REGS
14401 	    && class2 != FLOAT_REGS);
14402 
14403   if (class1 == VSX_REGS || class2 == VSX_REGS)
14404     return true;
14405 
14406   if (class1 == FLOAT_REGS
14407       && (!TARGET_MFPGPR || !TARGET_POWERPC64
14408 	  || ((mode != DFmode)
14409 	      && (mode != DDmode)
14410 	      && (mode != DImode))))
14411     return true;
14412 
14413   if (class2 == FLOAT_REGS
14414       && (!TARGET_MFPGPR || !TARGET_POWERPC64
14415 	  || ((mode != DFmode)
14416 	      && (mode != DDmode)
14417 	      && (mode != DImode))))
14418     return true;
14419 
14420   if (class1 == ALTIVEC_REGS || class2 == ALTIVEC_REGS)
14421     return true;
14422 
14423   return false;
14424 }
14425 
14426 /* Debug version of rs6000_secondary_memory_needed.  */
14427 static bool
rs6000_debug_secondary_memory_needed(enum reg_class class1,enum reg_class class2,enum machine_mode mode)14428 rs6000_debug_secondary_memory_needed (enum reg_class class1,
14429 				      enum reg_class class2,
14430 				      enum machine_mode mode)
14431 {
14432   bool ret = rs6000_secondary_memory_needed (class1, class2, mode);
14433 
14434   fprintf (stderr,
14435 	   "rs6000_secondary_memory_needed, return: %s, class1 = %s, "
14436 	   "class2 = %s, mode = %s\n",
14437 	   ret ? "true" : "false", reg_class_names[class1],
14438 	   reg_class_names[class2], GET_MODE_NAME (mode));
14439 
14440   return ret;
14441 }
14442 
14443 /* Return the register class of a scratch register needed to copy IN into
14444    or out of a register in RCLASS in MODE.  If it can be done directly,
14445    NO_REGS is returned.  */
14446 
14447 static enum reg_class
rs6000_secondary_reload_class(enum reg_class rclass,enum machine_mode mode,rtx in)14448 rs6000_secondary_reload_class (enum reg_class rclass, enum machine_mode mode,
14449 			       rtx in)
14450 {
14451   int regno;
14452 
14453   if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
14454 #if TARGET_MACHO
14455 		     && MACHOPIC_INDIRECT
14456 #endif
14457 		     ))
14458     {
14459       /* We cannot copy a symbolic operand directly into anything
14460 	 other than BASE_REGS for TARGET_ELF.  So indicate that a
14461 	 register from BASE_REGS is needed as an intermediate
14462 	 register.
14463 
14464 	 On Darwin, pic addresses require a load from memory, which
14465 	 needs a base register.  */
14466       if (rclass != BASE_REGS
14467 	  && (GET_CODE (in) == SYMBOL_REF
14468 	      || GET_CODE (in) == HIGH
14469 	      || GET_CODE (in) == LABEL_REF
14470 	      || GET_CODE (in) == CONST))
14471 	return BASE_REGS;
14472     }
14473 
14474   if (GET_CODE (in) == REG)
14475     {
14476       regno = REGNO (in);
14477       if (regno >= FIRST_PSEUDO_REGISTER)
14478 	{
14479 	  regno = true_regnum (in);
14480 	  if (regno >= FIRST_PSEUDO_REGISTER)
14481 	    regno = -1;
14482 	}
14483     }
14484   else if (GET_CODE (in) == SUBREG)
14485     {
14486       regno = true_regnum (in);
14487       if (regno >= FIRST_PSEUDO_REGISTER)
14488 	regno = -1;
14489     }
14490   else
14491     regno = -1;
14492 
14493   /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
14494      into anything.  */
14495   if (rclass == GENERAL_REGS || rclass == BASE_REGS
14496       || (regno >= 0 && INT_REGNO_P (regno)))
14497     return NO_REGS;
14498 
14499   /* Constants, memory, and FP registers can go into FP registers.  */
14500   if ((regno == -1 || FP_REGNO_P (regno))
14501       && (rclass == FLOAT_REGS || rclass == NON_SPECIAL_REGS))
14502     return (mode != SDmode) ? NO_REGS : GENERAL_REGS;
14503 
14504   /* Memory, and FP/altivec registers can go into fp/altivec registers under
14505      VSX.  */
14506   if (TARGET_VSX
14507       && (regno == -1 || VSX_REGNO_P (regno))
14508       && VSX_REG_CLASS_P (rclass))
14509     return NO_REGS;
14510 
14511   /* Memory, and AltiVec registers can go into AltiVec registers.  */
14512   if ((regno == -1 || ALTIVEC_REGNO_P (regno))
14513       && rclass == ALTIVEC_REGS)
14514     return NO_REGS;
14515 
14516   /* We can copy among the CR registers.  */
14517   if ((rclass == CR_REGS || rclass == CR0_REGS)
14518       && regno >= 0 && CR_REGNO_P (regno))
14519     return NO_REGS;
14520 
14521   /* Otherwise, we need GENERAL_REGS.  */
14522   return GENERAL_REGS;
14523 }
14524 
14525 /* Debug version of rs6000_secondary_reload_class.  */
14526 static enum reg_class
rs6000_debug_secondary_reload_class(enum reg_class rclass,enum machine_mode mode,rtx in)14527 rs6000_debug_secondary_reload_class (enum reg_class rclass,
14528 				     enum machine_mode mode, rtx in)
14529 {
14530   enum reg_class ret = rs6000_secondary_reload_class (rclass, mode, in);
14531   fprintf (stderr,
14532 	   "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
14533 	   "mode = %s, input rtx:\n",
14534 	   reg_class_names[ret], reg_class_names[rclass],
14535 	   GET_MODE_NAME (mode));
14536   debug_rtx (in);
14537 
14538   return ret;
14539 }
14540 
14541 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid.  */
14542 
14543 static bool
rs6000_cannot_change_mode_class(enum machine_mode from,enum machine_mode to,enum reg_class rclass)14544 rs6000_cannot_change_mode_class (enum machine_mode from,
14545 				 enum machine_mode to,
14546 				 enum reg_class rclass)
14547 {
14548   unsigned from_size = GET_MODE_SIZE (from);
14549   unsigned to_size = GET_MODE_SIZE (to);
14550 
14551   if (from_size != to_size)
14552     {
14553       enum reg_class xclass = (TARGET_VSX) ? VSX_REGS : FLOAT_REGS;
14554       return ((from_size < 8 || to_size < 8 || TARGET_IEEEQUAD)
14555 	      && reg_classes_intersect_p (xclass, rclass));
14556     }
14557 
14558   if (TARGET_E500_DOUBLE
14559       && ((((to) == DFmode) + ((from) == DFmode)) == 1
14560 	  || (((to) == TFmode) + ((from) == TFmode)) == 1
14561 	  || (((to) == DDmode) + ((from) == DDmode)) == 1
14562 	  || (((to) == TDmode) + ((from) == TDmode)) == 1
14563 	  || (((to) == DImode) + ((from) == DImode)) == 1))
14564     return true;
14565 
14566   /* Since the VSX register set includes traditional floating point registers
14567      and altivec registers, just check for the size being different instead of
14568      trying to check whether the modes are vector modes.  Otherwise it won't
14569      allow say DF and DI to change classes.  */
14570   if (TARGET_VSX && VSX_REG_CLASS_P (rclass))
14571     return (from_size != 8 && from_size != 16);
14572 
14573   if (TARGET_ALTIVEC && rclass == ALTIVEC_REGS
14574       && (ALTIVEC_VECTOR_MODE (from) + ALTIVEC_VECTOR_MODE (to)) == 1)
14575     return true;
14576 
14577   if (TARGET_SPE && (SPE_VECTOR_MODE (from) + SPE_VECTOR_MODE (to)) == 1
14578       && reg_classes_intersect_p (GENERAL_REGS, rclass))
14579     return true;
14580 
14581   return false;
14582 }
14583 
14584 /* Debug version of rs6000_cannot_change_mode_class.  */
14585 static bool
rs6000_debug_cannot_change_mode_class(enum machine_mode from,enum machine_mode to,enum reg_class rclass)14586 rs6000_debug_cannot_change_mode_class (enum machine_mode from,
14587 				       enum machine_mode to,
14588 				       enum reg_class rclass)
14589 {
14590   bool ret = rs6000_cannot_change_mode_class (from, to, rclass);
14591 
14592   fprintf (stderr,
14593 	   "rs6000_cannot_change_mode_class, return %s, from = %s, "
14594 	   "to = %s, rclass = %s\n",
14595 	   ret ? "true" : "false",
14596 	   GET_MODE_NAME (from), GET_MODE_NAME (to),
14597 	   reg_class_names[rclass]);
14598 
14599   return ret;
14600 }
14601 
14602 /* Given a comparison operation, return the bit number in CCR to test.  We
14603    know this is a valid comparison.
14604 
14605    SCC_P is 1 if this is for an scc.  That means that %D will have been
14606    used instead of %C, so the bits will be in different places.
14607 
14608    Return -1 if OP isn't a valid comparison for some reason.  */
14609 
14610 int
ccr_bit(rtx op,int scc_p)14611 ccr_bit (rtx op, int scc_p)
14612 {
14613   enum rtx_code code = GET_CODE (op);
14614   enum machine_mode cc_mode;
14615   int cc_regnum;
14616   int base_bit;
14617   rtx reg;
14618 
14619   if (!COMPARISON_P (op))
14620     return -1;
14621 
14622   reg = XEXP (op, 0);
14623 
14624   gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
14625 
14626   cc_mode = GET_MODE (reg);
14627   cc_regnum = REGNO (reg);
14628   base_bit = 4 * (cc_regnum - CR0_REGNO);
14629 
14630   validate_condition_mode (code, cc_mode);
14631 
14632   /* When generating a sCOND operation, only positive conditions are
14633      allowed.  */
14634   gcc_assert (!scc_p
14635 	      || code == EQ || code == GT || code == LT || code == UNORDERED
14636 	      || code == GTU || code == LTU);
14637 
14638   switch (code)
14639     {
14640     case NE:
14641       return scc_p ? base_bit + 3 : base_bit + 2;
14642     case EQ:
14643       return base_bit + 2;
14644     case GT:  case GTU:  case UNLE:
14645       return base_bit + 1;
14646     case LT:  case LTU:  case UNGE:
14647       return base_bit;
14648     case ORDERED:  case UNORDERED:
14649       return base_bit + 3;
14650 
14651     case GE:  case GEU:
14652       /* If scc, we will have done a cror to put the bit in the
14653 	 unordered position.  So test that bit.  For integer, this is ! LT
14654 	 unless this is an scc insn.  */
14655       return scc_p ? base_bit + 3 : base_bit;
14656 
14657     case LE:  case LEU:
14658       return scc_p ? base_bit + 3 : base_bit + 1;
14659 
14660     default:
14661       gcc_unreachable ();
14662     }
14663 }
14664 
14665 /* Return the GOT register.  */
14666 
14667 rtx
rs6000_got_register(rtx value ATTRIBUTE_UNUSED)14668 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
14669 {
14670   /* The second flow pass currently (June 1999) can't update
14671      regs_ever_live without disturbing other parts of the compiler, so
14672      update it here to make the prolog/epilogue code happy.  */
14673   if (!can_create_pseudo_p ()
14674       && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
14675     df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM, true);
14676 
14677   crtl->uses_pic_offset_table = 1;
14678 
14679   return pic_offset_table_rtx;
14680 }
14681 
14682 static rs6000_stack_t stack_info;
14683 
14684 /* Function to init struct machine_function.
14685    This will be called, via a pointer variable,
14686    from push_function_context.  */
14687 
14688 static struct machine_function *
rs6000_init_machine_status(void)14689 rs6000_init_machine_status (void)
14690 {
14691   stack_info.reload_completed = 0;
14692   return ggc_alloc_cleared_machine_function ();
14693 }
14694 
14695 /* These macros test for integers and extract the low-order bits.  */
14696 #define INT_P(X)  \
14697 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE)	\
14698  && GET_MODE (X) == VOIDmode)
14699 
14700 #define INT_LOWPART(X) \
14701   (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
14702 
14703 int
extract_MB(rtx op)14704 extract_MB (rtx op)
14705 {
14706   int i;
14707   unsigned long val = INT_LOWPART (op);
14708 
14709   /* If the high bit is zero, the value is the first 1 bit we find
14710      from the left.  */
14711   if ((val & 0x80000000) == 0)
14712     {
14713       gcc_assert (val & 0xffffffff);
14714 
14715       i = 1;
14716       while (((val <<= 1) & 0x80000000) == 0)
14717 	++i;
14718       return i;
14719     }
14720 
14721   /* If the high bit is set and the low bit is not, or the mask is all
14722      1's, the value is zero.  */
14723   if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
14724     return 0;
14725 
14726   /* Otherwise we have a wrap-around mask.  Look for the first 0 bit
14727      from the right.  */
14728   i = 31;
14729   while (((val >>= 1) & 1) != 0)
14730     --i;
14731 
14732   return i;
14733 }
14734 
14735 int
extract_ME(rtx op)14736 extract_ME (rtx op)
14737 {
14738   int i;
14739   unsigned long val = INT_LOWPART (op);
14740 
14741   /* If the low bit is zero, the value is the first 1 bit we find from
14742      the right.  */
14743   if ((val & 1) == 0)
14744     {
14745       gcc_assert (val & 0xffffffff);
14746 
14747       i = 30;
14748       while (((val >>= 1) & 1) == 0)
14749 	--i;
14750 
14751       return i;
14752     }
14753 
14754   /* If the low bit is set and the high bit is not, or the mask is all
14755      1's, the value is 31.  */
14756   if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
14757     return 31;
14758 
14759   /* Otherwise we have a wrap-around mask.  Look for the first 0 bit
14760      from the left.  */
14761   i = 0;
14762   while (((val <<= 1) & 0x80000000) != 0)
14763     ++i;
14764 
14765   return i;
14766 }
14767 
14768 /* Locate some local-dynamic symbol still in use by this function
14769    so that we can print its name in some tls_ld pattern.  */
14770 
14771 static const char *
rs6000_get_some_local_dynamic_name(void)14772 rs6000_get_some_local_dynamic_name (void)
14773 {
14774   rtx insn;
14775 
14776   if (cfun->machine->some_ld_name)
14777     return cfun->machine->some_ld_name;
14778 
14779   for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
14780     if (INSN_P (insn)
14781 	&& for_each_rtx (&PATTERN (insn),
14782 			 rs6000_get_some_local_dynamic_name_1, 0))
14783       return cfun->machine->some_ld_name;
14784 
14785   gcc_unreachable ();
14786 }
14787 
14788 /* Helper function for rs6000_get_some_local_dynamic_name.  */
14789 
14790 static int
rs6000_get_some_local_dynamic_name_1(rtx * px,void * data ATTRIBUTE_UNUSED)14791 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
14792 {
14793   rtx x = *px;
14794 
14795   if (GET_CODE (x) == SYMBOL_REF)
14796     {
14797       const char *str = XSTR (x, 0);
14798       if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
14799 	{
14800 	  cfun->machine->some_ld_name = str;
14801 	  return 1;
14802 	}
14803     }
14804 
14805   return 0;
14806 }
14807 
14808 /* Write out a function code label.  */
14809 
14810 void
rs6000_output_function_entry(FILE * file,const char * fname)14811 rs6000_output_function_entry (FILE *file, const char *fname)
14812 {
14813   if (fname[0] != '.')
14814     {
14815       switch (DEFAULT_ABI)
14816 	{
14817 	default:
14818 	  gcc_unreachable ();
14819 
14820 	case ABI_AIX:
14821 	  if (DOT_SYMBOLS)
14822 	    putc ('.', file);
14823 	  else
14824 	    ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
14825 	  break;
14826 
14827 	case ABI_V4:
14828 	case ABI_DARWIN:
14829 	  break;
14830 	}
14831     }
14832 
14833   RS6000_OUTPUT_BASENAME (file, fname);
14834 }
14835 
14836 /* Print an operand.  Recognize special options, documented below.  */
14837 
14838 #if TARGET_ELF
14839 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
14840 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
14841 #else
14842 #define SMALL_DATA_RELOC "sda21"
14843 #define SMALL_DATA_REG 0
14844 #endif
14845 
14846 void
print_operand(FILE * file,rtx x,int code)14847 print_operand (FILE *file, rtx x, int code)
14848 {
14849   int i;
14850   unsigned HOST_WIDE_INT uval;
14851 
14852   switch (code)
14853     {
14854       /* %a is output_address.  */
14855 
14856     case 'b':
14857       /* If constant, low-order 16 bits of constant, unsigned.
14858 	 Otherwise, write normally.  */
14859       if (INT_P (x))
14860 	fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
14861       else
14862 	print_operand (file, x, 0);
14863       return;
14864 
14865     case 'B':
14866       /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
14867 	 for 64-bit mask direction.  */
14868       putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
14869       return;
14870 
14871       /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
14872 	 output_operand.  */
14873 
14874     case 'D':
14875       /* Like 'J' but get to the GT bit only.  */
14876       gcc_assert (REG_P (x));
14877 
14878       /* Bit 1 is GT bit.  */
14879       i = 4 * (REGNO (x) - CR0_REGNO) + 1;
14880 
14881       /* Add one for shift count in rlinm for scc.  */
14882       fprintf (file, "%d", i + 1);
14883       return;
14884 
14885     case 'E':
14886       /* X is a CR register.  Print the number of the EQ bit of the CR */
14887       if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
14888 	output_operand_lossage ("invalid %%E value");
14889       else
14890 	fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
14891       return;
14892 
14893     case 'f':
14894       /* X is a CR register.  Print the shift count needed to move it
14895 	 to the high-order four bits.  */
14896       if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
14897 	output_operand_lossage ("invalid %%f value");
14898       else
14899 	fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
14900       return;
14901 
14902     case 'F':
14903       /* Similar, but print the count for the rotate in the opposite
14904 	 direction.  */
14905       if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
14906 	output_operand_lossage ("invalid %%F value");
14907       else
14908 	fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
14909       return;
14910 
14911     case 'G':
14912       /* X is a constant integer.  If it is negative, print "m",
14913 	 otherwise print "z".  This is to make an aze or ame insn.  */
14914       if (GET_CODE (x) != CONST_INT)
14915 	output_operand_lossage ("invalid %%G value");
14916       else if (INTVAL (x) >= 0)
14917 	putc ('z', file);
14918       else
14919 	putc ('m', file);
14920       return;
14921 
14922     case 'h':
14923       /* If constant, output low-order five bits.  Otherwise, write
14924 	 normally.  */
14925       if (INT_P (x))
14926 	fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
14927       else
14928 	print_operand (file, x, 0);
14929       return;
14930 
14931     case 'H':
14932       /* If constant, output low-order six bits.  Otherwise, write
14933 	 normally.  */
14934       if (INT_P (x))
14935 	fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
14936       else
14937 	print_operand (file, x, 0);
14938       return;
14939 
14940     case 'I':
14941       /* Print `i' if this is a constant, else nothing.  */
14942       if (INT_P (x))
14943 	putc ('i', file);
14944       return;
14945 
14946     case 'j':
14947       /* Write the bit number in CCR for jump.  */
14948       i = ccr_bit (x, 0);
14949       if (i == -1)
14950 	output_operand_lossage ("invalid %%j code");
14951       else
14952 	fprintf (file, "%d", i);
14953       return;
14954 
14955     case 'J':
14956       /* Similar, but add one for shift count in rlinm for scc and pass
14957 	 scc flag to `ccr_bit'.  */
14958       i = ccr_bit (x, 1);
14959       if (i == -1)
14960 	output_operand_lossage ("invalid %%J code");
14961       else
14962 	/* If we want bit 31, write a shift count of zero, not 32.  */
14963 	fprintf (file, "%d", i == 31 ? 0 : i + 1);
14964       return;
14965 
14966     case 'k':
14967       /* X must be a constant.  Write the 1's complement of the
14968 	 constant.  */
14969       if (! INT_P (x))
14970 	output_operand_lossage ("invalid %%k value");
14971       else
14972 	fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
14973       return;
14974 
14975     case 'K':
14976       /* X must be a symbolic constant on ELF.  Write an
14977 	 expression suitable for an 'addi' that adds in the low 16
14978 	 bits of the MEM.  */
14979       if (GET_CODE (x) == CONST)
14980 	{
14981 	  if (GET_CODE (XEXP (x, 0)) != PLUS
14982 	      || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
14983 		  && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
14984 	      || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
14985 	    output_operand_lossage ("invalid %%K value");
14986 	}
14987       print_operand_address (file, x);
14988       fputs ("@l", file);
14989       return;
14990 
14991       /* %l is output_asm_label.  */
14992 
14993     case 'L':
14994       /* Write second word of DImode or DFmode reference.  Works on register
14995 	 or non-indexed memory only.  */
14996       if (REG_P (x))
14997 	fputs (reg_names[REGNO (x) + 1], file);
14998       else if (MEM_P (x))
14999 	{
15000 	  /* Handle possible auto-increment.  Since it is pre-increment and
15001 	     we have already done it, we can just use an offset of word.  */
15002 	  if (GET_CODE (XEXP (x, 0)) == PRE_INC
15003 	      || GET_CODE (XEXP (x, 0)) == PRE_DEC)
15004 	    output_address (plus_constant (Pmode, XEXP (XEXP (x, 0), 0),
15005 					   UNITS_PER_WORD));
15006 	  else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
15007 	    output_address (plus_constant (Pmode, XEXP (XEXP (x, 0), 0),
15008 					   UNITS_PER_WORD));
15009 	  else
15010 	    output_address (XEXP (adjust_address_nv (x, SImode,
15011 						     UNITS_PER_WORD),
15012 				  0));
15013 
15014 	  if (small_data_operand (x, GET_MODE (x)))
15015 	    fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
15016 		     reg_names[SMALL_DATA_REG]);
15017 	}
15018       return;
15019 
15020     case 'm':
15021       /* MB value for a mask operand.  */
15022       if (! mask_operand (x, SImode))
15023 	output_operand_lossage ("invalid %%m value");
15024 
15025       fprintf (file, "%d", extract_MB (x));
15026       return;
15027 
15028     case 'M':
15029       /* ME value for a mask operand.  */
15030       if (! mask_operand (x, SImode))
15031 	output_operand_lossage ("invalid %%M value");
15032 
15033       fprintf (file, "%d", extract_ME (x));
15034       return;
15035 
15036       /* %n outputs the negative of its operand.  */
15037 
15038     case 'N':
15039       /* Write the number of elements in the vector times 4.  */
15040       if (GET_CODE (x) != PARALLEL)
15041 	output_operand_lossage ("invalid %%N value");
15042       else
15043 	fprintf (file, "%d", XVECLEN (x, 0) * 4);
15044       return;
15045 
15046     case 'O':
15047       /* Similar, but subtract 1 first.  */
15048       if (GET_CODE (x) != PARALLEL)
15049 	output_operand_lossage ("invalid %%O value");
15050       else
15051 	fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
15052       return;
15053 
15054     case 'p':
15055       /* X is a CONST_INT that is a power of two.  Output the logarithm.  */
15056       if (! INT_P (x)
15057 	  || INT_LOWPART (x) < 0
15058 	  || (i = exact_log2 (INT_LOWPART (x))) < 0)
15059 	output_operand_lossage ("invalid %%p value");
15060       else
15061 	fprintf (file, "%d", i);
15062       return;
15063 
15064     case 'P':
15065       /* The operand must be an indirect memory reference.  The result
15066 	 is the register name.  */
15067       if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
15068 	  || REGNO (XEXP (x, 0)) >= 32)
15069 	output_operand_lossage ("invalid %%P value");
15070       else
15071 	fputs (reg_names[REGNO (XEXP (x, 0))], file);
15072       return;
15073 
15074     case 'q':
15075       /* This outputs the logical code corresponding to a boolean
15076 	 expression.  The expression may have one or both operands
15077 	 negated (if one, only the first one).  For condition register
15078 	 logical operations, it will also treat the negated
15079 	 CR codes as NOTs, but not handle NOTs of them.  */
15080       {
15081 	const char *const *t = 0;
15082 	const char *s;
15083 	enum rtx_code code = GET_CODE (x);
15084 	static const char * const tbl[3][3] = {
15085 	  { "and", "andc", "nor" },
15086 	  { "or", "orc", "nand" },
15087 	  { "xor", "eqv", "xor" } };
15088 
15089 	if (code == AND)
15090 	  t = tbl[0];
15091 	else if (code == IOR)
15092 	  t = tbl[1];
15093 	else if (code == XOR)
15094 	  t = tbl[2];
15095 	else
15096 	  output_operand_lossage ("invalid %%q value");
15097 
15098 	if (GET_CODE (XEXP (x, 0)) != NOT)
15099 	  s = t[0];
15100 	else
15101 	  {
15102 	    if (GET_CODE (XEXP (x, 1)) == NOT)
15103 	      s = t[2];
15104 	    else
15105 	      s = t[1];
15106 	  }
15107 
15108 	fputs (s, file);
15109       }
15110       return;
15111 
15112     case 'Q':
15113       if (! TARGET_MFCRF)
15114 	return;
15115       fputc (',', file);
15116       /* FALLTHRU */
15117 
15118     case 'R':
15119       /* X is a CR register.  Print the mask for `mtcrf'.  */
15120       if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
15121 	output_operand_lossage ("invalid %%R value");
15122       else
15123 	fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
15124       return;
15125 
15126     case 's':
15127       /* Low 5 bits of 32 - value */
15128       if (! INT_P (x))
15129 	output_operand_lossage ("invalid %%s value");
15130       else
15131 	fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
15132       return;
15133 
15134     case 'S':
15135       /* PowerPC64 mask position.  All 0's is excluded.
15136 	 CONST_INT 32-bit mask is considered sign-extended so any
15137 	 transition must occur within the CONST_INT, not on the boundary.  */
15138       if (! mask64_operand (x, DImode))
15139 	output_operand_lossage ("invalid %%S value");
15140 
15141       uval = INT_LOWPART (x);
15142 
15143       if (uval & 1)	/* Clear Left */
15144 	{
15145 #if HOST_BITS_PER_WIDE_INT > 64
15146 	  uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
15147 #endif
15148 	  i = 64;
15149 	}
15150       else		/* Clear Right */
15151 	{
15152 	  uval = ~uval;
15153 #if HOST_BITS_PER_WIDE_INT > 64
15154 	  uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
15155 #endif
15156 	  i = 63;
15157 	}
15158       while (uval != 0)
15159 	--i, uval >>= 1;
15160       gcc_assert (i >= 0);
15161       fprintf (file, "%d", i);
15162       return;
15163 
15164     case 't':
15165       /* Like 'J' but get to the OVERFLOW/UNORDERED bit.  */
15166       gcc_assert (REG_P (x) && GET_MODE (x) == CCmode);
15167 
15168       /* Bit 3 is OV bit.  */
15169       i = 4 * (REGNO (x) - CR0_REGNO) + 3;
15170 
15171       /* If we want bit 31, write a shift count of zero, not 32.  */
15172       fprintf (file, "%d", i == 31 ? 0 : i + 1);
15173       return;
15174 
15175     case 'T':
15176       /* Print the symbolic name of a branch target register.  */
15177       if (GET_CODE (x) != REG || (REGNO (x) != LR_REGNO
15178 				  && REGNO (x) != CTR_REGNO))
15179 	output_operand_lossage ("invalid %%T value");
15180       else if (REGNO (x) == LR_REGNO)
15181 	fputs ("lr", file);
15182       else
15183 	fputs ("ctr", file);
15184       return;
15185 
15186     case 'u':
15187       /* High-order 16 bits of constant for use in unsigned operand.  */
15188       if (! INT_P (x))
15189 	output_operand_lossage ("invalid %%u value");
15190       else
15191 	fprintf (file, HOST_WIDE_INT_PRINT_HEX,
15192 		 (INT_LOWPART (x) >> 16) & 0xffff);
15193       return;
15194 
15195     case 'v':
15196       /* High-order 16 bits of constant for use in signed operand.  */
15197       if (! INT_P (x))
15198 	output_operand_lossage ("invalid %%v value");
15199       else
15200 	fprintf (file, HOST_WIDE_INT_PRINT_HEX,
15201 		 (INT_LOWPART (x) >> 16) & 0xffff);
15202       return;
15203 
15204     case 'U':
15205       /* Print `u' if this has an auto-increment or auto-decrement.  */
15206       if (MEM_P (x)
15207 	  && (GET_CODE (XEXP (x, 0)) == PRE_INC
15208 	      || GET_CODE (XEXP (x, 0)) == PRE_DEC
15209 	      || GET_CODE (XEXP (x, 0)) == PRE_MODIFY))
15210 	putc ('u', file);
15211       return;
15212 
15213     case 'V':
15214       /* Print the trap code for this operand.  */
15215       switch (GET_CODE (x))
15216 	{
15217 	case EQ:
15218 	  fputs ("eq", file);   /* 4 */
15219 	  break;
15220 	case NE:
15221 	  fputs ("ne", file);   /* 24 */
15222 	  break;
15223 	case LT:
15224 	  fputs ("lt", file);   /* 16 */
15225 	  break;
15226 	case LE:
15227 	  fputs ("le", file);   /* 20 */
15228 	  break;
15229 	case GT:
15230 	  fputs ("gt", file);   /* 8 */
15231 	  break;
15232 	case GE:
15233 	  fputs ("ge", file);   /* 12 */
15234 	  break;
15235 	case LTU:
15236 	  fputs ("llt", file);  /* 2 */
15237 	  break;
15238 	case LEU:
15239 	  fputs ("lle", file);  /* 6 */
15240 	  break;
15241 	case GTU:
15242 	  fputs ("lgt", file);  /* 1 */
15243 	  break;
15244 	case GEU:
15245 	  fputs ("lge", file);  /* 5 */
15246 	  break;
15247 	default:
15248 	  gcc_unreachable ();
15249 	}
15250       break;
15251 
15252     case 'w':
15253       /* If constant, low-order 16 bits of constant, signed.  Otherwise, write
15254 	 normally.  */
15255       if (INT_P (x))
15256 	fprintf (file, HOST_WIDE_INT_PRINT_DEC,
15257 		 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
15258       else
15259 	print_operand (file, x, 0);
15260       return;
15261 
15262     case 'W':
15263       /* MB value for a PowerPC64 rldic operand.  */
15264       i = clz_hwi (GET_CODE (x) == CONST_INT
15265 		   ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
15266 
15267 #if HOST_BITS_PER_WIDE_INT == 32
15268       if (GET_CODE (x) == CONST_INT && i > 0)
15269 	i += 32;  /* zero-extend high-part was all 0's */
15270       else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
15271 	i = clz_hwi (CONST_DOUBLE_LOW (x)) + 32;
15272 #endif
15273 
15274       fprintf (file, "%d", i);
15275       return;
15276 
15277     case 'x':
15278       /* X is a FPR or Altivec register used in a VSX context.  */
15279       if (GET_CODE (x) != REG || !VSX_REGNO_P (REGNO (x)))
15280 	output_operand_lossage ("invalid %%x value");
15281       else
15282 	{
15283 	  int reg = REGNO (x);
15284 	  int vsx_reg = (FP_REGNO_P (reg)
15285 			 ? reg - 32
15286 			 : reg - FIRST_ALTIVEC_REGNO + 32);
15287 
15288 #ifdef TARGET_REGNAMES
15289 	  if (TARGET_REGNAMES)
15290 	    fprintf (file, "%%vs%d", vsx_reg);
15291 	  else
15292 #endif
15293 	    fprintf (file, "%d", vsx_reg);
15294 	}
15295       return;
15296 
15297     case 'X':
15298       if (MEM_P (x)
15299 	  && (legitimate_indexed_address_p (XEXP (x, 0), 0)
15300 	      || (GET_CODE (XEXP (x, 0)) == PRE_MODIFY
15301 		  && legitimate_indexed_address_p (XEXP (XEXP (x, 0), 1), 0))))
15302 	putc ('x', file);
15303       return;
15304 
15305     case 'Y':
15306       /* Like 'L', for third word of TImode  */
15307       if (REG_P (x))
15308 	fputs (reg_names[REGNO (x) + 2], file);
15309       else if (MEM_P (x))
15310 	{
15311 	  if (GET_CODE (XEXP (x, 0)) == PRE_INC
15312 	      || GET_CODE (XEXP (x, 0)) == PRE_DEC)
15313 	    output_address (plus_constant (Pmode, XEXP (XEXP (x, 0), 0), 8));
15314 	  else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
15315 	    output_address (plus_constant (Pmode, XEXP (XEXP (x, 0), 0), 8));
15316 	  else
15317 	    output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
15318 	  if (small_data_operand (x, GET_MODE (x)))
15319 	    fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
15320 		     reg_names[SMALL_DATA_REG]);
15321 	}
15322       return;
15323 
15324     case 'z':
15325       /* X is a SYMBOL_REF.  Write out the name preceded by a
15326 	 period and without any trailing data in brackets.  Used for function
15327 	 names.  If we are configured for System V (or the embedded ABI) on
15328 	 the PowerPC, do not emit the period, since those systems do not use
15329 	 TOCs and the like.  */
15330       gcc_assert (GET_CODE (x) == SYMBOL_REF);
15331 
15332       /* Mark the decl as referenced so that cgraph will output the
15333 	 function.  */
15334       if (SYMBOL_REF_DECL (x))
15335 	mark_decl_referenced (SYMBOL_REF_DECL (x));
15336 
15337       /* For macho, check to see if we need a stub.  */
15338       if (TARGET_MACHO)
15339 	{
15340 	  const char *name = XSTR (x, 0);
15341 #if TARGET_MACHO
15342 	  if (darwin_emit_branch_islands
15343 	      && MACHOPIC_INDIRECT
15344 	      && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
15345 	    name = machopic_indirection_name (x, /*stub_p=*/true);
15346 #endif
15347 	  assemble_name (file, name);
15348 	}
15349       else if (!DOT_SYMBOLS)
15350 	assemble_name (file, XSTR (x, 0));
15351       else
15352 	rs6000_output_function_entry (file, XSTR (x, 0));
15353       return;
15354 
15355     case 'Z':
15356       /* Like 'L', for last word of TImode.  */
15357       if (REG_P (x))
15358 	fputs (reg_names[REGNO (x) + 3], file);
15359       else if (MEM_P (x))
15360 	{
15361 	  if (GET_CODE (XEXP (x, 0)) == PRE_INC
15362 	      || GET_CODE (XEXP (x, 0)) == PRE_DEC)
15363 	    output_address (plus_constant (Pmode, XEXP (XEXP (x, 0), 0), 12));
15364 	  else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
15365 	    output_address (plus_constant (Pmode, XEXP (XEXP (x, 0), 0), 12));
15366 	  else
15367 	    output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
15368 	  if (small_data_operand (x, GET_MODE (x)))
15369 	    fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
15370 		     reg_names[SMALL_DATA_REG]);
15371 	}
15372       return;
15373 
15374       /* Print AltiVec or SPE memory operand.  */
15375     case 'y':
15376       {
15377 	rtx tmp;
15378 
15379 	gcc_assert (MEM_P (x));
15380 
15381 	tmp = XEXP (x, 0);
15382 
15383 	/* Ugly hack because %y is overloaded.  */
15384 	if ((TARGET_SPE || TARGET_E500_DOUBLE)
15385 	    && (GET_MODE_SIZE (GET_MODE (x)) == 8
15386 		|| GET_MODE (x) == TFmode
15387 		|| GET_MODE (x) == TImode))
15388 	  {
15389 	    /* Handle [reg].  */
15390 	    if (REG_P (tmp))
15391 	      {
15392 		fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
15393 		break;
15394 	      }
15395 	    /* Handle [reg+UIMM].  */
15396 	    else if (GET_CODE (tmp) == PLUS &&
15397 		     GET_CODE (XEXP (tmp, 1)) == CONST_INT)
15398 	      {
15399 		int x;
15400 
15401 		gcc_assert (REG_P (XEXP (tmp, 0)));
15402 
15403 		x = INTVAL (XEXP (tmp, 1));
15404 		fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
15405 		break;
15406 	      }
15407 
15408 	    /* Fall through.  Must be [reg+reg].  */
15409 	  }
15410 	if (VECTOR_MEM_ALTIVEC_P (GET_MODE (x))
15411 	    && GET_CODE (tmp) == AND
15412 	    && GET_CODE (XEXP (tmp, 1)) == CONST_INT
15413 	    && INTVAL (XEXP (tmp, 1)) == -16)
15414 	  tmp = XEXP (tmp, 0);
15415 	else if (VECTOR_MEM_VSX_P (GET_MODE (x))
15416 		 && GET_CODE (tmp) == PRE_MODIFY)
15417 	  tmp = XEXP (tmp, 1);
15418 	if (REG_P (tmp))
15419 	  fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
15420 	else
15421 	  {
15422 	    if (!GET_CODE (tmp) == PLUS
15423 		|| !REG_P (XEXP (tmp, 0))
15424 		|| !REG_P (XEXP (tmp, 1)))
15425 	      {
15426 		output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
15427 		break;
15428 	      }
15429 
15430 	    if (REGNO (XEXP (tmp, 0)) == 0)
15431 	      fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
15432 		       reg_names[ REGNO (XEXP (tmp, 0)) ]);
15433 	    else
15434 	      fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
15435 		       reg_names[ REGNO (XEXP (tmp, 1)) ]);
15436 	  }
15437 	break;
15438       }
15439 
15440     case 0:
15441       if (REG_P (x))
15442 	fprintf (file, "%s", reg_names[REGNO (x)]);
15443       else if (MEM_P (x))
15444 	{
15445 	  /* We need to handle PRE_INC and PRE_DEC here, since we need to
15446 	     know the width from the mode.  */
15447 	  if (GET_CODE (XEXP (x, 0)) == PRE_INC)
15448 	    fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
15449 		     reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
15450 	  else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
15451 	    fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
15452 		     reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
15453 	  else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
15454 	    output_address (XEXP (XEXP (x, 0), 1));
15455 	  else
15456 	    output_address (XEXP (x, 0));
15457 	}
15458       else
15459 	{
15460 	  if (toc_relative_expr_p (x, false))
15461 	    /* This hack along with a corresponding hack in
15462 	       rs6000_output_addr_const_extra arranges to output addends
15463 	       where the assembler expects to find them.  eg.
15464 	       (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 4)
15465 	       without this hack would be output as "x@toc+4".  We
15466 	       want "x+4@toc".  */
15467 	    output_addr_const (file, CONST_CAST_RTX (tocrel_base));
15468 	  else
15469 	    output_addr_const (file, x);
15470 	}
15471       return;
15472 
15473     case '&':
15474       assemble_name (file, rs6000_get_some_local_dynamic_name ());
15475       return;
15476 
15477     default:
15478       output_operand_lossage ("invalid %%xn code");
15479     }
15480 }
15481 
15482 /* Print the address of an operand.  */
15483 
15484 void
print_operand_address(FILE * file,rtx x)15485 print_operand_address (FILE *file, rtx x)
15486 {
15487   if (REG_P (x))
15488     fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
15489   else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
15490 	   || GET_CODE (x) == LABEL_REF)
15491     {
15492       output_addr_const (file, x);
15493       if (small_data_operand (x, GET_MODE (x)))
15494 	fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
15495 		 reg_names[SMALL_DATA_REG]);
15496       else
15497 	gcc_assert (!TARGET_TOC);
15498     }
15499   else if (GET_CODE (x) == PLUS && REG_P (XEXP (x, 0))
15500 	   && REG_P (XEXP (x, 1)))
15501     {
15502       if (REGNO (XEXP (x, 0)) == 0)
15503 	fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
15504 		 reg_names[ REGNO (XEXP (x, 0)) ]);
15505       else
15506 	fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
15507 		 reg_names[ REGNO (XEXP (x, 1)) ]);
15508     }
15509   else if (GET_CODE (x) == PLUS && REG_P (XEXP (x, 0))
15510 	   && GET_CODE (XEXP (x, 1)) == CONST_INT)
15511     fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
15512 	     INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
15513 #if TARGET_MACHO
15514   else if (GET_CODE (x) == LO_SUM && REG_P (XEXP (x, 0))
15515 	   && CONSTANT_P (XEXP (x, 1)))
15516     {
15517       fprintf (file, "lo16(");
15518       output_addr_const (file, XEXP (x, 1));
15519       fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
15520     }
15521 #endif
15522 #if TARGET_ELF
15523   else if (GET_CODE (x) == LO_SUM && REG_P (XEXP (x, 0))
15524 	   && CONSTANT_P (XEXP (x, 1)))
15525     {
15526       output_addr_const (file, XEXP (x, 1));
15527       fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
15528     }
15529 #endif
15530   else if (toc_relative_expr_p (x, false))
15531     {
15532       /* This hack along with a corresponding hack in
15533 	 rs6000_output_addr_const_extra arranges to output addends
15534 	 where the assembler expects to find them.  eg.
15535 	 (lo_sum (reg 9)
15536 	 .       (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 8))
15537 	 without this hack would be output as "x@toc+8@l(9)".  We
15538 	 want "x+8@toc@l(9)".  */
15539       output_addr_const (file, CONST_CAST_RTX (tocrel_base));
15540       if (GET_CODE (x) == LO_SUM)
15541 	fprintf (file, "@l(%s)", reg_names[REGNO (XEXP (x, 0))]);
15542       else
15543 	fprintf (file, "(%s)", reg_names[REGNO (XVECEXP (tocrel_base, 0, 1))]);
15544     }
15545   else
15546     gcc_unreachable ();
15547 }
15548 
15549 /* Implement TARGET_OUTPUT_ADDR_CONST_EXTRA.  */
15550 
15551 static bool
rs6000_output_addr_const_extra(FILE * file,rtx x)15552 rs6000_output_addr_const_extra (FILE *file, rtx x)
15553 {
15554   if (GET_CODE (x) == UNSPEC)
15555     switch (XINT (x, 1))
15556       {
15557       case UNSPEC_TOCREL:
15558 	gcc_checking_assert (GET_CODE (XVECEXP (x, 0, 0)) == SYMBOL_REF
15559 			     && REG_P (XVECEXP (x, 0, 1))
15560 			     && REGNO (XVECEXP (x, 0, 1)) == TOC_REGISTER);
15561 	output_addr_const (file, XVECEXP (x, 0, 0));
15562 	if (x == tocrel_base && tocrel_offset != const0_rtx)
15563 	  {
15564 	    if (INTVAL (tocrel_offset) >= 0)
15565 	      fprintf (file, "+");
15566 	    output_addr_const (file, CONST_CAST_RTX (tocrel_offset));
15567 	  }
15568 	if (!TARGET_AIX || (TARGET_ELF && TARGET_MINIMAL_TOC))
15569 	  {
15570 	    putc ('-', file);
15571 	    assemble_name (file, toc_label_name);
15572 	  }
15573 	else if (TARGET_ELF)
15574 	  fputs ("@toc", file);
15575 	return true;
15576 
15577 #if TARGET_MACHO
15578       case UNSPEC_MACHOPIC_OFFSET:
15579 	output_addr_const (file, XVECEXP (x, 0, 0));
15580 	putc ('-', file);
15581 	machopic_output_function_base_name (file);
15582 	return true;
15583 #endif
15584       }
15585   return false;
15586 }
15587 
15588 /* Target hook for assembling integer objects.  The PowerPC version has
15589    to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
15590    is defined.  It also needs to handle DI-mode objects on 64-bit
15591    targets.  */
15592 
15593 static bool
rs6000_assemble_integer(rtx x,unsigned int size,int aligned_p)15594 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
15595 {
15596 #ifdef RELOCATABLE_NEEDS_FIXUP
15597   /* Special handling for SI values.  */
15598   if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
15599     {
15600       static int recurse = 0;
15601 
15602       /* For -mrelocatable, we mark all addresses that need to be fixed up in
15603 	 the .fixup section.  Since the TOC section is already relocated, we
15604 	 don't need to mark it here.  We used to skip the text section, but it
15605 	 should never be valid for relocated addresses to be placed in the text
15606 	 section.  */
15607       if (TARGET_RELOCATABLE
15608 	  && in_section != toc_section
15609 	  && !recurse
15610 	  && GET_CODE (x) != CONST_INT
15611 	  && GET_CODE (x) != CONST_DOUBLE
15612 	  && CONSTANT_P (x))
15613 	{
15614 	  char buf[256];
15615 
15616 	  recurse = 1;
15617 	  ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
15618 	  fixuplabelno++;
15619 	  ASM_OUTPUT_LABEL (asm_out_file, buf);
15620 	  fprintf (asm_out_file, "\t.long\t(");
15621 	  output_addr_const (asm_out_file, x);
15622 	  fprintf (asm_out_file, ")@fixup\n");
15623 	  fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
15624 	  ASM_OUTPUT_ALIGN (asm_out_file, 2);
15625 	  fprintf (asm_out_file, "\t.long\t");
15626 	  assemble_name (asm_out_file, buf);
15627 	  fprintf (asm_out_file, "\n\t.previous\n");
15628 	  recurse = 0;
15629 	  return true;
15630 	}
15631       /* Remove initial .'s to turn a -mcall-aixdesc function
15632 	 address into the address of the descriptor, not the function
15633 	 itself.  */
15634       else if (GET_CODE (x) == SYMBOL_REF
15635 	       && XSTR (x, 0)[0] == '.'
15636 	       && DEFAULT_ABI == ABI_AIX)
15637 	{
15638 	  const char *name = XSTR (x, 0);
15639 	  while (*name == '.')
15640 	    name++;
15641 
15642 	  fprintf (asm_out_file, "\t.long\t%s\n", name);
15643 	  return true;
15644 	}
15645     }
15646 #endif /* RELOCATABLE_NEEDS_FIXUP */
15647   return default_assemble_integer (x, size, aligned_p);
15648 }
15649 
15650 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
15651 /* Emit an assembler directive to set symbol visibility for DECL to
15652    VISIBILITY_TYPE.  */
15653 
15654 static void
rs6000_assemble_visibility(tree decl,int vis)15655 rs6000_assemble_visibility (tree decl, int vis)
15656 {
15657   if (TARGET_XCOFF)
15658     return;
15659 
15660   /* Functions need to have their entry point symbol visibility set as
15661      well as their descriptor symbol visibility.  */
15662   if (DEFAULT_ABI == ABI_AIX
15663       && DOT_SYMBOLS
15664       && TREE_CODE (decl) == FUNCTION_DECL)
15665     {
15666       static const char * const visibility_types[] = {
15667 	NULL, "internal", "hidden", "protected"
15668       };
15669 
15670       const char *name, *type;
15671 
15672       name = ((* targetm.strip_name_encoding)
15673 	      (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
15674       type = visibility_types[vis];
15675 
15676       fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
15677       fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
15678     }
15679   else
15680     default_assemble_visibility (decl, vis);
15681 }
15682 #endif
15683 
15684 enum rtx_code
rs6000_reverse_condition(enum machine_mode mode,enum rtx_code code)15685 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
15686 {
15687   /* Reversal of FP compares takes care -- an ordered compare
15688      becomes an unordered compare and vice versa.  */
15689   if (mode == CCFPmode
15690       && (!flag_finite_math_only
15691 	  || code == UNLT || code == UNLE || code == UNGT || code == UNGE
15692 	  || code == UNEQ || code == LTGT))
15693     return reverse_condition_maybe_unordered (code);
15694   else
15695     return reverse_condition (code);
15696 }
15697 
15698 /* Generate a compare for CODE.  Return a brand-new rtx that
15699    represents the result of the compare.  */
15700 
15701 static rtx
rs6000_generate_compare(rtx cmp,enum machine_mode mode)15702 rs6000_generate_compare (rtx cmp, enum machine_mode mode)
15703 {
15704   enum machine_mode comp_mode;
15705   rtx compare_result;
15706   enum rtx_code code = GET_CODE (cmp);
15707   rtx op0 = XEXP (cmp, 0);
15708   rtx op1 = XEXP (cmp, 1);
15709 
15710   if (FLOAT_MODE_P (mode))
15711     comp_mode = CCFPmode;
15712   else if (code == GTU || code == LTU
15713 	   || code == GEU || code == LEU)
15714     comp_mode = CCUNSmode;
15715   else if ((code == EQ || code == NE)
15716 	   && unsigned_reg_p (op0)
15717 	   && (unsigned_reg_p (op1)
15718 	       || (CONST_INT_P (op1) && INTVAL (op1) != 0)))
15719     /* These are unsigned values, perhaps there will be a later
15720        ordering compare that can be shared with this one.  */
15721     comp_mode = CCUNSmode;
15722   else
15723     comp_mode = CCmode;
15724 
15725   /* If we have an unsigned compare, make sure we don't have a signed value as
15726      an immediate.  */
15727   if (comp_mode == CCUNSmode && GET_CODE (op1) == CONST_INT
15728       && INTVAL (op1) < 0)
15729     {
15730       op0 = copy_rtx_if_shared (op0);
15731       op1 = force_reg (GET_MODE (op0), op1);
15732       cmp = gen_rtx_fmt_ee (code, GET_MODE (cmp), op0, op1);
15733     }
15734 
15735   /* First, the compare.  */
15736   compare_result = gen_reg_rtx (comp_mode);
15737 
15738   /* E500 FP compare instructions on the GPRs.  Yuck!  */
15739   if ((!TARGET_FPRS && TARGET_HARD_FLOAT)
15740       && FLOAT_MODE_P (mode))
15741     {
15742       rtx cmp, or_result, compare_result2;
15743       enum machine_mode op_mode = GET_MODE (op0);
15744 
15745       if (op_mode == VOIDmode)
15746 	op_mode = GET_MODE (op1);
15747 
15748       /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
15749 	 This explains the following mess.  */
15750 
15751       switch (code)
15752 	{
15753 	case EQ: case UNEQ: case NE: case LTGT:
15754 	  switch (op_mode)
15755 	    {
15756 	    case SFmode:
15757 	      cmp = (flag_finite_math_only && !flag_trapping_math)
15758 		? gen_tstsfeq_gpr (compare_result, op0, op1)
15759 		: gen_cmpsfeq_gpr (compare_result, op0, op1);
15760 	      break;
15761 
15762 	    case DFmode:
15763 	      cmp = (flag_finite_math_only && !flag_trapping_math)
15764 		? gen_tstdfeq_gpr (compare_result, op0, op1)
15765 		: gen_cmpdfeq_gpr (compare_result, op0, op1);
15766 	      break;
15767 
15768 	    case TFmode:
15769 	      cmp = (flag_finite_math_only && !flag_trapping_math)
15770 		? gen_tsttfeq_gpr (compare_result, op0, op1)
15771 		: gen_cmptfeq_gpr (compare_result, op0, op1);
15772 	      break;
15773 
15774 	    default:
15775 	      gcc_unreachable ();
15776 	    }
15777 	  break;
15778 
15779 	case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
15780 	  switch (op_mode)
15781 	    {
15782 	    case SFmode:
15783 	      cmp = (flag_finite_math_only && !flag_trapping_math)
15784 		? gen_tstsfgt_gpr (compare_result, op0, op1)
15785 		: gen_cmpsfgt_gpr (compare_result, op0, op1);
15786 	      break;
15787 
15788 	    case DFmode:
15789 	      cmp = (flag_finite_math_only && !flag_trapping_math)
15790 		? gen_tstdfgt_gpr (compare_result, op0, op1)
15791 		: gen_cmpdfgt_gpr (compare_result, op0, op1);
15792 	      break;
15793 
15794 	    case TFmode:
15795 	      cmp = (flag_finite_math_only && !flag_trapping_math)
15796 		? gen_tsttfgt_gpr (compare_result, op0, op1)
15797 		: gen_cmptfgt_gpr (compare_result, op0, op1);
15798 	      break;
15799 
15800 	    default:
15801 	      gcc_unreachable ();
15802 	    }
15803 	  break;
15804 
15805 	case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
15806 	  switch (op_mode)
15807 	    {
15808 	    case SFmode:
15809 	      cmp = (flag_finite_math_only && !flag_trapping_math)
15810 		? gen_tstsflt_gpr (compare_result, op0, op1)
15811 		: gen_cmpsflt_gpr (compare_result, op0, op1);
15812 	      break;
15813 
15814 	    case DFmode:
15815 	      cmp = (flag_finite_math_only && !flag_trapping_math)
15816 		? gen_tstdflt_gpr (compare_result, op0, op1)
15817 		: gen_cmpdflt_gpr (compare_result, op0, op1);
15818 	      break;
15819 
15820 	    case TFmode:
15821 	      cmp = (flag_finite_math_only && !flag_trapping_math)
15822 		? gen_tsttflt_gpr (compare_result, op0, op1)
15823 		: gen_cmptflt_gpr (compare_result, op0, op1);
15824 	      break;
15825 
15826 	    default:
15827 	      gcc_unreachable ();
15828 	    }
15829 	  break;
15830         default:
15831           gcc_unreachable ();
15832 	}
15833 
15834       /* Synthesize LE and GE from LT/GT || EQ.  */
15835       if (code == LE || code == GE || code == LEU || code == GEU)
15836 	{
15837 	  emit_insn (cmp);
15838 
15839 	  switch (code)
15840 	    {
15841 	    case LE: code = LT; break;
15842 	    case GE: code = GT; break;
15843 	    case LEU: code = LT; break;
15844 	    case GEU: code = GT; break;
15845 	    default: gcc_unreachable ();
15846 	    }
15847 
15848 	  compare_result2 = gen_reg_rtx (CCFPmode);
15849 
15850 	  /* Do the EQ.  */
15851 	  switch (op_mode)
15852 	    {
15853 	    case SFmode:
15854 	      cmp = (flag_finite_math_only && !flag_trapping_math)
15855 		? gen_tstsfeq_gpr (compare_result2, op0, op1)
15856 		: gen_cmpsfeq_gpr (compare_result2, op0, op1);
15857 	      break;
15858 
15859 	    case DFmode:
15860 	      cmp = (flag_finite_math_only && !flag_trapping_math)
15861 		? gen_tstdfeq_gpr (compare_result2, op0, op1)
15862 		: gen_cmpdfeq_gpr (compare_result2, op0, op1);
15863 	      break;
15864 
15865 	    case TFmode:
15866 	      cmp = (flag_finite_math_only && !flag_trapping_math)
15867 		? gen_tsttfeq_gpr (compare_result2, op0, op1)
15868 		: gen_cmptfeq_gpr (compare_result2, op0, op1);
15869 	      break;
15870 
15871 	    default:
15872 	      gcc_unreachable ();
15873 	    }
15874 	  emit_insn (cmp);
15875 
15876 	  /* OR them together.  */
15877 	  or_result = gen_reg_rtx (CCFPmode);
15878 	  cmp = gen_e500_cr_ior_compare (or_result, compare_result,
15879 					   compare_result2);
15880 	  compare_result = or_result;
15881 	  code = EQ;
15882 	}
15883       else
15884 	{
15885 	  if (code == NE || code == LTGT)
15886 	    code = NE;
15887 	  else
15888 	    code = EQ;
15889 	}
15890 
15891       emit_insn (cmp);
15892     }
15893   else
15894     {
15895       /* Generate XLC-compatible TFmode compare as PARALLEL with extra
15896 	 CLOBBERs to match cmptf_internal2 pattern.  */
15897       if (comp_mode == CCFPmode && TARGET_XL_COMPAT
15898 	  && GET_MODE (op0) == TFmode
15899 	  && !TARGET_IEEEQUAD
15900 	  && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
15901 	emit_insn (gen_rtx_PARALLEL (VOIDmode,
15902 	  gen_rtvec (10,
15903 		     gen_rtx_SET (VOIDmode,
15904 				  compare_result,
15905 				  gen_rtx_COMPARE (comp_mode, op0, op1)),
15906 		     gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15907 		     gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15908 		     gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15909 		     gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15910 		     gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15911 		     gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15912 		     gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15913 		     gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15914 		     gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (Pmode)))));
15915       else if (GET_CODE (op1) == UNSPEC
15916 	       && XINT (op1, 1) == UNSPEC_SP_TEST)
15917 	{
15918 	  rtx op1b = XVECEXP (op1, 0, 0);
15919 	  comp_mode = CCEQmode;
15920 	  compare_result = gen_reg_rtx (CCEQmode);
15921 	  if (TARGET_64BIT)
15922 	    emit_insn (gen_stack_protect_testdi (compare_result, op0, op1b));
15923 	  else
15924 	    emit_insn (gen_stack_protect_testsi (compare_result, op0, op1b));
15925 	}
15926       else
15927 	emit_insn (gen_rtx_SET (VOIDmode, compare_result,
15928 				gen_rtx_COMPARE (comp_mode, op0, op1)));
15929     }
15930 
15931   /* Some kinds of FP comparisons need an OR operation;
15932      under flag_finite_math_only we don't bother.  */
15933   if (FLOAT_MODE_P (mode)
15934       && !flag_finite_math_only
15935       && !(TARGET_HARD_FLOAT && !TARGET_FPRS)
15936       && (code == LE || code == GE
15937 	  || code == UNEQ || code == LTGT
15938 	  || code == UNGT || code == UNLT))
15939     {
15940       enum rtx_code or1, or2;
15941       rtx or1_rtx, or2_rtx, compare2_rtx;
15942       rtx or_result = gen_reg_rtx (CCEQmode);
15943 
15944       switch (code)
15945 	{
15946 	case LE: or1 = LT;  or2 = EQ;  break;
15947 	case GE: or1 = GT;  or2 = EQ;  break;
15948 	case UNEQ: or1 = UNORDERED;  or2 = EQ;  break;
15949 	case LTGT: or1 = LT;  or2 = GT;  break;
15950 	case UNGT: or1 = UNORDERED;  or2 = GT;  break;
15951 	case UNLT: or1 = UNORDERED;  or2 = LT;  break;
15952 	default:  gcc_unreachable ();
15953 	}
15954       validate_condition_mode (or1, comp_mode);
15955       validate_condition_mode (or2, comp_mode);
15956       or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
15957       or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
15958       compare2_rtx = gen_rtx_COMPARE (CCEQmode,
15959 				      gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
15960 				      const_true_rtx);
15961       emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
15962 
15963       compare_result = or_result;
15964       code = EQ;
15965     }
15966 
15967   validate_condition_mode (code, GET_MODE (compare_result));
15968 
15969   return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
15970 }
15971 
15972 
15973 /* Emit the RTL for an sISEL pattern.  */
15974 
15975 void
rs6000_emit_sISEL(enum machine_mode mode ATTRIBUTE_UNUSED,rtx operands[])15976 rs6000_emit_sISEL (enum machine_mode mode ATTRIBUTE_UNUSED, rtx operands[])
15977 {
15978   rs6000_emit_int_cmove (operands[0], operands[1], const1_rtx, const0_rtx);
15979 }
15980 
15981 void
rs6000_emit_sCOND(enum machine_mode mode,rtx operands[])15982 rs6000_emit_sCOND (enum machine_mode mode, rtx operands[])
15983 {
15984   rtx condition_rtx;
15985   enum machine_mode op_mode;
15986   enum rtx_code cond_code;
15987   rtx result = operands[0];
15988 
15989   if (TARGET_ISEL && (mode == SImode || mode == DImode))
15990     {
15991       rs6000_emit_sISEL (mode, operands);
15992       return;
15993     }
15994 
15995   condition_rtx = rs6000_generate_compare (operands[1], mode);
15996   cond_code = GET_CODE (condition_rtx);
15997 
15998   if (FLOAT_MODE_P (mode)
15999       && !TARGET_FPRS && TARGET_HARD_FLOAT)
16000     {
16001       rtx t;
16002 
16003       PUT_MODE (condition_rtx, SImode);
16004       t = XEXP (condition_rtx, 0);
16005 
16006       gcc_assert (cond_code == NE || cond_code == EQ);
16007 
16008       if (cond_code == NE)
16009 	emit_insn (gen_e500_flip_gt_bit (t, t));
16010 
16011       emit_insn (gen_move_from_CR_gt_bit (result, t));
16012       return;
16013     }
16014 
16015   if (cond_code == NE
16016       || cond_code == GE || cond_code == LE
16017       || cond_code == GEU || cond_code == LEU
16018       || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
16019     {
16020       rtx not_result = gen_reg_rtx (CCEQmode);
16021       rtx not_op, rev_cond_rtx;
16022       enum machine_mode cc_mode;
16023 
16024       cc_mode = GET_MODE (XEXP (condition_rtx, 0));
16025 
16026       rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
16027 				     SImode, XEXP (condition_rtx, 0), const0_rtx);
16028       not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
16029       emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
16030       condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
16031     }
16032 
16033   op_mode = GET_MODE (XEXP (operands[1], 0));
16034   if (op_mode == VOIDmode)
16035     op_mode = GET_MODE (XEXP (operands[1], 1));
16036 
16037   if (TARGET_POWERPC64 && (op_mode == DImode || FLOAT_MODE_P (mode)))
16038     {
16039       PUT_MODE (condition_rtx, DImode);
16040       convert_move (result, condition_rtx, 0);
16041     }
16042   else
16043     {
16044       PUT_MODE (condition_rtx, SImode);
16045       emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
16046     }
16047 }
16048 
16049 /* Emit a branch of kind CODE to location LOC.  */
16050 
16051 void
rs6000_emit_cbranch(enum machine_mode mode,rtx operands[])16052 rs6000_emit_cbranch (enum machine_mode mode, rtx operands[])
16053 {
16054   rtx condition_rtx, loc_ref;
16055 
16056   condition_rtx = rs6000_generate_compare (operands[0], mode);
16057   loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
16058   emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
16059 			       gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
16060 						     loc_ref, pc_rtx)));
16061 }
16062 
16063 /* Return the string to output a conditional branch to LABEL, which is
16064    the operand template of the label, or NULL if the branch is really a
16065    conditional return.
16066 
16067    OP is the conditional expression.  XEXP (OP, 0) is assumed to be a
16068    condition code register and its mode specifies what kind of
16069    comparison we made.
16070 
16071    REVERSED is nonzero if we should reverse the sense of the comparison.
16072 
16073    INSN is the insn.  */
16074 
16075 char *
output_cbranch(rtx op,const char * label,int reversed,rtx insn)16076 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
16077 {
16078   static char string[64];
16079   enum rtx_code code = GET_CODE (op);
16080   rtx cc_reg = XEXP (op, 0);
16081   enum machine_mode mode = GET_MODE (cc_reg);
16082   int cc_regno = REGNO (cc_reg) - CR0_REGNO;
16083   int need_longbranch = label != NULL && get_attr_length (insn) == 8;
16084   int really_reversed = reversed ^ need_longbranch;
16085   char *s = string;
16086   const char *ccode;
16087   const char *pred;
16088   rtx note;
16089 
16090   validate_condition_mode (code, mode);
16091 
16092   /* Work out which way this really branches.  We could use
16093      reverse_condition_maybe_unordered here always but this
16094      makes the resulting assembler clearer.  */
16095   if (really_reversed)
16096     {
16097       /* Reversal of FP compares takes care -- an ordered compare
16098 	 becomes an unordered compare and vice versa.  */
16099       if (mode == CCFPmode)
16100 	code = reverse_condition_maybe_unordered (code);
16101       else
16102 	code = reverse_condition (code);
16103     }
16104 
16105   if ((!TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
16106     {
16107       /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
16108 	 to the GT bit.  */
16109       switch (code)
16110 	{
16111 	case EQ:
16112 	  /* Opposite of GT.  */
16113 	  code = GT;
16114 	  break;
16115 
16116 	case NE:
16117 	  code = UNLE;
16118 	  break;
16119 
16120 	default:
16121 	  gcc_unreachable ();
16122 	}
16123     }
16124 
16125   switch (code)
16126     {
16127       /* Not all of these are actually distinct opcodes, but
16128 	 we distinguish them for clarity of the resulting assembler.  */
16129     case NE: case LTGT:
16130       ccode = "ne"; break;
16131     case EQ: case UNEQ:
16132       ccode = "eq"; break;
16133     case GE: case GEU:
16134       ccode = "ge"; break;
16135     case GT: case GTU: case UNGT:
16136       ccode = "gt"; break;
16137     case LE: case LEU:
16138       ccode = "le"; break;
16139     case LT: case LTU: case UNLT:
16140       ccode = "lt"; break;
16141     case UNORDERED: ccode = "un"; break;
16142     case ORDERED: ccode = "nu"; break;
16143     case UNGE: ccode = "nl"; break;
16144     case UNLE: ccode = "ng"; break;
16145     default:
16146       gcc_unreachable ();
16147     }
16148 
16149   /* Maybe we have a guess as to how likely the branch is.  */
16150   pred = "";
16151   note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
16152   if (note != NULL_RTX)
16153     {
16154       /* PROB is the difference from 50%.  */
16155       int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
16156 
16157       /* Only hint for highly probable/improbable branches on newer
16158 	 cpus as static prediction overrides processor dynamic
16159 	 prediction.  For older cpus we may as well always hint, but
16160 	 assume not taken for branches that are very close to 50% as a
16161 	 mispredicted taken branch is more expensive than a
16162 	 mispredicted not-taken branch.  */
16163       if (rs6000_always_hint
16164 	  || (abs (prob) > REG_BR_PROB_BASE / 100 * 48
16165 	      && br_prob_note_reliable_p (note)))
16166 	{
16167 	  if (abs (prob) > REG_BR_PROB_BASE / 20
16168 	      && ((prob > 0) ^ need_longbranch))
16169 	    pred = "+";
16170 	  else
16171 	    pred = "-";
16172 	}
16173     }
16174 
16175   if (label == NULL)
16176     s += sprintf (s, "b%slr%s ", ccode, pred);
16177   else
16178     s += sprintf (s, "b%s%s ", ccode, pred);
16179 
16180   /* We need to escape any '%' characters in the reg_names string.
16181      Assume they'd only be the first character....  */
16182   if (reg_names[cc_regno + CR0_REGNO][0] == '%')
16183     *s++ = '%';
16184   s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
16185 
16186   if (label != NULL)
16187     {
16188       /* If the branch distance was too far, we may have to use an
16189 	 unconditional branch to go the distance.  */
16190       if (need_longbranch)
16191 	s += sprintf (s, ",$+8\n\tb %s", label);
16192       else
16193 	s += sprintf (s, ",%s", label);
16194     }
16195 
16196   return string;
16197 }
16198 
16199 /* Return the string to flip the GT bit on a CR.  */
16200 char *
output_e500_flip_gt_bit(rtx dst,rtx src)16201 output_e500_flip_gt_bit (rtx dst, rtx src)
16202 {
16203   static char string[64];
16204   int a, b;
16205 
16206   gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
16207 	      && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
16208 
16209   /* GT bit.  */
16210   a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
16211   b = 4 * (REGNO (src) - CR0_REGNO) + 1;
16212 
16213   sprintf (string, "crnot %d,%d", a, b);
16214   return string;
16215 }
16216 
16217 /* Return insn for VSX or Altivec comparisons.  */
16218 
16219 static rtx
rs6000_emit_vector_compare_inner(enum rtx_code code,rtx op0,rtx op1)16220 rs6000_emit_vector_compare_inner (enum rtx_code code, rtx op0, rtx op1)
16221 {
16222   rtx mask;
16223   enum machine_mode mode = GET_MODE (op0);
16224 
16225   switch (code)
16226     {
16227     default:
16228       break;
16229 
16230     case GE:
16231       if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
16232 	return NULL_RTX;
16233 
16234     case EQ:
16235     case GT:
16236     case GTU:
16237     case ORDERED:
16238     case UNORDERED:
16239     case UNEQ:
16240     case LTGT:
16241       mask = gen_reg_rtx (mode);
16242       emit_insn (gen_rtx_SET (VOIDmode,
16243 			      mask,
16244 			      gen_rtx_fmt_ee (code, mode, op0, op1)));
16245       return mask;
16246     }
16247 
16248   return NULL_RTX;
16249 }
16250 
16251 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
16252    DMODE is expected destination mode. This is a recursive function.  */
16253 
16254 static rtx
rs6000_emit_vector_compare(enum rtx_code rcode,rtx op0,rtx op1,enum machine_mode dmode)16255 rs6000_emit_vector_compare (enum rtx_code rcode,
16256 			    rtx op0, rtx op1,
16257 			    enum machine_mode dmode)
16258 {
16259   rtx mask;
16260   bool swap_operands = false;
16261   bool try_again = false;
16262 
16263   gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode));
16264   gcc_assert (GET_MODE (op0) == GET_MODE (op1));
16265 
16266   /* See if the comparison works as is.  */
16267   mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
16268   if (mask)
16269     return mask;
16270 
16271   switch (rcode)
16272     {
16273     case LT:
16274       rcode = GT;
16275       swap_operands = true;
16276       try_again = true;
16277       break;
16278     case LTU:
16279       rcode = GTU;
16280       swap_operands = true;
16281       try_again = true;
16282       break;
16283     case NE:
16284     case UNLE:
16285     case UNLT:
16286     case UNGE:
16287     case UNGT:
16288       /* Invert condition and try again.
16289 	 e.g., A != B becomes ~(A==B).  */
16290       {
16291 	enum rtx_code rev_code;
16292 	enum insn_code nor_code;
16293 	rtx mask2;
16294 
16295 	rev_code = reverse_condition_maybe_unordered (rcode);
16296 	if (rev_code == UNKNOWN)
16297 	  return NULL_RTX;
16298 
16299 	nor_code = optab_handler (one_cmpl_optab, dmode);
16300 	if (nor_code == CODE_FOR_nothing)
16301 	  return NULL_RTX;
16302 
16303 	mask2 = rs6000_emit_vector_compare (rev_code, op0, op1, dmode);
16304 	if (!mask2)
16305 	  return NULL_RTX;
16306 
16307 	mask = gen_reg_rtx (dmode);
16308 	emit_insn (GEN_FCN (nor_code) (mask, mask2));
16309 	return mask;
16310       }
16311       break;
16312     case GE:
16313     case GEU:
16314     case LE:
16315     case LEU:
16316       /* Try GT/GTU/LT/LTU OR EQ */
16317       {
16318 	rtx c_rtx, eq_rtx;
16319 	enum insn_code ior_code;
16320 	enum rtx_code new_code;
16321 
16322 	switch (rcode)
16323 	  {
16324 	  case  GE:
16325 	    new_code = GT;
16326 	    break;
16327 
16328 	  case GEU:
16329 	    new_code = GTU;
16330 	    break;
16331 
16332 	  case LE:
16333 	    new_code = LT;
16334 	    break;
16335 
16336 	  case LEU:
16337 	    new_code = LTU;
16338 	    break;
16339 
16340 	  default:
16341 	    gcc_unreachable ();
16342 	  }
16343 
16344 	ior_code = optab_handler (ior_optab, dmode);
16345 	if (ior_code == CODE_FOR_nothing)
16346 	  return NULL_RTX;
16347 
16348 	c_rtx = rs6000_emit_vector_compare (new_code, op0, op1, dmode);
16349 	if (!c_rtx)
16350 	  return NULL_RTX;
16351 
16352 	eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1, dmode);
16353 	if (!eq_rtx)
16354 	  return NULL_RTX;
16355 
16356 	mask = gen_reg_rtx (dmode);
16357 	emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
16358 	return mask;
16359       }
16360       break;
16361     default:
16362       return NULL_RTX;
16363     }
16364 
16365   if (try_again)
16366     {
16367       if (swap_operands)
16368 	{
16369 	  rtx tmp;
16370 	  tmp = op0;
16371 	  op0 = op1;
16372 	  op1 = tmp;
16373 	}
16374 
16375       mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
16376       if (mask)
16377 	return mask;
16378     }
16379 
16380   /* You only get two chances.  */
16381   return NULL_RTX;
16382 }
16383 
16384 /* Emit vector conditional expression.  DEST is destination. OP_TRUE and
16385    OP_FALSE are two VEC_COND_EXPR operands.  CC_OP0 and CC_OP1 are the two
16386    operands for the relation operation COND.  */
16387 
16388 int
rs6000_emit_vector_cond_expr(rtx dest,rtx op_true,rtx op_false,rtx cond,rtx cc_op0,rtx cc_op1)16389 rs6000_emit_vector_cond_expr (rtx dest, rtx op_true, rtx op_false,
16390 			      rtx cond, rtx cc_op0, rtx cc_op1)
16391 {
16392   enum machine_mode dest_mode = GET_MODE (dest);
16393   enum machine_mode mask_mode = GET_MODE (cc_op0);
16394   enum rtx_code rcode = GET_CODE (cond);
16395   enum machine_mode cc_mode = CCmode;
16396   rtx mask;
16397   rtx cond2;
16398   rtx tmp;
16399   bool invert_move = false;
16400 
16401   if (VECTOR_UNIT_NONE_P (dest_mode))
16402     return 0;
16403 
16404   gcc_assert (GET_MODE_SIZE (dest_mode) == GET_MODE_SIZE (mask_mode)
16405 	      && GET_MODE_NUNITS (dest_mode) == GET_MODE_NUNITS (mask_mode));
16406 
16407   switch (rcode)
16408     {
16409       /* Swap operands if we can, and fall back to doing the operation as
16410 	 specified, and doing a NOR to invert the test.  */
16411     case NE:
16412     case UNLE:
16413     case UNLT:
16414     case UNGE:
16415     case UNGT:
16416       /* Invert condition and try again.
16417 	 e.g., A  = (B != C) ? D : E becomes A = (B == C) ? E : D.  */
16418       invert_move = true;
16419       rcode = reverse_condition_maybe_unordered (rcode);
16420       if (rcode == UNKNOWN)
16421 	return 0;
16422       break;
16423 
16424       /* Mark unsigned tests with CCUNSmode.  */
16425     case GTU:
16426     case GEU:
16427     case LTU:
16428     case LEU:
16429       cc_mode = CCUNSmode;
16430       break;
16431 
16432     default:
16433       break;
16434     }
16435 
16436   /* Get the vector mask for the given relational operations.  */
16437   mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, mask_mode);
16438 
16439   if (!mask)
16440     return 0;
16441 
16442   if (invert_move)
16443     {
16444       tmp = op_true;
16445       op_true = op_false;
16446       op_false = tmp;
16447     }
16448 
16449   cond2 = gen_rtx_fmt_ee (NE, cc_mode, gen_lowpart (dest_mode, mask),
16450 			  CONST0_RTX (dest_mode));
16451   emit_insn (gen_rtx_SET (VOIDmode,
16452 			  dest,
16453 			  gen_rtx_IF_THEN_ELSE (dest_mode,
16454 						cond2,
16455 						op_true,
16456 						op_false)));
16457   return 1;
16458 }
16459 
16460 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
16461    operands of the last comparison is nonzero/true, FALSE_COND if it
16462    is zero/false.  Return 0 if the hardware has no such operation.  */
16463 
16464 int
rs6000_emit_cmove(rtx dest,rtx op,rtx true_cond,rtx false_cond)16465 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
16466 {
16467   enum rtx_code code = GET_CODE (op);
16468   rtx op0 = XEXP (op, 0);
16469   rtx op1 = XEXP (op, 1);
16470   REAL_VALUE_TYPE c1;
16471   enum machine_mode compare_mode = GET_MODE (op0);
16472   enum machine_mode result_mode = GET_MODE (dest);
16473   rtx temp;
16474   bool is_against_zero;
16475 
16476   /* These modes should always match.  */
16477   if (GET_MODE (op1) != compare_mode
16478       /* In the isel case however, we can use a compare immediate, so
16479 	 op1 may be a small constant.  */
16480       && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
16481     return 0;
16482   if (GET_MODE (true_cond) != result_mode)
16483     return 0;
16484   if (GET_MODE (false_cond) != result_mode)
16485     return 0;
16486 
16487   /* Don't allow using floating point comparisons for integer results for
16488      now.  */
16489   if (FLOAT_MODE_P (compare_mode) && !FLOAT_MODE_P (result_mode))
16490     return 0;
16491 
16492   /* First, work out if the hardware can do this at all, or
16493      if it's too slow....  */
16494   if (!FLOAT_MODE_P (compare_mode))
16495     {
16496       if (TARGET_ISEL)
16497 	return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
16498       return 0;
16499     }
16500   else if (TARGET_HARD_FLOAT && !TARGET_FPRS
16501 	   && SCALAR_FLOAT_MODE_P (compare_mode))
16502     return 0;
16503 
16504   is_against_zero = op1 == CONST0_RTX (compare_mode);
16505 
16506   /* A floating-point subtract might overflow, underflow, or produce
16507      an inexact result, thus changing the floating-point flags, so it
16508      can't be generated if we care about that.  It's safe if one side
16509      of the construct is zero, since then no subtract will be
16510      generated.  */
16511   if (SCALAR_FLOAT_MODE_P (compare_mode)
16512       && flag_trapping_math && ! is_against_zero)
16513     return 0;
16514 
16515   /* Eliminate half of the comparisons by switching operands, this
16516      makes the remaining code simpler.  */
16517   if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
16518       || code == LTGT || code == LT || code == UNLE)
16519     {
16520       code = reverse_condition_maybe_unordered (code);
16521       temp = true_cond;
16522       true_cond = false_cond;
16523       false_cond = temp;
16524     }
16525 
16526   /* UNEQ and LTGT take four instructions for a comparison with zero,
16527      it'll probably be faster to use a branch here too.  */
16528   if (code == UNEQ && HONOR_NANS (compare_mode))
16529     return 0;
16530 
16531   if (GET_CODE (op1) == CONST_DOUBLE)
16532     REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
16533 
16534   /* We're going to try to implement comparisons by performing
16535      a subtract, then comparing against zero.  Unfortunately,
16536      Inf - Inf is NaN which is not zero, and so if we don't
16537      know that the operand is finite and the comparison
16538      would treat EQ different to UNORDERED, we can't do it.  */
16539   if (HONOR_INFINITIES (compare_mode)
16540       && code != GT && code != UNGE
16541       && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
16542       /* Constructs of the form (a OP b ? a : b) are safe.  */
16543       && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
16544 	  || (! rtx_equal_p (op0, true_cond)
16545 	      && ! rtx_equal_p (op1, true_cond))))
16546     return 0;
16547 
16548   /* At this point we know we can use fsel.  */
16549 
16550   /* Reduce the comparison to a comparison against zero.  */
16551   if (! is_against_zero)
16552     {
16553       temp = gen_reg_rtx (compare_mode);
16554       emit_insn (gen_rtx_SET (VOIDmode, temp,
16555 			      gen_rtx_MINUS (compare_mode, op0, op1)));
16556       op0 = temp;
16557       op1 = CONST0_RTX (compare_mode);
16558     }
16559 
16560   /* If we don't care about NaNs we can reduce some of the comparisons
16561      down to faster ones.  */
16562   if (! HONOR_NANS (compare_mode))
16563     switch (code)
16564       {
16565       case GT:
16566 	code = LE;
16567 	temp = true_cond;
16568 	true_cond = false_cond;
16569 	false_cond = temp;
16570 	break;
16571       case UNGE:
16572 	code = GE;
16573 	break;
16574       case UNEQ:
16575 	code = EQ;
16576 	break;
16577       default:
16578 	break;
16579       }
16580 
16581   /* Now, reduce everything down to a GE.  */
16582   switch (code)
16583     {
16584     case GE:
16585       break;
16586 
16587     case LE:
16588       temp = gen_reg_rtx (compare_mode);
16589       emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
16590       op0 = temp;
16591       break;
16592 
16593     case ORDERED:
16594       temp = gen_reg_rtx (compare_mode);
16595       emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
16596       op0 = temp;
16597       break;
16598 
16599     case EQ:
16600       temp = gen_reg_rtx (compare_mode);
16601       emit_insn (gen_rtx_SET (VOIDmode, temp,
16602 			      gen_rtx_NEG (compare_mode,
16603 					   gen_rtx_ABS (compare_mode, op0))));
16604       op0 = temp;
16605       break;
16606 
16607     case UNGE:
16608       /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
16609       temp = gen_reg_rtx (result_mode);
16610       emit_insn (gen_rtx_SET (VOIDmode, temp,
16611 			      gen_rtx_IF_THEN_ELSE (result_mode,
16612 						    gen_rtx_GE (VOIDmode,
16613 								op0, op1),
16614 						    true_cond, false_cond)));
16615       false_cond = true_cond;
16616       true_cond = temp;
16617 
16618       temp = gen_reg_rtx (compare_mode);
16619       emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
16620       op0 = temp;
16621       break;
16622 
16623     case GT:
16624       /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
16625       temp = gen_reg_rtx (result_mode);
16626       emit_insn (gen_rtx_SET (VOIDmode, temp,
16627 			      gen_rtx_IF_THEN_ELSE (result_mode,
16628 						    gen_rtx_GE (VOIDmode,
16629 								op0, op1),
16630 						    true_cond, false_cond)));
16631       true_cond = false_cond;
16632       false_cond = temp;
16633 
16634       temp = gen_reg_rtx (compare_mode);
16635       emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
16636       op0 = temp;
16637       break;
16638 
16639     default:
16640       gcc_unreachable ();
16641     }
16642 
16643   emit_insn (gen_rtx_SET (VOIDmode, dest,
16644 			  gen_rtx_IF_THEN_ELSE (result_mode,
16645 						gen_rtx_GE (VOIDmode,
16646 							    op0, op1),
16647 						true_cond, false_cond)));
16648   return 1;
16649 }
16650 
16651 /* Same as above, but for ints (isel).  */
16652 
16653 static int
rs6000_emit_int_cmove(rtx dest,rtx op,rtx true_cond,rtx false_cond)16654 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
16655 {
16656   rtx condition_rtx, cr;
16657   enum machine_mode mode = GET_MODE (dest);
16658   enum rtx_code cond_code;
16659   rtx (*isel_func) (rtx, rtx, rtx, rtx, rtx);
16660   bool signedp;
16661 
16662   if (mode != SImode && (!TARGET_POWERPC64 || mode != DImode))
16663     return 0;
16664 
16665   /* We still have to do the compare, because isel doesn't do a
16666      compare, it just looks at the CRx bits set by a previous compare
16667      instruction.  */
16668   condition_rtx = rs6000_generate_compare (op, mode);
16669   cond_code = GET_CODE (condition_rtx);
16670   cr = XEXP (condition_rtx, 0);
16671   signedp = GET_MODE (cr) == CCmode;
16672 
16673   isel_func = (mode == SImode
16674 	       ? (signedp ? gen_isel_signed_si : gen_isel_unsigned_si)
16675 	       : (signedp ? gen_isel_signed_di : gen_isel_unsigned_di));
16676 
16677   switch (cond_code)
16678     {
16679     case LT: case GT: case LTU: case GTU: case EQ:
16680       /* isel handles these directly.  */
16681       break;
16682 
16683     default:
16684       /* We need to swap the sense of the comparison.  */
16685       {
16686 	rtx t = true_cond;
16687 	true_cond = false_cond;
16688 	false_cond = t;
16689 	PUT_CODE (condition_rtx, reverse_condition (cond_code));
16690       }
16691       break;
16692     }
16693 
16694   false_cond = force_reg (mode, false_cond);
16695   if (true_cond != const0_rtx)
16696     true_cond = force_reg (mode, true_cond);
16697 
16698   emit_insn (isel_func (dest, condition_rtx, true_cond, false_cond, cr));
16699 
16700   return 1;
16701 }
16702 
16703 const char *
output_isel(rtx * operands)16704 output_isel (rtx *operands)
16705 {
16706   enum rtx_code code;
16707 
16708   code = GET_CODE (operands[1]);
16709 
16710   if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
16711     {
16712       gcc_assert (GET_CODE (operands[2]) == REG
16713 		  && GET_CODE (operands[3]) == REG);
16714       PUT_CODE (operands[1], reverse_condition (code));
16715       return "isel %0,%3,%2,%j1";
16716     }
16717 
16718   return "isel %0,%2,%3,%j1";
16719 }
16720 
16721 void
rs6000_emit_minmax(rtx dest,enum rtx_code code,rtx op0,rtx op1)16722 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
16723 {
16724   enum machine_mode mode = GET_MODE (op0);
16725   enum rtx_code c;
16726   rtx target;
16727 
16728   /* VSX/altivec have direct min/max insns.  */
16729   if ((code == SMAX || code == SMIN)
16730       && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
16731 	  || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))))
16732     {
16733       emit_insn (gen_rtx_SET (VOIDmode,
16734 			      dest,
16735 			      gen_rtx_fmt_ee (code, mode, op0, op1)));
16736       return;
16737     }
16738 
16739   if (code == SMAX || code == SMIN)
16740     c = GE;
16741   else
16742     c = GEU;
16743 
16744   if (code == SMAX || code == UMAX)
16745     target = emit_conditional_move (dest, c, op0, op1, mode,
16746 				    op0, op1, mode, 0);
16747   else
16748     target = emit_conditional_move (dest, c, op0, op1, mode,
16749 				    op1, op0, mode, 0);
16750   gcc_assert (target);
16751   if (target != dest)
16752     emit_move_insn (dest, target);
16753 }
16754 
16755 /* A subroutine of the atomic operation splitters.  Jump to LABEL if
16756    COND is true.  Mark the jump as unlikely to be taken.  */
16757 
16758 static void
emit_unlikely_jump(rtx cond,rtx label)16759 emit_unlikely_jump (rtx cond, rtx label)
16760 {
16761   rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
16762   rtx x;
16763 
16764   x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
16765   x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x));
16766   add_reg_note (x, REG_BR_PROB, very_unlikely);
16767 }
16768 
16769 /* A subroutine of the atomic operation splitters.  Emit a load-locked
16770    instruction in MODE.  */
16771 
16772 static void
emit_load_locked(enum machine_mode mode,rtx reg,rtx mem)16773 emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)
16774 {
16775   rtx (*fn) (rtx, rtx) = NULL;
16776 
16777   switch (mode)
16778     {
16779     case SImode:
16780       fn = gen_load_lockedsi;
16781       break;
16782     case DImode:
16783       fn = gen_load_lockeddi;
16784       break;
16785     default:
16786       gcc_unreachable ();
16787     }
16788   emit_insn (fn (reg, mem));
16789 }
16790 
16791 /* A subroutine of the atomic operation splitters.  Emit a store-conditional
16792    instruction in MODE.  */
16793 
16794 static void
emit_store_conditional(enum machine_mode mode,rtx res,rtx mem,rtx val)16795 emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val)
16796 {
16797   rtx (*fn) (rtx, rtx, rtx) = NULL;
16798 
16799   switch (mode)
16800     {
16801     case SImode:
16802       fn = gen_store_conditionalsi;
16803       break;
16804     case DImode:
16805       fn = gen_store_conditionaldi;
16806       break;
16807     default:
16808       gcc_unreachable ();
16809     }
16810 
16811   /* Emit sync before stwcx. to address PPC405 Erratum.  */
16812   if (PPC405_ERRATUM77)
16813     emit_insn (gen_hwsync ());
16814 
16815   emit_insn (fn (res, mem, val));
16816 }
16817 
16818 /* Expand barriers before and after a load_locked/store_cond sequence.  */
16819 
16820 static rtx
rs6000_pre_atomic_barrier(rtx mem,enum memmodel model)16821 rs6000_pre_atomic_barrier (rtx mem, enum memmodel model)
16822 {
16823   rtx addr = XEXP (mem, 0);
16824   int strict_p = (reload_in_progress || reload_completed);
16825 
16826   if (!legitimate_indirect_address_p (addr, strict_p)
16827       && !legitimate_indexed_address_p (addr, strict_p))
16828     {
16829       addr = force_reg (Pmode, addr);
16830       mem = replace_equiv_address_nv (mem, addr);
16831     }
16832 
16833   switch (model)
16834     {
16835     case MEMMODEL_RELAXED:
16836     case MEMMODEL_CONSUME:
16837     case MEMMODEL_ACQUIRE:
16838       break;
16839     case MEMMODEL_RELEASE:
16840     case MEMMODEL_ACQ_REL:
16841       emit_insn (gen_lwsync ());
16842       break;
16843     case MEMMODEL_SEQ_CST:
16844       emit_insn (gen_hwsync ());
16845       break;
16846     default:
16847       gcc_unreachable ();
16848     }
16849   return mem;
16850 }
16851 
16852 static void
rs6000_post_atomic_barrier(enum memmodel model)16853 rs6000_post_atomic_barrier (enum memmodel model)
16854 {
16855   switch (model)
16856     {
16857     case MEMMODEL_RELAXED:
16858     case MEMMODEL_CONSUME:
16859     case MEMMODEL_RELEASE:
16860       break;
16861     case MEMMODEL_ACQUIRE:
16862     case MEMMODEL_ACQ_REL:
16863     case MEMMODEL_SEQ_CST:
16864       emit_insn (gen_isync ());
16865       break;
16866     default:
16867       gcc_unreachable ();
16868     }
16869 }
16870 
16871 /* A subroutine of the various atomic expanders.  For sub-word operations,
16872    we must adjust things to operate on SImode.  Given the original MEM,
16873    return a new aligned memory.  Also build and return the quantities by
16874    which to shift and mask.  */
16875 
16876 static rtx
rs6000_adjust_atomic_subword(rtx orig_mem,rtx * pshift,rtx * pmask)16877 rs6000_adjust_atomic_subword (rtx orig_mem, rtx *pshift, rtx *pmask)
16878 {
16879   rtx addr, align, shift, mask, mem;
16880   HOST_WIDE_INT shift_mask;
16881   enum machine_mode mode = GET_MODE (orig_mem);
16882 
16883   /* For smaller modes, we have to implement this via SImode.  */
16884   shift_mask = (mode == QImode ? 0x18 : 0x10);
16885 
16886   addr = XEXP (orig_mem, 0);
16887   addr = force_reg (GET_MODE (addr), addr);
16888 
16889   /* Aligned memory containing subword.  Generate a new memory.  We
16890      do not want any of the existing MEM_ATTR data, as we're now
16891      accessing memory outside the original object.  */
16892   align = expand_simple_binop (Pmode, AND, addr, GEN_INT (-4),
16893 			       NULL_RTX, 1, OPTAB_LIB_WIDEN);
16894   mem = gen_rtx_MEM (SImode, align);
16895   MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (orig_mem);
16896   if (MEM_ALIAS_SET (orig_mem) == ALIAS_SET_MEMORY_BARRIER)
16897     set_mem_alias_set (mem, ALIAS_SET_MEMORY_BARRIER);
16898 
16899   /* Shift amount for subword relative to aligned word.  */
16900   shift = gen_reg_rtx (SImode);
16901   addr = gen_lowpart (SImode, addr);
16902   emit_insn (gen_rlwinm (shift, addr, GEN_INT (3), GEN_INT (shift_mask)));
16903   shift = expand_simple_binop (SImode, XOR, shift, GEN_INT (shift_mask),
16904 			       shift, 1, OPTAB_LIB_WIDEN);
16905   *pshift = shift;
16906 
16907   /* Mask for insertion.  */
16908   mask = expand_simple_binop (SImode, ASHIFT, GEN_INT (GET_MODE_MASK (mode)),
16909 			      shift, NULL_RTX, 1, OPTAB_LIB_WIDEN);
16910   *pmask = mask;
16911 
16912   return mem;
16913 }
16914 
16915 /* A subroutine of the various atomic expanders.  For sub-word operands,
16916    combine OLDVAL and NEWVAL via MASK.  Returns a new pseduo.  */
16917 
16918 static rtx
rs6000_mask_atomic_subword(rtx oldval,rtx newval,rtx mask)16919 rs6000_mask_atomic_subword (rtx oldval, rtx newval, rtx mask)
16920 {
16921   rtx x;
16922 
16923   x = gen_reg_rtx (SImode);
16924   emit_insn (gen_rtx_SET (VOIDmode, x,
16925 			  gen_rtx_AND (SImode,
16926 				       gen_rtx_NOT (SImode, mask),
16927 				       oldval)));
16928 
16929   x = expand_simple_binop (SImode, IOR, newval, x, x, 1, OPTAB_LIB_WIDEN);
16930 
16931   return x;
16932 }
16933 
16934 /* A subroutine of the various atomic expanders.  For sub-word operands,
16935    extract WIDE to NARROW via SHIFT.  */
16936 
16937 static void
rs6000_finish_atomic_subword(rtx narrow,rtx wide,rtx shift)16938 rs6000_finish_atomic_subword (rtx narrow, rtx wide, rtx shift)
16939 {
16940   wide = expand_simple_binop (SImode, LSHIFTRT, wide, shift,
16941 			      wide, 1, OPTAB_LIB_WIDEN);
16942   emit_move_insn (narrow, gen_lowpart (GET_MODE (narrow), wide));
16943 }
16944 
16945 /* Expand an atomic compare and swap operation.  */
16946 
16947 void
rs6000_expand_atomic_compare_and_swap(rtx operands[])16948 rs6000_expand_atomic_compare_and_swap (rtx operands[])
16949 {
16950   rtx boolval, retval, mem, oldval, newval, cond;
16951   rtx label1, label2, x, mask, shift;
16952   enum machine_mode mode;
16953   enum memmodel mod_s, mod_f;
16954   bool is_weak;
16955 
16956   boolval = operands[0];
16957   retval = operands[1];
16958   mem = operands[2];
16959   oldval = operands[3];
16960   newval = operands[4];
16961   is_weak = (INTVAL (operands[5]) != 0);
16962   mod_s = (enum memmodel) INTVAL (operands[6]);
16963   mod_f = (enum memmodel) INTVAL (operands[7]);
16964   mode = GET_MODE (mem);
16965 
16966   mask = shift = NULL_RTX;
16967   if (mode == QImode || mode == HImode)
16968     {
16969       mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
16970 
16971       /* Shift and mask OLDVAL into position with the word.  */
16972       oldval = convert_modes (SImode, mode, oldval, 1);
16973       oldval = expand_simple_binop (SImode, ASHIFT, oldval, shift,
16974 				    NULL_RTX, 1, OPTAB_LIB_WIDEN);
16975 
16976       /* Shift and mask NEWVAL into position within the word.  */
16977       newval = convert_modes (SImode, mode, newval, 1);
16978       newval = expand_simple_binop (SImode, ASHIFT, newval, shift,
16979 				    NULL_RTX, 1, OPTAB_LIB_WIDEN);
16980 
16981       /* Prepare to adjust the return value.  */
16982       retval = gen_reg_rtx (SImode);
16983       mode = SImode;
16984     }
16985   else if (reg_overlap_mentioned_p (retval, oldval))
16986     oldval = copy_to_reg (oldval);
16987 
16988   mem = rs6000_pre_atomic_barrier (mem, mod_s);
16989 
16990   label1 = NULL_RTX;
16991   if (!is_weak)
16992     {
16993       label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
16994       emit_label (XEXP (label1, 0));
16995     }
16996   label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
16997 
16998   emit_load_locked (mode, retval, mem);
16999 
17000   x = retval;
17001   if (mask)
17002     {
17003       x = expand_simple_binop (SImode, AND, retval, mask,
17004 			       NULL_RTX, 1, OPTAB_LIB_WIDEN);
17005     }
17006 
17007   cond = gen_reg_rtx (CCmode);
17008   x = gen_rtx_COMPARE (CCmode, x, oldval);
17009   emit_insn (gen_rtx_SET (VOIDmode, cond, x));
17010 
17011   x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
17012   emit_unlikely_jump (x, label2);
17013 
17014   x = newval;
17015   if (mask)
17016     x = rs6000_mask_atomic_subword (retval, newval, mask);
17017 
17018   emit_store_conditional (mode, cond, mem, x);
17019 
17020   if (!is_weak)
17021     {
17022       x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
17023       emit_unlikely_jump (x, label1);
17024     }
17025 
17026   if (mod_f != MEMMODEL_RELAXED)
17027     emit_label (XEXP (label2, 0));
17028 
17029   rs6000_post_atomic_barrier (mod_s);
17030 
17031   if (mod_f == MEMMODEL_RELAXED)
17032     emit_label (XEXP (label2, 0));
17033 
17034   if (shift)
17035     rs6000_finish_atomic_subword (operands[1], retval, shift);
17036 
17037   /* In all cases, CR0 contains EQ on success, and NE on failure.  */
17038   x = gen_rtx_EQ (SImode, cond, const0_rtx);
17039   emit_insn (gen_rtx_SET (VOIDmode, boolval, x));
17040 }
17041 
17042 /* Expand an atomic exchange operation.  */
17043 
17044 void
rs6000_expand_atomic_exchange(rtx operands[])17045 rs6000_expand_atomic_exchange (rtx operands[])
17046 {
17047   rtx retval, mem, val, cond;
17048   enum machine_mode mode;
17049   enum memmodel model;
17050   rtx label, x, mask, shift;
17051 
17052   retval = operands[0];
17053   mem = operands[1];
17054   val = operands[2];
17055   model = (enum memmodel) INTVAL (operands[3]);
17056   mode = GET_MODE (mem);
17057 
17058   mask = shift = NULL_RTX;
17059   if (mode == QImode || mode == HImode)
17060     {
17061       mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
17062 
17063       /* Shift and mask VAL into position with the word.  */
17064       val = convert_modes (SImode, mode, val, 1);
17065       val = expand_simple_binop (SImode, ASHIFT, val, shift,
17066 				 NULL_RTX, 1, OPTAB_LIB_WIDEN);
17067 
17068       /* Prepare to adjust the return value.  */
17069       retval = gen_reg_rtx (SImode);
17070       mode = SImode;
17071     }
17072 
17073   mem = rs6000_pre_atomic_barrier (mem, model);
17074 
17075   label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
17076   emit_label (XEXP (label, 0));
17077 
17078   emit_load_locked (mode, retval, mem);
17079 
17080   x = val;
17081   if (mask)
17082     x = rs6000_mask_atomic_subword (retval, val, mask);
17083 
17084   cond = gen_reg_rtx (CCmode);
17085   emit_store_conditional (mode, cond, mem, x);
17086 
17087   x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
17088   emit_unlikely_jump (x, label);
17089 
17090   rs6000_post_atomic_barrier (model);
17091 
17092   if (shift)
17093     rs6000_finish_atomic_subword (operands[0], retval, shift);
17094 }
17095 
17096 /* Expand an atomic fetch-and-operate pattern.  CODE is the binary operation
17097    to perform.  MEM is the memory on which to operate.  VAL is the second
17098    operand of the binary operator.  BEFORE and AFTER are optional locations to
17099    return the value of MEM either before of after the operation.  MODEL_RTX
17100    is a CONST_INT containing the memory model to use.  */
17101 
17102 void
rs6000_expand_atomic_op(enum rtx_code code,rtx mem,rtx val,rtx orig_before,rtx orig_after,rtx model_rtx)17103 rs6000_expand_atomic_op (enum rtx_code code, rtx mem, rtx val,
17104 			 rtx orig_before, rtx orig_after, rtx model_rtx)
17105 {
17106   enum memmodel model = (enum memmodel) INTVAL (model_rtx);
17107   enum machine_mode mode = GET_MODE (mem);
17108   rtx label, x, cond, mask, shift;
17109   rtx before = orig_before, after = orig_after;
17110 
17111   mask = shift = NULL_RTX;
17112   if (mode == QImode || mode == HImode)
17113     {
17114       mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
17115 
17116       /* Shift and mask VAL into position with the word.  */
17117       val = convert_modes (SImode, mode, val, 1);
17118       val = expand_simple_binop (SImode, ASHIFT, val, shift,
17119 				 NULL_RTX, 1, OPTAB_LIB_WIDEN);
17120 
17121       switch (code)
17122 	{
17123 	case IOR:
17124 	case XOR:
17125 	  /* We've already zero-extended VAL.  That is sufficient to
17126 	     make certain that it does not affect other bits.  */
17127 	  mask = NULL;
17128 	  break;
17129 
17130 	case AND:
17131 	  /* If we make certain that all of the other bits in VAL are
17132 	     set, that will be sufficient to not affect other bits.  */
17133 	  x = gen_rtx_NOT (SImode, mask);
17134 	  x = gen_rtx_IOR (SImode, x, val);
17135 	  emit_insn (gen_rtx_SET (VOIDmode, val, x));
17136 	  mask = NULL;
17137 	  break;
17138 
17139 	case NOT:
17140 	case PLUS:
17141 	case MINUS:
17142 	  /* These will all affect bits outside the field and need
17143 	     adjustment via MASK within the loop.  */
17144 	  break;
17145 
17146 	default:
17147 	  gcc_unreachable ();
17148 	}
17149 
17150       /* Prepare to adjust the return value.  */
17151       before = gen_reg_rtx (SImode);
17152       if (after)
17153 	after = gen_reg_rtx (SImode);
17154       mode = SImode;
17155     }
17156 
17157   mem = rs6000_pre_atomic_barrier (mem, model);
17158 
17159   label = gen_label_rtx ();
17160   emit_label (label);
17161   label = gen_rtx_LABEL_REF (VOIDmode, label);
17162 
17163   if (before == NULL_RTX)
17164     before = gen_reg_rtx (mode);
17165 
17166   emit_load_locked (mode, before, mem);
17167 
17168   if (code == NOT)
17169     {
17170       x = expand_simple_binop (mode, AND, before, val,
17171 			       NULL_RTX, 1, OPTAB_LIB_WIDEN);
17172       after = expand_simple_unop (mode, NOT, x, after, 1);
17173     }
17174   else
17175     {
17176       after = expand_simple_binop (mode, code, before, val,
17177 				   after, 1, OPTAB_LIB_WIDEN);
17178     }
17179 
17180   x = after;
17181   if (mask)
17182     {
17183       x = expand_simple_binop (SImode, AND, after, mask,
17184 			       NULL_RTX, 1, OPTAB_LIB_WIDEN);
17185       x = rs6000_mask_atomic_subword (before, x, mask);
17186     }
17187 
17188   cond = gen_reg_rtx (CCmode);
17189   emit_store_conditional (mode, cond, mem, x);
17190 
17191   x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
17192   emit_unlikely_jump (x, label);
17193 
17194   rs6000_post_atomic_barrier (model);
17195 
17196   if (shift)
17197     {
17198       if (orig_before)
17199 	rs6000_finish_atomic_subword (orig_before, before, shift);
17200       if (orig_after)
17201 	rs6000_finish_atomic_subword (orig_after, after, shift);
17202     }
17203   else if (orig_after && after != orig_after)
17204     emit_move_insn (orig_after, after);
17205 }
17206 
17207 /* Emit instructions to move SRC to DST.  Called by splitters for
17208    multi-register moves.  It will emit at most one instruction for
17209    each register that is accessed; that is, it won't emit li/lis pairs
17210    (or equivalent for 64-bit code).  One of SRC or DST must be a hard
17211    register.  */
17212 
17213 void
rs6000_split_multireg_move(rtx dst,rtx src)17214 rs6000_split_multireg_move (rtx dst, rtx src)
17215 {
17216   /* The register number of the first register being moved.  */
17217   int reg;
17218   /* The mode that is to be moved.  */
17219   enum machine_mode mode;
17220   /* The mode that the move is being done in, and its size.  */
17221   enum machine_mode reg_mode;
17222   int reg_mode_size;
17223   /* The number of registers that will be moved.  */
17224   int nregs;
17225 
17226   reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
17227   mode = GET_MODE (dst);
17228   nregs = hard_regno_nregs[reg][mode];
17229   if (FP_REGNO_P (reg))
17230     reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode :
17231 	((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? DFmode : SFmode);
17232   else if (ALTIVEC_REGNO_P (reg))
17233     reg_mode = V16QImode;
17234   else if (TARGET_E500_DOUBLE && mode == TFmode)
17235     reg_mode = DFmode;
17236   else
17237     reg_mode = word_mode;
17238   reg_mode_size = GET_MODE_SIZE (reg_mode);
17239 
17240   gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
17241 
17242   if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
17243     {
17244       /* Move register range backwards, if we might have destructive
17245 	 overlap.  */
17246       int i;
17247       for (i = nregs - 1; i >= 0; i--)
17248 	emit_insn (gen_rtx_SET (VOIDmode,
17249 				simplify_gen_subreg (reg_mode, dst, mode,
17250 						     i * reg_mode_size),
17251 				simplify_gen_subreg (reg_mode, src, mode,
17252 						     i * reg_mode_size)));
17253     }
17254   else
17255     {
17256       int i;
17257       int j = -1;
17258       bool used_update = false;
17259       rtx restore_basereg = NULL_RTX;
17260 
17261       if (MEM_P (src) && INT_REGNO_P (reg))
17262 	{
17263 	  rtx breg;
17264 
17265 	  if (GET_CODE (XEXP (src, 0)) == PRE_INC
17266 	      || GET_CODE (XEXP (src, 0)) == PRE_DEC)
17267 	    {
17268 	      rtx delta_rtx;
17269 	      breg = XEXP (XEXP (src, 0), 0);
17270 	      delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
17271 			   ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
17272 			   : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
17273 	      emit_insn (gen_add3_insn (breg, breg, delta_rtx));
17274 	      src = replace_equiv_address (src, breg);
17275 	    }
17276 	  else if (! rs6000_offsettable_memref_p (src, reg_mode))
17277 	    {
17278 	      if (GET_CODE (XEXP (src, 0)) == PRE_MODIFY)
17279 		{
17280 		  rtx basereg = XEXP (XEXP (src, 0), 0);
17281 		  if (TARGET_UPDATE)
17282 		    {
17283 		      rtx ndst = simplify_gen_subreg (reg_mode, dst, mode, 0);
17284 		      emit_insn (gen_rtx_SET (VOIDmode, ndst,
17285 				 gen_rtx_MEM (reg_mode, XEXP (src, 0))));
17286 		      used_update = true;
17287 		    }
17288 		  else
17289 		    emit_insn (gen_rtx_SET (VOIDmode, basereg,
17290 			       XEXP (XEXP (src, 0), 1)));
17291 		  src = replace_equiv_address (src, basereg);
17292 		}
17293 	      else
17294 		{
17295 		  rtx basereg = gen_rtx_REG (Pmode, reg);
17296 		  emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
17297 		  src = replace_equiv_address (src, basereg);
17298 		}
17299 	    }
17300 
17301 	  breg = XEXP (src, 0);
17302 	  if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
17303 	    breg = XEXP (breg, 0);
17304 
17305 	  /* If the base register we are using to address memory is
17306 	     also a destination reg, then change that register last.  */
17307 	  if (REG_P (breg)
17308 	      && REGNO (breg) >= REGNO (dst)
17309 	      && REGNO (breg) < REGNO (dst) + nregs)
17310 	    j = REGNO (breg) - REGNO (dst);
17311 	}
17312       else if (MEM_P (dst) && INT_REGNO_P (reg))
17313 	{
17314 	  rtx breg;
17315 
17316 	  if (GET_CODE (XEXP (dst, 0)) == PRE_INC
17317 	      || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
17318 	    {
17319 	      rtx delta_rtx;
17320 	      breg = XEXP (XEXP (dst, 0), 0);
17321 	      delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
17322 			   ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
17323 			   : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
17324 
17325 	      /* We have to update the breg before doing the store.
17326 		 Use store with update, if available.  */
17327 
17328 	      if (TARGET_UPDATE)
17329 		{
17330 		  rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
17331 		  emit_insn (TARGET_32BIT
17332 			     ? (TARGET_POWERPC64
17333 				? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
17334 				: gen_movsi_update (breg, breg, delta_rtx, nsrc))
17335 			     : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
17336 		  used_update = true;
17337 		}
17338 	      else
17339 		emit_insn (gen_add3_insn (breg, breg, delta_rtx));
17340 	      dst = replace_equiv_address (dst, breg);
17341 	    }
17342 	  else if (!rs6000_offsettable_memref_p (dst, reg_mode)
17343 		   && GET_CODE (XEXP (dst, 0)) != LO_SUM)
17344 	    {
17345 	      if (GET_CODE (XEXP (dst, 0)) == PRE_MODIFY)
17346 		{
17347 		  rtx basereg = XEXP (XEXP (dst, 0), 0);
17348 		  if (TARGET_UPDATE)
17349 		    {
17350 		      rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
17351 		      emit_insn (gen_rtx_SET (VOIDmode,
17352 				 gen_rtx_MEM (reg_mode, XEXP (dst, 0)), nsrc));
17353 		      used_update = true;
17354 		    }
17355 		  else
17356 		    emit_insn (gen_rtx_SET (VOIDmode, basereg,
17357 			       XEXP (XEXP (dst, 0), 1)));
17358 		  dst = replace_equiv_address (dst, basereg);
17359 		}
17360 	      else
17361 		{
17362 		  rtx basereg = XEXP (XEXP (dst, 0), 0);
17363 		  rtx offsetreg = XEXP (XEXP (dst, 0), 1);
17364 		  gcc_assert (GET_CODE (XEXP (dst, 0)) == PLUS
17365 			      && REG_P (basereg)
17366 			      && REG_P (offsetreg)
17367 			      && REGNO (basereg) != REGNO (offsetreg));
17368 		  if (REGNO (basereg) == 0)
17369 		    {
17370 		      rtx tmp = offsetreg;
17371 		      offsetreg = basereg;
17372 		      basereg = tmp;
17373 		    }
17374 		  emit_insn (gen_add3_insn (basereg, basereg, offsetreg));
17375 		  restore_basereg = gen_sub3_insn (basereg, basereg, offsetreg);
17376 		  dst = replace_equiv_address (dst, basereg);
17377 		}
17378 	    }
17379 	  else if (GET_CODE (XEXP (dst, 0)) != LO_SUM)
17380 	    gcc_assert (rs6000_offsettable_memref_p (dst, reg_mode));
17381 	}
17382 
17383       for (i = 0; i < nregs; i++)
17384 	{
17385 	  /* Calculate index to next subword.  */
17386 	  ++j;
17387 	  if (j == nregs)
17388 	    j = 0;
17389 
17390 	  /* If compiler already emitted move of first word by
17391 	     store with update, no need to do anything.  */
17392 	  if (j == 0 && used_update)
17393 	    continue;
17394 
17395 	  emit_insn (gen_rtx_SET (VOIDmode,
17396 				  simplify_gen_subreg (reg_mode, dst, mode,
17397 						       j * reg_mode_size),
17398 				  simplify_gen_subreg (reg_mode, src, mode,
17399 						       j * reg_mode_size)));
17400 	}
17401       if (restore_basereg != NULL_RTX)
17402 	emit_insn (restore_basereg);
17403     }
17404 }
17405 
17406 
17407 /* This page contains routines that are used to determine what the
17408    function prologue and epilogue code will do and write them out.  */
17409 
17410 static inline bool
save_reg_p(int r)17411 save_reg_p (int r)
17412 {
17413   return !call_used_regs[r] && df_regs_ever_live_p (r);
17414 }
17415 
17416 /* Return the first fixed-point register that is required to be
17417    saved. 32 if none.  */
17418 
17419 int
first_reg_to_save(void)17420 first_reg_to_save (void)
17421 {
17422   int first_reg;
17423 
17424   /* Find lowest numbered live register.  */
17425   for (first_reg = 13; first_reg <= 31; first_reg++)
17426     if (save_reg_p (first_reg))
17427       break;
17428 
17429   if (first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM
17430       && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
17431 	  || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
17432 	  || (TARGET_TOC && TARGET_MINIMAL_TOC))
17433       && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
17434     first_reg = RS6000_PIC_OFFSET_TABLE_REGNUM;
17435 
17436 #if TARGET_MACHO
17437   if (flag_pic
17438       && crtl->uses_pic_offset_table
17439       && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
17440     return RS6000_PIC_OFFSET_TABLE_REGNUM;
17441 #endif
17442 
17443   return first_reg;
17444 }
17445 
17446 /* Similar, for FP regs.  */
17447 
17448 int
first_fp_reg_to_save(void)17449 first_fp_reg_to_save (void)
17450 {
17451   int first_reg;
17452 
17453   /* Find lowest numbered live register.  */
17454   for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
17455     if (save_reg_p (first_reg))
17456       break;
17457 
17458   return first_reg;
17459 }
17460 
17461 /* Similar, for AltiVec regs.  */
17462 
17463 static int
first_altivec_reg_to_save(void)17464 first_altivec_reg_to_save (void)
17465 {
17466   int i;
17467 
17468   /* Stack frame remains as is unless we are in AltiVec ABI.  */
17469   if (! TARGET_ALTIVEC_ABI)
17470     return LAST_ALTIVEC_REGNO + 1;
17471 
17472   /* On Darwin, the unwind routines are compiled without
17473      TARGET_ALTIVEC, and use save_world to save/restore the
17474      altivec registers when necessary.  */
17475   if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
17476       && ! TARGET_ALTIVEC)
17477     return FIRST_ALTIVEC_REGNO + 20;
17478 
17479   /* Find lowest numbered live register.  */
17480   for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
17481     if (save_reg_p (i))
17482       break;
17483 
17484   return i;
17485 }
17486 
17487 /* Return a 32-bit mask of the AltiVec registers we need to set in
17488    VRSAVE.  Bit n of the return value is 1 if Vn is live.  The MSB in
17489    the 32-bit word is 0.  */
17490 
17491 static unsigned int
compute_vrsave_mask(void)17492 compute_vrsave_mask (void)
17493 {
17494   unsigned int i, mask = 0;
17495 
17496   /* On Darwin, the unwind routines are compiled without
17497      TARGET_ALTIVEC, and use save_world to save/restore the
17498      call-saved altivec registers when necessary.  */
17499   if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
17500       && ! TARGET_ALTIVEC)
17501     mask |= 0xFFF;
17502 
17503   /* First, find out if we use _any_ altivec registers.  */
17504   for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
17505     if (df_regs_ever_live_p (i))
17506       mask |= ALTIVEC_REG_BIT (i);
17507 
17508   if (mask == 0)
17509     return mask;
17510 
17511   /* Next, remove the argument registers from the set.  These must
17512      be in the VRSAVE mask set by the caller, so we don't need to add
17513      them in again.  More importantly, the mask we compute here is
17514      used to generate CLOBBERs in the set_vrsave insn, and we do not
17515      wish the argument registers to die.  */
17516   for (i = crtl->args.info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
17517     mask &= ~ALTIVEC_REG_BIT (i);
17518 
17519   /* Similarly, remove the return value from the set.  */
17520   {
17521     bool yes = false;
17522     diddle_return_value (is_altivec_return_reg, &yes);
17523     if (yes)
17524       mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
17525   }
17526 
17527   return mask;
17528 }
17529 
17530 /* For a very restricted set of circumstances, we can cut down the
17531    size of prologues/epilogues by calling our own save/restore-the-world
17532    routines.  */
17533 
17534 static void
compute_save_world_info(rs6000_stack_t * info_ptr)17535 compute_save_world_info (rs6000_stack_t *info_ptr)
17536 {
17537   info_ptr->world_save_p = 1;
17538   info_ptr->world_save_p
17539     = (WORLD_SAVE_P (info_ptr)
17540        && DEFAULT_ABI == ABI_DARWIN
17541        && !cfun->has_nonlocal_label
17542        && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
17543        && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
17544        && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
17545        && info_ptr->cr_save_p);
17546 
17547   /* This will not work in conjunction with sibcalls.  Make sure there
17548      are none.  (This check is expensive, but seldom executed.) */
17549   if (WORLD_SAVE_P (info_ptr))
17550     {
17551       rtx insn;
17552       for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
17553 	if ( GET_CODE (insn) == CALL_INSN
17554 	     && SIBLING_CALL_P (insn))
17555 	  {
17556 	    info_ptr->world_save_p = 0;
17557 	    break;
17558 	  }
17559     }
17560 
17561   if (WORLD_SAVE_P (info_ptr))
17562     {
17563       /* Even if we're not touching VRsave, make sure there's room on the
17564 	 stack for it, if it looks like we're calling SAVE_WORLD, which
17565 	 will attempt to save it. */
17566       info_ptr->vrsave_size  = 4;
17567 
17568       /* If we are going to save the world, we need to save the link register too.  */
17569       info_ptr->lr_save_p = 1;
17570 
17571       /* "Save" the VRsave register too if we're saving the world.  */
17572       if (info_ptr->vrsave_mask == 0)
17573 	info_ptr->vrsave_mask = compute_vrsave_mask ();
17574 
17575       /* Because the Darwin register save/restore routines only handle
17576 	 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
17577 	 check.  */
17578       gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
17579 		  && (info_ptr->first_altivec_reg_save
17580 		      >= FIRST_SAVED_ALTIVEC_REGNO));
17581     }
17582   return;
17583 }
17584 
17585 
17586 static void
is_altivec_return_reg(rtx reg,void * xyes)17587 is_altivec_return_reg (rtx reg, void *xyes)
17588 {
17589   bool *yes = (bool *) xyes;
17590   if (REGNO (reg) == ALTIVEC_ARG_RETURN)
17591     *yes = true;
17592 }
17593 
17594 
17595 /* Look for user-defined global regs in the range FIRST to LAST-1.
17596    We should not restore these, and so cannot use lmw or out-of-line
17597    restore functions if there are any.  We also can't save them
17598    (well, emit frame notes for them), because frame unwinding during
17599    exception handling will restore saved registers.  */
17600 
17601 static bool
global_regs_p(unsigned first,unsigned last)17602 global_regs_p (unsigned first, unsigned last)
17603 {
17604   while (first < last)
17605     if (global_regs[first++])
17606       return true;
17607   return false;
17608 }
17609 
17610 /* Determine the strategy for savings/restoring registers.  */
17611 
17612 enum {
17613   SAVRES_MULTIPLE = 0x1,
17614   SAVE_INLINE_FPRS = 0x2,
17615   SAVE_INLINE_GPRS = 0x4,
17616   REST_INLINE_FPRS = 0x8,
17617   REST_INLINE_GPRS = 0x10,
17618   SAVE_NOINLINE_GPRS_SAVES_LR = 0x20,
17619   SAVE_NOINLINE_FPRS_SAVES_LR = 0x40,
17620   REST_NOINLINE_FPRS_DOESNT_RESTORE_LR = 0x80,
17621   SAVE_INLINE_VRS = 0x100,
17622   REST_INLINE_VRS = 0x200
17623 };
17624 
17625 static int
rs6000_savres_strategy(rs6000_stack_t * info,bool using_static_chain_p)17626 rs6000_savres_strategy (rs6000_stack_t *info,
17627 			bool using_static_chain_p)
17628 {
17629   int strategy = 0;
17630   bool lr_save_p;
17631 
17632   if (TARGET_MULTIPLE
17633       && !TARGET_POWERPC64
17634       && !(TARGET_SPE_ABI && info->spe_64bit_regs_used)
17635       && info->first_gp_reg_save < 31
17636       && !global_regs_p (info->first_gp_reg_save, 32))
17637     strategy |= SAVRES_MULTIPLE;
17638 
17639   if (crtl->calls_eh_return
17640       || cfun->machine->ra_need_lr)
17641     strategy |= (SAVE_INLINE_FPRS | REST_INLINE_FPRS
17642 		 | SAVE_INLINE_GPRS | REST_INLINE_GPRS
17643 		 | SAVE_INLINE_VRS | REST_INLINE_VRS);
17644 
17645   if (info->first_fp_reg_save == 64
17646       /* The out-of-line FP routines use double-precision stores;
17647 	 we can't use those routines if we don't have such stores.  */
17648       || (TARGET_HARD_FLOAT && !TARGET_DOUBLE_FLOAT)
17649       || global_regs_p (info->first_fp_reg_save, 64))
17650     strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
17651 
17652   if (info->first_gp_reg_save == 32
17653       || (!(strategy & SAVRES_MULTIPLE)
17654 	  && global_regs_p (info->first_gp_reg_save, 32)))
17655     strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
17656 
17657   if (info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
17658       || global_regs_p (info->first_altivec_reg_save, LAST_ALTIVEC_REGNO + 1))
17659     strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
17660 
17661   /* Define cutoff for using out-of-line functions to save registers.  */
17662   if (DEFAULT_ABI == ABI_V4 || TARGET_ELF)
17663     {
17664       if (!optimize_size)
17665 	{
17666 	  strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
17667 	  strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
17668 	  strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
17669 	}
17670       else
17671 	{
17672 	  /* Prefer out-of-line restore if it will exit.  */
17673 	  if (info->first_fp_reg_save > 61)
17674 	    strategy |= SAVE_INLINE_FPRS;
17675 	  if (info->first_gp_reg_save > 29)
17676 	    {
17677 	      if (info->first_fp_reg_save == 64)
17678 		strategy |= SAVE_INLINE_GPRS;
17679 	      else
17680 		strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
17681 	    }
17682 	  if (info->first_altivec_reg_save == LAST_ALTIVEC_REGNO)
17683 	    strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
17684 	}
17685     }
17686   else if (DEFAULT_ABI == ABI_DARWIN)
17687     {
17688       if (info->first_fp_reg_save > 60)
17689 	strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
17690       if (info->first_gp_reg_save > 29)
17691 	strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
17692       strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
17693     }
17694   else
17695     {
17696       gcc_checking_assert (DEFAULT_ABI == ABI_AIX);
17697       if (info->first_fp_reg_save > 61)
17698 	strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
17699       strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
17700       strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
17701     }
17702 
17703   /* Don't bother to try to save things out-of-line if r11 is occupied
17704      by the static chain.  It would require too much fiddling and the
17705      static chain is rarely used anyway.  FPRs are saved w.r.t the stack
17706      pointer on Darwin, and AIX uses r1 or r12.  */
17707   if (using_static_chain_p && DEFAULT_ABI != ABI_AIX)
17708     strategy |= ((DEFAULT_ABI == ABI_DARWIN ? 0 : SAVE_INLINE_FPRS)
17709 		 | SAVE_INLINE_GPRS
17710 		 | SAVE_INLINE_VRS | REST_INLINE_VRS);
17711 
17712   /* We can only use the out-of-line routines to restore if we've
17713      saved all the registers from first_fp_reg_save in the prologue.
17714      Otherwise, we risk loading garbage.  */
17715   if ((strategy & (SAVE_INLINE_FPRS | REST_INLINE_FPRS)) == SAVE_INLINE_FPRS)
17716     {
17717       int i;
17718 
17719       for (i = info->first_fp_reg_save; i < 64; i++)
17720 	if (!save_reg_p (i))
17721 	  {
17722 	    strategy |= REST_INLINE_FPRS;
17723 	    break;
17724 	  }
17725     }
17726 
17727   /* If we are going to use store multiple, then don't even bother
17728      with the out-of-line routines, since the store-multiple
17729      instruction will always be smaller.  */
17730   if ((strategy & SAVRES_MULTIPLE))
17731     strategy |= SAVE_INLINE_GPRS;
17732 
17733   /* info->lr_save_p isn't yet set if the only reason lr needs to be
17734      saved is an out-of-line save or restore.  Set up the value for
17735      the next test (excluding out-of-line gpr restore).  */
17736   lr_save_p = (info->lr_save_p
17737 	       || !(strategy & SAVE_INLINE_GPRS)
17738 	       || !(strategy & SAVE_INLINE_FPRS)
17739 	       || !(strategy & SAVE_INLINE_VRS)
17740 	       || !(strategy & REST_INLINE_FPRS)
17741 	       || !(strategy & REST_INLINE_VRS));
17742 
17743   /* The situation is more complicated with load multiple.  We'd
17744      prefer to use the out-of-line routines for restores, since the
17745      "exit" out-of-line routines can handle the restore of LR and the
17746      frame teardown.  However if doesn't make sense to use the
17747      out-of-line routine if that is the only reason we'd need to save
17748      LR, and we can't use the "exit" out-of-line gpr restore if we
17749      have saved some fprs; In those cases it is advantageous to use
17750      load multiple when available.  */
17751   if ((strategy & SAVRES_MULTIPLE)
17752       && (!lr_save_p
17753 	  || info->first_fp_reg_save != 64))
17754     strategy |= REST_INLINE_GPRS;
17755 
17756   /* Saving CR interferes with the exit routines used on the SPE, so
17757      just punt here.  */
17758   if (TARGET_SPE_ABI
17759       && info->spe_64bit_regs_used
17760       && info->cr_save_p)
17761     strategy |= REST_INLINE_GPRS;
17762 
17763   /* We can only use load multiple or the out-of-line routines to
17764      restore if we've used store multiple or out-of-line routines
17765      in the prologue, i.e. if we've saved all the registers from
17766      first_gp_reg_save.  Otherwise, we risk loading garbage.  */
17767   if ((strategy & (SAVE_INLINE_GPRS | REST_INLINE_GPRS | SAVRES_MULTIPLE))
17768       == SAVE_INLINE_GPRS)
17769     {
17770       int i;
17771 
17772       for (i = info->first_gp_reg_save; i < 32; i++)
17773 	if (!save_reg_p (i))
17774 	  {
17775 	    strategy |= REST_INLINE_GPRS;
17776 	    break;
17777 	  }
17778     }
17779 
17780   if (TARGET_ELF && TARGET_64BIT)
17781     {
17782       if (!(strategy & SAVE_INLINE_FPRS))
17783 	strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
17784       else if (!(strategy & SAVE_INLINE_GPRS)
17785 	       && info->first_fp_reg_save == 64)
17786 	strategy |= SAVE_NOINLINE_GPRS_SAVES_LR;
17787     }
17788   else if (TARGET_AIX && !(strategy & REST_INLINE_FPRS))
17789     strategy |= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR;
17790 
17791   if (TARGET_MACHO && !(strategy & SAVE_INLINE_FPRS))
17792     strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
17793 
17794   return strategy;
17795 }
17796 
17797 /* Calculate the stack information for the current function.  This is
17798    complicated by having two separate calling sequences, the AIX calling
17799    sequence and the V.4 calling sequence.
17800 
17801    AIX (and Darwin/Mac OS X) stack frames look like:
17802 							  32-bit  64-bit
17803 	SP---->	+---------------------------------------+
17804 		| back chain to caller			| 0	  0
17805 		+---------------------------------------+
17806 		| saved CR				| 4       8 (8-11)
17807 		+---------------------------------------+
17808 		| saved LR				| 8       16
17809 		+---------------------------------------+
17810 		| reserved for compilers		| 12      24
17811 		+---------------------------------------+
17812 		| reserved for binders			| 16      32
17813 		+---------------------------------------+
17814 		| saved TOC pointer			| 20      40
17815 		+---------------------------------------+
17816 		| Parameter save area (P)		| 24      48
17817 		+---------------------------------------+
17818 		| Alloca space (A)			| 24+P    etc.
17819 		+---------------------------------------+
17820 		| Local variable space (L)		| 24+P+A
17821 		+---------------------------------------+
17822 		| Float/int conversion temporary (X)	| 24+P+A+L
17823 		+---------------------------------------+
17824 		| Save area for AltiVec registers (W)	| 24+P+A+L+X
17825 		+---------------------------------------+
17826 		| AltiVec alignment padding (Y)		| 24+P+A+L+X+W
17827 		+---------------------------------------+
17828 		| Save area for VRSAVE register (Z)	| 24+P+A+L+X+W+Y
17829 		+---------------------------------------+
17830 		| Save area for GP registers (G)	| 24+P+A+X+L+X+W+Y+Z
17831 		+---------------------------------------+
17832 		| Save area for FP registers (F)	| 24+P+A+X+L+X+W+Y+Z+G
17833 		+---------------------------------------+
17834 	old SP->| back chain to caller's caller		|
17835 		+---------------------------------------+
17836 
17837    The required alignment for AIX configurations is two words (i.e., 8
17838    or 16 bytes).
17839 
17840 
17841    V.4 stack frames look like:
17842 
17843 	SP---->	+---------------------------------------+
17844 		| back chain to caller			| 0
17845 		+---------------------------------------+
17846 		| caller's saved LR			| 4
17847 		+---------------------------------------+
17848 		| Parameter save area (P)		| 8
17849 		+---------------------------------------+
17850 		| Alloca space (A)			| 8+P
17851 		+---------------------------------------+
17852 		| Varargs save area (V)			| 8+P+A
17853 		+---------------------------------------+
17854 		| Local variable space (L)		| 8+P+A+V
17855 		+---------------------------------------+
17856 		| Float/int conversion temporary (X)	| 8+P+A+V+L
17857 		+---------------------------------------+
17858 		| Save area for AltiVec registers (W)	| 8+P+A+V+L+X
17859 		+---------------------------------------+
17860 		| AltiVec alignment padding (Y)		| 8+P+A+V+L+X+W
17861 		+---------------------------------------+
17862 		| Save area for VRSAVE register (Z)	| 8+P+A+V+L+X+W+Y
17863 		+---------------------------------------+
17864 		| SPE: area for 64-bit GP registers	|
17865 		+---------------------------------------+
17866 		| SPE alignment padding			|
17867 		+---------------------------------------+
17868 		| saved CR (C)				| 8+P+A+V+L+X+W+Y+Z
17869 		+---------------------------------------+
17870 		| Save area for GP registers (G)	| 8+P+A+V+L+X+W+Y+Z+C
17871 		+---------------------------------------+
17872 		| Save area for FP registers (F)	| 8+P+A+V+L+X+W+Y+Z+C+G
17873 		+---------------------------------------+
17874 	old SP->| back chain to caller's caller		|
17875 		+---------------------------------------+
17876 
17877    The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
17878    given.  (But note below and in sysv4.h that we require only 8 and
17879    may round up the size of our stack frame anyways.  The historical
17880    reason is early versions of powerpc-linux which didn't properly
17881    align the stack at program startup.  A happy side-effect is that
17882    -mno-eabi libraries can be used with -meabi programs.)
17883 
17884    The EABI configuration defaults to the V.4 layout.  However,
17885    the stack alignment requirements may differ.  If -mno-eabi is not
17886    given, the required stack alignment is 8 bytes; if -mno-eabi is
17887    given, the required alignment is 16 bytes.  (But see V.4 comment
17888    above.)  */
17889 
17890 #ifndef ABI_STACK_BOUNDARY
17891 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
17892 #endif
17893 
17894 static rs6000_stack_t *
rs6000_stack_info(void)17895 rs6000_stack_info (void)
17896 {
17897   rs6000_stack_t *info_ptr = &stack_info;
17898   int reg_size = TARGET_32BIT ? 4 : 8;
17899   int ehrd_size;
17900   int save_align;
17901   int first_gp;
17902   HOST_WIDE_INT non_fixed_size;
17903   bool using_static_chain_p;
17904 
17905   if (reload_completed && info_ptr->reload_completed)
17906     return info_ptr;
17907 
17908   memset (info_ptr, 0, sizeof (*info_ptr));
17909   info_ptr->reload_completed = reload_completed;
17910 
17911   if (TARGET_SPE)
17912     {
17913       /* Cache value so we don't rescan instruction chain over and over.  */
17914       if (cfun->machine->insn_chain_scanned_p == 0)
17915 	cfun->machine->insn_chain_scanned_p
17916 	  = spe_func_has_64bit_regs_p () + 1;
17917       info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
17918     }
17919 
17920   /* Select which calling sequence.  */
17921   info_ptr->abi = DEFAULT_ABI;
17922 
17923   /* Calculate which registers need to be saved & save area size.  */
17924   info_ptr->first_gp_reg_save = first_reg_to_save ();
17925   /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
17926      even if it currently looks like we won't.  Reload may need it to
17927      get at a constant; if so, it will have already created a constant
17928      pool entry for it.  */
17929   if (((TARGET_TOC && TARGET_MINIMAL_TOC)
17930        || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
17931        || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
17932       && crtl->uses_const_pool
17933       && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
17934     first_gp = RS6000_PIC_OFFSET_TABLE_REGNUM;
17935   else
17936     first_gp = info_ptr->first_gp_reg_save;
17937 
17938   info_ptr->gp_size = reg_size * (32 - first_gp);
17939 
17940   /* For the SPE, we have an additional upper 32-bits on each GPR.
17941      Ideally we should save the entire 64-bits only when the upper
17942      half is used in SIMD instructions.  Since we only record
17943      registers live (not the size they are used in), this proves
17944      difficult because we'd have to traverse the instruction chain at
17945      the right time, taking reload into account.  This is a real pain,
17946      so we opt to save the GPRs in 64-bits always if but one register
17947      gets used in 64-bits.  Otherwise, all the registers in the frame
17948      get saved in 32-bits.
17949 
17950      So... since when we save all GPRs (except the SP) in 64-bits, the
17951      traditional GP save area will be empty.  */
17952   if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
17953     info_ptr->gp_size = 0;
17954 
17955   info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
17956   info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
17957 
17958   info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
17959   info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
17960 				 - info_ptr->first_altivec_reg_save);
17961 
17962   /* Does this function call anything?  */
17963   info_ptr->calls_p = (! crtl->is_leaf
17964 		       || cfun->machine->ra_needs_full_frame);
17965 
17966   /* Determine if we need to save the condition code registers.  */
17967   if (df_regs_ever_live_p (CR2_REGNO)
17968       || df_regs_ever_live_p (CR3_REGNO)
17969       || df_regs_ever_live_p (CR4_REGNO))
17970     {
17971       info_ptr->cr_save_p = 1;
17972       if (DEFAULT_ABI == ABI_V4)
17973 	info_ptr->cr_size = reg_size;
17974     }
17975 
17976   /* If the current function calls __builtin_eh_return, then we need
17977      to allocate stack space for registers that will hold data for
17978      the exception handler.  */
17979   if (crtl->calls_eh_return)
17980     {
17981       unsigned int i;
17982       for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
17983 	continue;
17984 
17985       /* SPE saves EH registers in 64-bits.  */
17986       ehrd_size = i * (TARGET_SPE_ABI
17987 		       && info_ptr->spe_64bit_regs_used != 0
17988 		       ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
17989     }
17990   else
17991     ehrd_size = 0;
17992 
17993   /* Determine various sizes.  */
17994   info_ptr->reg_size     = reg_size;
17995   info_ptr->fixed_size   = RS6000_SAVE_AREA;
17996   info_ptr->vars_size    = RS6000_ALIGN (get_frame_size (), 8);
17997   info_ptr->parm_size    = RS6000_ALIGN (crtl->outgoing_args_size,
17998 					 TARGET_ALTIVEC ? 16 : 8);
17999   if (FRAME_GROWS_DOWNWARD)
18000     info_ptr->vars_size
18001       += RS6000_ALIGN (info_ptr->fixed_size + info_ptr->vars_size
18002 		       + info_ptr->parm_size,
18003 		       ABI_STACK_BOUNDARY / BITS_PER_UNIT)
18004 	 - (info_ptr->fixed_size + info_ptr->vars_size
18005 	    + info_ptr->parm_size);
18006 
18007   if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
18008     info_ptr->spe_gp_size = 8 * (32 - first_gp);
18009   else
18010     info_ptr->spe_gp_size = 0;
18011 
18012   if (TARGET_ALTIVEC_ABI)
18013     info_ptr->vrsave_mask = compute_vrsave_mask ();
18014   else
18015     info_ptr->vrsave_mask = 0;
18016 
18017   if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
18018     info_ptr->vrsave_size  = 4;
18019   else
18020     info_ptr->vrsave_size  = 0;
18021 
18022   compute_save_world_info (info_ptr);
18023 
18024   /* Calculate the offsets.  */
18025   switch (DEFAULT_ABI)
18026     {
18027     case ABI_NONE:
18028     default:
18029       gcc_unreachable ();
18030 
18031     case ABI_AIX:
18032     case ABI_DARWIN:
18033       info_ptr->fp_save_offset   = - info_ptr->fp_size;
18034       info_ptr->gp_save_offset   = info_ptr->fp_save_offset - info_ptr->gp_size;
18035 
18036       if (TARGET_ALTIVEC_ABI)
18037 	{
18038 	  info_ptr->vrsave_save_offset
18039 	    = info_ptr->gp_save_offset - info_ptr->vrsave_size;
18040 
18041 	  /* Align stack so vector save area is on a quadword boundary.
18042 	     The padding goes above the vectors.  */
18043 	  if (info_ptr->altivec_size != 0)
18044 	    info_ptr->altivec_padding_size
18045 	      = info_ptr->vrsave_save_offset & 0xF;
18046 	  else
18047 	    info_ptr->altivec_padding_size = 0;
18048 
18049 	  info_ptr->altivec_save_offset
18050 	    = info_ptr->vrsave_save_offset
18051 	    - info_ptr->altivec_padding_size
18052 	    - info_ptr->altivec_size;
18053 	  gcc_assert (info_ptr->altivec_size == 0
18054 		      || info_ptr->altivec_save_offset % 16 == 0);
18055 
18056 	  /* Adjust for AltiVec case.  */
18057 	  info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
18058 	}
18059       else
18060 	info_ptr->ehrd_offset      = info_ptr->gp_save_offset - ehrd_size;
18061       info_ptr->cr_save_offset   = reg_size; /* first word when 64-bit.  */
18062       info_ptr->lr_save_offset   = 2*reg_size;
18063       break;
18064 
18065     case ABI_V4:
18066       info_ptr->fp_save_offset   = - info_ptr->fp_size;
18067       info_ptr->gp_save_offset   = info_ptr->fp_save_offset - info_ptr->gp_size;
18068       info_ptr->cr_save_offset   = info_ptr->gp_save_offset - info_ptr->cr_size;
18069 
18070       if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
18071 	{
18072 	  /* Align stack so SPE GPR save area is aligned on a
18073 	     double-word boundary.  */
18074 	  if (info_ptr->spe_gp_size != 0 && info_ptr->cr_save_offset != 0)
18075 	    info_ptr->spe_padding_size
18076 	      = 8 - (-info_ptr->cr_save_offset % 8);
18077 	  else
18078 	    info_ptr->spe_padding_size = 0;
18079 
18080 	  info_ptr->spe_gp_save_offset
18081 	    = info_ptr->cr_save_offset
18082 	    - info_ptr->spe_padding_size
18083 	    - info_ptr->spe_gp_size;
18084 
18085 	  /* Adjust for SPE case.  */
18086 	  info_ptr->ehrd_offset = info_ptr->spe_gp_save_offset;
18087 	}
18088       else if (TARGET_ALTIVEC_ABI)
18089 	{
18090 	  info_ptr->vrsave_save_offset
18091 	    = info_ptr->cr_save_offset - info_ptr->vrsave_size;
18092 
18093 	  /* Align stack so vector save area is on a quadword boundary.  */
18094 	  if (info_ptr->altivec_size != 0)
18095 	    info_ptr->altivec_padding_size
18096 	      = 16 - (-info_ptr->vrsave_save_offset % 16);
18097 	  else
18098 	    info_ptr->altivec_padding_size = 0;
18099 
18100 	  info_ptr->altivec_save_offset
18101 	    = info_ptr->vrsave_save_offset
18102 	    - info_ptr->altivec_padding_size
18103 	    - info_ptr->altivec_size;
18104 
18105 	  /* Adjust for AltiVec case.  */
18106 	  info_ptr->ehrd_offset = info_ptr->altivec_save_offset;
18107 	}
18108       else
18109 	info_ptr->ehrd_offset    = info_ptr->cr_save_offset;
18110       info_ptr->ehrd_offset      -= ehrd_size;
18111       info_ptr->lr_save_offset   = reg_size;
18112       break;
18113     }
18114 
18115   save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
18116   info_ptr->save_size    = RS6000_ALIGN (info_ptr->fp_size
18117 					 + info_ptr->gp_size
18118 					 + info_ptr->altivec_size
18119 					 + info_ptr->altivec_padding_size
18120 					 + info_ptr->spe_gp_size
18121 					 + info_ptr->spe_padding_size
18122 					 + ehrd_size
18123 					 + info_ptr->cr_size
18124 					 + info_ptr->vrsave_size,
18125 					 save_align);
18126 
18127   non_fixed_size	 = (info_ptr->vars_size
18128 			    + info_ptr->parm_size
18129 			    + info_ptr->save_size);
18130 
18131   info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
18132 				       ABI_STACK_BOUNDARY / BITS_PER_UNIT);
18133 
18134   /* Determine if we need to save the link register.  */
18135   if (info_ptr->calls_p
18136       || (DEFAULT_ABI == ABI_AIX
18137 	  && crtl->profile
18138 	  && !TARGET_PROFILE_KERNEL)
18139       || (DEFAULT_ABI == ABI_V4 && cfun->calls_alloca)
18140 #ifdef TARGET_RELOCATABLE
18141       || (TARGET_RELOCATABLE && (get_pool_size () != 0))
18142 #endif
18143       || rs6000_ra_ever_killed ())
18144     info_ptr->lr_save_p = 1;
18145 
18146   using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
18147 			  && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
18148 			  && call_used_regs[STATIC_CHAIN_REGNUM]);
18149   info_ptr->savres_strategy = rs6000_savres_strategy (info_ptr,
18150 						      using_static_chain_p);
18151 
18152   if (!(info_ptr->savres_strategy & SAVE_INLINE_GPRS)
18153       || !(info_ptr->savres_strategy & SAVE_INLINE_FPRS)
18154       || !(info_ptr->savres_strategy & SAVE_INLINE_VRS)
18155       || !(info_ptr->savres_strategy & REST_INLINE_GPRS)
18156       || !(info_ptr->savres_strategy & REST_INLINE_FPRS)
18157       || !(info_ptr->savres_strategy & REST_INLINE_VRS))
18158     info_ptr->lr_save_p = 1;
18159 
18160   if (info_ptr->lr_save_p)
18161     df_set_regs_ever_live (LR_REGNO, true);
18162 
18163   /* Determine if we need to allocate any stack frame:
18164 
18165      For AIX we need to push the stack if a frame pointer is needed
18166      (because the stack might be dynamically adjusted), if we are
18167      debugging, if we make calls, or if the sum of fp_save, gp_save,
18168      and local variables are more than the space needed to save all
18169      non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
18170      + 18*8 = 288 (GPR13 reserved).
18171 
18172      For V.4 we don't have the stack cushion that AIX uses, but assume
18173      that the debugger can handle stackless frames.  */
18174 
18175   if (info_ptr->calls_p)
18176     info_ptr->push_p = 1;
18177 
18178   else if (DEFAULT_ABI == ABI_V4)
18179     info_ptr->push_p = non_fixed_size != 0;
18180 
18181   else if (frame_pointer_needed)
18182     info_ptr->push_p = 1;
18183 
18184   else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
18185     info_ptr->push_p = 1;
18186 
18187   else
18188     info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
18189 
18190   /* Zero offsets if we're not saving those registers.  */
18191   if (info_ptr->fp_size == 0)
18192     info_ptr->fp_save_offset = 0;
18193 
18194   if (info_ptr->gp_size == 0)
18195     info_ptr->gp_save_offset = 0;
18196 
18197   if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
18198     info_ptr->altivec_save_offset = 0;
18199 
18200   /* Zero VRSAVE offset if not saved and restored.  */
18201   if (! TARGET_ALTIVEC_VRSAVE || info_ptr->vrsave_mask == 0)
18202     info_ptr->vrsave_save_offset = 0;
18203 
18204   if (! TARGET_SPE_ABI
18205       || info_ptr->spe_64bit_regs_used == 0
18206       || info_ptr->spe_gp_size == 0)
18207     info_ptr->spe_gp_save_offset = 0;
18208 
18209   if (! info_ptr->lr_save_p)
18210     info_ptr->lr_save_offset = 0;
18211 
18212   if (! info_ptr->cr_save_p)
18213     info_ptr->cr_save_offset = 0;
18214 
18215   return info_ptr;
18216 }
18217 
18218 /* Return true if the current function uses any GPRs in 64-bit SIMD
18219    mode.  */
18220 
18221 static bool
spe_func_has_64bit_regs_p(void)18222 spe_func_has_64bit_regs_p (void)
18223 {
18224   rtx insns, insn;
18225 
18226   /* Functions that save and restore all the call-saved registers will
18227      need to save/restore the registers in 64-bits.  */
18228   if (crtl->calls_eh_return
18229       || cfun->calls_setjmp
18230       || crtl->has_nonlocal_goto)
18231     return true;
18232 
18233   insns = get_insns ();
18234 
18235   for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
18236     {
18237       if (INSN_P (insn))
18238 	{
18239 	  rtx i;
18240 
18241 	  /* FIXME: This should be implemented with attributes...
18242 
18243 	         (set_attr "spe64" "true")....then,
18244 	         if (get_spe64(insn)) return true;
18245 
18246 	     It's the only reliable way to do the stuff below.  */
18247 
18248 	  i = PATTERN (insn);
18249 	  if (GET_CODE (i) == SET)
18250 	    {
18251 	      enum machine_mode mode = GET_MODE (SET_SRC (i));
18252 
18253 	      if (SPE_VECTOR_MODE (mode))
18254 		return true;
18255 	      if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode))
18256 		return true;
18257 	    }
18258 	}
18259     }
18260 
18261   return false;
18262 }
18263 
18264 static void
debug_stack_info(rs6000_stack_t * info)18265 debug_stack_info (rs6000_stack_t *info)
18266 {
18267   const char *abi_string;
18268 
18269   if (! info)
18270     info = rs6000_stack_info ();
18271 
18272   fprintf (stderr, "\nStack information for function %s:\n",
18273 	   ((current_function_decl && DECL_NAME (current_function_decl))
18274 	    ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
18275 	    : "<unknown>"));
18276 
18277   switch (info->abi)
18278     {
18279     default:		 abi_string = "Unknown";	break;
18280     case ABI_NONE:	 abi_string = "NONE";		break;
18281     case ABI_AIX:	 abi_string = "AIX";		break;
18282     case ABI_DARWIN:	 abi_string = "Darwin";		break;
18283     case ABI_V4:	 abi_string = "V.4";		break;
18284     }
18285 
18286   fprintf (stderr, "\tABI                 = %5s\n", abi_string);
18287 
18288   if (TARGET_ALTIVEC_ABI)
18289     fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
18290 
18291   if (TARGET_SPE_ABI)
18292     fprintf (stderr, "\tSPE ABI extensions enabled.\n");
18293 
18294   if (info->first_gp_reg_save != 32)
18295     fprintf (stderr, "\tfirst_gp_reg_save   = %5d\n", info->first_gp_reg_save);
18296 
18297   if (info->first_fp_reg_save != 64)
18298     fprintf (stderr, "\tfirst_fp_reg_save   = %5d\n", info->first_fp_reg_save);
18299 
18300   if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
18301     fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
18302 	     info->first_altivec_reg_save);
18303 
18304   if (info->lr_save_p)
18305     fprintf (stderr, "\tlr_save_p           = %5d\n", info->lr_save_p);
18306 
18307   if (info->cr_save_p)
18308     fprintf (stderr, "\tcr_save_p           = %5d\n", info->cr_save_p);
18309 
18310   if (info->vrsave_mask)
18311     fprintf (stderr, "\tvrsave_mask         = 0x%x\n", info->vrsave_mask);
18312 
18313   if (info->push_p)
18314     fprintf (stderr, "\tpush_p              = %5d\n", info->push_p);
18315 
18316   if (info->calls_p)
18317     fprintf (stderr, "\tcalls_p             = %5d\n", info->calls_p);
18318 
18319   if (info->gp_save_offset)
18320     fprintf (stderr, "\tgp_save_offset      = %5d\n", info->gp_save_offset);
18321 
18322   if (info->fp_save_offset)
18323     fprintf (stderr, "\tfp_save_offset      = %5d\n", info->fp_save_offset);
18324 
18325   if (info->altivec_save_offset)
18326     fprintf (stderr, "\taltivec_save_offset = %5d\n",
18327 	     info->altivec_save_offset);
18328 
18329   if (info->spe_gp_save_offset)
18330     fprintf (stderr, "\tspe_gp_save_offset  = %5d\n",
18331 	     info->spe_gp_save_offset);
18332 
18333   if (info->vrsave_save_offset)
18334     fprintf (stderr, "\tvrsave_save_offset  = %5d\n",
18335 	     info->vrsave_save_offset);
18336 
18337   if (info->lr_save_offset)
18338     fprintf (stderr, "\tlr_save_offset      = %5d\n", info->lr_save_offset);
18339 
18340   if (info->cr_save_offset)
18341     fprintf (stderr, "\tcr_save_offset      = %5d\n", info->cr_save_offset);
18342 
18343   if (info->varargs_save_offset)
18344     fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
18345 
18346   if (info->total_size)
18347     fprintf (stderr, "\ttotal_size          = " HOST_WIDE_INT_PRINT_DEC "\n",
18348 	     info->total_size);
18349 
18350   if (info->vars_size)
18351     fprintf (stderr, "\tvars_size           = " HOST_WIDE_INT_PRINT_DEC "\n",
18352 	     info->vars_size);
18353 
18354   if (info->parm_size)
18355     fprintf (stderr, "\tparm_size           = %5d\n", info->parm_size);
18356 
18357   if (info->fixed_size)
18358     fprintf (stderr, "\tfixed_size          = %5d\n", info->fixed_size);
18359 
18360   if (info->gp_size)
18361     fprintf (stderr, "\tgp_size             = %5d\n", info->gp_size);
18362 
18363   if (info->spe_gp_size)
18364     fprintf (stderr, "\tspe_gp_size         = %5d\n", info->spe_gp_size);
18365 
18366   if (info->fp_size)
18367     fprintf (stderr, "\tfp_size             = %5d\n", info->fp_size);
18368 
18369   if (info->altivec_size)
18370     fprintf (stderr, "\taltivec_size        = %5d\n", info->altivec_size);
18371 
18372   if (info->vrsave_size)
18373     fprintf (stderr, "\tvrsave_size         = %5d\n", info->vrsave_size);
18374 
18375   if (info->altivec_padding_size)
18376     fprintf (stderr, "\taltivec_padding_size= %5d\n",
18377 	     info->altivec_padding_size);
18378 
18379   if (info->spe_padding_size)
18380     fprintf (stderr, "\tspe_padding_size    = %5d\n",
18381 	     info->spe_padding_size);
18382 
18383   if (info->cr_size)
18384     fprintf (stderr, "\tcr_size             = %5d\n", info->cr_size);
18385 
18386   if (info->save_size)
18387     fprintf (stderr, "\tsave_size           = %5d\n", info->save_size);
18388 
18389   if (info->reg_size != 4)
18390     fprintf (stderr, "\treg_size            = %5d\n", info->reg_size);
18391 
18392     fprintf (stderr, "\tsave-strategy       =  %04x\n", info->savres_strategy);
18393 
18394   fprintf (stderr, "\n");
18395 }
18396 
18397 rtx
rs6000_return_addr(int count,rtx frame)18398 rs6000_return_addr (int count, rtx frame)
18399 {
18400   /* Currently we don't optimize very well between prolog and body
18401      code and for PIC code the code can be actually quite bad, so
18402      don't try to be too clever here.  */
18403   if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
18404     {
18405       cfun->machine->ra_needs_full_frame = 1;
18406 
18407       return
18408 	gen_rtx_MEM
18409 	  (Pmode,
18410 	   memory_address
18411 	   (Pmode,
18412 	    plus_constant (Pmode,
18413 			   copy_to_reg
18414 			   (gen_rtx_MEM (Pmode,
18415 					 memory_address (Pmode, frame))),
18416 			   RETURN_ADDRESS_OFFSET)));
18417     }
18418 
18419   cfun->machine->ra_need_lr = 1;
18420   return get_hard_reg_initial_val (Pmode, LR_REGNO);
18421 }
18422 
18423 /* Say whether a function is a candidate for sibcall handling or not.  */
18424 
18425 static bool
rs6000_function_ok_for_sibcall(tree decl,tree exp)18426 rs6000_function_ok_for_sibcall (tree decl, tree exp)
18427 {
18428   tree fntype;
18429 
18430   if (decl)
18431     fntype = TREE_TYPE (decl);
18432   else
18433     fntype = TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp)));
18434 
18435   /* We can't do it if the called function has more vector parameters
18436      than the current function; there's nowhere to put the VRsave code.  */
18437   if (TARGET_ALTIVEC_ABI
18438       && TARGET_ALTIVEC_VRSAVE
18439       && !(decl && decl == current_function_decl))
18440     {
18441       function_args_iterator args_iter;
18442       tree type;
18443       int nvreg = 0;
18444 
18445       /* Functions with vector parameters are required to have a
18446 	 prototype, so the argument type info must be available
18447 	 here.  */
18448       FOREACH_FUNCTION_ARGS(fntype, type, args_iter)
18449 	if (TREE_CODE (type) == VECTOR_TYPE
18450 	    && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
18451 	  nvreg++;
18452 
18453       FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl), type, args_iter)
18454 	if (TREE_CODE (type) == VECTOR_TYPE
18455 	    && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
18456 	  nvreg--;
18457 
18458       if (nvreg > 0)
18459 	return false;
18460     }
18461 
18462   /* Under the AIX ABI we can't allow calls to non-local functions,
18463      because the callee may have a different TOC pointer to the
18464      caller and there's no way to ensure we restore the TOC when we
18465      return.  With the secure-plt SYSV ABI we can't make non-local
18466      calls when -fpic/PIC because the plt call stubs use r30.  */
18467   if (DEFAULT_ABI == ABI_DARWIN
18468       || (DEFAULT_ABI == ABI_AIX
18469 	  && decl
18470 	  && !DECL_EXTERNAL (decl)
18471 	  && (*targetm.binds_local_p) (decl))
18472       || (DEFAULT_ABI == ABI_V4
18473 	  && (!TARGET_SECURE_PLT
18474 	      || !flag_pic
18475 	      || (decl
18476 		  && (*targetm.binds_local_p) (decl)))))
18477     {
18478       tree attr_list = TYPE_ATTRIBUTES (fntype);
18479 
18480       if (!lookup_attribute ("longcall", attr_list)
18481 	  || lookup_attribute ("shortcall", attr_list))
18482 	return true;
18483     }
18484 
18485   return false;
18486 }
18487 
18488 /* NULL if INSN insn is valid within a low-overhead loop.
18489    Otherwise return why doloop cannot be applied.
18490    PowerPC uses the COUNT register for branch on table instructions.  */
18491 
18492 static const char *
rs6000_invalid_within_doloop(const_rtx insn)18493 rs6000_invalid_within_doloop (const_rtx insn)
18494 {
18495   if (CALL_P (insn))
18496     return "Function call in the loop.";
18497 
18498   if (JUMP_P (insn)
18499       && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
18500 	  || GET_CODE (PATTERN (insn)) == ADDR_VEC))
18501     return "Computed branch in the loop.";
18502 
18503   return NULL;
18504 }
18505 
18506 static int
rs6000_ra_ever_killed(void)18507 rs6000_ra_ever_killed (void)
18508 {
18509   rtx top;
18510   rtx reg;
18511   rtx insn;
18512 
18513   if (cfun->is_thunk)
18514     return 0;
18515 
18516   if (cfun->machine->lr_save_state)
18517     return cfun->machine->lr_save_state - 1;
18518 
18519   /* regs_ever_live has LR marked as used if any sibcalls are present,
18520      but this should not force saving and restoring in the
18521      pro/epilogue.  Likewise, reg_set_between_p thinks a sibcall
18522      clobbers LR, so that is inappropriate.  */
18523 
18524   /* Also, the prologue can generate a store into LR that
18525      doesn't really count, like this:
18526 
18527         move LR->R0
18528         bcl to set PIC register
18529         move LR->R31
18530         move R0->LR
18531 
18532      When we're called from the epilogue, we need to avoid counting
18533      this as a store.  */
18534 
18535   push_topmost_sequence ();
18536   top = get_insns ();
18537   pop_topmost_sequence ();
18538   reg = gen_rtx_REG (Pmode, LR_REGNO);
18539 
18540   for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
18541     {
18542       if (INSN_P (insn))
18543 	{
18544 	  if (CALL_P (insn))
18545 	    {
18546 	      if (!SIBLING_CALL_P (insn))
18547 		return 1;
18548 	    }
18549 	  else if (find_regno_note (insn, REG_INC, LR_REGNO))
18550 	    return 1;
18551 	  else if (set_of (reg, insn) != NULL_RTX
18552 		   && !prologue_epilogue_contains (insn))
18553 	    return 1;
18554     	}
18555     }
18556   return 0;
18557 }
18558 
18559 /* Emit instructions needed to load the TOC register.
18560    This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
18561    a constant pool; or for SVR4 -fpic.  */
18562 
18563 void
rs6000_emit_load_toc_table(int fromprolog)18564 rs6000_emit_load_toc_table (int fromprolog)
18565 {
18566   rtx dest;
18567   dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
18568 
18569   if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)
18570     {
18571       char buf[30];
18572       rtx lab, tmp1, tmp2, got;
18573 
18574       lab = gen_label_rtx ();
18575       ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (lab));
18576       lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
18577       if (flag_pic == 2)
18578 	got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
18579       else
18580 	got = rs6000_got_sym ();
18581       tmp1 = tmp2 = dest;
18582       if (!fromprolog)
18583 	{
18584 	  tmp1 = gen_reg_rtx (Pmode);
18585 	  tmp2 = gen_reg_rtx (Pmode);
18586 	}
18587       emit_insn (gen_load_toc_v4_PIC_1 (lab));
18588       emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
18589       emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
18590       emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
18591     }
18592   else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
18593     {
18594       emit_insn (gen_load_toc_v4_pic_si ());
18595       emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
18596     }
18597   else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
18598     {
18599       char buf[30];
18600       rtx temp0 = (fromprolog
18601 		   ? gen_rtx_REG (Pmode, 0)
18602 		   : gen_reg_rtx (Pmode));
18603 
18604       if (fromprolog)
18605 	{
18606 	  rtx symF, symL;
18607 
18608 	  ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
18609 	  symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
18610 
18611 	  ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
18612 	  symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
18613 
18614 	  emit_insn (gen_load_toc_v4_PIC_1 (symF));
18615 	  emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
18616 	  emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, symL, symF));
18617 	}
18618       else
18619 	{
18620 	  rtx tocsym, lab;
18621 
18622 	  tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
18623 	  lab = gen_label_rtx ();
18624 	  emit_insn (gen_load_toc_v4_PIC_1b (tocsym, lab));
18625 	  emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
18626 	  if (TARGET_LINK_STACK)
18627 	    emit_insn (gen_addsi3 (dest, dest, GEN_INT (4)));
18628 	  emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
18629 	}
18630       emit_insn (gen_addsi3 (dest, temp0, dest));
18631     }
18632   else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
18633     {
18634       /* This is for AIX code running in non-PIC ELF32.  */
18635       char buf[30];
18636       rtx realsym;
18637       ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
18638       realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
18639 
18640       emit_insn (gen_elf_high (dest, realsym));
18641       emit_insn (gen_elf_low (dest, dest, realsym));
18642     }
18643   else
18644     {
18645       gcc_assert (DEFAULT_ABI == ABI_AIX);
18646 
18647       if (TARGET_32BIT)
18648 	emit_insn (gen_load_toc_aix_si (dest));
18649       else
18650 	emit_insn (gen_load_toc_aix_di (dest));
18651     }
18652 }
18653 
18654 /* Emit instructions to restore the link register after determining where
18655    its value has been stored.  */
18656 
18657 void
rs6000_emit_eh_reg_restore(rtx source,rtx scratch)18658 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
18659 {
18660   rs6000_stack_t *info = rs6000_stack_info ();
18661   rtx operands[2];
18662 
18663   operands[0] = source;
18664   operands[1] = scratch;
18665 
18666   if (info->lr_save_p)
18667     {
18668       rtx frame_rtx = stack_pointer_rtx;
18669       HOST_WIDE_INT sp_offset = 0;
18670       rtx tmp;
18671 
18672       if (frame_pointer_needed
18673 	  || cfun->calls_alloca
18674 	  || info->total_size > 32767)
18675 	{
18676 	  tmp = gen_frame_mem (Pmode, frame_rtx);
18677 	  emit_move_insn (operands[1], tmp);
18678 	  frame_rtx = operands[1];
18679 	}
18680       else if (info->push_p)
18681 	sp_offset = info->total_size;
18682 
18683       tmp = plus_constant (Pmode, frame_rtx,
18684 			   info->lr_save_offset + sp_offset);
18685       tmp = gen_frame_mem (Pmode, tmp);
18686       emit_move_insn (tmp, operands[0]);
18687     }
18688   else
18689     emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO), operands[0]);
18690 
18691   /* Freeze lr_save_p.  We've just emitted rtl that depends on the
18692      state of lr_save_p so any change from here on would be a bug.  In
18693      particular, stop rs6000_ra_ever_killed from considering the SET
18694      of lr we may have added just above.  */
18695   cfun->machine->lr_save_state = info->lr_save_p + 1;
18696 }
18697 
18698 static GTY(()) alias_set_type set = -1;
18699 
18700 alias_set_type
get_TOC_alias_set(void)18701 get_TOC_alias_set (void)
18702 {
18703   if (set == -1)
18704     set = new_alias_set ();
18705   return set;
18706 }
18707 
18708 /* This returns nonzero if the current function uses the TOC.  This is
18709    determined by the presence of (use (unspec ... UNSPEC_TOC)), which
18710    is generated by the ABI_V4 load_toc_* patterns.  */
18711 #if TARGET_ELF
18712 static int
uses_TOC(void)18713 uses_TOC (void)
18714 {
18715   rtx insn;
18716 
18717   for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
18718     if (INSN_P (insn))
18719       {
18720 	rtx pat = PATTERN (insn);
18721 	int i;
18722 
18723 	if (GET_CODE (pat) == PARALLEL)
18724 	  for (i = 0; i < XVECLEN (pat, 0); i++)
18725 	    {
18726 	      rtx sub = XVECEXP (pat, 0, i);
18727 	      if (GET_CODE (sub) == USE)
18728 		{
18729 		  sub = XEXP (sub, 0);
18730 		  if (GET_CODE (sub) == UNSPEC
18731 		      && XINT (sub, 1) == UNSPEC_TOC)
18732 		    return 1;
18733 		}
18734 	    }
18735       }
18736   return 0;
18737 }
18738 #endif
18739 
18740 rtx
create_TOC_reference(rtx symbol,rtx largetoc_reg)18741 create_TOC_reference (rtx symbol, rtx largetoc_reg)
18742 {
18743   rtx tocrel, tocreg, hi;
18744 
18745   if (TARGET_DEBUG_ADDR)
18746     {
18747       if (GET_CODE (symbol) == SYMBOL_REF)
18748 	fprintf (stderr, "\ncreate_TOC_reference, (symbol_ref %s)\n",
18749 		 XSTR (symbol, 0));
18750       else
18751 	{
18752 	  fprintf (stderr, "\ncreate_TOC_reference, code %s:\n",
18753 		   GET_RTX_NAME (GET_CODE (symbol)));
18754 	  debug_rtx (symbol);
18755 	}
18756     }
18757 
18758   if (!can_create_pseudo_p ())
18759     df_set_regs_ever_live (TOC_REGISTER, true);
18760 
18761   tocreg = gen_rtx_REG (Pmode, TOC_REGISTER);
18762   tocrel = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, symbol, tocreg), UNSPEC_TOCREL);
18763   if (TARGET_CMODEL == CMODEL_SMALL || can_create_pseudo_p ())
18764     return tocrel;
18765 
18766   hi = gen_rtx_HIGH (Pmode, copy_rtx (tocrel));
18767   if (largetoc_reg != NULL)
18768     {
18769       emit_move_insn (largetoc_reg, hi);
18770       hi = largetoc_reg;
18771     }
18772   return gen_rtx_LO_SUM (Pmode, hi, tocrel);
18773 }
18774 
18775 /* Issue assembly directives that create a reference to the given DWARF
18776    FRAME_TABLE_LABEL from the current function section.  */
18777 void
rs6000_aix_asm_output_dwarf_table_ref(char * frame_table_label)18778 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label)
18779 {
18780   fprintf (asm_out_file, "\t.ref %s\n",
18781 	   (* targetm.strip_name_encoding) (frame_table_label));
18782 }
18783 
18784 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
18785    and the change to the stack pointer.  */
18786 
18787 static void
rs6000_emit_stack_tie(rtx fp,bool hard_frame_needed)18788 rs6000_emit_stack_tie (rtx fp, bool hard_frame_needed)
18789 {
18790   rtvec p;
18791   int i;
18792   rtx regs[3];
18793 
18794   i = 0;
18795   regs[i++] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
18796   if (hard_frame_needed)
18797     regs[i++] = gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM);
18798   if (!(REGNO (fp) == STACK_POINTER_REGNUM
18799 	|| (hard_frame_needed
18800 	    && REGNO (fp) == HARD_FRAME_POINTER_REGNUM)))
18801     regs[i++] = fp;
18802 
18803   p = rtvec_alloc (i);
18804   while (--i >= 0)
18805     {
18806       rtx mem = gen_frame_mem (BLKmode, regs[i]);
18807       RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, const0_rtx);
18808     }
18809 
18810   emit_insn (gen_stack_tie (gen_rtx_PARALLEL (VOIDmode, p)));
18811 }
18812 
18813 /* Emit the correct code for allocating stack space, as insns.
18814    If COPY_REG, make sure a copy of the old frame is left there.
18815    The generated code may use hard register 0 as a temporary.  */
18816 
18817 static void
rs6000_emit_allocate_stack(HOST_WIDE_INT size,rtx copy_reg,int copy_off)18818 rs6000_emit_allocate_stack (HOST_WIDE_INT size, rtx copy_reg, int copy_off)
18819 {
18820   rtx insn;
18821   rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
18822   rtx tmp_reg = gen_rtx_REG (Pmode, 0);
18823   rtx todec = gen_int_mode (-size, Pmode);
18824   rtx par, set, mem;
18825 
18826   if (INTVAL (todec) != -size)
18827     {
18828       warning (0, "stack frame too large");
18829       emit_insn (gen_trap ());
18830       return;
18831     }
18832 
18833   if (crtl->limit_stack)
18834     {
18835       if (REG_P (stack_limit_rtx)
18836 	  && REGNO (stack_limit_rtx) > 1
18837 	  && REGNO (stack_limit_rtx) <= 31)
18838 	{
18839 	  emit_insn (gen_add3_insn (tmp_reg, stack_limit_rtx, GEN_INT (size)));
18840 	  emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
18841 				    const0_rtx));
18842 	}
18843       else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
18844 	       && TARGET_32BIT
18845 	       && DEFAULT_ABI == ABI_V4)
18846 	{
18847 	  rtx toload = gen_rtx_CONST (VOIDmode,
18848 				      gen_rtx_PLUS (Pmode,
18849 						    stack_limit_rtx,
18850 						    GEN_INT (size)));
18851 
18852 	  emit_insn (gen_elf_high (tmp_reg, toload));
18853 	  emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
18854 	  emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
18855 				    const0_rtx));
18856 	}
18857       else
18858 	warning (0, "stack limit expression is not supported");
18859     }
18860 
18861   if (copy_reg)
18862     {
18863       if (copy_off != 0)
18864 	emit_insn (gen_add3_insn (copy_reg, stack_reg, GEN_INT (copy_off)));
18865       else
18866 	emit_move_insn (copy_reg, stack_reg);
18867     }
18868 
18869   if (size > 32767)
18870     {
18871       /* Need a note here so that try_split doesn't get confused.  */
18872       if (get_last_insn () == NULL_RTX)
18873 	emit_note (NOTE_INSN_DELETED);
18874       insn = emit_move_insn (tmp_reg, todec);
18875       try_split (PATTERN (insn), insn, 0);
18876       todec = tmp_reg;
18877     }
18878 
18879   insn = emit_insn (TARGET_32BIT
18880 		    ? gen_movsi_update_stack (stack_reg, stack_reg,
18881 					todec, stack_reg)
18882 		    : gen_movdi_di_update_stack (stack_reg, stack_reg,
18883 					   todec, stack_reg));
18884   /* Since we didn't use gen_frame_mem to generate the MEM, grab
18885      it now and set the alias set/attributes. The above gen_*_update
18886      calls will generate a PARALLEL with the MEM set being the first
18887      operation. */
18888   par = PATTERN (insn);
18889   gcc_assert (GET_CODE (par) == PARALLEL);
18890   set = XVECEXP (par, 0, 0);
18891   gcc_assert (GET_CODE (set) == SET);
18892   mem = SET_DEST (set);
18893   gcc_assert (MEM_P (mem));
18894   MEM_NOTRAP_P (mem) = 1;
18895   set_mem_alias_set (mem, get_frame_alias_set ());
18896 
18897   RTX_FRAME_RELATED_P (insn) = 1;
18898   add_reg_note (insn, REG_FRAME_RELATED_EXPR,
18899 		gen_rtx_SET (VOIDmode, stack_reg,
18900 			     gen_rtx_PLUS (Pmode, stack_reg,
18901 					   GEN_INT (-size))));
18902 }
18903 
18904 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
18905 
18906 #if PROBE_INTERVAL > 32768
18907 #error Cannot use indexed addressing mode for stack probing
18908 #endif
18909 
18910 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
18911    inclusive.  These are offsets from the current stack pointer.  */
18912 
18913 static void
rs6000_emit_probe_stack_range(HOST_WIDE_INT first,HOST_WIDE_INT size)18914 rs6000_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
18915 {
18916   /* See if we have a constant small number of probes to generate.  If so,
18917      that's the easy case.  */
18918   if (first + size <= 32768)
18919     {
18920       HOST_WIDE_INT i;
18921 
18922       /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
18923 	 it exceeds SIZE.  If only one probe is needed, this will not
18924 	 generate any code.  Then probe at FIRST + SIZE.  */
18925       for (i = PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
18926 	emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
18927 					 -(first + i)));
18928 
18929       emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
18930 				       -(first + size)));
18931     }
18932 
18933   /* Otherwise, do the same as above, but in a loop.  Note that we must be
18934      extra careful with variables wrapping around because we might be at
18935      the very top (or the very bottom) of the address space and we have
18936      to be able to handle this case properly; in particular, we use an
18937      equality test for the loop condition.  */
18938   else
18939     {
18940       HOST_WIDE_INT rounded_size;
18941       rtx r12 = gen_rtx_REG (Pmode, 12);
18942       rtx r0 = gen_rtx_REG (Pmode, 0);
18943 
18944       /* Sanity check for the addressing mode we're going to use.  */
18945       gcc_assert (first <= 32768);
18946 
18947       /* Step 1: round SIZE to the previous multiple of the interval.  */
18948 
18949       rounded_size = size & -PROBE_INTERVAL;
18950 
18951 
18952       /* Step 2: compute initial and final value of the loop counter.  */
18953 
18954       /* TEST_ADDR = SP + FIRST.  */
18955       emit_insn (gen_rtx_SET (VOIDmode, r12,
18956 			      plus_constant (Pmode, stack_pointer_rtx,
18957 					     -first)));
18958 
18959       /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE.  */
18960       if (rounded_size > 32768)
18961 	{
18962 	  emit_move_insn (r0, GEN_INT (-rounded_size));
18963 	  emit_insn (gen_rtx_SET (VOIDmode, r0,
18964 				  gen_rtx_PLUS (Pmode, r12, r0)));
18965 	}
18966       else
18967 	emit_insn (gen_rtx_SET (VOIDmode, r0,
18968 			        plus_constant (Pmode, r12, -rounded_size)));
18969 
18970 
18971       /* Step 3: the loop
18972 
18973 	 while (TEST_ADDR != LAST_ADDR)
18974 	   {
18975 	     TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
18976 	     probe at TEST_ADDR
18977 	   }
18978 
18979 	 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
18980 	 until it is equal to ROUNDED_SIZE.  */
18981 
18982       if (TARGET_64BIT)
18983 	emit_insn (gen_probe_stack_rangedi (r12, r12, r0));
18984       else
18985 	emit_insn (gen_probe_stack_rangesi (r12, r12, r0));
18986 
18987 
18988       /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
18989 	 that SIZE is equal to ROUNDED_SIZE.  */
18990 
18991       if (size != rounded_size)
18992 	emit_stack_probe (plus_constant (Pmode, r12, rounded_size - size));
18993     }
18994 }
18995 
18996 /* Probe a range of stack addresses from REG1 to REG2 inclusive.  These are
18997    absolute addresses.  */
18998 
18999 const char *
output_probe_stack_range(rtx reg1,rtx reg2)19000 output_probe_stack_range (rtx reg1, rtx reg2)
19001 {
19002   static int labelno = 0;
19003   char loop_lab[32], end_lab[32];
19004   rtx xops[2];
19005 
19006   ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno);
19007   ASM_GENERATE_INTERNAL_LABEL (end_lab, "LPSRE", labelno++);
19008 
19009   ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
19010 
19011   /* Jump to END_LAB if TEST_ADDR == LAST_ADDR.  */
19012   xops[0] = reg1;
19013   xops[1] = reg2;
19014   if (TARGET_64BIT)
19015     output_asm_insn ("cmpd 0,%0,%1", xops);
19016   else
19017     output_asm_insn ("cmpw 0,%0,%1", xops);
19018 
19019   fputs ("\tbeq 0,", asm_out_file);
19020   assemble_name_raw (asm_out_file, end_lab);
19021   fputc ('\n', asm_out_file);
19022 
19023   /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL.  */
19024   xops[1] = GEN_INT (-PROBE_INTERVAL);
19025   output_asm_insn ("addi %0,%0,%1", xops);
19026 
19027   /* Probe at TEST_ADDR and branch.  */
19028   xops[1] = gen_rtx_REG (Pmode, 0);
19029   output_asm_insn ("stw %1,0(%0)", xops);
19030   fprintf (asm_out_file, "\tb ");
19031   assemble_name_raw (asm_out_file, loop_lab);
19032   fputc ('\n', asm_out_file);
19033 
19034   ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, end_lab);
19035 
19036   return "";
19037 }
19038 
19039 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
19040    with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
19041    is not NULL.  It would be nice if dwarf2out_frame_debug_expr could
19042    deduce these equivalences by itself so it wasn't necessary to hold
19043    its hand so much.  Don't be tempted to always supply d2_f_d_e with
19044    the actual cfa register, ie. r31 when we are using a hard frame
19045    pointer.  That fails when saving regs off r1, and sched moves the
19046    r31 setup past the reg saves.  */
19047 
19048 static rtx
rs6000_frame_related(rtx insn,rtx reg,HOST_WIDE_INT val,rtx reg2,rtx rreg)19049 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
19050 		      rtx reg2, rtx rreg)
19051 {
19052   rtx real, temp;
19053 
19054   if (REGNO (reg) == STACK_POINTER_REGNUM && reg2 == NULL_RTX)
19055     {
19056       /* No need for any replacement.  Just set RTX_FRAME_RELATED_P.  */
19057       int i;
19058 
19059       gcc_checking_assert (val == 0);
19060       real = PATTERN (insn);
19061       if (GET_CODE (real) == PARALLEL)
19062 	for (i = 0; i < XVECLEN (real, 0); i++)
19063 	  if (GET_CODE (XVECEXP (real, 0, i)) == SET)
19064 	    {
19065 	      rtx set = XVECEXP (real, 0, i);
19066 
19067 	      RTX_FRAME_RELATED_P (set) = 1;
19068 	    }
19069       RTX_FRAME_RELATED_P (insn) = 1;
19070       return insn;
19071     }
19072 
19073   /* copy_rtx will not make unique copies of registers, so we need to
19074      ensure we don't have unwanted sharing here.  */
19075   if (reg == reg2)
19076     reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
19077 
19078   if (reg == rreg)
19079     reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
19080 
19081   real = copy_rtx (PATTERN (insn));
19082 
19083   if (reg2 != NULL_RTX)
19084     real = replace_rtx (real, reg2, rreg);
19085 
19086   if (REGNO (reg) == STACK_POINTER_REGNUM)
19087     gcc_checking_assert (val == 0);
19088   else
19089     real = replace_rtx (real, reg,
19090 			gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
19091 							  STACK_POINTER_REGNUM),
19092 				      GEN_INT (val)));
19093 
19094   /* We expect that 'real' is either a SET or a PARALLEL containing
19095      SETs (and possibly other stuff).  In a PARALLEL, all the SETs
19096      are important so they all have to be marked RTX_FRAME_RELATED_P.  */
19097 
19098   if (GET_CODE (real) == SET)
19099     {
19100       rtx set = real;
19101 
19102       temp = simplify_rtx (SET_SRC (set));
19103       if (temp)
19104 	SET_SRC (set) = temp;
19105       temp = simplify_rtx (SET_DEST (set));
19106       if (temp)
19107 	SET_DEST (set) = temp;
19108       if (GET_CODE (SET_DEST (set)) == MEM)
19109 	{
19110 	  temp = simplify_rtx (XEXP (SET_DEST (set), 0));
19111 	  if (temp)
19112 	    XEXP (SET_DEST (set), 0) = temp;
19113 	}
19114     }
19115   else
19116     {
19117       int i;
19118 
19119       gcc_assert (GET_CODE (real) == PARALLEL);
19120       for (i = 0; i < XVECLEN (real, 0); i++)
19121 	if (GET_CODE (XVECEXP (real, 0, i)) == SET)
19122 	  {
19123 	    rtx set = XVECEXP (real, 0, i);
19124 
19125 	    temp = simplify_rtx (SET_SRC (set));
19126 	    if (temp)
19127 	      SET_SRC (set) = temp;
19128 	    temp = simplify_rtx (SET_DEST (set));
19129 	    if (temp)
19130 	      SET_DEST (set) = temp;
19131 	    if (GET_CODE (SET_DEST (set)) == MEM)
19132 	      {
19133 		temp = simplify_rtx (XEXP (SET_DEST (set), 0));
19134 		if (temp)
19135 		  XEXP (SET_DEST (set), 0) = temp;
19136 	      }
19137 	    RTX_FRAME_RELATED_P (set) = 1;
19138 	  }
19139     }
19140 
19141   RTX_FRAME_RELATED_P (insn) = 1;
19142   add_reg_note (insn, REG_FRAME_RELATED_EXPR, real);
19143 
19144   return insn;
19145 }
19146 
19147 /* Returns an insn that has a vrsave set operation with the
19148    appropriate CLOBBERs.  */
19149 
19150 static rtx
generate_set_vrsave(rtx reg,rs6000_stack_t * info,int epiloguep)19151 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
19152 {
19153   int nclobs, i;
19154   rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
19155   rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
19156 
19157   clobs[0]
19158     = gen_rtx_SET (VOIDmode,
19159 		   vrsave,
19160 		   gen_rtx_UNSPEC_VOLATILE (SImode,
19161 					    gen_rtvec (2, reg, vrsave),
19162 					    UNSPECV_SET_VRSAVE));
19163 
19164   nclobs = 1;
19165 
19166   /* We need to clobber the registers in the mask so the scheduler
19167      does not move sets to VRSAVE before sets of AltiVec registers.
19168 
19169      However, if the function receives nonlocal gotos, reload will set
19170      all call saved registers live.  We will end up with:
19171 
19172      	(set (reg 999) (mem))
19173 	(parallel [ (set (reg vrsave) (unspec blah))
19174 		    (clobber (reg 999))])
19175 
19176      The clobber will cause the store into reg 999 to be dead, and
19177      flow will attempt to delete an epilogue insn.  In this case, we
19178      need an unspec use/set of the register.  */
19179 
19180   for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
19181     if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
19182       {
19183 	if (!epiloguep || call_used_regs [i])
19184 	  clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
19185 					     gen_rtx_REG (V4SImode, i));
19186 	else
19187 	  {
19188 	    rtx reg = gen_rtx_REG (V4SImode, i);
19189 
19190 	    clobs[nclobs++]
19191 	      = gen_rtx_SET (VOIDmode,
19192 			     reg,
19193 			     gen_rtx_UNSPEC (V4SImode,
19194 					     gen_rtvec (1, reg), 27));
19195 	  }
19196       }
19197 
19198   insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
19199 
19200   for (i = 0; i < nclobs; ++i)
19201     XVECEXP (insn, 0, i) = clobs[i];
19202 
19203   return insn;
19204 }
19205 
19206 static rtx
gen_frame_set(rtx reg,rtx frame_reg,int offset,bool store)19207 gen_frame_set (rtx reg, rtx frame_reg, int offset, bool store)
19208 {
19209   rtx addr, mem;
19210 
19211   addr = gen_rtx_PLUS (Pmode, frame_reg, GEN_INT (offset));
19212   mem = gen_frame_mem (GET_MODE (reg), addr);
19213   return gen_rtx_SET (VOIDmode, store ? mem : reg, store ? reg : mem);
19214 }
19215 
19216 static rtx
gen_frame_load(rtx reg,rtx frame_reg,int offset)19217 gen_frame_load (rtx reg, rtx frame_reg, int offset)
19218 {
19219   return gen_frame_set (reg, frame_reg, offset, false);
19220 }
19221 
19222 static rtx
gen_frame_store(rtx reg,rtx frame_reg,int offset)19223 gen_frame_store (rtx reg, rtx frame_reg, int offset)
19224 {
19225   return gen_frame_set (reg, frame_reg, offset, true);
19226 }
19227 
19228 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
19229    Save REGNO into [FRAME_REG + OFFSET] in mode MODE.  */
19230 
19231 static rtx
emit_frame_save(rtx frame_reg,enum machine_mode mode,unsigned int regno,int offset,HOST_WIDE_INT frame_reg_to_sp)19232 emit_frame_save (rtx frame_reg, enum machine_mode mode,
19233 		 unsigned int regno, int offset, HOST_WIDE_INT frame_reg_to_sp)
19234 {
19235   rtx reg, insn;
19236 
19237   /* Some cases that need register indexed addressing.  */
19238   gcc_checking_assert (!((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
19239 			 || (TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
19240 			 || (TARGET_E500_DOUBLE && mode == DFmode)
19241 			 || (TARGET_SPE_ABI
19242 			     && SPE_VECTOR_MODE (mode)
19243 			     && !SPE_CONST_OFFSET_OK (offset))));
19244 
19245   reg = gen_rtx_REG (mode, regno);
19246   insn = emit_insn (gen_frame_store (reg, frame_reg, offset));
19247   return rs6000_frame_related (insn, frame_reg, frame_reg_to_sp,
19248 			       NULL_RTX, NULL_RTX);
19249 }
19250 
19251 /* Emit an offset memory reference suitable for a frame store, while
19252    converting to a valid addressing mode.  */
19253 
19254 static rtx
gen_frame_mem_offset(enum machine_mode mode,rtx reg,int offset)19255 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
19256 {
19257   rtx int_rtx, offset_rtx;
19258 
19259   int_rtx = GEN_INT (offset);
19260 
19261   if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode) && !SPE_CONST_OFFSET_OK (offset))
19262       || (TARGET_E500_DOUBLE && mode == DFmode))
19263     {
19264       offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
19265       emit_move_insn (offset_rtx, int_rtx);
19266     }
19267   else
19268     offset_rtx = int_rtx;
19269 
19270   return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
19271 }
19272 
19273 #ifndef TARGET_FIX_AND_CONTINUE
19274 #define TARGET_FIX_AND_CONTINUE 0
19275 #endif
19276 
19277 /* It's really GPR 13 or 14, FPR 14 and VR 20.  We need the smallest.  */
19278 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
19279 #define LAST_SAVRES_REGISTER 31
19280 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
19281 
19282 enum {
19283   SAVRES_LR = 0x1,
19284   SAVRES_SAVE = 0x2,
19285   SAVRES_REG = 0x0c,
19286   SAVRES_GPR = 0,
19287   SAVRES_FPR = 4,
19288   SAVRES_VR  = 8
19289 };
19290 
19291 static GTY(()) rtx savres_routine_syms[N_SAVRES_REGISTERS][12];
19292 
19293 /* Temporary holding space for an out-of-line register save/restore
19294    routine name.  */
19295 static char savres_routine_name[30];
19296 
19297 /* Return the name for an out-of-line register save/restore routine.
19298    We are saving/restoring GPRs if GPR is true.  */
19299 
19300 static char *
rs6000_savres_routine_name(rs6000_stack_t * info,int regno,int sel)19301 rs6000_savres_routine_name (rs6000_stack_t *info, int regno, int sel)
19302 {
19303   const char *prefix = "";
19304   const char *suffix = "";
19305 
19306   /* Different targets are supposed to define
19307      {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
19308      routine name could be defined with:
19309 
19310      sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
19311 
19312      This is a nice idea in practice, but in reality, things are
19313      complicated in several ways:
19314 
19315      - ELF targets have save/restore routines for GPRs.
19316 
19317      - SPE targets use different prefixes for 32/64-bit registers, and
19318        neither of them fit neatly in the FOO_{PREFIX,SUFFIX} regimen.
19319 
19320      - PPC64 ELF targets have routines for save/restore of GPRs that
19321        differ in what they do with the link register, so having a set
19322        prefix doesn't work.  (We only use one of the save routines at
19323        the moment, though.)
19324 
19325      - PPC32 elf targets have "exit" versions of the restore routines
19326        that restore the link register and can save some extra space.
19327        These require an extra suffix.  (There are also "tail" versions
19328        of the restore routines and "GOT" versions of the save routines,
19329        but we don't generate those at present.  Same problems apply,
19330        though.)
19331 
19332      We deal with all this by synthesizing our own prefix/suffix and
19333      using that for the simple sprintf call shown above.  */
19334   if (TARGET_SPE)
19335     {
19336       /* No floating point saves on the SPE.  */
19337       gcc_assert ((sel & SAVRES_REG) == SAVRES_GPR);
19338 
19339       if ((sel & SAVRES_SAVE))
19340 	prefix = info->spe_64bit_regs_used ? "_save64gpr_" : "_save32gpr_";
19341       else
19342 	prefix = info->spe_64bit_regs_used ? "_rest64gpr_" : "_rest32gpr_";
19343 
19344       if ((sel & SAVRES_LR))
19345 	suffix = "_x";
19346     }
19347   else if (DEFAULT_ABI == ABI_V4)
19348     {
19349       if (TARGET_64BIT)
19350 	goto aix_names;
19351 
19352       if ((sel & SAVRES_REG) == SAVRES_GPR)
19353 	prefix = (sel & SAVRES_SAVE) ? "_savegpr_" : "_restgpr_";
19354       else if ((sel & SAVRES_REG) == SAVRES_FPR)
19355 	prefix = (sel & SAVRES_SAVE) ? "_savefpr_" : "_restfpr_";
19356       else if ((sel & SAVRES_REG) == SAVRES_VR)
19357 	prefix = (sel & SAVRES_SAVE) ? "_savevr_" : "_restvr_";
19358       else
19359 	abort ();
19360 
19361       if ((sel & SAVRES_LR))
19362 	suffix = "_x";
19363     }
19364   else if (DEFAULT_ABI == ABI_AIX)
19365     {
19366 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
19367       /* No out-of-line save/restore routines for GPRs on AIX.  */
19368       gcc_assert (!TARGET_AIX || (sel & SAVRES_REG) != SAVRES_GPR);
19369 #endif
19370 
19371     aix_names:
19372       if ((sel & SAVRES_REG) == SAVRES_GPR)
19373 	prefix = ((sel & SAVRES_SAVE)
19374 		  ? ((sel & SAVRES_LR) ? "_savegpr0_" : "_savegpr1_")
19375 		  : ((sel & SAVRES_LR) ? "_restgpr0_" : "_restgpr1_"));
19376       else if ((sel & SAVRES_REG) == SAVRES_FPR)
19377 	{
19378 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
19379 	  if ((sel & SAVRES_LR))
19380 	    prefix = ((sel & SAVRES_SAVE) ? "_savefpr_" : "_restfpr_");
19381 	  else
19382 #endif
19383 	    {
19384 	      prefix = (sel & SAVRES_SAVE) ? SAVE_FP_PREFIX : RESTORE_FP_PREFIX;
19385 	      suffix = (sel & SAVRES_SAVE) ? SAVE_FP_SUFFIX : RESTORE_FP_SUFFIX;
19386 	    }
19387 	}
19388       else if ((sel & SAVRES_REG) == SAVRES_VR)
19389 	prefix = (sel & SAVRES_SAVE) ? "_savevr_" : "_restvr_";
19390       else
19391 	abort ();
19392     }
19393 
19394    if (DEFAULT_ABI == ABI_DARWIN)
19395     {
19396       /* The Darwin approach is (slightly) different, in order to be
19397 	 compatible with code generated by the system toolchain.  There is a
19398 	 single symbol for the start of save sequence, and the code here
19399 	 embeds an offset into that code on the basis of the first register
19400 	 to be saved.  */
19401       prefix = (sel & SAVRES_SAVE) ? "save" : "rest" ;
19402       if ((sel & SAVRES_REG) == SAVRES_GPR)
19403 	sprintf (savres_routine_name, "*%sGPR%s%s%.0d ; %s r%d-r31", prefix,
19404 		 ((sel & SAVRES_LR) ? "x" : ""), (regno == 13 ? "" : "+"),
19405 		 (regno - 13) * 4, prefix, regno);
19406       else if ((sel & SAVRES_REG) == SAVRES_FPR)
19407 	sprintf (savres_routine_name, "*%sFP%s%.0d ; %s f%d-f31", prefix,
19408 		 (regno == 14 ? "" : "+"), (regno - 14) * 4, prefix, regno);
19409       else if ((sel & SAVRES_REG) == SAVRES_VR)
19410 	sprintf (savres_routine_name, "*%sVEC%s%.0d ; %s v%d-v31", prefix,
19411 		 (regno == 20 ? "" : "+"), (regno - 20) * 8, prefix, regno);
19412       else
19413 	abort ();
19414     }
19415   else
19416     sprintf (savres_routine_name, "%s%d%s", prefix, regno, suffix);
19417 
19418   return savres_routine_name;
19419 }
19420 
19421 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
19422    We are saving/restoring GPRs if GPR is true.  */
19423 
19424 static rtx
rs6000_savres_routine_sym(rs6000_stack_t * info,int sel)19425 rs6000_savres_routine_sym (rs6000_stack_t *info, int sel)
19426 {
19427   int regno = ((sel & SAVRES_REG) == SAVRES_GPR
19428 	       ? info->first_gp_reg_save
19429 	       : (sel & SAVRES_REG) == SAVRES_FPR
19430 	       ? info->first_fp_reg_save - 32
19431 	       : (sel & SAVRES_REG) == SAVRES_VR
19432 	       ? info->first_altivec_reg_save - FIRST_ALTIVEC_REGNO
19433 	       : -1);
19434   rtx sym;
19435   int select = sel;
19436 
19437   /* On the SPE, we never have any FPRs, but we do have 32/64-bit
19438      versions of the gpr routines.  */
19439   if (TARGET_SPE_ABI && (sel & SAVRES_REG) == SAVRES_GPR
19440       && info->spe_64bit_regs_used)
19441     select ^= SAVRES_FPR ^ SAVRES_GPR;
19442 
19443   /* Don't generate bogus routine names.  */
19444   gcc_assert (FIRST_SAVRES_REGISTER <= regno
19445 	      && regno <= LAST_SAVRES_REGISTER
19446 	      && select >= 0 && select <= 12);
19447 
19448   sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select];
19449 
19450   if (sym == NULL)
19451     {
19452       char *name;
19453 
19454       name = rs6000_savres_routine_name (info, regno, sel);
19455 
19456       sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select]
19457 	= gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
19458       SYMBOL_REF_FLAGS (sym) |= SYMBOL_FLAG_FUNCTION;
19459     }
19460 
19461   return sym;
19462 }
19463 
19464 /* Emit a sequence of insns, including a stack tie if needed, for
19465    resetting the stack pointer.  If UPDT_REGNO is not 1, then don't
19466    reset the stack pointer, but move the base of the frame into
19467    reg UPDT_REGNO for use by out-of-line register restore routines.  */
19468 
19469 static rtx
rs6000_emit_stack_reset(rs6000_stack_t * info,rtx frame_reg_rtx,HOST_WIDE_INT frame_off,unsigned updt_regno)19470 rs6000_emit_stack_reset (rs6000_stack_t *info,
19471 			 rtx frame_reg_rtx, HOST_WIDE_INT frame_off,
19472 			 unsigned updt_regno)
19473 {
19474   rtx updt_reg_rtx;
19475 
19476   /* This blockage is needed so that sched doesn't decide to move
19477      the sp change before the register restores.  */
19478   if (DEFAULT_ABI == ABI_V4
19479       || (TARGET_SPE_ABI
19480 	  && info->spe_64bit_regs_used != 0
19481 	  && info->first_gp_reg_save != 32))
19482     rs6000_emit_stack_tie (frame_reg_rtx, frame_pointer_needed);
19483 
19484   /* If we are restoring registers out-of-line, we will be using the
19485      "exit" variants of the restore routines, which will reset the
19486      stack for us.  But we do need to point updt_reg into the
19487      right place for those routines.  */
19488   updt_reg_rtx = gen_rtx_REG (Pmode, updt_regno);
19489 
19490   if (frame_off != 0)
19491     return emit_insn (gen_add3_insn (updt_reg_rtx,
19492 				     frame_reg_rtx, GEN_INT (frame_off)));
19493   else if (REGNO (frame_reg_rtx) != updt_regno)
19494     return emit_move_insn (updt_reg_rtx, frame_reg_rtx);
19495 
19496   return NULL_RTX;
19497 }
19498 
19499 /* Return the register number used as a pointer by out-of-line
19500    save/restore functions.  */
19501 
19502 static inline unsigned
ptr_regno_for_savres(int sel)19503 ptr_regno_for_savres (int sel)
19504 {
19505   if (DEFAULT_ABI == ABI_AIX)
19506     return (sel & SAVRES_REG) == SAVRES_FPR || (sel & SAVRES_LR) ? 1 : 12;
19507   return DEFAULT_ABI == ABI_DARWIN && (sel & SAVRES_REG) == SAVRES_FPR ? 1 : 11;
19508 }
19509 
19510 /* Construct a parallel rtx describing the effect of a call to an
19511    out-of-line register save/restore routine, and emit the insn
19512    or jump_insn as appropriate.  */
19513 
19514 static rtx
rs6000_emit_savres_rtx(rs6000_stack_t * info,rtx frame_reg_rtx,int save_area_offset,int lr_offset,enum machine_mode reg_mode,int sel)19515 rs6000_emit_savres_rtx (rs6000_stack_t *info,
19516 			rtx frame_reg_rtx, int save_area_offset, int lr_offset,
19517 			enum machine_mode reg_mode, int sel)
19518 {
19519   int i;
19520   int offset, start_reg, end_reg, n_regs, use_reg;
19521   int reg_size = GET_MODE_SIZE (reg_mode);
19522   rtx sym;
19523   rtvec p;
19524   rtx par, insn;
19525 
19526   offset = 0;
19527   start_reg = ((sel & SAVRES_REG) == SAVRES_GPR
19528 	       ? info->first_gp_reg_save
19529 	       : (sel & SAVRES_REG) == SAVRES_FPR
19530 	       ? info->first_fp_reg_save
19531 	       : (sel & SAVRES_REG) == SAVRES_VR
19532 	       ? info->first_altivec_reg_save
19533 	       : -1);
19534   end_reg = ((sel & SAVRES_REG) == SAVRES_GPR
19535 	     ? 32
19536 	     : (sel & SAVRES_REG) == SAVRES_FPR
19537 	     ? 64
19538 	     : (sel & SAVRES_REG) == SAVRES_VR
19539 	     ? LAST_ALTIVEC_REGNO + 1
19540 	     : -1);
19541   n_regs = end_reg - start_reg;
19542   p = rtvec_alloc (3 + ((sel & SAVRES_LR) ? 1 : 0)
19543 		   + ((sel & SAVRES_REG) == SAVRES_VR ? 1 : 0)
19544 		   + n_regs);
19545 
19546   if (!(sel & SAVRES_SAVE) && (sel & SAVRES_LR))
19547     RTVEC_ELT (p, offset++) = ret_rtx;
19548 
19549   RTVEC_ELT (p, offset++)
19550     = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, LR_REGNO));
19551 
19552   sym = rs6000_savres_routine_sym (info, sel);
19553   RTVEC_ELT (p, offset++) = gen_rtx_USE (VOIDmode, sym);
19554 
19555   use_reg = ptr_regno_for_savres (sel);
19556   if ((sel & SAVRES_REG) == SAVRES_VR)
19557     {
19558       /* Vector regs are saved/restored using [reg+reg] addressing.  */
19559       RTVEC_ELT (p, offset++)
19560 	= gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, use_reg));
19561       RTVEC_ELT (p, offset++)
19562 	= gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
19563     }
19564   else
19565     RTVEC_ELT (p, offset++)
19566       = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, use_reg));
19567 
19568   for (i = 0; i < end_reg - start_reg; i++)
19569     RTVEC_ELT (p, i + offset)
19570       = gen_frame_set (gen_rtx_REG (reg_mode, start_reg + i),
19571 		       frame_reg_rtx, save_area_offset + reg_size * i,
19572 		       (sel & SAVRES_SAVE) != 0);
19573 
19574   if ((sel & SAVRES_SAVE) && (sel & SAVRES_LR))
19575     RTVEC_ELT (p, i + offset)
19576       = gen_frame_store (gen_rtx_REG (Pmode, 0), frame_reg_rtx, lr_offset);
19577 
19578   par = gen_rtx_PARALLEL (VOIDmode, p);
19579 
19580   if (!(sel & SAVRES_SAVE) && (sel & SAVRES_LR))
19581     {
19582       insn = emit_jump_insn (par);
19583       JUMP_LABEL (insn) = ret_rtx;
19584     }
19585   else
19586     insn = emit_insn (par);
19587   return insn;
19588 }
19589 
19590 /* Determine whether the gp REG is really used.  */
19591 
19592 static bool
rs6000_reg_live_or_pic_offset_p(int reg)19593 rs6000_reg_live_or_pic_offset_p (int reg)
19594 {
19595   /* If the function calls eh_return, claim used all the registers that would
19596      be checked for liveness otherwise.  This is required for the PIC offset
19597      register with -mminimal-toc on AIX, as it is advertised as "fixed" for
19598      register allocation purposes in this case.  */
19599 
19600   return (((crtl->calls_eh_return || df_regs_ever_live_p (reg))
19601            && (!call_used_regs[reg]
19602                || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
19603 		   && !TARGET_SINGLE_PIC_BASE
19604                    && TARGET_TOC && TARGET_MINIMAL_TOC)))
19605           || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
19606 	      && !TARGET_SINGLE_PIC_BASE
19607               && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
19608                   || (DEFAULT_ABI == ABI_DARWIN && flag_pic))));
19609 }
19610 
19611 /* Emit function prologue as insns.  */
19612 
19613 void
rs6000_emit_prologue(void)19614 rs6000_emit_prologue (void)
19615 {
19616   rs6000_stack_t *info = rs6000_stack_info ();
19617   enum machine_mode reg_mode = Pmode;
19618   int reg_size = TARGET_32BIT ? 4 : 8;
19619   rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
19620   rtx frame_reg_rtx = sp_reg_rtx;
19621   unsigned int cr_save_regno;
19622   rtx cr_save_rtx = NULL_RTX;
19623   rtx insn;
19624   int strategy;
19625   int using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
19626 			      && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
19627 			      && call_used_regs[STATIC_CHAIN_REGNUM]);
19628   /* Offset to top of frame for frame_reg and sp respectively.  */
19629   HOST_WIDE_INT frame_off = 0;
19630   HOST_WIDE_INT sp_off = 0;
19631 
19632 #ifdef ENABLE_CHECKING
19633   /* Track and check usage of r0, r11, r12.  */
19634   int reg_inuse = using_static_chain_p ? 1 << 11 : 0;
19635 #define START_USE(R) do \
19636   {						\
19637     gcc_assert ((reg_inuse & (1 << (R))) == 0);	\
19638     reg_inuse |= 1 << (R);			\
19639   } while (0)
19640 #define END_USE(R) do \
19641   {						\
19642     gcc_assert ((reg_inuse & (1 << (R))) != 0);	\
19643     reg_inuse &= ~(1 << (R));			\
19644   } while (0)
19645 #define NOT_INUSE(R) do \
19646   {						\
19647     gcc_assert ((reg_inuse & (1 << (R))) == 0);	\
19648   } while (0)
19649 #else
19650 #define START_USE(R) do {} while (0)
19651 #define END_USE(R) do {} while (0)
19652 #define NOT_INUSE(R) do {} while (0)
19653 #endif
19654 
19655   if (flag_stack_usage_info)
19656     current_function_static_stack_size = info->total_size;
19657 
19658   if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK && info->total_size)
19659     rs6000_emit_probe_stack_range (STACK_CHECK_PROTECT, info->total_size);
19660 
19661   if (TARGET_FIX_AND_CONTINUE)
19662     {
19663       /* gdb on darwin arranges to forward a function from the old
19664 	 address by modifying the first 5 instructions of the function
19665 	 to branch to the overriding function.  This is necessary to
19666 	 permit function pointers that point to the old function to
19667 	 actually forward to the new function.  */
19668       emit_insn (gen_nop ());
19669       emit_insn (gen_nop ());
19670       emit_insn (gen_nop ());
19671       emit_insn (gen_nop ());
19672       emit_insn (gen_nop ());
19673     }
19674 
19675   if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
19676     {
19677       reg_mode = V2SImode;
19678       reg_size = 8;
19679     }
19680 
19681   /* Handle world saves specially here.  */
19682   if (WORLD_SAVE_P (info))
19683     {
19684       int i, j, sz;
19685       rtx treg;
19686       rtvec p;
19687       rtx reg0;
19688 
19689       /* save_world expects lr in r0. */
19690       reg0 = gen_rtx_REG (Pmode, 0);
19691       if (info->lr_save_p)
19692 	{
19693 	  insn = emit_move_insn (reg0,
19694 				 gen_rtx_REG (Pmode, LR_REGNO));
19695 	  RTX_FRAME_RELATED_P (insn) = 1;
19696 	}
19697 
19698       /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
19699 	 assumptions about the offsets of various bits of the stack
19700 	 frame.  */
19701       gcc_assert (info->gp_save_offset == -220
19702 		  && info->fp_save_offset == -144
19703 		  && info->lr_save_offset == 8
19704 		  && info->cr_save_offset == 4
19705 		  && info->push_p
19706 		  && info->lr_save_p
19707 		  && (!crtl->calls_eh_return
19708 		      || info->ehrd_offset == -432)
19709 		  && info->vrsave_save_offset == -224
19710 		  && info->altivec_save_offset == -416);
19711 
19712       treg = gen_rtx_REG (SImode, 11);
19713       emit_move_insn (treg, GEN_INT (-info->total_size));
19714 
19715       /* SAVE_WORLD takes the caller's LR in R0 and the frame size
19716 	 in R11.  It also clobbers R12, so beware!  */
19717 
19718       /* Preserve CR2 for save_world prologues */
19719       sz = 5;
19720       sz += 32 - info->first_gp_reg_save;
19721       sz += 64 - info->first_fp_reg_save;
19722       sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
19723       p = rtvec_alloc (sz);
19724       j = 0;
19725       RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
19726 					    gen_rtx_REG (SImode,
19727 							 LR_REGNO));
19728       RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
19729 					gen_rtx_SYMBOL_REF (Pmode,
19730 							    "*save_world"));
19731       /* We do floats first so that the instruction pattern matches
19732 	 properly.  */
19733       for (i = 0; i < 64 - info->first_fp_reg_save; i++)
19734 	RTVEC_ELT (p, j++)
19735 	  = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
19736 					  ? DFmode : SFmode,
19737 					  info->first_fp_reg_save + i),
19738 			     frame_reg_rtx,
19739 			     info->fp_save_offset + frame_off + 8 * i);
19740       for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
19741 	RTVEC_ELT (p, j++)
19742 	  = gen_frame_store (gen_rtx_REG (V4SImode,
19743 					  info->first_altivec_reg_save + i),
19744 			     frame_reg_rtx,
19745 			     info->altivec_save_offset + frame_off + 16 * i);
19746       for (i = 0; i < 32 - info->first_gp_reg_save; i++)
19747 	RTVEC_ELT (p, j++)
19748 	  = gen_frame_store (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
19749 			     frame_reg_rtx,
19750 			     info->gp_save_offset + frame_off + reg_size * i);
19751 
19752       /* CR register traditionally saved as CR2.  */
19753       RTVEC_ELT (p, j++)
19754 	= gen_frame_store (gen_rtx_REG (SImode, CR2_REGNO),
19755 			   frame_reg_rtx, info->cr_save_offset + frame_off);
19756       /* Explain about use of R0.  */
19757       if (info->lr_save_p)
19758 	RTVEC_ELT (p, j++)
19759 	  = gen_frame_store (reg0,
19760 			     frame_reg_rtx, info->lr_save_offset + frame_off);
19761       /* Explain what happens to the stack pointer.  */
19762       {
19763 	rtx newval = gen_rtx_PLUS (Pmode, sp_reg_rtx, treg);
19764 	RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, sp_reg_rtx, newval);
19765       }
19766 
19767       insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
19768       rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
19769 			    treg, GEN_INT (-info->total_size));
19770       sp_off = frame_off = info->total_size;
19771     }
19772 
19773   strategy = info->savres_strategy;
19774 
19775   /* For V.4, update stack before we do any saving and set back pointer.  */
19776   if (! WORLD_SAVE_P (info)
19777       && info->push_p
19778       && (DEFAULT_ABI == ABI_V4
19779 	  || crtl->calls_eh_return))
19780     {
19781       bool need_r11 = (TARGET_SPE
19782 		       ? (!(strategy & SAVE_INLINE_GPRS)
19783 			  && info->spe_64bit_regs_used == 0)
19784 		       : (!(strategy & SAVE_INLINE_FPRS)
19785 			  || !(strategy & SAVE_INLINE_GPRS)
19786 			  || !(strategy & SAVE_INLINE_VRS)));
19787       int ptr_regno = -1;
19788       rtx ptr_reg = NULL_RTX;
19789       int ptr_off = 0;
19790 
19791       if (info->total_size < 32767)
19792 	frame_off = info->total_size;
19793       else if (need_r11)
19794 	ptr_regno = 11;
19795       else if (info->cr_save_p
19796 	       || info->lr_save_p
19797 	       || info->first_fp_reg_save < 64
19798 	       || info->first_gp_reg_save < 32
19799 	       || info->altivec_size != 0
19800 	       || info->vrsave_mask != 0
19801 	       || crtl->calls_eh_return)
19802 	ptr_regno = 12;
19803       else
19804 	{
19805 	  /* The prologue won't be saving any regs so there is no need
19806 	     to set up a frame register to access any frame save area.
19807 	     We also won't be using frame_off anywhere below, but set
19808 	     the correct value anyway to protect against future
19809 	     changes to this function.  */
19810 	  frame_off = info->total_size;
19811 	}
19812       if (ptr_regno != -1)
19813 	{
19814 	  /* Set up the frame offset to that needed by the first
19815 	     out-of-line save function.  */
19816 	  START_USE (ptr_regno);
19817 	  ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
19818 	  frame_reg_rtx = ptr_reg;
19819 	  if (!(strategy & SAVE_INLINE_FPRS) && info->fp_size != 0)
19820 	    gcc_checking_assert (info->fp_save_offset + info->fp_size == 0);
19821 	  else if (!(strategy & SAVE_INLINE_GPRS) && info->first_gp_reg_save < 32)
19822 	    ptr_off = info->gp_save_offset + info->gp_size;
19823 	  else if (!(strategy & SAVE_INLINE_VRS) && info->altivec_size != 0)
19824 	    ptr_off = info->altivec_save_offset + info->altivec_size;
19825 	  frame_off = -ptr_off;
19826 	}
19827       rs6000_emit_allocate_stack (info->total_size, ptr_reg, ptr_off);
19828       sp_off = info->total_size;
19829       if (frame_reg_rtx != sp_reg_rtx)
19830 	rs6000_emit_stack_tie (frame_reg_rtx, false);
19831     }
19832 
19833   /* If we use the link register, get it into r0.  */
19834   if (!WORLD_SAVE_P (info) && info->lr_save_p)
19835     {
19836       rtx addr, reg, mem;
19837 
19838       reg = gen_rtx_REG (Pmode, 0);
19839       START_USE (0);
19840       insn = emit_move_insn (reg, gen_rtx_REG (Pmode, LR_REGNO));
19841       RTX_FRAME_RELATED_P (insn) = 1;
19842 
19843       if (!(strategy & (SAVE_NOINLINE_GPRS_SAVES_LR
19844 			| SAVE_NOINLINE_FPRS_SAVES_LR)))
19845 	{
19846 	  addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
19847 			       GEN_INT (info->lr_save_offset + frame_off));
19848 	  mem = gen_rtx_MEM (Pmode, addr);
19849 	  /* This should not be of rs6000_sr_alias_set, because of
19850 	     __builtin_return_address.  */
19851 
19852 	  insn = emit_move_insn (mem, reg);
19853 	  rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
19854 				NULL_RTX, NULL_RTX);
19855 	  END_USE (0);
19856 	}
19857     }
19858 
19859   /* If we need to save CR, put it into r12 or r11.  Choose r12 except when
19860      r12 will be needed by out-of-line gpr restore.  */
19861   cr_save_regno = (DEFAULT_ABI == ABI_AIX
19862 		   && !(strategy & (SAVE_INLINE_GPRS
19863 				    | SAVE_NOINLINE_GPRS_SAVES_LR))
19864 		   ? 11 : 12);
19865   if (!WORLD_SAVE_P (info)
19866       && info->cr_save_p
19867       && REGNO (frame_reg_rtx) != cr_save_regno
19868       && !(using_static_chain_p && cr_save_regno == 11))
19869     {
19870       rtx set;
19871 
19872       cr_save_rtx = gen_rtx_REG (SImode, cr_save_regno);
19873       START_USE (cr_save_regno);
19874       insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
19875       RTX_FRAME_RELATED_P (insn) = 1;
19876       /* Now, there's no way that dwarf2out_frame_debug_expr is going
19877 	 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
19878 	 But that's OK.  All we have to do is specify that _one_ condition
19879 	 code register is saved in this stack slot.  The thrower's epilogue
19880 	 will then restore all the call-saved registers.
19881 	 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux.  */
19882       set = gen_rtx_SET (VOIDmode, cr_save_rtx,
19883 			 gen_rtx_REG (SImode, CR2_REGNO));
19884       add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
19885     }
19886 
19887   /* Do any required saving of fpr's.  If only one or two to save, do
19888      it ourselves.  Otherwise, call function.  */
19889   if (!WORLD_SAVE_P (info) && (strategy & SAVE_INLINE_FPRS))
19890     {
19891       int i;
19892       for (i = 0; i < 64 - info->first_fp_reg_save; i++)
19893 	if (save_reg_p (info->first_fp_reg_save + i))
19894 	  emit_frame_save (frame_reg_rtx,
19895 			   (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
19896 			    ? DFmode : SFmode),
19897 			   info->first_fp_reg_save + i,
19898 			   info->fp_save_offset + frame_off + 8 * i,
19899 			   sp_off - frame_off);
19900     }
19901   else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
19902     {
19903       bool lr = (strategy & SAVE_NOINLINE_FPRS_SAVES_LR) != 0;
19904       int sel = SAVRES_SAVE | SAVRES_FPR | (lr ? SAVRES_LR : 0);
19905       unsigned ptr_regno = ptr_regno_for_savres (sel);
19906       rtx ptr_reg = frame_reg_rtx;
19907 
19908       if (REGNO (frame_reg_rtx) == ptr_regno)
19909 	gcc_checking_assert (frame_off == 0);
19910       else
19911 	{
19912 	  ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
19913 	  NOT_INUSE (ptr_regno);
19914 	  emit_insn (gen_add3_insn (ptr_reg,
19915 				    frame_reg_rtx, GEN_INT (frame_off)));
19916 	}
19917       insn = rs6000_emit_savres_rtx (info, ptr_reg,
19918 				     info->fp_save_offset,
19919 				     info->lr_save_offset,
19920 				     DFmode, sel);
19921       rs6000_frame_related (insn, ptr_reg, sp_off,
19922 			    NULL_RTX, NULL_RTX);
19923       if (lr)
19924 	END_USE (0);
19925     }
19926 
19927   /* Save GPRs.  This is done as a PARALLEL if we are using
19928      the store-multiple instructions.  */
19929   if (!WORLD_SAVE_P (info)
19930       && TARGET_SPE_ABI
19931       && info->spe_64bit_regs_used != 0
19932       && info->first_gp_reg_save != 32)
19933     {
19934       int i;
19935       rtx spe_save_area_ptr;
19936       HOST_WIDE_INT save_off;
19937       int ool_adjust = 0;
19938 
19939       /* Determine whether we can address all of the registers that need
19940 	 to be saved with an offset from frame_reg_rtx that fits in
19941 	 the small const field for SPE memory instructions.  */
19942       int spe_regs_addressable
19943 	= (SPE_CONST_OFFSET_OK (info->spe_gp_save_offset + frame_off
19944 				+ reg_size * (32 - info->first_gp_reg_save - 1))
19945 	   && (strategy & SAVE_INLINE_GPRS));
19946 
19947       if (spe_regs_addressable)
19948 	{
19949 	  spe_save_area_ptr = frame_reg_rtx;
19950 	  save_off = frame_off;
19951 	}
19952       else
19953 	{
19954 	  /* Make r11 point to the start of the SPE save area.  We need
19955 	     to be careful here if r11 is holding the static chain.  If
19956 	     it is, then temporarily save it in r0.  */
19957 	  HOST_WIDE_INT offset;
19958 
19959 	  if (!(strategy & SAVE_INLINE_GPRS))
19960 	    ool_adjust = 8 * (info->first_gp_reg_save
19961 			      - (FIRST_SAVRES_REGISTER + 1));
19962 	  offset = info->spe_gp_save_offset + frame_off - ool_adjust;
19963 	  spe_save_area_ptr = gen_rtx_REG (Pmode, 11);
19964 	  save_off = frame_off - offset;
19965 
19966 	  if (using_static_chain_p)
19967 	    {
19968 	      rtx r0 = gen_rtx_REG (Pmode, 0);
19969 
19970 	      START_USE (0);
19971 	      gcc_assert (info->first_gp_reg_save > 11);
19972 
19973 	      emit_move_insn (r0, spe_save_area_ptr);
19974 	    }
19975 	  else if (REGNO (frame_reg_rtx) != 11)
19976 	    START_USE (11);
19977 
19978 	  emit_insn (gen_addsi3 (spe_save_area_ptr,
19979 				 frame_reg_rtx, GEN_INT (offset)));
19980 	  if (!using_static_chain_p && REGNO (frame_reg_rtx) == 11)
19981 	    frame_off = -info->spe_gp_save_offset + ool_adjust;
19982 	}
19983 
19984       if ((strategy & SAVE_INLINE_GPRS))
19985 	{
19986 	  for (i = 0; i < 32 - info->first_gp_reg_save; i++)
19987 	    if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
19988 	      emit_frame_save (spe_save_area_ptr, reg_mode,
19989 			       info->first_gp_reg_save + i,
19990 			       (info->spe_gp_save_offset + save_off
19991 				+ reg_size * i),
19992 			       sp_off - save_off);
19993 	}
19994       else
19995 	{
19996 	  insn = rs6000_emit_savres_rtx (info, spe_save_area_ptr,
19997 					 info->spe_gp_save_offset + save_off,
19998 					 0, reg_mode,
19999 					 SAVRES_SAVE | SAVRES_GPR);
20000 
20001 	  rs6000_frame_related (insn, spe_save_area_ptr, sp_off - save_off,
20002 				NULL_RTX, NULL_RTX);
20003 	}
20004 
20005       /* Move the static chain pointer back.  */
20006       if (!spe_regs_addressable)
20007 	{
20008 	  if (using_static_chain_p)
20009 	    {
20010 	      emit_move_insn (spe_save_area_ptr, gen_rtx_REG (Pmode, 0));
20011 	      END_USE (0);
20012 	    }
20013 	  else if (REGNO (frame_reg_rtx) != 11)
20014 	    END_USE (11);
20015 	}
20016     }
20017   else if (!WORLD_SAVE_P (info) && !(strategy & SAVE_INLINE_GPRS))
20018     {
20019       bool lr = (strategy & SAVE_NOINLINE_GPRS_SAVES_LR) != 0;
20020       int sel = SAVRES_SAVE | SAVRES_GPR | (lr ? SAVRES_LR : 0);
20021       unsigned ptr_regno = ptr_regno_for_savres (sel);
20022       rtx ptr_reg = frame_reg_rtx;
20023       bool ptr_set_up = REGNO (ptr_reg) == ptr_regno;
20024       int end_save = info->gp_save_offset + info->gp_size;
20025       int ptr_off;
20026 
20027       if (!ptr_set_up)
20028 	ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
20029 
20030       /* Need to adjust r11 (r12) if we saved any FPRs.  */
20031       if (end_save + frame_off != 0)
20032 	{
20033 	  rtx offset = GEN_INT (end_save + frame_off);
20034 
20035 	  if (ptr_set_up)
20036 	    frame_off = -end_save;
20037 	  else
20038 	    NOT_INUSE (ptr_regno);
20039 	  emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
20040 	}
20041       else if (!ptr_set_up)
20042 	{
20043 	  NOT_INUSE (ptr_regno);
20044 	  emit_move_insn (ptr_reg, frame_reg_rtx);
20045 	}
20046       ptr_off = -end_save;
20047       insn = rs6000_emit_savres_rtx (info, ptr_reg,
20048 				     info->gp_save_offset + ptr_off,
20049 				     info->lr_save_offset + ptr_off,
20050 				     reg_mode, sel);
20051       rs6000_frame_related (insn, ptr_reg, sp_off - ptr_off,
20052 			    NULL_RTX, NULL_RTX);
20053       if (lr)
20054 	END_USE (0);
20055     }
20056   else if (!WORLD_SAVE_P (info) && (strategy & SAVRES_MULTIPLE))
20057     {
20058       rtvec p;
20059       int i;
20060       p = rtvec_alloc (32 - info->first_gp_reg_save);
20061       for (i = 0; i < 32 - info->first_gp_reg_save; i++)
20062 	RTVEC_ELT (p, i)
20063 	  = gen_frame_store (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
20064 			     frame_reg_rtx,
20065 			     info->gp_save_offset + frame_off + reg_size * i);
20066       insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
20067       rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
20068 			    NULL_RTX, NULL_RTX);
20069     }
20070   else if (!WORLD_SAVE_P (info))
20071     {
20072       int i;
20073       for (i = 0; i < 32 - info->first_gp_reg_save; i++)
20074 	if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
20075 	  emit_frame_save (frame_reg_rtx, reg_mode,
20076 			   info->first_gp_reg_save + i,
20077 			   info->gp_save_offset + frame_off + reg_size * i,
20078 			   sp_off - frame_off);
20079     }
20080 
20081   if (crtl->calls_eh_return)
20082     {
20083       unsigned int i;
20084       rtvec p;
20085 
20086       for (i = 0; ; ++i)
20087 	{
20088 	  unsigned int regno = EH_RETURN_DATA_REGNO (i);
20089 	  if (regno == INVALID_REGNUM)
20090 	    break;
20091 	}
20092 
20093       p = rtvec_alloc (i);
20094 
20095       for (i = 0; ; ++i)
20096 	{
20097 	  unsigned int regno = EH_RETURN_DATA_REGNO (i);
20098 	  if (regno == INVALID_REGNUM)
20099 	    break;
20100 
20101 	  insn
20102 	    = gen_frame_store (gen_rtx_REG (reg_mode, regno),
20103 			       sp_reg_rtx,
20104 			       info->ehrd_offset + sp_off + reg_size * (int) i);
20105 	  RTVEC_ELT (p, i) = insn;
20106 	  RTX_FRAME_RELATED_P (insn) = 1;
20107 	}
20108 
20109       insn = emit_insn (gen_blockage ());
20110       RTX_FRAME_RELATED_P (insn) = 1;
20111       add_reg_note (insn, REG_FRAME_RELATED_EXPR, gen_rtx_PARALLEL (VOIDmode, p));
20112     }
20113 
20114   /* In AIX ABI we need to make sure r2 is really saved.  */
20115   if (TARGET_AIX && crtl->calls_eh_return)
20116     {
20117       rtx tmp_reg, tmp_reg_si, hi, lo, compare_result, toc_save_done, jump;
20118       rtx save_insn, join_insn, note;
20119       long toc_restore_insn;
20120 
20121       tmp_reg = gen_rtx_REG (Pmode, 11);
20122       tmp_reg_si = gen_rtx_REG (SImode, 11);
20123       if (using_static_chain_p)
20124 	{
20125 	  START_USE (0);
20126 	  emit_move_insn (gen_rtx_REG (Pmode, 0), tmp_reg);
20127 	}
20128       else
20129 	START_USE (11);
20130       emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, LR_REGNO));
20131       /* Peek at instruction to which this function returns.  If it's
20132 	 restoring r2, then we know we've already saved r2.  We can't
20133 	 unconditionally save r2 because the value we have will already
20134 	 be updated if we arrived at this function via a plt call or
20135 	 toc adjusting stub.  */
20136       emit_move_insn (tmp_reg_si, gen_rtx_MEM (SImode, tmp_reg));
20137       toc_restore_insn = TARGET_32BIT ? 0x80410014 : 0xE8410028;
20138       hi = gen_int_mode (toc_restore_insn & ~0xffff, SImode);
20139       emit_insn (gen_xorsi3 (tmp_reg_si, tmp_reg_si, hi));
20140       compare_result = gen_rtx_REG (CCUNSmode, CR0_REGNO);
20141       validate_condition_mode (EQ, CCUNSmode);
20142       lo = gen_int_mode (toc_restore_insn & 0xffff, SImode);
20143       emit_insn (gen_rtx_SET (VOIDmode, compare_result,
20144 			      gen_rtx_COMPARE (CCUNSmode, tmp_reg_si, lo)));
20145       toc_save_done = gen_label_rtx ();
20146       jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
20147 				   gen_rtx_EQ (VOIDmode, compare_result,
20148 					       const0_rtx),
20149 				   gen_rtx_LABEL_REF (VOIDmode, toc_save_done),
20150 				   pc_rtx);
20151       jump = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, jump));
20152       JUMP_LABEL (jump) = toc_save_done;
20153       LABEL_NUSES (toc_save_done) += 1;
20154 
20155       save_insn = emit_frame_save (frame_reg_rtx, reg_mode,
20156 				   TOC_REGNUM, frame_off + 5 * reg_size,
20157 				   sp_off - frame_off);
20158 
20159       emit_label (toc_save_done);
20160 
20161       /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
20162 	 have a CFG that has different saves along different paths.
20163 	 Move the note to a dummy blockage insn, which describes that
20164 	 R2 is unconditionally saved after the label.  */
20165       /* ??? An alternate representation might be a special insn pattern
20166 	 containing both the branch and the store.  That might let the
20167 	 code that minimizes the number of DW_CFA_advance opcodes better
20168 	 freedom in placing the annotations.  */
20169       note = find_reg_note (save_insn, REG_FRAME_RELATED_EXPR, NULL);
20170       if (note)
20171 	remove_note (save_insn, note);
20172       else
20173 	note = alloc_reg_note (REG_FRAME_RELATED_EXPR,
20174 			       copy_rtx (PATTERN (save_insn)), NULL_RTX);
20175       RTX_FRAME_RELATED_P (save_insn) = 0;
20176 
20177       join_insn = emit_insn (gen_blockage ());
20178       REG_NOTES (join_insn) = note;
20179       RTX_FRAME_RELATED_P (join_insn) = 1;
20180 
20181       if (using_static_chain_p)
20182 	{
20183 	  emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, 0));
20184 	  END_USE (0);
20185 	}
20186       else
20187 	END_USE (11);
20188     }
20189 
20190   /* Save CR if we use any that must be preserved.  */
20191   if (!WORLD_SAVE_P (info) && info->cr_save_p)
20192     {
20193       rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
20194 			       GEN_INT (info->cr_save_offset + frame_off));
20195       rtx mem = gen_frame_mem (SImode, addr);
20196       /* See the large comment above about why CR2_REGNO is used.  */
20197       rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
20198 
20199       /* If we didn't copy cr before, do so now using r0.  */
20200       if (cr_save_rtx == NULL_RTX)
20201 	{
20202 	  rtx set;
20203 
20204 	  START_USE (0);
20205 	  cr_save_rtx = gen_rtx_REG (SImode, 0);
20206 	  insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
20207 	  RTX_FRAME_RELATED_P (insn) = 1;
20208 	  set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
20209 	  add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
20210 	}
20211       insn = emit_move_insn (mem, cr_save_rtx);
20212       END_USE (REGNO (cr_save_rtx));
20213 
20214       rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
20215 			    NULL_RTX, NULL_RTX);
20216     }
20217 
20218   /* Update stack and set back pointer unless this is V.4,
20219      for which it was done previously.  */
20220   if (!WORLD_SAVE_P (info) && info->push_p
20221       && !(DEFAULT_ABI == ABI_V4 || crtl->calls_eh_return))
20222     {
20223       rtx ptr_reg = NULL;
20224       int ptr_off = 0;
20225 
20226       /* If saving altivec regs we need to be able to address all save
20227 	 locations using a 16-bit offset.  */
20228       if ((strategy & SAVE_INLINE_VRS) == 0
20229 	  || (info->altivec_size != 0
20230 	      && (info->altivec_save_offset + info->altivec_size - 16
20231 		  + info->total_size - frame_off) > 32767)
20232 	  || (info->vrsave_size != 0
20233 	      && (info->vrsave_save_offset
20234 		  + info->total_size - frame_off) > 32767))
20235 	{
20236 	  int sel = SAVRES_SAVE | SAVRES_VR;
20237 	  unsigned ptr_regno = ptr_regno_for_savres (sel);
20238 
20239 	  if (using_static_chain_p
20240 	      && ptr_regno == STATIC_CHAIN_REGNUM)
20241 	    ptr_regno = 12;
20242 	  if (REGNO (frame_reg_rtx) != ptr_regno)
20243 	    START_USE (ptr_regno);
20244 	  ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
20245 	  frame_reg_rtx = ptr_reg;
20246 	  ptr_off = info->altivec_save_offset + info->altivec_size;
20247 	  frame_off = -ptr_off;
20248 	}
20249       else if (REGNO (frame_reg_rtx) == 1)
20250 	frame_off = info->total_size;
20251       rs6000_emit_allocate_stack (info->total_size, ptr_reg, ptr_off);
20252       sp_off = info->total_size;
20253       if (frame_reg_rtx != sp_reg_rtx)
20254 	rs6000_emit_stack_tie (frame_reg_rtx, false);
20255     }
20256 
20257   /* Set frame pointer, if needed.  */
20258   if (frame_pointer_needed)
20259     {
20260       insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
20261 			     sp_reg_rtx);
20262       RTX_FRAME_RELATED_P (insn) = 1;
20263     }
20264 
20265   /* Save AltiVec registers if needed.  Save here because the red zone does
20266      not always include AltiVec registers.  */
20267   if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI
20268       && info->altivec_size != 0 && (strategy & SAVE_INLINE_VRS) == 0)
20269     {
20270       int end_save = info->altivec_save_offset + info->altivec_size;
20271       int ptr_off;
20272       /* Oddly, the vector save/restore functions point r0 at the end
20273 	 of the save area, then use r11 or r12 to load offsets for
20274 	 [reg+reg] addressing.  */
20275       rtx ptr_reg = gen_rtx_REG (Pmode, 0);
20276       int scratch_regno = ptr_regno_for_savres (SAVRES_SAVE | SAVRES_VR);
20277       rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
20278 
20279       gcc_checking_assert (scratch_regno == 11 || scratch_regno == 12);
20280       NOT_INUSE (0);
20281       if (end_save + frame_off != 0)
20282 	{
20283 	  rtx offset = GEN_INT (end_save + frame_off);
20284 
20285 	  emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
20286 	}
20287       else
20288 	emit_move_insn (ptr_reg, frame_reg_rtx);
20289 
20290       ptr_off = -end_save;
20291       insn = rs6000_emit_savres_rtx (info, scratch_reg,
20292 				     info->altivec_save_offset + ptr_off,
20293 				     0, V4SImode, SAVRES_SAVE | SAVRES_VR);
20294       rs6000_frame_related (insn, scratch_reg, sp_off - ptr_off,
20295 			    NULL_RTX, NULL_RTX);
20296       if (REGNO (frame_reg_rtx) == REGNO (scratch_reg))
20297 	{
20298 	  /* The oddity mentioned above clobbered our frame reg.  */
20299 	  emit_move_insn (frame_reg_rtx, ptr_reg);
20300 	  frame_off = ptr_off;
20301 	}
20302     }
20303   else if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI
20304 	   && info->altivec_size != 0)
20305     {
20306       int i;
20307 
20308       for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
20309 	if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
20310 	  {
20311 	    rtx areg, savereg, mem;
20312 	    int offset;
20313 
20314 	    offset = (info->altivec_save_offset + frame_off
20315 		      + 16 * (i - info->first_altivec_reg_save));
20316 
20317 	    savereg = gen_rtx_REG (V4SImode, i);
20318 
20319 	    NOT_INUSE (0);
20320 	    areg = gen_rtx_REG (Pmode, 0);
20321 	    emit_move_insn (areg, GEN_INT (offset));
20322 
20323 	    /* AltiVec addressing mode is [reg+reg].  */
20324 	    mem = gen_frame_mem (V4SImode,
20325 				 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
20326 
20327 	    insn = emit_move_insn (mem, savereg);
20328 
20329 	    rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
20330 				  areg, GEN_INT (offset));
20331 	  }
20332     }
20333 
20334   /* VRSAVE is a bit vector representing which AltiVec registers
20335      are used.  The OS uses this to determine which vector
20336      registers to save on a context switch.  We need to save
20337      VRSAVE on the stack frame, add whatever AltiVec registers we
20338      used in this function, and do the corresponding magic in the
20339      epilogue.  */
20340 
20341   if (!WORLD_SAVE_P (info)
20342       && TARGET_ALTIVEC
20343       && TARGET_ALTIVEC_VRSAVE
20344       && info->vrsave_mask != 0)
20345     {
20346       rtx reg, vrsave;
20347       int offset;
20348       int save_regno;
20349 
20350       /* Get VRSAVE onto a GPR.  Note that ABI_V4 and ABI_DARWIN might
20351 	 be using r12 as frame_reg_rtx and r11 as the static chain
20352 	 pointer for nested functions.  */
20353       save_regno = 12;
20354       if (DEFAULT_ABI == ABI_AIX && !using_static_chain_p)
20355 	save_regno = 11;
20356       else if (REGNO (frame_reg_rtx) == 12)
20357 	{
20358 	  save_regno = 11;
20359 	  if (using_static_chain_p)
20360 	    save_regno = 0;
20361 	}
20362 
20363       NOT_INUSE (save_regno);
20364       reg = gen_rtx_REG (SImode, save_regno);
20365       vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
20366       if (TARGET_MACHO)
20367 	emit_insn (gen_get_vrsave_internal (reg));
20368       else
20369 	emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
20370 
20371       /* Save VRSAVE.  */
20372       offset = info->vrsave_save_offset + frame_off;
20373       insn = emit_insn (gen_frame_store (reg, frame_reg_rtx, offset));
20374 
20375       /* Include the registers in the mask.  */
20376       emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
20377 
20378       insn = emit_insn (generate_set_vrsave (reg, info, 0));
20379     }
20380 
20381   /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up.  */
20382   if (!TARGET_SINGLE_PIC_BASE
20383       && ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
20384 	  || (DEFAULT_ABI == ABI_V4
20385 	      && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
20386 	      && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))))
20387     {
20388       /* If emit_load_toc_table will use the link register, we need to save
20389 	 it.  We use R12 for this purpose because emit_load_toc_table
20390 	 can use register 0.  This allows us to use a plain 'blr' to return
20391 	 from the procedure more often.  */
20392       int save_LR_around_toc_setup = (TARGET_ELF
20393 				      && DEFAULT_ABI != ABI_AIX
20394 				      && flag_pic
20395 				      && ! info->lr_save_p
20396 				      && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
20397       if (save_LR_around_toc_setup)
20398 	{
20399 	  rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
20400 	  rtx tmp = gen_rtx_REG (Pmode, 12);
20401 
20402 	  insn = emit_move_insn (tmp, lr);
20403 	  RTX_FRAME_RELATED_P (insn) = 1;
20404 
20405 	  rs6000_emit_load_toc_table (TRUE);
20406 
20407 	  insn = emit_move_insn (lr, tmp);
20408 	  add_reg_note (insn, REG_CFA_RESTORE, lr);
20409 	  RTX_FRAME_RELATED_P (insn) = 1;
20410 	}
20411       else
20412 	rs6000_emit_load_toc_table (TRUE);
20413     }
20414 
20415 #if TARGET_MACHO
20416   if (!TARGET_SINGLE_PIC_BASE
20417       && DEFAULT_ABI == ABI_DARWIN
20418       && flag_pic && crtl->uses_pic_offset_table)
20419     {
20420       rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
20421       rtx src = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
20422 
20423       /* Save and restore LR locally around this call (in R0).  */
20424       if (!info->lr_save_p)
20425 	emit_move_insn (gen_rtx_REG (Pmode, 0), lr);
20426 
20427       emit_insn (gen_load_macho_picbase (src));
20428 
20429       emit_move_insn (gen_rtx_REG (Pmode,
20430 				   RS6000_PIC_OFFSET_TABLE_REGNUM),
20431 		      lr);
20432 
20433       if (!info->lr_save_p)
20434 	emit_move_insn (lr, gen_rtx_REG (Pmode, 0));
20435     }
20436 #endif
20437 
20438   /* If we need to, save the TOC register after doing the stack setup.
20439      Do not emit eh frame info for this save.  The unwinder wants info,
20440      conceptually attached to instructions in this function, about
20441      register values in the caller of this function.  This R2 may have
20442      already been changed from the value in the caller.
20443      We don't attempt to write accurate DWARF EH frame info for R2
20444      because code emitted by gcc for a (non-pointer) function call
20445      doesn't save and restore R2.  Instead, R2 is managed out-of-line
20446      by a linker generated plt call stub when the function resides in
20447      a shared library.  This behaviour is costly to describe in DWARF,
20448      both in terms of the size of DWARF info and the time taken in the
20449      unwinder to interpret it.  R2 changes, apart from the
20450      calls_eh_return case earlier in this function, are handled by
20451      linux-unwind.h frob_update_context.  */
20452   if (rs6000_save_toc_in_prologue_p ())
20453     {
20454       rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM);
20455       emit_insn (gen_frame_store (reg, sp_reg_rtx, 5 * reg_size));
20456     }
20457 }
20458 
20459 /* Write function prologue.  */
20460 
20461 static void
rs6000_output_function_prologue(FILE * file,HOST_WIDE_INT size ATTRIBUTE_UNUSED)20462 rs6000_output_function_prologue (FILE *file,
20463 				 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
20464 {
20465   rs6000_stack_t *info = rs6000_stack_info ();
20466 
20467   if (TARGET_DEBUG_STACK)
20468     debug_stack_info (info);
20469 
20470   /* Write .extern for any function we will call to save and restore
20471      fp values.  */
20472   if (info->first_fp_reg_save < 64
20473       && !TARGET_MACHO
20474       && !TARGET_ELF)
20475     {
20476       char *name;
20477       int regno = info->first_fp_reg_save - 32;
20478 
20479       if ((info->savres_strategy & SAVE_INLINE_FPRS) == 0)
20480 	{
20481 	  bool lr = (info->savres_strategy & SAVE_NOINLINE_FPRS_SAVES_LR) != 0;
20482 	  int sel = SAVRES_SAVE | SAVRES_FPR | (lr ? SAVRES_LR : 0);
20483 	  name = rs6000_savres_routine_name (info, regno, sel);
20484 	  fprintf (file, "\t.extern %s\n", name);
20485 	}
20486       if ((info->savres_strategy & REST_INLINE_FPRS) == 0)
20487 	{
20488 	  bool lr = (info->savres_strategy
20489 		     & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
20490 	  int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
20491 	  name = rs6000_savres_routine_name (info, regno, sel);
20492 	  fprintf (file, "\t.extern %s\n", name);
20493 	}
20494     }
20495 
20496   rs6000_pic_labelno++;
20497 }
20498 
20499 /* Non-zero if vmx regs are restored before the frame pop, zero if
20500    we restore after the pop when possible.  */
20501 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
20502 
20503 /* Restoring cr is a two step process: loading a reg from the frame
20504    save, then moving the reg to cr.  For ABI_V4 we must let the
20505    unwinder know that the stack location is no longer valid at or
20506    before the stack deallocation, but we can't emit a cfa_restore for
20507    cr at the stack deallocation like we do for other registers.
20508    The trouble is that it is possible for the move to cr to be
20509    scheduled after the stack deallocation.  So say exactly where cr
20510    is located on each of the two insns.  */
20511 
20512 static rtx
load_cr_save(int regno,rtx frame_reg_rtx,int offset,bool exit_func)20513 load_cr_save (int regno, rtx frame_reg_rtx, int offset, bool exit_func)
20514 {
20515   rtx mem = gen_frame_mem_offset (SImode, frame_reg_rtx, offset);
20516   rtx reg = gen_rtx_REG (SImode, regno);
20517   rtx insn = emit_move_insn (reg, mem);
20518 
20519   if (!exit_func && DEFAULT_ABI == ABI_V4)
20520     {
20521       rtx cr = gen_rtx_REG (SImode, CR2_REGNO);
20522       rtx set = gen_rtx_SET (VOIDmode, reg, cr);
20523 
20524       add_reg_note (insn, REG_CFA_REGISTER, set);
20525       RTX_FRAME_RELATED_P (insn) = 1;
20526     }
20527   return reg;
20528 }
20529 
20530 /* Reload CR from REG.  */
20531 
20532 static void
restore_saved_cr(rtx reg,int using_mfcr_multiple,bool exit_func)20533 restore_saved_cr (rtx reg, int using_mfcr_multiple, bool exit_func)
20534 {
20535   int count = 0;
20536   int i;
20537 
20538   if (using_mfcr_multiple)
20539     {
20540       for (i = 0; i < 8; i++)
20541 	if (save_reg_p (CR0_REGNO + i))
20542 	  count++;
20543       gcc_assert (count);
20544     }
20545 
20546   if (using_mfcr_multiple && count > 1)
20547     {
20548       rtvec p;
20549       int ndx;
20550 
20551       p = rtvec_alloc (count);
20552 
20553       ndx = 0;
20554       for (i = 0; i < 8; i++)
20555 	if (save_reg_p (CR0_REGNO + i))
20556 	  {
20557 	    rtvec r = rtvec_alloc (2);
20558 	    RTVEC_ELT (r, 0) = reg;
20559 	    RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
20560 	    RTVEC_ELT (p, ndx) =
20561 	      gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i),
20562 			   gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
20563 	    ndx++;
20564 	  }
20565       emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
20566       gcc_assert (ndx == count);
20567     }
20568   else
20569     for (i = 0; i < 8; i++)
20570       if (save_reg_p (CR0_REGNO + i))
20571 	emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode, CR0_REGNO + i),
20572 					reg));
20573 
20574   if (!exit_func && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap))
20575     {
20576       rtx insn = get_last_insn ();
20577       rtx cr = gen_rtx_REG (SImode, CR2_REGNO);
20578 
20579       add_reg_note (insn, REG_CFA_RESTORE, cr);
20580       RTX_FRAME_RELATED_P (insn) = 1;
20581     }
20582 }
20583 
20584 /* Like cr, the move to lr instruction can be scheduled after the
20585    stack deallocation, but unlike cr, its stack frame save is still
20586    valid.  So we only need to emit the cfa_restore on the correct
20587    instruction.  */
20588 
20589 static void
load_lr_save(int regno,rtx frame_reg_rtx,int offset)20590 load_lr_save (int regno, rtx frame_reg_rtx, int offset)
20591 {
20592   rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx, offset);
20593   rtx reg = gen_rtx_REG (Pmode, regno);
20594 
20595   emit_move_insn (reg, mem);
20596 }
20597 
20598 static void
restore_saved_lr(int regno,bool exit_func)20599 restore_saved_lr (int regno, bool exit_func)
20600 {
20601   rtx reg = gen_rtx_REG (Pmode, regno);
20602   rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
20603   rtx insn = emit_move_insn (lr, reg);
20604 
20605   if (!exit_func && flag_shrink_wrap)
20606     {
20607       add_reg_note (insn, REG_CFA_RESTORE, lr);
20608       RTX_FRAME_RELATED_P (insn) = 1;
20609     }
20610 }
20611 
20612 static rtx
add_crlr_cfa_restore(const rs6000_stack_t * info,rtx cfa_restores)20613 add_crlr_cfa_restore (const rs6000_stack_t *info, rtx cfa_restores)
20614 {
20615   if (info->cr_save_p)
20616     cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
20617 				   gen_rtx_REG (SImode, CR2_REGNO),
20618 				   cfa_restores);
20619   if (info->lr_save_p)
20620     cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
20621 				   gen_rtx_REG (Pmode, LR_REGNO),
20622 				   cfa_restores);
20623   return cfa_restores;
20624 }
20625 
20626 /* Return true if OFFSET from stack pointer can be clobbered by signals.
20627    V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
20628    below stack pointer not cloberred by signals.  */
20629 
20630 static inline bool
offset_below_red_zone_p(HOST_WIDE_INT offset)20631 offset_below_red_zone_p (HOST_WIDE_INT offset)
20632 {
20633   return offset < (DEFAULT_ABI == ABI_V4
20634 		   ? 0
20635 		   : TARGET_32BIT ? -220 : -288);
20636 }
20637 
20638 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn.  */
20639 
20640 static void
emit_cfa_restores(rtx cfa_restores)20641 emit_cfa_restores (rtx cfa_restores)
20642 {
20643   rtx insn = get_last_insn ();
20644   rtx *loc = &REG_NOTES (insn);
20645 
20646   while (*loc)
20647     loc = &XEXP (*loc, 1);
20648   *loc = cfa_restores;
20649   RTX_FRAME_RELATED_P (insn) = 1;
20650 }
20651 
20652 /* Emit function epilogue as insns.  */
20653 
20654 void
rs6000_emit_epilogue(int sibcall)20655 rs6000_emit_epilogue (int sibcall)
20656 {
20657   rs6000_stack_t *info;
20658   int restoring_GPRs_inline;
20659   int restoring_FPRs_inline;
20660   int using_load_multiple;
20661   int using_mtcr_multiple;
20662   int use_backchain_to_restore_sp;
20663   int restore_lr;
20664   int strategy;
20665   HOST_WIDE_INT frame_off = 0;
20666   rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
20667   rtx frame_reg_rtx = sp_reg_rtx;
20668   rtx cfa_restores = NULL_RTX;
20669   rtx insn;
20670   rtx cr_save_reg = NULL_RTX;
20671   enum machine_mode reg_mode = Pmode;
20672   int reg_size = TARGET_32BIT ? 4 : 8;
20673   int i;
20674   bool exit_func;
20675   unsigned ptr_regno;
20676 
20677   info = rs6000_stack_info ();
20678 
20679   if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
20680     {
20681       reg_mode = V2SImode;
20682       reg_size = 8;
20683     }
20684 
20685   strategy = info->savres_strategy;
20686   using_load_multiple = strategy & SAVRES_MULTIPLE;
20687   restoring_FPRs_inline = sibcall || (strategy & REST_INLINE_FPRS);
20688   restoring_GPRs_inline = sibcall || (strategy & REST_INLINE_GPRS);
20689   using_mtcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
20690 			 || rs6000_cpu == PROCESSOR_PPC603
20691 			 || rs6000_cpu == PROCESSOR_PPC750
20692 			 || optimize_size);
20693   /* Restore via the backchain when we have a large frame, since this
20694      is more efficient than an addis, addi pair.  The second condition
20695      here will not trigger at the moment;  We don't actually need a
20696      frame pointer for alloca, but the generic parts of the compiler
20697      give us one anyway.  */
20698   use_backchain_to_restore_sp = (info->total_size > 32767 - info->lr_save_offset
20699 				 || (cfun->calls_alloca
20700 				     && !frame_pointer_needed));
20701   restore_lr = (info->lr_save_p
20702 		&& (restoring_FPRs_inline
20703 		    || (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR))
20704 		&& (restoring_GPRs_inline
20705 		    || info->first_fp_reg_save < 64));
20706 
20707   if (WORLD_SAVE_P (info))
20708     {
20709       int i, j;
20710       char rname[30];
20711       const char *alloc_rname;
20712       rtvec p;
20713 
20714       /* eh_rest_world_r10 will return to the location saved in the LR
20715 	 stack slot (which is not likely to be our caller.)
20716 	 Input: R10 -- stack adjustment.  Clobbers R0, R11, R12, R7, R8.
20717 	 rest_world is similar, except any R10 parameter is ignored.
20718 	 The exception-handling stuff that was here in 2.95 is no
20719 	 longer necessary.  */
20720 
20721       p = rtvec_alloc (9
20722 		       + 1
20723 		       + 32 - info->first_gp_reg_save
20724 		       + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
20725 		       + 63 + 1 - info->first_fp_reg_save);
20726 
20727       strcpy (rname, ((crtl->calls_eh_return) ?
20728 		      "*eh_rest_world_r10" : "*rest_world"));
20729       alloc_rname = ggc_strdup (rname);
20730 
20731       j = 0;
20732       RTVEC_ELT (p, j++) = ret_rtx;
20733       RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
20734 					gen_rtx_REG (Pmode,
20735 						     LR_REGNO));
20736       RTVEC_ELT (p, j++)
20737 	= gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
20738       /* The instruction pattern requires a clobber here;
20739 	 it is shared with the restVEC helper. */
20740       RTVEC_ELT (p, j++)
20741 	= gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
20742 
20743       {
20744 	/* CR register traditionally saved as CR2.  */
20745 	rtx reg = gen_rtx_REG (SImode, CR2_REGNO);
20746 	RTVEC_ELT (p, j++)
20747 	  = gen_frame_load (reg, frame_reg_rtx, info->cr_save_offset);
20748 	if (flag_shrink_wrap)
20749 	  {
20750 	    cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
20751 					   gen_rtx_REG (Pmode, LR_REGNO),
20752 					   cfa_restores);
20753 	    cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20754 	  }
20755       }
20756 
20757       for (i = 0; i < 32 - info->first_gp_reg_save; i++)
20758 	{
20759 	  rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
20760 	  RTVEC_ELT (p, j++)
20761 	    = gen_frame_load (reg,
20762 			      frame_reg_rtx, info->gp_save_offset + reg_size * i);
20763 	  if (flag_shrink_wrap)
20764 	    cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20765 	}
20766       for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
20767 	{
20768 	  rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
20769 	  RTVEC_ELT (p, j++)
20770 	    = gen_frame_load (reg,
20771 			      frame_reg_rtx, info->altivec_save_offset + 16 * i);
20772 	  if (flag_shrink_wrap)
20773 	    cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20774 	}
20775       for (i = 0; info->first_fp_reg_save + i <= 63; i++)
20776 	{
20777 	  rtx reg = gen_rtx_REG ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
20778 				  ? DFmode : SFmode),
20779 				 info->first_fp_reg_save + i);
20780 	  RTVEC_ELT (p, j++)
20781 	    = gen_frame_load (reg, frame_reg_rtx, info->fp_save_offset + 8 * i);
20782 	  if (flag_shrink_wrap)
20783 	    cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20784 	}
20785       RTVEC_ELT (p, j++)
20786 	= gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
20787       RTVEC_ELT (p, j++)
20788 	= gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
20789       RTVEC_ELT (p, j++)
20790 	= gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
20791       RTVEC_ELT (p, j++)
20792 	= gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
20793       RTVEC_ELT (p, j++)
20794 	= gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
20795       insn = emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
20796 
20797       if (flag_shrink_wrap)
20798 	{
20799 	  REG_NOTES (insn) = cfa_restores;
20800 	  add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
20801 	  RTX_FRAME_RELATED_P (insn) = 1;
20802 	}
20803       return;
20804     }
20805 
20806   /* frame_reg_rtx + frame_off points to the top of this stack frame.  */
20807   if (info->push_p)
20808     frame_off = info->total_size;
20809 
20810   /* Restore AltiVec registers if we must do so before adjusting the
20811      stack.  */
20812   if (TARGET_ALTIVEC_ABI
20813       && info->altivec_size != 0
20814       && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20815 	  || (DEFAULT_ABI != ABI_V4
20816 	      && offset_below_red_zone_p (info->altivec_save_offset))))
20817     {
20818       int i;
20819       int scratch_regno = ptr_regno_for_savres (SAVRES_VR);
20820 
20821       gcc_checking_assert (scratch_regno == 11 || scratch_regno == 12);
20822       if (use_backchain_to_restore_sp)
20823 	{
20824 	  int frame_regno = 11;
20825 
20826 	  if ((strategy & REST_INLINE_VRS) == 0)
20827 	    {
20828 	      /* Of r11 and r12, select the one not clobbered by an
20829 		 out-of-line restore function for the frame register.  */
20830 	      frame_regno = 11 + 12 - scratch_regno;
20831 	    }
20832 	  frame_reg_rtx = gen_rtx_REG (Pmode, frame_regno);
20833 	  emit_move_insn (frame_reg_rtx,
20834 			  gen_rtx_MEM (Pmode, sp_reg_rtx));
20835 	  frame_off = 0;
20836 	}
20837       else if (frame_pointer_needed)
20838 	frame_reg_rtx = hard_frame_pointer_rtx;
20839 
20840       if ((strategy & REST_INLINE_VRS) == 0)
20841 	{
20842 	  int end_save = info->altivec_save_offset + info->altivec_size;
20843 	  int ptr_off;
20844 	  rtx ptr_reg = gen_rtx_REG (Pmode, 0);
20845 	  rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
20846 
20847 	  if (end_save + frame_off != 0)
20848 	    {
20849 	      rtx offset = GEN_INT (end_save + frame_off);
20850 
20851 	      emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
20852 	    }
20853 	  else
20854 	    emit_move_insn (ptr_reg, frame_reg_rtx);
20855 
20856 	  ptr_off = -end_save;
20857 	  insn = rs6000_emit_savres_rtx (info, scratch_reg,
20858 					 info->altivec_save_offset + ptr_off,
20859 					 0, V4SImode, SAVRES_VR);
20860 	}
20861       else
20862 	{
20863 	  for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
20864 	    if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
20865 	      {
20866 		rtx addr, areg, mem, reg;
20867 
20868 		areg = gen_rtx_REG (Pmode, 0);
20869 		emit_move_insn
20870 		  (areg, GEN_INT (info->altivec_save_offset
20871 				  + frame_off
20872 				  + 16 * (i - info->first_altivec_reg_save)));
20873 
20874 		/* AltiVec addressing mode is [reg+reg].  */
20875 		addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
20876 		mem = gen_frame_mem (V4SImode, addr);
20877 
20878 		reg = gen_rtx_REG (V4SImode, i);
20879 		emit_move_insn (reg, mem);
20880 	      }
20881 	}
20882 
20883       for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
20884 	if (((strategy & REST_INLINE_VRS) == 0
20885 	     || (info->vrsave_mask & ALTIVEC_REG_BIT (i)) != 0)
20886 	    && (flag_shrink_wrap
20887 		|| (offset_below_red_zone_p
20888 		    (info->altivec_save_offset
20889 		     + 16 * (i - info->first_altivec_reg_save)))))
20890 	  {
20891 	    rtx reg = gen_rtx_REG (V4SImode, i);
20892 	    cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20893 	  }
20894     }
20895 
20896   /* Restore VRSAVE if we must do so before adjusting the stack.  */
20897   if (TARGET_ALTIVEC
20898       && TARGET_ALTIVEC_VRSAVE
20899       && info->vrsave_mask != 0
20900       && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20901 	  || (DEFAULT_ABI != ABI_V4
20902 	      && offset_below_red_zone_p (info->vrsave_save_offset))))
20903     {
20904       rtx reg;
20905 
20906       if (frame_reg_rtx == sp_reg_rtx)
20907 	{
20908 	  if (use_backchain_to_restore_sp)
20909 	    {
20910 	      frame_reg_rtx = gen_rtx_REG (Pmode, 11);
20911 	      emit_move_insn (frame_reg_rtx,
20912 			      gen_rtx_MEM (Pmode, sp_reg_rtx));
20913 	      frame_off = 0;
20914 	    }
20915 	  else if (frame_pointer_needed)
20916 	    frame_reg_rtx = hard_frame_pointer_rtx;
20917 	}
20918 
20919       reg = gen_rtx_REG (SImode, 12);
20920       emit_insn (gen_frame_load (reg, frame_reg_rtx,
20921 				 info->vrsave_save_offset + frame_off));
20922 
20923       emit_insn (generate_set_vrsave (reg, info, 1));
20924     }
20925 
20926   insn = NULL_RTX;
20927   /* If we have a large stack frame, restore the old stack pointer
20928      using the backchain.  */
20929   if (use_backchain_to_restore_sp)
20930     {
20931       if (frame_reg_rtx == sp_reg_rtx)
20932 	{
20933 	  /* Under V.4, don't reset the stack pointer until after we're done
20934 	     loading the saved registers.  */
20935 	  if (DEFAULT_ABI == ABI_V4)
20936 	    frame_reg_rtx = gen_rtx_REG (Pmode, 11);
20937 
20938 	  insn = emit_move_insn (frame_reg_rtx,
20939 				 gen_rtx_MEM (Pmode, sp_reg_rtx));
20940 	  frame_off = 0;
20941 	}
20942       else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20943 	       && DEFAULT_ABI == ABI_V4)
20944 	/* frame_reg_rtx has been set up by the altivec restore.  */
20945 	;
20946       else
20947 	{
20948 	  insn = emit_move_insn (sp_reg_rtx, frame_reg_rtx);
20949 	  frame_reg_rtx = sp_reg_rtx;
20950 	}
20951     }
20952   /* If we have a frame pointer, we can restore the old stack pointer
20953      from it.  */
20954   else if (frame_pointer_needed)
20955     {
20956       frame_reg_rtx = sp_reg_rtx;
20957       if (DEFAULT_ABI == ABI_V4)
20958 	frame_reg_rtx = gen_rtx_REG (Pmode, 11);
20959       /* Prevent reordering memory accesses against stack pointer restore.  */
20960       else if (cfun->calls_alloca
20961 	       || offset_below_red_zone_p (-info->total_size))
20962 	rs6000_emit_stack_tie (frame_reg_rtx, true);
20963 
20964       insn = emit_insn (gen_add3_insn (frame_reg_rtx, hard_frame_pointer_rtx,
20965 				       GEN_INT (info->total_size)));
20966       frame_off = 0;
20967     }
20968   else if (info->push_p
20969 	   && DEFAULT_ABI != ABI_V4
20970 	   && !crtl->calls_eh_return)
20971     {
20972       /* Prevent reordering memory accesses against stack pointer restore.  */
20973       if (cfun->calls_alloca
20974 	  || offset_below_red_zone_p (-info->total_size))
20975 	rs6000_emit_stack_tie (frame_reg_rtx, false);
20976       insn = emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx,
20977 				       GEN_INT (info->total_size)));
20978       frame_off = 0;
20979     }
20980   if (insn && frame_reg_rtx == sp_reg_rtx)
20981     {
20982       if (cfa_restores)
20983 	{
20984 	  REG_NOTES (insn) = cfa_restores;
20985 	  cfa_restores = NULL_RTX;
20986 	}
20987       add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
20988       RTX_FRAME_RELATED_P (insn) = 1;
20989     }
20990 
20991   /* Restore AltiVec registers if we have not done so already.  */
20992   if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20993       && TARGET_ALTIVEC_ABI
20994       && info->altivec_size != 0
20995       && (DEFAULT_ABI == ABI_V4
20996 	  || !offset_below_red_zone_p (info->altivec_save_offset)))
20997     {
20998       int i;
20999 
21000       if ((strategy & REST_INLINE_VRS) == 0)
21001 	{
21002 	  int end_save = info->altivec_save_offset + info->altivec_size;
21003 	  int ptr_off;
21004 	  rtx ptr_reg = gen_rtx_REG (Pmode, 0);
21005 	  int scratch_regno = ptr_regno_for_savres (SAVRES_VR);
21006 	  rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
21007 
21008 	  if (end_save + frame_off != 0)
21009 	    {
21010 	      rtx offset = GEN_INT (end_save + frame_off);
21011 
21012 	      emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
21013 	    }
21014 	  else
21015 	    emit_move_insn (ptr_reg, frame_reg_rtx);
21016 
21017 	  ptr_off = -end_save;
21018 	  insn = rs6000_emit_savres_rtx (info, scratch_reg,
21019 					 info->altivec_save_offset + ptr_off,
21020 					 0, V4SImode, SAVRES_VR);
21021 	  if (REGNO (frame_reg_rtx) == REGNO (scratch_reg))
21022 	    {
21023 	      /* Frame reg was clobbered by out-of-line save.  Restore it
21024 		 from ptr_reg, and if we are calling out-of-line gpr or
21025 		 fpr restore set up the correct pointer and offset.  */
21026 	      unsigned newptr_regno = 1;
21027 	      if (!restoring_GPRs_inline)
21028 		{
21029 		  bool lr = info->gp_save_offset + info->gp_size == 0;
21030 		  int sel = SAVRES_GPR | (lr ? SAVRES_LR : 0);
21031 		  newptr_regno = ptr_regno_for_savres (sel);
21032 		  end_save = info->gp_save_offset + info->gp_size;
21033 		}
21034 	      else if (!restoring_FPRs_inline)
21035 		{
21036 		  bool lr = !(strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR);
21037 		  int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
21038 		  newptr_regno = ptr_regno_for_savres (sel);
21039 		  end_save = info->gp_save_offset + info->gp_size;
21040 		}
21041 
21042 	      if (newptr_regno != 1 && REGNO (frame_reg_rtx) != newptr_regno)
21043 		frame_reg_rtx = gen_rtx_REG (Pmode, newptr_regno);
21044 
21045 	      if (end_save + ptr_off != 0)
21046 		{
21047 		  rtx offset = GEN_INT (end_save + ptr_off);
21048 
21049 		  frame_off = -end_save;
21050 		  emit_insn (gen_add3_insn (frame_reg_rtx, ptr_reg, offset));
21051 		}
21052 	      else
21053 		{
21054 		  frame_off = ptr_off;
21055 		  emit_move_insn (frame_reg_rtx, ptr_reg);
21056 		}
21057 	    }
21058 	}
21059       else
21060 	{
21061 	  for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
21062 	    if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
21063 	      {
21064 		rtx addr, areg, mem, reg;
21065 
21066 		areg = gen_rtx_REG (Pmode, 0);
21067 		emit_move_insn
21068 		  (areg, GEN_INT (info->altivec_save_offset
21069 				  + frame_off
21070 				  + 16 * (i - info->first_altivec_reg_save)));
21071 
21072 		/* AltiVec addressing mode is [reg+reg].  */
21073 		addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
21074 		mem = gen_frame_mem (V4SImode, addr);
21075 
21076 		reg = gen_rtx_REG (V4SImode, i);
21077 		emit_move_insn (reg, mem);
21078 	      }
21079 	}
21080 
21081       for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
21082 	if (((strategy & REST_INLINE_VRS) == 0
21083 	     || (info->vrsave_mask & ALTIVEC_REG_BIT (i)) != 0)
21084 	    && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap))
21085 	  {
21086 	    rtx reg = gen_rtx_REG (V4SImode, i);
21087 	    cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
21088 	  }
21089     }
21090 
21091   /* Restore VRSAVE if we have not done so already.  */
21092   if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
21093       && TARGET_ALTIVEC
21094       && TARGET_ALTIVEC_VRSAVE
21095       && info->vrsave_mask != 0
21096       && (DEFAULT_ABI == ABI_V4
21097 	  || !offset_below_red_zone_p (info->vrsave_save_offset)))
21098     {
21099       rtx reg;
21100 
21101       reg = gen_rtx_REG (SImode, 12);
21102       emit_insn (gen_frame_load (reg, frame_reg_rtx,
21103 				 info->vrsave_save_offset + frame_off));
21104 
21105       emit_insn (generate_set_vrsave (reg, info, 1));
21106     }
21107 
21108   /* If we exit by an out-of-line restore function on ABI_V4 then that
21109      function will deallocate the stack, so we don't need to worry
21110      about the unwinder restoring cr from an invalid stack frame
21111      location.  */
21112   exit_func = (!restoring_FPRs_inline
21113 	       || (!restoring_GPRs_inline
21114 		   && info->first_fp_reg_save == 64));
21115 
21116   /* Get the old lr if we saved it.  If we are restoring registers
21117      out-of-line, then the out-of-line routines can do this for us.  */
21118   if (restore_lr && restoring_GPRs_inline)
21119     load_lr_save (0, frame_reg_rtx, info->lr_save_offset + frame_off);
21120 
21121   /* Get the old cr if we saved it.  */
21122   if (info->cr_save_p)
21123     {
21124       unsigned cr_save_regno = 12;
21125 
21126       if (!restoring_GPRs_inline)
21127 	{
21128 	  /* Ensure we don't use the register used by the out-of-line
21129 	     gpr register restore below.  */
21130 	  bool lr = info->gp_save_offset + info->gp_size == 0;
21131 	  int sel = SAVRES_GPR | (lr ? SAVRES_LR : 0);
21132 	  int gpr_ptr_regno = ptr_regno_for_savres (sel);
21133 
21134 	  if (gpr_ptr_regno == 12)
21135 	    cr_save_regno = 11;
21136 	  gcc_checking_assert (REGNO (frame_reg_rtx) != cr_save_regno);
21137 	}
21138       else if (REGNO (frame_reg_rtx) == 12)
21139 	cr_save_regno = 11;
21140 
21141       cr_save_reg = load_cr_save (cr_save_regno, frame_reg_rtx,
21142 				  info->cr_save_offset + frame_off,
21143 				  exit_func);
21144     }
21145 
21146   /* Set LR here to try to overlap restores below.  */
21147   if (restore_lr && restoring_GPRs_inline)
21148     restore_saved_lr (0, exit_func);
21149 
21150   /* Load exception handler data registers, if needed.  */
21151   if (crtl->calls_eh_return)
21152     {
21153       unsigned int i, regno;
21154 
21155       if (TARGET_AIX)
21156 	{
21157 	  rtx reg = gen_rtx_REG (reg_mode, 2);
21158 	  emit_insn (gen_frame_load (reg, frame_reg_rtx,
21159 				     frame_off + 5 * reg_size));
21160 	}
21161 
21162       for (i = 0; ; ++i)
21163 	{
21164 	  rtx mem;
21165 
21166 	  regno = EH_RETURN_DATA_REGNO (i);
21167 	  if (regno == INVALID_REGNUM)
21168 	    break;
21169 
21170 	  /* Note: possible use of r0 here to address SPE regs.  */
21171 	  mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
21172 				      info->ehrd_offset + frame_off
21173 				      + reg_size * (int) i);
21174 
21175 	  emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
21176 	}
21177     }
21178 
21179   /* Restore GPRs.  This is done as a PARALLEL if we are using
21180      the load-multiple instructions.  */
21181   if (TARGET_SPE_ABI
21182       && info->spe_64bit_regs_used
21183       && info->first_gp_reg_save != 32)
21184     {
21185       /* Determine whether we can address all of the registers that need
21186 	 to be saved with an offset from frame_reg_rtx that fits in
21187 	 the small const field for SPE memory instructions.  */
21188       int spe_regs_addressable
21189 	= (SPE_CONST_OFFSET_OK (info->spe_gp_save_offset + frame_off
21190 				+ reg_size * (32 - info->first_gp_reg_save - 1))
21191 	   && restoring_GPRs_inline);
21192 
21193       if (!spe_regs_addressable)
21194 	{
21195 	  int ool_adjust = 0;
21196 	  rtx old_frame_reg_rtx = frame_reg_rtx;
21197 	  /* Make r11 point to the start of the SPE save area.  We worried about
21198 	     not clobbering it when we were saving registers in the prologue.
21199 	     There's no need to worry here because the static chain is passed
21200 	     anew to every function.  */
21201 
21202 	  if (!restoring_GPRs_inline)
21203 	    ool_adjust = 8 * (info->first_gp_reg_save
21204 			      - (FIRST_SAVRES_REGISTER + 1));
21205 	  frame_reg_rtx = gen_rtx_REG (Pmode, 11);
21206 	  emit_insn (gen_addsi3 (frame_reg_rtx, old_frame_reg_rtx,
21207 				 GEN_INT (info->spe_gp_save_offset
21208 					  + frame_off
21209 					  - ool_adjust)));
21210 	  /* Keep the invariant that frame_reg_rtx + frame_off points
21211 	     at the top of the stack frame.  */
21212 	  frame_off = -info->spe_gp_save_offset + ool_adjust;
21213 	}
21214 
21215       if (restoring_GPRs_inline)
21216 	{
21217 	  HOST_WIDE_INT spe_offset = info->spe_gp_save_offset + frame_off;
21218 
21219 	  for (i = 0; i < 32 - info->first_gp_reg_save; i++)
21220 	    if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
21221 	      {
21222 		rtx offset, addr, mem, reg;
21223 
21224 		/* We're doing all this to ensure that the immediate offset
21225 		   fits into the immediate field of 'evldd'.  */
21226 		gcc_assert (SPE_CONST_OFFSET_OK (spe_offset + reg_size * i));
21227 
21228 		offset = GEN_INT (spe_offset + reg_size * i);
21229 		addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, offset);
21230 		mem = gen_rtx_MEM (V2SImode, addr);
21231 		reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
21232 
21233 		emit_move_insn (reg, mem);
21234 	      }
21235 	}
21236       else
21237 	rs6000_emit_savres_rtx (info, frame_reg_rtx,
21238 				info->spe_gp_save_offset + frame_off,
21239 				info->lr_save_offset + frame_off,
21240 				reg_mode,
21241 				SAVRES_GPR | SAVRES_LR);
21242     }
21243   else if (!restoring_GPRs_inline)
21244     {
21245       /* We are jumping to an out-of-line function.  */
21246       rtx ptr_reg;
21247       int end_save = info->gp_save_offset + info->gp_size;
21248       bool can_use_exit = end_save == 0;
21249       int sel = SAVRES_GPR | (can_use_exit ? SAVRES_LR : 0);
21250       int ptr_off;
21251 
21252       /* Emit stack reset code if we need it.  */
21253       ptr_regno = ptr_regno_for_savres (sel);
21254       ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
21255       if (can_use_exit)
21256 	rs6000_emit_stack_reset (info, frame_reg_rtx, frame_off, ptr_regno);
21257       else if (end_save + frame_off != 0)
21258 	emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx,
21259 				  GEN_INT (end_save + frame_off)));
21260       else if (REGNO (frame_reg_rtx) != ptr_regno)
21261 	emit_move_insn (ptr_reg, frame_reg_rtx);
21262       if (REGNO (frame_reg_rtx) == ptr_regno)
21263 	frame_off = -end_save;
21264 
21265       if (can_use_exit && info->cr_save_p)
21266 	restore_saved_cr (cr_save_reg, using_mtcr_multiple, true);
21267 
21268       ptr_off = -end_save;
21269       rs6000_emit_savres_rtx (info, ptr_reg,
21270 			      info->gp_save_offset + ptr_off,
21271 			      info->lr_save_offset + ptr_off,
21272 			      reg_mode, sel);
21273     }
21274   else if (using_load_multiple)
21275     {
21276       rtvec p;
21277       p = rtvec_alloc (32 - info->first_gp_reg_save);
21278       for (i = 0; i < 32 - info->first_gp_reg_save; i++)
21279 	RTVEC_ELT (p, i)
21280 	  = gen_frame_load (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
21281 			    frame_reg_rtx,
21282 			    info->gp_save_offset + frame_off + reg_size * i);
21283       emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
21284     }
21285   else
21286     {
21287       for (i = 0; i < 32 - info->first_gp_reg_save; i++)
21288 	if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
21289 	  emit_insn (gen_frame_load
21290 		     (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
21291 		      frame_reg_rtx,
21292 		      info->gp_save_offset + frame_off + reg_size * i));
21293     }
21294 
21295   if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
21296     {
21297       /* If the frame pointer was used then we can't delay emitting
21298 	 a REG_CFA_DEF_CFA note.  This must happen on the insn that
21299 	 restores the frame pointer, r31.  We may have already emitted
21300 	 a REG_CFA_DEF_CFA note, but that's OK;  A duplicate is
21301 	 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
21302 	 be harmless if emitted.  */
21303       if (frame_pointer_needed)
21304 	{
21305 	  insn = get_last_insn ();
21306 	  add_reg_note (insn, REG_CFA_DEF_CFA,
21307 			plus_constant (Pmode, frame_reg_rtx, frame_off));
21308 	  RTX_FRAME_RELATED_P (insn) = 1;
21309 	}
21310 
21311       /* Set up cfa_restores.  We always need these when
21312 	 shrink-wrapping.  If not shrink-wrapping then we only need
21313 	 the cfa_restore when the stack location is no longer valid.
21314 	 The cfa_restores must be emitted on or before the insn that
21315 	 invalidates the stack, and of course must not be emitted
21316 	 before the insn that actually does the restore.  The latter
21317 	 is why it is a bad idea to emit the cfa_restores as a group
21318 	 on the last instruction here that actually does a restore:
21319 	 That insn may be reordered with respect to others doing
21320 	 restores.  */
21321       if (flag_shrink_wrap
21322 	  && !restoring_GPRs_inline
21323 	  && info->first_fp_reg_save == 64)
21324 	cfa_restores = add_crlr_cfa_restore (info, cfa_restores);
21325 
21326       for (i = info->first_gp_reg_save; i < 32; i++)
21327 	if (!restoring_GPRs_inline
21328 	    || using_load_multiple
21329 	    || rs6000_reg_live_or_pic_offset_p (i))
21330 	  {
21331 	    rtx reg = gen_rtx_REG (reg_mode, i);
21332 
21333 	    cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
21334 	  }
21335     }
21336 
21337   if (!restoring_GPRs_inline
21338       && info->first_fp_reg_save == 64)
21339     {
21340       /* We are jumping to an out-of-line function.  */
21341       if (cfa_restores)
21342 	emit_cfa_restores (cfa_restores);
21343       return;
21344     }
21345 
21346   if (restore_lr && !restoring_GPRs_inline)
21347     {
21348       load_lr_save (0, frame_reg_rtx, info->lr_save_offset + frame_off);
21349       restore_saved_lr (0, exit_func);
21350     }
21351 
21352   /* Restore fpr's if we need to do it without calling a function.  */
21353   if (restoring_FPRs_inline)
21354     for (i = 0; i < 64 - info->first_fp_reg_save; i++)
21355       if (save_reg_p (info->first_fp_reg_save + i))
21356 	{
21357 	  rtx reg = gen_rtx_REG ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
21358 				  ? DFmode : SFmode),
21359 				 info->first_fp_reg_save + i);
21360 	  emit_insn (gen_frame_load (reg, frame_reg_rtx,
21361 				     info->fp_save_offset + frame_off + 8 * i));
21362 	  if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
21363 	    cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
21364 	}
21365 
21366   /* If we saved cr, restore it here.  Just those that were used.  */
21367   if (info->cr_save_p)
21368     restore_saved_cr (cr_save_reg, using_mtcr_multiple, exit_func);
21369 
21370   /* If this is V.4, unwind the stack pointer after all of the loads
21371      have been done, or set up r11 if we are restoring fp out of line.  */
21372   ptr_regno = 1;
21373   if (!restoring_FPRs_inline)
21374     {
21375       bool lr = (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
21376       int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
21377       ptr_regno = ptr_regno_for_savres (sel);
21378     }
21379 
21380   insn = rs6000_emit_stack_reset (info, frame_reg_rtx, frame_off, ptr_regno);
21381   if (REGNO (frame_reg_rtx) == ptr_regno)
21382     frame_off = 0;
21383 
21384   if (insn && restoring_FPRs_inline)
21385     {
21386       if (cfa_restores)
21387 	{
21388 	  REG_NOTES (insn) = cfa_restores;
21389 	  cfa_restores = NULL_RTX;
21390 	}
21391       add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
21392       RTX_FRAME_RELATED_P (insn) = 1;
21393     }
21394 
21395   if (crtl->calls_eh_return)
21396     {
21397       rtx sa = EH_RETURN_STACKADJ_RTX;
21398       emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx, sa));
21399     }
21400 
21401   if (!sibcall)
21402     {
21403       rtvec p;
21404       bool lr = (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
21405       if (! restoring_FPRs_inline)
21406 	{
21407 	  p = rtvec_alloc (4 + 64 - info->first_fp_reg_save);
21408 	  RTVEC_ELT (p, 0) = ret_rtx;
21409 	}
21410       else
21411 	{
21412 	  if (cfa_restores)
21413 	    {
21414 	      /* We can't hang the cfa_restores off a simple return,
21415 		 since the shrink-wrap code sometimes uses an existing
21416 		 return.  This means there might be a path from
21417 		 pre-prologue code to this return, and dwarf2cfi code
21418 		 wants the eh_frame unwinder state to be the same on
21419 		 all paths to any point.  So we need to emit the
21420 		 cfa_restores before the return.  For -m64 we really
21421 		 don't need epilogue cfa_restores at all, except for
21422 		 this irritating dwarf2cfi with shrink-wrap
21423 		 requirement;  The stack red-zone means eh_frame info
21424 		 from the prologue telling the unwinder to restore
21425 		 from the stack is perfectly good right to the end of
21426 		 the function.  */
21427 	      emit_insn (gen_blockage ());
21428 	      emit_cfa_restores (cfa_restores);
21429 	      cfa_restores = NULL_RTX;
21430 	    }
21431 	  p = rtvec_alloc (2);
21432 	  RTVEC_ELT (p, 0) = simple_return_rtx;
21433 	}
21434 
21435       RTVEC_ELT (p, 1) = ((restoring_FPRs_inline || !lr)
21436 			  ? gen_rtx_USE (VOIDmode,
21437 					 gen_rtx_REG (Pmode, LR_REGNO))
21438 			  : gen_rtx_CLOBBER (VOIDmode,
21439 					     gen_rtx_REG (Pmode, LR_REGNO)));
21440 
21441       /* If we have to restore more than two FP registers, branch to the
21442 	 restore function.  It will return to our caller.  */
21443       if (! restoring_FPRs_inline)
21444 	{
21445 	  int i;
21446 	  rtx sym;
21447 
21448 	  if (flag_shrink_wrap)
21449 	    cfa_restores = add_crlr_cfa_restore (info, cfa_restores);
21450 
21451 	  sym = rs6000_savres_routine_sym (info,
21452 					   SAVRES_FPR | (lr ? SAVRES_LR : 0));
21453 	  RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, sym);
21454 	  RTVEC_ELT (p, 3) = gen_rtx_USE (VOIDmode,
21455 					  gen_rtx_REG (Pmode,
21456 						       DEFAULT_ABI == ABI_AIX
21457 						       ? 1 : 11));
21458 	  for (i = 0; i < 64 - info->first_fp_reg_save; i++)
21459 	    {
21460 	      rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
21461 
21462 	      RTVEC_ELT (p, i + 4)
21463 		= gen_frame_load (reg, sp_reg_rtx, info->fp_save_offset + 8 * i);
21464 	      if (flag_shrink_wrap)
21465 		cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
21466 					       cfa_restores);
21467 	    }
21468 	}
21469 
21470       emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
21471     }
21472 
21473   if (cfa_restores)
21474     {
21475       if (sibcall)
21476 	/* Ensure the cfa_restores are hung off an insn that won't
21477 	   be reordered above other restores.  */
21478 	emit_insn (gen_blockage ());
21479 
21480       emit_cfa_restores (cfa_restores);
21481     }
21482 }
21483 
21484 /* Write function epilogue.  */
21485 
21486 static void
rs6000_output_function_epilogue(FILE * file,HOST_WIDE_INT size ATTRIBUTE_UNUSED)21487 rs6000_output_function_epilogue (FILE *file,
21488 				 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
21489 {
21490 #if TARGET_MACHO
21491   macho_branch_islands ();
21492   /* Mach-O doesn't support labels at the end of objects, so if
21493      it looks like we might want one, insert a NOP.  */
21494   {
21495     rtx insn = get_last_insn ();
21496     rtx deleted_debug_label = NULL_RTX;
21497     while (insn
21498 	   && NOTE_P (insn)
21499 	   && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
21500       {
21501 	/* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
21502 	   notes only, instead set their CODE_LABEL_NUMBER to -1,
21503 	   otherwise there would be code generation differences
21504 	   in between -g and -g0.  */
21505 	if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
21506 	  deleted_debug_label = insn;
21507 	insn = PREV_INSN (insn);
21508       }
21509     if (insn
21510 	&& (LABEL_P (insn)
21511 	    || (NOTE_P (insn)
21512 		&& NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
21513       fputs ("\tnop\n", file);
21514     else if (deleted_debug_label)
21515       for (insn = deleted_debug_label; insn; insn = NEXT_INSN (insn))
21516 	if (NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
21517 	  CODE_LABEL_NUMBER (insn) = -1;
21518   }
21519 #endif
21520 
21521   /* Output a traceback table here.  See /usr/include/sys/debug.h for info
21522      on its format.
21523 
21524      We don't output a traceback table if -finhibit-size-directive was
21525      used.  The documentation for -finhibit-size-directive reads
21526      ``don't output a @code{.size} assembler directive, or anything
21527      else that would cause trouble if the function is split in the
21528      middle, and the two halves are placed at locations far apart in
21529      memory.''  The traceback table has this property, since it
21530      includes the offset from the start of the function to the
21531      traceback table itself.
21532 
21533      System V.4 Powerpc's (and the embedded ABI derived from it) use a
21534      different traceback table.  */
21535   if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
21536       && rs6000_traceback != traceback_none && !cfun->is_thunk)
21537     {
21538       const char *fname = NULL;
21539       const char *language_string = lang_hooks.name;
21540       int fixed_parms = 0, float_parms = 0, parm_info = 0;
21541       int i;
21542       int optional_tbtab;
21543       rs6000_stack_t *info = rs6000_stack_info ();
21544 
21545       if (rs6000_traceback == traceback_full)
21546 	optional_tbtab = 1;
21547       else if (rs6000_traceback == traceback_part)
21548 	optional_tbtab = 0;
21549       else
21550 	optional_tbtab = !optimize_size && !TARGET_ELF;
21551 
21552       if (optional_tbtab)
21553 	{
21554 	  fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
21555 	  while (*fname == '.')	/* V.4 encodes . in the name */
21556 	    fname++;
21557 
21558 	  /* Need label immediately before tbtab, so we can compute
21559 	     its offset from the function start.  */
21560 	  ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
21561 	  ASM_OUTPUT_LABEL (file, fname);
21562 	}
21563 
21564       /* The .tbtab pseudo-op can only be used for the first eight
21565 	 expressions, since it can't handle the possibly variable
21566 	 length fields that follow.  However, if you omit the optional
21567 	 fields, the assembler outputs zeros for all optional fields
21568 	 anyways, giving each variable length field is minimum length
21569 	 (as defined in sys/debug.h).  Thus we can not use the .tbtab
21570 	 pseudo-op at all.  */
21571 
21572       /* An all-zero word flags the start of the tbtab, for debuggers
21573 	 that have to find it by searching forward from the entry
21574 	 point or from the current pc.  */
21575       fputs ("\t.long 0\n", file);
21576 
21577       /* Tbtab format type.  Use format type 0.  */
21578       fputs ("\t.byte 0,", file);
21579 
21580       /* Language type.  Unfortunately, there does not seem to be any
21581 	 official way to discover the language being compiled, so we
21582 	 use language_string.
21583 	 C is 0.  Fortran is 1.  Pascal is 2.  Ada is 3.  C++ is 9.
21584 	 Java is 13.  Objective-C is 14.  Objective-C++ isn't assigned
21585 	 a number, so for now use 9.  LTO and Go aren't assigned numbers
21586 	 either, so for now use 0.  */
21587       if (! strcmp (language_string, "GNU C")
21588 	  || ! strcmp (language_string, "GNU GIMPLE")
21589 	  || ! strcmp (language_string, "GNU Go"))
21590 	i = 0;
21591       else if (! strcmp (language_string, "GNU F77")
21592 	       || ! strcmp (language_string, "GNU Fortran"))
21593 	i = 1;
21594       else if (! strcmp (language_string, "GNU Pascal"))
21595 	i = 2;
21596       else if (! strcmp (language_string, "GNU Ada"))
21597 	i = 3;
21598       else if (! strcmp (language_string, "GNU C++")
21599 	       || ! strcmp (language_string, "GNU Objective-C++"))
21600 	i = 9;
21601       else if (! strcmp (language_string, "GNU Java"))
21602 	i = 13;
21603       else if (! strcmp (language_string, "GNU Objective-C"))
21604 	i = 14;
21605       else
21606 	gcc_unreachable ();
21607       fprintf (file, "%d,", i);
21608 
21609       /* 8 single bit fields: global linkage (not set for C extern linkage,
21610 	 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
21611 	 from start of procedure stored in tbtab, internal function, function
21612 	 has controlled storage, function has no toc, function uses fp,
21613 	 function logs/aborts fp operations.  */
21614       /* Assume that fp operations are used if any fp reg must be saved.  */
21615       fprintf (file, "%d,",
21616 	       (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
21617 
21618       /* 6 bitfields: function is interrupt handler, name present in
21619 	 proc table, function calls alloca, on condition directives
21620 	 (controls stack walks, 3 bits), saves condition reg, saves
21621 	 link reg.  */
21622       /* The `function calls alloca' bit seems to be set whenever reg 31 is
21623 	 set up as a frame pointer, even when there is no alloca call.  */
21624       fprintf (file, "%d,",
21625 	       ((optional_tbtab << 6)
21626 		| ((optional_tbtab & frame_pointer_needed) << 5)
21627 		| (info->cr_save_p << 1)
21628 		| (info->lr_save_p)));
21629 
21630       /* 3 bitfields: saves backchain, fixup code, number of fpr saved
21631 	 (6 bits).  */
21632       fprintf (file, "%d,",
21633 	       (info->push_p << 7) | (64 - info->first_fp_reg_save));
21634 
21635       /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits).  */
21636       fprintf (file, "%d,", (32 - first_reg_to_save ()));
21637 
21638       if (optional_tbtab)
21639 	{
21640 	  /* Compute the parameter info from the function decl argument
21641 	     list.  */
21642 	  tree decl;
21643 	  int next_parm_info_bit = 31;
21644 
21645 	  for (decl = DECL_ARGUMENTS (current_function_decl);
21646 	       decl; decl = DECL_CHAIN (decl))
21647 	    {
21648 	      rtx parameter = DECL_INCOMING_RTL (decl);
21649 	      enum machine_mode mode = GET_MODE (parameter);
21650 
21651 	      if (GET_CODE (parameter) == REG)
21652 		{
21653 		  if (SCALAR_FLOAT_MODE_P (mode))
21654 		    {
21655 		      int bits;
21656 
21657 		      float_parms++;
21658 
21659 		      switch (mode)
21660 			{
21661 			case SFmode:
21662 			case SDmode:
21663 			  bits = 0x2;
21664 			  break;
21665 
21666 			case DFmode:
21667 			case DDmode:
21668 			case TFmode:
21669 			case TDmode:
21670 			  bits = 0x3;
21671 			  break;
21672 
21673 			default:
21674 			  gcc_unreachable ();
21675 			}
21676 
21677 		      /* If only one bit will fit, don't or in this entry.  */
21678 		      if (next_parm_info_bit > 0)
21679 			parm_info |= (bits << (next_parm_info_bit - 1));
21680 		      next_parm_info_bit -= 2;
21681 		    }
21682 		  else
21683 		    {
21684 		      fixed_parms += ((GET_MODE_SIZE (mode)
21685 				       + (UNITS_PER_WORD - 1))
21686 				      / UNITS_PER_WORD);
21687 		      next_parm_info_bit -= 1;
21688 		    }
21689 		}
21690 	    }
21691 	}
21692 
21693       /* Number of fixed point parameters.  */
21694       /* This is actually the number of words of fixed point parameters; thus
21695 	 an 8 byte struct counts as 2; and thus the maximum value is 8.  */
21696       fprintf (file, "%d,", fixed_parms);
21697 
21698       /* 2 bitfields: number of floating point parameters (7 bits), parameters
21699 	 all on stack.  */
21700       /* This is actually the number of fp registers that hold parameters;
21701 	 and thus the maximum value is 13.  */
21702       /* Set parameters on stack bit if parameters are not in their original
21703 	 registers, regardless of whether they are on the stack?  Xlc
21704 	 seems to set the bit when not optimizing.  */
21705       fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
21706 
21707       if (! optional_tbtab)
21708 	return;
21709 
21710       /* Optional fields follow.  Some are variable length.  */
21711 
21712       /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
21713 	 11 double float.  */
21714       /* There is an entry for each parameter in a register, in the order that
21715 	 they occur in the parameter list.  Any intervening arguments on the
21716 	 stack are ignored.  If the list overflows a long (max possible length
21717 	 34 bits) then completely leave off all elements that don't fit.  */
21718       /* Only emit this long if there was at least one parameter.  */
21719       if (fixed_parms || float_parms)
21720 	fprintf (file, "\t.long %d\n", parm_info);
21721 
21722       /* Offset from start of code to tb table.  */
21723       fputs ("\t.long ", file);
21724       ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
21725       RS6000_OUTPUT_BASENAME (file, fname);
21726       putc ('-', file);
21727       rs6000_output_function_entry (file, fname);
21728       putc ('\n', file);
21729 
21730       /* Interrupt handler mask.  */
21731       /* Omit this long, since we never set the interrupt handler bit
21732 	 above.  */
21733 
21734       /* Number of CTL (controlled storage) anchors.  */
21735       /* Omit this long, since the has_ctl bit is never set above.  */
21736 
21737       /* Displacement into stack of each CTL anchor.  */
21738       /* Omit this list of longs, because there are no CTL anchors.  */
21739 
21740       /* Length of function name.  */
21741       if (*fname == '*')
21742 	++fname;
21743       fprintf (file, "\t.short %d\n", (int) strlen (fname));
21744 
21745       /* Function name.  */
21746       assemble_string (fname, strlen (fname));
21747 
21748       /* Register for alloca automatic storage; this is always reg 31.
21749 	 Only emit this if the alloca bit was set above.  */
21750       if (frame_pointer_needed)
21751 	fputs ("\t.byte 31\n", file);
21752 
21753       fputs ("\t.align 2\n", file);
21754     }
21755 }
21756 
21757 /* A C compound statement that outputs the assembler code for a thunk
21758    function, used to implement C++ virtual function calls with
21759    multiple inheritance.  The thunk acts as a wrapper around a virtual
21760    function, adjusting the implicit object parameter before handing
21761    control off to the real function.
21762 
21763    First, emit code to add the integer DELTA to the location that
21764    contains the incoming first argument.  Assume that this argument
21765    contains a pointer, and is the one used to pass the `this' pointer
21766    in C++.  This is the incoming argument *before* the function
21767    prologue, e.g. `%o0' on a sparc.  The addition must preserve the
21768    values of all other incoming arguments.
21769 
21770    After the addition, emit code to jump to FUNCTION, which is a
21771    `FUNCTION_DECL'.  This is a direct pure jump, not a call, and does
21772    not touch the return address.  Hence returning from FUNCTION will
21773    return to whoever called the current `thunk'.
21774 
21775    The effect must be as if FUNCTION had been called directly with the
21776    adjusted first argument.  This macro is responsible for emitting
21777    all of the code for a thunk function; output_function_prologue()
21778    and output_function_epilogue() are not invoked.
21779 
21780    The THUNK_FNDECL is redundant.  (DELTA and FUNCTION have already
21781    been extracted from it.)  It might possibly be useful on some
21782    targets, but probably not.
21783 
21784    If you do not define this macro, the target-independent code in the
21785    C++ frontend will generate a less efficient heavyweight thunk that
21786    calls FUNCTION instead of jumping to it.  The generic approach does
21787    not support varargs.  */
21788 
21789 static void
rs6000_output_mi_thunk(FILE * file,tree thunk_fndecl ATTRIBUTE_UNUSED,HOST_WIDE_INT delta,HOST_WIDE_INT vcall_offset,tree function)21790 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
21791 			HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
21792 			tree function)
21793 {
21794   rtx this_rtx, insn, funexp;
21795 
21796   reload_completed = 1;
21797   epilogue_completed = 1;
21798 
21799   /* Mark the end of the (empty) prologue.  */
21800   emit_note (NOTE_INSN_PROLOGUE_END);
21801 
21802   /* Find the "this" pointer.  If the function returns a structure,
21803      the structure return pointer is in r3.  */
21804   if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
21805     this_rtx = gen_rtx_REG (Pmode, 4);
21806   else
21807     this_rtx = gen_rtx_REG (Pmode, 3);
21808 
21809   /* Apply the constant offset, if required.  */
21810   if (delta)
21811     emit_insn (gen_add3_insn (this_rtx, this_rtx, GEN_INT (delta)));
21812 
21813   /* Apply the offset from the vtable, if required.  */
21814   if (vcall_offset)
21815     {
21816       rtx vcall_offset_rtx = GEN_INT (vcall_offset);
21817       rtx tmp = gen_rtx_REG (Pmode, 12);
21818 
21819       emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx));
21820       if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
21821 	{
21822 	  emit_insn (gen_add3_insn (tmp, tmp, vcall_offset_rtx));
21823 	  emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
21824 	}
21825       else
21826 	{
21827 	  rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
21828 
21829 	  emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
21830 	}
21831       emit_insn (gen_add3_insn (this_rtx, this_rtx, tmp));
21832     }
21833 
21834   /* Generate a tail call to the target function.  */
21835   if (!TREE_USED (function))
21836     {
21837       assemble_external (function);
21838       TREE_USED (function) = 1;
21839     }
21840   funexp = XEXP (DECL_RTL (function), 0);
21841   funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
21842 
21843 #if TARGET_MACHO
21844   if (MACHOPIC_INDIRECT)
21845     funexp = machopic_indirect_call_target (funexp);
21846 #endif
21847 
21848   /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
21849      generate sibcall RTL explicitly.  */
21850   insn = emit_call_insn (
21851 	   gen_rtx_PARALLEL (VOIDmode,
21852 	     gen_rtvec (4,
21853 			gen_rtx_CALL (VOIDmode,
21854 				      funexp, const0_rtx),
21855 			gen_rtx_USE (VOIDmode, const0_rtx),
21856 			gen_rtx_USE (VOIDmode,
21857 				     gen_rtx_REG (SImode,
21858 						  LR_REGNO)),
21859 			simple_return_rtx)));
21860   SIBLING_CALL_P (insn) = 1;
21861   emit_barrier ();
21862 
21863   /* Run just enough of rest_of_compilation to get the insns emitted.
21864      There's not really enough bulk here to make other passes such as
21865      instruction scheduling worth while.  Note that use_thunk calls
21866      assemble_start_function and assemble_end_function.  */
21867   insn = get_insns ();
21868   shorten_branches (insn);
21869   final_start_function (insn, file, 1);
21870   final (insn, file, 1);
21871   final_end_function ();
21872 
21873   reload_completed = 0;
21874   epilogue_completed = 0;
21875 }
21876 
21877 /* A quick summary of the various types of 'constant-pool tables'
21878    under PowerPC:
21879 
21880    Target	Flags		Name		One table per
21881    AIX		(none)		AIX TOC		object file
21882    AIX		-mfull-toc	AIX TOC		object file
21883    AIX		-mminimal-toc	AIX minimal TOC	translation unit
21884    SVR4/EABI	(none)		SVR4 SDATA	object file
21885    SVR4/EABI	-fpic		SVR4 pic	object file
21886    SVR4/EABI	-fPIC		SVR4 PIC	translation unit
21887    SVR4/EABI	-mrelocatable	EABI TOC	function
21888    SVR4/EABI	-maix		AIX TOC		object file
21889    SVR4/EABI	-maix -mminimal-toc
21890 				AIX minimal TOC	translation unit
21891 
21892    Name			Reg.	Set by	entries	      contains:
21893 					made by	 addrs?	fp?	sum?
21894 
21895    AIX TOC		2	crt0	as	 Y	option	option
21896    AIX minimal TOC	30	prolog	gcc	 Y	Y	option
21897    SVR4 SDATA		13	crt0	gcc	 N	Y	N
21898    SVR4 pic		30	prolog	ld	 Y	not yet	N
21899    SVR4 PIC		30	prolog	gcc	 Y	option	option
21900    EABI TOC		30	prolog	gcc	 Y	option	option
21901 
21902 */
21903 
21904 /* Hash functions for the hash table.  */
21905 
21906 static unsigned
rs6000_hash_constant(rtx k)21907 rs6000_hash_constant (rtx k)
21908 {
21909   enum rtx_code code = GET_CODE (k);
21910   enum machine_mode mode = GET_MODE (k);
21911   unsigned result = (code << 3) ^ mode;
21912   const char *format;
21913   int flen, fidx;
21914 
21915   format = GET_RTX_FORMAT (code);
21916   flen = strlen (format);
21917   fidx = 0;
21918 
21919   switch (code)
21920     {
21921     case LABEL_REF:
21922       return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
21923 
21924     case CONST_DOUBLE:
21925       if (mode != VOIDmode)
21926 	return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
21927       flen = 2;
21928       break;
21929 
21930     case CODE_LABEL:
21931       fidx = 3;
21932       break;
21933 
21934     default:
21935       break;
21936     }
21937 
21938   for (; fidx < flen; fidx++)
21939     switch (format[fidx])
21940       {
21941       case 's':
21942 	{
21943 	  unsigned i, len;
21944 	  const char *str = XSTR (k, fidx);
21945 	  len = strlen (str);
21946 	  result = result * 613 + len;
21947 	  for (i = 0; i < len; i++)
21948 	    result = result * 613 + (unsigned) str[i];
21949 	  break;
21950 	}
21951       case 'u':
21952       case 'e':
21953 	result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
21954 	break;
21955       case 'i':
21956       case 'n':
21957 	result = result * 613 + (unsigned) XINT (k, fidx);
21958 	break;
21959       case 'w':
21960 	if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
21961 	  result = result * 613 + (unsigned) XWINT (k, fidx);
21962 	else
21963 	  {
21964 	    size_t i;
21965 	    for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
21966 	      result = result * 613 + (unsigned) (XWINT (k, fidx)
21967 						  >> CHAR_BIT * i);
21968 	  }
21969 	break;
21970       case '0':
21971 	break;
21972       default:
21973 	gcc_unreachable ();
21974       }
21975 
21976   return result;
21977 }
21978 
21979 static unsigned
toc_hash_function(const void * hash_entry)21980 toc_hash_function (const void *hash_entry)
21981 {
21982   const struct toc_hash_struct *thc =
21983     (const struct toc_hash_struct *) hash_entry;
21984   return rs6000_hash_constant (thc->key) ^ thc->key_mode;
21985 }
21986 
21987 /* Compare H1 and H2 for equivalence.  */
21988 
21989 static int
toc_hash_eq(const void * h1,const void * h2)21990 toc_hash_eq (const void *h1, const void *h2)
21991 {
21992   rtx r1 = ((const struct toc_hash_struct *) h1)->key;
21993   rtx r2 = ((const struct toc_hash_struct *) h2)->key;
21994 
21995   if (((const struct toc_hash_struct *) h1)->key_mode
21996       != ((const struct toc_hash_struct *) h2)->key_mode)
21997     return 0;
21998 
21999   return rtx_equal_p (r1, r2);
22000 }
22001 
22002 /* These are the names given by the C++ front-end to vtables, and
22003    vtable-like objects.  Ideally, this logic should not be here;
22004    instead, there should be some programmatic way of inquiring as
22005    to whether or not an object is a vtable.  */
22006 
22007 #define VTABLE_NAME_P(NAME)				\
22008   (strncmp ("_vt.", name, strlen ("_vt.")) == 0		\
22009   || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0	\
22010   || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0	\
22011   || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0	\
22012   || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
22013 
22014 #ifdef NO_DOLLAR_IN_LABEL
22015 /* Return a GGC-allocated character string translating dollar signs in
22016    input NAME to underscores.  Used by XCOFF ASM_OUTPUT_LABELREF.  */
22017 
22018 const char *
rs6000_xcoff_strip_dollar(const char * name)22019 rs6000_xcoff_strip_dollar (const char *name)
22020 {
22021   char *strip, *p;
22022   const char *q;
22023   size_t len;
22024 
22025   q = (const char *) strchr (name, '$');
22026 
22027   if (q == 0 || q == name)
22028     return name;
22029 
22030   len = strlen (name);
22031   strip = XALLOCAVEC (char, len + 1);
22032   strcpy (strip, name);
22033   p = strip + (q - name);
22034   while (p)
22035     {
22036       *p = '_';
22037       p = strchr (p + 1, '$');
22038     }
22039 
22040   return ggc_alloc_string (strip, len);
22041 }
22042 #endif
22043 
22044 void
rs6000_output_symbol_ref(FILE * file,rtx x)22045 rs6000_output_symbol_ref (FILE *file, rtx x)
22046 {
22047   /* Currently C++ toc references to vtables can be emitted before it
22048      is decided whether the vtable is public or private.  If this is
22049      the case, then the linker will eventually complain that there is
22050      a reference to an unknown section.  Thus, for vtables only,
22051      we emit the TOC reference to reference the symbol and not the
22052      section.  */
22053   const char *name = XSTR (x, 0);
22054 
22055   if (VTABLE_NAME_P (name))
22056     {
22057       RS6000_OUTPUT_BASENAME (file, name);
22058     }
22059   else
22060     assemble_name (file, name);
22061 }
22062 
22063 /* Output a TOC entry.  We derive the entry name from what is being
22064    written.  */
22065 
22066 void
output_toc(FILE * file,rtx x,int labelno,enum machine_mode mode)22067 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
22068 {
22069   char buf[256];
22070   const char *name = buf;
22071   rtx base = x;
22072   HOST_WIDE_INT offset = 0;
22073 
22074   gcc_assert (!TARGET_NO_TOC);
22075 
22076   /* When the linker won't eliminate them, don't output duplicate
22077      TOC entries (this happens on AIX if there is any kind of TOC,
22078      and on SVR4 under -fPIC or -mrelocatable).  Don't do this for
22079      CODE_LABELs.  */
22080   if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
22081     {
22082       struct toc_hash_struct *h;
22083       void * * found;
22084 
22085       /* Create toc_hash_table.  This can't be done at TARGET_OPTION_OVERRIDE
22086 	 time because GGC is not initialized at that point.  */
22087       if (toc_hash_table == NULL)
22088 	toc_hash_table = htab_create_ggc (1021, toc_hash_function,
22089 					  toc_hash_eq, NULL);
22090 
22091       h = ggc_alloc_toc_hash_struct ();
22092       h->key = x;
22093       h->key_mode = mode;
22094       h->labelno = labelno;
22095 
22096       found = htab_find_slot (toc_hash_table, h, INSERT);
22097       if (*found == NULL)
22098 	*found = h;
22099       else  /* This is indeed a duplicate.
22100 	       Set this label equal to that label.  */
22101 	{
22102 	  fputs ("\t.set ", file);
22103 	  ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
22104 	  fprintf (file, "%d,", labelno);
22105 	  ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
22106 	  fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
22107 					      found)->labelno));
22108 
22109 #ifdef HAVE_AS_TLS
22110 	  if (TARGET_XCOFF && GET_CODE (x) == SYMBOL_REF
22111 	      && (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_GLOBAL_DYNAMIC
22112 		  || SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC))
22113 	    {
22114 	      fputs ("\t.set ", file);
22115 	      ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCM");
22116 	      fprintf (file, "%d,", labelno);
22117 	      ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCM");
22118 	      fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
22119 			       			      found)->labelno));
22120 	    }
22121 #endif
22122 	  return;
22123 	}
22124     }
22125 
22126   /* If we're going to put a double constant in the TOC, make sure it's
22127      aligned properly when strict alignment is on.  */
22128   if (GET_CODE (x) == CONST_DOUBLE
22129       && STRICT_ALIGNMENT
22130       && GET_MODE_BITSIZE (mode) >= 64
22131       && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
22132     ASM_OUTPUT_ALIGN (file, 3);
22133   }
22134 
22135   (*targetm.asm_out.internal_label) (file, "LC", labelno);
22136 
22137   /* Handle FP constants specially.  Note that if we have a minimal
22138      TOC, things we put here aren't actually in the TOC, so we can allow
22139      FP constants.  */
22140   if (GET_CODE (x) == CONST_DOUBLE &&
22141       (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode))
22142     {
22143       REAL_VALUE_TYPE rv;
22144       long k[4];
22145 
22146       REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
22147       if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
22148 	REAL_VALUE_TO_TARGET_DECIMAL128 (rv, k);
22149       else
22150 	REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
22151 
22152       if (TARGET_64BIT)
22153 	{
22154 	  if (TARGET_MINIMAL_TOC)
22155 	    fputs (DOUBLE_INT_ASM_OP, file);
22156 	  else
22157 	    fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
22158 		     k[0] & 0xffffffff, k[1] & 0xffffffff,
22159 		     k[2] & 0xffffffff, k[3] & 0xffffffff);
22160 	  fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
22161 		   k[0] & 0xffffffff, k[1] & 0xffffffff,
22162 		   k[2] & 0xffffffff, k[3] & 0xffffffff);
22163 	  return;
22164 	}
22165       else
22166 	{
22167 	  if (TARGET_MINIMAL_TOC)
22168 	    fputs ("\t.long ", file);
22169 	  else
22170 	    fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
22171 		     k[0] & 0xffffffff, k[1] & 0xffffffff,
22172 		     k[2] & 0xffffffff, k[3] & 0xffffffff);
22173 	  fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
22174 		   k[0] & 0xffffffff, k[1] & 0xffffffff,
22175 		   k[2] & 0xffffffff, k[3] & 0xffffffff);
22176 	  return;
22177 	}
22178     }
22179   else if (GET_CODE (x) == CONST_DOUBLE &&
22180 	   (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
22181     {
22182       REAL_VALUE_TYPE rv;
22183       long k[2];
22184 
22185       REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
22186 
22187       if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
22188 	REAL_VALUE_TO_TARGET_DECIMAL64 (rv, k);
22189       else
22190 	REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
22191 
22192       if (TARGET_64BIT)
22193 	{
22194 	  if (TARGET_MINIMAL_TOC)
22195 	    fputs (DOUBLE_INT_ASM_OP, file);
22196 	  else
22197 	    fprintf (file, "\t.tc FD_%lx_%lx[TC],",
22198 		     k[0] & 0xffffffff, k[1] & 0xffffffff);
22199 	  fprintf (file, "0x%lx%08lx\n",
22200 		   k[0] & 0xffffffff, k[1] & 0xffffffff);
22201 	  return;
22202 	}
22203       else
22204 	{
22205 	  if (TARGET_MINIMAL_TOC)
22206 	    fputs ("\t.long ", file);
22207 	  else
22208 	    fprintf (file, "\t.tc FD_%lx_%lx[TC],",
22209 		     k[0] & 0xffffffff, k[1] & 0xffffffff);
22210 	  fprintf (file, "0x%lx,0x%lx\n",
22211 		   k[0] & 0xffffffff, k[1] & 0xffffffff);
22212 	  return;
22213 	}
22214     }
22215   else if (GET_CODE (x) == CONST_DOUBLE &&
22216 	   (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
22217     {
22218       REAL_VALUE_TYPE rv;
22219       long l;
22220 
22221       REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
22222       if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
22223 	REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
22224       else
22225 	REAL_VALUE_TO_TARGET_SINGLE (rv, l);
22226 
22227       if (TARGET_64BIT)
22228 	{
22229 	  if (TARGET_MINIMAL_TOC)
22230 	    fputs (DOUBLE_INT_ASM_OP, file);
22231 	  else
22232 	    fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
22233 	  fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
22234 	  return;
22235 	}
22236       else
22237 	{
22238 	  if (TARGET_MINIMAL_TOC)
22239 	    fputs ("\t.long ", file);
22240 	  else
22241 	    fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
22242 	  fprintf (file, "0x%lx\n", l & 0xffffffff);
22243 	  return;
22244 	}
22245     }
22246   else if (GET_MODE (x) == VOIDmode
22247 	   && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
22248     {
22249       unsigned HOST_WIDE_INT low;
22250       HOST_WIDE_INT high;
22251 
22252       if (GET_CODE (x) == CONST_DOUBLE)
22253 	{
22254 	  low = CONST_DOUBLE_LOW (x);
22255 	  high = CONST_DOUBLE_HIGH (x);
22256 	}
22257       else
22258 #if HOST_BITS_PER_WIDE_INT == 32
22259 	{
22260 	  low = INTVAL (x);
22261 	  high = (low & 0x80000000) ? ~0 : 0;
22262 	}
22263 #else
22264 	{
22265 	  low = INTVAL (x) & 0xffffffff;
22266 	  high = (HOST_WIDE_INT) INTVAL (x) >> 32;
22267 	}
22268 #endif
22269 
22270       /* TOC entries are always Pmode-sized, but since this
22271 	 is a bigendian machine then if we're putting smaller
22272 	 integer constants in the TOC we have to pad them.
22273 	 (This is still a win over putting the constants in
22274 	 a separate constant pool, because then we'd have
22275 	 to have both a TOC entry _and_ the actual constant.)
22276 
22277 	 For a 32-bit target, CONST_INT values are loaded and shifted
22278 	 entirely within `low' and can be stored in one TOC entry.  */
22279 
22280       /* It would be easy to make this work, but it doesn't now.  */
22281       gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
22282 
22283       if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
22284 	{
22285 #if HOST_BITS_PER_WIDE_INT == 32
22286 	  lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
22287 			 POINTER_SIZE, &low, &high, 0);
22288 #else
22289 	  low |= high << 32;
22290 	  low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
22291 	  high = (HOST_WIDE_INT) low >> 32;
22292 	  low &= 0xffffffff;
22293 #endif
22294 	}
22295 
22296       if (TARGET_64BIT)
22297 	{
22298 	  if (TARGET_MINIMAL_TOC)
22299 	    fputs (DOUBLE_INT_ASM_OP, file);
22300 	  else
22301 	    fprintf (file, "\t.tc ID_%lx_%lx[TC],",
22302 		     (long) high & 0xffffffff, (long) low & 0xffffffff);
22303 	  fprintf (file, "0x%lx%08lx\n",
22304 		   (long) high & 0xffffffff, (long) low & 0xffffffff);
22305 	  return;
22306 	}
22307       else
22308 	{
22309 	  if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
22310 	    {
22311 	      if (TARGET_MINIMAL_TOC)
22312 		fputs ("\t.long ", file);
22313 	      else
22314 		fprintf (file, "\t.tc ID_%lx_%lx[TC],",
22315 			 (long) high & 0xffffffff, (long) low & 0xffffffff);
22316 	      fprintf (file, "0x%lx,0x%lx\n",
22317 		       (long) high & 0xffffffff, (long) low & 0xffffffff);
22318 	    }
22319 	  else
22320 	    {
22321 	      if (TARGET_MINIMAL_TOC)
22322 		fputs ("\t.long ", file);
22323 	      else
22324 		fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
22325 	      fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
22326 	    }
22327 	  return;
22328 	}
22329     }
22330 
22331   if (GET_CODE (x) == CONST)
22332     {
22333       gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS
22334 		  && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT);
22335 
22336       base = XEXP (XEXP (x, 0), 0);
22337       offset = INTVAL (XEXP (XEXP (x, 0), 1));
22338     }
22339 
22340   switch (GET_CODE (base))
22341     {
22342     case SYMBOL_REF:
22343       name = XSTR (base, 0);
22344       break;
22345 
22346     case LABEL_REF:
22347       ASM_GENERATE_INTERNAL_LABEL (buf, "L",
22348 				   CODE_LABEL_NUMBER (XEXP (base, 0)));
22349       break;
22350 
22351     case CODE_LABEL:
22352       ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
22353       break;
22354 
22355     default:
22356       gcc_unreachable ();
22357     }
22358 
22359   if (TARGET_MINIMAL_TOC)
22360     fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
22361   else
22362     {
22363       fputs ("\t.tc ", file);
22364       RS6000_OUTPUT_BASENAME (file, name);
22365 
22366       if (offset < 0)
22367 	fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
22368       else if (offset)
22369 	fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
22370 
22371       /* Mark large TOC symbols on AIX with [TE] so they are mapped
22372 	 after other TOC symbols, reducing overflow of small TOC access
22373 	 to [TC] symbols.  */
22374       fputs (TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL
22375 	     ? "[TE]," : "[TC],", file);
22376     }
22377 
22378   /* Currently C++ toc references to vtables can be emitted before it
22379      is decided whether the vtable is public or private.  If this is
22380      the case, then the linker will eventually complain that there is
22381      a TOC reference to an unknown section.  Thus, for vtables only,
22382      we emit the TOC reference to reference the symbol and not the
22383      section.  */
22384   if (VTABLE_NAME_P (name))
22385     {
22386       RS6000_OUTPUT_BASENAME (file, name);
22387       if (offset < 0)
22388 	fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
22389       else if (offset > 0)
22390 	fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
22391     }
22392   else
22393     output_addr_const (file, x);
22394 
22395 #if HAVE_AS_TLS
22396   if (TARGET_XCOFF && GET_CODE (base) == SYMBOL_REF
22397       && SYMBOL_REF_TLS_MODEL (base) != 0)
22398     {
22399       if (SYMBOL_REF_TLS_MODEL (base) == TLS_MODEL_LOCAL_EXEC)
22400 	fputs ("@le", file);
22401       else if (SYMBOL_REF_TLS_MODEL (base) == TLS_MODEL_INITIAL_EXEC)
22402 	fputs ("@ie", file);
22403       /* Use global-dynamic for local-dynamic.  */
22404       else if (SYMBOL_REF_TLS_MODEL (base) == TLS_MODEL_GLOBAL_DYNAMIC
22405 	       || SYMBOL_REF_TLS_MODEL (base) == TLS_MODEL_LOCAL_DYNAMIC)
22406 	{
22407 	  putc ('\n', file);
22408 	  (*targetm.asm_out.internal_label) (file, "LCM", labelno);
22409 	  fputs ("\t.tc .", file);
22410 	  RS6000_OUTPUT_BASENAME (file, name);
22411 	  fputs ("[TC],", file);
22412 	  output_addr_const (file, x);
22413 	  fputs ("@m", file);
22414 	}
22415     }
22416 #endif
22417 
22418   putc ('\n', file);
22419 }
22420 
22421 /* Output an assembler pseudo-op to write an ASCII string of N characters
22422    starting at P to FILE.
22423 
22424    On the RS/6000, we have to do this using the .byte operation and
22425    write out special characters outside the quoted string.
22426    Also, the assembler is broken; very long strings are truncated,
22427    so we must artificially break them up early.  */
22428 
22429 void
output_ascii(FILE * file,const char * p,int n)22430 output_ascii (FILE *file, const char *p, int n)
22431 {
22432   char c;
22433   int i, count_string;
22434   const char *for_string = "\t.byte \"";
22435   const char *for_decimal = "\t.byte ";
22436   const char *to_close = NULL;
22437 
22438   count_string = 0;
22439   for (i = 0; i < n; i++)
22440     {
22441       c = *p++;
22442       if (c >= ' ' && c < 0177)
22443 	{
22444 	  if (for_string)
22445 	    fputs (for_string, file);
22446 	  putc (c, file);
22447 
22448 	  /* Write two quotes to get one.  */
22449 	  if (c == '"')
22450 	    {
22451 	      putc (c, file);
22452 	      ++count_string;
22453 	    }
22454 
22455 	  for_string = NULL;
22456 	  for_decimal = "\"\n\t.byte ";
22457 	  to_close = "\"\n";
22458 	  ++count_string;
22459 
22460 	  if (count_string >= 512)
22461 	    {
22462 	      fputs (to_close, file);
22463 
22464 	      for_string = "\t.byte \"";
22465 	      for_decimal = "\t.byte ";
22466 	      to_close = NULL;
22467 	      count_string = 0;
22468 	    }
22469 	}
22470       else
22471 	{
22472 	  if (for_decimal)
22473 	    fputs (for_decimal, file);
22474 	  fprintf (file, "%d", c);
22475 
22476 	  for_string = "\n\t.byte \"";
22477 	  for_decimal = ", ";
22478 	  to_close = "\n";
22479 	  count_string = 0;
22480 	}
22481     }
22482 
22483   /* Now close the string if we have written one.  Then end the line.  */
22484   if (to_close)
22485     fputs (to_close, file);
22486 }
22487 
22488 /* Generate a unique section name for FILENAME for a section type
22489    represented by SECTION_DESC.  Output goes into BUF.
22490 
22491    SECTION_DESC can be any string, as long as it is different for each
22492    possible section type.
22493 
22494    We name the section in the same manner as xlc.  The name begins with an
22495    underscore followed by the filename (after stripping any leading directory
22496    names) with the last period replaced by the string SECTION_DESC.  If
22497    FILENAME does not contain a period, SECTION_DESC is appended to the end of
22498    the name.  */
22499 
22500 void
rs6000_gen_section_name(char ** buf,const char * filename,const char * section_desc)22501 rs6000_gen_section_name (char **buf, const char *filename,
22502 			 const char *section_desc)
22503 {
22504   const char *q, *after_last_slash, *last_period = 0;
22505   char *p;
22506   int len;
22507 
22508   after_last_slash = filename;
22509   for (q = filename; *q; q++)
22510     {
22511       if (*q == '/')
22512 	after_last_slash = q + 1;
22513       else if (*q == '.')
22514 	last_period = q;
22515     }
22516 
22517   len = strlen (after_last_slash) + strlen (section_desc) + 2;
22518   *buf = (char *) xmalloc (len);
22519 
22520   p = *buf;
22521   *p++ = '_';
22522 
22523   for (q = after_last_slash; *q; q++)
22524     {
22525       if (q == last_period)
22526 	{
22527 	  strcpy (p, section_desc);
22528 	  p += strlen (section_desc);
22529 	  break;
22530 	}
22531 
22532       else if (ISALNUM (*q))
22533 	*p++ = *q;
22534     }
22535 
22536   if (last_period == 0)
22537     strcpy (p, section_desc);
22538   else
22539     *p = '\0';
22540 }
22541 
22542 /* Emit profile function.  */
22543 
22544 void
output_profile_hook(int labelno ATTRIBUTE_UNUSED)22545 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
22546 {
22547   /* Non-standard profiling for kernels, which just saves LR then calls
22548      _mcount without worrying about arg saves.  The idea is to change
22549      the function prologue as little as possible as it isn't easy to
22550      account for arg save/restore code added just for _mcount.  */
22551   if (TARGET_PROFILE_KERNEL)
22552     return;
22553 
22554   if (DEFAULT_ABI == ABI_AIX)
22555     {
22556 #ifndef NO_PROFILE_COUNTERS
22557 # define NO_PROFILE_COUNTERS 0
22558 #endif
22559       if (NO_PROFILE_COUNTERS)
22560 	emit_library_call (init_one_libfunc (RS6000_MCOUNT),
22561 			   LCT_NORMAL, VOIDmode, 0);
22562       else
22563 	{
22564 	  char buf[30];
22565 	  const char *label_name;
22566 	  rtx fun;
22567 
22568 	  ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
22569 	  label_name = ggc_strdup ((*targetm.strip_name_encoding) (buf));
22570 	  fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
22571 
22572 	  emit_library_call (init_one_libfunc (RS6000_MCOUNT),
22573 			     LCT_NORMAL, VOIDmode, 1, fun, Pmode);
22574 	}
22575     }
22576   else if (DEFAULT_ABI == ABI_DARWIN)
22577     {
22578       const char *mcount_name = RS6000_MCOUNT;
22579       int caller_addr_regno = LR_REGNO;
22580 
22581       /* Be conservative and always set this, at least for now.  */
22582       crtl->uses_pic_offset_table = 1;
22583 
22584 #if TARGET_MACHO
22585       /* For PIC code, set up a stub and collect the caller's address
22586 	 from r0, which is where the prologue puts it.  */
22587       if (MACHOPIC_INDIRECT
22588 	  && crtl->uses_pic_offset_table)
22589 	caller_addr_regno = 0;
22590 #endif
22591       emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
22592 			 LCT_NORMAL, VOIDmode, 1,
22593 			 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
22594     }
22595 }
22596 
22597 /* Write function profiler code.  */
22598 
22599 void
output_function_profiler(FILE * file,int labelno)22600 output_function_profiler (FILE *file, int labelno)
22601 {
22602   char buf[100];
22603 
22604   switch (DEFAULT_ABI)
22605     {
22606     default:
22607       gcc_unreachable ();
22608 
22609     case ABI_V4:
22610       if (!TARGET_32BIT)
22611 	{
22612 	  warning (0, "no profiling of 64-bit code for this ABI");
22613 	  return;
22614 	}
22615       ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
22616       fprintf (file, "\tmflr %s\n", reg_names[0]);
22617       if (NO_PROFILE_COUNTERS)
22618 	{
22619 	  asm_fprintf (file, "\tstw %s,4(%s)\n",
22620 		       reg_names[0], reg_names[1]);
22621 	}
22622       else if (TARGET_SECURE_PLT && flag_pic)
22623 	{
22624 	  if (TARGET_LINK_STACK)
22625 	    {
22626 	      char name[32];
22627 	      get_ppc476_thunk_name (name);
22628 	      asm_fprintf (file, "\tbl %s\n", name);
22629 	    }
22630 	  else
22631 	    asm_fprintf (file, "\tbcl 20,31,1f\n1:\n");
22632 	  asm_fprintf (file, "\tstw %s,4(%s)\n",
22633 		       reg_names[0], reg_names[1]);
22634 	  asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
22635 	  asm_fprintf (file, "\taddis %s,%s,",
22636 		       reg_names[12], reg_names[12]);
22637 	  assemble_name (file, buf);
22638 	  asm_fprintf (file, "-1b@ha\n\tla %s,", reg_names[0]);
22639 	  assemble_name (file, buf);
22640 	  asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
22641 	}
22642       else if (flag_pic == 1)
22643 	{
22644 	  fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
22645 	  asm_fprintf (file, "\tstw %s,4(%s)\n",
22646 		       reg_names[0], reg_names[1]);
22647 	  asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
22648 	  asm_fprintf (file, "\tlwz %s,", reg_names[0]);
22649 	  assemble_name (file, buf);
22650 	  asm_fprintf (file, "@got(%s)\n", reg_names[12]);
22651 	}
22652       else if (flag_pic > 1)
22653 	{
22654 	  asm_fprintf (file, "\tstw %s,4(%s)\n",
22655 		       reg_names[0], reg_names[1]);
22656 	  /* Now, we need to get the address of the label.  */
22657 	  if (TARGET_LINK_STACK)
22658 	    {
22659 	      char name[32];
22660 	      get_ppc476_thunk_name (name);
22661 	      asm_fprintf (file, "\tbl %s\n\tb 1f\n\t.long ", name);
22662 	      assemble_name (file, buf);
22663 	      fputs ("-.\n1:", file);
22664 	      asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
22665 	      asm_fprintf (file, "\taddi %s,%s,4\n",
22666 			   reg_names[11], reg_names[11]);
22667 	    }
22668 	  else
22669 	    {
22670 	      fputs ("\tbcl 20,31,1f\n\t.long ", file);
22671 	      assemble_name (file, buf);
22672 	      fputs ("-.\n1:", file);
22673 	      asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
22674 	    }
22675 	  asm_fprintf (file, "\tlwz %s,0(%s)\n",
22676 		       reg_names[0], reg_names[11]);
22677 	  asm_fprintf (file, "\tadd %s,%s,%s\n",
22678 		       reg_names[0], reg_names[0], reg_names[11]);
22679 	}
22680       else
22681 	{
22682 	  asm_fprintf (file, "\tlis %s,", reg_names[12]);
22683 	  assemble_name (file, buf);
22684 	  fputs ("@ha\n", file);
22685 	  asm_fprintf (file, "\tstw %s,4(%s)\n",
22686 		       reg_names[0], reg_names[1]);
22687 	  asm_fprintf (file, "\tla %s,", reg_names[0]);
22688 	  assemble_name (file, buf);
22689 	  asm_fprintf (file, "@l(%s)\n", reg_names[12]);
22690 	}
22691 
22692       /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH.  */
22693       fprintf (file, "\tbl %s%s\n",
22694 	       RS6000_MCOUNT, flag_pic ? "@plt" : "");
22695       break;
22696 
22697     case ABI_AIX:
22698     case ABI_DARWIN:
22699       if (!TARGET_PROFILE_KERNEL)
22700 	{
22701 	  /* Don't do anything, done in output_profile_hook ().  */
22702 	}
22703       else
22704 	{
22705 	  gcc_assert (!TARGET_32BIT);
22706 
22707 	  asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
22708 	  asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
22709 
22710 	  if (cfun->static_chain_decl != NULL)
22711 	    {
22712 	      asm_fprintf (file, "\tstd %s,24(%s)\n",
22713 			   reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
22714 	      fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
22715 	      asm_fprintf (file, "\tld %s,24(%s)\n",
22716 			   reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
22717 	    }
22718 	  else
22719 	    fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
22720 	}
22721       break;
22722     }
22723 }
22724 
22725 
22726 
22727 /* The following variable value is the last issued insn.  */
22728 
22729 static rtx last_scheduled_insn;
22730 
22731 /* The following variable helps to balance issuing of load and
22732    store instructions */
22733 
22734 static int load_store_pendulum;
22735 
22736 /* Power4 load update and store update instructions are cracked into a
22737    load or store and an integer insn which are executed in the same cycle.
22738    Branches have their own dispatch slot which does not count against the
22739    GCC issue rate, but it changes the program flow so there are no other
22740    instructions to issue in this cycle.  */
22741 
22742 static int
rs6000_variable_issue_1(rtx insn,int more)22743 rs6000_variable_issue_1 (rtx insn, int more)
22744 {
22745   last_scheduled_insn = insn;
22746   if (GET_CODE (PATTERN (insn)) == USE
22747       || GET_CODE (PATTERN (insn)) == CLOBBER)
22748     {
22749       cached_can_issue_more = more;
22750       return cached_can_issue_more;
22751     }
22752 
22753   if (insn_terminates_group_p (insn, current_group))
22754     {
22755       cached_can_issue_more = 0;
22756       return cached_can_issue_more;
22757     }
22758 
22759   /* If no reservation, but reach here */
22760   if (recog_memoized (insn) < 0)
22761     return more;
22762 
22763   if (rs6000_sched_groups)
22764     {
22765       if (is_microcoded_insn (insn))
22766         cached_can_issue_more = 0;
22767       else if (is_cracked_insn (insn))
22768         cached_can_issue_more = more > 2 ? more - 2 : 0;
22769       else
22770         cached_can_issue_more = more - 1;
22771 
22772       return cached_can_issue_more;
22773     }
22774 
22775   if (rs6000_cpu_attr == CPU_CELL && is_nonpipeline_insn (insn))
22776     return 0;
22777 
22778   cached_can_issue_more = more - 1;
22779   return cached_can_issue_more;
22780 }
22781 
22782 static int
rs6000_variable_issue(FILE * stream,int verbose,rtx insn,int more)22783 rs6000_variable_issue (FILE *stream, int verbose, rtx insn, int more)
22784 {
22785   int r = rs6000_variable_issue_1 (insn, more);
22786   if (verbose)
22787     fprintf (stream, "// rs6000_variable_issue (more = %d) = %d\n", more, r);
22788   return r;
22789 }
22790 
22791 /* Adjust the cost of a scheduling dependency.  Return the new cost of
22792    a dependency LINK or INSN on DEP_INSN.  COST is the current cost.  */
22793 
22794 static int
rs6000_adjust_cost(rtx insn,rtx link,rtx dep_insn,int cost)22795 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
22796 {
22797   enum attr_type attr_type;
22798 
22799   if (! recog_memoized (insn))
22800     return 0;
22801 
22802   switch (REG_NOTE_KIND (link))
22803     {
22804     case REG_DEP_TRUE:
22805       {
22806         /* Data dependency; DEP_INSN writes a register that INSN reads
22807 	   some cycles later.  */
22808 
22809 	/* Separate a load from a narrower, dependent store.  */
22810 	if (rs6000_sched_groups
22811 	    && GET_CODE (PATTERN (insn)) == SET
22812 	    && GET_CODE (PATTERN (dep_insn)) == SET
22813 	    && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
22814 	    && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
22815 	    && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
22816 		> GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
22817 	  return cost + 14;
22818 
22819         attr_type = get_attr_type (insn);
22820 
22821         switch (attr_type)
22822           {
22823           case TYPE_JMPREG:
22824             /* Tell the first scheduling pass about the latency between
22825                a mtctr and bctr (and mtlr and br/blr).  The first
22826                scheduling pass will not know about this latency since
22827                the mtctr instruction, which has the latency associated
22828                to it, will be generated by reload.  */
22829             return 4;
22830           case TYPE_BRANCH:
22831             /* Leave some extra cycles between a compare and its
22832                dependent branch, to inhibit expensive mispredicts.  */
22833             if ((rs6000_cpu_attr == CPU_PPC603
22834                  || rs6000_cpu_attr == CPU_PPC604
22835                  || rs6000_cpu_attr == CPU_PPC604E
22836                  || rs6000_cpu_attr == CPU_PPC620
22837                  || rs6000_cpu_attr == CPU_PPC630
22838                  || rs6000_cpu_attr == CPU_PPC750
22839                  || rs6000_cpu_attr == CPU_PPC7400
22840                  || rs6000_cpu_attr == CPU_PPC7450
22841                  || rs6000_cpu_attr == CPU_PPCE5500
22842                  || rs6000_cpu_attr == CPU_PPCE6500
22843                  || rs6000_cpu_attr == CPU_POWER4
22844                  || rs6000_cpu_attr == CPU_POWER5
22845 		 || rs6000_cpu_attr == CPU_POWER7
22846                  || rs6000_cpu_attr == CPU_CELL)
22847                 && recog_memoized (dep_insn)
22848                 && (INSN_CODE (dep_insn) >= 0))
22849 
22850               switch (get_attr_type (dep_insn))
22851                 {
22852                 case TYPE_CMP:
22853                 case TYPE_COMPARE:
22854                 case TYPE_DELAYED_COMPARE:
22855                 case TYPE_IMUL_COMPARE:
22856                 case TYPE_LMUL_COMPARE:
22857                 case TYPE_FPCOMPARE:
22858                 case TYPE_CR_LOGICAL:
22859                 case TYPE_DELAYED_CR:
22860 		  return cost + 2;
22861 		default:
22862 		  break;
22863 		}
22864             break;
22865 
22866           case TYPE_STORE:
22867           case TYPE_STORE_U:
22868           case TYPE_STORE_UX:
22869           case TYPE_FPSTORE:
22870           case TYPE_FPSTORE_U:
22871           case TYPE_FPSTORE_UX:
22872             if ((rs6000_cpu == PROCESSOR_POWER6)
22873                 && recog_memoized (dep_insn)
22874                 && (INSN_CODE (dep_insn) >= 0))
22875               {
22876 
22877                 if (GET_CODE (PATTERN (insn)) != SET)
22878                   /* If this happens, we have to extend this to schedule
22879                      optimally.  Return default for now.  */
22880                   return cost;
22881 
22882                 /* Adjust the cost for the case where the value written
22883                    by a fixed point operation is used as the address
22884                    gen value on a store. */
22885                 switch (get_attr_type (dep_insn))
22886                   {
22887                   case TYPE_LOAD:
22888                   case TYPE_LOAD_U:
22889                   case TYPE_LOAD_UX:
22890                   case TYPE_CNTLZ:
22891                     {
22892                       if (! store_data_bypass_p (dep_insn, insn))
22893                         return 4;
22894                       break;
22895                     }
22896                   case TYPE_LOAD_EXT:
22897                   case TYPE_LOAD_EXT_U:
22898                   case TYPE_LOAD_EXT_UX:
22899                   case TYPE_VAR_SHIFT_ROTATE:
22900                   case TYPE_VAR_DELAYED_COMPARE:
22901                     {
22902                       if (! store_data_bypass_p (dep_insn, insn))
22903                         return 6;
22904                       break;
22905 		    }
22906                   case TYPE_INTEGER:
22907                   case TYPE_COMPARE:
22908                   case TYPE_FAST_COMPARE:
22909                   case TYPE_EXTS:
22910                   case TYPE_SHIFT:
22911                   case TYPE_INSERT_WORD:
22912                   case TYPE_INSERT_DWORD:
22913                   case TYPE_FPLOAD_U:
22914                   case TYPE_FPLOAD_UX:
22915                   case TYPE_STORE_U:
22916                   case TYPE_STORE_UX:
22917                   case TYPE_FPSTORE_U:
22918                   case TYPE_FPSTORE_UX:
22919                     {
22920                       if (! store_data_bypass_p (dep_insn, insn))
22921                         return 3;
22922                       break;
22923                     }
22924                   case TYPE_IMUL:
22925                   case TYPE_IMUL2:
22926                   case TYPE_IMUL3:
22927                   case TYPE_LMUL:
22928                   case TYPE_IMUL_COMPARE:
22929                   case TYPE_LMUL_COMPARE:
22930                     {
22931                       if (! store_data_bypass_p (dep_insn, insn))
22932                         return 17;
22933                       break;
22934                     }
22935                   case TYPE_IDIV:
22936                     {
22937                       if (! store_data_bypass_p (dep_insn, insn))
22938                         return 45;
22939                       break;
22940                     }
22941                   case TYPE_LDIV:
22942                     {
22943                       if (! store_data_bypass_p (dep_insn, insn))
22944                         return 57;
22945                       break;
22946                     }
22947                   default:
22948                     break;
22949                   }
22950               }
22951 	    break;
22952 
22953           case TYPE_LOAD:
22954           case TYPE_LOAD_U:
22955           case TYPE_LOAD_UX:
22956           case TYPE_LOAD_EXT:
22957           case TYPE_LOAD_EXT_U:
22958           case TYPE_LOAD_EXT_UX:
22959             if ((rs6000_cpu == PROCESSOR_POWER6)
22960                 && recog_memoized (dep_insn)
22961                 && (INSN_CODE (dep_insn) >= 0))
22962               {
22963 
22964                 /* Adjust the cost for the case where the value written
22965                    by a fixed point instruction is used within the address
22966                    gen portion of a subsequent load(u)(x) */
22967                 switch (get_attr_type (dep_insn))
22968                   {
22969                   case TYPE_LOAD:
22970                   case TYPE_LOAD_U:
22971                   case TYPE_LOAD_UX:
22972                   case TYPE_CNTLZ:
22973                     {
22974                       if (set_to_load_agen (dep_insn, insn))
22975                         return 4;
22976                       break;
22977                     }
22978                   case TYPE_LOAD_EXT:
22979                   case TYPE_LOAD_EXT_U:
22980                   case TYPE_LOAD_EXT_UX:
22981                   case TYPE_VAR_SHIFT_ROTATE:
22982                   case TYPE_VAR_DELAYED_COMPARE:
22983                     {
22984                       if (set_to_load_agen (dep_insn, insn))
22985                         return 6;
22986                       break;
22987                     }
22988                   case TYPE_INTEGER:
22989                   case TYPE_COMPARE:
22990                   case TYPE_FAST_COMPARE:
22991                   case TYPE_EXTS:
22992                   case TYPE_SHIFT:
22993                   case TYPE_INSERT_WORD:
22994                   case TYPE_INSERT_DWORD:
22995                   case TYPE_FPLOAD_U:
22996                   case TYPE_FPLOAD_UX:
22997                   case TYPE_STORE_U:
22998                   case TYPE_STORE_UX:
22999                   case TYPE_FPSTORE_U:
23000                   case TYPE_FPSTORE_UX:
23001                     {
23002                       if (set_to_load_agen (dep_insn, insn))
23003                         return 3;
23004                       break;
23005                     }
23006                   case TYPE_IMUL:
23007                   case TYPE_IMUL2:
23008                   case TYPE_IMUL3:
23009                   case TYPE_LMUL:
23010                   case TYPE_IMUL_COMPARE:
23011                   case TYPE_LMUL_COMPARE:
23012                     {
23013                       if (set_to_load_agen (dep_insn, insn))
23014                         return 17;
23015                       break;
23016                     }
23017                   case TYPE_IDIV:
23018                     {
23019                       if (set_to_load_agen (dep_insn, insn))
23020                         return 45;
23021                       break;
23022                     }
23023                   case TYPE_LDIV:
23024                     {
23025                       if (set_to_load_agen (dep_insn, insn))
23026                         return 57;
23027                       break;
23028                     }
23029                   default:
23030                     break;
23031                   }
23032               }
23033             break;
23034 
23035           case TYPE_FPLOAD:
23036             if ((rs6000_cpu == PROCESSOR_POWER6)
23037                 && recog_memoized (dep_insn)
23038                 && (INSN_CODE (dep_insn) >= 0)
23039                 && (get_attr_type (dep_insn) == TYPE_MFFGPR))
23040               return 2;
23041 
23042           default:
23043             break;
23044           }
23045 
23046 	/* Fall out to return default cost.  */
23047       }
23048       break;
23049 
23050     case REG_DEP_OUTPUT:
23051       /* Output dependency; DEP_INSN writes a register that INSN writes some
23052 	 cycles later.  */
23053       if ((rs6000_cpu == PROCESSOR_POWER6)
23054           && recog_memoized (dep_insn)
23055           && (INSN_CODE (dep_insn) >= 0))
23056         {
23057           attr_type = get_attr_type (insn);
23058 
23059           switch (attr_type)
23060             {
23061             case TYPE_FP:
23062               if (get_attr_type (dep_insn) == TYPE_FP)
23063                 return 1;
23064               break;
23065             case TYPE_FPLOAD:
23066               if (get_attr_type (dep_insn) == TYPE_MFFGPR)
23067                 return 2;
23068               break;
23069             default:
23070               break;
23071             }
23072         }
23073     case REG_DEP_ANTI:
23074       /* Anti dependency; DEP_INSN reads a register that INSN writes some
23075 	 cycles later.  */
23076       return 0;
23077 
23078     default:
23079       gcc_unreachable ();
23080     }
23081 
23082   return cost;
23083 }
23084 
23085 /* Debug version of rs6000_adjust_cost.  */
23086 
23087 static int
rs6000_debug_adjust_cost(rtx insn,rtx link,rtx dep_insn,int cost)23088 rs6000_debug_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
23089 {
23090   int ret = rs6000_adjust_cost (insn, link, dep_insn, cost);
23091 
23092   if (ret != cost)
23093     {
23094       const char *dep;
23095 
23096       switch (REG_NOTE_KIND (link))
23097 	{
23098 	default:	     dep = "unknown depencency"; break;
23099 	case REG_DEP_TRUE:   dep = "data dependency";	 break;
23100 	case REG_DEP_OUTPUT: dep = "output dependency";  break;
23101 	case REG_DEP_ANTI:   dep = "anti depencency";	 break;
23102 	}
23103 
23104       fprintf (stderr,
23105 	       "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
23106 	       "%s, insn:\n", ret, cost, dep);
23107 
23108       debug_rtx (insn);
23109     }
23110 
23111   return ret;
23112 }
23113 
23114 /* The function returns a true if INSN is microcoded.
23115    Return false otherwise.  */
23116 
23117 static bool
is_microcoded_insn(rtx insn)23118 is_microcoded_insn (rtx insn)
23119 {
23120   if (!insn || !NONDEBUG_INSN_P (insn)
23121       || GET_CODE (PATTERN (insn)) == USE
23122       || GET_CODE (PATTERN (insn)) == CLOBBER)
23123     return false;
23124 
23125   if (rs6000_cpu_attr == CPU_CELL)
23126     return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;
23127 
23128   if (rs6000_sched_groups)
23129     {
23130       enum attr_type type = get_attr_type (insn);
23131       if (type == TYPE_LOAD_EXT_U
23132 	  || type == TYPE_LOAD_EXT_UX
23133 	  || type == TYPE_LOAD_UX
23134 	  || type == TYPE_STORE_UX
23135 	  || type == TYPE_MFCR)
23136 	return true;
23137     }
23138 
23139   return false;
23140 }
23141 
23142 /* The function returns true if INSN is cracked into 2 instructions
23143    by the processor (and therefore occupies 2 issue slots).  */
23144 
23145 static bool
is_cracked_insn(rtx insn)23146 is_cracked_insn (rtx insn)
23147 {
23148   if (!insn || !NONDEBUG_INSN_P (insn)
23149       || GET_CODE (PATTERN (insn)) == USE
23150       || GET_CODE (PATTERN (insn)) == CLOBBER)
23151     return false;
23152 
23153   if (rs6000_sched_groups)
23154     {
23155       enum attr_type type = get_attr_type (insn);
23156       if (type == TYPE_LOAD_U || type == TYPE_STORE_U
23157 	  || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
23158 	  || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
23159 	  || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
23160 	  || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
23161 	  || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
23162 	  || type == TYPE_IDIV || type == TYPE_LDIV
23163 	  || type == TYPE_INSERT_WORD)
23164 	return true;
23165     }
23166 
23167   return false;
23168 }
23169 
23170 /* The function returns true if INSN can be issued only from
23171    the branch slot.  */
23172 
23173 static bool
is_branch_slot_insn(rtx insn)23174 is_branch_slot_insn (rtx insn)
23175 {
23176   if (!insn || !NONDEBUG_INSN_P (insn)
23177       || GET_CODE (PATTERN (insn)) == USE
23178       || GET_CODE (PATTERN (insn)) == CLOBBER)
23179     return false;
23180 
23181   if (rs6000_sched_groups)
23182     {
23183       enum attr_type type = get_attr_type (insn);
23184       if (type == TYPE_BRANCH || type == TYPE_JMPREG)
23185 	return true;
23186       return false;
23187     }
23188 
23189   return false;
23190 }
23191 
23192 /* The function returns true if out_inst sets a value that is
23193    used in the address generation computation of in_insn */
23194 static bool
set_to_load_agen(rtx out_insn,rtx in_insn)23195 set_to_load_agen (rtx out_insn, rtx in_insn)
23196 {
23197   rtx out_set, in_set;
23198 
23199   /* For performance reasons, only handle the simple case where
23200      both loads are a single_set. */
23201   out_set = single_set (out_insn);
23202   if (out_set)
23203     {
23204       in_set = single_set (in_insn);
23205       if (in_set)
23206         return reg_mentioned_p (SET_DEST (out_set), SET_SRC (in_set));
23207     }
23208 
23209   return false;
23210 }
23211 
23212 /* Try to determine base/offset/size parts of the given MEM.
23213    Return true if successful, false if all the values couldn't
23214    be determined.
23215 
23216    This function only looks for REG or REG+CONST address forms.
23217    REG+REG address form will return false. */
23218 
23219 static bool
get_memref_parts(rtx mem,rtx * base,HOST_WIDE_INT * offset,HOST_WIDE_INT * size)23220 get_memref_parts (rtx mem, rtx *base, HOST_WIDE_INT *offset,
23221 		  HOST_WIDE_INT *size)
23222 {
23223   rtx addr_rtx;
23224   if MEM_SIZE_KNOWN_P (mem)
23225     *size = MEM_SIZE (mem);
23226   else
23227     return false;
23228 
23229   if (GET_CODE (XEXP (mem, 0)) == PRE_MODIFY)
23230     addr_rtx = XEXP (XEXP (mem, 0), 1);
23231   else
23232     addr_rtx = (XEXP (mem, 0));
23233 
23234   if (GET_CODE (addr_rtx) == REG)
23235     {
23236       *base = addr_rtx;
23237       *offset = 0;
23238     }
23239   else if (GET_CODE (addr_rtx) == PLUS
23240 	   && CONST_INT_P (XEXP (addr_rtx, 1)))
23241     {
23242       *base = XEXP (addr_rtx, 0);
23243       *offset = INTVAL (XEXP (addr_rtx, 1));
23244     }
23245   else
23246     return false;
23247 
23248   return true;
23249 }
23250 
23251 /* The function returns true if the target storage location of
23252    mem1 is adjacent to the target storage location of mem2 */
23253 /* Return 1 if memory locations are adjacent.  */
23254 
23255 static bool
adjacent_mem_locations(rtx mem1,rtx mem2)23256 adjacent_mem_locations (rtx mem1, rtx mem2)
23257 {
23258   rtx reg1, reg2;
23259   HOST_WIDE_INT off1, size1, off2, size2;
23260 
23261   if (get_memref_parts (mem1, &reg1, &off1, &size1)
23262       && get_memref_parts (mem2, &reg2, &off2, &size2))
23263     return ((REGNO (reg1) == REGNO (reg2))
23264 	    && ((off1 + size1 == off2)
23265 		|| (off2 + size2 == off1)));
23266 
23267   return false;
23268 }
23269 
23270 /* This function returns true if it can be determined that the two MEM
23271    locations overlap by at least 1 byte based on base reg/offset/size. */
23272 
23273 static bool
mem_locations_overlap(rtx mem1,rtx mem2)23274 mem_locations_overlap (rtx mem1, rtx mem2)
23275 {
23276   rtx reg1, reg2;
23277   HOST_WIDE_INT off1, size1, off2, size2;
23278 
23279   if (get_memref_parts (mem1, &reg1, &off1, &size1)
23280       && get_memref_parts (mem2, &reg2, &off2, &size2))
23281     return ((REGNO (reg1) == REGNO (reg2))
23282 	    && (((off1 <= off2) && (off1 + size1 > off2))
23283 		|| ((off2 <= off1) && (off2 + size2 > off1))));
23284 
23285   return false;
23286 }
23287 
23288 /* A C statement (sans semicolon) to update the integer scheduling
23289    priority INSN_PRIORITY (INSN). Increase the priority to execute the
23290    INSN earlier, reduce the priority to execute INSN later.  Do not
23291    define this macro if you do not need to adjust the scheduling
23292    priorities of insns.  */
23293 
23294 static int
rs6000_adjust_priority(rtx insn ATTRIBUTE_UNUSED,int priority)23295 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
23296 {
23297   rtx load_mem, str_mem;
23298   /* On machines (like the 750) which have asymmetric integer units,
23299      where one integer unit can do multiply and divides and the other
23300      can't, reduce the priority of multiply/divide so it is scheduled
23301      before other integer operations.  */
23302 
23303 #if 0
23304   if (! INSN_P (insn))
23305     return priority;
23306 
23307   if (GET_CODE (PATTERN (insn)) == USE)
23308     return priority;
23309 
23310   switch (rs6000_cpu_attr) {
23311   case CPU_PPC750:
23312     switch (get_attr_type (insn))
23313       {
23314       default:
23315 	break;
23316 
23317       case TYPE_IMUL:
23318       case TYPE_IDIV:
23319 	fprintf (stderr, "priority was %#x (%d) before adjustment\n",
23320 		 priority, priority);
23321 	if (priority >= 0 && priority < 0x01000000)
23322 	  priority >>= 3;
23323 	break;
23324       }
23325   }
23326 #endif
23327 
23328   if (insn_must_be_first_in_group (insn)
23329       && reload_completed
23330       && current_sched_info->sched_max_insns_priority
23331       && rs6000_sched_restricted_insns_priority)
23332     {
23333 
23334       /* Prioritize insns that can be dispatched only in the first
23335 	 dispatch slot.  */
23336       if (rs6000_sched_restricted_insns_priority == 1)
23337 	/* Attach highest priority to insn. This means that in
23338 	   haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
23339 	   precede 'priority' (critical path) considerations.  */
23340 	return current_sched_info->sched_max_insns_priority;
23341       else if (rs6000_sched_restricted_insns_priority == 2)
23342 	/* Increase priority of insn by a minimal amount. This means that in
23343 	   haifa-sched.c:ready_sort(), only 'priority' (critical path)
23344 	   considerations precede dispatch-slot restriction considerations.  */
23345 	return (priority + 1);
23346     }
23347 
23348   if (rs6000_cpu == PROCESSOR_POWER6
23349       && ((load_store_pendulum == -2 && is_load_insn (insn, &load_mem))
23350           || (load_store_pendulum == 2 && is_store_insn (insn, &str_mem))))
23351     /* Attach highest priority to insn if the scheduler has just issued two
23352        stores and this instruction is a load, or two loads and this instruction
23353        is a store. Power6 wants loads and stores scheduled alternately
23354        when possible */
23355     return current_sched_info->sched_max_insns_priority;
23356 
23357   return priority;
23358 }
23359 
23360 /* Return true if the instruction is nonpipelined on the Cell. */
23361 static bool
is_nonpipeline_insn(rtx insn)23362 is_nonpipeline_insn (rtx insn)
23363 {
23364   enum attr_type type;
23365   if (!insn || !NONDEBUG_INSN_P (insn)
23366       || GET_CODE (PATTERN (insn)) == USE
23367       || GET_CODE (PATTERN (insn)) == CLOBBER)
23368     return false;
23369 
23370   type = get_attr_type (insn);
23371   if (type == TYPE_IMUL
23372       || type == TYPE_IMUL2
23373       || type == TYPE_IMUL3
23374       || type == TYPE_LMUL
23375       || type == TYPE_IDIV
23376       || type == TYPE_LDIV
23377       || type == TYPE_SDIV
23378       || type == TYPE_DDIV
23379       || type == TYPE_SSQRT
23380       || type == TYPE_DSQRT
23381       || type == TYPE_MFCR
23382       || type == TYPE_MFCRF
23383       || type == TYPE_MFJMPR)
23384     {
23385       return true;
23386     }
23387   return false;
23388 }
23389 
23390 
23391 /* Return how many instructions the machine can issue per cycle.  */
23392 
23393 static int
rs6000_issue_rate(void)23394 rs6000_issue_rate (void)
23395 {
23396   /* Unless scheduling for register pressure, use issue rate of 1 for
23397      first scheduling pass to decrease degradation.  */
23398   if (!reload_completed && !flag_sched_pressure)
23399     return 1;
23400 
23401   switch (rs6000_cpu_attr) {
23402   case CPU_RS64A:
23403   case CPU_PPC601: /* ? */
23404   case CPU_PPC7450:
23405     return 3;
23406   case CPU_PPC440:
23407   case CPU_PPC603:
23408   case CPU_PPC750:
23409   case CPU_PPC7400:
23410   case CPU_PPC8540:
23411   case CPU_PPC8548:
23412   case CPU_CELL:
23413   case CPU_PPCE300C2:
23414   case CPU_PPCE300C3:
23415   case CPU_PPCE500MC:
23416   case CPU_PPCE500MC64:
23417   case CPU_PPCE5500:
23418   case CPU_PPCE6500:
23419   case CPU_TITAN:
23420     return 2;
23421   case CPU_PPC476:
23422   case CPU_PPC604:
23423   case CPU_PPC604E:
23424   case CPU_PPC620:
23425   case CPU_PPC630:
23426     return 4;
23427   case CPU_POWER4:
23428   case CPU_POWER5:
23429   case CPU_POWER6:
23430   case CPU_POWER7:
23431     return 5;
23432   default:
23433     return 1;
23434   }
23435 }
23436 
23437 /* Return how many instructions to look ahead for better insn
23438    scheduling.  */
23439 
23440 static int
rs6000_use_sched_lookahead(void)23441 rs6000_use_sched_lookahead (void)
23442 {
23443   switch (rs6000_cpu_attr)
23444     {
23445     case CPU_PPC8540:
23446     case CPU_PPC8548:
23447       return 4;
23448 
23449     case CPU_CELL:
23450       return (reload_completed ? 8 : 0);
23451 
23452     default:
23453       return 0;
23454     }
23455 }
23456 
23457 /* We are choosing insn from the ready queue.  Return nonzero if INSN can be chosen.  */
23458 static int
rs6000_use_sched_lookahead_guard(rtx insn)23459 rs6000_use_sched_lookahead_guard (rtx insn)
23460 {
23461   if (rs6000_cpu_attr != CPU_CELL)
23462     return 1;
23463 
23464    if (insn == NULL_RTX || !INSN_P (insn))
23465      abort ();
23466 
23467   if (!reload_completed
23468       || is_nonpipeline_insn (insn)
23469       || is_microcoded_insn (insn))
23470     return 0;
23471 
23472   return 1;
23473 }
23474 
23475 /* Determine if PAT refers to memory. If so, set MEM_REF to the MEM rtx
23476    and return true.  */
23477 
23478 static bool
find_mem_ref(rtx pat,rtx * mem_ref)23479 find_mem_ref (rtx pat, rtx *mem_ref)
23480 {
23481   const char * fmt;
23482   int i, j;
23483 
23484   /* stack_tie does not produce any real memory traffic.  */
23485   if (tie_operand (pat, VOIDmode))
23486     return false;
23487 
23488   if (GET_CODE (pat) == MEM)
23489     {
23490       *mem_ref = pat;
23491       return true;
23492     }
23493 
23494   /* Recursively process the pattern.  */
23495   fmt = GET_RTX_FORMAT (GET_CODE (pat));
23496 
23497   for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0; i--)
23498     {
23499       if (fmt[i] == 'e')
23500 	{
23501 	  if (find_mem_ref (XEXP (pat, i), mem_ref))
23502 	    return true;
23503 	}
23504       else if (fmt[i] == 'E')
23505 	for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
23506 	  {
23507 	    if (find_mem_ref (XVECEXP (pat, i, j), mem_ref))
23508 	      return true;
23509 	  }
23510     }
23511 
23512   return false;
23513 }
23514 
23515 /* Determine if PAT is a PATTERN of a load insn.  */
23516 
23517 static bool
is_load_insn1(rtx pat,rtx * load_mem)23518 is_load_insn1 (rtx pat, rtx *load_mem)
23519 {
23520   if (!pat || pat == NULL_RTX)
23521     return false;
23522 
23523   if (GET_CODE (pat) == SET)
23524     return find_mem_ref (SET_SRC (pat), load_mem);
23525 
23526   if (GET_CODE (pat) == PARALLEL)
23527     {
23528       int i;
23529 
23530       for (i = 0; i < XVECLEN (pat, 0); i++)
23531 	if (is_load_insn1 (XVECEXP (pat, 0, i), load_mem))
23532 	  return true;
23533     }
23534 
23535   return false;
23536 }
23537 
23538 /* Determine if INSN loads from memory.  */
23539 
23540 static bool
is_load_insn(rtx insn,rtx * load_mem)23541 is_load_insn (rtx insn, rtx *load_mem)
23542 {
23543   if (!insn || !INSN_P (insn))
23544     return false;
23545 
23546   if (GET_CODE (insn) == CALL_INSN)
23547     return false;
23548 
23549   return is_load_insn1 (PATTERN (insn), load_mem);
23550 }
23551 
23552 /* Determine if PAT is a PATTERN of a store insn.  */
23553 
23554 static bool
is_store_insn1(rtx pat,rtx * str_mem)23555 is_store_insn1 (rtx pat, rtx *str_mem)
23556 {
23557   if (!pat || pat == NULL_RTX)
23558     return false;
23559 
23560   if (GET_CODE (pat) == SET)
23561     return find_mem_ref (SET_DEST (pat), str_mem);
23562 
23563   if (GET_CODE (pat) == PARALLEL)
23564     {
23565       int i;
23566 
23567       for (i = 0; i < XVECLEN (pat, 0); i++)
23568 	if (is_store_insn1 (XVECEXP (pat, 0, i), str_mem))
23569 	  return true;
23570     }
23571 
23572   return false;
23573 }
23574 
23575 /* Determine if INSN stores to memory.  */
23576 
23577 static bool
is_store_insn(rtx insn,rtx * str_mem)23578 is_store_insn (rtx insn, rtx *str_mem)
23579 {
23580   if (!insn || !INSN_P (insn))
23581     return false;
23582 
23583   return is_store_insn1 (PATTERN (insn), str_mem);
23584 }
23585 
23586 /* Returns whether the dependence between INSN and NEXT is considered
23587    costly by the given target.  */
23588 
23589 static bool
rs6000_is_costly_dependence(dep_t dep,int cost,int distance)23590 rs6000_is_costly_dependence (dep_t dep, int cost, int distance)
23591 {
23592   rtx insn;
23593   rtx next;
23594   rtx load_mem, str_mem;
23595 
23596   /* If the flag is not enabled - no dependence is considered costly;
23597      allow all dependent insns in the same group.
23598      This is the most aggressive option.  */
23599   if (rs6000_sched_costly_dep == no_dep_costly)
23600     return false;
23601 
23602   /* If the flag is set to 1 - a dependence is always considered costly;
23603      do not allow dependent instructions in the same group.
23604      This is the most conservative option.  */
23605   if (rs6000_sched_costly_dep == all_deps_costly)
23606     return true;
23607 
23608   insn = DEP_PRO (dep);
23609   next = DEP_CON (dep);
23610 
23611   if (rs6000_sched_costly_dep == store_to_load_dep_costly
23612       && is_load_insn (next, &load_mem)
23613       && is_store_insn (insn, &str_mem))
23614     /* Prevent load after store in the same group.  */
23615     return true;
23616 
23617   if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
23618       && is_load_insn (next, &load_mem)
23619       && is_store_insn (insn, &str_mem)
23620       && DEP_TYPE (dep) == REG_DEP_TRUE
23621       && mem_locations_overlap(str_mem, load_mem))
23622      /* Prevent load after store in the same group if it is a true
23623 	dependence.  */
23624      return true;
23625 
23626   /* The flag is set to X; dependences with latency >= X are considered costly,
23627      and will not be scheduled in the same group.  */
23628   if (rs6000_sched_costly_dep <= max_dep_latency
23629       && ((cost - distance) >= (int)rs6000_sched_costly_dep))
23630     return true;
23631 
23632   return false;
23633 }
23634 
23635 /* Return the next insn after INSN that is found before TAIL is reached,
23636    skipping any "non-active" insns - insns that will not actually occupy
23637    an issue slot.  Return NULL_RTX if such an insn is not found.  */
23638 
23639 static rtx
get_next_active_insn(rtx insn,rtx tail)23640 get_next_active_insn (rtx insn, rtx tail)
23641 {
23642   if (insn == NULL_RTX || insn == tail)
23643     return NULL_RTX;
23644 
23645   while (1)
23646     {
23647       insn = NEXT_INSN (insn);
23648       if (insn == NULL_RTX || insn == tail)
23649 	return NULL_RTX;
23650 
23651       if (CALL_P (insn)
23652 	  || JUMP_P (insn)
23653 	  || (NONJUMP_INSN_P (insn)
23654 	      && GET_CODE (PATTERN (insn)) != USE
23655 	      && GET_CODE (PATTERN (insn)) != CLOBBER
23656 	      && INSN_CODE (insn) != CODE_FOR_stack_tie))
23657 	break;
23658     }
23659   return insn;
23660 }
23661 
23662 /* We are about to begin issuing insns for this clock cycle. */
23663 
23664 static int
rs6000_sched_reorder(FILE * dump ATTRIBUTE_UNUSED,int sched_verbose,rtx * ready ATTRIBUTE_UNUSED,int * pn_ready ATTRIBUTE_UNUSED,int clock_var ATTRIBUTE_UNUSED)23665 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose,
23666                         rtx *ready ATTRIBUTE_UNUSED,
23667                         int *pn_ready ATTRIBUTE_UNUSED,
23668 		        int clock_var ATTRIBUTE_UNUSED)
23669 {
23670   int n_ready = *pn_ready;
23671 
23672   if (sched_verbose)
23673     fprintf (dump, "// rs6000_sched_reorder :\n");
23674 
23675   /* Reorder the ready list, if the second to last ready insn
23676      is a nonepipeline insn.  */
23677   if (rs6000_cpu_attr == CPU_CELL && n_ready > 1)
23678   {
23679     if (is_nonpipeline_insn (ready[n_ready - 1])
23680         && (recog_memoized (ready[n_ready - 2]) > 0))
23681       /* Simply swap first two insns.  */
23682       {
23683 	rtx tmp = ready[n_ready - 1];
23684 	ready[n_ready - 1] = ready[n_ready - 2];
23685 	ready[n_ready - 2] = tmp;
23686       }
23687   }
23688 
23689   if (rs6000_cpu == PROCESSOR_POWER6)
23690     load_store_pendulum = 0;
23691 
23692   return rs6000_issue_rate ();
23693 }
23694 
23695 /* Like rs6000_sched_reorder, but called after issuing each insn.  */
23696 
23697 static int
rs6000_sched_reorder2(FILE * dump,int sched_verbose,rtx * ready,int * pn_ready,int clock_var ATTRIBUTE_UNUSED)23698 rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx *ready,
23699 		         int *pn_ready, int clock_var ATTRIBUTE_UNUSED)
23700 {
23701   if (sched_verbose)
23702     fprintf (dump, "// rs6000_sched_reorder2 :\n");
23703 
23704   /* For Power6, we need to handle some special cases to try and keep the
23705      store queue from overflowing and triggering expensive flushes.
23706 
23707      This code monitors how load and store instructions are being issued
23708      and skews the ready list one way or the other to increase the likelihood
23709      that a desired instruction is issued at the proper time.
23710 
23711      A couple of things are done.  First, we maintain a "load_store_pendulum"
23712      to track the current state of load/store issue.
23713 
23714        - If the pendulum is at zero, then no loads or stores have been
23715          issued in the current cycle so we do nothing.
23716 
23717        - If the pendulum is 1, then a single load has been issued in this
23718          cycle and we attempt to locate another load in the ready list to
23719          issue with it.
23720 
23721        - If the pendulum is -2, then two stores have already been
23722          issued in this cycle, so we increase the priority of the first load
23723          in the ready list to increase it's likelihood of being chosen first
23724          in the next cycle.
23725 
23726        - If the pendulum is -1, then a single store has been issued in this
23727          cycle and we attempt to locate another store in the ready list to
23728          issue with it, preferring a store to an adjacent memory location to
23729          facilitate store pairing in the store queue.
23730 
23731        - If the pendulum is 2, then two loads have already been
23732          issued in this cycle, so we increase the priority of the first store
23733          in the ready list to increase it's likelihood of being chosen first
23734          in the next cycle.
23735 
23736        - If the pendulum < -2 or > 2, then do nothing.
23737 
23738        Note: This code covers the most common scenarios.  There exist non
23739              load/store instructions which make use of the LSU and which
23740              would need to be accounted for to strictly model the behavior
23741              of the machine.  Those instructions are currently unaccounted
23742              for to help minimize compile time overhead of this code.
23743    */
23744   if (rs6000_cpu == PROCESSOR_POWER6 && last_scheduled_insn)
23745     {
23746       int pos;
23747       int i;
23748       rtx tmp, load_mem, str_mem;
23749 
23750       if (is_store_insn (last_scheduled_insn, &str_mem))
23751         /* Issuing a store, swing the load_store_pendulum to the left */
23752         load_store_pendulum--;
23753       else if (is_load_insn (last_scheduled_insn, &load_mem))
23754         /* Issuing a load, swing the load_store_pendulum to the right */
23755         load_store_pendulum++;
23756       else
23757         return cached_can_issue_more;
23758 
23759       /* If the pendulum is balanced, or there is only one instruction on
23760          the ready list, then all is well, so return. */
23761       if ((load_store_pendulum == 0) || (*pn_ready <= 1))
23762         return cached_can_issue_more;
23763 
23764       if (load_store_pendulum == 1)
23765         {
23766           /* A load has been issued in this cycle.  Scan the ready list
23767              for another load to issue with it */
23768           pos = *pn_ready-1;
23769 
23770           while (pos >= 0)
23771             {
23772               if (is_load_insn (ready[pos], &load_mem))
23773                 {
23774                   /* Found a load.  Move it to the head of the ready list,
23775                      and adjust it's priority so that it is more likely to
23776                      stay there */
23777                   tmp = ready[pos];
23778                   for (i=pos; i<*pn_ready-1; i++)
23779                     ready[i] = ready[i + 1];
23780                   ready[*pn_ready-1] = tmp;
23781 
23782                   if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
23783                     INSN_PRIORITY (tmp)++;
23784                   break;
23785                 }
23786               pos--;
23787             }
23788         }
23789       else if (load_store_pendulum == -2)
23790         {
23791           /* Two stores have been issued in this cycle.  Increase the
23792              priority of the first load in the ready list to favor it for
23793              issuing in the next cycle. */
23794           pos = *pn_ready-1;
23795 
23796           while (pos >= 0)
23797             {
23798               if (is_load_insn (ready[pos], &load_mem)
23799                   && !sel_sched_p ()
23800 		  && INSN_PRIORITY_KNOWN (ready[pos]))
23801                 {
23802                   INSN_PRIORITY (ready[pos])++;
23803 
23804                   /* Adjust the pendulum to account for the fact that a load
23805                      was found and increased in priority.  This is to prevent
23806                      increasing the priority of multiple loads */
23807                   load_store_pendulum--;
23808 
23809                   break;
23810                 }
23811               pos--;
23812             }
23813         }
23814       else if (load_store_pendulum == -1)
23815         {
23816           /* A store has been issued in this cycle.  Scan the ready list for
23817              another store to issue with it, preferring a store to an adjacent
23818              memory location */
23819           int first_store_pos = -1;
23820 
23821           pos = *pn_ready-1;
23822 
23823           while (pos >= 0)
23824             {
23825               if (is_store_insn (ready[pos], &str_mem))
23826                 {
23827 		  rtx str_mem2;
23828                   /* Maintain the index of the first store found on the
23829                      list */
23830                   if (first_store_pos == -1)
23831                     first_store_pos = pos;
23832 
23833                   if (is_store_insn (last_scheduled_insn, &str_mem2)
23834                       && adjacent_mem_locations (str_mem, str_mem2))
23835                     {
23836                       /* Found an adjacent store.  Move it to the head of the
23837                          ready list, and adjust it's priority so that it is
23838                          more likely to stay there */
23839                       tmp = ready[pos];
23840                       for (i=pos; i<*pn_ready-1; i++)
23841                         ready[i] = ready[i + 1];
23842                       ready[*pn_ready-1] = tmp;
23843 
23844                       if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
23845                         INSN_PRIORITY (tmp)++;
23846 
23847                       first_store_pos = -1;
23848 
23849                       break;
23850                     };
23851                 }
23852               pos--;
23853             }
23854 
23855           if (first_store_pos >= 0)
23856             {
23857               /* An adjacent store wasn't found, but a non-adjacent store was,
23858                  so move the non-adjacent store to the front of the ready
23859                  list, and adjust its priority so that it is more likely to
23860                  stay there. */
23861               tmp = ready[first_store_pos];
23862               for (i=first_store_pos; i<*pn_ready-1; i++)
23863                 ready[i] = ready[i + 1];
23864               ready[*pn_ready-1] = tmp;
23865               if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
23866                 INSN_PRIORITY (tmp)++;
23867             }
23868         }
23869       else if (load_store_pendulum == 2)
23870        {
23871            /* Two loads have been issued in this cycle.  Increase the priority
23872               of the first store in the ready list to favor it for issuing in
23873               the next cycle. */
23874           pos = *pn_ready-1;
23875 
23876           while (pos >= 0)
23877             {
23878               if (is_store_insn (ready[pos], &str_mem)
23879                   && !sel_sched_p ()
23880 		  && INSN_PRIORITY_KNOWN (ready[pos]))
23881                 {
23882                   INSN_PRIORITY (ready[pos])++;
23883 
23884                   /* Adjust the pendulum to account for the fact that a store
23885                      was found and increased in priority.  This is to prevent
23886                      increasing the priority of multiple stores */
23887                   load_store_pendulum++;
23888 
23889                   break;
23890                 }
23891               pos--;
23892             }
23893         }
23894     }
23895 
23896   return cached_can_issue_more;
23897 }
23898 
23899 /* Return whether the presence of INSN causes a dispatch group termination
23900    of group WHICH_GROUP.
23901 
23902    If WHICH_GROUP == current_group, this function will return true if INSN
23903    causes the termination of the current group (i.e, the dispatch group to
23904    which INSN belongs). This means that INSN will be the last insn in the
23905    group it belongs to.
23906 
23907    If WHICH_GROUP == previous_group, this function will return true if INSN
23908    causes the termination of the previous group (i.e, the dispatch group that
23909    precedes the group to which INSN belongs).  This means that INSN will be
23910    the first insn in the group it belongs to).  */
23911 
23912 static bool
insn_terminates_group_p(rtx insn,enum group_termination which_group)23913 insn_terminates_group_p (rtx insn, enum group_termination which_group)
23914 {
23915   bool first, last;
23916 
23917   if (! insn)
23918     return false;
23919 
23920   first = insn_must_be_first_in_group (insn);
23921   last = insn_must_be_last_in_group (insn);
23922 
23923   if (first && last)
23924     return true;
23925 
23926   if (which_group == current_group)
23927     return last;
23928   else if (which_group == previous_group)
23929     return first;
23930 
23931   return false;
23932 }
23933 
23934 
23935 static bool
insn_must_be_first_in_group(rtx insn)23936 insn_must_be_first_in_group (rtx insn)
23937 {
23938   enum attr_type type;
23939 
23940   if (!insn
23941       || GET_CODE (insn) == NOTE
23942       || DEBUG_INSN_P (insn)
23943       || GET_CODE (PATTERN (insn)) == USE
23944       || GET_CODE (PATTERN (insn)) == CLOBBER)
23945     return false;
23946 
23947   switch (rs6000_cpu)
23948     {
23949     case PROCESSOR_POWER5:
23950       if (is_cracked_insn (insn))
23951         return true;
23952     case PROCESSOR_POWER4:
23953       if (is_microcoded_insn (insn))
23954         return true;
23955 
23956       if (!rs6000_sched_groups)
23957         return false;
23958 
23959       type = get_attr_type (insn);
23960 
23961       switch (type)
23962         {
23963         case TYPE_MFCR:
23964         case TYPE_MFCRF:
23965         case TYPE_MTCR:
23966         case TYPE_DELAYED_CR:
23967         case TYPE_CR_LOGICAL:
23968         case TYPE_MTJMPR:
23969         case TYPE_MFJMPR:
23970         case TYPE_IDIV:
23971         case TYPE_LDIV:
23972         case TYPE_LOAD_L:
23973         case TYPE_STORE_C:
23974         case TYPE_ISYNC:
23975         case TYPE_SYNC:
23976           return true;
23977         default:
23978           break;
23979         }
23980       break;
23981     case PROCESSOR_POWER6:
23982       type = get_attr_type (insn);
23983 
23984       switch (type)
23985         {
23986         case TYPE_INSERT_DWORD:
23987         case TYPE_EXTS:
23988         case TYPE_CNTLZ:
23989         case TYPE_SHIFT:
23990         case TYPE_VAR_SHIFT_ROTATE:
23991         case TYPE_TRAP:
23992         case TYPE_IMUL:
23993         case TYPE_IMUL2:
23994         case TYPE_IMUL3:
23995         case TYPE_LMUL:
23996         case TYPE_IDIV:
23997         case TYPE_INSERT_WORD:
23998         case TYPE_DELAYED_COMPARE:
23999         case TYPE_IMUL_COMPARE:
24000         case TYPE_LMUL_COMPARE:
24001         case TYPE_FPCOMPARE:
24002         case TYPE_MFCR:
24003         case TYPE_MTCR:
24004         case TYPE_MFJMPR:
24005         case TYPE_MTJMPR:
24006         case TYPE_ISYNC:
24007         case TYPE_SYNC:
24008         case TYPE_LOAD_L:
24009         case TYPE_STORE_C:
24010         case TYPE_LOAD_U:
24011         case TYPE_LOAD_UX:
24012         case TYPE_LOAD_EXT_UX:
24013         case TYPE_STORE_U:
24014         case TYPE_STORE_UX:
24015         case TYPE_FPLOAD_U:
24016         case TYPE_FPLOAD_UX:
24017         case TYPE_FPSTORE_U:
24018         case TYPE_FPSTORE_UX:
24019           return true;
24020         default:
24021           break;
24022         }
24023       break;
24024     case PROCESSOR_POWER7:
24025       type = get_attr_type (insn);
24026 
24027       switch (type)
24028         {
24029         case TYPE_CR_LOGICAL:
24030         case TYPE_MFCR:
24031         case TYPE_MFCRF:
24032         case TYPE_MTCR:
24033         case TYPE_IDIV:
24034         case TYPE_LDIV:
24035         case TYPE_COMPARE:
24036         case TYPE_DELAYED_COMPARE:
24037         case TYPE_VAR_DELAYED_COMPARE:
24038         case TYPE_ISYNC:
24039         case TYPE_LOAD_L:
24040         case TYPE_STORE_C:
24041         case TYPE_LOAD_U:
24042         case TYPE_LOAD_UX:
24043         case TYPE_LOAD_EXT:
24044         case TYPE_LOAD_EXT_U:
24045         case TYPE_LOAD_EXT_UX:
24046         case TYPE_STORE_U:
24047         case TYPE_STORE_UX:
24048         case TYPE_FPLOAD_U:
24049         case TYPE_FPLOAD_UX:
24050         case TYPE_FPSTORE_U:
24051         case TYPE_FPSTORE_UX:
24052         case TYPE_MFJMPR:
24053         case TYPE_MTJMPR:
24054           return true;
24055         default:
24056           break;
24057         }
24058       break;
24059     default:
24060       break;
24061     }
24062 
24063   return false;
24064 }
24065 
24066 static bool
insn_must_be_last_in_group(rtx insn)24067 insn_must_be_last_in_group (rtx insn)
24068 {
24069   enum attr_type type;
24070 
24071   if (!insn
24072       || GET_CODE (insn) == NOTE
24073       || DEBUG_INSN_P (insn)
24074       || GET_CODE (PATTERN (insn)) == USE
24075       || GET_CODE (PATTERN (insn)) == CLOBBER)
24076     return false;
24077 
24078   switch (rs6000_cpu) {
24079   case PROCESSOR_POWER4:
24080   case PROCESSOR_POWER5:
24081     if (is_microcoded_insn (insn))
24082       return true;
24083 
24084     if (is_branch_slot_insn (insn))
24085       return true;
24086 
24087     break;
24088   case PROCESSOR_POWER6:
24089     type = get_attr_type (insn);
24090 
24091     switch (type)
24092       {
24093       case TYPE_EXTS:
24094       case TYPE_CNTLZ:
24095       case TYPE_SHIFT:
24096       case TYPE_VAR_SHIFT_ROTATE:
24097       case TYPE_TRAP:
24098       case TYPE_IMUL:
24099       case TYPE_IMUL2:
24100       case TYPE_IMUL3:
24101       case TYPE_LMUL:
24102       case TYPE_IDIV:
24103       case TYPE_DELAYED_COMPARE:
24104       case TYPE_IMUL_COMPARE:
24105       case TYPE_LMUL_COMPARE:
24106       case TYPE_FPCOMPARE:
24107       case TYPE_MFCR:
24108       case TYPE_MTCR:
24109       case TYPE_MFJMPR:
24110       case TYPE_MTJMPR:
24111       case TYPE_ISYNC:
24112       case TYPE_SYNC:
24113       case TYPE_LOAD_L:
24114       case TYPE_STORE_C:
24115         return true;
24116       default:
24117         break;
24118     }
24119     break;
24120   case PROCESSOR_POWER7:
24121     type = get_attr_type (insn);
24122 
24123     switch (type)
24124       {
24125       case TYPE_ISYNC:
24126       case TYPE_SYNC:
24127       case TYPE_LOAD_L:
24128       case TYPE_STORE_C:
24129       case TYPE_LOAD_EXT_U:
24130       case TYPE_LOAD_EXT_UX:
24131       case TYPE_STORE_UX:
24132         return true;
24133       default:
24134         break;
24135     }
24136     break;
24137   default:
24138     break;
24139   }
24140 
24141   return false;
24142 }
24143 
24144 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
24145    dispatch group) from the insns in GROUP_INSNS.  Return false otherwise.  */
24146 
24147 static bool
is_costly_group(rtx * group_insns,rtx next_insn)24148 is_costly_group (rtx *group_insns, rtx next_insn)
24149 {
24150   int i;
24151   int issue_rate = rs6000_issue_rate ();
24152 
24153   for (i = 0; i < issue_rate; i++)
24154     {
24155       sd_iterator_def sd_it;
24156       dep_t dep;
24157       rtx insn = group_insns[i];
24158 
24159       if (!insn)
24160 	continue;
24161 
24162       FOR_EACH_DEP (insn, SD_LIST_RES_FORW, sd_it, dep)
24163 	{
24164 	  rtx next = DEP_CON (dep);
24165 
24166 	  if (next == next_insn
24167 	      && rs6000_is_costly_dependence (dep, dep_cost (dep), 0))
24168 	    return true;
24169 	}
24170     }
24171 
24172   return false;
24173 }
24174 
24175 /* Utility of the function redefine_groups.
24176    Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
24177    in the same dispatch group.  If so, insert nops before NEXT_INSN, in order
24178    to keep it "far" (in a separate group) from GROUP_INSNS, following
24179    one of the following schemes, depending on the value of the flag
24180    -minsert_sched_nops = X:
24181    (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
24182        in order to force NEXT_INSN into a separate group.
24183    (2) X < sched_finish_regroup_exact: insert exactly X nops.
24184    GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
24185    insertion (has a group just ended, how many vacant issue slots remain in the
24186    last group, and how many dispatch groups were encountered so far).  */
24187 
24188 static int
force_new_group(int sched_verbose,FILE * dump,rtx * group_insns,rtx next_insn,bool * group_end,int can_issue_more,int * group_count)24189 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
24190 		 rtx next_insn, bool *group_end, int can_issue_more,
24191 		 int *group_count)
24192 {
24193   rtx nop;
24194   bool force;
24195   int issue_rate = rs6000_issue_rate ();
24196   bool end = *group_end;
24197   int i;
24198 
24199   if (next_insn == NULL_RTX || DEBUG_INSN_P (next_insn))
24200     return can_issue_more;
24201 
24202   if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
24203     return can_issue_more;
24204 
24205   force = is_costly_group (group_insns, next_insn);
24206   if (!force)
24207     return can_issue_more;
24208 
24209   if (sched_verbose > 6)
24210     fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
24211 	     *group_count ,can_issue_more);
24212 
24213   if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
24214     {
24215       if (*group_end)
24216 	can_issue_more = 0;
24217 
24218       /* Since only a branch can be issued in the last issue_slot, it is
24219 	 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
24220 	 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
24221 	 in this case the last nop will start a new group and the branch
24222 	 will be forced to the new group.  */
24223       if (can_issue_more && !is_branch_slot_insn (next_insn))
24224 	can_issue_more--;
24225 
24226       /* Power6 and Power7 have special group ending nop. */
24227       if (rs6000_cpu_attr == CPU_POWER6 || rs6000_cpu_attr == CPU_POWER7)
24228 	{
24229 	  nop = gen_group_ending_nop ();
24230 	  emit_insn_before (nop, next_insn);
24231 	  can_issue_more = 0;
24232 	}
24233       else
24234 	while (can_issue_more > 0)
24235 	  {
24236 	    nop = gen_nop ();
24237 	    emit_insn_before (nop, next_insn);
24238 	    can_issue_more--;
24239 	  }
24240 
24241       *group_end = true;
24242       return 0;
24243     }
24244 
24245   if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
24246     {
24247       int n_nops = rs6000_sched_insert_nops;
24248 
24249       /* Nops can't be issued from the branch slot, so the effective
24250 	 issue_rate for nops is 'issue_rate - 1'.  */
24251       if (can_issue_more == 0)
24252 	can_issue_more = issue_rate;
24253       can_issue_more--;
24254       if (can_issue_more == 0)
24255 	{
24256 	  can_issue_more = issue_rate - 1;
24257 	  (*group_count)++;
24258 	  end = true;
24259 	  for (i = 0; i < issue_rate; i++)
24260 	    {
24261 	      group_insns[i] = 0;
24262 	    }
24263 	}
24264 
24265       while (n_nops > 0)
24266 	{
24267 	  nop = gen_nop ();
24268 	  emit_insn_before (nop, next_insn);
24269 	  if (can_issue_more == issue_rate - 1) /* new group begins */
24270 	    end = false;
24271 	  can_issue_more--;
24272 	  if (can_issue_more == 0)
24273 	    {
24274 	      can_issue_more = issue_rate - 1;
24275 	      (*group_count)++;
24276 	      end = true;
24277 	      for (i = 0; i < issue_rate; i++)
24278 		{
24279 		  group_insns[i] = 0;
24280 		}
24281 	    }
24282 	  n_nops--;
24283 	}
24284 
24285       /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1').  */
24286       can_issue_more++;
24287 
24288       /* Is next_insn going to start a new group?  */
24289       *group_end
24290 	= (end
24291 	   || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
24292 	   || (can_issue_more <= 2 && is_cracked_insn (next_insn))
24293 	   || (can_issue_more < issue_rate &&
24294 	       insn_terminates_group_p (next_insn, previous_group)));
24295       if (*group_end && end)
24296 	(*group_count)--;
24297 
24298       if (sched_verbose > 6)
24299 	fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
24300 		 *group_count, can_issue_more);
24301       return can_issue_more;
24302     }
24303 
24304   return can_issue_more;
24305 }
24306 
24307 /* This function tries to synch the dispatch groups that the compiler "sees"
24308    with the dispatch groups that the processor dispatcher is expected to
24309    form in practice.  It tries to achieve this synchronization by forcing the
24310    estimated processor grouping on the compiler (as opposed to the function
24311    'pad_goups' which tries to force the scheduler's grouping on the processor).
24312 
24313    The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
24314    examines the (estimated) dispatch groups that will be formed by the processor
24315    dispatcher.  It marks these group boundaries to reflect the estimated
24316    processor grouping, overriding the grouping that the scheduler had marked.
24317    Depending on the value of the flag '-minsert-sched-nops' this function can
24318    force certain insns into separate groups or force a certain distance between
24319    them by inserting nops, for example, if there exists a "costly dependence"
24320    between the insns.
24321 
24322    The function estimates the group boundaries that the processor will form as
24323    follows:  It keeps track of how many vacant issue slots are available after
24324    each insn.  A subsequent insn will start a new group if one of the following
24325    4 cases applies:
24326    - no more vacant issue slots remain in the current dispatch group.
24327    - only the last issue slot, which is the branch slot, is vacant, but the next
24328      insn is not a branch.
24329    - only the last 2 or less issue slots, including the branch slot, are vacant,
24330      which means that a cracked insn (which occupies two issue slots) can't be
24331      issued in this group.
24332    - less than 'issue_rate' slots are vacant, and the next insn always needs to
24333      start a new group.  */
24334 
24335 static int
redefine_groups(FILE * dump,int sched_verbose,rtx prev_head_insn,rtx tail)24336 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
24337 {
24338   rtx insn, next_insn;
24339   int issue_rate;
24340   int can_issue_more;
24341   int slot, i;
24342   bool group_end;
24343   int group_count = 0;
24344   rtx *group_insns;
24345 
24346   /* Initialize.  */
24347   issue_rate = rs6000_issue_rate ();
24348   group_insns = XALLOCAVEC (rtx, issue_rate);
24349   for (i = 0; i < issue_rate; i++)
24350     {
24351       group_insns[i] = 0;
24352     }
24353   can_issue_more = issue_rate;
24354   slot = 0;
24355   insn = get_next_active_insn (prev_head_insn, tail);
24356   group_end = false;
24357 
24358   while (insn != NULL_RTX)
24359     {
24360       slot = (issue_rate - can_issue_more);
24361       group_insns[slot] = insn;
24362       can_issue_more =
24363 	rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
24364       if (insn_terminates_group_p (insn, current_group))
24365 	can_issue_more = 0;
24366 
24367       next_insn = get_next_active_insn (insn, tail);
24368       if (next_insn == NULL_RTX)
24369 	return group_count + 1;
24370 
24371       /* Is next_insn going to start a new group?  */
24372       group_end
24373 	= (can_issue_more == 0
24374 	   || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
24375 	   || (can_issue_more <= 2 && is_cracked_insn (next_insn))
24376 	   || (can_issue_more < issue_rate &&
24377 	       insn_terminates_group_p (next_insn, previous_group)));
24378 
24379       can_issue_more = force_new_group (sched_verbose, dump, group_insns,
24380 					next_insn, &group_end, can_issue_more,
24381 					&group_count);
24382 
24383       if (group_end)
24384 	{
24385 	  group_count++;
24386 	  can_issue_more = 0;
24387 	  for (i = 0; i < issue_rate; i++)
24388 	    {
24389 	      group_insns[i] = 0;
24390 	    }
24391 	}
24392 
24393       if (GET_MODE (next_insn) == TImode && can_issue_more)
24394 	PUT_MODE (next_insn, VOIDmode);
24395       else if (!can_issue_more && GET_MODE (next_insn) != TImode)
24396 	PUT_MODE (next_insn, TImode);
24397 
24398       insn = next_insn;
24399       if (can_issue_more == 0)
24400 	can_issue_more = issue_rate;
24401     } /* while */
24402 
24403   return group_count;
24404 }
24405 
24406 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
24407    dispatch group boundaries that the scheduler had marked.  Pad with nops
24408    any dispatch groups which have vacant issue slots, in order to force the
24409    scheduler's grouping on the processor dispatcher.  The function
24410    returns the number of dispatch groups found.  */
24411 
24412 static int
pad_groups(FILE * dump,int sched_verbose,rtx prev_head_insn,rtx tail)24413 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
24414 {
24415   rtx insn, next_insn;
24416   rtx nop;
24417   int issue_rate;
24418   int can_issue_more;
24419   int group_end;
24420   int group_count = 0;
24421 
24422   /* Initialize issue_rate.  */
24423   issue_rate = rs6000_issue_rate ();
24424   can_issue_more = issue_rate;
24425 
24426   insn = get_next_active_insn (prev_head_insn, tail);
24427   next_insn = get_next_active_insn (insn, tail);
24428 
24429   while (insn != NULL_RTX)
24430     {
24431       can_issue_more =
24432       	rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
24433 
24434       group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
24435 
24436       if (next_insn == NULL_RTX)
24437 	break;
24438 
24439       if (group_end)
24440 	{
24441 	  /* If the scheduler had marked group termination at this location
24442 	     (between insn and next_insn), and neither insn nor next_insn will
24443 	     force group termination, pad the group with nops to force group
24444 	     termination.  */
24445 	  if (can_issue_more
24446 	      && (rs6000_sched_insert_nops == sched_finish_pad_groups)
24447 	      && !insn_terminates_group_p (insn, current_group)
24448 	      && !insn_terminates_group_p (next_insn, previous_group))
24449 	    {
24450 	      if (!is_branch_slot_insn (next_insn))
24451 		can_issue_more--;
24452 
24453 	      while (can_issue_more)
24454 		{
24455 		  nop = gen_nop ();
24456 		  emit_insn_before (nop, next_insn);
24457 		  can_issue_more--;
24458 		}
24459 	    }
24460 
24461 	  can_issue_more = issue_rate;
24462 	  group_count++;
24463 	}
24464 
24465       insn = next_insn;
24466       next_insn = get_next_active_insn (insn, tail);
24467     }
24468 
24469   return group_count;
24470 }
24471 
24472 /* We're beginning a new block.  Initialize data structures as necessary.  */
24473 
24474 static void
rs6000_sched_init(FILE * dump ATTRIBUTE_UNUSED,int sched_verbose ATTRIBUTE_UNUSED,int max_ready ATTRIBUTE_UNUSED)24475 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED,
24476 		     int sched_verbose ATTRIBUTE_UNUSED,
24477 		     int max_ready ATTRIBUTE_UNUSED)
24478 {
24479   last_scheduled_insn = NULL_RTX;
24480   load_store_pendulum = 0;
24481 }
24482 
24483 /* The following function is called at the end of scheduling BB.
24484    After reload, it inserts nops at insn group bundling.  */
24485 
24486 static void
rs6000_sched_finish(FILE * dump,int sched_verbose)24487 rs6000_sched_finish (FILE *dump, int sched_verbose)
24488 {
24489   int n_groups;
24490 
24491   if (sched_verbose)
24492     fprintf (dump, "=== Finishing schedule.\n");
24493 
24494   if (reload_completed && rs6000_sched_groups)
24495     {
24496       /* Do not run sched_finish hook when selective scheduling enabled.  */
24497       if (sel_sched_p ())
24498 	return;
24499 
24500       if (rs6000_sched_insert_nops == sched_finish_none)
24501 	return;
24502 
24503       if (rs6000_sched_insert_nops == sched_finish_pad_groups)
24504 	n_groups = pad_groups (dump, sched_verbose,
24505 			       current_sched_info->prev_head,
24506 			       current_sched_info->next_tail);
24507       else
24508 	n_groups = redefine_groups (dump, sched_verbose,
24509 				    current_sched_info->prev_head,
24510 				    current_sched_info->next_tail);
24511 
24512       if (sched_verbose >= 6)
24513 	{
24514     	  fprintf (dump, "ngroups = %d\n", n_groups);
24515 	  print_rtl (dump, current_sched_info->prev_head);
24516 	  fprintf (dump, "Done finish_sched\n");
24517 	}
24518     }
24519 }
24520 
24521 struct _rs6000_sched_context
24522 {
24523   short cached_can_issue_more;
24524   rtx last_scheduled_insn;
24525   int load_store_pendulum;
24526 };
24527 
24528 typedef struct _rs6000_sched_context rs6000_sched_context_def;
24529 typedef rs6000_sched_context_def *rs6000_sched_context_t;
24530 
24531 /* Allocate store for new scheduling context.  */
24532 static void *
rs6000_alloc_sched_context(void)24533 rs6000_alloc_sched_context (void)
24534 {
24535   return xmalloc (sizeof (rs6000_sched_context_def));
24536 }
24537 
24538 /* If CLEAN_P is true then initializes _SC with clean data,
24539    and from the global context otherwise.  */
24540 static void
rs6000_init_sched_context(void * _sc,bool clean_p)24541 rs6000_init_sched_context (void *_sc, bool clean_p)
24542 {
24543   rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
24544 
24545   if (clean_p)
24546     {
24547       sc->cached_can_issue_more = 0;
24548       sc->last_scheduled_insn = NULL_RTX;
24549       sc->load_store_pendulum = 0;
24550     }
24551   else
24552     {
24553       sc->cached_can_issue_more = cached_can_issue_more;
24554       sc->last_scheduled_insn = last_scheduled_insn;
24555       sc->load_store_pendulum = load_store_pendulum;
24556     }
24557 }
24558 
24559 /* Sets the global scheduling context to the one pointed to by _SC.  */
24560 static void
rs6000_set_sched_context(void * _sc)24561 rs6000_set_sched_context (void *_sc)
24562 {
24563   rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
24564 
24565   gcc_assert (sc != NULL);
24566 
24567   cached_can_issue_more = sc->cached_can_issue_more;
24568   last_scheduled_insn = sc->last_scheduled_insn;
24569   load_store_pendulum = sc->load_store_pendulum;
24570 }
24571 
24572 /* Free _SC.  */
24573 static void
rs6000_free_sched_context(void * _sc)24574 rs6000_free_sched_context (void *_sc)
24575 {
24576   gcc_assert (_sc != NULL);
24577 
24578   free (_sc);
24579 }
24580 
24581 
24582 /* Length in units of the trampoline for entering a nested function.  */
24583 
24584 int
rs6000_trampoline_size(void)24585 rs6000_trampoline_size (void)
24586 {
24587   int ret = 0;
24588 
24589   switch (DEFAULT_ABI)
24590     {
24591     default:
24592       gcc_unreachable ();
24593 
24594     case ABI_AIX:
24595       ret = (TARGET_32BIT) ? 12 : 24;
24596       break;
24597 
24598     case ABI_DARWIN:
24599     case ABI_V4:
24600       ret = (TARGET_32BIT) ? 40 : 48;
24601       break;
24602     }
24603 
24604   return ret;
24605 }
24606 
24607 /* Emit RTL insns to initialize the variable parts of a trampoline.
24608    FNADDR is an RTX for the address of the function's pure code.
24609    CXT is an RTX for the static chain value for the function.  */
24610 
24611 static void
rs6000_trampoline_init(rtx m_tramp,tree fndecl,rtx cxt)24612 rs6000_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
24613 {
24614   int regsize = (TARGET_32BIT) ? 4 : 8;
24615   rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
24616   rtx ctx_reg = force_reg (Pmode, cxt);
24617   rtx addr = force_reg (Pmode, XEXP (m_tramp, 0));
24618 
24619   switch (DEFAULT_ABI)
24620     {
24621     default:
24622       gcc_unreachable ();
24623 
24624     /* Under AIX, just build the 3 word function descriptor */
24625     case ABI_AIX:
24626       {
24627 	rtx fnmem, fn_reg, toc_reg;
24628 
24629 	if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS)
24630 	  error ("You cannot take the address of a nested function if you use "
24631 		 "the -mno-pointers-to-nested-functions option.");
24632 
24633 	fnmem = gen_const_mem (Pmode, force_reg (Pmode, fnaddr));
24634 	fn_reg = gen_reg_rtx (Pmode);
24635 	toc_reg = gen_reg_rtx (Pmode);
24636 
24637   /* Macro to shorten the code expansions below.  */
24638 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
24639 
24640 	m_tramp = replace_equiv_address (m_tramp, addr);
24641 
24642 	emit_move_insn (fn_reg, MEM_PLUS (fnmem, 0));
24643 	emit_move_insn (toc_reg, MEM_PLUS (fnmem, regsize));
24644 	emit_move_insn (MEM_PLUS (m_tramp, 0), fn_reg);
24645 	emit_move_insn (MEM_PLUS (m_tramp, regsize), toc_reg);
24646 	emit_move_insn (MEM_PLUS (m_tramp, 2*regsize), ctx_reg);
24647 
24648 # undef MEM_PLUS
24649       }
24650       break;
24651 
24652     /* Under V.4/eabi/darwin, __trampoline_setup does the real work.  */
24653     case ABI_DARWIN:
24654     case ABI_V4:
24655       emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
24656 			 LCT_NORMAL, VOIDmode, 4,
24657 			 addr, Pmode,
24658 			 GEN_INT (rs6000_trampoline_size ()), SImode,
24659 			 fnaddr, Pmode,
24660 			 ctx_reg, Pmode);
24661       break;
24662     }
24663 }
24664 
24665 
24666 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
24667    identifier as an argument, so the front end shouldn't look it up.  */
24668 
24669 static bool
rs6000_attribute_takes_identifier_p(const_tree attr_id)24670 rs6000_attribute_takes_identifier_p (const_tree attr_id)
24671 {
24672   return is_attribute_p ("altivec", attr_id);
24673 }
24674 
24675 /* Handle the "altivec" attribute.  The attribute may have
24676    arguments as follows:
24677 
24678 	__attribute__((altivec(vector__)))
24679 	__attribute__((altivec(pixel__)))	(always followed by 'unsigned short')
24680 	__attribute__((altivec(bool__)))	(always followed by 'unsigned')
24681 
24682   and may appear more than once (e.g., 'vector bool char') in a
24683   given declaration.  */
24684 
24685 static tree
rs6000_handle_altivec_attribute(tree * node,tree name ATTRIBUTE_UNUSED,tree args,int flags ATTRIBUTE_UNUSED,bool * no_add_attrs)24686 rs6000_handle_altivec_attribute (tree *node,
24687 				 tree name ATTRIBUTE_UNUSED,
24688 				 tree args,
24689 				 int flags ATTRIBUTE_UNUSED,
24690 				 bool *no_add_attrs)
24691 {
24692   tree type = *node, result = NULL_TREE;
24693   enum machine_mode mode;
24694   int unsigned_p;
24695   char altivec_type
24696     = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
24697 	&& TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
24698        ? *IDENTIFIER_POINTER (TREE_VALUE (args))
24699        : '?');
24700 
24701   while (POINTER_TYPE_P (type)
24702 	 || TREE_CODE (type) == FUNCTION_TYPE
24703 	 || TREE_CODE (type) == METHOD_TYPE
24704 	 || TREE_CODE (type) == ARRAY_TYPE)
24705     type = TREE_TYPE (type);
24706 
24707   mode = TYPE_MODE (type);
24708 
24709   /* Check for invalid AltiVec type qualifiers.  */
24710   if (type == long_double_type_node)
24711     error ("use of %<long double%> in AltiVec types is invalid");
24712   else if (type == boolean_type_node)
24713     error ("use of boolean types in AltiVec types is invalid");
24714   else if (TREE_CODE (type) == COMPLEX_TYPE)
24715     error ("use of %<complex%> in AltiVec types is invalid");
24716   else if (DECIMAL_FLOAT_MODE_P (mode))
24717     error ("use of decimal floating point types in AltiVec types is invalid");
24718   else if (!TARGET_VSX)
24719     {
24720       if (type == long_unsigned_type_node || type == long_integer_type_node)
24721 	{
24722 	  if (TARGET_64BIT)
24723 	    error ("use of %<long%> in AltiVec types is invalid for "
24724 		   "64-bit code without -mvsx");
24725 	  else if (rs6000_warn_altivec_long)
24726 	    warning (0, "use of %<long%> in AltiVec types is deprecated; "
24727 		     "use %<int%>");
24728 	}
24729       else if (type == long_long_unsigned_type_node
24730 	       || type == long_long_integer_type_node)
24731 	error ("use of %<long long%> in AltiVec types is invalid without "
24732 	       "-mvsx");
24733       else if (type == double_type_node)
24734 	error ("use of %<double%> in AltiVec types is invalid without -mvsx");
24735     }
24736 
24737   switch (altivec_type)
24738     {
24739     case 'v':
24740       unsigned_p = TYPE_UNSIGNED (type);
24741       switch (mode)
24742 	{
24743 	case DImode:
24744 	  result = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node);
24745 	  break;
24746 	case SImode:
24747 	  result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
24748 	  break;
24749 	case HImode:
24750 	  result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
24751 	  break;
24752 	case QImode:
24753 	  result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
24754 	  break;
24755 	case SFmode: result = V4SF_type_node; break;
24756 	case DFmode: result = V2DF_type_node; break;
24757 	  /* If the user says 'vector int bool', we may be handed the 'bool'
24758 	     attribute _before_ the 'vector' attribute, and so select the
24759 	     proper type in the 'b' case below.  */
24760 	case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
24761 	case V2DImode: case V2DFmode:
24762 	  result = type;
24763 	default: break;
24764 	}
24765       break;
24766     case 'b':
24767       switch (mode)
24768 	{
24769 	case DImode: case V2DImode: result = bool_V2DI_type_node; break;
24770 	case SImode: case V4SImode: result = bool_V4SI_type_node; break;
24771 	case HImode: case V8HImode: result = bool_V8HI_type_node; break;
24772 	case QImode: case V16QImode: result = bool_V16QI_type_node;
24773 	default: break;
24774 	}
24775       break;
24776     case 'p':
24777       switch (mode)
24778 	{
24779 	case V8HImode: result = pixel_V8HI_type_node;
24780 	default: break;
24781 	}
24782     default: break;
24783     }
24784 
24785   /* Propagate qualifiers attached to the element type
24786      onto the vector type.  */
24787   if (result && result != type && TYPE_QUALS (type))
24788     result = build_qualified_type (result, TYPE_QUALS (type));
24789 
24790   *no_add_attrs = true;  /* No need to hang on to the attribute.  */
24791 
24792   if (result)
24793     *node = lang_hooks.types.reconstruct_complex_type (*node, result);
24794 
24795   return NULL_TREE;
24796 }
24797 
24798 /* AltiVec defines four built-in scalar types that serve as vector
24799    elements; we must teach the compiler how to mangle them.  */
24800 
24801 static const char *
rs6000_mangle_type(const_tree type)24802 rs6000_mangle_type (const_tree type)
24803 {
24804   type = TYPE_MAIN_VARIANT (type);
24805 
24806   if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
24807       && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
24808     return NULL;
24809 
24810   if (type == bool_char_type_node) return "U6__boolc";
24811   if (type == bool_short_type_node) return "U6__bools";
24812   if (type == pixel_type_node) return "u7__pixel";
24813   if (type == bool_int_type_node) return "U6__booli";
24814   if (type == bool_long_type_node) return "U6__booll";
24815 
24816   /* Mangle IBM extended float long double as `g' (__float128) on
24817      powerpc*-linux where long-double-64 previously was the default.  */
24818   if (TYPE_MAIN_VARIANT (type) == long_double_type_node
24819       && TARGET_ELF
24820       && TARGET_LONG_DOUBLE_128
24821       && !TARGET_IEEEQUAD)
24822     return "g";
24823 
24824   /* For all other types, use normal C++ mangling.  */
24825   return NULL;
24826 }
24827 
24828 /* Handle a "longcall" or "shortcall" attribute; arguments as in
24829    struct attribute_spec.handler.  */
24830 
24831 static tree
rs6000_handle_longcall_attribute(tree * node,tree name,tree args ATTRIBUTE_UNUSED,int flags ATTRIBUTE_UNUSED,bool * no_add_attrs)24832 rs6000_handle_longcall_attribute (tree *node, tree name,
24833 				  tree args ATTRIBUTE_UNUSED,
24834 				  int flags ATTRIBUTE_UNUSED,
24835 				  bool *no_add_attrs)
24836 {
24837   if (TREE_CODE (*node) != FUNCTION_TYPE
24838       && TREE_CODE (*node) != FIELD_DECL
24839       && TREE_CODE (*node) != TYPE_DECL)
24840     {
24841       warning (OPT_Wattributes, "%qE attribute only applies to functions",
24842 	       name);
24843       *no_add_attrs = true;
24844     }
24845 
24846   return NULL_TREE;
24847 }
24848 
24849 /* Set longcall attributes on all functions declared when
24850    rs6000_default_long_calls is true.  */
24851 static void
rs6000_set_default_type_attributes(tree type)24852 rs6000_set_default_type_attributes (tree type)
24853 {
24854   if (rs6000_default_long_calls
24855       && (TREE_CODE (type) == FUNCTION_TYPE
24856 	  || TREE_CODE (type) == METHOD_TYPE))
24857     TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
24858 					NULL_TREE,
24859 					TYPE_ATTRIBUTES (type));
24860 
24861 #if TARGET_MACHO
24862   darwin_set_default_type_attributes (type);
24863 #endif
24864 }
24865 
24866 /* Return a reference suitable for calling a function with the
24867    longcall attribute.  */
24868 
24869 rtx
rs6000_longcall_ref(rtx call_ref)24870 rs6000_longcall_ref (rtx call_ref)
24871 {
24872   const char *call_name;
24873   tree node;
24874 
24875   if (GET_CODE (call_ref) != SYMBOL_REF)
24876     return call_ref;
24877 
24878   /* System V adds '.' to the internal name, so skip them.  */
24879   call_name = XSTR (call_ref, 0);
24880   if (*call_name == '.')
24881     {
24882       while (*call_name == '.')
24883 	call_name++;
24884 
24885       node = get_identifier (call_name);
24886       call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
24887     }
24888 
24889   return force_reg (Pmode, call_ref);
24890 }
24891 
24892 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
24893 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
24894 #endif
24895 
24896 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
24897    struct attribute_spec.handler.  */
24898 static tree
rs6000_handle_struct_attribute(tree * node,tree name,tree args ATTRIBUTE_UNUSED,int flags ATTRIBUTE_UNUSED,bool * no_add_attrs)24899 rs6000_handle_struct_attribute (tree *node, tree name,
24900 				tree args ATTRIBUTE_UNUSED,
24901 				int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
24902 {
24903   tree *type = NULL;
24904   if (DECL_P (*node))
24905     {
24906       if (TREE_CODE (*node) == TYPE_DECL)
24907         type = &TREE_TYPE (*node);
24908     }
24909   else
24910     type = node;
24911 
24912   if (!(type && (TREE_CODE (*type) == RECORD_TYPE
24913                  || TREE_CODE (*type) == UNION_TYPE)))
24914     {
24915       warning (OPT_Wattributes, "%qE attribute ignored", name);
24916       *no_add_attrs = true;
24917     }
24918 
24919   else if ((is_attribute_p ("ms_struct", name)
24920             && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
24921            || ((is_attribute_p ("gcc_struct", name)
24922                 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
24923     {
24924       warning (OPT_Wattributes, "%qE incompatible attribute ignored",
24925                name);
24926       *no_add_attrs = true;
24927     }
24928 
24929   return NULL_TREE;
24930 }
24931 
24932 static bool
rs6000_ms_bitfield_layout_p(const_tree record_type)24933 rs6000_ms_bitfield_layout_p (const_tree record_type)
24934 {
24935   return (TARGET_USE_MS_BITFIELD_LAYOUT &&
24936           !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
24937     || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
24938 }
24939 
24940 #ifdef USING_ELFOS_H
24941 
24942 /* A get_unnamed_section callback, used for switching to toc_section.  */
24943 
24944 static void
rs6000_elf_output_toc_section_asm_op(const void * data ATTRIBUTE_UNUSED)24945 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
24946 {
24947   if (DEFAULT_ABI == ABI_AIX
24948       && TARGET_MINIMAL_TOC
24949       && !TARGET_RELOCATABLE)
24950     {
24951       if (!toc_initialized)
24952 	{
24953 	  toc_initialized = 1;
24954 	  fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
24955 	  (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
24956 	  fprintf (asm_out_file, "\t.tc ");
24957 	  ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
24958 	  ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
24959 	  fprintf (asm_out_file, "\n");
24960 
24961 	  fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
24962 	  ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
24963 	  fprintf (asm_out_file, " = .+32768\n");
24964 	}
24965       else
24966 	fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
24967     }
24968   else if (DEFAULT_ABI == ABI_AIX && !TARGET_RELOCATABLE)
24969     fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
24970   else
24971     {
24972       fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
24973       if (!toc_initialized)
24974 	{
24975 	  ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
24976 	  fprintf (asm_out_file, " = .+32768\n");
24977 	  toc_initialized = 1;
24978 	}
24979     }
24980 }
24981 
24982 /* Implement TARGET_ASM_INIT_SECTIONS.  */
24983 
24984 static void
rs6000_elf_asm_init_sections(void)24985 rs6000_elf_asm_init_sections (void)
24986 {
24987   toc_section
24988     = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
24989 
24990   sdata2_section
24991     = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
24992 			   SDATA2_SECTION_ASM_OP);
24993 }
24994 
24995 /* Implement TARGET_SELECT_RTX_SECTION.  */
24996 
24997 static section *
rs6000_elf_select_rtx_section(enum machine_mode mode,rtx x,unsigned HOST_WIDE_INT align)24998 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
24999 			       unsigned HOST_WIDE_INT align)
25000 {
25001   if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
25002     return toc_section;
25003   else
25004     return default_elf_select_rtx_section (mode, x, align);
25005 }
25006 
25007 /* For a SYMBOL_REF, set generic flags and then perform some
25008    target-specific processing.
25009 
25010    When the AIX ABI is requested on a non-AIX system, replace the
25011    function name with the real name (with a leading .) rather than the
25012    function descriptor name.  This saves a lot of overriding code to
25013    read the prefixes.  */
25014 
25015 static void rs6000_elf_encode_section_info (tree, rtx, int) ATTRIBUTE_UNUSED;
25016 static void
rs6000_elf_encode_section_info(tree decl,rtx rtl,int first)25017 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
25018 {
25019   default_encode_section_info (decl, rtl, first);
25020 
25021   if (first
25022       && TREE_CODE (decl) == FUNCTION_DECL
25023       && !TARGET_AIX
25024       && DEFAULT_ABI == ABI_AIX)
25025     {
25026       rtx sym_ref = XEXP (rtl, 0);
25027       size_t len = strlen (XSTR (sym_ref, 0));
25028       char *str = XALLOCAVEC (char, len + 2);
25029       str[0] = '.';
25030       memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
25031       XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
25032     }
25033 }
25034 
25035 static inline bool
compare_section_name(const char * section,const char * templ)25036 compare_section_name (const char *section, const char *templ)
25037 {
25038   int len;
25039 
25040   len = strlen (templ);
25041   return (strncmp (section, templ, len) == 0
25042 	  && (section[len] == 0 || section[len] == '.'));
25043 }
25044 
25045 bool
rs6000_elf_in_small_data_p(const_tree decl)25046 rs6000_elf_in_small_data_p (const_tree decl)
25047 {
25048   if (rs6000_sdata == SDATA_NONE)
25049     return false;
25050 
25051   /* We want to merge strings, so we never consider them small data.  */
25052   if (TREE_CODE (decl) == STRING_CST)
25053     return false;
25054 
25055   /* Functions are never in the small data area.  */
25056   if (TREE_CODE (decl) == FUNCTION_DECL)
25057     return false;
25058 
25059   if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
25060     {
25061       const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
25062       if (compare_section_name (section, ".sdata")
25063 	  || compare_section_name (section, ".sdata2")
25064 	  || compare_section_name (section, ".gnu.linkonce.s")
25065 	  || compare_section_name (section, ".sbss")
25066 	  || compare_section_name (section, ".sbss2")
25067 	  || compare_section_name (section, ".gnu.linkonce.sb")
25068 	  || strcmp (section, ".PPC.EMB.sdata0") == 0
25069 	  || strcmp (section, ".PPC.EMB.sbss0") == 0)
25070 	return true;
25071     }
25072   else
25073     {
25074       HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
25075 
25076       if (size > 0
25077 	  && size <= g_switch_value
25078 	  /* If it's not public, and we're not going to reference it there,
25079 	     there's no need to put it in the small data section.  */
25080 	  && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
25081 	return true;
25082     }
25083 
25084   return false;
25085 }
25086 
25087 #endif /* USING_ELFOS_H */
25088 
25089 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P.  */
25090 
25091 static bool
rs6000_use_blocks_for_constant_p(enum machine_mode mode,const_rtx x)25092 rs6000_use_blocks_for_constant_p (enum machine_mode mode, const_rtx x)
25093 {
25094   return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
25095 }
25096 
25097 /* Do not place thread-local symbols refs in the object blocks.  */
25098 
25099 static bool
rs6000_use_blocks_for_decl_p(const_tree decl)25100 rs6000_use_blocks_for_decl_p (const_tree decl)
25101 {
25102   return !DECL_THREAD_LOCAL_P (decl);
25103 }
25104 
25105 /* Return a REG that occurs in ADDR with coefficient 1.
25106    ADDR can be effectively incremented by incrementing REG.
25107 
25108    r0 is special and we must not select it as an address
25109    register by this routine since our caller will try to
25110    increment the returned register via an "la" instruction.  */
25111 
25112 rtx
find_addr_reg(rtx addr)25113 find_addr_reg (rtx addr)
25114 {
25115   while (GET_CODE (addr) == PLUS)
25116     {
25117       if (GET_CODE (XEXP (addr, 0)) == REG
25118 	  && REGNO (XEXP (addr, 0)) != 0)
25119 	addr = XEXP (addr, 0);
25120       else if (GET_CODE (XEXP (addr, 1)) == REG
25121 	       && REGNO (XEXP (addr, 1)) != 0)
25122 	addr = XEXP (addr, 1);
25123       else if (CONSTANT_P (XEXP (addr, 0)))
25124 	addr = XEXP (addr, 1);
25125       else if (CONSTANT_P (XEXP (addr, 1)))
25126 	addr = XEXP (addr, 0);
25127       else
25128 	gcc_unreachable ();
25129     }
25130   gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
25131   return addr;
25132 }
25133 
25134 void
rs6000_fatal_bad_address(rtx op)25135 rs6000_fatal_bad_address (rtx op)
25136 {
25137   fatal_insn ("bad address", op);
25138 }
25139 
25140 #if TARGET_MACHO
25141 
25142 typedef struct branch_island_d {
25143   tree function_name;
25144   tree label_name;
25145   int line_number;
25146 } branch_island;
25147 
25148 
25149 static vec<branch_island, va_gc> *branch_islands;
25150 
25151 /* Remember to generate a branch island for far calls to the given
25152    function.  */
25153 
25154 static void
add_compiler_branch_island(tree label_name,tree function_name,int line_number)25155 add_compiler_branch_island (tree label_name, tree function_name,
25156 			    int line_number)
25157 {
25158   branch_island bi = {function_name, label_name, line_number};
25159   vec_safe_push (branch_islands, bi);
25160 }
25161 
25162 /* Generate far-jump branch islands for everything recorded in
25163    branch_islands.  Invoked immediately after the last instruction of
25164    the epilogue has been emitted; the branch islands must be appended
25165    to, and contiguous with, the function body.  Mach-O stubs are
25166    generated in machopic_output_stub().  */
25167 
25168 static void
macho_branch_islands(void)25169 macho_branch_islands (void)
25170 {
25171   char tmp_buf[512];
25172 
25173   while (!vec_safe_is_empty (branch_islands))
25174     {
25175       branch_island *bi = &branch_islands->last ();
25176       const char *label = IDENTIFIER_POINTER (bi->label_name);
25177       const char *name = IDENTIFIER_POINTER (bi->function_name);
25178       char name_buf[512];
25179       /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF().  */
25180       if (name[0] == '*' || name[0] == '&')
25181 	strcpy (name_buf, name+1);
25182       else
25183 	{
25184 	  name_buf[0] = '_';
25185 	  strcpy (name_buf+1, name);
25186 	}
25187       strcpy (tmp_buf, "\n");
25188       strcat (tmp_buf, label);
25189 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
25190       if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
25191 	dbxout_stabd (N_SLINE, bi->line_number);
25192 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
25193       if (flag_pic)
25194 	{
25195 	  if (TARGET_LINK_STACK)
25196 	    {
25197 	      char name[32];
25198 	      get_ppc476_thunk_name (name);
25199 	      strcat (tmp_buf, ":\n\tmflr r0\n\tbl ");
25200 	      strcat (tmp_buf, name);
25201 	      strcat (tmp_buf, "\n");
25202 	      strcat (tmp_buf, label);
25203 	      strcat (tmp_buf, "_pic:\n\tmflr r11\n");
25204 	    }
25205 	  else
25206 	    {
25207 	      strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
25208 	      strcat (tmp_buf, label);
25209 	      strcat (tmp_buf, "_pic\n");
25210 	      strcat (tmp_buf, label);
25211 	      strcat (tmp_buf, "_pic:\n\tmflr r11\n");
25212 	    }
25213 
25214 	  strcat (tmp_buf, "\taddis r11,r11,ha16(");
25215 	  strcat (tmp_buf, name_buf);
25216 	  strcat (tmp_buf, " - ");
25217 	  strcat (tmp_buf, label);
25218 	  strcat (tmp_buf, "_pic)\n");
25219 
25220 	  strcat (tmp_buf, "\tmtlr r0\n");
25221 
25222 	  strcat (tmp_buf, "\taddi r12,r11,lo16(");
25223 	  strcat (tmp_buf, name_buf);
25224 	  strcat (tmp_buf, " - ");
25225 	  strcat (tmp_buf, label);
25226 	  strcat (tmp_buf, "_pic)\n");
25227 
25228 	  strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
25229 	}
25230       else
25231 	{
25232 	  strcat (tmp_buf, ":\nlis r12,hi16(");
25233 	  strcat (tmp_buf, name_buf);
25234 	  strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
25235 	  strcat (tmp_buf, name_buf);
25236 	  strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
25237 	}
25238       output_asm_insn (tmp_buf, 0);
25239 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
25240       if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
25241 	dbxout_stabd (N_SLINE, bi->line_number);
25242 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
25243       branch_islands->pop ();
25244     }
25245 }
25246 
25247 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
25248    already there or not.  */
25249 
25250 static int
no_previous_def(tree function_name)25251 no_previous_def (tree function_name)
25252 {
25253   branch_island *bi;
25254   unsigned ix;
25255 
25256   FOR_EACH_VEC_SAFE_ELT (branch_islands, ix, bi)
25257     if (function_name == bi->function_name)
25258       return 0;
25259   return 1;
25260 }
25261 
25262 /* GET_PREV_LABEL gets the label name from the previous definition of
25263    the function.  */
25264 
25265 static tree
get_prev_label(tree function_name)25266 get_prev_label (tree function_name)
25267 {
25268   branch_island *bi;
25269   unsigned ix;
25270 
25271   FOR_EACH_VEC_SAFE_ELT (branch_islands, ix, bi)
25272     if (function_name == bi->function_name)
25273       return bi->label_name;
25274   return NULL_TREE;
25275 }
25276 
25277 /* INSN is either a function call or a millicode call.  It may have an
25278    unconditional jump in its delay slot.
25279 
25280    CALL_DEST is the routine we are calling.  */
25281 
25282 char *
output_call(rtx insn,rtx * operands,int dest_operand_number,int cookie_operand_number)25283 output_call (rtx insn, rtx *operands, int dest_operand_number,
25284 	     int cookie_operand_number)
25285 {
25286   static char buf[256];
25287   if (darwin_emit_branch_islands
25288       && GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
25289       && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
25290     {
25291       tree labelname;
25292       tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
25293 
25294       if (no_previous_def (funname))
25295 	{
25296 	  rtx label_rtx = gen_label_rtx ();
25297 	  char *label_buf, temp_buf[256];
25298 	  ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
25299 				       CODE_LABEL_NUMBER (label_rtx));
25300 	  label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
25301 	  labelname = get_identifier (label_buf);
25302 	  add_compiler_branch_island (labelname, funname, insn_line (insn));
25303 	}
25304       else
25305 	labelname = get_prev_label (funname);
25306 
25307       /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
25308 	 instruction will reach 'foo', otherwise link as 'bl L42'".
25309 	 "L42" should be a 'branch island', that will do a far jump to
25310 	 'foo'.  Branch islands are generated in
25311 	 macho_branch_islands().  */
25312       sprintf (buf, "jbsr %%z%d,%.246s",
25313 	       dest_operand_number, IDENTIFIER_POINTER (labelname));
25314     }
25315   else
25316     sprintf (buf, "bl %%z%d", dest_operand_number);
25317   return buf;
25318 }
25319 
25320 /* Generate PIC and indirect symbol stubs.  */
25321 
25322 void
machopic_output_stub(FILE * file,const char * symb,const char * stub)25323 machopic_output_stub (FILE *file, const char *symb, const char *stub)
25324 {
25325   unsigned int length;
25326   char *symbol_name, *lazy_ptr_name;
25327   char *local_label_0;
25328   static int label = 0;
25329 
25330   /* Lose our funky encoding stuff so it doesn't contaminate the stub.  */
25331   symb = (*targetm.strip_name_encoding) (symb);
25332 
25333 
25334   length = strlen (symb);
25335   symbol_name = XALLOCAVEC (char, length + 32);
25336   GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
25337 
25338   lazy_ptr_name = XALLOCAVEC (char, length + 32);
25339   GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
25340 
25341   if (flag_pic == 2)
25342     switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
25343   else
25344     switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
25345 
25346   if (flag_pic == 2)
25347     {
25348       fprintf (file, "\t.align 5\n");
25349 
25350       fprintf (file, "%s:\n", stub);
25351       fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
25352 
25353       label++;
25354       local_label_0 = XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
25355       sprintf (local_label_0, "\"L%011d$spb\"", label);
25356 
25357       fprintf (file, "\tmflr r0\n");
25358       if (TARGET_LINK_STACK)
25359 	{
25360 	  char name[32];
25361 	  get_ppc476_thunk_name (name);
25362 	  fprintf (file, "\tbl %s\n", name);
25363 	  fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
25364 	}
25365       else
25366 	{
25367 	  fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
25368 	  fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
25369 	}
25370       fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
25371 	       lazy_ptr_name, local_label_0);
25372       fprintf (file, "\tmtlr r0\n");
25373       fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
25374 	       (TARGET_64BIT ? "ldu" : "lwzu"),
25375 	       lazy_ptr_name, local_label_0);
25376       fprintf (file, "\tmtctr r12\n");
25377       fprintf (file, "\tbctr\n");
25378     }
25379   else
25380     {
25381       fprintf (file, "\t.align 4\n");
25382 
25383       fprintf (file, "%s:\n", stub);
25384       fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
25385 
25386       fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
25387       fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
25388 	       (TARGET_64BIT ? "ldu" : "lwzu"),
25389 	       lazy_ptr_name);
25390       fprintf (file, "\tmtctr r12\n");
25391       fprintf (file, "\tbctr\n");
25392     }
25393 
25394   switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
25395   fprintf (file, "%s:\n", lazy_ptr_name);
25396   fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
25397   fprintf (file, "%sdyld_stub_binding_helper\n",
25398 	   (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
25399 }
25400 
25401 /* Legitimize PIC addresses.  If the address is already
25402    position-independent, we return ORIG.  Newly generated
25403    position-independent addresses go into a reg.  This is REG if non
25404    zero, otherwise we allocate register(s) as necessary.  */
25405 
25406 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
25407 
25408 rtx
rs6000_machopic_legitimize_pic_address(rtx orig,enum machine_mode mode,rtx reg)25409 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
25410 					rtx reg)
25411 {
25412   rtx base, offset;
25413 
25414   if (reg == NULL && ! reload_in_progress && ! reload_completed)
25415     reg = gen_reg_rtx (Pmode);
25416 
25417   if (GET_CODE (orig) == CONST)
25418     {
25419       rtx reg_temp;
25420 
25421       if (GET_CODE (XEXP (orig, 0)) == PLUS
25422 	  && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
25423 	return orig;
25424 
25425       gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
25426 
25427       /* Use a different reg for the intermediate value, as
25428 	 it will be marked UNCHANGING.  */
25429       reg_temp = !can_create_pseudo_p () ? reg : gen_reg_rtx (Pmode);
25430       base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
25431 						     Pmode, reg_temp);
25432       offset =
25433 	rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
25434 						Pmode, reg);
25435 
25436       if (GET_CODE (offset) == CONST_INT)
25437 	{
25438 	  if (SMALL_INT (offset))
25439 	    return plus_constant (Pmode, base, INTVAL (offset));
25440 	  else if (! reload_in_progress && ! reload_completed)
25441 	    offset = force_reg (Pmode, offset);
25442 	  else
25443 	    {
25444  	      rtx mem = force_const_mem (Pmode, orig);
25445 	      return machopic_legitimize_pic_address (mem, Pmode, reg);
25446 	    }
25447 	}
25448       return gen_rtx_PLUS (Pmode, base, offset);
25449     }
25450 
25451   /* Fall back on generic machopic code.  */
25452   return machopic_legitimize_pic_address (orig, mode, reg);
25453 }
25454 
25455 /* Output a .machine directive for the Darwin assembler, and call
25456    the generic start_file routine.  */
25457 
25458 static void
rs6000_darwin_file_start(void)25459 rs6000_darwin_file_start (void)
25460 {
25461   static const struct
25462   {
25463     const char *arg;
25464     const char *name;
25465     HOST_WIDE_INT if_set;
25466   } mapping[] = {
25467     { "ppc64", "ppc64", MASK_64BIT },
25468     { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
25469     { "power4", "ppc970", 0 },
25470     { "G5", "ppc970", 0 },
25471     { "7450", "ppc7450", 0 },
25472     { "7400", "ppc7400", MASK_ALTIVEC },
25473     { "G4", "ppc7400", 0 },
25474     { "750", "ppc750", 0 },
25475     { "740", "ppc750", 0 },
25476     { "G3", "ppc750", 0 },
25477     { "604e", "ppc604e", 0 },
25478     { "604", "ppc604", 0 },
25479     { "603e", "ppc603", 0 },
25480     { "603", "ppc603", 0 },
25481     { "601", "ppc601", 0 },
25482     { NULL, "ppc", 0 } };
25483   const char *cpu_id = "";
25484   size_t i;
25485 
25486   rs6000_file_start ();
25487   darwin_file_start ();
25488 
25489   /* Determine the argument to -mcpu=.  Default to G3 if not specified.  */
25490 
25491   if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
25492     cpu_id = rs6000_default_cpu;
25493 
25494   if (global_options_set.x_rs6000_cpu_index)
25495     cpu_id = processor_target_table[rs6000_cpu_index].name;
25496 
25497   /* Look through the mapping array.  Pick the first name that either
25498      matches the argument, has a bit set in IF_SET that is also set
25499      in the target flags, or has a NULL name.  */
25500 
25501   i = 0;
25502   while (mapping[i].arg != NULL
25503 	 && strcmp (mapping[i].arg, cpu_id) != 0
25504 	 && (mapping[i].if_set & rs6000_isa_flags) == 0)
25505     i++;
25506 
25507   fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
25508 }
25509 
25510 #endif /* TARGET_MACHO */
25511 
25512 #if TARGET_ELF
25513 static int
rs6000_elf_reloc_rw_mask(void)25514 rs6000_elf_reloc_rw_mask (void)
25515 {
25516   if (flag_pic)
25517     return 3;
25518   else if (DEFAULT_ABI == ABI_AIX)
25519     return 2;
25520   else
25521     return 0;
25522 }
25523 
25524 /* Record an element in the table of global constructors.  SYMBOL is
25525    a SYMBOL_REF of the function to be called; PRIORITY is a number
25526    between 0 and MAX_INIT_PRIORITY.
25527 
25528    This differs from default_named_section_asm_out_constructor in
25529    that we have special handling for -mrelocatable.  */
25530 
25531 static void rs6000_elf_asm_out_constructor (rtx, int) ATTRIBUTE_UNUSED;
25532 static void
rs6000_elf_asm_out_constructor(rtx symbol,int priority)25533 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
25534 {
25535   const char *section = ".ctors";
25536   char buf[16];
25537 
25538   if (priority != DEFAULT_INIT_PRIORITY)
25539     {
25540       sprintf (buf, ".ctors.%.5u",
25541 	       /* Invert the numbering so the linker puts us in the proper
25542 		  order; constructors are run from right to left, and the
25543 		  linker sorts in increasing order.  */
25544 	       MAX_INIT_PRIORITY - priority);
25545       section = buf;
25546     }
25547 
25548   switch_to_section (get_section (section, SECTION_WRITE, NULL));
25549   assemble_align (POINTER_SIZE);
25550 
25551   if (TARGET_RELOCATABLE)
25552     {
25553       fputs ("\t.long (", asm_out_file);
25554       output_addr_const (asm_out_file, symbol);
25555       fputs (")@fixup\n", asm_out_file);
25556     }
25557   else
25558     assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
25559 }
25560 
25561 static void rs6000_elf_asm_out_destructor (rtx, int) ATTRIBUTE_UNUSED;
25562 static void
rs6000_elf_asm_out_destructor(rtx symbol,int priority)25563 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
25564 {
25565   const char *section = ".dtors";
25566   char buf[16];
25567 
25568   if (priority != DEFAULT_INIT_PRIORITY)
25569     {
25570       sprintf (buf, ".dtors.%.5u",
25571 	       /* Invert the numbering so the linker puts us in the proper
25572 		  order; constructors are run from right to left, and the
25573 		  linker sorts in increasing order.  */
25574 	       MAX_INIT_PRIORITY - priority);
25575       section = buf;
25576     }
25577 
25578   switch_to_section (get_section (section, SECTION_WRITE, NULL));
25579   assemble_align (POINTER_SIZE);
25580 
25581   if (TARGET_RELOCATABLE)
25582     {
25583       fputs ("\t.long (", asm_out_file);
25584       output_addr_const (asm_out_file, symbol);
25585       fputs (")@fixup\n", asm_out_file);
25586     }
25587   else
25588     assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
25589 }
25590 
25591 void
rs6000_elf_declare_function_name(FILE * file,const char * name,tree decl)25592 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
25593 {
25594   if (TARGET_64BIT)
25595     {
25596       fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
25597       ASM_OUTPUT_LABEL (file, name);
25598       fputs (DOUBLE_INT_ASM_OP, file);
25599       rs6000_output_function_entry (file, name);
25600       fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
25601       if (DOT_SYMBOLS)
25602 	{
25603 	  fputs ("\t.size\t", file);
25604 	  assemble_name (file, name);
25605 	  fputs (",24\n\t.type\t.", file);
25606 	  assemble_name (file, name);
25607 	  fputs (",@function\n", file);
25608 	  if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
25609 	    {
25610 	      fputs ("\t.globl\t.", file);
25611 	      assemble_name (file, name);
25612 	      putc ('\n', file);
25613 	    }
25614 	}
25615       else
25616 	ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
25617       ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
25618       rs6000_output_function_entry (file, name);
25619       fputs (":\n", file);
25620       return;
25621     }
25622 
25623   if (TARGET_RELOCATABLE
25624       && !TARGET_SECURE_PLT
25625       && (get_pool_size () != 0 || crtl->profile)
25626       && uses_TOC ())
25627     {
25628       char buf[256];
25629 
25630       (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
25631 
25632       ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
25633       fprintf (file, "\t.long ");
25634       assemble_name (file, buf);
25635       putc ('-', file);
25636       ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
25637       assemble_name (file, buf);
25638       putc ('\n', file);
25639     }
25640 
25641   ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
25642   ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
25643 
25644   if (DEFAULT_ABI == ABI_AIX)
25645     {
25646       const char *desc_name, *orig_name;
25647 
25648       orig_name = (*targetm.strip_name_encoding) (name);
25649       desc_name = orig_name;
25650       while (*desc_name == '.')
25651 	desc_name++;
25652 
25653       if (TREE_PUBLIC (decl))
25654 	fprintf (file, "\t.globl %s\n", desc_name);
25655 
25656       fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
25657       fprintf (file, "%s:\n", desc_name);
25658       fprintf (file, "\t.long %s\n", orig_name);
25659       fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
25660       if (DEFAULT_ABI == ABI_AIX)
25661 	fputs ("\t.long 0\n", file);
25662       fprintf (file, "\t.previous\n");
25663     }
25664   ASM_OUTPUT_LABEL (file, name);
25665 }
25666 
25667 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED;
25668 static void
rs6000_elf_file_end(void)25669 rs6000_elf_file_end (void)
25670 {
25671 #ifdef HAVE_AS_GNU_ATTRIBUTE
25672   if (TARGET_32BIT && DEFAULT_ABI == ABI_V4)
25673     {
25674       if (rs6000_passes_float)
25675 	fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n",
25676 		 ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT) ? 1
25677 		  : (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT) ? 3
25678 		  : 2));
25679       if (rs6000_passes_vector)
25680 	fprintf (asm_out_file, "\t.gnu_attribute 8, %d\n",
25681 		 (TARGET_ALTIVEC_ABI ? 2
25682 		  : TARGET_SPE_ABI ? 3
25683 		  : 1));
25684       if (rs6000_returns_struct)
25685 	fprintf (asm_out_file, "\t.gnu_attribute 12, %d\n",
25686 		 aix_struct_return ? 2 : 1);
25687     }
25688 #endif
25689 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
25690   if (TARGET_32BIT)
25691     file_end_indicate_exec_stack ();
25692 #endif
25693 }
25694 #endif
25695 
25696 #if TARGET_XCOFF
25697 static void
rs6000_xcoff_asm_output_anchor(rtx symbol)25698 rs6000_xcoff_asm_output_anchor (rtx symbol)
25699 {
25700   char buffer[100];
25701 
25702   sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
25703 	   SYMBOL_REF_BLOCK_OFFSET (symbol));
25704   ASM_OUTPUT_DEF (asm_out_file, XSTR (symbol, 0), buffer);
25705 }
25706 
25707 static void
rs6000_xcoff_asm_globalize_label(FILE * stream,const char * name)25708 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
25709 {
25710   fputs (GLOBAL_ASM_OP, stream);
25711   RS6000_OUTPUT_BASENAME (stream, name);
25712   putc ('\n', stream);
25713 }
25714 
25715 /* A get_unnamed_decl callback, used for read-only sections.  PTR
25716    points to the section string variable.  */
25717 
25718 static void
rs6000_xcoff_output_readonly_section_asm_op(const void * directive)25719 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
25720 {
25721   fprintf (asm_out_file, "\t.csect %s[RO],%s\n",
25722 	   *(const char *const *) directive,
25723 	   XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
25724 }
25725 
25726 /* Likewise for read-write sections.  */
25727 
25728 static void
rs6000_xcoff_output_readwrite_section_asm_op(const void * directive)25729 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
25730 {
25731   fprintf (asm_out_file, "\t.csect %s[RW],%s\n",
25732 	   *(const char *const *) directive,
25733 	   XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
25734 }
25735 
25736 static void
rs6000_xcoff_output_tls_section_asm_op(const void * directive)25737 rs6000_xcoff_output_tls_section_asm_op (const void *directive)
25738 {
25739   fprintf (asm_out_file, "\t.csect %s[TL],%s\n",
25740 	   *(const char *const *) directive,
25741 	   XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
25742 }
25743 
25744 /* A get_unnamed_section callback, used for switching to toc_section.  */
25745 
25746 static void
rs6000_xcoff_output_toc_section_asm_op(const void * data ATTRIBUTE_UNUSED)25747 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
25748 {
25749   if (TARGET_MINIMAL_TOC)
25750     {
25751       /* toc_section is always selected at least once from
25752 	 rs6000_xcoff_file_start, so this is guaranteed to
25753 	 always be defined once and only once in each file.  */
25754       if (!toc_initialized)
25755 	{
25756 	  fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
25757 	  fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
25758 	  toc_initialized = 1;
25759 	}
25760       fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
25761 	       (TARGET_32BIT ? "" : ",3"));
25762     }
25763   else
25764     fputs ("\t.toc\n", asm_out_file);
25765 }
25766 
25767 /* Implement TARGET_ASM_INIT_SECTIONS.  */
25768 
25769 static void
rs6000_xcoff_asm_init_sections(void)25770 rs6000_xcoff_asm_init_sections (void)
25771 {
25772   read_only_data_section
25773     = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
25774 			   &xcoff_read_only_section_name);
25775 
25776   private_data_section
25777     = get_unnamed_section (SECTION_WRITE,
25778 			   rs6000_xcoff_output_readwrite_section_asm_op,
25779 			   &xcoff_private_data_section_name);
25780 
25781   tls_data_section
25782     = get_unnamed_section (SECTION_TLS,
25783 			   rs6000_xcoff_output_tls_section_asm_op,
25784 			   &xcoff_tls_data_section_name);
25785 
25786   tls_private_data_section
25787     = get_unnamed_section (SECTION_TLS,
25788 			   rs6000_xcoff_output_tls_section_asm_op,
25789 			   &xcoff_private_data_section_name);
25790 
25791   read_only_private_data_section
25792     = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
25793 			   &xcoff_private_data_section_name);
25794 
25795   toc_section
25796     = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
25797 
25798   readonly_data_section = read_only_data_section;
25799   exception_section = data_section;
25800 }
25801 
25802 static int
rs6000_xcoff_reloc_rw_mask(void)25803 rs6000_xcoff_reloc_rw_mask (void)
25804 {
25805   return 3;
25806 }
25807 
25808 static void
rs6000_xcoff_asm_named_section(const char * name,unsigned int flags,tree decl ATTRIBUTE_UNUSED)25809 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
25810 				tree decl ATTRIBUTE_UNUSED)
25811 {
25812   int smclass;
25813   static const char * const suffix[4] = { "PR", "RO", "RW", "TL" };
25814 
25815   if (flags & SECTION_CODE)
25816     smclass = 0;
25817   else if (flags & SECTION_TLS)
25818     smclass = 3;
25819   else if (flags & SECTION_WRITE)
25820     smclass = 2;
25821   else
25822     smclass = 1;
25823 
25824   fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
25825 	   (flags & SECTION_CODE) ? "." : "",
25826 	   name, suffix[smclass], flags & SECTION_ENTSIZE);
25827 }
25828 
25829 static section *
rs6000_xcoff_select_section(tree decl,int reloc,unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)25830 rs6000_xcoff_select_section (tree decl, int reloc,
25831 			     unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
25832 {
25833   if (decl_readonly_section (decl, reloc))
25834     {
25835       if (TREE_PUBLIC (decl))
25836 	return read_only_data_section;
25837       else
25838 	return read_only_private_data_section;
25839     }
25840   else
25841     {
25842 #if HAVE_AS_TLS
25843       if (TREE_CODE (decl) == VAR_DECL && DECL_THREAD_LOCAL_P (decl))
25844 	{
25845 	  if (TREE_PUBLIC (decl))
25846 	    return tls_data_section;
25847 	  else if (bss_initializer_p (decl))
25848 	    {
25849 	      /* Convert to COMMON to emit in BSS.  */
25850 	      DECL_COMMON (decl) = 1;
25851 	      return tls_comm_section;
25852 	    }
25853 	  else
25854 	    return tls_private_data_section;
25855 	}
25856       else
25857 #endif
25858 	if (TREE_PUBLIC (decl))
25859 	return data_section;
25860       else
25861 	return private_data_section;
25862     }
25863 }
25864 
25865 static void
rs6000_xcoff_unique_section(tree decl,int reloc ATTRIBUTE_UNUSED)25866 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
25867 {
25868   const char *name;
25869 
25870   /* Use select_section for private and uninitialized data.  */
25871   if (!TREE_PUBLIC (decl)
25872       || DECL_COMMON (decl)
25873       || DECL_INITIAL (decl) == NULL_TREE
25874       || DECL_INITIAL (decl) == error_mark_node
25875       || (flag_zero_initialized_in_bss
25876 	  && initializer_zerop (DECL_INITIAL (decl))))
25877     return;
25878 
25879   name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
25880   name = (*targetm.strip_name_encoding) (name);
25881   DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
25882 }
25883 
25884 /* Select section for constant in constant pool.
25885 
25886    On RS/6000, all constants are in the private read-only data area.
25887    However, if this is being placed in the TOC it must be output as a
25888    toc entry.  */
25889 
25890 static section *
rs6000_xcoff_select_rtx_section(enum machine_mode mode,rtx x,unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)25891 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
25892 				 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
25893 {
25894   if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
25895     return toc_section;
25896   else
25897     return read_only_private_data_section;
25898 }
25899 
25900 /* Remove any trailing [DS] or the like from the symbol name.  */
25901 
25902 static const char *
rs6000_xcoff_strip_name_encoding(const char * name)25903 rs6000_xcoff_strip_name_encoding (const char *name)
25904 {
25905   size_t len;
25906   if (*name == '*')
25907     name++;
25908   len = strlen (name);
25909   if (name[len - 1] == ']')
25910     return ggc_alloc_string (name, len - 4);
25911   else
25912     return name;
25913 }
25914 
25915 /* Section attributes.  AIX is always PIC.  */
25916 
25917 static unsigned int
rs6000_xcoff_section_type_flags(tree decl,const char * name,int reloc)25918 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
25919 {
25920   unsigned int align;
25921   unsigned int flags = default_section_type_flags (decl, name, reloc);
25922 
25923   /* Align to at least UNIT size.  */
25924   if ((flags & SECTION_CODE) != 0 || !decl || !DECL_P (decl))
25925     align = MIN_UNITS_PER_WORD;
25926   else
25927     /* Increase alignment of large objects if not already stricter.  */
25928     align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
25929 		 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
25930 		 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
25931 
25932   return flags | (exact_log2 (align) & SECTION_ENTSIZE);
25933 }
25934 
25935 /* Output at beginning of assembler file.
25936 
25937    Initialize the section names for the RS/6000 at this point.
25938 
25939    Specify filename, including full path, to assembler.
25940 
25941    We want to go into the TOC section so at least one .toc will be emitted.
25942    Also, in order to output proper .bs/.es pairs, we need at least one static
25943    [RW] section emitted.
25944 
25945    Finally, declare mcount when profiling to make the assembler happy.  */
25946 
25947 static void
rs6000_xcoff_file_start(void)25948 rs6000_xcoff_file_start (void)
25949 {
25950   rs6000_gen_section_name (&xcoff_bss_section_name,
25951 			   main_input_filename, ".bss_");
25952   rs6000_gen_section_name (&xcoff_private_data_section_name,
25953 			   main_input_filename, ".rw_");
25954   rs6000_gen_section_name (&xcoff_read_only_section_name,
25955 			   main_input_filename, ".ro_");
25956   rs6000_gen_section_name (&xcoff_tls_data_section_name,
25957 			   main_input_filename, ".tls_");
25958   rs6000_gen_section_name (&xcoff_tbss_section_name,
25959 			   main_input_filename, ".tbss_[UL]");
25960 
25961   fputs ("\t.file\t", asm_out_file);
25962   output_quoted_string (asm_out_file, main_input_filename);
25963   fputc ('\n', asm_out_file);
25964   if (write_symbols != NO_DEBUG)
25965     switch_to_section (private_data_section);
25966   switch_to_section (text_section);
25967   if (profile_flag)
25968     fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
25969   rs6000_file_start ();
25970 }
25971 
25972 /* Output at end of assembler file.
25973    On the RS/6000, referencing data should automatically pull in text.  */
25974 
25975 static void
rs6000_xcoff_file_end(void)25976 rs6000_xcoff_file_end (void)
25977 {
25978   switch_to_section (text_section);
25979   fputs ("_section_.text:\n", asm_out_file);
25980   switch_to_section (data_section);
25981   fputs (TARGET_32BIT
25982 	 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
25983 	 asm_out_file);
25984 }
25985 
25986 #ifdef HAVE_AS_TLS
25987 static void
rs6000_xcoff_encode_section_info(tree decl,rtx rtl,int first)25988 rs6000_xcoff_encode_section_info (tree decl, rtx rtl, int first)
25989 {
25990   rtx symbol;
25991   int flags;
25992 
25993   default_encode_section_info (decl, rtl, first);
25994 
25995   /* Careful not to prod global register variables.  */
25996   if (!MEM_P (rtl))
25997     return;
25998   symbol = XEXP (rtl, 0);
25999   if (GET_CODE (symbol) != SYMBOL_REF)
26000     return;
26001 
26002   flags = SYMBOL_REF_FLAGS (symbol);
26003 
26004   if (TREE_CODE (decl) == VAR_DECL && DECL_THREAD_LOCAL_P (decl))
26005     flags &= ~SYMBOL_FLAG_HAS_BLOCK_INFO;
26006 
26007   SYMBOL_REF_FLAGS (symbol) = flags;
26008 }
26009 #endif /* HAVE_AS_TLS */
26010 #endif /* TARGET_XCOFF */
26011 
26012 /* Compute a (partial) cost for rtx X.  Return true if the complete
26013    cost has been computed, and false if subexpressions should be
26014    scanned.  In either case, *TOTAL contains the cost result.  */
26015 
26016 static bool
rs6000_rtx_costs(rtx x,int code,int outer_code,int opno ATTRIBUTE_UNUSED,int * total,bool speed)26017 rs6000_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
26018 		  int *total, bool speed)
26019 {
26020   enum machine_mode mode = GET_MODE (x);
26021 
26022   switch (code)
26023     {
26024       /* On the RS/6000, if it is valid in the insn, it is free.  */
26025     case CONST_INT:
26026       if (((outer_code == SET
26027 	    || outer_code == PLUS
26028 	    || outer_code == MINUS)
26029 	   && (satisfies_constraint_I (x)
26030 	       || satisfies_constraint_L (x)))
26031 	  || (outer_code == AND
26032 	      && (satisfies_constraint_K (x)
26033 		  || (mode == SImode
26034 		      ? satisfies_constraint_L (x)
26035 		      : satisfies_constraint_J (x))
26036 		  || mask_operand (x, mode)
26037 		  || (mode == DImode
26038 		      && mask64_operand (x, DImode))))
26039 	  || ((outer_code == IOR || outer_code == XOR)
26040 	      && (satisfies_constraint_K (x)
26041 		  || (mode == SImode
26042 		      ? satisfies_constraint_L (x)
26043 		      : satisfies_constraint_J (x))))
26044 	  || outer_code == ASHIFT
26045 	  || outer_code == ASHIFTRT
26046 	  || outer_code == LSHIFTRT
26047 	  || outer_code == ROTATE
26048 	  || outer_code == ROTATERT
26049 	  || outer_code == ZERO_EXTRACT
26050 	  || (outer_code == MULT
26051 	      && satisfies_constraint_I (x))
26052 	  || ((outer_code == DIV || outer_code == UDIV
26053 	       || outer_code == MOD || outer_code == UMOD)
26054 	      && exact_log2 (INTVAL (x)) >= 0)
26055 	  || (outer_code == COMPARE
26056 	      && (satisfies_constraint_I (x)
26057 		  || satisfies_constraint_K (x)))
26058 	  || ((outer_code == EQ || outer_code == NE)
26059 	      && (satisfies_constraint_I (x)
26060 		  || satisfies_constraint_K (x)
26061 		  || (mode == SImode
26062 		      ? satisfies_constraint_L (x)
26063 		      : satisfies_constraint_J (x))))
26064 	  || (outer_code == GTU
26065 	      && satisfies_constraint_I (x))
26066 	  || (outer_code == LTU
26067 	      && satisfies_constraint_P (x)))
26068 	{
26069 	  *total = 0;
26070 	  return true;
26071 	}
26072       else if ((outer_code == PLUS
26073 		&& reg_or_add_cint_operand (x, VOIDmode))
26074 	       || (outer_code == MINUS
26075 		   && reg_or_sub_cint_operand (x, VOIDmode))
26076 	       || ((outer_code == SET
26077 		    || outer_code == IOR
26078 		    || outer_code == XOR)
26079 		   && (INTVAL (x)
26080 		       & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
26081 	{
26082 	  *total = COSTS_N_INSNS (1);
26083 	  return true;
26084 	}
26085       /* FALLTHRU */
26086 
26087     case CONST_DOUBLE:
26088       if (mode == DImode && code == CONST_DOUBLE)
26089 	{
26090 	  if ((outer_code == IOR || outer_code == XOR)
26091 	      && CONST_DOUBLE_HIGH (x) == 0
26092 	      && (CONST_DOUBLE_LOW (x)
26093 		  & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)
26094 	    {
26095 	      *total = 0;
26096 	      return true;
26097 	    }
26098 	  else if ((outer_code == AND && and64_2_operand (x, DImode))
26099 		   || ((outer_code == SET
26100 			|| outer_code == IOR
26101 			|| outer_code == XOR)
26102 		       && CONST_DOUBLE_HIGH (x) == 0))
26103 	    {
26104 	      *total = COSTS_N_INSNS (1);
26105 	      return true;
26106 	    }
26107 	}
26108       /* FALLTHRU */
26109 
26110     case CONST:
26111     case HIGH:
26112     case SYMBOL_REF:
26113     case MEM:
26114       /* When optimizing for size, MEM should be slightly more expensive
26115 	 than generating address, e.g., (plus (reg) (const)).
26116 	 L1 cache latency is about two instructions.  */
26117       *total = !speed ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
26118       return true;
26119 
26120     case LABEL_REF:
26121       *total = 0;
26122       return true;
26123 
26124     case PLUS:
26125     case MINUS:
26126       if (FLOAT_MODE_P (mode))
26127 	*total = rs6000_cost->fp;
26128       else
26129 	*total = COSTS_N_INSNS (1);
26130       return false;
26131 
26132     case MULT:
26133       if (GET_CODE (XEXP (x, 1)) == CONST_INT
26134 	  && satisfies_constraint_I (XEXP (x, 1)))
26135 	{
26136 	  if (INTVAL (XEXP (x, 1)) >= -256
26137 	      && INTVAL (XEXP (x, 1)) <= 255)
26138 	    *total = rs6000_cost->mulsi_const9;
26139 	  else
26140 	    *total = rs6000_cost->mulsi_const;
26141 	}
26142       else if (mode == SFmode)
26143 	*total = rs6000_cost->fp;
26144       else if (FLOAT_MODE_P (mode))
26145 	*total = rs6000_cost->dmul;
26146       else if (mode == DImode)
26147 	*total = rs6000_cost->muldi;
26148       else
26149 	*total = rs6000_cost->mulsi;
26150       return false;
26151 
26152     case FMA:
26153       if (mode == SFmode)
26154 	*total = rs6000_cost->fp;
26155       else
26156 	*total = rs6000_cost->dmul;
26157       break;
26158 
26159     case DIV:
26160     case MOD:
26161       if (FLOAT_MODE_P (mode))
26162 	{
26163 	  *total = mode == DFmode ? rs6000_cost->ddiv
26164 				  : rs6000_cost->sdiv;
26165 	  return false;
26166 	}
26167       /* FALLTHRU */
26168 
26169     case UDIV:
26170     case UMOD:
26171       if (GET_CODE (XEXP (x, 1)) == CONST_INT
26172 	  && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
26173 	{
26174 	  if (code == DIV || code == MOD)
26175 	    /* Shift, addze */
26176 	    *total = COSTS_N_INSNS (2);
26177 	  else
26178 	    /* Shift */
26179 	    *total = COSTS_N_INSNS (1);
26180 	}
26181       else
26182 	{
26183 	  if (GET_MODE (XEXP (x, 1)) == DImode)
26184 	    *total = rs6000_cost->divdi;
26185 	  else
26186 	    *total = rs6000_cost->divsi;
26187 	}
26188       /* Add in shift and subtract for MOD. */
26189       if (code == MOD || code == UMOD)
26190 	*total += COSTS_N_INSNS (2);
26191       return false;
26192 
26193     case CTZ:
26194     case FFS:
26195       *total = COSTS_N_INSNS (4);
26196       return false;
26197 
26198     case POPCOUNT:
26199       *total = COSTS_N_INSNS (TARGET_POPCNTD ? 1 : 6);
26200       return false;
26201 
26202     case PARITY:
26203       *total = COSTS_N_INSNS (TARGET_CMPB ? 2 : 6);
26204       return false;
26205 
26206     case NOT:
26207       if (outer_code == AND || outer_code == IOR || outer_code == XOR)
26208 	{
26209 	  *total = 0;
26210 	  return false;
26211 	}
26212       /* FALLTHRU */
26213 
26214     case AND:
26215     case CLZ:
26216     case IOR:
26217     case XOR:
26218     case ZERO_EXTRACT:
26219       *total = COSTS_N_INSNS (1);
26220       return false;
26221 
26222     case ASHIFT:
26223     case ASHIFTRT:
26224     case LSHIFTRT:
26225     case ROTATE:
26226     case ROTATERT:
26227       /* Handle mul_highpart.  */
26228       if (outer_code == TRUNCATE
26229 	  && GET_CODE (XEXP (x, 0)) == MULT)
26230 	{
26231 	  if (mode == DImode)
26232 	    *total = rs6000_cost->muldi;
26233 	  else
26234 	    *total = rs6000_cost->mulsi;
26235 	  return true;
26236 	}
26237       else if (outer_code == AND)
26238 	*total = 0;
26239       else
26240 	*total = COSTS_N_INSNS (1);
26241       return false;
26242 
26243     case SIGN_EXTEND:
26244     case ZERO_EXTEND:
26245       if (GET_CODE (XEXP (x, 0)) == MEM)
26246 	*total = 0;
26247       else
26248 	*total = COSTS_N_INSNS (1);
26249       return false;
26250 
26251     case COMPARE:
26252     case NEG:
26253     case ABS:
26254       if (!FLOAT_MODE_P (mode))
26255 	{
26256 	  *total = COSTS_N_INSNS (1);
26257 	  return false;
26258 	}
26259       /* FALLTHRU */
26260 
26261     case FLOAT:
26262     case UNSIGNED_FLOAT:
26263     case FIX:
26264     case UNSIGNED_FIX:
26265     case FLOAT_TRUNCATE:
26266       *total = rs6000_cost->fp;
26267       return false;
26268 
26269     case FLOAT_EXTEND:
26270       if (mode == DFmode)
26271 	*total = 0;
26272       else
26273 	*total = rs6000_cost->fp;
26274       return false;
26275 
26276     case UNSPEC:
26277       switch (XINT (x, 1))
26278 	{
26279 	case UNSPEC_FRSP:
26280 	  *total = rs6000_cost->fp;
26281 	  return true;
26282 
26283 	default:
26284 	  break;
26285 	}
26286       break;
26287 
26288     case CALL:
26289     case IF_THEN_ELSE:
26290       if (!speed)
26291 	{
26292 	  *total = COSTS_N_INSNS (1);
26293 	  return true;
26294 	}
26295       else if (FLOAT_MODE_P (mode)
26296 	       && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
26297 	{
26298 	  *total = rs6000_cost->fp;
26299 	  return false;
26300 	}
26301       break;
26302 
26303     case EQ:
26304     case GTU:
26305     case LTU:
26306       /* Carry bit requires mode == Pmode.
26307 	 NEG or PLUS already counted so only add one.  */
26308       if (mode == Pmode
26309 	  && (outer_code == NEG || outer_code == PLUS))
26310 	{
26311 	  *total = COSTS_N_INSNS (1);
26312 	  return true;
26313 	}
26314       if (outer_code == SET)
26315 	{
26316 	  if (XEXP (x, 1) == const0_rtx)
26317 	    {
26318 	      if (TARGET_ISEL && !TARGET_MFCRF)
26319 		*total = COSTS_N_INSNS (8);
26320 	      else
26321 		*total = COSTS_N_INSNS (2);
26322 	      return true;
26323 	    }
26324 	  else if (mode == Pmode)
26325 	    {
26326 	      *total = COSTS_N_INSNS (3);
26327 	      return false;
26328 	    }
26329 	}
26330       /* FALLTHRU */
26331 
26332     case GT:
26333     case LT:
26334     case UNORDERED:
26335       if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
26336 	{
26337 	  if (TARGET_ISEL && !TARGET_MFCRF)
26338 	    *total = COSTS_N_INSNS (8);
26339 	  else
26340 	    *total = COSTS_N_INSNS (2);
26341 	  return true;
26342 	}
26343       /* CC COMPARE.  */
26344       if (outer_code == COMPARE)
26345 	{
26346 	  *total = 0;
26347 	  return true;
26348 	}
26349       break;
26350 
26351     default:
26352       break;
26353     }
26354 
26355   return false;
26356 }
26357 
26358 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost.  */
26359 
26360 static bool
rs6000_debug_rtx_costs(rtx x,int code,int outer_code,int opno,int * total,bool speed)26361 rs6000_debug_rtx_costs (rtx x, int code, int outer_code, int opno, int *total,
26362 			bool speed)
26363 {
26364   bool ret = rs6000_rtx_costs (x, code, outer_code, opno, total, speed);
26365 
26366   fprintf (stderr,
26367 	   "\nrs6000_rtx_costs, return = %s, code = %s, outer_code = %s, "
26368 	   "opno = %d, total = %d, speed = %s, x:\n",
26369 	   ret ? "complete" : "scan inner",
26370 	   GET_RTX_NAME (code),
26371 	   GET_RTX_NAME (outer_code),
26372 	   opno,
26373 	   *total,
26374 	   speed ? "true" : "false");
26375 
26376   debug_rtx (x);
26377 
26378   return ret;
26379 }
26380 
26381 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost.  */
26382 
26383 static int
rs6000_debug_address_cost(rtx x,enum machine_mode mode,addr_space_t as,bool speed)26384 rs6000_debug_address_cost (rtx x, enum machine_mode mode,
26385 			   addr_space_t as, bool speed)
26386 {
26387   int ret = TARGET_ADDRESS_COST (x, mode, as, speed);
26388 
26389   fprintf (stderr, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
26390 	   ret, speed ? "true" : "false");
26391   debug_rtx (x);
26392 
26393   return ret;
26394 }
26395 
26396 
26397 /* A C expression returning the cost of moving data from a register of class
26398    CLASS1 to one of CLASS2.  */
26399 
26400 static int
rs6000_register_move_cost(enum machine_mode mode,reg_class_t from,reg_class_t to)26401 rs6000_register_move_cost (enum machine_mode mode,
26402 			   reg_class_t from, reg_class_t to)
26403 {
26404   int ret;
26405 
26406   if (TARGET_DEBUG_COST)
26407     dbg_cost_ctrl++;
26408 
26409   /*  Moves from/to GENERAL_REGS.  */
26410   if (reg_classes_intersect_p (to, GENERAL_REGS)
26411       || reg_classes_intersect_p (from, GENERAL_REGS))
26412     {
26413       reg_class_t rclass = from;
26414 
26415       if (! reg_classes_intersect_p (to, GENERAL_REGS))
26416 	rclass = to;
26417 
26418       if (rclass == FLOAT_REGS || rclass == ALTIVEC_REGS || rclass == VSX_REGS)
26419 	ret = (rs6000_memory_move_cost (mode, rclass, false)
26420 	       + rs6000_memory_move_cost (mode, GENERAL_REGS, false));
26421 
26422       /* It's more expensive to move CR_REGS than CR0_REGS because of the
26423 	 shift.  */
26424       else if (rclass == CR_REGS)
26425 	ret = 4;
26426 
26427       /* For those processors that have slow LR/CTR moves, make them more
26428          expensive than memory in order to bias spills to memory .*/
26429       else if ((rs6000_cpu == PROCESSOR_POWER6
26430 		|| rs6000_cpu == PROCESSOR_POWER7)
26431 	       && reg_classes_intersect_p (rclass, LINK_OR_CTR_REGS))
26432         ret = 6 * hard_regno_nregs[0][mode];
26433 
26434       else
26435 	/* A move will cost one instruction per GPR moved.  */
26436 	ret = 2 * hard_regno_nregs[0][mode];
26437     }
26438 
26439   /* If we have VSX, we can easily move between FPR or Altivec registers.  */
26440   else if (VECTOR_UNIT_VSX_P (mode)
26441 	   && reg_classes_intersect_p (to, VSX_REGS)
26442 	   && reg_classes_intersect_p (from, VSX_REGS))
26443     ret = 2 * hard_regno_nregs[32][mode];
26444 
26445   /* Moving between two similar registers is just one instruction.  */
26446   else if (reg_classes_intersect_p (to, from))
26447     ret = (mode == TFmode || mode == TDmode) ? 4 : 2;
26448 
26449   /* Everything else has to go through GENERAL_REGS.  */
26450   else
26451     ret = (rs6000_register_move_cost (mode, GENERAL_REGS, to)
26452 	   + rs6000_register_move_cost (mode, from, GENERAL_REGS));
26453 
26454   if (TARGET_DEBUG_COST)
26455     {
26456       if (dbg_cost_ctrl == 1)
26457 	fprintf (stderr,
26458 		 "rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n",
26459 		 ret, GET_MODE_NAME (mode), reg_class_names[from],
26460 		 reg_class_names[to]);
26461       dbg_cost_ctrl--;
26462     }
26463 
26464   return ret;
26465 }
26466 
26467 /* A C expressions returning the cost of moving data of MODE from a register to
26468    or from memory.  */
26469 
26470 static int
rs6000_memory_move_cost(enum machine_mode mode,reg_class_t rclass,bool in ATTRIBUTE_UNUSED)26471 rs6000_memory_move_cost (enum machine_mode mode, reg_class_t rclass,
26472 			 bool in ATTRIBUTE_UNUSED)
26473 {
26474   int ret;
26475 
26476   if (TARGET_DEBUG_COST)
26477     dbg_cost_ctrl++;
26478 
26479   if (reg_classes_intersect_p (rclass, GENERAL_REGS))
26480     ret = 4 * hard_regno_nregs[0][mode];
26481   else if (reg_classes_intersect_p (rclass, FLOAT_REGS))
26482     ret = 4 * hard_regno_nregs[32][mode];
26483   else if (reg_classes_intersect_p (rclass, ALTIVEC_REGS))
26484     ret = 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];
26485   else
26486     ret = 4 + rs6000_register_move_cost (mode, rclass, GENERAL_REGS);
26487 
26488   if (TARGET_DEBUG_COST)
26489     {
26490       if (dbg_cost_ctrl == 1)
26491 	fprintf (stderr,
26492 		 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
26493 		 ret, GET_MODE_NAME (mode), reg_class_names[rclass], in);
26494       dbg_cost_ctrl--;
26495     }
26496 
26497   return ret;
26498 }
26499 
26500 /* Returns a code for a target-specific builtin that implements
26501    reciprocal of the function, or NULL_TREE if not available.  */
26502 
26503 static tree
rs6000_builtin_reciprocal(unsigned int fn,bool md_fn,bool sqrt ATTRIBUTE_UNUSED)26504 rs6000_builtin_reciprocal (unsigned int fn, bool md_fn,
26505 			   bool sqrt ATTRIBUTE_UNUSED)
26506 {
26507   if (optimize_insn_for_size_p ())
26508     return NULL_TREE;
26509 
26510   if (md_fn)
26511     switch (fn)
26512       {
26513       case VSX_BUILTIN_XVSQRTDP:
26514 	if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode))
26515 	  return NULL_TREE;
26516 
26517 	return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
26518 
26519       case VSX_BUILTIN_XVSQRTSP:
26520 	if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode))
26521 	  return NULL_TREE;
26522 
26523 	return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_4SF];
26524 
26525       default:
26526 	return NULL_TREE;
26527       }
26528 
26529   else
26530     switch (fn)
26531       {
26532       case BUILT_IN_SQRT:
26533 	if (!RS6000_RECIP_AUTO_RSQRTE_P (DFmode))
26534 	  return NULL_TREE;
26535 
26536 	return rs6000_builtin_decls[RS6000_BUILTIN_RSQRT];
26537 
26538       case BUILT_IN_SQRTF:
26539 	if (!RS6000_RECIP_AUTO_RSQRTE_P (SFmode))
26540 	  return NULL_TREE;
26541 
26542 	return rs6000_builtin_decls[RS6000_BUILTIN_RSQRTF];
26543 
26544       default:
26545 	return NULL_TREE;
26546       }
26547 }
26548 
26549 /* Load up a constant.  If the mode is a vector mode, splat the value across
26550    all of the vector elements.  */
26551 
26552 static rtx
rs6000_load_constant_and_splat(enum machine_mode mode,REAL_VALUE_TYPE dconst)26553 rs6000_load_constant_and_splat (enum machine_mode mode, REAL_VALUE_TYPE dconst)
26554 {
26555   rtx reg;
26556 
26557   if (mode == SFmode || mode == DFmode)
26558     {
26559       rtx d = CONST_DOUBLE_FROM_REAL_VALUE (dconst, mode);
26560       reg = force_reg (mode, d);
26561     }
26562   else if (mode == V4SFmode)
26563     {
26564       rtx d = CONST_DOUBLE_FROM_REAL_VALUE (dconst, SFmode);
26565       rtvec v = gen_rtvec (4, d, d, d, d);
26566       reg = gen_reg_rtx (mode);
26567       rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
26568     }
26569   else if (mode == V2DFmode)
26570     {
26571       rtx d = CONST_DOUBLE_FROM_REAL_VALUE (dconst, DFmode);
26572       rtvec v = gen_rtvec (2, d, d);
26573       reg = gen_reg_rtx (mode);
26574       rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
26575     }
26576   else
26577     gcc_unreachable ();
26578 
26579   return reg;
26580 }
26581 
26582 /* Generate an FMA instruction.  */
26583 
26584 static void
rs6000_emit_madd(rtx target,rtx m1,rtx m2,rtx a)26585 rs6000_emit_madd (rtx target, rtx m1, rtx m2, rtx a)
26586 {
26587   enum machine_mode mode = GET_MODE (target);
26588   rtx dst;
26589 
26590   dst = expand_ternary_op (mode, fma_optab, m1, m2, a, target, 0);
26591   gcc_assert (dst != NULL);
26592 
26593   if (dst != target)
26594     emit_move_insn (target, dst);
26595 }
26596 
26597 /* Generate a FMSUB instruction: dst = fma(m1, m2, -a).  */
26598 
26599 static void
rs6000_emit_msub(rtx target,rtx m1,rtx m2,rtx a)26600 rs6000_emit_msub (rtx target, rtx m1, rtx m2, rtx a)
26601 {
26602   enum machine_mode mode = GET_MODE (target);
26603   rtx dst;
26604 
26605   /* Altivec does not support fms directly;
26606      generate in terms of fma in that case.  */
26607   if (optab_handler (fms_optab, mode) != CODE_FOR_nothing)
26608     dst = expand_ternary_op (mode, fms_optab, m1, m2, a, target, 0);
26609   else
26610     {
26611       a = expand_unop (mode, neg_optab, a, NULL_RTX, 0);
26612       dst = expand_ternary_op (mode, fma_optab, m1, m2, a, target, 0);
26613     }
26614   gcc_assert (dst != NULL);
26615 
26616   if (dst != target)
26617     emit_move_insn (target, dst);
26618 }
26619 
26620 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a).  */
26621 
26622 static void
rs6000_emit_nmsub(rtx dst,rtx m1,rtx m2,rtx a)26623 rs6000_emit_nmsub (rtx dst, rtx m1, rtx m2, rtx a)
26624 {
26625   enum machine_mode mode = GET_MODE (dst);
26626   rtx r;
26627 
26628   /* This is a tad more complicated, since the fnma_optab is for
26629      a different expression: fma(-m1, m2, a), which is the same
26630      thing except in the case of signed zeros.
26631 
26632      Fortunately we know that if FMA is supported that FNMSUB is
26633      also supported in the ISA.  Just expand it directly.  */
26634 
26635   gcc_assert (optab_handler (fma_optab, mode) != CODE_FOR_nothing);
26636 
26637   r = gen_rtx_NEG (mode, a);
26638   r = gen_rtx_FMA (mode, m1, m2, r);
26639   r = gen_rtx_NEG (mode, r);
26640   emit_insn (gen_rtx_SET (VOIDmode, dst, r));
26641 }
26642 
26643 /* Newton-Raphson approximation of floating point divide with just 2 passes
26644    (either single precision floating point, or newer machines with higher
26645    accuracy estimates).  Support both scalar and vector divide.  Assumes no
26646    trapping math and finite arguments.  */
26647 
26648 static void
rs6000_emit_swdiv_high_precision(rtx dst,rtx n,rtx d)26649 rs6000_emit_swdiv_high_precision (rtx dst, rtx n, rtx d)
26650 {
26651   enum machine_mode mode = GET_MODE (dst);
26652   rtx x0, e0, e1, y1, u0, v0;
26653   enum insn_code code = optab_handler (smul_optab, mode);
26654   gen_2arg_fn_t gen_mul = (gen_2arg_fn_t) GEN_FCN (code);
26655   rtx one = rs6000_load_constant_and_splat (mode, dconst1);
26656 
26657   gcc_assert (code != CODE_FOR_nothing);
26658 
26659   /* x0 = 1./d estimate */
26660   x0 = gen_reg_rtx (mode);
26661   emit_insn (gen_rtx_SET (VOIDmode, x0,
26662 			  gen_rtx_UNSPEC (mode, gen_rtvec (1, d),
26663 					  UNSPEC_FRES)));
26664 
26665   e0 = gen_reg_rtx (mode);
26666   rs6000_emit_nmsub (e0, d, x0, one);		/* e0 = 1. - (d * x0) */
26667 
26668   e1 = gen_reg_rtx (mode);
26669   rs6000_emit_madd (e1, e0, e0, e0);		/* e1 = (e0 * e0) + e0 */
26670 
26671   y1 = gen_reg_rtx (mode);
26672   rs6000_emit_madd (y1, e1, x0, x0);		/* y1 = (e1 * x0) + x0 */
26673 
26674   u0 = gen_reg_rtx (mode);
26675   emit_insn (gen_mul (u0, n, y1));		/* u0 = n * y1 */
26676 
26677   v0 = gen_reg_rtx (mode);
26678   rs6000_emit_nmsub (v0, d, u0, n);		/* v0 = n - (d * u0) */
26679 
26680   rs6000_emit_madd (dst, v0, y1, u0);		/* dst = (v0 * y1) + u0 */
26681 }
26682 
26683 /* Newton-Raphson approximation of floating point divide that has a low
26684    precision estimate.  Assumes no trapping math and finite arguments.  */
26685 
26686 static void
rs6000_emit_swdiv_low_precision(rtx dst,rtx n,rtx d)26687 rs6000_emit_swdiv_low_precision (rtx dst, rtx n, rtx d)
26688 {
26689   enum machine_mode mode = GET_MODE (dst);
26690   rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one;
26691   enum insn_code code = optab_handler (smul_optab, mode);
26692   gen_2arg_fn_t gen_mul = (gen_2arg_fn_t) GEN_FCN (code);
26693 
26694   gcc_assert (code != CODE_FOR_nothing);
26695 
26696   one = rs6000_load_constant_and_splat (mode, dconst1);
26697 
26698   /* x0 = 1./d estimate */
26699   x0 = gen_reg_rtx (mode);
26700   emit_insn (gen_rtx_SET (VOIDmode, x0,
26701 			  gen_rtx_UNSPEC (mode, gen_rtvec (1, d),
26702 					  UNSPEC_FRES)));
26703 
26704   e0 = gen_reg_rtx (mode);
26705   rs6000_emit_nmsub (e0, d, x0, one);		/* e0 = 1. - d * x0 */
26706 
26707   y1 = gen_reg_rtx (mode);
26708   rs6000_emit_madd (y1, e0, x0, x0);		/* y1 = x0 + e0 * x0 */
26709 
26710   e1 = gen_reg_rtx (mode);
26711   emit_insn (gen_mul (e1, e0, e0));		/* e1 = e0 * e0 */
26712 
26713   y2 = gen_reg_rtx (mode);
26714   rs6000_emit_madd (y2, e1, y1, y1);		/* y2 = y1 + e1 * y1 */
26715 
26716   e2 = gen_reg_rtx (mode);
26717   emit_insn (gen_mul (e2, e1, e1));		/* e2 = e1 * e1 */
26718 
26719   y3 = gen_reg_rtx (mode);
26720   rs6000_emit_madd (y3, e2, y2, y2);		/* y3 = y2 + e2 * y2 */
26721 
26722   u0 = gen_reg_rtx (mode);
26723   emit_insn (gen_mul (u0, n, y3));		/* u0 = n * y3 */
26724 
26725   v0 = gen_reg_rtx (mode);
26726   rs6000_emit_nmsub (v0, d, u0, n);		/* v0 = n - d * u0 */
26727 
26728   rs6000_emit_madd (dst, v0, y3, u0);		/* dst = u0 + v0 * y3 */
26729 }
26730 
26731 /* Newton-Raphson approximation of floating point divide DST = N/D.  If NOTE_P,
26732    add a reg_note saying that this was a division.  Support both scalar and
26733    vector divide.  Assumes no trapping math and finite arguments.  */
26734 
26735 void
rs6000_emit_swdiv(rtx dst,rtx n,rtx d,bool note_p)26736 rs6000_emit_swdiv (rtx dst, rtx n, rtx d, bool note_p)
26737 {
26738   enum machine_mode mode = GET_MODE (dst);
26739 
26740   if (RS6000_RECIP_HIGH_PRECISION_P (mode))
26741     rs6000_emit_swdiv_high_precision (dst, n, d);
26742   else
26743     rs6000_emit_swdiv_low_precision (dst, n, d);
26744 
26745   if (note_p)
26746     add_reg_note (get_last_insn (), REG_EQUAL, gen_rtx_DIV (mode, n, d));
26747 }
26748 
26749 /* Newton-Raphson approximation of single/double-precision floating point
26750    rsqrt.  Assumes no trapping math and finite arguments.  */
26751 
26752 void
rs6000_emit_swrsqrt(rtx dst,rtx src)26753 rs6000_emit_swrsqrt (rtx dst, rtx src)
26754 {
26755   enum machine_mode mode = GET_MODE (src);
26756   rtx x0 = gen_reg_rtx (mode);
26757   rtx y = gen_reg_rtx (mode);
26758   int passes = (TARGET_RECIP_PRECISION) ? 2 : 3;
26759   REAL_VALUE_TYPE dconst3_2;
26760   int i;
26761   rtx halfthree;
26762   enum insn_code code = optab_handler (smul_optab, mode);
26763   gen_2arg_fn_t gen_mul = (gen_2arg_fn_t) GEN_FCN (code);
26764 
26765   gcc_assert (code != CODE_FOR_nothing);
26766 
26767   /* Load up the constant 1.5 either as a scalar, or as a vector.  */
26768   real_from_integer (&dconst3_2, VOIDmode, 3, 0, 0);
26769   SET_REAL_EXP (&dconst3_2, REAL_EXP (&dconst3_2) - 1);
26770 
26771   halfthree = rs6000_load_constant_and_splat (mode, dconst3_2);
26772 
26773   /* x0 = rsqrt estimate */
26774   emit_insn (gen_rtx_SET (VOIDmode, x0,
26775 			  gen_rtx_UNSPEC (mode, gen_rtvec (1, src),
26776 					  UNSPEC_RSQRT)));
26777 
26778   /* y = 0.5 * src = 1.5 * src - src -> fewer constants */
26779   rs6000_emit_msub (y, src, halfthree, src);
26780 
26781   for (i = 0; i < passes; i++)
26782     {
26783       rtx x1 = gen_reg_rtx (mode);
26784       rtx u = gen_reg_rtx (mode);
26785       rtx v = gen_reg_rtx (mode);
26786 
26787       /* x1 = x0 * (1.5 - y * (x0 * x0)) */
26788       emit_insn (gen_mul (u, x0, x0));
26789       rs6000_emit_nmsub (v, y, u, halfthree);
26790       emit_insn (gen_mul (x1, x0, v));
26791       x0 = x1;
26792     }
26793 
26794   emit_move_insn (dst, x0);
26795   return;
26796 }
26797 
26798 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
26799    (Power7) targets.  DST is the target, and SRC is the argument operand.  */
26800 
26801 void
rs6000_emit_popcount(rtx dst,rtx src)26802 rs6000_emit_popcount (rtx dst, rtx src)
26803 {
26804   enum machine_mode mode = GET_MODE (dst);
26805   rtx tmp1, tmp2;
26806 
26807   /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can.  */
26808   if (TARGET_POPCNTD)
26809     {
26810       if (mode == SImode)
26811 	emit_insn (gen_popcntdsi2 (dst, src));
26812       else
26813 	emit_insn (gen_popcntddi2 (dst, src));
26814       return;
26815     }
26816 
26817   tmp1 = gen_reg_rtx (mode);
26818 
26819   if (mode == SImode)
26820     {
26821       emit_insn (gen_popcntbsi2 (tmp1, src));
26822       tmp2 = expand_mult (SImode, tmp1, GEN_INT (0x01010101),
26823 			   NULL_RTX, 0);
26824       tmp2 = force_reg (SImode, tmp2);
26825       emit_insn (gen_lshrsi3 (dst, tmp2, GEN_INT (24)));
26826     }
26827   else
26828     {
26829       emit_insn (gen_popcntbdi2 (tmp1, src));
26830       tmp2 = expand_mult (DImode, tmp1,
26831 			  GEN_INT ((HOST_WIDE_INT)
26832 				   0x01010101 << 32 | 0x01010101),
26833 			  NULL_RTX, 0);
26834       tmp2 = force_reg (DImode, tmp2);
26835       emit_insn (gen_lshrdi3 (dst, tmp2, GEN_INT (56)));
26836     }
26837 }
26838 
26839 
26840 /* Emit parity intrinsic on TARGET_POPCNTB targets.  DST is the
26841    target, and SRC is the argument operand.  */
26842 
26843 void
rs6000_emit_parity(rtx dst,rtx src)26844 rs6000_emit_parity (rtx dst, rtx src)
26845 {
26846   enum machine_mode mode = GET_MODE (dst);
26847   rtx tmp;
26848 
26849   tmp = gen_reg_rtx (mode);
26850 
26851   /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can.  */
26852   if (TARGET_CMPB)
26853     {
26854       if (mode == SImode)
26855 	{
26856 	  emit_insn (gen_popcntbsi2 (tmp, src));
26857 	  emit_insn (gen_paritysi2_cmpb (dst, tmp));
26858 	}
26859       else
26860 	{
26861 	  emit_insn (gen_popcntbdi2 (tmp, src));
26862 	  emit_insn (gen_paritydi2_cmpb (dst, tmp));
26863 	}
26864       return;
26865     }
26866 
26867   if (mode == SImode)
26868     {
26869       /* Is mult+shift >= shift+xor+shift+xor?  */
26870       if (rs6000_cost->mulsi_const >= COSTS_N_INSNS (3))
26871 	{
26872 	  rtx tmp1, tmp2, tmp3, tmp4;
26873 
26874 	  tmp1 = gen_reg_rtx (SImode);
26875 	  emit_insn (gen_popcntbsi2 (tmp1, src));
26876 
26877 	  tmp2 = gen_reg_rtx (SImode);
26878 	  emit_insn (gen_lshrsi3 (tmp2, tmp1, GEN_INT (16)));
26879 	  tmp3 = gen_reg_rtx (SImode);
26880 	  emit_insn (gen_xorsi3 (tmp3, tmp1, tmp2));
26881 
26882 	  tmp4 = gen_reg_rtx (SImode);
26883 	  emit_insn (gen_lshrsi3 (tmp4, tmp3, GEN_INT (8)));
26884 	  emit_insn (gen_xorsi3 (tmp, tmp3, tmp4));
26885 	}
26886       else
26887 	rs6000_emit_popcount (tmp, src);
26888       emit_insn (gen_andsi3 (dst, tmp, const1_rtx));
26889     }
26890   else
26891     {
26892       /* Is mult+shift >= shift+xor+shift+xor+shift+xor?  */
26893       if (rs6000_cost->muldi >= COSTS_N_INSNS (5))
26894 	{
26895 	  rtx tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
26896 
26897 	  tmp1 = gen_reg_rtx (DImode);
26898 	  emit_insn (gen_popcntbdi2 (tmp1, src));
26899 
26900 	  tmp2 = gen_reg_rtx (DImode);
26901 	  emit_insn (gen_lshrdi3 (tmp2, tmp1, GEN_INT (32)));
26902 	  tmp3 = gen_reg_rtx (DImode);
26903 	  emit_insn (gen_xordi3 (tmp3, tmp1, tmp2));
26904 
26905 	  tmp4 = gen_reg_rtx (DImode);
26906 	  emit_insn (gen_lshrdi3 (tmp4, tmp3, GEN_INT (16)));
26907 	  tmp5 = gen_reg_rtx (DImode);
26908 	  emit_insn (gen_xordi3 (tmp5, tmp3, tmp4));
26909 
26910 	  tmp6 = gen_reg_rtx (DImode);
26911 	  emit_insn (gen_lshrdi3 (tmp6, tmp5, GEN_INT (8)));
26912 	  emit_insn (gen_xordi3 (tmp, tmp5, tmp6));
26913 	}
26914       else
26915         rs6000_emit_popcount (tmp, src);
26916       emit_insn (gen_anddi3 (dst, tmp, const1_rtx));
26917     }
26918 }
26919 
26920 /* Expand an Altivec constant permutation.  Return true if we match
26921    an efficient implementation; false to fall back to VPERM.  */
26922 
26923 bool
altivec_expand_vec_perm_const(rtx operands[4])26924 altivec_expand_vec_perm_const (rtx operands[4])
26925 {
26926   struct altivec_perm_insn {
26927     enum insn_code impl;
26928     unsigned char perm[16];
26929   };
26930   static const struct altivec_perm_insn patterns[] = {
26931     { CODE_FOR_altivec_vpkuhum,
26932       {  1,  3,  5,  7,  9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
26933     { CODE_FOR_altivec_vpkuwum,
26934       {  2,  3,  6,  7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
26935     { CODE_FOR_altivec_vmrghb,
26936       {  0, 16,  1, 17,  2, 18,  3, 19,  4, 20,  5, 21,  6, 22,  7, 23 } },
26937     { CODE_FOR_altivec_vmrghh,
26938       {  0,  1, 16, 17,  2,  3, 18, 19,  4,  5, 20, 21,  6,  7, 22, 23 } },
26939     { CODE_FOR_altivec_vmrghw,
26940       {  0,  1,  2,  3, 16, 17, 18, 19,  4,  5,  6,  7, 20, 21, 22, 23 } },
26941     { CODE_FOR_altivec_vmrglb,
26942       {  8, 24,  9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
26943     { CODE_FOR_altivec_vmrglh,
26944       {  8,  9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
26945     { CODE_FOR_altivec_vmrglw,
26946       {  8,  9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } }
26947   };
26948 
26949   unsigned int i, j, elt, which;
26950   unsigned char perm[16];
26951   rtx target, op0, op1, sel, x;
26952   bool one_vec;
26953 
26954   target = operands[0];
26955   op0 = operands[1];
26956   op1 = operands[2];
26957   sel = operands[3];
26958 
26959   /* Unpack the constant selector.  */
26960   for (i = which = 0; i < 16; ++i)
26961     {
26962       rtx e = XVECEXP (sel, 0, i);
26963       elt = INTVAL (e) & 31;
26964       which |= (elt < 16 ? 1 : 2);
26965       perm[i] = elt;
26966     }
26967 
26968   /* Simplify the constant selector based on operands.  */
26969   switch (which)
26970     {
26971     default:
26972       gcc_unreachable ();
26973 
26974     case 3:
26975       one_vec = false;
26976       if (!rtx_equal_p (op0, op1))
26977 	break;
26978       /* FALLTHRU */
26979 
26980     case 2:
26981       for (i = 0; i < 16; ++i)
26982 	perm[i] &= 15;
26983       op0 = op1;
26984       one_vec = true;
26985       break;
26986 
26987     case 1:
26988       op1 = op0;
26989       one_vec = true;
26990       break;
26991     }
26992 
26993   /* Look for splat patterns.  */
26994   if (one_vec)
26995     {
26996       elt = perm[0];
26997 
26998       for (i = 0; i < 16; ++i)
26999 	if (perm[i] != elt)
27000 	  break;
27001       if (i == 16)
27002 	{
27003 	  emit_insn (gen_altivec_vspltb (target, op0, GEN_INT (elt)));
27004 	  return true;
27005 	}
27006 
27007       if (elt % 2 == 0)
27008 	{
27009 	  for (i = 0; i < 16; i += 2)
27010 	    if (perm[i] != elt || perm[i + 1] != elt + 1)
27011 	      break;
27012 	  if (i == 16)
27013 	    {
27014 	      x = gen_reg_rtx (V8HImode);
27015 	      emit_insn (gen_altivec_vsplth (x, gen_lowpart (V8HImode, op0),
27016 					     GEN_INT (elt / 2)));
27017 	      emit_move_insn (target, gen_lowpart (V16QImode, x));
27018 	      return true;
27019 	    }
27020 	}
27021 
27022       if (elt % 4 == 0)
27023 	{
27024 	  for (i = 0; i < 16; i += 4)
27025 	    if (perm[i] != elt
27026 		|| perm[i + 1] != elt + 1
27027 		|| perm[i + 2] != elt + 2
27028 		|| perm[i + 3] != elt + 3)
27029 	      break;
27030 	  if (i == 16)
27031 	    {
27032 	      x = gen_reg_rtx (V4SImode);
27033 	      emit_insn (gen_altivec_vspltw (x, gen_lowpart (V4SImode, op0),
27034 					     GEN_INT (elt / 4)));
27035 	      emit_move_insn (target, gen_lowpart (V16QImode, x));
27036 	      return true;
27037 	    }
27038 	}
27039     }
27040 
27041   /* Look for merge and pack patterns.  */
27042   for (j = 0; j < ARRAY_SIZE (patterns); ++j)
27043     {
27044       bool swapped;
27045 
27046       elt = patterns[j].perm[0];
27047       if (perm[0] == elt)
27048 	swapped = false;
27049       else if (perm[0] == elt + 16)
27050 	swapped = true;
27051       else
27052 	continue;
27053       for (i = 1; i < 16; ++i)
27054 	{
27055 	  elt = patterns[j].perm[i];
27056 	  if (swapped)
27057 	    elt = (elt >= 16 ? elt - 16 : elt + 16);
27058 	  else if (one_vec && elt >= 16)
27059 	    elt -= 16;
27060 	  if (perm[i] != elt)
27061 	    break;
27062 	}
27063       if (i == 16)
27064 	{
27065 	  enum insn_code icode = patterns[j].impl;
27066 	  enum machine_mode omode = insn_data[icode].operand[0].mode;
27067 	  enum machine_mode imode = insn_data[icode].operand[1].mode;
27068 
27069 	  if (swapped)
27070 	    x = op0, op0 = op1, op1 = x;
27071 	  if (imode != V16QImode)
27072 	    {
27073 	      op0 = gen_lowpart (imode, op0);
27074 	      op1 = gen_lowpart (imode, op1);
27075 	    }
27076 	  if (omode == V16QImode)
27077 	    x = target;
27078 	  else
27079 	    x = gen_reg_rtx (omode);
27080 	  emit_insn (GEN_FCN (icode) (x, op0, op1));
27081 	  if (omode != V16QImode)
27082 	    emit_move_insn (target, gen_lowpart (V16QImode, x));
27083 	  return true;
27084 	}
27085     }
27086 
27087   return false;
27088 }
27089 
27090 /* Expand a Paired Single, VSX Permute Doubleword, or SPE constant permutation.
27091    Return true if we match an efficient implementation.  */
27092 
27093 static bool
rs6000_expand_vec_perm_const_1(rtx target,rtx op0,rtx op1,unsigned char perm0,unsigned char perm1)27094 rs6000_expand_vec_perm_const_1 (rtx target, rtx op0, rtx op1,
27095 				unsigned char perm0, unsigned char perm1)
27096 {
27097   rtx x;
27098 
27099   /* If both selectors come from the same operand, fold to single op.  */
27100   if ((perm0 & 2) == (perm1 & 2))
27101     {
27102       if (perm0 & 2)
27103 	op0 = op1;
27104       else
27105 	op1 = op0;
27106     }
27107   /* If both operands are equal, fold to simpler permutation.  */
27108   if (rtx_equal_p (op0, op1))
27109     {
27110       perm0 = perm0 & 1;
27111       perm1 = (perm1 & 1) + 2;
27112     }
27113   /* If the first selector comes from the second operand, swap.  */
27114   else if (perm0 & 2)
27115     {
27116       if (perm1 & 2)
27117 	return false;
27118       perm0 -= 2;
27119       perm1 += 2;
27120       x = op0, op0 = op1, op1 = x;
27121     }
27122   /* If the second selector does not come from the second operand, fail.  */
27123   else if ((perm1 & 2) == 0)
27124     return false;
27125 
27126   /* Success! */
27127   if (target != NULL)
27128     {
27129       enum machine_mode vmode, dmode;
27130       rtvec v;
27131 
27132       vmode = GET_MODE (target);
27133       gcc_assert (GET_MODE_NUNITS (vmode) == 2);
27134       dmode = mode_for_vector (GET_MODE_INNER (vmode), 4);
27135 
27136       x = gen_rtx_VEC_CONCAT (dmode, op0, op1);
27137       v = gen_rtvec (2, GEN_INT (perm0), GEN_INT (perm1));
27138       x = gen_rtx_VEC_SELECT (vmode, x, gen_rtx_PARALLEL (VOIDmode, v));
27139       emit_insn (gen_rtx_SET (VOIDmode, target, x));
27140     }
27141   return true;
27142 }
27143 
27144 bool
rs6000_expand_vec_perm_const(rtx operands[4])27145 rs6000_expand_vec_perm_const (rtx operands[4])
27146 {
27147   rtx target, op0, op1, sel;
27148   unsigned char perm0, perm1;
27149 
27150   target = operands[0];
27151   op0 = operands[1];
27152   op1 = operands[2];
27153   sel = operands[3];
27154 
27155   /* Unpack the constant selector.  */
27156   perm0 = INTVAL (XVECEXP (sel, 0, 0)) & 3;
27157   perm1 = INTVAL (XVECEXP (sel, 0, 1)) & 3;
27158 
27159   return rs6000_expand_vec_perm_const_1 (target, op0, op1, perm0, perm1);
27160 }
27161 
27162 /* Test whether a constant permutation is supported.  */
27163 
27164 static bool
rs6000_vectorize_vec_perm_const_ok(enum machine_mode vmode,const unsigned char * sel)27165 rs6000_vectorize_vec_perm_const_ok (enum machine_mode vmode,
27166 				    const unsigned char *sel)
27167 {
27168   /* AltiVec (and thus VSX) can handle arbitrary permutations.  */
27169   if (TARGET_ALTIVEC)
27170     return true;
27171 
27172   /* Check for ps_merge* or evmerge* insns.  */
27173   if ((TARGET_PAIRED_FLOAT && vmode == V2SFmode)
27174       || (TARGET_SPE && vmode == V2SImode))
27175     {
27176       rtx op0 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 1);
27177       rtx op1 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 2);
27178       return rs6000_expand_vec_perm_const_1 (NULL, op0, op1, sel[0], sel[1]);
27179     }
27180 
27181   return false;
27182 }
27183 
27184 /* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave.  */
27185 
27186 static void
rs6000_do_expand_vec_perm(rtx target,rtx op0,rtx op1,enum machine_mode vmode,unsigned nelt,rtx perm[])27187 rs6000_do_expand_vec_perm (rtx target, rtx op0, rtx op1,
27188 			   enum machine_mode vmode, unsigned nelt, rtx perm[])
27189 {
27190   enum machine_mode imode;
27191   rtx x;
27192 
27193   imode = vmode;
27194   if (GET_MODE_CLASS (vmode) != MODE_VECTOR_INT)
27195     {
27196       imode = GET_MODE_INNER (vmode);
27197       imode = mode_for_size (GET_MODE_BITSIZE (imode), MODE_INT, 0);
27198       imode = mode_for_vector (imode, nelt);
27199     }
27200 
27201   x = gen_rtx_CONST_VECTOR (imode, gen_rtvec_v (nelt, perm));
27202   x = expand_vec_perm (vmode, op0, op1, x, target);
27203   if (x != target)
27204     emit_move_insn (target, x);
27205 }
27206 
27207 /* Expand an extract even operation.  */
27208 
27209 void
rs6000_expand_extract_even(rtx target,rtx op0,rtx op1)27210 rs6000_expand_extract_even (rtx target, rtx op0, rtx op1)
27211 {
27212   enum machine_mode vmode = GET_MODE (target);
27213   unsigned i, nelt = GET_MODE_NUNITS (vmode);
27214   rtx perm[16];
27215 
27216   for (i = 0; i < nelt; i++)
27217     perm[i] = GEN_INT (i * 2);
27218 
27219   rs6000_do_expand_vec_perm (target, op0, op1, vmode, nelt, perm);
27220 }
27221 
27222 /* Expand a vector interleave operation.  */
27223 
27224 void
rs6000_expand_interleave(rtx target,rtx op0,rtx op1,bool highp)27225 rs6000_expand_interleave (rtx target, rtx op0, rtx op1, bool highp)
27226 {
27227   enum machine_mode vmode = GET_MODE (target);
27228   unsigned i, high, nelt = GET_MODE_NUNITS (vmode);
27229   rtx perm[16];
27230 
27231   high = (highp == BYTES_BIG_ENDIAN ? 0 : nelt / 2);
27232   for (i = 0; i < nelt / 2; i++)
27233     {
27234       perm[i * 2] = GEN_INT (i + high);
27235       perm[i * 2 + 1] = GEN_INT (i + nelt + high);
27236     }
27237 
27238   rs6000_do_expand_vec_perm (target, op0, op1, vmode, nelt, perm);
27239 }
27240 
27241 /* Return an RTX representing where to find the function value of a
27242    function returning MODE.  */
27243 static rtx
rs6000_complex_function_value(enum machine_mode mode)27244 rs6000_complex_function_value (enum machine_mode mode)
27245 {
27246   unsigned int regno;
27247   rtx r1, r2;
27248   enum machine_mode inner = GET_MODE_INNER (mode);
27249   unsigned int inner_bytes = GET_MODE_SIZE (inner);
27250 
27251   if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
27252     regno = FP_ARG_RETURN;
27253   else
27254     {
27255       regno = GP_ARG_RETURN;
27256 
27257       /* 32-bit is OK since it'll go in r3/r4.  */
27258       if (TARGET_32BIT && inner_bytes >= 4)
27259 	return gen_rtx_REG (mode, regno);
27260     }
27261 
27262   if (inner_bytes >= 8)
27263     return gen_rtx_REG (mode, regno);
27264 
27265   r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
27266 			  const0_rtx);
27267   r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
27268 			  GEN_INT (inner_bytes));
27269   return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
27270 }
27271 
27272 /* Target hook for TARGET_FUNCTION_VALUE.
27273 
27274    On the SPE, both FPs and vectors are returned in r3.
27275 
27276    On RS/6000 an integer value is in r3 and a floating-point value is in
27277    fp1, unless -msoft-float.  */
27278 
27279 static rtx
rs6000_function_value(const_tree valtype,const_tree fn_decl_or_type ATTRIBUTE_UNUSED,bool outgoing ATTRIBUTE_UNUSED)27280 rs6000_function_value (const_tree valtype,
27281 		       const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
27282 		       bool outgoing ATTRIBUTE_UNUSED)
27283 {
27284   enum machine_mode mode;
27285   unsigned int regno;
27286 
27287   /* Special handling for structs in darwin64.  */
27288   if (TARGET_MACHO
27289       && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype), valtype))
27290     {
27291       CUMULATIVE_ARGS valcum;
27292       rtx valret;
27293 
27294       valcum.words = 0;
27295       valcum.fregno = FP_ARG_MIN_REG;
27296       valcum.vregno = ALTIVEC_ARG_MIN_REG;
27297       /* Do a trial code generation as if this were going to be passed as
27298 	 an argument; if any part goes in memory, we return NULL.  */
27299       valret = rs6000_darwin64_record_arg (&valcum, valtype, true, /* retval= */ true);
27300       if (valret)
27301 	return valret;
27302       /* Otherwise fall through to standard ABI rules.  */
27303     }
27304 
27305   if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
27306     {
27307       /* Long long return value need be split in -mpowerpc64, 32bit ABI.  */
27308       return gen_rtx_PARALLEL (DImode,
27309 	gen_rtvec (2,
27310 		   gen_rtx_EXPR_LIST (VOIDmode,
27311 				      gen_rtx_REG (SImode, GP_ARG_RETURN),
27312 				      const0_rtx),
27313 		   gen_rtx_EXPR_LIST (VOIDmode,
27314 				      gen_rtx_REG (SImode,
27315 						   GP_ARG_RETURN + 1),
27316 				      GEN_INT (4))));
27317     }
27318   if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DCmode)
27319     {
27320       return gen_rtx_PARALLEL (DCmode,
27321 	gen_rtvec (4,
27322 		   gen_rtx_EXPR_LIST (VOIDmode,
27323 				      gen_rtx_REG (SImode, GP_ARG_RETURN),
27324 				      const0_rtx),
27325 		   gen_rtx_EXPR_LIST (VOIDmode,
27326 				      gen_rtx_REG (SImode,
27327 						   GP_ARG_RETURN + 1),
27328 				      GEN_INT (4)),
27329 		   gen_rtx_EXPR_LIST (VOIDmode,
27330 				      gen_rtx_REG (SImode,
27331 						   GP_ARG_RETURN + 2),
27332 				      GEN_INT (8)),
27333 		   gen_rtx_EXPR_LIST (VOIDmode,
27334 				      gen_rtx_REG (SImode,
27335 						   GP_ARG_RETURN + 3),
27336 				      GEN_INT (12))));
27337     }
27338 
27339   mode = TYPE_MODE (valtype);
27340   if ((INTEGRAL_TYPE_P (valtype) && GET_MODE_BITSIZE (mode) < BITS_PER_WORD)
27341       || POINTER_TYPE_P (valtype))
27342     mode = TARGET_32BIT ? SImode : DImode;
27343 
27344   if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
27345     /* _Decimal128 must use an even/odd register pair.  */
27346     regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
27347   else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS
27348 	   && ((TARGET_SINGLE_FLOAT && (mode == SFmode)) || TARGET_DOUBLE_FLOAT))
27349     regno = FP_ARG_RETURN;
27350   else if (TREE_CODE (valtype) == COMPLEX_TYPE
27351 	   && targetm.calls.split_complex_arg)
27352     return rs6000_complex_function_value (mode);
27353   /* VSX is a superset of Altivec and adds V2DImode/V2DFmode.  Since the same
27354      return register is used in both cases, and we won't see V2DImode/V2DFmode
27355      for pure altivec, combine the two cases.  */
27356   else if (TREE_CODE (valtype) == VECTOR_TYPE
27357 	   && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
27358 	   && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
27359     regno = ALTIVEC_ARG_RETURN;
27360   else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
27361 	   && (mode == DFmode || mode == DCmode
27362 	       || mode == TFmode || mode == TCmode))
27363     return spe_build_register_parallel (mode, GP_ARG_RETURN);
27364   else
27365     regno = GP_ARG_RETURN;
27366 
27367   return gen_rtx_REG (mode, regno);
27368 }
27369 
27370 /* Define how to find the value returned by a library function
27371    assuming the value has mode MODE.  */
27372 rtx
rs6000_libcall_value(enum machine_mode mode)27373 rs6000_libcall_value (enum machine_mode mode)
27374 {
27375   unsigned int regno;
27376 
27377   if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
27378     {
27379       /* Long long return value need be split in -mpowerpc64, 32bit ABI.  */
27380       return gen_rtx_PARALLEL (DImode,
27381 	gen_rtvec (2,
27382 		   gen_rtx_EXPR_LIST (VOIDmode,
27383 				      gen_rtx_REG (SImode, GP_ARG_RETURN),
27384 				      const0_rtx),
27385 		   gen_rtx_EXPR_LIST (VOIDmode,
27386 				      gen_rtx_REG (SImode,
27387 						   GP_ARG_RETURN + 1),
27388 				      GEN_INT (4))));
27389     }
27390 
27391   if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
27392     /* _Decimal128 must use an even/odd register pair.  */
27393     regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
27394   else if (SCALAR_FLOAT_MODE_P (mode)
27395 	   && TARGET_HARD_FLOAT && TARGET_FPRS
27396            && ((TARGET_SINGLE_FLOAT && mode == SFmode) || TARGET_DOUBLE_FLOAT))
27397     regno = FP_ARG_RETURN;
27398   /* VSX is a superset of Altivec and adds V2DImode/V2DFmode.  Since the same
27399      return register is used in both cases, and we won't see V2DImode/V2DFmode
27400      for pure altivec, combine the two cases.  */
27401   else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
27402 	   && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
27403     regno = ALTIVEC_ARG_RETURN;
27404   else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
27405     return rs6000_complex_function_value (mode);
27406   else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
27407 	   && (mode == DFmode || mode == DCmode
27408 	       || mode == TFmode || mode == TCmode))
27409     return spe_build_register_parallel (mode, GP_ARG_RETURN);
27410   else
27411     regno = GP_ARG_RETURN;
27412 
27413   return gen_rtx_REG (mode, regno);
27414 }
27415 
27416 
27417 /* Given FROM and TO register numbers, say whether this elimination is allowed.
27418    Frame pointer elimination is automatically handled.
27419 
27420    For the RS/6000, if frame pointer elimination is being done, we would like
27421    to convert ap into fp, not sp.
27422 
27423    We need r30 if -mminimal-toc was specified, and there are constant pool
27424    references.  */
27425 
27426 static bool
rs6000_can_eliminate(const int from,const int to)27427 rs6000_can_eliminate (const int from, const int to)
27428 {
27429   return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM
27430           ? ! frame_pointer_needed
27431           : from == RS6000_PIC_OFFSET_TABLE_REGNUM
27432             ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0
27433             : true);
27434 }
27435 
27436 /* Define the offset between two registers, FROM to be eliminated and its
27437    replacement TO, at the start of a routine.  */
27438 HOST_WIDE_INT
rs6000_initial_elimination_offset(int from,int to)27439 rs6000_initial_elimination_offset (int from, int to)
27440 {
27441   rs6000_stack_t *info = rs6000_stack_info ();
27442   HOST_WIDE_INT offset;
27443 
27444   if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
27445     offset = info->push_p ? 0 : -info->total_size;
27446   else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
27447     {
27448       offset = info->push_p ? 0 : -info->total_size;
27449       if (FRAME_GROWS_DOWNWARD)
27450 	offset += info->fixed_size + info->vars_size + info->parm_size;
27451     }
27452   else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
27453     offset = FRAME_GROWS_DOWNWARD
27454 	     ? info->fixed_size + info->vars_size + info->parm_size
27455 	     : 0;
27456   else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
27457     offset = info->total_size;
27458   else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
27459     offset = info->push_p ? info->total_size : 0;
27460   else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
27461     offset = 0;
27462   else
27463     gcc_unreachable ();
27464 
27465   return offset;
27466 }
27467 
27468 static rtx
rs6000_dwarf_register_span(rtx reg)27469 rs6000_dwarf_register_span (rtx reg)
27470 {
27471   rtx parts[8];
27472   int i, words;
27473   unsigned regno = REGNO (reg);
27474   enum machine_mode mode = GET_MODE (reg);
27475 
27476   if (TARGET_SPE
27477       && regno < 32
27478       && (SPE_VECTOR_MODE (GET_MODE (reg))
27479 	  || (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode)
27480 	      && mode != SFmode && mode != SDmode && mode != SCmode)))
27481     ;
27482   else
27483     return NULL_RTX;
27484 
27485   regno = REGNO (reg);
27486 
27487   /* The duality of the SPE register size wreaks all kinds of havoc.
27488      This is a way of distinguishing r0 in 32-bits from r0 in
27489      64-bits.  */
27490   words = (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
27491   gcc_assert (words <= 4);
27492   for (i = 0; i < words; i++, regno++)
27493     {
27494       if (BYTES_BIG_ENDIAN)
27495 	{
27496 	  parts[2 * i] = gen_rtx_REG (SImode, regno + 1200);
27497 	  parts[2 * i + 1] = gen_rtx_REG (SImode, regno);
27498 	}
27499       else
27500 	{
27501 	  parts[2 * i] = gen_rtx_REG (SImode, regno);
27502 	  parts[2 * i + 1] = gen_rtx_REG (SImode, regno + 1200);
27503 	}
27504     }
27505 
27506   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (words * 2, parts));
27507 }
27508 
27509 /* Fill in sizes for SPE register high parts in table used by unwinder.  */
27510 
27511 static void
rs6000_init_dwarf_reg_sizes_extra(tree address)27512 rs6000_init_dwarf_reg_sizes_extra (tree address)
27513 {
27514   if (TARGET_SPE)
27515     {
27516       int i;
27517       enum machine_mode mode = TYPE_MODE (char_type_node);
27518       rtx addr = expand_expr (address, NULL_RTX, VOIDmode, EXPAND_NORMAL);
27519       rtx mem = gen_rtx_MEM (BLKmode, addr);
27520       rtx value = gen_int_mode (4, mode);
27521 
27522       for (i = 1201; i < 1232; i++)
27523 	{
27524 	  int column = DWARF_REG_TO_UNWIND_COLUMN (i);
27525 	  HOST_WIDE_INT offset
27526 	    = DWARF_FRAME_REGNUM (column) * GET_MODE_SIZE (mode);
27527 
27528 	  emit_move_insn (adjust_address (mem, mode, offset), value);
27529 	}
27530     }
27531 }
27532 
27533 /* Map internal gcc register numbers to DWARF2 register numbers.  */
27534 
27535 unsigned int
rs6000_dbx_register_number(unsigned int regno)27536 rs6000_dbx_register_number (unsigned int regno)
27537 {
27538   if (regno <= 63 || write_symbols != DWARF2_DEBUG)
27539     return regno;
27540   if (regno == LR_REGNO)
27541     return 108;
27542   if (regno == CTR_REGNO)
27543     return 109;
27544   if (CR_REGNO_P (regno))
27545     return regno - CR0_REGNO + 86;
27546   if (regno == CA_REGNO)
27547     return 101;  /* XER */
27548   if (ALTIVEC_REGNO_P (regno))
27549     return regno - FIRST_ALTIVEC_REGNO + 1124;
27550   if (regno == VRSAVE_REGNO)
27551     return 356;
27552   if (regno == VSCR_REGNO)
27553     return 67;
27554   if (regno == SPE_ACC_REGNO)
27555     return 99;
27556   if (regno == SPEFSCR_REGNO)
27557     return 612;
27558   /* SPE high reg number.  We get these values of regno from
27559      rs6000_dwarf_register_span.  */
27560   gcc_assert (regno >= 1200 && regno < 1232);
27561   return regno;
27562 }
27563 
27564 /* target hook eh_return_filter_mode */
27565 static enum machine_mode
rs6000_eh_return_filter_mode(void)27566 rs6000_eh_return_filter_mode (void)
27567 {
27568   return TARGET_32BIT ? SImode : word_mode;
27569 }
27570 
27571 /* Target hook for scalar_mode_supported_p.  */
27572 static bool
rs6000_scalar_mode_supported_p(enum machine_mode mode)27573 rs6000_scalar_mode_supported_p (enum machine_mode mode)
27574 {
27575   if (DECIMAL_FLOAT_MODE_P (mode))
27576     return default_decimal_float_supported_p ();
27577   else
27578     return default_scalar_mode_supported_p (mode);
27579 }
27580 
27581 /* Target hook for vector_mode_supported_p.  */
27582 static bool
rs6000_vector_mode_supported_p(enum machine_mode mode)27583 rs6000_vector_mode_supported_p (enum machine_mode mode)
27584 {
27585 
27586   if (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (mode))
27587     return true;
27588 
27589   if (TARGET_SPE && SPE_VECTOR_MODE (mode))
27590     return true;
27591 
27592   else if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
27593     return true;
27594 
27595   else
27596     return false;
27597 }
27598 
27599 /* Target hook for invalid_arg_for_unprototyped_fn. */
27600 static const char *
invalid_arg_for_unprototyped_fn(const_tree typelist,const_tree funcdecl,const_tree val)27601 invalid_arg_for_unprototyped_fn (const_tree typelist, const_tree funcdecl, const_tree val)
27602 {
27603   return (!rs6000_darwin64_abi
27604 	  && typelist == 0
27605           && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
27606           && (funcdecl == NULL_TREE
27607               || (TREE_CODE (funcdecl) == FUNCTION_DECL
27608                   && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
27609 	  ? N_("AltiVec argument passed to unprototyped function")
27610 	  : NULL;
27611 }
27612 
27613 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
27614    setup by using __stack_chk_fail_local hidden function instead of
27615    calling __stack_chk_fail directly.  Otherwise it is better to call
27616    __stack_chk_fail directly.  */
27617 
27618 static tree ATTRIBUTE_UNUSED
rs6000_stack_protect_fail(void)27619 rs6000_stack_protect_fail (void)
27620 {
27621   return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
27622 	 ? default_hidden_stack_protect_fail ()
27623 	 : default_external_stack_protect_fail ();
27624 }
27625 
27626 void
rs6000_final_prescan_insn(rtx insn,rtx * operand ATTRIBUTE_UNUSED,int num_operands ATTRIBUTE_UNUSED)27627 rs6000_final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED,
27628 			   int num_operands ATTRIBUTE_UNUSED)
27629 {
27630   if (rs6000_warn_cell_microcode)
27631     {
27632       const char *temp;
27633       int insn_code_number = recog_memoized (insn);
27634       location_t location = INSN_LOCATION (insn);
27635 
27636       /* Punt on insns we cannot recognize.  */
27637       if (insn_code_number < 0)
27638 	return;
27639 
27640       temp = get_insn_template (insn_code_number, insn);
27641 
27642       if (get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS)
27643 	warning_at (location, OPT_mwarn_cell_microcode,
27644 		    "emitting microcode insn %s\t[%s] #%d",
27645 		    temp, insn_data[INSN_CODE (insn)].name, INSN_UID (insn));
27646       else if (get_attr_cell_micro (insn) == CELL_MICRO_CONDITIONAL)
27647 	warning_at (location, OPT_mwarn_cell_microcode,
27648 		    "emitting conditional microcode insn %s\t[%s] #%d",
27649 		    temp, insn_data[INSN_CODE (insn)].name, INSN_UID (insn));
27650     }
27651 }
27652 
27653 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook.  */
27654 
27655 #if TARGET_ELF
27656 static unsigned HOST_WIDE_INT
rs6000_asan_shadow_offset(void)27657 rs6000_asan_shadow_offset (void)
27658 {
27659   return (unsigned HOST_WIDE_INT) 1 << (TARGET_64BIT ? 41 : 29);
27660 }
27661 #endif
27662 
27663 /* Mask options that we want to support inside of attribute((target)) and
27664    #pragma GCC target operations.  Note, we do not include things like
27665    64/32-bit, endianess, hard/soft floating point, etc. that would have
27666    different calling sequences.  */
27667 
27668 struct rs6000_opt_mask {
27669   const char *name;		/* option name */
27670   HOST_WIDE_INT mask;		/* mask to set */
27671   bool invert;			/* invert sense of mask */
27672   bool valid_target;		/* option is a target option */
27673 };
27674 
27675 static struct rs6000_opt_mask const rs6000_opt_masks[] =
27676 {
27677   { "altivec",			OPTION_MASK_ALTIVEC,		false, true  },
27678   { "cmpb",			OPTION_MASK_CMPB,		false, true  },
27679   { "dlmzb",			OPTION_MASK_DLMZB,		false, true  },
27680   { "fprnd",			OPTION_MASK_FPRND,		false, true  },
27681   { "hard-dfp",			OPTION_MASK_DFP,		false, true  },
27682   { "isel",			OPTION_MASK_ISEL,		false, true  },
27683   { "mfcrf",			OPTION_MASK_MFCRF,		false, true  },
27684   { "mfpgpr",			OPTION_MASK_MFPGPR,		false, true  },
27685   { "mulhw",			OPTION_MASK_MULHW,		false, true  },
27686   { "multiple",			OPTION_MASK_MULTIPLE,		false, true  },
27687   { "update",			OPTION_MASK_NO_UPDATE,		true , true  },
27688   { "popcntb",			OPTION_MASK_POPCNTB,		false, true  },
27689   { "popcntd",			OPTION_MASK_POPCNTD,		false, true  },
27690   { "powerpc-gfxopt",		OPTION_MASK_PPC_GFXOPT,		false, true  },
27691   { "powerpc-gpopt",		OPTION_MASK_PPC_GPOPT,		false, true  },
27692   { "recip-precision",		OPTION_MASK_RECIP_PRECISION,	false, true  },
27693   { "string",			OPTION_MASK_STRING,		false, true  },
27694   { "vsx",			OPTION_MASK_VSX,		false, true  },
27695 #ifdef OPTION_MASK_64BIT
27696 #if TARGET_AIX_OS
27697   { "aix64",			OPTION_MASK_64BIT,		false, false },
27698   { "aix32",			OPTION_MASK_64BIT,		true,  false },
27699 #else
27700   { "64",			OPTION_MASK_64BIT,		false, false },
27701   { "32",			OPTION_MASK_64BIT,		true,  false },
27702 #endif
27703 #endif
27704 #ifdef OPTION_MASK_EABI
27705   { "eabi",			OPTION_MASK_EABI,		false, false },
27706 #endif
27707 #ifdef OPTION_MASK_LITTLE_ENDIAN
27708   { "little",			OPTION_MASK_LITTLE_ENDIAN,	false, false },
27709   { "big",			OPTION_MASK_LITTLE_ENDIAN,	true,  false },
27710 #endif
27711 #ifdef OPTION_MASK_RELOCATABLE
27712   { "relocatable",		OPTION_MASK_RELOCATABLE,	false, false },
27713 #endif
27714 #ifdef OPTION_MASK_STRICT_ALIGN
27715   { "strict-align",		OPTION_MASK_STRICT_ALIGN,	false, false },
27716 #endif
27717   { "soft-float",		OPTION_MASK_SOFT_FLOAT,		false, false },
27718   { "string",			OPTION_MASK_STRING,		false, false },
27719 };
27720 
27721 /* Builtin mask mapping for printing the flags.  */
27722 static struct rs6000_opt_mask const rs6000_builtin_mask_names[] =
27723 {
27724   { "altivec",		 RS6000_BTM_ALTIVEC,	false, false },
27725   { "vsx",		 RS6000_BTM_VSX,	false, false },
27726   { "spe",		 RS6000_BTM_SPE,	false, false },
27727   { "paired",		 RS6000_BTM_PAIRED,	false, false },
27728   { "fre",		 RS6000_BTM_FRE,	false, false },
27729   { "fres",		 RS6000_BTM_FRES,	false, false },
27730   { "frsqrte",		 RS6000_BTM_FRSQRTE,	false, false },
27731   { "frsqrtes",		 RS6000_BTM_FRSQRTES,	false, false },
27732   { "popcntd",		 RS6000_BTM_POPCNTD,	false, false },
27733   { "cell",		 RS6000_BTM_CELL,	false, false },
27734 };
27735 
27736 /* Option variables that we want to support inside attribute((target)) and
27737    #pragma GCC target operations.  */
27738 
27739 struct rs6000_opt_var {
27740   const char *name;		/* option name */
27741   size_t global_offset;		/* offset of the option in global_options.  */
27742   size_t target_offset;		/* offset of the option in target optiosn.  */
27743 };
27744 
27745 static struct rs6000_opt_var const rs6000_opt_vars[] =
27746 {
27747   { "friz",
27748     offsetof (struct gcc_options, x_TARGET_FRIZ),
27749     offsetof (struct cl_target_option, x_TARGET_FRIZ), },
27750   { "avoid-indexed-addresses",
27751     offsetof (struct gcc_options, x_TARGET_AVOID_XFORM),
27752     offsetof (struct cl_target_option, x_TARGET_AVOID_XFORM) },
27753   { "paired",
27754     offsetof (struct gcc_options, x_rs6000_paired_float),
27755     offsetof (struct cl_target_option, x_rs6000_paired_float), },
27756   { "longcall",
27757     offsetof (struct gcc_options, x_rs6000_default_long_calls),
27758     offsetof (struct cl_target_option, x_rs6000_default_long_calls), },
27759 };
27760 
27761 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
27762    parsing.  Return true if there were no errors.  */
27763 
27764 static bool
rs6000_inner_target_options(tree args,bool attr_p)27765 rs6000_inner_target_options (tree args, bool attr_p)
27766 {
27767   bool ret = true;
27768 
27769   if (args == NULL_TREE)
27770     ;
27771 
27772   else if (TREE_CODE (args) == STRING_CST)
27773     {
27774       char *p = ASTRDUP (TREE_STRING_POINTER (args));
27775       char *q;
27776 
27777       while ((q = strtok (p, ",")) != NULL)
27778 	{
27779 	  bool error_p = false;
27780 	  bool not_valid_p = false;
27781 	  const char *cpu_opt = NULL;
27782 
27783 	  p = NULL;
27784 	  if (strncmp (q, "cpu=", 4) == 0)
27785 	    {
27786 	      int cpu_index = rs6000_cpu_name_lookup (q+4);
27787 	      if (cpu_index >= 0)
27788 		rs6000_cpu_index = cpu_index;
27789 	      else
27790 		{
27791 		  error_p = true;
27792 		  cpu_opt = q+4;
27793 		}
27794 	    }
27795 	  else if (strncmp (q, "tune=", 5) == 0)
27796 	    {
27797 	      int tune_index = rs6000_cpu_name_lookup (q+5);
27798 	      if (tune_index >= 0)
27799 		rs6000_tune_index = tune_index;
27800 	      else
27801 		{
27802 		  error_p = true;
27803 		  cpu_opt = q+5;
27804 		}
27805 	    }
27806 	  else
27807 	    {
27808 	      size_t i;
27809 	      bool invert = false;
27810 	      char *r = q;
27811 
27812 	      error_p = true;
27813 	      if (strncmp (r, "no-", 3) == 0)
27814 		{
27815 		  invert = true;
27816 		  r += 3;
27817 		}
27818 
27819 	      for (i = 0; i < ARRAY_SIZE (rs6000_opt_masks); i++)
27820 		if (strcmp (r, rs6000_opt_masks[i].name) == 0)
27821 		  {
27822 		    HOST_WIDE_INT mask = rs6000_opt_masks[i].mask;
27823 
27824 		    if (!rs6000_opt_masks[i].valid_target)
27825 		      not_valid_p = true;
27826 		    else
27827 		      {
27828 			error_p = false;
27829 			rs6000_isa_flags_explicit |= mask;
27830 
27831 			/* VSX needs altivec, so -mvsx automagically sets
27832 			   altivec.  */
27833 			if (mask == OPTION_MASK_VSX && !invert)
27834 			  mask |= OPTION_MASK_ALTIVEC;
27835 
27836 			if (rs6000_opt_masks[i].invert)
27837 			  invert = !invert;
27838 
27839 			if (invert)
27840 			  rs6000_isa_flags &= ~mask;
27841 			else
27842 			  rs6000_isa_flags |= mask;
27843 		      }
27844 		    break;
27845 		  }
27846 
27847 	      if (error_p && !not_valid_p)
27848 		{
27849 		  for (i = 0; i < ARRAY_SIZE (rs6000_opt_vars); i++)
27850 		    if (strcmp (r, rs6000_opt_vars[i].name) == 0)
27851 		      {
27852 			size_t j = rs6000_opt_vars[i].global_offset;
27853 			*((int *) ((char *)&global_options + j)) = !invert;
27854 			error_p = false;
27855 			break;
27856 		      }
27857 		}
27858 	    }
27859 
27860 	  if (error_p)
27861 	    {
27862 	      const char *eprefix, *esuffix;
27863 
27864 	      ret = false;
27865 	      if (attr_p)
27866 		{
27867 		  eprefix = "__attribute__((__target__(";
27868 		  esuffix = ")))";
27869 		}
27870 	      else
27871 		{
27872 		  eprefix = "#pragma GCC target ";
27873 		  esuffix = "";
27874 		}
27875 
27876 	      if (cpu_opt)
27877 		error ("invalid cpu \"%s\" for %s\"%s\"%s", cpu_opt, eprefix,
27878 		       q, esuffix);
27879 	      else if (not_valid_p)
27880 		error ("%s\"%s\"%s is not allowed", eprefix, q, esuffix);
27881 	      else
27882 		error ("%s\"%s\"%s is invalid", eprefix, q, esuffix);
27883 	    }
27884 	}
27885     }
27886 
27887   else if (TREE_CODE (args) == TREE_LIST)
27888     {
27889       do
27890 	{
27891 	  tree value = TREE_VALUE (args);
27892 	  if (value)
27893 	    {
27894 	      bool ret2 = rs6000_inner_target_options (value, attr_p);
27895 	      if (!ret2)
27896 		ret = false;
27897 	    }
27898 	  args = TREE_CHAIN (args);
27899 	}
27900       while (args != NULL_TREE);
27901     }
27902 
27903   else
27904     gcc_unreachable ();
27905 
27906   return ret;
27907 }
27908 
27909 /* Print out the target options as a list for -mdebug=target.  */
27910 
27911 static void
rs6000_debug_target_options(tree args,const char * prefix)27912 rs6000_debug_target_options (tree args, const char *prefix)
27913 {
27914   if (args == NULL_TREE)
27915     fprintf (stderr, "%s<NULL>", prefix);
27916 
27917   else if (TREE_CODE (args) == STRING_CST)
27918     {
27919       char *p = ASTRDUP (TREE_STRING_POINTER (args));
27920       char *q;
27921 
27922       while ((q = strtok (p, ",")) != NULL)
27923 	{
27924 	  p = NULL;
27925 	  fprintf (stderr, "%s\"%s\"", prefix, q);
27926 	  prefix = ", ";
27927 	}
27928     }
27929 
27930   else if (TREE_CODE (args) == TREE_LIST)
27931     {
27932       do
27933 	{
27934 	  tree value = TREE_VALUE (args);
27935 	  if (value)
27936 	    {
27937 	      rs6000_debug_target_options (value, prefix);
27938 	      prefix = ", ";
27939 	    }
27940 	  args = TREE_CHAIN (args);
27941 	}
27942       while (args != NULL_TREE);
27943     }
27944 
27945   else
27946     gcc_unreachable ();
27947 
27948   return;
27949 }
27950 
27951 
27952 /* Hook to validate attribute((target("..."))).  */
27953 
27954 static bool
rs6000_valid_attribute_p(tree fndecl,tree ARG_UNUSED (name),tree args,int flags)27955 rs6000_valid_attribute_p (tree fndecl,
27956 			  tree ARG_UNUSED (name),
27957 			  tree args,
27958 			  int flags)
27959 {
27960   struct cl_target_option cur_target;
27961   bool ret;
27962   tree old_optimize = build_optimization_node ();
27963   tree new_target, new_optimize;
27964   tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
27965 
27966   gcc_assert ((fndecl != NULL_TREE) && (args != NULL_TREE));
27967 
27968   if (TARGET_DEBUG_TARGET)
27969     {
27970       tree tname = DECL_NAME (fndecl);
27971       fprintf (stderr, "\n==================== rs6000_valid_attribute_p:\n");
27972       if (tname)
27973 	fprintf (stderr, "function: %.*s\n",
27974 		 (int) IDENTIFIER_LENGTH (tname),
27975 		 IDENTIFIER_POINTER (tname));
27976       else
27977 	fprintf (stderr, "function: unknown\n");
27978 
27979       fprintf (stderr, "args:");
27980       rs6000_debug_target_options (args, " ");
27981       fprintf (stderr, "\n");
27982 
27983       if (flags)
27984 	fprintf (stderr, "flags: 0x%x\n", flags);
27985 
27986       fprintf (stderr, "--------------------\n");
27987     }
27988 
27989   old_optimize = build_optimization_node ();
27990   func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
27991 
27992   /* If the function changed the optimization levels as well as setting target
27993      options, start with the optimizations specified.  */
27994   if (func_optimize && func_optimize != old_optimize)
27995     cl_optimization_restore (&global_options,
27996 			     TREE_OPTIMIZATION (func_optimize));
27997 
27998   /* The target attributes may also change some optimization flags, so update
27999      the optimization options if necessary.  */
28000   cl_target_option_save (&cur_target, &global_options);
28001   rs6000_cpu_index = rs6000_tune_index = -1;
28002   ret = rs6000_inner_target_options (args, true);
28003 
28004   /* Set up any additional state.  */
28005   if (ret)
28006     {
28007       ret = rs6000_option_override_internal (false);
28008       new_target = build_target_option_node ();
28009     }
28010   else
28011     new_target = NULL;
28012 
28013   new_optimize = build_optimization_node ();
28014 
28015   if (!new_target)
28016     ret = false;
28017 
28018   else if (fndecl)
28019     {
28020       DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
28021 
28022       if (old_optimize != new_optimize)
28023 	DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
28024     }
28025 
28026   cl_target_option_restore (&global_options, &cur_target);
28027 
28028   if (old_optimize != new_optimize)
28029     cl_optimization_restore (&global_options,
28030 			     TREE_OPTIMIZATION (old_optimize));
28031 
28032   return ret;
28033 }
28034 
28035 
28036 /* Hook to validate the current #pragma GCC target and set the state, and
28037    update the macros based on what was changed.  If ARGS is NULL, then
28038    POP_TARGET is used to reset the options.  */
28039 
28040 bool
rs6000_pragma_target_parse(tree args,tree pop_target)28041 rs6000_pragma_target_parse (tree args, tree pop_target)
28042 {
28043   tree prev_tree = build_target_option_node ();
28044   tree cur_tree;
28045   struct cl_target_option *prev_opt, *cur_opt;
28046   HOST_WIDE_INT prev_flags, cur_flags, diff_flags;
28047   HOST_WIDE_INT prev_bumask, cur_bumask, diff_bumask;
28048 
28049   if (TARGET_DEBUG_TARGET)
28050     {
28051       fprintf (stderr, "\n==================== rs6000_pragma_target_parse\n");
28052       fprintf (stderr, "args:");
28053       rs6000_debug_target_options (args, " ");
28054       fprintf (stderr, "\n");
28055 
28056       if (pop_target)
28057 	{
28058 	  fprintf (stderr, "pop_target:\n");
28059 	  debug_tree (pop_target);
28060 	}
28061       else
28062 	fprintf (stderr, "pop_target: <NULL>\n");
28063 
28064       fprintf (stderr, "--------------------\n");
28065     }
28066 
28067   if (! args)
28068     {
28069       cur_tree = ((pop_target)
28070 		  ? pop_target
28071 		  : target_option_default_node);
28072       cl_target_option_restore (&global_options,
28073 				TREE_TARGET_OPTION (cur_tree));
28074     }
28075   else
28076     {
28077       rs6000_cpu_index = rs6000_tune_index = -1;
28078       if (!rs6000_inner_target_options (args, false)
28079 	  || !rs6000_option_override_internal (false)
28080 	  || (cur_tree = build_target_option_node ()) == NULL_TREE)
28081 	{
28082 	  if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
28083 	    fprintf (stderr, "invalid pragma\n");
28084 
28085 	  return false;
28086 	}
28087     }
28088 
28089   target_option_current_node = cur_tree;
28090 
28091   /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
28092      change the macros that are defined.  */
28093   if (rs6000_target_modify_macros_ptr)
28094     {
28095       prev_opt    = TREE_TARGET_OPTION (prev_tree);
28096       prev_bumask = prev_opt->x_rs6000_builtin_mask;
28097       prev_flags  = prev_opt->x_rs6000_isa_flags;
28098 
28099       cur_opt     = TREE_TARGET_OPTION (cur_tree);
28100       cur_flags   = cur_opt->x_rs6000_isa_flags;
28101       cur_bumask  = cur_opt->x_rs6000_builtin_mask;
28102 
28103       diff_bumask = (prev_bumask ^ cur_bumask);
28104       diff_flags  = (prev_flags ^ cur_flags);
28105 
28106       if ((diff_flags != 0) || (diff_bumask != 0))
28107 	{
28108 	  /* Delete old macros.  */
28109 	  rs6000_target_modify_macros_ptr (false,
28110 					   prev_flags & diff_flags,
28111 					   prev_bumask & diff_bumask);
28112 
28113 	  /* Define new macros.  */
28114 	  rs6000_target_modify_macros_ptr (true,
28115 					   cur_flags & diff_flags,
28116 					   cur_bumask & diff_bumask);
28117 	}
28118     }
28119 
28120   return true;
28121 }
28122 
28123 
28124 /* Remember the last target of rs6000_set_current_function.  */
28125 static GTY(()) tree rs6000_previous_fndecl;
28126 
28127 /* Establish appropriate back-end context for processing the function
28128    FNDECL.  The argument might be NULL to indicate processing at top
28129    level, outside of any function scope.  */
28130 static void
rs6000_set_current_function(tree fndecl)28131 rs6000_set_current_function (tree fndecl)
28132 {
28133   tree old_tree = (rs6000_previous_fndecl
28134 		   ? DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl)
28135 		   : NULL_TREE);
28136 
28137   tree new_tree = (fndecl
28138 		   ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl)
28139 		   : NULL_TREE);
28140 
28141   if (TARGET_DEBUG_TARGET)
28142     {
28143       bool print_final = false;
28144       fprintf (stderr, "\n==================== rs6000_set_current_function");
28145 
28146       if (fndecl)
28147 	fprintf (stderr, ", fndecl %s (%p)",
28148 		 (DECL_NAME (fndecl)
28149 		  ? IDENTIFIER_POINTER (DECL_NAME (fndecl))
28150 		  : "<unknown>"), (void *)fndecl);
28151 
28152       if (rs6000_previous_fndecl)
28153 	fprintf (stderr, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl);
28154 
28155       fprintf (stderr, "\n");
28156       if (new_tree)
28157 	{
28158 	  fprintf (stderr, "\nnew fndecl target specific options:\n");
28159 	  debug_tree (new_tree);
28160 	  print_final = true;
28161 	}
28162 
28163       if (old_tree)
28164 	{
28165 	  fprintf (stderr, "\nold fndecl target specific options:\n");
28166 	  debug_tree (old_tree);
28167 	  print_final = true;
28168 	}
28169 
28170       if (print_final)
28171 	fprintf (stderr, "--------------------\n");
28172     }
28173 
28174   /* Only change the context if the function changes.  This hook is called
28175      several times in the course of compiling a function, and we don't want to
28176      slow things down too much or call target_reinit when it isn't safe.  */
28177   if (fndecl && fndecl != rs6000_previous_fndecl)
28178     {
28179       rs6000_previous_fndecl = fndecl;
28180       if (old_tree == new_tree)
28181 	;
28182 
28183       else if (new_tree)
28184 	{
28185 	  cl_target_option_restore (&global_options,
28186 				    TREE_TARGET_OPTION (new_tree));
28187 	  target_reinit ();
28188 	}
28189 
28190       else if (old_tree)
28191 	{
28192 	  struct cl_target_option *def
28193 	    = TREE_TARGET_OPTION (target_option_current_node);
28194 
28195 	  cl_target_option_restore (&global_options, def);
28196 	  target_reinit ();
28197 	}
28198     }
28199 }
28200 
28201 
28202 /* Save the current options */
28203 
28204 static void
rs6000_function_specific_save(struct cl_target_option * ptr)28205 rs6000_function_specific_save (struct cl_target_option *ptr)
28206 {
28207   ptr->x_rs6000_isa_flags = rs6000_isa_flags;
28208   ptr->x_rs6000_isa_flags_explicit = rs6000_isa_flags_explicit;
28209 }
28210 
28211 /* Restore the current options */
28212 
28213 static void
rs6000_function_specific_restore(struct cl_target_option * ptr)28214 rs6000_function_specific_restore (struct cl_target_option *ptr)
28215 {
28216   rs6000_isa_flags = ptr->x_rs6000_isa_flags;
28217   rs6000_isa_flags_explicit = ptr->x_rs6000_isa_flags_explicit;
28218   (void) rs6000_option_override_internal (false);
28219 }
28220 
28221 /* Print the current options */
28222 
28223 static void
rs6000_function_specific_print(FILE * file,int indent,struct cl_target_option * ptr)28224 rs6000_function_specific_print (FILE *file, int indent,
28225 				struct cl_target_option *ptr)
28226 {
28227   rs6000_print_isa_options (file, indent, "Isa options set",
28228 			    ptr->x_rs6000_isa_flags);
28229 
28230   rs6000_print_isa_options (file, indent, "Isa options explicit",
28231 			    ptr->x_rs6000_isa_flags_explicit);
28232 }
28233 
28234 /* Helper function to print the current isa or misc options on a line.  */
28235 
28236 static void
rs6000_print_options_internal(FILE * file,int indent,const char * string,HOST_WIDE_INT flags,const char * prefix,const struct rs6000_opt_mask * opts,size_t num_elements)28237 rs6000_print_options_internal (FILE *file,
28238 			       int indent,
28239 			       const char *string,
28240 			       HOST_WIDE_INT flags,
28241 			       const char *prefix,
28242 			       const struct rs6000_opt_mask *opts,
28243 			       size_t num_elements)
28244 {
28245   size_t i;
28246   size_t start_column = 0;
28247   size_t cur_column;
28248   size_t max_column = 76;
28249   const char *comma = "";
28250   const char *nl = "\n";
28251 
28252   if (indent)
28253     start_column += fprintf (file, "%*s", indent, "");
28254 
28255   if (!flags)
28256     {
28257       fprintf (stderr, DEBUG_FMT_S, string, "<none>");
28258       return;
28259     }
28260 
28261   start_column += fprintf (stderr, DEBUG_FMT_WX, string, flags);
28262 
28263   /* Print the various mask options.  */
28264   cur_column = start_column;
28265   for (i = 0; i < num_elements; i++)
28266     {
28267       if ((flags & opts[i].mask) != 0)
28268 	{
28269 	  const char *no_str = rs6000_opt_masks[i].invert ? "no-" : "";
28270 	  size_t len = (strlen (comma)
28271 			+ strlen (prefix)
28272 			+ strlen (no_str)
28273 			+ strlen (rs6000_opt_masks[i].name));
28274 
28275 	  cur_column += len;
28276 	  if (cur_column > max_column)
28277 	    {
28278 	      fprintf (stderr, ", \\\n%*s", (int)start_column, "");
28279 	      cur_column = start_column + len;
28280 	      comma = "";
28281 	      nl = "\n\n";
28282 	    }
28283 
28284 	  fprintf (file, "%s%s%s%s", comma, prefix, no_str,
28285 		   rs6000_opt_masks[i].name);
28286 	  flags &= ~ opts[i].mask;
28287 	  comma = ", ";
28288 	}
28289     }
28290 
28291   fputs (nl, file);
28292 }
28293 
28294 /* Helper function to print the current isa options on a line.  */
28295 
28296 static void
rs6000_print_isa_options(FILE * file,int indent,const char * string,HOST_WIDE_INT flags)28297 rs6000_print_isa_options (FILE *file, int indent, const char *string,
28298 			  HOST_WIDE_INT flags)
28299 {
28300   rs6000_print_options_internal (file, indent, string, flags, "-m",
28301 				 &rs6000_opt_masks[0],
28302 				 ARRAY_SIZE (rs6000_opt_masks));
28303 }
28304 
28305 static void
rs6000_print_builtin_options(FILE * file,int indent,const char * string,HOST_WIDE_INT flags)28306 rs6000_print_builtin_options (FILE *file, int indent, const char *string,
28307 			      HOST_WIDE_INT flags)
28308 {
28309   rs6000_print_options_internal (file, indent, string, flags, "",
28310 				 &rs6000_builtin_mask_names[0],
28311 				 ARRAY_SIZE (rs6000_builtin_mask_names));
28312 }
28313 
28314 
28315 /* Hook to determine if one function can safely inline another.  */
28316 
28317 static bool
rs6000_can_inline_p(tree caller,tree callee)28318 rs6000_can_inline_p (tree caller, tree callee)
28319 {
28320   bool ret = false;
28321   tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
28322   tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
28323 
28324   /* If callee has no option attributes, then it is ok to inline.  */
28325   if (!callee_tree)
28326     ret = true;
28327 
28328   /* If caller has no option attributes, but callee does then it is not ok to
28329      inline.  */
28330   else if (!caller_tree)
28331     ret = false;
28332 
28333   else
28334     {
28335       struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
28336       struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
28337 
28338       /* Callee's options should a subset of the caller's, i.e. a vsx function
28339 	 can inline an altivec function but a non-vsx function can't inline a
28340 	 vsx function.  */
28341       if ((caller_opts->x_rs6000_isa_flags & callee_opts->x_rs6000_isa_flags)
28342 	  == callee_opts->x_rs6000_isa_flags)
28343 	ret = true;
28344     }
28345 
28346   if (TARGET_DEBUG_TARGET)
28347     fprintf (stderr, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
28348 	     (DECL_NAME (caller)
28349 	      ? IDENTIFIER_POINTER (DECL_NAME (caller))
28350 	      : "<unknown>"),
28351 	     (DECL_NAME (callee)
28352 	      ? IDENTIFIER_POINTER (DECL_NAME (callee))
28353 	      : "<unknown>"),
28354 	     (ret ? "can" : "cannot"));
28355 
28356   return ret;
28357 }
28358 
28359 /* Allocate a stack temp and fixup the address so it meets the particular
28360    memory requirements (either offetable or REG+REG addressing).  */
28361 
28362 rtx
rs6000_allocate_stack_temp(enum machine_mode mode,bool offsettable_p,bool reg_reg_p)28363 rs6000_allocate_stack_temp (enum machine_mode mode,
28364 			    bool offsettable_p,
28365 			    bool reg_reg_p)
28366 {
28367   rtx stack = assign_stack_temp (mode, GET_MODE_SIZE (mode));
28368   rtx addr = XEXP (stack, 0);
28369   int strict_p = (reload_in_progress || reload_completed);
28370 
28371   if (!legitimate_indirect_address_p (addr, strict_p))
28372     {
28373       if (offsettable_p
28374 	  && !rs6000_legitimate_offset_address_p (mode, addr, strict_p, true))
28375 	stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
28376 
28377       else if (reg_reg_p && !legitimate_indexed_address_p (addr, strict_p))
28378 	stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
28379     }
28380 
28381   return stack;
28382 }
28383 
28384 /* Given a memory reference, if it is not a reg or reg+reg addressing, convert
28385    to such a form to deal with memory reference instructions like STFIWX that
28386    only take reg+reg addressing.  */
28387 
28388 rtx
rs6000_address_for_fpconvert(rtx x)28389 rs6000_address_for_fpconvert (rtx x)
28390 {
28391   int strict_p = (reload_in_progress || reload_completed);
28392   rtx addr;
28393 
28394   gcc_assert (MEM_P (x));
28395   addr = XEXP (x, 0);
28396   if (! legitimate_indirect_address_p (addr, strict_p)
28397       && ! legitimate_indexed_address_p (addr, strict_p))
28398     {
28399       if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
28400 	{
28401 	  rtx reg = XEXP (addr, 0);
28402 	  HOST_WIDE_INT size = GET_MODE_SIZE (GET_MODE (x));
28403 	  rtx size_rtx = GEN_INT ((GET_CODE (addr) == PRE_DEC) ? -size : size);
28404 	  gcc_assert (REG_P (reg));
28405 	  emit_insn (gen_add3_insn (reg, reg, size_rtx));
28406 	  addr = reg;
28407 	}
28408       else if (GET_CODE (addr) == PRE_MODIFY)
28409 	{
28410 	  rtx reg = XEXP (addr, 0);
28411 	  rtx expr = XEXP (addr, 1);
28412 	  gcc_assert (REG_P (reg));
28413 	  gcc_assert (GET_CODE (expr) == PLUS);
28414 	  emit_insn (gen_add3_insn (reg, XEXP (expr, 0), XEXP (expr, 1)));
28415 	  addr = reg;
28416 	}
28417 
28418       x = replace_equiv_address (x, copy_addr_to_reg (addr));
28419     }
28420 
28421   return x;
28422 }
28423 
28424 /* Given a memory reference, if it is not in the form for altivec memory
28425    reference instructions (i.e. reg or reg+reg addressing with AND of -16),
28426    convert to the altivec format.  */
28427 
28428 rtx
rs6000_address_for_altivec(rtx x)28429 rs6000_address_for_altivec (rtx x)
28430 {
28431   gcc_assert (MEM_P (x));
28432   if (!altivec_indexed_or_indirect_operand (x, GET_MODE (x)))
28433     {
28434       rtx addr = XEXP (x, 0);
28435       int strict_p = (reload_in_progress || reload_completed);
28436 
28437       if (!legitimate_indexed_address_p (addr, strict_p)
28438 	  && !legitimate_indirect_address_p (addr, strict_p))
28439 	addr = copy_to_mode_reg (Pmode, addr);
28440 
28441       addr = gen_rtx_AND (Pmode, addr, GEN_INT (-16));
28442       x = change_address (x, GET_MODE (x), addr);
28443     }
28444 
28445   return x;
28446 }
28447 
28448 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
28449 
28450    On the RS/6000, all integer constants are acceptable, most won't be valid
28451    for particular insns, though.  Only easy FP constants are acceptable.  */
28452 
28453 static bool
rs6000_legitimate_constant_p(enum machine_mode mode,rtx x)28454 rs6000_legitimate_constant_p (enum machine_mode mode, rtx x)
28455 {
28456   if (TARGET_ELF && rs6000_tls_referenced_p (x))
28457     return false;
28458 
28459   return ((GET_CODE (x) != CONST_DOUBLE && GET_CODE (x) != CONST_VECTOR)
28460 	  || GET_MODE (x) == VOIDmode
28461 	  || (TARGET_POWERPC64 && mode == DImode)
28462 	  || easy_fp_constant (x, mode)
28463 	  || easy_vector_constant (x, mode));
28464 }
28465 
28466 
28467 /* A function pointer under AIX is a pointer to a data area whose first word
28468    contains the actual address of the function, whose second word contains a
28469    pointer to its TOC, and whose third word contains a value to place in the
28470    static chain register (r11).  Note that if we load the static chain, our
28471    "trampoline" need not have any executable code.  */
28472 
28473 void
rs6000_call_indirect_aix(rtx value,rtx func_desc,rtx flag)28474 rs6000_call_indirect_aix (rtx value, rtx func_desc, rtx flag)
28475 {
28476   rtx func_addr;
28477   rtx toc_reg;
28478   rtx sc_reg;
28479   rtx stack_ptr;
28480   rtx stack_toc_offset;
28481   rtx stack_toc_mem;
28482   rtx func_toc_offset;
28483   rtx func_toc_mem;
28484   rtx func_sc_offset;
28485   rtx func_sc_mem;
28486   rtx insn;
28487   rtx (*call_func) (rtx, rtx, rtx, rtx);
28488   rtx (*call_value_func) (rtx, rtx, rtx, rtx, rtx);
28489 
28490   stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
28491   toc_reg = gen_rtx_REG (Pmode, TOC_REGNUM);
28492 
28493   /* Load up address of the actual function.  */
28494   func_desc = force_reg (Pmode, func_desc);
28495   func_addr = gen_reg_rtx (Pmode);
28496   emit_move_insn (func_addr, gen_rtx_MEM (Pmode, func_desc));
28497 
28498   if (TARGET_32BIT)
28499     {
28500 
28501       stack_toc_offset = GEN_INT (TOC_SAVE_OFFSET_32BIT);
28502       func_toc_offset = GEN_INT (AIX_FUNC_DESC_TOC_32BIT);
28503       func_sc_offset = GEN_INT (AIX_FUNC_DESC_SC_32BIT);
28504       if (TARGET_POINTERS_TO_NESTED_FUNCTIONS)
28505 	{
28506 	  call_func = gen_call_indirect_aix32bit;
28507 	  call_value_func = gen_call_value_indirect_aix32bit;
28508 	}
28509       else
28510 	{
28511 	  call_func = gen_call_indirect_aix32bit_nor11;
28512 	  call_value_func = gen_call_value_indirect_aix32bit_nor11;
28513 	}
28514     }
28515   else
28516     {
28517       stack_toc_offset = GEN_INT (TOC_SAVE_OFFSET_64BIT);
28518       func_toc_offset = GEN_INT (AIX_FUNC_DESC_TOC_64BIT);
28519       func_sc_offset = GEN_INT (AIX_FUNC_DESC_SC_64BIT);
28520       if (TARGET_POINTERS_TO_NESTED_FUNCTIONS)
28521 	{
28522 	  call_func = gen_call_indirect_aix64bit;
28523 	  call_value_func = gen_call_value_indirect_aix64bit;
28524 	}
28525       else
28526 	{
28527 	  call_func = gen_call_indirect_aix64bit_nor11;
28528 	  call_value_func = gen_call_value_indirect_aix64bit_nor11;
28529 	}
28530     }
28531 
28532   /* Reserved spot to store the TOC.  */
28533   stack_toc_mem = gen_frame_mem (Pmode,
28534 				 gen_rtx_PLUS (Pmode,
28535 					       stack_ptr,
28536 					       stack_toc_offset));
28537 
28538   gcc_assert (cfun);
28539   gcc_assert (cfun->machine);
28540 
28541   /* Can we optimize saving the TOC in the prologue or do we need to do it at
28542      every call?  */
28543   if (TARGET_SAVE_TOC_INDIRECT && !cfun->calls_alloca)
28544     cfun->machine->save_toc_in_prologue = true;
28545 
28546   else
28547     {
28548       MEM_VOLATILE_P (stack_toc_mem) = 1;
28549       emit_move_insn (stack_toc_mem, toc_reg);
28550     }
28551 
28552   /* Calculate the address to load the TOC of the called function.  We don't
28553      actually load this until the split after reload.  */
28554   func_toc_mem = gen_rtx_MEM (Pmode,
28555 			      gen_rtx_PLUS (Pmode,
28556 					    func_desc,
28557 					    func_toc_offset));
28558 
28559   /* If we have a static chain, load it up.  */
28560   if (TARGET_POINTERS_TO_NESTED_FUNCTIONS)
28561     {
28562       func_sc_mem = gen_rtx_MEM (Pmode,
28563 				 gen_rtx_PLUS (Pmode,
28564 					       func_desc,
28565 					       func_sc_offset));
28566 
28567       sc_reg = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
28568       emit_move_insn (sc_reg, func_sc_mem);
28569     }
28570 
28571   /* Create the call.  */
28572   if (value)
28573     insn = call_value_func (value, func_addr, flag, func_toc_mem,
28574 			    stack_toc_mem);
28575   else
28576     insn = call_func (func_addr, flag, func_toc_mem, stack_toc_mem);
28577 
28578   emit_call_insn (insn);
28579 }
28580 
28581 /* Return whether we need to always update the saved TOC pointer when we update
28582    the stack pointer.  */
28583 
28584 static bool
rs6000_save_toc_in_prologue_p(void)28585 rs6000_save_toc_in_prologue_p (void)
28586 {
28587   return (cfun && cfun->machine && cfun->machine->save_toc_in_prologue);
28588 }
28589 
28590 #ifdef HAVE_GAS_HIDDEN
28591 # define USE_HIDDEN_LINKONCE 1
28592 #else
28593 # define USE_HIDDEN_LINKONCE 0
28594 #endif
28595 
28596 /* Fills in the label name that should be used for a 476 link stack thunk.  */
28597 
28598 void
get_ppc476_thunk_name(char name[32])28599 get_ppc476_thunk_name (char name[32])
28600 {
28601   gcc_assert (TARGET_LINK_STACK);
28602 
28603   if (USE_HIDDEN_LINKONCE)
28604     sprintf (name, "__ppc476.get_thunk");
28605   else
28606     ASM_GENERATE_INTERNAL_LABEL (name, "LPPC476_", 0);
28607 }
28608 
28609 /* This function emits the simple thunk routine that is used to preserve
28610    the link stack on the 476 cpu.  */
28611 
28612 static void rs6000_code_end (void) ATTRIBUTE_UNUSED;
28613 static void
rs6000_code_end(void)28614 rs6000_code_end (void)
28615 {
28616   char name[32];
28617   tree decl;
28618 
28619   if (!TARGET_LINK_STACK)
28620     return;
28621 
28622   get_ppc476_thunk_name (name);
28623 
28624   decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL, get_identifier (name),
28625 		     build_function_type_list (void_type_node, NULL_TREE));
28626   DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
28627 				   NULL_TREE, void_type_node);
28628   TREE_PUBLIC (decl) = 1;
28629   TREE_STATIC (decl) = 1;
28630 
28631 #if RS6000_WEAK
28632   if (USE_HIDDEN_LINKONCE)
28633     {
28634       DECL_COMDAT_GROUP (decl) = DECL_ASSEMBLER_NAME (decl);
28635       targetm.asm_out.unique_section (decl, 0);
28636       switch_to_section (get_named_section (decl, NULL, 0));
28637       DECL_WEAK (decl) = 1;
28638       ASM_WEAKEN_DECL (asm_out_file, decl, name, 0);
28639       targetm.asm_out.globalize_label (asm_out_file, name);
28640       targetm.asm_out.assemble_visibility (decl, VISIBILITY_HIDDEN);
28641       ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
28642     }
28643   else
28644 #endif
28645     {
28646       switch_to_section (text_section);
28647       ASM_OUTPUT_LABEL (asm_out_file, name);
28648     }
28649 
28650   DECL_INITIAL (decl) = make_node (BLOCK);
28651   current_function_decl = decl;
28652   init_function_start (decl);
28653   first_function_block_is_cold = false;
28654   /* Make sure unwind info is emitted for the thunk if needed.  */
28655   final_start_function (emit_barrier (), asm_out_file, 1);
28656 
28657   fputs ("\tblr\n", asm_out_file);
28658 
28659   final_end_function ();
28660   init_insn_lengths ();
28661   free_after_compilation (cfun);
28662   set_cfun (NULL);
28663   current_function_decl = NULL;
28664 }
28665 
28666 /* Add r30 to hard reg set if the prologue sets it up and it is not
28667    pic_offset_table_rtx.  */
28668 
28669 static void
rs6000_set_up_by_prologue(struct hard_reg_set_container * set)28670 rs6000_set_up_by_prologue (struct hard_reg_set_container *set)
28671 {
28672   if (!TARGET_SINGLE_PIC_BASE
28673       && TARGET_TOC
28674       && TARGET_MINIMAL_TOC
28675       && get_pool_size () != 0)
28676     add_to_hard_reg_set (&set->set, Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
28677 }
28678 
28679 struct gcc_target targetm = TARGET_INITIALIZER;
28680 
28681 #include "gt-rs6000.h"
28682