1 /* Definitions of target machine for GNU compiler, for IBM S/390 2 Copyright (C) 1999-2013 Free Software Foundation, Inc. 3 Contributed by Hartmut Penner (hpenner@de.ibm.com) and 4 Ulrich Weigand (uweigand@de.ibm.com). 5 Andreas Krebbel (Andreas.Krebbel@de.ibm.com) 6 7 This file is part of GCC. 8 9 GCC is free software; you can redistribute it and/or modify it under 10 the terms of the GNU General Public License as published by the Free 11 Software Foundation; either version 3, or (at your option) any later 12 version. 13 14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY 15 WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with GCC; see the file COPYING3. If not see 21 <http://www.gnu.org/licenses/>. */ 22 23 #ifndef _S390_H 24 #define _S390_H 25 26 /* Optional architectural facilities supported by the processor. */ 27 28 enum processor_flags 29 { 30 PF_IEEE_FLOAT = 1, 31 PF_ZARCH = 2, 32 PF_LONG_DISPLACEMENT = 4, 33 PF_EXTIMM = 8, 34 PF_DFP = 16, 35 PF_Z10 = 32, 36 PF_Z196 = 64, 37 PF_ZEC12 = 128 38 }; 39 40 /* This is necessary to avoid a warning about comparing different enum 41 types. */ 42 #define s390_tune_attr ((enum attr_cpu)s390_tune) 43 44 /* These flags indicate that the generated code should run on a cpu 45 providing the respective hardware facility regardless of the 46 current cpu mode (ESA or z/Architecture). */ 47 48 #define TARGET_CPU_IEEE_FLOAT \ 49 (s390_arch_flags & PF_IEEE_FLOAT) 50 #define TARGET_CPU_ZARCH \ 51 (s390_arch_flags & PF_ZARCH) 52 #define TARGET_CPU_LONG_DISPLACEMENT \ 53 (s390_arch_flags & PF_LONG_DISPLACEMENT) 54 #define TARGET_CPU_EXTIMM \ 55 (s390_arch_flags & PF_EXTIMM) 56 #define TARGET_CPU_DFP \ 57 (s390_arch_flags & PF_DFP) 58 #define TARGET_CPU_Z10 \ 59 (s390_arch_flags & PF_Z10) 60 #define TARGET_CPU_Z196 \ 61 (s390_arch_flags & PF_Z196) 62 #define TARGET_CPU_ZEC12 \ 63 (s390_arch_flags & PF_ZEC12) 64 65 /* These flags indicate that the generated code should run on a cpu 66 providing the respective hardware facility when run in 67 z/Architecture mode. */ 68 69 #define TARGET_LONG_DISPLACEMENT \ 70 (TARGET_ZARCH && TARGET_CPU_LONG_DISPLACEMENT) 71 #define TARGET_EXTIMM \ 72 (TARGET_ZARCH && TARGET_CPU_EXTIMM) 73 #define TARGET_DFP \ 74 (TARGET_ZARCH && TARGET_CPU_DFP && TARGET_HARD_FLOAT) 75 #define TARGET_Z10 \ 76 (TARGET_ZARCH && TARGET_CPU_Z10) 77 #define TARGET_Z196 \ 78 (TARGET_ZARCH && TARGET_CPU_Z196) 79 #define TARGET_ZEC12 \ 80 (TARGET_ZARCH && TARGET_CPU_ZEC12) 81 82 83 #define TARGET_AVOID_CMP_AND_BRANCH (s390_tune == PROCESSOR_2817_Z196) 84 85 /* Run-time target specification. */ 86 87 /* Defaults for option flags defined only on some subtargets. */ 88 #ifndef TARGET_TPF_PROFILING 89 #define TARGET_TPF_PROFILING 0 90 #endif 91 92 /* This will be overridden by OS headers. */ 93 #define TARGET_TPF 0 94 95 /* Target CPU builtins. */ 96 #define TARGET_CPU_CPP_BUILTINS() \ 97 do \ 98 { \ 99 builtin_assert ("cpu=s390"); \ 100 builtin_assert ("machine=s390"); \ 101 builtin_define ("__s390__"); \ 102 if (TARGET_ZARCH) \ 103 builtin_define ("__zarch__"); \ 104 if (TARGET_64BIT) \ 105 builtin_define ("__s390x__"); \ 106 if (TARGET_LONG_DOUBLE_128) \ 107 builtin_define ("__LONG_DOUBLE_128__"); \ 108 } \ 109 while (0) 110 111 #ifdef DEFAULT_TARGET_64BIT 112 #define TARGET_DEFAULT (MASK_64BIT | MASK_ZARCH | MASK_HARD_DFP) 113 #else 114 #define TARGET_DEFAULT 0 115 #endif 116 117 /* Support for configure-time defaults. */ 118 #define OPTION_DEFAULT_SPECS \ 119 { "mode", "%{!mesa:%{!mzarch:-m%(VALUE)}}" }, \ 120 { "arch", "%{!march=*:-march=%(VALUE)}" }, \ 121 { "tune", "%{!mtune=*:-mtune=%(VALUE)}" } 122 123 /* Defaulting rules. */ 124 #ifdef DEFAULT_TARGET_64BIT 125 #define DRIVER_SELF_SPECS \ 126 "%{!m31:%{!m64:-m64}}", \ 127 "%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}", \ 128 "%{!march=*:%{mesa:-march=g5}%{mzarch:-march=z900}}" 129 #else 130 #define DRIVER_SELF_SPECS \ 131 "%{!m31:%{!m64:-m31}}", \ 132 "%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}", \ 133 "%{!march=*:%{mesa:-march=g5}%{mzarch:-march=z900}}" 134 #endif 135 136 /* Constants needed to control the TEST DATA CLASS (TDC) instruction. */ 137 #define S390_TDC_POSITIVE_ZERO (1 << 11) 138 #define S390_TDC_NEGATIVE_ZERO (1 << 10) 139 #define S390_TDC_POSITIVE_NORMALIZED_BFP_NUMBER (1 << 9) 140 #define S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER (1 << 8) 141 #define S390_TDC_POSITIVE_DENORMALIZED_BFP_NUMBER (1 << 7) 142 #define S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER (1 << 6) 143 #define S390_TDC_POSITIVE_INFINITY (1 << 5) 144 #define S390_TDC_NEGATIVE_INFINITY (1 << 4) 145 #define S390_TDC_POSITIVE_QUIET_NAN (1 << 3) 146 #define S390_TDC_NEGATIVE_QUIET_NAN (1 << 2) 147 #define S390_TDC_POSITIVE_SIGNALING_NAN (1 << 1) 148 #define S390_TDC_NEGATIVE_SIGNALING_NAN (1 << 0) 149 150 /* The following values are different for DFP. */ 151 #define S390_TDC_POSITIVE_DENORMALIZED_DFP_NUMBER (1 << 9) 152 #define S390_TDC_NEGATIVE_DENORMALIZED_DFP_NUMBER (1 << 8) 153 #define S390_TDC_POSITIVE_NORMALIZED_DFP_NUMBER (1 << 7) 154 #define S390_TDC_NEGATIVE_NORMALIZED_DFP_NUMBER (1 << 6) 155 156 /* For signbit, the BFP-DFP-difference makes no difference. */ 157 #define S390_TDC_SIGNBIT_SET (S390_TDC_NEGATIVE_ZERO \ 158 | S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER \ 159 | S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER\ 160 | S390_TDC_NEGATIVE_INFINITY \ 161 | S390_TDC_NEGATIVE_QUIET_NAN \ 162 | S390_TDC_NEGATIVE_SIGNALING_NAN ) 163 164 #define S390_TDC_INFINITY (S390_TDC_POSITIVE_INFINITY \ 165 | S390_TDC_NEGATIVE_INFINITY ) 166 167 /* Target machine storage layout. */ 168 169 /* Everything is big-endian. */ 170 #define BITS_BIG_ENDIAN 1 171 #define BYTES_BIG_ENDIAN 1 172 #define WORDS_BIG_ENDIAN 1 173 174 #define STACK_SIZE_MODE (Pmode) 175 176 #ifndef IN_LIBGCC2 177 178 /* Width of a word, in units (bytes). */ 179 #define UNITS_PER_WORD (TARGET_ZARCH ? 8 : 4) 180 181 /* Width of a pointer. To be used instead of UNITS_PER_WORD in 182 ABI-relevant contexts. This always matches 183 GET_MODE_SIZE (Pmode). */ 184 #define UNITS_PER_LONG (TARGET_64BIT ? 8 : 4) 185 #define MIN_UNITS_PER_WORD 4 186 #define MAX_BITS_PER_WORD 64 187 #else 188 189 /* In libgcc, UNITS_PER_WORD has ABI-relevant effects, e.g. whether 190 the library should export TImode functions or not. Thus, we have 191 to redefine UNITS_PER_WORD depending on __s390x__ for libgcc. */ 192 #ifdef __s390x__ 193 #define UNITS_PER_WORD 8 194 #else 195 #define UNITS_PER_WORD 4 196 #endif 197 #endif 198 199 /* Width of a pointer, in bits. */ 200 #define POINTER_SIZE (TARGET_64BIT ? 64 : 32) 201 202 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 203 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32) 204 205 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 206 #define STACK_BOUNDARY 64 207 208 /* Allocation boundary (in *bits*) for the code of a function. */ 209 #define FUNCTION_BOUNDARY 32 210 211 /* There is no point aligning anything to a rounder boundary than this. */ 212 #define BIGGEST_ALIGNMENT 64 213 214 /* Alignment of field after `int : 0' in a structure. */ 215 #define EMPTY_FIELD_BOUNDARY 32 216 217 /* Alignment on even addresses for LARL instruction. */ 218 #define CONSTANT_ALIGNMENT(EXP, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN) 219 #define DATA_ALIGNMENT(TYPE, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN) 220 221 /* Alignment is not required by the hardware. */ 222 #define STRICT_ALIGNMENT 0 223 224 /* Mode of stack savearea. 225 FUNCTION is VOIDmode because calling convention maintains SP. 226 BLOCK needs Pmode for SP. 227 NONLOCAL needs twice Pmode to maintain both backchain and SP. */ 228 #define STACK_SAVEAREA_MODE(LEVEL) \ 229 (LEVEL == SAVE_FUNCTION ? VOIDmode \ 230 : LEVEL == SAVE_NONLOCAL ? (TARGET_64BIT ? OImode : TImode) : Pmode) 231 232 233 /* Type layout. */ 234 235 /* Sizes in bits of the source language data types. */ 236 #define SHORT_TYPE_SIZE 16 237 #define INT_TYPE_SIZE 32 238 #define LONG_TYPE_SIZE (TARGET_64BIT ? 64 : 32) 239 #define LONG_LONG_TYPE_SIZE 64 240 #define FLOAT_TYPE_SIZE 32 241 #define DOUBLE_TYPE_SIZE 64 242 #define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_128 ? 128 : 64) 243 244 /* Define this to set long double type size to use in libgcc2.c, which can 245 not depend on target_flags. */ 246 #ifdef __LONG_DOUBLE_128__ 247 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 248 #else 249 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 250 #endif 251 252 /* Work around target_flags dependency in ada/targtyps.c. */ 253 #define WIDEST_HARDWARE_FP_SIZE 64 254 255 /* We use "unsigned char" as default. */ 256 #define DEFAULT_SIGNED_CHAR 0 257 258 259 /* Register usage. */ 260 261 /* We have 16 general purpose registers (registers 0-15), 262 and 16 floating point registers (registers 16-31). 263 (On non-IEEE machines, we have only 4 fp registers.) 264 265 Amongst the general purpose registers, some are used 266 for specific purposes: 267 GPR 11: Hard frame pointer (if needed) 268 GPR 12: Global offset table pointer (if needed) 269 GPR 13: Literal pool base register 270 GPR 14: Return address register 271 GPR 15: Stack pointer 272 273 Registers 32-35 are 'fake' hard registers that do not 274 correspond to actual hardware: 275 Reg 32: Argument pointer 276 Reg 33: Condition code 277 Reg 34: Frame pointer 278 Reg 35: Return address pointer 279 280 Registers 36 and 37 are mapped to access registers 281 0 and 1, used to implement thread-local storage. */ 282 283 #define FIRST_PSEUDO_REGISTER 38 284 285 /* Standard register usage. */ 286 #define GENERAL_REGNO_P(N) ((int)(N) >= 0 && (N) < 16) 287 #define ADDR_REGNO_P(N) ((N) >= 1 && (N) < 16) 288 #define FP_REGNO_P(N) ((N) >= 16 && (N) < 32) 289 #define CC_REGNO_P(N) ((N) == 33) 290 #define FRAME_REGNO_P(N) ((N) == 32 || (N) == 34 || (N) == 35) 291 #define ACCESS_REGNO_P(N) ((N) == 36 || (N) == 37) 292 293 #define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) 294 #define ADDR_REG_P(X) (REG_P (X) && ADDR_REGNO_P (REGNO (X))) 295 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) 296 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) 297 #define FRAME_REG_P(X) (REG_P (X) && FRAME_REGNO_P (REGNO (X))) 298 #define ACCESS_REG_P(X) (REG_P (X) && ACCESS_REGNO_P (REGNO (X))) 299 300 /* Set up fixed registers and calling convention: 301 302 GPRs 0-5 are always call-clobbered, 303 GPRs 6-15 are always call-saved. 304 GPR 12 is fixed if used as GOT pointer. 305 GPR 13 is always fixed (as literal pool pointer). 306 GPR 14 is always fixed on S/390 machines (as return address). 307 GPR 15 is always fixed (as stack pointer). 308 The 'fake' hard registers are call-clobbered and fixed. 309 The access registers are call-saved and fixed. 310 311 On 31-bit, FPRs 18-19 are call-clobbered; 312 on 64-bit, FPRs 24-31 are call-clobbered. 313 The remaining FPRs are call-saved. */ 314 315 #define FIXED_REGISTERS \ 316 { 0, 0, 0, 0, \ 317 0, 0, 0, 0, \ 318 0, 0, 0, 0, \ 319 0, 1, 1, 1, \ 320 0, 0, 0, 0, \ 321 0, 0, 0, 0, \ 322 0, 0, 0, 0, \ 323 0, 0, 0, 0, \ 324 1, 1, 1, 1, \ 325 1, 1 } 326 327 #define CALL_USED_REGISTERS \ 328 { 1, 1, 1, 1, \ 329 1, 1, 0, 0, \ 330 0, 0, 0, 0, \ 331 0, 1, 1, 1, \ 332 1, 1, 1, 1, \ 333 1, 1, 1, 1, \ 334 1, 1, 1, 1, \ 335 1, 1, 1, 1, \ 336 1, 1, 1, 1, \ 337 1, 1 } 338 339 #define CALL_REALLY_USED_REGISTERS \ 340 { 1, 1, 1, 1, \ 341 1, 1, 0, 0, \ 342 0, 0, 0, 0, \ 343 0, 0, 0, 0, \ 344 1, 1, 1, 1, \ 345 1, 1, 1, 1, \ 346 1, 1, 1, 1, \ 347 1, 1, 1, 1, \ 348 1, 1, 1, 1, \ 349 0, 0 } 350 351 /* Preferred register allocation order. */ 352 #define REG_ALLOC_ORDER \ 353 { 1, 2, 3, 4, 5, 0, 12, 11, 10, 9, 8, 7, 6, 14, 13, \ 354 16, 17, 18, 19, 20, 21, 22, 23, \ 355 24, 25, 26, 27, 28, 29, 30, 31, \ 356 15, 32, 33, 34, 35, 36, 37 } 357 358 359 /* Fitting values into registers. */ 360 361 /* Integer modes <= word size fit into any GPR. 362 Integer modes > word size fit into successive GPRs, starting with 363 an even-numbered register. 364 SImode and DImode fit into FPRs as well. 365 366 Floating point modes <= word size fit into any FPR or GPR. 367 Floating point modes > word size (i.e. DFmode on 32-bit) fit 368 into any FPR, or an even-odd GPR pair. 369 TFmode fits only into an even-odd FPR pair. 370 371 Complex floating point modes fit either into two FPRs, or into 372 successive GPRs (again starting with an even number). 373 TCmode fits only into two successive even-odd FPR pairs. 374 375 Condition code modes fit only into the CC register. */ 376 377 /* Because all registers in a class have the same size HARD_REGNO_NREGS 378 is equivalent to CLASS_MAX_NREGS. */ 379 #define HARD_REGNO_NREGS(REGNO, MODE) \ 380 s390_class_max_nregs (REGNO_REG_CLASS (REGNO), (MODE)) 381 382 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 383 s390_hard_regno_mode_ok ((REGNO), (MODE)) 384 385 #define HARD_REGNO_RENAME_OK(FROM, TO) \ 386 s390_hard_regno_rename_ok (FROM, TO) 387 388 #define MODES_TIEABLE_P(MODE1, MODE2) \ 389 (((MODE1) == SFmode || (MODE1) == DFmode) \ 390 == ((MODE2) == SFmode || (MODE2) == DFmode)) 391 392 /* When generating code that runs in z/Architecture mode, 393 but conforms to the 31-bit ABI, GPRs can hold 8 bytes; 394 the ABI guarantees only that the lower 4 bytes are 395 saved across calls, however. */ 396 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \ 397 (!TARGET_64BIT && TARGET_ZARCH \ 398 && GET_MODE_SIZE (MODE) > 4 \ 399 && (((REGNO) >= 6 && (REGNO) <= 15) || (REGNO) == 32)) 400 401 /* Maximum number of registers to represent a value of mode MODE 402 in a register of class CLASS. */ 403 #define CLASS_MAX_NREGS(CLASS, MODE) \ 404 s390_class_max_nregs ((CLASS), (MODE)) 405 406 /* If a 4-byte value is loaded into a FPR, it is placed into the 407 *upper* half of the register, not the lower. Therefore, we 408 cannot use SUBREGs to switch between modes in FP registers. 409 Likewise for access registers, since they have only half the 410 word size on 64-bit. */ 411 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 412 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ 413 ? ((reg_classes_intersect_p (FP_REGS, CLASS) \ 414 && (GET_MODE_SIZE (FROM) < 8 || GET_MODE_SIZE (TO) < 8)) \ 415 || reg_classes_intersect_p (ACCESS_REGS, CLASS)) : 0) 416 417 /* Register classes. */ 418 419 /* We use the following register classes: 420 GENERAL_REGS All general purpose registers 421 ADDR_REGS All general purpose registers except %r0 422 (These registers can be used in address generation) 423 FP_REGS All floating point registers 424 CC_REGS The condition code register 425 ACCESS_REGS The access registers 426 427 GENERAL_FP_REGS Union of GENERAL_REGS and FP_REGS 428 ADDR_FP_REGS Union of ADDR_REGS and FP_REGS 429 GENERAL_CC_REGS Union of GENERAL_REGS and CC_REGS 430 ADDR_CC_REGS Union of ADDR_REGS and CC_REGS 431 432 NO_REGS No registers 433 ALL_REGS All registers 434 435 Note that the 'fake' frame pointer and argument pointer registers 436 are included amongst the address registers here. */ 437 438 enum reg_class 439 { 440 NO_REGS, CC_REGS, ADDR_REGS, GENERAL_REGS, ACCESS_REGS, 441 ADDR_CC_REGS, GENERAL_CC_REGS, 442 FP_REGS, ADDR_FP_REGS, GENERAL_FP_REGS, 443 ALL_REGS, LIM_REG_CLASSES 444 }; 445 #define N_REG_CLASSES (int) LIM_REG_CLASSES 446 447 #define REG_CLASS_NAMES \ 448 { "NO_REGS", "CC_REGS", "ADDR_REGS", "GENERAL_REGS", "ACCESS_REGS", \ 449 "ADDR_CC_REGS", "GENERAL_CC_REGS", \ 450 "FP_REGS", "ADDR_FP_REGS", "GENERAL_FP_REGS", "ALL_REGS" } 451 452 /* Class -> register mapping. */ 453 #define REG_CLASS_CONTENTS \ 454 { \ 455 { 0x00000000, 0x00000000 }, /* NO_REGS */ \ 456 { 0x00000000, 0x00000002 }, /* CC_REGS */ \ 457 { 0x0000fffe, 0x0000000d }, /* ADDR_REGS */ \ 458 { 0x0000ffff, 0x0000000d }, /* GENERAL_REGS */ \ 459 { 0x00000000, 0x00000030 }, /* ACCESS_REGS */ \ 460 { 0x0000fffe, 0x0000000f }, /* ADDR_CC_REGS */ \ 461 { 0x0000ffff, 0x0000000f }, /* GENERAL_CC_REGS */ \ 462 { 0xffff0000, 0x00000000 }, /* FP_REGS */ \ 463 { 0xfffffffe, 0x0000000d }, /* ADDR_FP_REGS */ \ 464 { 0xffffffff, 0x0000000d }, /* GENERAL_FP_REGS */ \ 465 { 0xffffffff, 0x0000003f }, /* ALL_REGS */ \ 466 } 467 468 /* In some case register allocation order is not enough for IRA to 469 generate a good code. The following macro (if defined) increases 470 cost of REGNO for a pseudo approximately by pseudo usage frequency 471 multiplied by the macro value. 472 473 We avoid usage of BASE_REGNUM by nonzero macro value because the 474 reload can decide not to use the hard register because some 475 constant was forced to be in memory. */ 476 #define IRA_HARD_REGNO_ADD_COST_MULTIPLIER(regno) \ 477 (regno == BASE_REGNUM ? 0.0 : 0.5) 478 479 /* Register -> class mapping. */ 480 extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; 481 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) 482 483 /* ADDR_REGS can be used as base or index register. */ 484 #define INDEX_REG_CLASS ADDR_REGS 485 #define BASE_REG_CLASS ADDR_REGS 486 487 /* Check whether REGNO is a hard register of the suitable class 488 or a pseudo register currently allocated to one such. */ 489 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 490 (((REGNO) < FIRST_PSEUDO_REGISTER \ 491 && REGNO_REG_CLASS ((REGNO)) == ADDR_REGS) \ 492 || ADDR_REGNO_P (reg_renumber[REGNO])) 493 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO) 494 495 496 /* We need secondary memory to move data between GPRs and FPRs. With 497 DFP the ldgr lgdr instructions are available. But these 498 instructions do not handle GPR pairs so it is not possible for 31 499 bit. */ 500 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 501 ((CLASS1) != (CLASS2) \ 502 && ((CLASS1) == FP_REGS || (CLASS2) == FP_REGS) \ 503 && (!TARGET_DFP || !TARGET_64BIT || GET_MODE_SIZE (MODE) != 8)) 504 505 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on 64bit 506 because the movsi and movsf patterns don't handle r/f moves. */ 507 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ 508 (GET_MODE_BITSIZE (MODE) < 32 \ 509 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ 510 : MODE) 511 512 513 /* Stack layout and calling conventions. */ 514 515 /* Our stack grows from higher to lower addresses. However, local variables 516 are accessed by positive offsets, and function arguments are stored at 517 increasing addresses. */ 518 #define STACK_GROWS_DOWNWARD 519 #define FRAME_GROWS_DOWNWARD 1 520 /* #undef ARGS_GROW_DOWNWARD */ 521 522 /* The basic stack layout looks like this: the stack pointer points 523 to the register save area for called functions. Above that area 524 is the location to place outgoing arguments. Above those follow 525 dynamic allocations (alloca), and finally the local variables. */ 526 527 /* Offset from stack-pointer to first location of outgoing args. */ 528 #define STACK_POINTER_OFFSET (TARGET_64BIT ? 160 : 96) 529 530 /* Offset within stack frame to start allocating local variables at. */ 531 #define STARTING_FRAME_OFFSET 0 532 533 /* Offset from the stack pointer register to an item dynamically 534 allocated on the stack, e.g., by `alloca'. */ 535 #define STACK_DYNAMIC_OFFSET(FUNDECL) \ 536 (STACK_POINTER_OFFSET + crtl->outgoing_args_size) 537 538 /* Offset of first parameter from the argument pointer register value. 539 We have a fake argument pointer register that points directly to 540 the argument area. */ 541 #define FIRST_PARM_OFFSET(FNDECL) 0 542 543 /* Defining this macro makes __builtin_frame_address(0) and 544 __builtin_return_address(0) work with -fomit-frame-pointer. */ 545 #define INITIAL_FRAME_ADDRESS_RTX \ 546 (plus_constant (Pmode, arg_pointer_rtx, -STACK_POINTER_OFFSET)) 547 548 /* The return address of the current frame is retrieved 549 from the initial value of register RETURN_REGNUM. 550 For frames farther back, we use the stack slot where 551 the corresponding RETURN_REGNUM register was saved. */ 552 #define DYNAMIC_CHAIN_ADDRESS(FRAME) \ 553 (TARGET_PACKED_STACK ? \ 554 plus_constant (Pmode, (FRAME), \ 555 STACK_POINTER_OFFSET - UNITS_PER_LONG) : (FRAME)) 556 557 /* For -mpacked-stack this adds 160 - 8 (96 - 4) to the output of 558 builtin_frame_address. Otherwise arg pointer - 559 STACK_POINTER_OFFSET would be returned for 560 __builtin_frame_address(0) what might result in an address pointing 561 somewhere into the middle of the local variables since the packed 562 stack layout generally does not need all the bytes in the register 563 save area. */ 564 #define FRAME_ADDR_RTX(FRAME) \ 565 DYNAMIC_CHAIN_ADDRESS ((FRAME)) 566 567 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 568 s390_return_addr_rtx ((COUNT), DYNAMIC_CHAIN_ADDRESS ((FRAME))) 569 570 /* In 31-bit mode, we need to mask off the high bit of return addresses. */ 571 #define MASK_RETURN_ADDR (TARGET_64BIT ? constm1_rtx : GEN_INT (0x7fffffff)) 572 573 574 /* Exception handling. */ 575 576 /* Describe calling conventions for DWARF-2 exception handling. */ 577 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_REGNUM) 578 #define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET 579 #define DWARF_FRAME_RETURN_COLUMN 14 580 581 /* Describe how we implement __builtin_eh_return. */ 582 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 6 : INVALID_REGNUM) 583 #define EH_RETURN_HANDLER_RTX gen_rtx_MEM (Pmode, return_address_pointer_rtx) 584 585 /* Select a format to encode pointers in exception handling data. */ 586 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 587 (flag_pic \ 588 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \ 589 : DW_EH_PE_absptr) 590 591 /* Register save slot alignment. */ 592 #define DWARF_CIE_DATA_ALIGNMENT (-UNITS_PER_LONG) 593 594 /* Let the assembler generate debug line info. */ 595 #define DWARF2_ASM_LINE_DEBUG_INFO 1 596 597 598 /* Frame registers. */ 599 600 #define STACK_POINTER_REGNUM 15 601 #define FRAME_POINTER_REGNUM 34 602 #define HARD_FRAME_POINTER_REGNUM 11 603 #define ARG_POINTER_REGNUM 32 604 #define RETURN_ADDRESS_POINTER_REGNUM 35 605 606 /* The static chain must be call-clobbered, but not used for 607 function argument passing. As register 1 is clobbered by 608 the trampoline code, we only have one option. */ 609 #define STATIC_CHAIN_REGNUM 0 610 611 /* Number of hardware registers that go into the DWARF-2 unwind info. 612 To avoid ABI incompatibility, this number must not change even as 613 'fake' hard registers are added or removed. */ 614 #define DWARF_FRAME_REGISTERS 34 615 616 617 /* Frame pointer and argument pointer elimination. */ 618 619 #define ELIMINABLE_REGS \ 620 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 621 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ 622 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 623 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ 624 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 625 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ 626 { BASE_REGNUM, BASE_REGNUM }} 627 628 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 629 (OFFSET) = s390_initial_elimination_offset ((FROM), (TO)) 630 631 632 /* Stack arguments. */ 633 634 /* We need current_function_outgoing_args to be valid. */ 635 #define ACCUMULATE_OUTGOING_ARGS 1 636 637 638 /* Register arguments. */ 639 640 typedef struct s390_arg_structure 641 { 642 int gprs; /* gpr so far */ 643 int fprs; /* fpr so far */ 644 } 645 CUMULATIVE_ARGS; 646 647 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, NN, N_NAMED_ARGS) \ 648 ((CUM).gprs=0, (CUM).fprs=0) 649 650 /* Arguments can be placed in general registers 2 to 6, or in floating 651 point registers 0 and 2 for 31 bit and fprs 0, 2, 4 and 6 for 64 652 bit. */ 653 #define FUNCTION_ARG_REGNO_P(N) (((N) >=2 && (N) <7) || \ 654 (N) == 16 || (N) == 17 || (TARGET_64BIT && ((N) == 18 || (N) == 19))) 655 656 657 /* Only gpr 2 and fpr 0 are ever used as return registers. */ 658 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 2 || (N) == 16) 659 660 661 /* Function entry and exit. */ 662 663 /* When returning from a function, the stack pointer does not matter. */ 664 #define EXIT_IGNORE_STACK 1 665 666 667 /* Profiling. */ 668 669 #define FUNCTION_PROFILER(FILE, LABELNO) \ 670 s390_function_profiler ((FILE), ((LABELNO))) 671 672 #define PROFILE_BEFORE_PROLOGUE 1 673 674 675 /* Trampolines for nested functions. */ 676 677 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 32 : 16) 678 #define TRAMPOLINE_ALIGNMENT BITS_PER_WORD 679 680 /* Addressing modes, and classification of registers for them. */ 681 682 /* Recognize any constant value that is a valid address. */ 683 #define CONSTANT_ADDRESS_P(X) 0 684 685 /* Maximum number of registers that can appear in a valid memory address. */ 686 #define MAX_REGS_PER_ADDRESS 2 687 688 /* This definition replaces the formerly used 'm' constraint with a 689 different constraint letter in order to avoid changing semantics of 690 the 'm' constraint when accepting new address formats in 691 TARGET_LEGITIMATE_ADDRESS_P. The constraint letter defined here 692 must not be used in insn definitions or inline assemblies. */ 693 #define TARGET_MEM_CONSTRAINT 'e' 694 695 /* Try a machine-dependent way of reloading an illegitimate address 696 operand. If we find one, push the reload and jump to WIN. This 697 macro is used in only one place: `find_reloads_address' in reload.c. */ 698 #define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) \ 699 do { \ 700 rtx new_rtx = legitimize_reload_address (AD, MODE, OPNUM, (int)(TYPE)); \ 701 if (new_rtx) \ 702 { \ 703 (AD) = new_rtx; \ 704 goto WIN; \ 705 } \ 706 } while (0) 707 708 /* Helper macro for s390.c and s390.md to check for symbolic constants. */ 709 #define SYMBOLIC_CONST(X) \ 710 (GET_CODE (X) == SYMBOL_REF \ 711 || GET_CODE (X) == LABEL_REF \ 712 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) 713 714 #define TLS_SYMBOLIC_CONST(X) \ 715 ((GET_CODE (X) == SYMBOL_REF && tls_symbolic_operand (X)) \ 716 || (GET_CODE (X) == CONST && tls_symbolic_reference_mentioned_p (X))) 717 718 719 /* Condition codes. */ 720 721 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 722 return the mode to be used for the comparison. */ 723 #define SELECT_CC_MODE(OP, X, Y) s390_select_ccmode ((OP), (X), (Y)) 724 725 /* Relative costs of operations. */ 726 727 /* A C expression for the cost of a branch instruction. A value of 1 728 is the default; other values are interpreted relative to that. */ 729 #define BRANCH_COST(speed_p, predictable_p) s390_branch_cost 730 731 /* Nonzero if access to memory by bytes is slow and undesirable. */ 732 #define SLOW_BYTE_ACCESS 1 733 734 /* An integer expression for the size in bits of the largest integer machine 735 mode that should actually be used. We allow pairs of registers. */ 736 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode) 737 738 /* The maximum number of bytes that a single instruction can move quickly 739 between memory and registers or between two memory locations. */ 740 #define MOVE_MAX (TARGET_ZARCH ? 16 : 8) 741 #define MOVE_MAX_PIECES (TARGET_ZARCH ? 8 : 4) 742 #define MAX_MOVE_MAX 16 743 744 /* Determine whether to use move_by_pieces or block move insn. */ 745 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \ 746 ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \ 747 || (TARGET_ZARCH && (SIZE) == 8) ) 748 749 /* Determine whether to use clear_by_pieces or block clear insn. */ 750 #define CLEAR_BY_PIECES_P(SIZE, ALIGN) \ 751 ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \ 752 || (TARGET_ZARCH && (SIZE) == 8) ) 753 754 /* This macro is used to determine whether store_by_pieces should be 755 called to "memcpy" storage when the source is a constant string. */ 756 #define STORE_BY_PIECES_P(SIZE, ALIGN) MOVE_BY_PIECES_P (SIZE, ALIGN) 757 758 /* Likewise to decide whether to "memset" storage with byte values 759 other than zero. */ 760 #define SET_BY_PIECES_P(SIZE, ALIGN) STORE_BY_PIECES_P (SIZE, ALIGN) 761 762 /* Don't perform CSE on function addresses. */ 763 #define NO_FUNCTION_CSE 764 765 /* This value is used in tree-sra to decide whether it might benefical 766 to split a struct move into several word-size moves. For S/390 767 only small values make sense here since struct moves are relatively 768 cheap thanks to mvc so the small default value chosen for archs 769 with memmove patterns should be ok. But this value is multiplied 770 in tree-sra with UNITS_PER_WORD to make a decision so we adjust it 771 here to compensate for that factor since mvc costs exactly the same 772 on 31 and 64 bit. */ 773 #define MOVE_RATIO(speed) (TARGET_64BIT? 2 : 4) 774 775 776 /* Sections. */ 777 778 /* Output before read-only data. */ 779 #define TEXT_SECTION_ASM_OP ".text" 780 781 /* Output before writable (initialized) data. */ 782 #define DATA_SECTION_ASM_OP ".data" 783 784 /* Output before writable (uninitialized) data. */ 785 #define BSS_SECTION_ASM_OP ".bss" 786 787 /* S/390 constant pool breaks the devices in crtstuff.c to control section 788 in where code resides. We have to write it as asm code. */ 789 #ifndef __s390x__ 790 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 791 asm (SECTION_OP "\n\ 792 bras\t%r2,1f\n\ 793 0: .long\t" USER_LABEL_PREFIX #FUNC " - 0b\n\ 794 1: l\t%r3,0(%r2)\n\ 795 bas\t%r14,0(%r3,%r2)\n\ 796 .previous"); 797 #endif 798 799 800 /* Position independent code. */ 801 802 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 12 : INVALID_REGNUM) 803 804 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) 805 806 807 /* Assembler file format. */ 808 809 /* Character to start a comment. */ 810 #define ASM_COMMENT_START "#" 811 812 /* Declare an uninitialized external linkage data object. */ 813 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ 814 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN) 815 816 /* Globalizing directive for a label. */ 817 #define GLOBAL_ASM_OP ".globl " 818 819 /* Advance the location counter to a multiple of 2**LOG bytes. */ 820 #define ASM_OUTPUT_ALIGN(FILE, LOG) \ 821 if ((LOG)) fprintf ((FILE), "\t.align\t%d\n", 1 << (LOG)) 822 823 /* Advance the location counter by SIZE bytes. */ 824 #define ASM_OUTPUT_SKIP(FILE, SIZE) \ 825 fprintf ((FILE), "\t.set\t.,.+" HOST_WIDE_INT_PRINT_UNSIGNED "\n", (SIZE)) 826 827 /* The LOCAL_LABEL_PREFIX variable is used by dbxelf.h. */ 828 #define LOCAL_LABEL_PREFIX "." 829 830 #define LABEL_ALIGN(LABEL) \ 831 s390_label_align (LABEL) 832 833 /* How to refer to registers in assembler output. This sequence is 834 indexed by compiler's hard-register-number (see above). */ 835 #define REGISTER_NAMES \ 836 { "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", \ 837 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \ 838 "%f0", "%f2", "%f4", "%f6", "%f1", "%f3", "%f5", "%f7", \ 839 "%f8", "%f10", "%f12", "%f14", "%f9", "%f11", "%f13", "%f15", \ 840 "%ap", "%cc", "%fp", "%rp", "%a0", "%a1" \ 841 } 842 843 /* Print operand X (an rtx) in assembler syntax to file FILE. */ 844 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 845 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) 846 847 /* Output an element of a case-vector that is absolute. */ 848 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 849 do { \ 850 char buf[32]; \ 851 fputs (integer_asm_op (UNITS_PER_LONG, TRUE), (FILE)); \ 852 ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \ 853 assemble_name ((FILE), buf); \ 854 fputc ('\n', (FILE)); \ 855 } while (0) 856 857 /* Output an element of a case-vector that is relative. */ 858 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 859 do { \ 860 char buf[32]; \ 861 fputs (integer_asm_op (UNITS_PER_LONG, TRUE), (FILE)); \ 862 ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \ 863 assemble_name ((FILE), buf); \ 864 fputc ('-', (FILE)); \ 865 ASM_GENERATE_INTERNAL_LABEL (buf, "L", (REL)); \ 866 assemble_name ((FILE), buf); \ 867 fputc ('\n', (FILE)); \ 868 } while (0) 869 870 871 /* Miscellaneous parameters. */ 872 873 /* Specify the machine mode that this machine uses for the index in the 874 tablejump instruction. */ 875 #define CASE_VECTOR_MODE (TARGET_64BIT ? DImode : SImode) 876 877 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 878 is done just by pretending it is already truncated. */ 879 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 880 881 /* Specify the machine mode that pointers have. 882 After generation of rtl, the compiler makes no further distinction 883 between pointers and any other objects of this machine mode. */ 884 #define Pmode ((enum machine_mode) (TARGET_64BIT ? DImode : SImode)) 885 886 /* This is -1 for "pointer mode" extend. See ptr_extend in s390.md. */ 887 #define POINTERS_EXTEND_UNSIGNED -1 888 889 /* A function address in a call instruction is a byte address (for 890 indexing purposes) so give the MEM rtx a byte's mode. */ 891 #define FUNCTION_MODE QImode 892 893 /* Specify the value which is used when clz operand is zero. */ 894 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 64, 1) 895 896 /* Machine-specific symbol_ref flags. */ 897 #define SYMBOL_FLAG_ALIGN1 (SYMBOL_FLAG_MACH_DEP << 0) 898 #define SYMBOL_REF_ALIGN1_P(X) \ 899 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_ALIGN1)) 900 #define SYMBOL_FLAG_NOT_NATURALLY_ALIGNED (SYMBOL_FLAG_MACH_DEP << 1) 901 #define SYMBOL_REF_NOT_NATURALLY_ALIGNED_P(X) \ 902 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_NOT_NATURALLY_ALIGNED)) 903 904 /* Check whether integer displacement is in range. */ 905 #define DISP_IN_RANGE(d) \ 906 (TARGET_LONG_DISPLACEMENT? ((d) >= -524288 && (d) <= 524287) \ 907 : ((d) >= 0 && (d) <= 4095)) 908 909 /* Reads can reuse write prefetches, used by tree-ssa-prefetch-loops.c. */ 910 #define READ_CAN_USE_WRITE_PREFETCH 1 911 912 extern const int processor_flags_table[]; 913 #endif 914