1 /* Perform simple optimizations to clean up the result of reload.
2 Copyright (C) 1987-2013 Free Software Foundation, Inc.
3
4 This file is part of GCC.
5
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
10
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
19
20 #include "config.h"
21 #include "system.h"
22 #include "coretypes.h"
23 #include "tm.h"
24
25 #include "machmode.h"
26 #include "hard-reg-set.h"
27 #include "rtl.h"
28 #include "tm_p.h"
29 #include "obstack.h"
30 #include "insn-config.h"
31 #include "flags.h"
32 #include "function.h"
33 #include "expr.h"
34 #include "optabs.h"
35 #include "regs.h"
36 #include "basic-block.h"
37 #include "reload.h"
38 #include "recog.h"
39 #include "cselib.h"
40 #include "diagnostic-core.h"
41 #include "except.h"
42 #include "tree.h"
43 #include "target.h"
44 #include "tree-pass.h"
45 #include "df.h"
46 #include "dbgcnt.h"
47
48 static int reload_cse_noop_set_p (rtx);
49 static bool reload_cse_simplify (rtx, rtx);
50 static void reload_cse_regs_1 (void);
51 static int reload_cse_simplify_set (rtx, rtx);
52 static int reload_cse_simplify_operands (rtx, rtx);
53
54 static void reload_combine (void);
55 static void reload_combine_note_use (rtx *, rtx, int, rtx);
56 static void reload_combine_note_store (rtx, const_rtx, void *);
57
58 static bool reload_cse_move2add (rtx);
59 static void move2add_note_store (rtx, const_rtx, void *);
60
61 /* Call cse / combine like post-reload optimization phases.
62 FIRST is the first instruction. */
63
64 static void
reload_cse_regs(rtx first ATTRIBUTE_UNUSED)65 reload_cse_regs (rtx first ATTRIBUTE_UNUSED)
66 {
67 bool moves_converted;
68 reload_cse_regs_1 ();
69 reload_combine ();
70 moves_converted = reload_cse_move2add (first);
71 if (flag_expensive_optimizations)
72 {
73 if (moves_converted)
74 reload_combine ();
75 reload_cse_regs_1 ();
76 }
77 }
78
79 /* See whether a single set SET is a noop. */
80 static int
reload_cse_noop_set_p(rtx set)81 reload_cse_noop_set_p (rtx set)
82 {
83 if (cselib_reg_set_mode (SET_DEST (set)) != GET_MODE (SET_DEST (set)))
84 return 0;
85
86 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set));
87 }
88
89 /* Try to simplify INSN. Return true if the CFG may have changed. */
90 static bool
reload_cse_simplify(rtx insn,rtx testreg)91 reload_cse_simplify (rtx insn, rtx testreg)
92 {
93 rtx body = PATTERN (insn);
94 basic_block insn_bb = BLOCK_FOR_INSN (insn);
95 unsigned insn_bb_succs = EDGE_COUNT (insn_bb->succs);
96
97 if (GET_CODE (body) == SET)
98 {
99 int count = 0;
100
101 /* Simplify even if we may think it is a no-op.
102 We may think a memory load of a value smaller than WORD_SIZE
103 is redundant because we haven't taken into account possible
104 implicit extension. reload_cse_simplify_set() will bring
105 this out, so it's safer to simplify before we delete. */
106 count += reload_cse_simplify_set (body, insn);
107
108 if (!count && reload_cse_noop_set_p (body))
109 {
110 rtx value = SET_DEST (body);
111 if (REG_P (value)
112 && ! REG_FUNCTION_VALUE_P (value))
113 value = 0;
114 if (check_for_inc_dec (insn))
115 delete_insn_and_edges (insn);
116 /* We're done with this insn. */
117 goto done;
118 }
119
120 if (count > 0)
121 apply_change_group ();
122 else
123 reload_cse_simplify_operands (insn, testreg);
124 }
125 else if (GET_CODE (body) == PARALLEL)
126 {
127 int i;
128 int count = 0;
129 rtx value = NULL_RTX;
130
131 /* Registers mentioned in the clobber list for an asm cannot be reused
132 within the body of the asm. Invalidate those registers now so that
133 we don't try to substitute values for them. */
134 if (asm_noperands (body) >= 0)
135 {
136 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
137 {
138 rtx part = XVECEXP (body, 0, i);
139 if (GET_CODE (part) == CLOBBER && REG_P (XEXP (part, 0)))
140 cselib_invalidate_rtx (XEXP (part, 0));
141 }
142 }
143
144 /* If every action in a PARALLEL is a noop, we can delete
145 the entire PARALLEL. */
146 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
147 {
148 rtx part = XVECEXP (body, 0, i);
149 if (GET_CODE (part) == SET)
150 {
151 if (! reload_cse_noop_set_p (part))
152 break;
153 if (REG_P (SET_DEST (part))
154 && REG_FUNCTION_VALUE_P (SET_DEST (part)))
155 {
156 if (value)
157 break;
158 value = SET_DEST (part);
159 }
160 }
161 else if (GET_CODE (part) != CLOBBER)
162 break;
163 }
164
165 if (i < 0)
166 {
167 if (check_for_inc_dec (insn))
168 delete_insn_and_edges (insn);
169 /* We're done with this insn. */
170 goto done;
171 }
172
173 /* It's not a no-op, but we can try to simplify it. */
174 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
175 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
176 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
177
178 if (count > 0)
179 apply_change_group ();
180 else
181 reload_cse_simplify_operands (insn, testreg);
182 }
183
184 done:
185 return (EDGE_COUNT (insn_bb->succs) != insn_bb_succs);
186 }
187
188 /* Do a very simple CSE pass over the hard registers.
189
190 This function detects no-op moves where we happened to assign two
191 different pseudo-registers to the same hard register, and then
192 copied one to the other. Reload will generate a useless
193 instruction copying a register to itself.
194
195 This function also detects cases where we load a value from memory
196 into two different registers, and (if memory is more expensive than
197 registers) changes it to simply copy the first register into the
198 second register.
199
200 Another optimization is performed that scans the operands of each
201 instruction to see whether the value is already available in a
202 hard register. It then replaces the operand with the hard register
203 if possible, much like an optional reload would. */
204
205 static void
reload_cse_regs_1(void)206 reload_cse_regs_1 (void)
207 {
208 bool cfg_changed = false;
209 basic_block bb;
210 rtx insn;
211 rtx testreg = gen_rtx_REG (VOIDmode, -1);
212
213 cselib_init (CSELIB_RECORD_MEMORY);
214 init_alias_analysis ();
215
216 FOR_EACH_BB (bb)
217 FOR_BB_INSNS (bb, insn)
218 {
219 if (INSN_P (insn))
220 cfg_changed |= reload_cse_simplify (insn, testreg);
221
222 cselib_process_insn (insn);
223 }
224
225 /* Clean up. */
226 end_alias_analysis ();
227 cselib_finish ();
228 if (cfg_changed)
229 cleanup_cfg (0);
230 }
231
232 /* Try to simplify a single SET instruction. SET is the set pattern.
233 INSN is the instruction it came from.
234 This function only handles one case: if we set a register to a value
235 which is not a register, we try to find that value in some other register
236 and change the set into a register copy. */
237
238 static int
reload_cse_simplify_set(rtx set,rtx insn)239 reload_cse_simplify_set (rtx set, rtx insn)
240 {
241 int did_change = 0;
242 int dreg;
243 rtx src;
244 reg_class_t dclass;
245 int old_cost;
246 cselib_val *val;
247 struct elt_loc_list *l;
248 #ifdef LOAD_EXTEND_OP
249 enum rtx_code extend_op = UNKNOWN;
250 #endif
251 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
252
253 dreg = true_regnum (SET_DEST (set));
254 if (dreg < 0)
255 return 0;
256
257 src = SET_SRC (set);
258 if (side_effects_p (src) || true_regnum (src) >= 0)
259 return 0;
260
261 dclass = REGNO_REG_CLASS (dreg);
262
263 #ifdef LOAD_EXTEND_OP
264 /* When replacing a memory with a register, we need to honor assumptions
265 that combine made wrt the contents of sign bits. We'll do this by
266 generating an extend instruction instead of a reg->reg copy. Thus
267 the destination must be a register that we can widen. */
268 if (MEM_P (src)
269 && GET_MODE_BITSIZE (GET_MODE (src)) < BITS_PER_WORD
270 && (extend_op = LOAD_EXTEND_OP (GET_MODE (src))) != UNKNOWN
271 && !REG_P (SET_DEST (set)))
272 return 0;
273 #endif
274
275 val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0, VOIDmode);
276 if (! val)
277 return 0;
278
279 /* If memory loads are cheaper than register copies, don't change them. */
280 if (MEM_P (src))
281 old_cost = memory_move_cost (GET_MODE (src), dclass, true);
282 else if (REG_P (src))
283 old_cost = register_move_cost (GET_MODE (src),
284 REGNO_REG_CLASS (REGNO (src)), dclass);
285 else
286 old_cost = set_src_cost (src, speed);
287
288 for (l = val->locs; l; l = l->next)
289 {
290 rtx this_rtx = l->loc;
291 int this_cost;
292
293 if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0))
294 {
295 #ifdef LOAD_EXTEND_OP
296 if (extend_op != UNKNOWN)
297 {
298 HOST_WIDE_INT this_val;
299
300 /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other
301 constants, such as SYMBOL_REF, cannot be extended. */
302 if (!CONST_INT_P (this_rtx))
303 continue;
304
305 this_val = INTVAL (this_rtx);
306 switch (extend_op)
307 {
308 case ZERO_EXTEND:
309 this_val &= GET_MODE_MASK (GET_MODE (src));
310 break;
311 case SIGN_EXTEND:
312 /* ??? In theory we're already extended. */
313 if (this_val == trunc_int_for_mode (this_val, GET_MODE (src)))
314 break;
315 default:
316 gcc_unreachable ();
317 }
318 this_rtx = GEN_INT (this_val);
319 }
320 #endif
321 this_cost = set_src_cost (this_rtx, speed);
322 }
323 else if (REG_P (this_rtx))
324 {
325 #ifdef LOAD_EXTEND_OP
326 if (extend_op != UNKNOWN)
327 {
328 this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx);
329 this_cost = set_src_cost (this_rtx, speed);
330 }
331 else
332 #endif
333 this_cost = register_move_cost (GET_MODE (this_rtx),
334 REGNO_REG_CLASS (REGNO (this_rtx)),
335 dclass);
336 }
337 else
338 continue;
339
340 /* If equal costs, prefer registers over anything else. That
341 tends to lead to smaller instructions on some machines. */
342 if (this_cost < old_cost
343 || (this_cost == old_cost
344 && REG_P (this_rtx)
345 && !REG_P (SET_SRC (set))))
346 {
347 #ifdef LOAD_EXTEND_OP
348 if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set))) < BITS_PER_WORD
349 && extend_op != UNKNOWN
350 #ifdef CANNOT_CHANGE_MODE_CLASS
351 && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set)),
352 word_mode,
353 REGNO_REG_CLASS (REGNO (SET_DEST (set))))
354 #endif
355 )
356 {
357 rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set)));
358 ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set));
359 validate_change (insn, &SET_DEST (set), wide_dest, 1);
360 }
361 #endif
362
363 validate_unshare_change (insn, &SET_SRC (set), this_rtx, 1);
364 old_cost = this_cost, did_change = 1;
365 }
366 }
367
368 return did_change;
369 }
370
371 /* Try to replace operands in INSN with equivalent values that are already
372 in registers. This can be viewed as optional reloading.
373
374 For each non-register operand in the insn, see if any hard regs are
375 known to be equivalent to that operand. Record the alternatives which
376 can accept these hard registers. Among all alternatives, select the
377 ones which are better or equal to the one currently matching, where
378 "better" is in terms of '?' and '!' constraints. Among the remaining
379 alternatives, select the one which replaces most operands with
380 hard registers. */
381
382 static int
reload_cse_simplify_operands(rtx insn,rtx testreg)383 reload_cse_simplify_operands (rtx insn, rtx testreg)
384 {
385 int i, j;
386
387 /* For each operand, all registers that are equivalent to it. */
388 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
389
390 const char *constraints[MAX_RECOG_OPERANDS];
391
392 /* Vector recording how bad an alternative is. */
393 int *alternative_reject;
394 /* Vector recording how many registers can be introduced by choosing
395 this alternative. */
396 int *alternative_nregs;
397 /* Array of vectors recording, for each operand and each alternative,
398 which hard register to substitute, or -1 if the operand should be
399 left as it is. */
400 int *op_alt_regno[MAX_RECOG_OPERANDS];
401 /* Array of alternatives, sorted in order of decreasing desirability. */
402 int *alternative_order;
403
404 extract_insn (insn);
405
406 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
407 return 0;
408
409 /* Figure out which alternative currently matches. */
410 if (! constrain_operands (1))
411 fatal_insn_not_found (insn);
412
413 alternative_reject = XALLOCAVEC (int, recog_data.n_alternatives);
414 alternative_nregs = XALLOCAVEC (int, recog_data.n_alternatives);
415 alternative_order = XALLOCAVEC (int, recog_data.n_alternatives);
416 memset (alternative_reject, 0, recog_data.n_alternatives * sizeof (int));
417 memset (alternative_nregs, 0, recog_data.n_alternatives * sizeof (int));
418
419 /* For each operand, find out which regs are equivalent. */
420 for (i = 0; i < recog_data.n_operands; i++)
421 {
422 cselib_val *v;
423 struct elt_loc_list *l;
424 rtx op;
425
426 CLEAR_HARD_REG_SET (equiv_regs[i]);
427
428 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
429 right, so avoid the problem here. Likewise if we have a constant
430 and the insn pattern doesn't tell us the mode we need. */
431 if (LABEL_P (recog_data.operand[i])
432 || (CONSTANT_P (recog_data.operand[i])
433 && recog_data.operand_mode[i] == VOIDmode))
434 continue;
435
436 op = recog_data.operand[i];
437 #ifdef LOAD_EXTEND_OP
438 if (MEM_P (op)
439 && GET_MODE_BITSIZE (GET_MODE (op)) < BITS_PER_WORD
440 && LOAD_EXTEND_OP (GET_MODE (op)) != UNKNOWN)
441 {
442 rtx set = single_set (insn);
443
444 /* We might have multiple sets, some of which do implicit
445 extension. Punt on this for now. */
446 if (! set)
447 continue;
448 /* If the destination is also a MEM or a STRICT_LOW_PART, no
449 extension applies.
450 Also, if there is an explicit extension, we don't have to
451 worry about an implicit one. */
452 else if (MEM_P (SET_DEST (set))
453 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART
454 || GET_CODE (SET_SRC (set)) == ZERO_EXTEND
455 || GET_CODE (SET_SRC (set)) == SIGN_EXTEND)
456 ; /* Continue ordinary processing. */
457 #ifdef CANNOT_CHANGE_MODE_CLASS
458 /* If the register cannot change mode to word_mode, it follows that
459 it cannot have been used in word_mode. */
460 else if (REG_P (SET_DEST (set))
461 && CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set)),
462 word_mode,
463 REGNO_REG_CLASS (REGNO (SET_DEST (set)))))
464 ; /* Continue ordinary processing. */
465 #endif
466 /* If this is a straight load, make the extension explicit. */
467 else if (REG_P (SET_DEST (set))
468 && recog_data.n_operands == 2
469 && SET_SRC (set) == op
470 && SET_DEST (set) == recog_data.operand[1-i])
471 {
472 validate_change (insn, recog_data.operand_loc[i],
473 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (op)),
474 word_mode, op),
475 1);
476 validate_change (insn, recog_data.operand_loc[1-i],
477 gen_rtx_REG (word_mode, REGNO (SET_DEST (set))),
478 1);
479 if (! apply_change_group ())
480 return 0;
481 return reload_cse_simplify_operands (insn, testreg);
482 }
483 else
484 /* ??? There might be arithmetic operations with memory that are
485 safe to optimize, but is it worth the trouble? */
486 continue;
487 }
488 #endif /* LOAD_EXTEND_OP */
489 if (side_effects_p (op))
490 continue;
491 v = cselib_lookup (op, recog_data.operand_mode[i], 0, VOIDmode);
492 if (! v)
493 continue;
494
495 for (l = v->locs; l; l = l->next)
496 if (REG_P (l->loc))
497 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
498 }
499
500 for (i = 0; i < recog_data.n_operands; i++)
501 {
502 enum machine_mode mode;
503 int regno;
504 const char *p;
505
506 op_alt_regno[i] = XALLOCAVEC (int, recog_data.n_alternatives);
507 for (j = 0; j < recog_data.n_alternatives; j++)
508 op_alt_regno[i][j] = -1;
509
510 p = constraints[i] = recog_data.constraints[i];
511 mode = recog_data.operand_mode[i];
512
513 /* Add the reject values for each alternative given by the constraints
514 for this operand. */
515 j = 0;
516 while (*p != '\0')
517 {
518 char c = *p++;
519 if (c == ',')
520 j++;
521 else if (c == '?')
522 alternative_reject[j] += 3;
523 else if (c == '!')
524 alternative_reject[j] += 300;
525 }
526
527 /* We won't change operands which are already registers. We
528 also don't want to modify output operands. */
529 regno = true_regnum (recog_data.operand[i]);
530 if (regno >= 0
531 || constraints[i][0] == '='
532 || constraints[i][0] == '+')
533 continue;
534
535 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
536 {
537 enum reg_class rclass = NO_REGS;
538
539 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
540 continue;
541
542 SET_REGNO_RAW (testreg, regno);
543 PUT_MODE (testreg, mode);
544
545 /* We found a register equal to this operand. Now look for all
546 alternatives that can accept this register and have not been
547 assigned a register they can use yet. */
548 j = 0;
549 p = constraints[i];
550 for (;;)
551 {
552 char c = *p;
553
554 switch (c)
555 {
556 case '=': case '+': case '?':
557 case '#': case '&': case '!':
558 case '*': case '%':
559 case '0': case '1': case '2': case '3': case '4':
560 case '5': case '6': case '7': case '8': case '9':
561 case '<': case '>': case 'V': case 'o':
562 case 'E': case 'F': case 'G': case 'H':
563 case 's': case 'i': case 'n':
564 case 'I': case 'J': case 'K': case 'L':
565 case 'M': case 'N': case 'O': case 'P':
566 case 'p': case 'X': case TARGET_MEM_CONSTRAINT:
567 /* These don't say anything we care about. */
568 break;
569
570 case 'g': case 'r':
571 rclass = reg_class_subunion[(int) rclass][(int) GENERAL_REGS];
572 break;
573
574 default:
575 rclass
576 = (reg_class_subunion
577 [(int) rclass]
578 [(int) REG_CLASS_FROM_CONSTRAINT ((unsigned char) c, p)]);
579 break;
580
581 case ',': case '\0':
582 /* See if REGNO fits this alternative, and set it up as the
583 replacement register if we don't have one for this
584 alternative yet and the operand being replaced is not
585 a cheap CONST_INT. */
586 if (op_alt_regno[i][j] == -1
587 && recog_data.alternative_enabled_p[j]
588 && reg_fits_class_p (testreg, rclass, 0, mode)
589 && (!CONST_INT_P (recog_data.operand[i])
590 || (set_src_cost (recog_data.operand[i],
591 optimize_bb_for_speed_p
592 (BLOCK_FOR_INSN (insn)))
593 > set_src_cost (testreg,
594 optimize_bb_for_speed_p
595 (BLOCK_FOR_INSN (insn))))))
596 {
597 alternative_nregs[j]++;
598 op_alt_regno[i][j] = regno;
599 }
600 j++;
601 rclass = NO_REGS;
602 break;
603 }
604 p += CONSTRAINT_LEN (c, p);
605
606 if (c == '\0')
607 break;
608 }
609 }
610 }
611
612 /* Record all alternatives which are better or equal to the currently
613 matching one in the alternative_order array. */
614 for (i = j = 0; i < recog_data.n_alternatives; i++)
615 if (alternative_reject[i] <= alternative_reject[which_alternative])
616 alternative_order[j++] = i;
617 recog_data.n_alternatives = j;
618
619 /* Sort it. Given a small number of alternatives, a dumb algorithm
620 won't hurt too much. */
621 for (i = 0; i < recog_data.n_alternatives - 1; i++)
622 {
623 int best = i;
624 int best_reject = alternative_reject[alternative_order[i]];
625 int best_nregs = alternative_nregs[alternative_order[i]];
626 int tmp;
627
628 for (j = i + 1; j < recog_data.n_alternatives; j++)
629 {
630 int this_reject = alternative_reject[alternative_order[j]];
631 int this_nregs = alternative_nregs[alternative_order[j]];
632
633 if (this_reject < best_reject
634 || (this_reject == best_reject && this_nregs > best_nregs))
635 {
636 best = j;
637 best_reject = this_reject;
638 best_nregs = this_nregs;
639 }
640 }
641
642 tmp = alternative_order[best];
643 alternative_order[best] = alternative_order[i];
644 alternative_order[i] = tmp;
645 }
646
647 /* Substitute the operands as determined by op_alt_regno for the best
648 alternative. */
649 j = alternative_order[0];
650
651 for (i = 0; i < recog_data.n_operands; i++)
652 {
653 enum machine_mode mode = recog_data.operand_mode[i];
654 if (op_alt_regno[i][j] == -1)
655 continue;
656
657 validate_change (insn, recog_data.operand_loc[i],
658 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
659 }
660
661 for (i = recog_data.n_dups - 1; i >= 0; i--)
662 {
663 int op = recog_data.dup_num[i];
664 enum machine_mode mode = recog_data.operand_mode[op];
665
666 if (op_alt_regno[op][j] == -1)
667 continue;
668
669 validate_change (insn, recog_data.dup_loc[i],
670 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
671 }
672
673 return apply_change_group ();
674 }
675
676 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
677 addressing now.
678 This code might also be useful when reload gave up on reg+reg addressing
679 because of clashes between the return register and INDEX_REG_CLASS. */
680
681 /* The maximum number of uses of a register we can keep track of to
682 replace them with reg+reg addressing. */
683 #define RELOAD_COMBINE_MAX_USES 16
684
685 /* Describes a recorded use of a register. */
686 struct reg_use
687 {
688 /* The insn where a register has been used. */
689 rtx insn;
690 /* Points to the memory reference enclosing the use, if any, NULL_RTX
691 otherwise. */
692 rtx containing_mem;
693 /* Location of the register within INSN. */
694 rtx *usep;
695 /* The reverse uid of the insn. */
696 int ruid;
697 };
698
699 /* If the register is used in some unknown fashion, USE_INDEX is negative.
700 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
701 indicates where it is first set or clobbered.
702 Otherwise, USE_INDEX is the index of the last encountered use of the
703 register (which is first among these we have seen since we scan backwards).
704 USE_RUID indicates the first encountered, i.e. last, of these uses.
705 If ALL_OFFSETS_MATCH is true, all encountered uses were inside a PLUS
706 with a constant offset; OFFSET contains this constant in that case.
707 STORE_RUID is always meaningful if we only want to use a value in a
708 register in a different place: it denotes the next insn in the insn
709 stream (i.e. the last encountered) that sets or clobbers the register.
710 REAL_STORE_RUID is similar, but clobbers are ignored when updating it. */
711 static struct
712 {
713 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
714 rtx offset;
715 int use_index;
716 int store_ruid;
717 int real_store_ruid;
718 int use_ruid;
719 bool all_offsets_match;
720 } reg_state[FIRST_PSEUDO_REGISTER];
721
722 /* Reverse linear uid. This is increased in reload_combine while scanning
723 the instructions from last to first. It is used to set last_label_ruid
724 and the store_ruid / use_ruid fields in reg_state. */
725 static int reload_combine_ruid;
726
727 /* The RUID of the last label we encountered in reload_combine. */
728 static int last_label_ruid;
729
730 /* The RUID of the last jump we encountered in reload_combine. */
731 static int last_jump_ruid;
732
733 /* The register numbers of the first and last index register. A value of
734 -1 in LAST_INDEX_REG indicates that we've previously computed these
735 values and found no suitable index registers. */
736 static int first_index_reg = -1;
737 static int last_index_reg;
738
739 #define LABEL_LIVE(LABEL) \
740 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
741
742 /* Subroutine of reload_combine_split_ruids, called to fix up a single
743 ruid pointed to by *PRUID if it is higher than SPLIT_RUID. */
744
745 static inline void
reload_combine_split_one_ruid(int * pruid,int split_ruid)746 reload_combine_split_one_ruid (int *pruid, int split_ruid)
747 {
748 if (*pruid > split_ruid)
749 (*pruid)++;
750 }
751
752 /* Called when we insert a new insn in a position we've already passed in
753 the scan. Examine all our state, increasing all ruids that are higher
754 than SPLIT_RUID by one in order to make room for a new insn. */
755
756 static void
reload_combine_split_ruids(int split_ruid)757 reload_combine_split_ruids (int split_ruid)
758 {
759 unsigned i;
760
761 reload_combine_split_one_ruid (&reload_combine_ruid, split_ruid);
762 reload_combine_split_one_ruid (&last_label_ruid, split_ruid);
763 reload_combine_split_one_ruid (&last_jump_ruid, split_ruid);
764
765 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
766 {
767 int j, idx = reg_state[i].use_index;
768 reload_combine_split_one_ruid (®_state[i].use_ruid, split_ruid);
769 reload_combine_split_one_ruid (®_state[i].store_ruid, split_ruid);
770 reload_combine_split_one_ruid (®_state[i].real_store_ruid,
771 split_ruid);
772 if (idx < 0)
773 continue;
774 for (j = idx; j < RELOAD_COMBINE_MAX_USES; j++)
775 {
776 reload_combine_split_one_ruid (®_state[i].reg_use[j].ruid,
777 split_ruid);
778 }
779 }
780 }
781
782 /* Called when we are about to rescan a previously encountered insn with
783 reload_combine_note_use after modifying some part of it. This clears all
784 information about uses in that particular insn. */
785
786 static void
reload_combine_purge_insn_uses(rtx insn)787 reload_combine_purge_insn_uses (rtx insn)
788 {
789 unsigned i;
790
791 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
792 {
793 int j, k, idx = reg_state[i].use_index;
794 if (idx < 0)
795 continue;
796 j = k = RELOAD_COMBINE_MAX_USES;
797 while (j-- > idx)
798 {
799 if (reg_state[i].reg_use[j].insn != insn)
800 {
801 k--;
802 if (k != j)
803 reg_state[i].reg_use[k] = reg_state[i].reg_use[j];
804 }
805 }
806 reg_state[i].use_index = k;
807 }
808 }
809
810 /* Called when we need to forget about all uses of REGNO after an insn
811 which is identified by RUID. */
812
813 static void
reload_combine_purge_reg_uses_after_ruid(unsigned regno,int ruid)814 reload_combine_purge_reg_uses_after_ruid (unsigned regno, int ruid)
815 {
816 int j, k, idx = reg_state[regno].use_index;
817 if (idx < 0)
818 return;
819 j = k = RELOAD_COMBINE_MAX_USES;
820 while (j-- > idx)
821 {
822 if (reg_state[regno].reg_use[j].ruid >= ruid)
823 {
824 k--;
825 if (k != j)
826 reg_state[regno].reg_use[k] = reg_state[regno].reg_use[j];
827 }
828 }
829 reg_state[regno].use_index = k;
830 }
831
832 /* Find the use of REGNO with the ruid that is highest among those
833 lower than RUID_LIMIT, and return it if it is the only use of this
834 reg in the insn. Return NULL otherwise. */
835
836 static struct reg_use *
reload_combine_closest_single_use(unsigned regno,int ruid_limit)837 reload_combine_closest_single_use (unsigned regno, int ruid_limit)
838 {
839 int i, best_ruid = 0;
840 int use_idx = reg_state[regno].use_index;
841 struct reg_use *retval;
842
843 if (use_idx < 0)
844 return NULL;
845 retval = NULL;
846 for (i = use_idx; i < RELOAD_COMBINE_MAX_USES; i++)
847 {
848 struct reg_use *use = reg_state[regno].reg_use + i;
849 int this_ruid = use->ruid;
850 if (this_ruid >= ruid_limit)
851 continue;
852 if (this_ruid > best_ruid)
853 {
854 best_ruid = this_ruid;
855 retval = use;
856 }
857 else if (this_ruid == best_ruid)
858 retval = NULL;
859 }
860 if (last_label_ruid >= best_ruid)
861 return NULL;
862 return retval;
863 }
864
865 /* After we've moved an add insn, fix up any debug insns that occur
866 between the old location of the add and the new location. REG is
867 the destination register of the add insn; REPLACEMENT is the
868 SET_SRC of the add. FROM and TO specify the range in which we
869 should make this change on debug insns. */
870
871 static void
fixup_debug_insns(rtx reg,rtx replacement,rtx from,rtx to)872 fixup_debug_insns (rtx reg, rtx replacement, rtx from, rtx to)
873 {
874 rtx insn;
875 for (insn = from; insn != to; insn = NEXT_INSN (insn))
876 {
877 rtx t;
878
879 if (!DEBUG_INSN_P (insn))
880 continue;
881
882 t = INSN_VAR_LOCATION_LOC (insn);
883 t = simplify_replace_rtx (t, reg, replacement);
884 validate_change (insn, &INSN_VAR_LOCATION_LOC (insn), t, 0);
885 }
886 }
887
888 /* Subroutine of reload_combine_recognize_const_pattern. Try to replace REG
889 with SRC in the insn described by USE, taking costs into account. Return
890 true if we made the replacement. */
891
892 static bool
try_replace_in_use(struct reg_use * use,rtx reg,rtx src)893 try_replace_in_use (struct reg_use *use, rtx reg, rtx src)
894 {
895 rtx use_insn = use->insn;
896 rtx mem = use->containing_mem;
897 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn));
898
899 if (mem != NULL_RTX)
900 {
901 addr_space_t as = MEM_ADDR_SPACE (mem);
902 rtx oldaddr = XEXP (mem, 0);
903 rtx newaddr = NULL_RTX;
904 int old_cost = address_cost (oldaddr, GET_MODE (mem), as, speed);
905 int new_cost;
906
907 newaddr = simplify_replace_rtx (oldaddr, reg, src);
908 if (memory_address_addr_space_p (GET_MODE (mem), newaddr, as))
909 {
910 XEXP (mem, 0) = newaddr;
911 new_cost = address_cost (newaddr, GET_MODE (mem), as, speed);
912 XEXP (mem, 0) = oldaddr;
913 if (new_cost <= old_cost
914 && validate_change (use_insn,
915 &XEXP (mem, 0), newaddr, 0))
916 return true;
917 }
918 }
919 else
920 {
921 rtx new_set = single_set (use_insn);
922 if (new_set
923 && REG_P (SET_DEST (new_set))
924 && GET_CODE (SET_SRC (new_set)) == PLUS
925 && REG_P (XEXP (SET_SRC (new_set), 0))
926 && CONSTANT_P (XEXP (SET_SRC (new_set), 1)))
927 {
928 rtx new_src;
929 int old_cost = set_src_cost (SET_SRC (new_set), speed);
930
931 gcc_assert (rtx_equal_p (XEXP (SET_SRC (new_set), 0), reg));
932 new_src = simplify_replace_rtx (SET_SRC (new_set), reg, src);
933
934 if (set_src_cost (new_src, speed) <= old_cost
935 && validate_change (use_insn, &SET_SRC (new_set),
936 new_src, 0))
937 return true;
938 }
939 }
940 return false;
941 }
942
943 /* Called by reload_combine when scanning INSN. This function tries to detect
944 patterns where a constant is added to a register, and the result is used
945 in an address.
946 Return true if no further processing is needed on INSN; false if it wasn't
947 recognized and should be handled normally. */
948
949 static bool
reload_combine_recognize_const_pattern(rtx insn)950 reload_combine_recognize_const_pattern (rtx insn)
951 {
952 int from_ruid = reload_combine_ruid;
953 rtx set, pat, reg, src, addreg;
954 unsigned int regno;
955 struct reg_use *use;
956 bool must_move_add;
957 rtx add_moved_after_insn = NULL_RTX;
958 int add_moved_after_ruid = 0;
959 int clobbered_regno = -1;
960
961 set = single_set (insn);
962 if (set == NULL_RTX)
963 return false;
964
965 reg = SET_DEST (set);
966 src = SET_SRC (set);
967 if (!REG_P (reg)
968 || hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] != 1
969 || GET_MODE (reg) != Pmode
970 || reg == stack_pointer_rtx)
971 return false;
972
973 regno = REGNO (reg);
974
975 /* We look for a REG1 = REG2 + CONSTANT insn, followed by either
976 uses of REG1 inside an address, or inside another add insn. If
977 possible and profitable, merge the addition into subsequent
978 uses. */
979 if (GET_CODE (src) != PLUS
980 || !REG_P (XEXP (src, 0))
981 || !CONSTANT_P (XEXP (src, 1)))
982 return false;
983
984 addreg = XEXP (src, 0);
985 must_move_add = rtx_equal_p (reg, addreg);
986
987 pat = PATTERN (insn);
988 if (must_move_add && set != pat)
989 {
990 /* We have to be careful when moving the add; apart from the
991 single_set there may also be clobbers. Recognize one special
992 case, that of one clobber alongside the set (likely a clobber
993 of the CC register). */
994 gcc_assert (GET_CODE (PATTERN (insn)) == PARALLEL);
995 if (XVECLEN (pat, 0) != 2 || XVECEXP (pat, 0, 0) != set
996 || GET_CODE (XVECEXP (pat, 0, 1)) != CLOBBER
997 || !REG_P (XEXP (XVECEXP (pat, 0, 1), 0)))
998 return false;
999 clobbered_regno = REGNO (XEXP (XVECEXP (pat, 0, 1), 0));
1000 }
1001
1002 do
1003 {
1004 use = reload_combine_closest_single_use (regno, from_ruid);
1005
1006 if (use)
1007 /* Start the search for the next use from here. */
1008 from_ruid = use->ruid;
1009
1010 if (use && GET_MODE (*use->usep) == Pmode)
1011 {
1012 bool delete_add = false;
1013 rtx use_insn = use->insn;
1014 int use_ruid = use->ruid;
1015
1016 /* Avoid moving the add insn past a jump. */
1017 if (must_move_add && use_ruid <= last_jump_ruid)
1018 break;
1019
1020 /* If the add clobbers another hard reg in parallel, don't move
1021 it past a real set of this hard reg. */
1022 if (must_move_add && clobbered_regno >= 0
1023 && reg_state[clobbered_regno].real_store_ruid >= use_ruid)
1024 break;
1025
1026 #ifdef HAVE_cc0
1027 /* Do not separate cc0 setter and cc0 user on HAVE_cc0 targets. */
1028 if (must_move_add && sets_cc0_p (PATTERN (use_insn)))
1029 break;
1030 #endif
1031
1032 gcc_assert (reg_state[regno].store_ruid <= use_ruid);
1033 /* Avoid moving a use of ADDREG past a point where it is stored. */
1034 if (reg_state[REGNO (addreg)].store_ruid > use_ruid)
1035 break;
1036
1037 /* We also must not move the addition past an insn that sets
1038 the same register, unless we can combine two add insns. */
1039 if (must_move_add && reg_state[regno].store_ruid == use_ruid)
1040 {
1041 if (use->containing_mem == NULL_RTX)
1042 delete_add = true;
1043 else
1044 break;
1045 }
1046
1047 if (try_replace_in_use (use, reg, src))
1048 {
1049 reload_combine_purge_insn_uses (use_insn);
1050 reload_combine_note_use (&PATTERN (use_insn), use_insn,
1051 use_ruid, NULL_RTX);
1052
1053 if (delete_add)
1054 {
1055 fixup_debug_insns (reg, src, insn, use_insn);
1056 delete_insn (insn);
1057 return true;
1058 }
1059 if (must_move_add)
1060 {
1061 add_moved_after_insn = use_insn;
1062 add_moved_after_ruid = use_ruid;
1063 }
1064 continue;
1065 }
1066 }
1067 /* If we get here, we couldn't handle this use. */
1068 if (must_move_add)
1069 break;
1070 }
1071 while (use);
1072
1073 if (!must_move_add || add_moved_after_insn == NULL_RTX)
1074 /* Process the add normally. */
1075 return false;
1076
1077 fixup_debug_insns (reg, src, insn, add_moved_after_insn);
1078
1079 reorder_insns (insn, insn, add_moved_after_insn);
1080 reload_combine_purge_reg_uses_after_ruid (regno, add_moved_after_ruid);
1081 reload_combine_split_ruids (add_moved_after_ruid - 1);
1082 reload_combine_note_use (&PATTERN (insn), insn,
1083 add_moved_after_ruid, NULL_RTX);
1084 reg_state[regno].store_ruid = add_moved_after_ruid;
1085
1086 return true;
1087 }
1088
1089 /* Called by reload_combine when scanning INSN. Try to detect a pattern we
1090 can handle and improve. Return true if no further processing is needed on
1091 INSN; false if it wasn't recognized and should be handled normally. */
1092
1093 static bool
reload_combine_recognize_pattern(rtx insn)1094 reload_combine_recognize_pattern (rtx insn)
1095 {
1096 rtx set, reg, src;
1097 unsigned int regno;
1098
1099 set = single_set (insn);
1100 if (set == NULL_RTX)
1101 return false;
1102
1103 reg = SET_DEST (set);
1104 src = SET_SRC (set);
1105 if (!REG_P (reg)
1106 || hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] != 1)
1107 return false;
1108
1109 regno = REGNO (reg);
1110
1111 /* Look for (set (REGX) (CONST_INT))
1112 (set (REGX) (PLUS (REGX) (REGY)))
1113 ...
1114 ... (MEM (REGX)) ...
1115 and convert it to
1116 (set (REGZ) (CONST_INT))
1117 ...
1118 ... (MEM (PLUS (REGZ) (REGY)))... .
1119
1120 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
1121 and that we know all uses of REGX before it dies.
1122 Also, explicitly check that REGX != REGY; our life information
1123 does not yet show whether REGY changes in this insn. */
1124
1125 if (GET_CODE (src) == PLUS
1126 && reg_state[regno].all_offsets_match
1127 && last_index_reg != -1
1128 && REG_P (XEXP (src, 1))
1129 && rtx_equal_p (XEXP (src, 0), reg)
1130 && !rtx_equal_p (XEXP (src, 1), reg)
1131 && reg_state[regno].use_index >= 0
1132 && reg_state[regno].use_index < RELOAD_COMBINE_MAX_USES
1133 && last_label_ruid < reg_state[regno].use_ruid)
1134 {
1135 rtx base = XEXP (src, 1);
1136 rtx prev = prev_nonnote_nondebug_insn (insn);
1137 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
1138 rtx index_reg = NULL_RTX;
1139 rtx reg_sum = NULL_RTX;
1140 int i;
1141
1142 /* Now we need to set INDEX_REG to an index register (denoted as
1143 REGZ in the illustration above) and REG_SUM to the expression
1144 register+register that we want to use to substitute uses of REG
1145 (typically in MEMs) with. First check REG and BASE for being
1146 index registers; we can use them even if they are not dead. */
1147 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
1148 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
1149 REGNO (base)))
1150 {
1151 index_reg = reg;
1152 reg_sum = src;
1153 }
1154 else
1155 {
1156 /* Otherwise, look for a free index register. Since we have
1157 checked above that neither REG nor BASE are index registers,
1158 if we find anything at all, it will be different from these
1159 two registers. */
1160 for (i = first_index_reg; i <= last_index_reg; i++)
1161 {
1162 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i)
1163 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
1164 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
1165 && (call_used_regs[i] || df_regs_ever_live_p (i))
1166 && (!frame_pointer_needed || i != HARD_FRAME_POINTER_REGNUM)
1167 && !fixed_regs[i] && !global_regs[i]
1168 && hard_regno_nregs[i][GET_MODE (reg)] == 1
1169 && targetm.hard_regno_scratch_ok (i))
1170 {
1171 index_reg = gen_rtx_REG (GET_MODE (reg), i);
1172 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
1173 break;
1174 }
1175 }
1176 }
1177
1178 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
1179 (REGY), i.e. BASE, is not clobbered before the last use we'll
1180 create. */
1181 if (reg_sum
1182 && prev_set
1183 && CONST_INT_P (SET_SRC (prev_set))
1184 && rtx_equal_p (SET_DEST (prev_set), reg)
1185 && (reg_state[REGNO (base)].store_ruid
1186 <= reg_state[regno].use_ruid))
1187 {
1188 /* Change destination register and, if necessary, the constant
1189 value in PREV, the constant loading instruction. */
1190 validate_change (prev, &SET_DEST (prev_set), index_reg, 1);
1191 if (reg_state[regno].offset != const0_rtx)
1192 validate_change (prev,
1193 &SET_SRC (prev_set),
1194 GEN_INT (INTVAL (SET_SRC (prev_set))
1195 + INTVAL (reg_state[regno].offset)),
1196 1);
1197
1198 /* Now for every use of REG that we have recorded, replace REG
1199 with REG_SUM. */
1200 for (i = reg_state[regno].use_index;
1201 i < RELOAD_COMBINE_MAX_USES; i++)
1202 validate_unshare_change (reg_state[regno].reg_use[i].insn,
1203 reg_state[regno].reg_use[i].usep,
1204 /* Each change must have its own
1205 replacement. */
1206 reg_sum, 1);
1207
1208 if (apply_change_group ())
1209 {
1210 struct reg_use *lowest_ruid = NULL;
1211
1212 /* For every new use of REG_SUM, we have to record the use
1213 of BASE therein, i.e. operand 1. */
1214 for (i = reg_state[regno].use_index;
1215 i < RELOAD_COMBINE_MAX_USES; i++)
1216 {
1217 struct reg_use *use = reg_state[regno].reg_use + i;
1218 reload_combine_note_use (&XEXP (*use->usep, 1), use->insn,
1219 use->ruid, use->containing_mem);
1220 if (lowest_ruid == NULL || use->ruid < lowest_ruid->ruid)
1221 lowest_ruid = use;
1222 }
1223
1224 fixup_debug_insns (reg, reg_sum, insn, lowest_ruid->insn);
1225
1226 /* Delete the reg-reg addition. */
1227 delete_insn (insn);
1228
1229 if (reg_state[regno].offset != const0_rtx)
1230 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
1231 are now invalid. */
1232 remove_reg_equal_equiv_notes (prev);
1233
1234 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
1235 return true;
1236 }
1237 }
1238 }
1239 return false;
1240 }
1241
1242 static void
reload_combine(void)1243 reload_combine (void)
1244 {
1245 rtx insn, prev;
1246 basic_block bb;
1247 unsigned int r;
1248 int min_labelno, n_labels;
1249 HARD_REG_SET ever_live_at_start, *label_live;
1250
1251 /* To avoid wasting too much time later searching for an index register,
1252 determine the minimum and maximum index register numbers. */
1253 if (INDEX_REG_CLASS == NO_REGS)
1254 last_index_reg = -1;
1255 else if (first_index_reg == -1 && last_index_reg == 0)
1256 {
1257 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
1258 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
1259 {
1260 if (first_index_reg == -1)
1261 first_index_reg = r;
1262
1263 last_index_reg = r;
1264 }
1265
1266 /* If no index register is available, we can quit now. Set LAST_INDEX_REG
1267 to -1 so we'll know to quit early the next time we get here. */
1268 if (first_index_reg == -1)
1269 {
1270 last_index_reg = -1;
1271 return;
1272 }
1273 }
1274
1275 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
1276 information is a bit fuzzy immediately after reload, but it's
1277 still good enough to determine which registers are live at a jump
1278 destination. */
1279 min_labelno = get_first_label_num ();
1280 n_labels = max_label_num () - min_labelno;
1281 label_live = XNEWVEC (HARD_REG_SET, n_labels);
1282 CLEAR_HARD_REG_SET (ever_live_at_start);
1283
1284 FOR_EACH_BB_REVERSE (bb)
1285 {
1286 insn = BB_HEAD (bb);
1287 if (LABEL_P (insn))
1288 {
1289 HARD_REG_SET live;
1290 bitmap live_in = df_get_live_in (bb);
1291
1292 REG_SET_TO_HARD_REG_SET (live, live_in);
1293 compute_use_by_pseudos (&live, live_in);
1294 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
1295 IOR_HARD_REG_SET (ever_live_at_start, live);
1296 }
1297 }
1298
1299 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
1300 last_label_ruid = last_jump_ruid = reload_combine_ruid = 0;
1301 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
1302 {
1303 reg_state[r].store_ruid = 0;
1304 reg_state[r].real_store_ruid = 0;
1305 if (fixed_regs[r])
1306 reg_state[r].use_index = -1;
1307 else
1308 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
1309 }
1310
1311 for (insn = get_last_insn (); insn; insn = prev)
1312 {
1313 bool control_flow_insn;
1314 rtx note;
1315
1316 prev = PREV_INSN (insn);
1317
1318 /* We cannot do our optimization across labels. Invalidating all the use
1319 information we have would be costly, so we just note where the label
1320 is and then later disable any optimization that would cross it. */
1321 if (LABEL_P (insn))
1322 last_label_ruid = reload_combine_ruid;
1323 else if (BARRIER_P (insn))
1324 {
1325 /* Crossing a barrier resets all the use information. */
1326 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
1327 if (! fixed_regs[r])
1328 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
1329 }
1330 else if (INSN_P (insn) && volatile_insn_p (PATTERN (insn)))
1331 /* Optimizations across insns being marked as volatile must be
1332 prevented. All the usage information is invalidated
1333 here. */
1334 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
1335 if (! fixed_regs[r]
1336 && reg_state[r].use_index != RELOAD_COMBINE_MAX_USES)
1337 reg_state[r].use_index = -1;
1338
1339 if (! NONDEBUG_INSN_P (insn))
1340 continue;
1341
1342 reload_combine_ruid++;
1343
1344 control_flow_insn = control_flow_insn_p (insn);
1345 if (control_flow_insn)
1346 last_jump_ruid = reload_combine_ruid;
1347
1348 if (reload_combine_recognize_const_pattern (insn)
1349 || reload_combine_recognize_pattern (insn))
1350 continue;
1351
1352 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
1353
1354 if (CALL_P (insn))
1355 {
1356 rtx link;
1357
1358 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
1359 if (call_used_regs[r])
1360 {
1361 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
1362 reg_state[r].store_ruid = reload_combine_ruid;
1363 }
1364
1365 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
1366 link = XEXP (link, 1))
1367 {
1368 rtx setuse = XEXP (link, 0);
1369 rtx usage_rtx = XEXP (setuse, 0);
1370 if ((GET_CODE (setuse) == USE || GET_CODE (setuse) == CLOBBER)
1371 && REG_P (usage_rtx))
1372 {
1373 unsigned int i;
1374 unsigned int start_reg = REGNO (usage_rtx);
1375 unsigned int num_regs
1376 = hard_regno_nregs[start_reg][GET_MODE (usage_rtx)];
1377 unsigned int end_reg = start_reg + num_regs - 1;
1378 for (i = start_reg; i <= end_reg; i++)
1379 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
1380 {
1381 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
1382 reg_state[i].store_ruid = reload_combine_ruid;
1383 }
1384 else
1385 reg_state[i].use_index = -1;
1386 }
1387 }
1388 }
1389
1390 if (control_flow_insn && GET_CODE (PATTERN (insn)) != RETURN)
1391 {
1392 /* Non-spill registers might be used at the call destination in
1393 some unknown fashion, so we have to mark the unknown use. */
1394 HARD_REG_SET *live;
1395
1396 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
1397 && JUMP_LABEL (insn))
1398 live = &LABEL_LIVE (JUMP_LABEL (insn));
1399 else
1400 live = &ever_live_at_start;
1401
1402 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
1403 if (TEST_HARD_REG_BIT (*live, r))
1404 reg_state[r].use_index = -1;
1405 }
1406
1407 reload_combine_note_use (&PATTERN (insn), insn, reload_combine_ruid,
1408 NULL_RTX);
1409
1410 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
1411 {
1412 if (REG_NOTE_KIND (note) == REG_INC && REG_P (XEXP (note, 0)))
1413 {
1414 int regno = REGNO (XEXP (note, 0));
1415 reg_state[regno].store_ruid = reload_combine_ruid;
1416 reg_state[regno].real_store_ruid = reload_combine_ruid;
1417 reg_state[regno].use_index = -1;
1418 }
1419 }
1420 }
1421
1422 free (label_live);
1423 }
1424
1425 /* Check if DST is a register or a subreg of a register; if it is,
1426 update store_ruid, real_store_ruid and use_index in the reg_state
1427 structure accordingly. Called via note_stores from reload_combine. */
1428
1429 static void
reload_combine_note_store(rtx dst,const_rtx set,void * data ATTRIBUTE_UNUSED)1430 reload_combine_note_store (rtx dst, const_rtx set, void *data ATTRIBUTE_UNUSED)
1431 {
1432 int regno = 0;
1433 int i;
1434 enum machine_mode mode = GET_MODE (dst);
1435
1436 if (GET_CODE (dst) == SUBREG)
1437 {
1438 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
1439 GET_MODE (SUBREG_REG (dst)),
1440 SUBREG_BYTE (dst),
1441 GET_MODE (dst));
1442 dst = SUBREG_REG (dst);
1443 }
1444
1445 /* Some targets do argument pushes without adding REG_INC notes. */
1446
1447 if (MEM_P (dst))
1448 {
1449 dst = XEXP (dst, 0);
1450 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC
1451 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC
1452 || GET_CODE (dst) == PRE_MODIFY || GET_CODE (dst) == POST_MODIFY)
1453 {
1454 regno = REGNO (XEXP (dst, 0));
1455 mode = GET_MODE (XEXP (dst, 0));
1456 for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--)
1457 {
1458 /* We could probably do better, but for now mark the register
1459 as used in an unknown fashion and set/clobbered at this
1460 insn. */
1461 reg_state[i].use_index = -1;
1462 reg_state[i].store_ruid = reload_combine_ruid;
1463 reg_state[i].real_store_ruid = reload_combine_ruid;
1464 }
1465 }
1466 else
1467 return;
1468 }
1469
1470 if (!REG_P (dst))
1471 return;
1472 regno += REGNO (dst);
1473
1474 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
1475 careful with registers / register parts that are not full words.
1476 Similarly for ZERO_EXTRACT. */
1477 if (GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
1478 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
1479 {
1480 for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--)
1481 {
1482 reg_state[i].use_index = -1;
1483 reg_state[i].store_ruid = reload_combine_ruid;
1484 reg_state[i].real_store_ruid = reload_combine_ruid;
1485 }
1486 }
1487 else
1488 {
1489 for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--)
1490 {
1491 reg_state[i].store_ruid = reload_combine_ruid;
1492 if (GET_CODE (set) == SET)
1493 reg_state[i].real_store_ruid = reload_combine_ruid;
1494 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
1495 }
1496 }
1497 }
1498
1499 /* XP points to a piece of rtl that has to be checked for any uses of
1500 registers.
1501 *XP is the pattern of INSN, or a part of it.
1502 Called from reload_combine, and recursively by itself. */
1503 static void
reload_combine_note_use(rtx * xp,rtx insn,int ruid,rtx containing_mem)1504 reload_combine_note_use (rtx *xp, rtx insn, int ruid, rtx containing_mem)
1505 {
1506 rtx x = *xp;
1507 enum rtx_code code = x->code;
1508 const char *fmt;
1509 int i, j;
1510 rtx offset = const0_rtx; /* For the REG case below. */
1511
1512 switch (code)
1513 {
1514 case SET:
1515 if (REG_P (SET_DEST (x)))
1516 {
1517 reload_combine_note_use (&SET_SRC (x), insn, ruid, NULL_RTX);
1518 return;
1519 }
1520 break;
1521
1522 case USE:
1523 /* If this is the USE of a return value, we can't change it. */
1524 if (REG_P (XEXP (x, 0)) && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
1525 {
1526 /* Mark the return register as used in an unknown fashion. */
1527 rtx reg = XEXP (x, 0);
1528 int regno = REGNO (reg);
1529 int nregs = hard_regno_nregs[regno][GET_MODE (reg)];
1530
1531 while (--nregs >= 0)
1532 reg_state[regno + nregs].use_index = -1;
1533 return;
1534 }
1535 break;
1536
1537 case CLOBBER:
1538 if (REG_P (SET_DEST (x)))
1539 {
1540 /* No spurious CLOBBERs of pseudo registers may remain. */
1541 gcc_assert (REGNO (SET_DEST (x)) < FIRST_PSEUDO_REGISTER);
1542 return;
1543 }
1544 break;
1545
1546 case PLUS:
1547 /* We are interested in (plus (reg) (const_int)) . */
1548 if (!REG_P (XEXP (x, 0))
1549 || !CONST_INT_P (XEXP (x, 1)))
1550 break;
1551 offset = XEXP (x, 1);
1552 x = XEXP (x, 0);
1553 /* Fall through. */
1554 case REG:
1555 {
1556 int regno = REGNO (x);
1557 int use_index;
1558 int nregs;
1559
1560 /* No spurious USEs of pseudo registers may remain. */
1561 gcc_assert (regno < FIRST_PSEUDO_REGISTER);
1562
1563 nregs = hard_regno_nregs[regno][GET_MODE (x)];
1564
1565 /* We can't substitute into multi-hard-reg uses. */
1566 if (nregs > 1)
1567 {
1568 while (--nregs >= 0)
1569 reg_state[regno + nregs].use_index = -1;
1570 return;
1571 }
1572
1573 /* We may be called to update uses in previously seen insns.
1574 Don't add uses beyond the last store we saw. */
1575 if (ruid < reg_state[regno].store_ruid)
1576 return;
1577
1578 /* If this register is already used in some unknown fashion, we
1579 can't do anything.
1580 If we decrement the index from zero to -1, we can't store more
1581 uses, so this register becomes used in an unknown fashion. */
1582 use_index = --reg_state[regno].use_index;
1583 if (use_index < 0)
1584 return;
1585
1586 if (use_index == RELOAD_COMBINE_MAX_USES - 1)
1587 {
1588 /* This is the first use of this register we have seen since we
1589 marked it as dead. */
1590 reg_state[regno].offset = offset;
1591 reg_state[regno].all_offsets_match = true;
1592 reg_state[regno].use_ruid = ruid;
1593 }
1594 else
1595 {
1596 if (reg_state[regno].use_ruid > ruid)
1597 reg_state[regno].use_ruid = ruid;
1598
1599 if (! rtx_equal_p (offset, reg_state[regno].offset))
1600 reg_state[regno].all_offsets_match = false;
1601 }
1602
1603 reg_state[regno].reg_use[use_index].insn = insn;
1604 reg_state[regno].reg_use[use_index].ruid = ruid;
1605 reg_state[regno].reg_use[use_index].containing_mem = containing_mem;
1606 reg_state[regno].reg_use[use_index].usep = xp;
1607 return;
1608 }
1609
1610 case MEM:
1611 containing_mem = x;
1612 break;
1613
1614 default:
1615 break;
1616 }
1617
1618 /* Recursively process the components of X. */
1619 fmt = GET_RTX_FORMAT (code);
1620 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1621 {
1622 if (fmt[i] == 'e')
1623 reload_combine_note_use (&XEXP (x, i), insn, ruid, containing_mem);
1624 else if (fmt[i] == 'E')
1625 {
1626 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1627 reload_combine_note_use (&XVECEXP (x, i, j), insn, ruid,
1628 containing_mem);
1629 }
1630 }
1631 }
1632
1633 /* See if we can reduce the cost of a constant by replacing a move
1634 with an add. We track situations in which a register is set to a
1635 constant or to a register plus a constant. */
1636 /* We cannot do our optimization across labels. Invalidating all the
1637 information about register contents we have would be costly, so we
1638 use move2add_last_label_luid to note where the label is and then
1639 later disable any optimization that would cross it.
1640 reg_offset[n] / reg_base_reg[n] / reg_symbol_ref[n] / reg_mode[n]
1641 are only valid if reg_set_luid[n] is greater than
1642 move2add_last_label_luid. */
1643 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
1644
1645 /* If reg_base_reg[n] is negative, register n has been set to
1646 reg_offset[n] or reg_symbol_ref[n] + reg_offset[n] in mode reg_mode[n].
1647 If reg_base_reg[n] is non-negative, register n has been set to the
1648 sum of reg_offset[n] and the value of register reg_base_reg[n]
1649 before reg_set_luid[n], calculated in mode reg_mode[n] . */
1650 static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER];
1651 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
1652 static rtx reg_symbol_ref[FIRST_PSEUDO_REGISTER];
1653 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
1654
1655 /* move2add_luid is linearly increased while scanning the instructions
1656 from first to last. It is used to set reg_set_luid in
1657 reload_cse_move2add and move2add_note_store. */
1658 static int move2add_luid;
1659
1660 /* move2add_last_label_luid is set whenever a label is found. Labels
1661 invalidate all previously collected reg_offset data. */
1662 static int move2add_last_label_luid;
1663
1664 /* ??? We don't know how zero / sign extension is handled, hence we
1665 can't go from a narrower to a wider mode. */
1666 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
1667 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
1668 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
1669 && TRULY_NOOP_TRUNCATION_MODES_P (OUTMODE, INMODE)))
1670
1671 /* This function is called with INSN that sets REG to (SYM + OFF),
1672 while REG is known to already have value (SYM + offset).
1673 This function tries to change INSN into an add instruction
1674 (set (REG) (plus (REG) (OFF - offset))) using the known value.
1675 It also updates the information about REG's known value.
1676 Return true if we made a change. */
1677
1678 static bool
move2add_use_add2_insn(rtx reg,rtx sym,rtx off,rtx insn)1679 move2add_use_add2_insn (rtx reg, rtx sym, rtx off, rtx insn)
1680 {
1681 rtx pat = PATTERN (insn);
1682 rtx src = SET_SRC (pat);
1683 int regno = REGNO (reg);
1684 rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[regno],
1685 GET_MODE (reg));
1686 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
1687 bool changed = false;
1688
1689 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
1690 use (set (reg) (reg)) instead.
1691 We don't delete this insn, nor do we convert it into a
1692 note, to avoid losing register notes or the return
1693 value flag. jump2 already knows how to get rid of
1694 no-op moves. */
1695 if (new_src == const0_rtx)
1696 {
1697 /* If the constants are different, this is a
1698 truncation, that, if turned into (set (reg)
1699 (reg)), would be discarded. Maybe we should
1700 try a truncMN pattern? */
1701 if (INTVAL (off) == reg_offset [regno])
1702 changed = validate_change (insn, &SET_SRC (pat), reg, 0);
1703 }
1704 else
1705 {
1706 struct full_rtx_costs oldcst, newcst;
1707 rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src);
1708
1709 get_full_set_rtx_cost (pat, &oldcst);
1710 SET_SRC (pat) = tem;
1711 get_full_set_rtx_cost (pat, &newcst);
1712 SET_SRC (pat) = src;
1713
1714 if (costs_lt_p (&newcst, &oldcst, speed)
1715 && have_add2_insn (reg, new_src))
1716 changed = validate_change (insn, &SET_SRC (pat), tem, 0);
1717 else if (sym == NULL_RTX && GET_MODE (reg) != BImode)
1718 {
1719 enum machine_mode narrow_mode;
1720 for (narrow_mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
1721 narrow_mode != VOIDmode
1722 && narrow_mode != GET_MODE (reg);
1723 narrow_mode = GET_MODE_WIDER_MODE (narrow_mode))
1724 {
1725 if (have_insn_for (STRICT_LOW_PART, narrow_mode)
1726 && ((reg_offset[regno] & ~GET_MODE_MASK (narrow_mode))
1727 == (INTVAL (off) & ~GET_MODE_MASK (narrow_mode))))
1728 {
1729 rtx narrow_reg = gen_rtx_REG (narrow_mode,
1730 REGNO (reg));
1731 rtx narrow_src = gen_int_mode (INTVAL (off),
1732 narrow_mode);
1733 rtx new_set
1734 = gen_rtx_SET (VOIDmode,
1735 gen_rtx_STRICT_LOW_PART (VOIDmode,
1736 narrow_reg),
1737 narrow_src);
1738 changed = validate_change (insn, &PATTERN (insn),
1739 new_set, 0);
1740 if (changed)
1741 break;
1742 }
1743 }
1744 }
1745 }
1746 reg_set_luid[regno] = move2add_luid;
1747 reg_base_reg[regno] = -1;
1748 reg_mode[regno] = GET_MODE (reg);
1749 reg_symbol_ref[regno] = sym;
1750 reg_offset[regno] = INTVAL (off);
1751 return changed;
1752 }
1753
1754
1755 /* This function is called with INSN that sets REG to (SYM + OFF),
1756 but REG doesn't have known value (SYM + offset). This function
1757 tries to find another register which is known to already have
1758 value (SYM + offset) and change INSN into an add instruction
1759 (set (REG) (plus (the found register) (OFF - offset))) if such
1760 a register is found. It also updates the information about
1761 REG's known value.
1762 Return true iff we made a change. */
1763
1764 static bool
move2add_use_add3_insn(rtx reg,rtx sym,rtx off,rtx insn)1765 move2add_use_add3_insn (rtx reg, rtx sym, rtx off, rtx insn)
1766 {
1767 rtx pat = PATTERN (insn);
1768 rtx src = SET_SRC (pat);
1769 int regno = REGNO (reg);
1770 int min_regno = 0;
1771 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
1772 int i;
1773 bool changed = false;
1774 struct full_rtx_costs oldcst, newcst, mincst;
1775 rtx plus_expr;
1776
1777 init_costs_to_max (&mincst);
1778 get_full_set_rtx_cost (pat, &oldcst);
1779
1780 plus_expr = gen_rtx_PLUS (GET_MODE (reg), reg, const0_rtx);
1781 SET_SRC (pat) = plus_expr;
1782
1783 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1784 if (reg_set_luid[i] > move2add_last_label_luid
1785 && reg_mode[i] == GET_MODE (reg)
1786 && reg_base_reg[i] < 0
1787 && reg_symbol_ref[i] != NULL_RTX
1788 && rtx_equal_p (sym, reg_symbol_ref[i]))
1789 {
1790 rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[i],
1791 GET_MODE (reg));
1792 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
1793 use (set (reg) (reg)) instead.
1794 We don't delete this insn, nor do we convert it into a
1795 note, to avoid losing register notes or the return
1796 value flag. jump2 already knows how to get rid of
1797 no-op moves. */
1798 if (new_src == const0_rtx)
1799 {
1800 init_costs_to_zero (&mincst);
1801 min_regno = i;
1802 break;
1803 }
1804 else
1805 {
1806 XEXP (plus_expr, 1) = new_src;
1807 get_full_set_rtx_cost (pat, &newcst);
1808
1809 if (costs_lt_p (&newcst, &mincst, speed))
1810 {
1811 mincst = newcst;
1812 min_regno = i;
1813 }
1814 }
1815 }
1816 SET_SRC (pat) = src;
1817
1818 if (costs_lt_p (&mincst, &oldcst, speed))
1819 {
1820 rtx tem;
1821
1822 tem = gen_rtx_REG (GET_MODE (reg), min_regno);
1823 if (i != min_regno)
1824 {
1825 rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[min_regno],
1826 GET_MODE (reg));
1827 tem = gen_rtx_PLUS (GET_MODE (reg), tem, new_src);
1828 }
1829 if (validate_change (insn, &SET_SRC (pat), tem, 0))
1830 changed = true;
1831 }
1832 reg_set_luid[regno] = move2add_luid;
1833 reg_base_reg[regno] = -1;
1834 reg_mode[regno] = GET_MODE (reg);
1835 reg_symbol_ref[regno] = sym;
1836 reg_offset[regno] = INTVAL (off);
1837 return changed;
1838 }
1839
1840 /* Convert move insns with constant inputs to additions if they are cheaper.
1841 Return true if any changes were made. */
1842 static bool
reload_cse_move2add(rtx first)1843 reload_cse_move2add (rtx first)
1844 {
1845 int i;
1846 rtx insn;
1847 bool changed = false;
1848
1849 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
1850 {
1851 reg_set_luid[i] = 0;
1852 reg_offset[i] = 0;
1853 reg_base_reg[i] = 0;
1854 reg_symbol_ref[i] = NULL_RTX;
1855 reg_mode[i] = VOIDmode;
1856 }
1857
1858 move2add_last_label_luid = 0;
1859 move2add_luid = 2;
1860 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
1861 {
1862 rtx pat, note;
1863
1864 if (LABEL_P (insn))
1865 {
1866 move2add_last_label_luid = move2add_luid;
1867 /* We're going to increment move2add_luid twice after a
1868 label, so that we can use move2add_last_label_luid + 1 as
1869 the luid for constants. */
1870 move2add_luid++;
1871 continue;
1872 }
1873 if (! INSN_P (insn))
1874 continue;
1875 pat = PATTERN (insn);
1876 /* For simplicity, we only perform this optimization on
1877 straightforward SETs. */
1878 if (GET_CODE (pat) == SET
1879 && REG_P (SET_DEST (pat)))
1880 {
1881 rtx reg = SET_DEST (pat);
1882 int regno = REGNO (reg);
1883 rtx src = SET_SRC (pat);
1884
1885 /* Check if we have valid information on the contents of this
1886 register in the mode of REG. */
1887 if (reg_set_luid[regno] > move2add_last_label_luid
1888 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno])
1889 && dbg_cnt (cse2_move2add))
1890 {
1891 /* Try to transform (set (REGX) (CONST_INT A))
1892 ...
1893 (set (REGX) (CONST_INT B))
1894 to
1895 (set (REGX) (CONST_INT A))
1896 ...
1897 (set (REGX) (plus (REGX) (CONST_INT B-A)))
1898 or
1899 (set (REGX) (CONST_INT A))
1900 ...
1901 (set (STRICT_LOW_PART (REGX)) (CONST_INT B))
1902 */
1903
1904 if (CONST_INT_P (src)
1905 && reg_base_reg[regno] < 0
1906 && reg_symbol_ref[regno] == NULL_RTX)
1907 {
1908 changed |= move2add_use_add2_insn (reg, NULL_RTX, src, insn);
1909 continue;
1910 }
1911
1912 /* Try to transform (set (REGX) (REGY))
1913 (set (REGX) (PLUS (REGX) (CONST_INT A)))
1914 ...
1915 (set (REGX) (REGY))
1916 (set (REGX) (PLUS (REGX) (CONST_INT B)))
1917 to
1918 (set (REGX) (REGY))
1919 (set (REGX) (PLUS (REGX) (CONST_INT A)))
1920 ...
1921 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
1922 else if (REG_P (src)
1923 && reg_set_luid[regno] == reg_set_luid[REGNO (src)]
1924 && reg_base_reg[regno] == reg_base_reg[REGNO (src)]
1925 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg),
1926 reg_mode[REGNO (src)]))
1927 {
1928 rtx next = next_nonnote_nondebug_insn (insn);
1929 rtx set = NULL_RTX;
1930 if (next)
1931 set = single_set (next);
1932 if (set
1933 && SET_DEST (set) == reg
1934 && GET_CODE (SET_SRC (set)) == PLUS
1935 && XEXP (SET_SRC (set), 0) == reg
1936 && CONST_INT_P (XEXP (SET_SRC (set), 1)))
1937 {
1938 rtx src3 = XEXP (SET_SRC (set), 1);
1939 HOST_WIDE_INT added_offset = INTVAL (src3);
1940 HOST_WIDE_INT base_offset = reg_offset[REGNO (src)];
1941 HOST_WIDE_INT regno_offset = reg_offset[regno];
1942 rtx new_src =
1943 gen_int_mode (added_offset
1944 + base_offset
1945 - regno_offset,
1946 GET_MODE (reg));
1947 bool success = false;
1948 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
1949
1950 if (new_src == const0_rtx)
1951 /* See above why we create (set (reg) (reg)) here. */
1952 success
1953 = validate_change (next, &SET_SRC (set), reg, 0);
1954 else
1955 {
1956 rtx old_src = SET_SRC (set);
1957 struct full_rtx_costs oldcst, newcst;
1958 rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src);
1959
1960 get_full_set_rtx_cost (set, &oldcst);
1961 SET_SRC (set) = tem;
1962 get_full_set_src_cost (tem, &newcst);
1963 SET_SRC (set) = old_src;
1964 costs_add_n_insns (&oldcst, 1);
1965
1966 if (costs_lt_p (&newcst, &oldcst, speed)
1967 && have_add2_insn (reg, new_src))
1968 {
1969 rtx newpat = gen_rtx_SET (VOIDmode, reg, tem);
1970 success
1971 = validate_change (next, &PATTERN (next),
1972 newpat, 0);
1973 }
1974 }
1975 if (success)
1976 delete_insn (insn);
1977 changed |= success;
1978 insn = next;
1979 reg_mode[regno] = GET_MODE (reg);
1980 reg_offset[regno] =
1981 trunc_int_for_mode (added_offset + base_offset,
1982 GET_MODE (reg));
1983 continue;
1984 }
1985 }
1986 }
1987
1988 /* Try to transform
1989 (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
1990 ...
1991 (set (REGY) (CONST (PLUS (SYMBOL_REF) (CONST_INT B))))
1992 to
1993 (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
1994 ...
1995 (set (REGY) (CONST (PLUS (REGX) (CONST_INT B-A)))) */
1996 if ((GET_CODE (src) == SYMBOL_REF
1997 || (GET_CODE (src) == CONST
1998 && GET_CODE (XEXP (src, 0)) == PLUS
1999 && GET_CODE (XEXP (XEXP (src, 0), 0)) == SYMBOL_REF
2000 && CONST_INT_P (XEXP (XEXP (src, 0), 1))))
2001 && dbg_cnt (cse2_move2add))
2002 {
2003 rtx sym, off;
2004
2005 if (GET_CODE (src) == SYMBOL_REF)
2006 {
2007 sym = src;
2008 off = const0_rtx;
2009 }
2010 else
2011 {
2012 sym = XEXP (XEXP (src, 0), 0);
2013 off = XEXP (XEXP (src, 0), 1);
2014 }
2015
2016 /* If the reg already contains the value which is sum of
2017 sym and some constant value, we can use an add2 insn. */
2018 if (reg_set_luid[regno] > move2add_last_label_luid
2019 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno])
2020 && reg_base_reg[regno] < 0
2021 && reg_symbol_ref[regno] != NULL_RTX
2022 && rtx_equal_p (sym, reg_symbol_ref[regno]))
2023 changed |= move2add_use_add2_insn (reg, sym, off, insn);
2024
2025 /* Otherwise, we have to find a register whose value is sum
2026 of sym and some constant value. */
2027 else
2028 changed |= move2add_use_add3_insn (reg, sym, off, insn);
2029
2030 continue;
2031 }
2032 }
2033
2034 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
2035 {
2036 if (REG_NOTE_KIND (note) == REG_INC
2037 && REG_P (XEXP (note, 0)))
2038 {
2039 /* Reset the information about this register. */
2040 int regno = REGNO (XEXP (note, 0));
2041 if (regno < FIRST_PSEUDO_REGISTER)
2042 reg_set_luid[regno] = 0;
2043 }
2044 }
2045 note_stores (PATTERN (insn), move2add_note_store, insn);
2046
2047 /* If INSN is a conditional branch, we try to extract an
2048 implicit set out of it. */
2049 if (any_condjump_p (insn))
2050 {
2051 rtx cnd = fis_get_condition (insn);
2052
2053 if (cnd != NULL_RTX
2054 && GET_CODE (cnd) == NE
2055 && REG_P (XEXP (cnd, 0))
2056 && !reg_set_p (XEXP (cnd, 0), insn)
2057 /* The following two checks, which are also in
2058 move2add_note_store, are intended to reduce the
2059 number of calls to gen_rtx_SET to avoid memory
2060 allocation if possible. */
2061 && SCALAR_INT_MODE_P (GET_MODE (XEXP (cnd, 0)))
2062 && hard_regno_nregs[REGNO (XEXP (cnd, 0))][GET_MODE (XEXP (cnd, 0))] == 1
2063 && CONST_INT_P (XEXP (cnd, 1)))
2064 {
2065 rtx implicit_set =
2066 gen_rtx_SET (VOIDmode, XEXP (cnd, 0), XEXP (cnd, 1));
2067 move2add_note_store (SET_DEST (implicit_set), implicit_set, insn);
2068 }
2069 }
2070
2071 /* If this is a CALL_INSN, all call used registers are stored with
2072 unknown values. */
2073 if (CALL_P (insn))
2074 {
2075 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
2076 {
2077 if (call_used_regs[i])
2078 /* Reset the information about this register. */
2079 reg_set_luid[i] = 0;
2080 }
2081 }
2082 }
2083 return changed;
2084 }
2085
2086 /* SET is a SET or CLOBBER that sets DST. DATA is the insn which
2087 contains SET.
2088 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
2089 Called from reload_cse_move2add via note_stores. */
2090
2091 static void
move2add_note_store(rtx dst,const_rtx set,void * data)2092 move2add_note_store (rtx dst, const_rtx set, void *data)
2093 {
2094 rtx insn = (rtx) data;
2095 unsigned int regno = 0;
2096 unsigned int nregs = 0;
2097 unsigned int i;
2098 enum machine_mode mode = GET_MODE (dst);
2099
2100 if (GET_CODE (dst) == SUBREG)
2101 {
2102 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
2103 GET_MODE (SUBREG_REG (dst)),
2104 SUBREG_BYTE (dst),
2105 GET_MODE (dst));
2106 nregs = subreg_nregs (dst);
2107 dst = SUBREG_REG (dst);
2108 }
2109
2110 /* Some targets do argument pushes without adding REG_INC notes. */
2111
2112 if (MEM_P (dst))
2113 {
2114 dst = XEXP (dst, 0);
2115 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC
2116 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC)
2117 reg_set_luid[REGNO (XEXP (dst, 0))] = 0;
2118 return;
2119 }
2120 if (!REG_P (dst))
2121 return;
2122
2123 regno += REGNO (dst);
2124 if (!nregs)
2125 nregs = hard_regno_nregs[regno][mode];
2126
2127 if (SCALAR_INT_MODE_P (GET_MODE (dst))
2128 && nregs == 1 && GET_CODE (set) == SET)
2129 {
2130 rtx note, sym = NULL_RTX;
2131 HOST_WIDE_INT off;
2132
2133 note = find_reg_equal_equiv_note (insn);
2134 if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF)
2135 {
2136 sym = XEXP (note, 0);
2137 off = 0;
2138 }
2139 else if (note && GET_CODE (XEXP (note, 0)) == CONST
2140 && GET_CODE (XEXP (XEXP (note, 0), 0)) == PLUS
2141 && GET_CODE (XEXP (XEXP (XEXP (note, 0), 0), 0)) == SYMBOL_REF
2142 && CONST_INT_P (XEXP (XEXP (XEXP (note, 0), 0), 1)))
2143 {
2144 sym = XEXP (XEXP (XEXP (note, 0), 0), 0);
2145 off = INTVAL (XEXP (XEXP (XEXP (note, 0), 0), 1));
2146 }
2147
2148 if (sym != NULL_RTX)
2149 {
2150 reg_base_reg[regno] = -1;
2151 reg_symbol_ref[regno] = sym;
2152 reg_offset[regno] = off;
2153 reg_mode[regno] = mode;
2154 reg_set_luid[regno] = move2add_luid;
2155 return;
2156 }
2157 }
2158
2159 if (SCALAR_INT_MODE_P (GET_MODE (dst))
2160 && nregs == 1 && GET_CODE (set) == SET
2161 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
2162 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
2163 {
2164 rtx src = SET_SRC (set);
2165 rtx base_reg;
2166 HOST_WIDE_INT offset;
2167 int base_regno;
2168 /* This may be different from mode, if SET_DEST (set) is a
2169 SUBREG. */
2170 enum machine_mode dst_mode = GET_MODE (dst);
2171
2172 switch (GET_CODE (src))
2173 {
2174 case PLUS:
2175 if (REG_P (XEXP (src, 0)))
2176 {
2177 base_reg = XEXP (src, 0);
2178
2179 if (CONST_INT_P (XEXP (src, 1)))
2180 offset = INTVAL (XEXP (src, 1));
2181 else if (REG_P (XEXP (src, 1))
2182 && (reg_set_luid[REGNO (XEXP (src, 1))]
2183 > move2add_last_label_luid)
2184 && (MODES_OK_FOR_MOVE2ADD
2185 (dst_mode, reg_mode[REGNO (XEXP (src, 1))])))
2186 {
2187 if (reg_base_reg[REGNO (XEXP (src, 1))] < 0
2188 && reg_symbol_ref[REGNO (XEXP (src, 1))] == NULL_RTX)
2189 offset = reg_offset[REGNO (XEXP (src, 1))];
2190 /* Maybe the first register is known to be a
2191 constant. */
2192 else if (reg_set_luid[REGNO (base_reg)]
2193 > move2add_last_label_luid
2194 && (MODES_OK_FOR_MOVE2ADD
2195 (dst_mode, reg_mode[REGNO (base_reg)]))
2196 && reg_base_reg[REGNO (base_reg)] < 0
2197 && reg_symbol_ref[REGNO (base_reg)] == NULL_RTX)
2198 {
2199 offset = reg_offset[REGNO (base_reg)];
2200 base_reg = XEXP (src, 1);
2201 }
2202 else
2203 goto invalidate;
2204 }
2205 else
2206 goto invalidate;
2207
2208 break;
2209 }
2210
2211 goto invalidate;
2212
2213 case REG:
2214 base_reg = src;
2215 offset = 0;
2216 break;
2217
2218 case CONST_INT:
2219 /* Start tracking the register as a constant. */
2220 reg_base_reg[regno] = -1;
2221 reg_symbol_ref[regno] = NULL_RTX;
2222 reg_offset[regno] = INTVAL (SET_SRC (set));
2223 /* We assign the same luid to all registers set to constants. */
2224 reg_set_luid[regno] = move2add_last_label_luid + 1;
2225 reg_mode[regno] = mode;
2226 return;
2227
2228 default:
2229 invalidate:
2230 /* Invalidate the contents of the register. */
2231 reg_set_luid[regno] = 0;
2232 return;
2233 }
2234
2235 base_regno = REGNO (base_reg);
2236 /* If information about the base register is not valid, set it
2237 up as a new base register, pretending its value is known
2238 starting from the current insn. */
2239 if (reg_set_luid[base_regno] <= move2add_last_label_luid)
2240 {
2241 reg_base_reg[base_regno] = base_regno;
2242 reg_symbol_ref[base_regno] = NULL_RTX;
2243 reg_offset[base_regno] = 0;
2244 reg_set_luid[base_regno] = move2add_luid;
2245 reg_mode[base_regno] = mode;
2246 }
2247 else if (! MODES_OK_FOR_MOVE2ADD (dst_mode,
2248 reg_mode[base_regno]))
2249 goto invalidate;
2250
2251 reg_mode[regno] = mode;
2252
2253 /* Copy base information from our base register. */
2254 reg_set_luid[regno] = reg_set_luid[base_regno];
2255 reg_base_reg[regno] = reg_base_reg[base_regno];
2256 reg_symbol_ref[regno] = reg_symbol_ref[base_regno];
2257
2258 /* Compute the sum of the offsets or constants. */
2259 reg_offset[regno] = trunc_int_for_mode (offset
2260 + reg_offset[base_regno],
2261 dst_mode);
2262 }
2263 else
2264 {
2265 unsigned int endregno = regno + nregs;
2266
2267 for (i = regno; i < endregno; i++)
2268 /* Reset the information about this register. */
2269 reg_set_luid[i] = 0;
2270 }
2271 }
2272
2273 static bool
gate_handle_postreload(void)2274 gate_handle_postreload (void)
2275 {
2276 return (optimize > 0 && reload_completed);
2277 }
2278
2279
2280 static unsigned int
rest_of_handle_postreload(void)2281 rest_of_handle_postreload (void)
2282 {
2283 if (!dbg_cnt (postreload_cse))
2284 return 0;
2285
2286 /* Do a very simple CSE pass over just the hard registers. */
2287 reload_cse_regs (get_insns ());
2288 /* Reload_cse_regs can eliminate potentially-trapping MEMs.
2289 Remove any EH edges associated with them. */
2290 if (cfun->can_throw_non_call_exceptions
2291 && purge_all_dead_edges ())
2292 cleanup_cfg (0);
2293
2294 return 0;
2295 }
2296
2297 struct rtl_opt_pass pass_postreload_cse =
2298 {
2299 {
2300 RTL_PASS,
2301 "postreload", /* name */
2302 OPTGROUP_NONE, /* optinfo_flags */
2303 gate_handle_postreload, /* gate */
2304 rest_of_handle_postreload, /* execute */
2305 NULL, /* sub */
2306 NULL, /* next */
2307 0, /* static_pass_number */
2308 TV_RELOAD_CSE_REGS, /* tv_id */
2309 0, /* properties_required */
2310 0, /* properties_provided */
2311 0, /* properties_destroyed */
2312 0, /* todo_flags_start */
2313 TODO_df_finish | TODO_verify_rtl_sharing |
2314 0 /* todo_flags_finish */
2315 }
2316 };
2317