1module top(input clk, cen, rst, ina, inb, output outa, outb, outc, outd);
2
3reg [31:0] temp = 0;
4
5integer i;
6
7always @(posedge clk)
8begin
9    if (cen) begin
10        if (rst) begin
11            temp <= 0;
12        end else begin
13            temp[0] <= ina;
14            temp[1] <= inb;
15            for (i = 2; i < 32; i++) begin
16                temp[i] <= temp[(i + 3) % 32] ^ temp[(i + 30) % 32] ^ temp[(i + 4) % 16] ^ temp[(i + 2) % 32];
17            end
18        end
19    end
20end
21
22assign outa = temp[3];
23assign outb = temp[5];
24assign outc = temp[9];
25assign outd = temp[15];
26
27endmodule
28