1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2007,2008 Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * Copyright (C) 2008 by Hongtao Zheng *
12 * hontor@126.com *
13 * *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
18 * *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
23 * *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
26 ***************************************************************************/
27
28 #ifndef OPENOCD_TARGET_ARM7_9_COMMON_H
29 #define OPENOCD_TARGET_ARM7_9_COMMON_H
30
31 #include "arm.h"
32 #include "arm_jtag.h"
33
34 #define ARM7_9_COMMON_MAGIC 0x0a790a79 /**< */
35
36 /**
37 * Structure for items that are common between both ARM7 and ARM9 targets.
38 */
39 struct arm7_9_common {
40 struct arm arm;
41 uint32_t common_magic;
42
43 struct arm_jtag jtag_info; /**< JTAG information for target */
44 struct reg_cache *eice_cache; /**< Embedded ICE register cache */
45
46 uint32_t arm_bkpt; /**< ARM breakpoint instruction */
47 uint16_t thumb_bkpt; /**< Thumb breakpoint instruction */
48
49 int sw_breakpoints_added; /**< Specifies which watchpoint software breakpoints are setup on */
50 int sw_breakpoint_count; /**< keep track of number of software breakpoints we have set */
51 int breakpoint_count; /**< Current number of set breakpoints */
52 int wp_available; /**< Current number of available watchpoint units */
53 int wp_available_max; /**< Maximum number of available watchpoint units */
54 int wp0_used; /**< Specifies if and how watchpoint unit 0 is used */
55 int wp1_used; /**< Specifies if and how watchpoint unit 1 is used */
56 int wp1_used_default; /**< Specifies if and how watchpoint unit 1 is used by default */
57 int dbgreq_adjust_pc; /**< Amount of PC adjustment caused by a DBGREQ */
58 bool use_dbgrq; /**< Specifies if DBGRQ should be used to halt the target */
59 bool need_bypass_before_restart; /**< Specifies if there should be a bypass before a JTAG restart */
60
61 bool has_single_step;
62 bool has_monitor_mode;
63 bool has_vector_catch; /**< Specifies if the target has a reset vector catch */
64
65 bool debug_entry_from_reset; /**< Specifies if debug entry was from a reset */
66
67 bool fast_memory_access;
68 bool dcc_downloads;
69
70 struct working_area *dcc_working_area;
71
72 int (*examine_debug_reason)(struct target *target);
73 /**< Function for determining why debug state was entered */
74
75 void (*change_to_arm)(struct target *target, uint32_t *r0, uint32_t *pc);
76 /**< Function for changing from Thumb to ARM mode */
77
78 void (*read_core_regs)(struct target *target, uint32_t mask, uint32_t *core_regs[16]);
79 /**< Function for reading the core registers */
80
81 void (*read_core_regs_target_buffer)(struct target *target, uint32_t mask,
82 void *buffer, int size);
83 void (*read_xpsr)(struct target *target, uint32_t *xpsr, int spsr);
84 /**< Function for reading CPSR or SPSR */
85
86 void (*write_xpsr)(struct target *target, uint32_t xpsr, int spsr);
87 /**< Function for writing to CPSR or SPSR */
88
89 void (*write_xpsr_im8)(struct target *target, uint8_t xpsr_im, int rot, int spsr);
90 /**< Function for writing an immediate value to CPSR or SPSR */
91
92 void (*write_core_regs)(struct target *target, uint32_t mask, uint32_t core_regs[16]);
93
94 void (*load_word_regs)(struct target *target, uint32_t mask);
95 void (*load_hword_reg)(struct target *target, int num);
96 void (*load_byte_reg)(struct target *target, int num);
97
98 void (*store_word_regs)(struct target *target, uint32_t mask);
99 void (*store_hword_reg)(struct target *target, int num);
100 void (*store_byte_reg)(struct target *target, int num);
101
102 void (*write_pc)(struct target *target, uint32_t pc);
103 /**< Function for writing to the program counter */
104
105 void (*branch_resume)(struct target *target);
106 void (*branch_resume_thumb)(struct target *target);
107
108 void (*enable_single_step)(struct target *target, uint32_t next_pc);
109 void (*disable_single_step)(struct target *target);
110
111 void (*set_special_dbgrq)(struct target *target);
112 /**< Function for setting DBGRQ if the normal way won't work */
113
114 int (*post_debug_entry)(struct target *target);
115 /**< Callback function called after entering debug mode */
116
117 void (*pre_restore_context)(struct target *target);
118 /**< Callback function called before restoring the processor context */
119
120 /**
121 * Variant specific memory write function that does not dispatch to bulk_write_memory.
122 * Used as a fallback when bulk writes are unavailable, or for writing data needed to
123 * do the bulk writes.
124 */
125 int (*write_memory)(struct target *target, target_addr_t address,
126 uint32_t size, uint32_t count, const uint8_t *buffer);
127 /**
128 * Write target memory in multiples of 4 bytes, optimized for
129 * writing large quantities of data.
130 */
131 int (*bulk_write_memory)(struct target *target, target_addr_t address,
132 uint32_t count, const uint8_t *buffer);
133 };
134
target_to_arm7_9(struct target * target)135 static inline struct arm7_9_common *target_to_arm7_9(struct target *target)
136 {
137 return container_of(target->arch_info, struct arm7_9_common, arm);
138 }
139
is_arm7_9(struct arm7_9_common * arm7_9)140 static inline bool is_arm7_9(struct arm7_9_common *arm7_9)
141 {
142 return arm7_9->common_magic == ARM7_9_COMMON_MAGIC;
143 }
144
145 extern const struct command_registration arm7_9_command_handlers[];
146
147 int arm7_9_poll(struct target *target);
148
149 int arm7_9_target_request_data(struct target *target, uint32_t size, uint8_t *buffer);
150
151 int arm7_9_assert_reset(struct target *target);
152 int arm7_9_deassert_reset(struct target *target);
153 int arm7_9_reset_request_halt(struct target *target);
154 int arm7_9_early_halt(struct target *target);
155 int arm7_9_soft_reset_halt(struct target *target);
156
157 int arm7_9_halt(struct target *target);
158 int arm7_9_resume(struct target *target, int current, target_addr_t address,
159 int handle_breakpoints, int debug_execution);
160 int arm7_9_step(struct target *target, int current, target_addr_t address,
161 int handle_breakpoints);
162 int arm7_9_read_memory(struct target *target, target_addr_t address,
163 uint32_t size, uint32_t count, uint8_t *buffer);
164 int arm7_9_write_memory(struct target *target, target_addr_t address,
165 uint32_t size, uint32_t count, const uint8_t *buffer);
166 int arm7_9_write_memory_opt(struct target *target, target_addr_t address,
167 uint32_t size, uint32_t count, const uint8_t *buffer);
168 int arm7_9_write_memory_no_opt(struct target *target, uint32_t address,
169 uint32_t size, uint32_t count, const uint8_t *buffer);
170 int arm7_9_bulk_write_memory(struct target *target, target_addr_t address,
171 uint32_t count, const uint8_t *buffer);
172
173 int arm7_9_run_algorithm(struct target *target, int num_mem_params,
174 struct mem_param *mem_params, int num_reg_prams,
175 struct reg_param *reg_param, uint32_t entry_point, void *arch_info);
176
177 int arm7_9_add_breakpoint(struct target *target, struct breakpoint *breakpoint);
178 int arm7_9_remove_breakpoint(struct target *target, struct breakpoint *breakpoint);
179 int arm7_9_add_watchpoint(struct target *target, struct watchpoint *watchpoint);
180 int arm7_9_remove_watchpoint(struct target *target, struct watchpoint *watchpoint);
181
182 void arm7_9_enable_eice_step(struct target *target, uint32_t next_pc);
183 void arm7_9_disable_eice_step(struct target *target);
184
185 int arm7_9_execute_sys_speed(struct target *target);
186
187 int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9);
188 int arm7_9_examine(struct target *target);
189 void arm7_9_deinit(struct target *target);
190 int arm7_9_check_reset(struct target *target);
191
192 int arm7_9_endianness_callback(jtag_callback_data_t pu8_in,
193 jtag_callback_data_t i_size, jtag_callback_data_t i_be,
194 jtag_callback_data_t i_flip);
195
196 #endif /* OPENOCD_TARGET_ARM7_9_COMMON_H */
197