1 /* 2 * $Id: i2s.h,v 1.11 2005/09/29 08:51:07 telka Exp $ 3 * 4 * XScale PXA26x/PXA255/PXA250/PXA210 I2S Registers 5 * Copyright (C) 2002, 2003 ETC s.r.o. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of the ETC s.r.o. nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 26 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 27 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 29 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 * Written by Marcel Telka <marcel@telka.sk>, 2002, 2003. 32 * 33 * Documentation: 34 * [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors 35 * Developer's Manual", February 2002, Order Number: 278522-001 36 * [2] Intel Corporation, "Intel PXA26x Processor Family Developer's Manual", 37 * March 2003, Order Number: 278638-002 38 * [3] Intel Corporation, "Intel PXA255 Processor Developer's Manual" 39 * March 2003, Order Number: 278693-001 40 * 41 */ 42 43 #ifndef PXA2X0_I2S_H 44 #define PXA2X0_I2S_H 45 46 #include <openwince.h> 47 48 #if LANGUAGE == C 49 #include <stdint.h> 50 #endif 51 52 #if defined(PXA2X0_NOPXA250) && !defined(PXA2X0_NOPXA255) 53 #define PXA2X0_NOPXA255 54 #endif 55 56 #if defined(PXA2X0_NOPXA255) && !defined(PXA2X0_NOPXA260) 57 #define PXA2X0_NOPXA260 58 #endif 59 60 /* I2S Registers */ 61 62 #define I2S_BASE 0x40400000 63 64 #if LANGUAGE == C 65 typedef volatile struct I2S_registers { 66 uint32_t sacr0; 67 uint32_t sacr1; 68 uint32_t __reserved1; 69 uint32_t sasr0; 70 uint32_t __reserved2; 71 uint32_t saimr; 72 uint32_t saicr; 73 uint32_t __reserved3[17]; 74 uint32_t sadiv; 75 uint32_t __reserved4[7]; 76 uint32_t sadr; 77 } I2S_registers_t; 78 79 #ifdef PXA2X0_UNMAPPED 80 #define I2S_pointer ((I2S_registers_t*) I2S_BASE) 81 #endif 82 83 #define SACR0 I2S_pointer->sacr0 84 #define SACR1 I2S_pointer->sacr1 85 #define SASR0 I2S_pointer->sasr0 86 #define SAIMR I2S_pointer->saimr 87 #define SAICR I2S_pointer->saicr 88 #define SADIV I2S_pointer->sadiv 89 #define SADR I2S_pointer->sadr 90 #endif /* LANGUAGE == C */ 91 92 #define SACR0_OFFSET 0x00 93 #define SACR1_OFFSET 0x04 94 #define SASR0_OFFSET 0x0C 95 #define SAIMR_OFFSET 0x14 96 #define SAICR_OFFSET 0x18 97 #define SADIV_OFFSET 0x60 98 #define SADR_OFFSET 0x80 99 100 /* SACR0 bits - see Table 14-3 in [1], Table 14-3 in [2], Table 14-3 in [3] */ 101 102 #define SACR0_RFTH_MASK bits(15,12) 103 #define SACR0_RFTH(x) bits_val(15,12,x) 104 #define get_SACR0_RFTH(x) bits_get(15,12,x) 105 #define SACR0_TFTH_MASK bits(11,8) 106 #define SACR0_TFTH(x) bits_val(11,8,x) 107 #define get_SACR0_TFTH(x) bits_get(11,8,x) 108 #define SACR0_STRF bit(5) 109 #define SACR0_EFWR bit(4) 110 #define SACR0_RST bit(3) 111 #define SACR0_BCKD bit(2) 112 #define SACR0_ENB bit(0) 113 114 /* SACR1 bits - see Table 14-6 in [1], Table 14-6 in [2], Table 14-6 in [3] */ 115 116 #define SACR1_ENLBF bit(5) 117 #define SACR1_DRPL bit(4) 118 #define SACR1_DREC bit(3) 119 #define SACR1_AMSL bit(0) 120 121 /* SASR0 bits - see Table 14-7 in [1], Table 14-7 in [2], Table 14-7 in [3] */ 122 123 #define SASR0_RFL_MASK bits(15,12) 124 #define SASR0_RFL(x) bits_val(15,12,x) 125 #define get_SASR0_RFL(x) bits_get(15,12,x) 126 #define SASR0_TFL_MASK bits(11,8) 127 #define SASR0_TFL(x) bits_val(11,8,x) 128 #define get_SASR0_TFL(x) bits_get(11,8,x) 129 #define SASR0_ROR bit(6) 130 #define SASR0_TUR bit(5) 131 #define SASR0_RFS bit(4) 132 #define SASR0_TFS bit(3) 133 #define SASR0_BSY bit(2) 134 #define SASR0_RNE bit(1) 135 #define SASR0_TNF bit(0) 136 137 /* SAIMR bits - see Table 14-10 in [1], Table 14-10 in [2], Table 14-10 in [3] */ 138 139 #define SAIMR_ROR bit(6) 140 #define SAIMR_TUR bit(5) 141 #define SAIMR_RFS bit(4) 142 #define SAIMR_TFS bit(3) 143 144 /* SAICR bits - see Table 14-9 in [1], Table 14-9 in [2], Table 14-9 in [3] */ 145 146 #define SAICR_ROR bit(6) 147 #define SAICR_TUR bit(5) 148 149 /* SADIV bits - see Table 14-8 in [1], Table 14-8 in [2], Table 14-8 in [3] */ 150 151 #define SADIV_SADIV_MASK bits(6,0) 152 #define SADIV_SADIV(x) bits_val(6,0,x) 153 #define get_SADIV_SADIV(x) bits_get(6,0,x) 154 155 /* SADR bits - see Table 14-11 in [1], Table 14-11 in [2], Table 14-11 in [3] */ 156 157 #define SADR_DTH_MASK bits(31,16) 158 #define SADR_DTH(x) bits_val(31,16,x) 159 #define get_SADR_DTH(x) bits_get(31,16,x) 160 #define SADR_DTL_MASK bits(15,0) 161 #define SADR_DTL(x) bits_val(15,0,x) 162 #define get_SADR_DTL(x) bits_get(15,0,x) 163 164 #endif /* PXA2X0_I2S_H */ 165