1 /**************************************************************************//** 2 * @file core_ca9.h 3 * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File 4 * @version 5 * @date 25 March 2013 6 * 7 * @note 8 * 9 ******************************************************************************/ 10 /* Copyright (c) 2009 - 2012 ARM LIMITED 11 12 All rights reserved. 13 Redistribution and use in source and binary forms, with or without 14 modification, are permitted provided that the following conditions are met: 15 - Redistributions of source code must retain the above copyright 16 notice, this list of conditions and the following disclaimer. 17 - Redistributions in binary form must reproduce the above copyright 18 notice, this list of conditions and the following disclaimer in the 19 documentation and/or other materials provided with the distribution. 20 - Neither the name of ARM nor the names of its contributors may be used 21 to endorse or promote products derived from this software without 22 specific prior written permission. 23 * 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 POSSIBILITY OF SUCH DAMAGE. 35 ---------------------------------------------------------------------------*/ 36 37 38 #if defined ( __ICCARM__ ) 39 #pragma system_include /* treat file as system include file for MISRA check */ 40 #endif 41 42 #ifdef __cplusplus 43 extern "C" { 44 #endif 45 46 #ifndef __CORE_CA9_H_GENERIC 47 #define __CORE_CA9_H_GENERIC 48 49 50 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 51 CMSIS violates the following MISRA-C:2004 rules: 52 53 \li Required Rule 8.5, object/function definition in header file.<br> 54 Function definitions in header files are used to allow 'inlining'. 55 56 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 57 Unions are used for effective representation of core registers. 58 59 \li Advisory Rule 19.7, Function-like macro defined.<br> 60 Function-like macros are used to allow more efficient code. 61 */ 62 63 64 /******************************************************************************* 65 * CMSIS definitions 66 ******************************************************************************/ 67 /** \ingroup Cortex_A9 68 @{ 69 */ 70 71 /* CMSIS CA9 definitions */ 72 #define __CA9_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ 73 #define __CA9_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */ 74 #define __CA9_CMSIS_VERSION ((__CA9_CMSIS_VERSION_MAIN << 16) | \ 75 __CA9_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ 76 77 #define __CORTEX_A (0x09) /*!< Cortex-A Core */ 78 79 80 #if defined ( __CC_ARM ) 81 #define __ASM __asm /*!< asm keyword for ARM Compiler */ 82 #define __INLINE __inline /*!< inline keyword for ARM Compiler */ 83 #define __STATIC_INLINE static __inline 84 #define __STATIC_ASM static __asm 85 86 #elif defined ( __ICCARM__ ) 87 #define __ASM __asm /*!< asm keyword for IAR Compiler */ 88 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ 89 #define __STATIC_INLINE static inline 90 #define __STATIC_ASM static __asm 91 92 #include <stdint.h> 93 inline uint32_t __get_PSR(void) { 94 __ASM("mrs r0, cpsr"); 95 } 96 97 #elif defined ( __TMS470__ ) 98 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ 99 #define __STATIC_INLINE static inline 100 #define __STATIC_ASM static __asm 101 102 #elif defined ( __GNUC__ ) 103 #define __ASM __asm /*!< asm keyword for GNU Compiler */ 104 #define __INLINE inline /*!< inline keyword for GNU Compiler */ 105 #define __STATIC_INLINE static inline 106 #define __STATIC_ASM static __asm 107 108 #elif defined ( __TASKING__ ) 109 #define __ASM __asm /*!< asm keyword for TASKING Compiler */ 110 #define __INLINE inline /*!< inline keyword for TASKING Compiler */ 111 #define __STATIC_INLINE static inline 112 #define __STATIC_ASM static __asm 113 114 #endif 115 116 /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. 117 */ 118 #if defined ( __CC_ARM ) 119 #if defined __TARGET_FPU_VFP 120 #if (__FPU_PRESENT == 1) 121 #define __FPU_USED 1 122 #else 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 124 #define __FPU_USED 0 125 #endif 126 #else 127 #define __FPU_USED 0 128 #endif 129 130 #elif defined ( __ICCARM__ ) 131 #if defined __ARMVFP__ 132 #if (__FPU_PRESENT == 1) 133 #define __FPU_USED 1 134 #else 135 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 136 #define __FPU_USED 0 137 #endif 138 #else 139 #define __FPU_USED 0 140 #endif 141 142 #elif defined ( __TMS470__ ) 143 #if defined __TI_VFP_SUPPORT__ 144 #if (__FPU_PRESENT == 1) 145 #define __FPU_USED 1 146 #else 147 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 148 #define __FPU_USED 0 149 #endif 150 #else 151 #define __FPU_USED 0 152 #endif 153 154 #elif defined ( __GNUC__ ) 155 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 156 #if (__FPU_PRESENT == 1) 157 #define __FPU_USED 1 158 #else 159 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 160 #define __FPU_USED 0 161 #endif 162 #else 163 #define __FPU_USED 0 164 #endif 165 166 #elif defined ( __TASKING__ ) 167 #if defined __FPU_VFP__ 168 #if (__FPU_PRESENT == 1) 169 #define __FPU_USED 1 170 #else 171 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 172 #define __FPU_USED 0 173 #endif 174 #else 175 #define __FPU_USED 0 176 #endif 177 #endif 178 179 #include <stdint.h> /*!< standard types definitions */ 180 #include "core_caInstr.h" /*!< Core Instruction Access */ 181 #include "core_caFunc.h" /*!< Core Function Access */ 182 #include "core_cm4_simd.h" /*!< Compiler specific SIMD Intrinsics */ 183 184 #endif /* __CORE_CA9_H_GENERIC */ 185 186 #ifndef __CMSIS_GENERIC 187 188 #ifndef __CORE_CA9_H_DEPENDANT 189 #define __CORE_CA9_H_DEPENDANT 190 191 /* check device defines and use defaults */ 192 #if defined __CHECK_DEVICE_DEFINES 193 #ifndef __CA9_REV 194 #define __CA9_REV 0x0000 195 #warning "__CA9_REV not defined in device header file; using default!" 196 #endif 197 198 #ifndef __FPU_PRESENT 199 #define __FPU_PRESENT 1 200 #warning "__FPU_PRESENT not defined in device header file; using default!" 201 #endif 202 203 #ifndef __Vendor_SysTickConfig 204 #define __Vendor_SysTickConfig 1 205 #endif 206 207 #if __Vendor_SysTickConfig == 0 208 #error "__Vendor_SysTickConfig set to 0, but vendor systick timer must be supplied for Cortex-A9" 209 #endif 210 #endif 211 212 /* IO definitions (access restrictions to peripheral registers) */ 213 /** 214 \defgroup CMSIS_glob_defs CMSIS Global Defines 215 216 <strong>IO Type Qualifiers</strong> are used 217 \li to specify the access to peripheral variables. 218 \li for automatic generation of peripheral register debug information. 219 */ 220 #ifdef __cplusplus 221 #define __I volatile /*!< Defines 'read only' permissions */ 222 #else 223 #define __I volatile const /*!< Defines 'read only' permissions */ 224 #endif 225 #define __O volatile /*!< Defines 'write only' permissions */ 226 #define __IO volatile /*!< Defines 'read / write' permissions */ 227 228 /*@} end of group Cortex_A9 */ 229 230 231 /******************************************************************************* 232 * Register Abstraction 233 ******************************************************************************/ 234 /** \defgroup CMSIS_core_register Defines and Type Definitions 235 \brief Type definitions and defines for Cortex-A processor based devices. 236 */ 237 238 /** \ingroup CMSIS_core_register 239 \defgroup CMSIS_CORE Status and Control Registers 240 \brief Core Register type definitions. 241 @{ 242 */ 243 244 /** \brief Union type to access the Application Program Status Register (APSR). 245 */ 246 typedef union 247 { 248 struct 249 { 250 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ 251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 252 uint32_t reserved1:7; /*!< bit: 20..23 Reserved */ 253 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 254 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 255 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 256 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 257 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 258 } b; /*!< Structure used for bit access */ 259 uint32_t w; /*!< Type used for word access */ 260 } APSR_Type; 261 262 263 /*@} end of group CMSIS_CORE */ 264 265 /*@} end of CMSIS_Core_FPUFunctions */ 266 267 268 #endif /* __CORE_CA9_H_GENERIC */ 269 270 #endif /* __CMSIS_GENERIC */ 271 272 #ifdef __cplusplus 273 } 274 275 276 #endif 277