1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Machine Code Emitter *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9uint64_t ARMMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, 10 SmallVectorImpl<MCFixup> &Fixups, 11 const MCSubtargetInfo &STI) const { 12 static const uint64_t InstBits[] = { 13 UINT64_C(0), 14 UINT64_C(0), 15 UINT64_C(0), 16 UINT64_C(0), 17 UINT64_C(0), 18 UINT64_C(0), 19 UINT64_C(0), 20 UINT64_C(0), 21 UINT64_C(0), 22 UINT64_C(0), 23 UINT64_C(0), 24 UINT64_C(0), 25 UINT64_C(0), 26 UINT64_C(0), 27 UINT64_C(0), 28 UINT64_C(0), 29 UINT64_C(0), 30 UINT64_C(0), 31 UINT64_C(0), 32 UINT64_C(0), 33 UINT64_C(0), 34 UINT64_C(0), 35 UINT64_C(0), 36 UINT64_C(0), 37 UINT64_C(0), 38 UINT64_C(44040192), // ADCri 39 UINT64_C(10485760), // ADCrr 40 UINT64_C(10485760), // ADCrsi 41 UINT64_C(10485776), // ADCrsr 42 UINT64_C(0), 43 UINT64_C(0), 44 UINT64_C(0), 45 UINT64_C(0), 46 UINT64_C(41943040), // ADDri 47 UINT64_C(8388608), // ADDrr 48 UINT64_C(8388608), // ADDrsi 49 UINT64_C(8388624), // ADDrsr 50 UINT64_C(0), 51 UINT64_C(0), 52 UINT64_C(34537472), // ADR 53 UINT64_C(4088398656), // AESD 54 UINT64_C(4088398592), // AESE 55 UINT64_C(4088398784), // AESIMC 56 UINT64_C(4088398720), // AESMC 57 UINT64_C(33554432), // ANDri 58 UINT64_C(0), // ANDrr 59 UINT64_C(0), // ANDrsi 60 UINT64_C(16), // ANDrsr 61 UINT64_C(0), 62 UINT64_C(0), 63 UINT64_C(0), 64 UINT64_C(0), 65 UINT64_C(0), 66 UINT64_C(130023455), // BFC 67 UINT64_C(130023440), // BFI 68 UINT64_C(62914560), // BICri 69 UINT64_C(29360128), // BICrr 70 UINT64_C(29360128), // BICrsi 71 UINT64_C(29360144), // BICrsr 72 UINT64_C(3776970864), // BKPT 73 UINT64_C(3942645760), // BL 74 UINT64_C(3778019120), // BLX 75 UINT64_C(19922736), // BLX_pred 76 UINT64_C(4194304000), // BLXi 77 UINT64_C(184549376), // BL_pred 78 UINT64_C(0), 79 UINT64_C(0), 80 UINT64_C(0), 81 UINT64_C(0), 82 UINT64_C(0), 83 UINT64_C(3778019088), // BX 84 UINT64_C(19922720), // BXJ 85 UINT64_C(0), 86 UINT64_C(19922718), // BX_RET 87 UINT64_C(19922704), // BX_pred 88 UINT64_C(167772160), // Bcc 89 UINT64_C(234881024), // CDP 90 UINT64_C(4261412864), // CDP2 91 UINT64_C(4118802463), // CLREX 92 UINT64_C(24055568), // CLZ 93 UINT64_C(57671680), // CMNri 94 UINT64_C(24117248), // CMNzrr 95 UINT64_C(24117248), // CMNzrsi 96 UINT64_C(24117264), // CMNzrsr 97 UINT64_C(55574528), // CMPri 98 UINT64_C(22020096), // CMPrr 99 UINT64_C(22020096), // CMPrsi 100 UINT64_C(22020112), // CMPrsr 101 UINT64_C(0), 102 UINT64_C(0), 103 UINT64_C(4043440128), // CPS1p 104 UINT64_C(4043309056), // CPS2p 105 UINT64_C(4043440128), // CPS3p 106 UINT64_C(3774873664), // CRC32B 107 UINT64_C(3774874176), // CRC32CB 108 UINT64_C(3776971328), // CRC32CH 109 UINT64_C(3779068480), // CRC32CW 110 UINT64_C(3776970816), // CRC32H 111 UINT64_C(3779067968), // CRC32W 112 UINT64_C(52490480), // DBG 113 UINT64_C(4118802512), // DMB 114 UINT64_C(4118802496), // DSB 115 UINT64_C(35651584), // EORri 116 UINT64_C(2097152), // EORrr 117 UINT64_C(2097152), // EORrsi 118 UINT64_C(2097168), // EORrsr 119 UINT64_C(23068782), // ERET 120 UINT64_C(246418176), // FCONSTD 121 UINT64_C(246417664), // FCONSTH 122 UINT64_C(246417920), // FCONSTS 123 UINT64_C(221252353), // FLDMXDB_UPD 124 UINT64_C(210766593), // FLDMXIA 125 UINT64_C(212863745), // FLDMXIA_UPD 126 UINT64_C(250739216), // FMSTAT 127 UINT64_C(220203777), // FSTMXDB_UPD 128 UINT64_C(209718017), // FSTMXIA 129 UINT64_C(211815169), // FSTMXIA_UPD 130 UINT64_C(52490240), // HINT 131 UINT64_C(3774873712), // HLT 132 UINT64_C(3779068016), // HVC 133 UINT64_C(4118802528), // ISB 134 UINT64_C(0), 135 UINT64_C(0), 136 UINT64_C(0), 137 UINT64_C(0), 138 UINT64_C(0), 139 UINT64_C(0), 140 UINT64_C(0), 141 UINT64_C(0), 142 UINT64_C(0), 143 UINT64_C(0), 144 UINT64_C(26217631), // LDA 145 UINT64_C(30411935), // LDAB 146 UINT64_C(26218143), // LDAEX 147 UINT64_C(30412447), // LDAEXB 148 UINT64_C(28315295), // LDAEXD 149 UINT64_C(32509599), // LDAEXH 150 UINT64_C(32509087), // LDAH 151 UINT64_C(4249878528), // LDC2L_OFFSET 152 UINT64_C(4241489920), // LDC2L_OPTION 153 UINT64_C(4235198464), // LDC2L_POST 154 UINT64_C(4251975680), // LDC2L_PRE 155 UINT64_C(4245684224), // LDC2_OFFSET 156 UINT64_C(4237295616), // LDC2_OPTION 157 UINT64_C(4231004160), // LDC2_POST 158 UINT64_C(4247781376), // LDC2_PRE 159 UINT64_C(223346688), // LDCL_OFFSET 160 UINT64_C(214958080), // LDCL_OPTION 161 UINT64_C(208666624), // LDCL_POST 162 UINT64_C(225443840), // LDCL_PRE 163 UINT64_C(219152384), // LDC_OFFSET 164 UINT64_C(210763776), // LDC_OPTION 165 UINT64_C(204472320), // LDC_POST 166 UINT64_C(221249536), // LDC_PRE 167 UINT64_C(135266304), // LDMDA 168 UINT64_C(137363456), // LDMDA_UPD 169 UINT64_C(152043520), // LDMDB 170 UINT64_C(154140672), // LDMDB_UPD 171 UINT64_C(143654912), // LDMIA 172 UINT64_C(0), 173 UINT64_C(145752064), // LDMIA_UPD 174 UINT64_C(160432128), // LDMIB 175 UINT64_C(162529280), // LDMIB_UPD 176 UINT64_C(0), 177 UINT64_C(74448896), // LDRBT_POST_IMM 178 UINT64_C(108003328), // LDRBT_POST_REG 179 UINT64_C(72351744), // LDRB_POST_IMM 180 UINT64_C(105906176), // LDRB_POST_REG 181 UINT64_C(91226112), // LDRB_PRE_IMM 182 UINT64_C(124780544), // LDRB_PRE_REG 183 UINT64_C(89128960), // LDRBi12 184 UINT64_C(122683392), // LDRBrs 185 UINT64_C(16777424), // LDRD 186 UINT64_C(208), // LDRD_POST 187 UINT64_C(18874576), // LDRD_PRE 188 UINT64_C(26218399), // LDREX 189 UINT64_C(30412703), // LDREXB 190 UINT64_C(28315551), // LDREXD 191 UINT64_C(32509855), // LDREXH 192 UINT64_C(17825968), // LDRH 193 UINT64_C(7340208), // LDRHTi 194 UINT64_C(3145904), // LDRHTr 195 UINT64_C(1048752), // LDRH_POST 196 UINT64_C(19923120), // LDRH_PRE 197 UINT64_C(0), 198 UINT64_C(0), 199 UINT64_C(0), 200 UINT64_C(17826000), // LDRSB 201 UINT64_C(7340240), // LDRSBTi 202 UINT64_C(3145936), // LDRSBTr 203 UINT64_C(1048784), // LDRSB_POST 204 UINT64_C(19923152), // LDRSB_PRE 205 UINT64_C(17826032), // LDRSH 206 UINT64_C(7340272), // LDRSHTi 207 UINT64_C(3145968), // LDRSHTr 208 UINT64_C(1048816), // LDRSH_POST 209 UINT64_C(19923184), // LDRSH_PRE 210 UINT64_C(0), 211 UINT64_C(70254592), // LDRT_POST_IMM 212 UINT64_C(103809024), // LDRT_POST_REG 213 UINT64_C(68157440), // LDR_POST_IMM 214 UINT64_C(101711872), // LDR_POST_REG 215 UINT64_C(87031808), // LDR_PRE_IMM 216 UINT64_C(120586240), // LDR_PRE_REG 217 UINT64_C(85917696), // LDRcp 218 UINT64_C(84934656), // LDRi12 219 UINT64_C(118489088), // LDRrs 220 UINT64_C(0), 221 UINT64_C(0), 222 UINT64_C(0), 223 UINT64_C(0), 224 UINT64_C(0), 225 UINT64_C(0), 226 UINT64_C(234881040), // MCR 227 UINT64_C(4261412880), // MCR2 228 UINT64_C(205520896), // MCRR 229 UINT64_C(4232052736), // MCRR2 230 UINT64_C(0), 231 UINT64_C(2097296), // MLA 232 UINT64_C(0), 233 UINT64_C(6291600), // MLS 234 UINT64_C(0), 235 UINT64_C(0), 236 UINT64_C(0), 237 UINT64_C(0), 238 UINT64_C(0), 239 UINT64_C(0), 240 UINT64_C(27324430), // MOVPCLR 241 UINT64_C(0), 242 UINT64_C(54525952), // MOVTi16 243 UINT64_C(0), 244 UINT64_C(0), 245 UINT64_C(0), 246 UINT64_C(60817408), // MOVi 247 UINT64_C(50331648), // MOVi16 248 UINT64_C(0), 249 UINT64_C(0), 250 UINT64_C(27262976), // MOVr 251 UINT64_C(27262976), // MOVr_TC 252 UINT64_C(27262976), // MOVsi 253 UINT64_C(27262992), // MOVsr 254 UINT64_C(0), 255 UINT64_C(0), 256 UINT64_C(235929616), // MRC 257 UINT64_C(4262461456), // MRC2 258 UINT64_C(206569472), // MRRC 259 UINT64_C(4233101312), // MRRC2 260 UINT64_C(17760256), // MRS 261 UINT64_C(16777728), // MRSbanked 262 UINT64_C(21954560), // MRSsys 263 UINT64_C(18935808), // MSR 264 UINT64_C(18936320), // MSRbanked 265 UINT64_C(52490240), // MSRi 266 UINT64_C(144), // MUL 267 UINT64_C(0), 268 UINT64_C(0), 269 UINT64_C(65011712), // MVNi 270 UINT64_C(31457280), // MVNr 271 UINT64_C(31457280), // MVNsi 272 UINT64_C(31457296), // MVNsr 273 UINT64_C(58720256), // ORRri 274 UINT64_C(25165824), // ORRrr 275 UINT64_C(25165824), // ORRrsi 276 UINT64_C(25165840), // ORRrsr 277 UINT64_C(0), 278 UINT64_C(0), 279 UINT64_C(0), 280 UINT64_C(0), 281 UINT64_C(0), 282 UINT64_C(0), 283 UINT64_C(0), 284 UINT64_C(0), 285 UINT64_C(0), 286 UINT64_C(109051920), // PKHBT 287 UINT64_C(109051984), // PKHTB 288 UINT64_C(4111527936), // PLDWi12 289 UINT64_C(4145082368), // PLDWrs 290 UINT64_C(4115722240), // PLDi12 291 UINT64_C(4149276672), // PLDrs 292 UINT64_C(4098945024), // PLIi12 293 UINT64_C(4132499456), // PLIrs 294 UINT64_C(16777296), // QADD 295 UINT64_C(102764304), // QADD16 296 UINT64_C(102764432), // QADD8 297 UINT64_C(102764336), // QASX 298 UINT64_C(20971600), // QDADD 299 UINT64_C(23068752), // QDSUB 300 UINT64_C(102764368), // QSAX 301 UINT64_C(18874448), // QSUB 302 UINT64_C(102764400), // QSUB16 303 UINT64_C(102764528), // QSUB8 304 UINT64_C(117378864), // RBIT 305 UINT64_C(113184560), // REV 306 UINT64_C(113184688), // REV16 307 UINT64_C(117378992), // REVSH 308 UINT64_C(4161800704), // RFEDA 309 UINT64_C(4163897856), // RFEDA_UPD 310 UINT64_C(4178577920), // RFEDB 311 UINT64_C(4180675072), // RFEDB_UPD 312 UINT64_C(4170189312), // RFEIA 313 UINT64_C(4172286464), // RFEIA_UPD 314 UINT64_C(4186966528), // RFEIB 315 UINT64_C(4189063680), // RFEIB_UPD 316 UINT64_C(0), 317 UINT64_C(0), 318 UINT64_C(0), 319 UINT64_C(0), 320 UINT64_C(0), 321 UINT64_C(0), 322 UINT64_C(0), 323 UINT64_C(39845888), // RSBri 324 UINT64_C(6291456), // RSBrr 325 UINT64_C(6291456), // RSBrsi 326 UINT64_C(6291472), // RSBrsr 327 UINT64_C(48234496), // RSCri 328 UINT64_C(14680064), // RSCrr 329 UINT64_C(14680064), // RSCrsi 330 UINT64_C(14680080), // RSCrsr 331 UINT64_C(101715728), // SADD16 332 UINT64_C(101715856), // SADD8 333 UINT64_C(101715760), // SASX 334 UINT64_C(46137344), // SBCri 335 UINT64_C(12582912), // SBCrr 336 UINT64_C(12582912), // SBCrsi 337 UINT64_C(12582928), // SBCrsr 338 UINT64_C(127926352), // SBFX 339 UINT64_C(118550544), // SDIV 340 UINT64_C(109055920), // SEL 341 UINT64_C(4043374592), // SETEND 342 UINT64_C(4044357632), // SETPAN 343 UINT64_C(4060089408), // SHA1C 344 UINT64_C(4088988352), // SHA1H 345 UINT64_C(4062186560), // SHA1M 346 UINT64_C(4061137984), // SHA1P 347 UINT64_C(4063235136), // SHA1SU0 348 UINT64_C(4089054080), // SHA1SU1 349 UINT64_C(4076866624), // SHA256H 350 UINT64_C(4077915200), // SHA256H2 351 UINT64_C(4089054144), // SHA256SU0 352 UINT64_C(4078963776), // SHA256SU1 353 UINT64_C(103812880), // SHADD16 354 UINT64_C(103813008), // SHADD8 355 UINT64_C(103812912), // SHASX 356 UINT64_C(103812944), // SHSAX 357 UINT64_C(103812976), // SHSUB16 358 UINT64_C(103813104), // SHSUB8 359 UINT64_C(23068784), // SMC 360 UINT64_C(16777344), // SMLABB 361 UINT64_C(16777408), // SMLABT 362 UINT64_C(117440528), // SMLAD 363 UINT64_C(117440560), // SMLADX 364 UINT64_C(14680208), // SMLAL 365 UINT64_C(20971648), // SMLALBB 366 UINT64_C(20971712), // SMLALBT 367 UINT64_C(121634832), // SMLALD 368 UINT64_C(121634864), // SMLALDX 369 UINT64_C(20971680), // SMLALTB 370 UINT64_C(20971744), // SMLALTT 371 UINT64_C(0), 372 UINT64_C(16777376), // SMLATB 373 UINT64_C(16777440), // SMLATT 374 UINT64_C(18874496), // SMLAWB 375 UINT64_C(18874560), // SMLAWT 376 UINT64_C(117440592), // SMLSD 377 UINT64_C(117440624), // SMLSDX 378 UINT64_C(121634896), // SMLSLD 379 UINT64_C(121634928), // SMLSLDX 380 UINT64_C(122683408), // SMMLA 381 UINT64_C(122683440), // SMMLAR 382 UINT64_C(122683600), // SMMLS 383 UINT64_C(122683632), // SMMLSR 384 UINT64_C(122744848), // SMMUL 385 UINT64_C(122744880), // SMMULR 386 UINT64_C(117501968), // SMUAD 387 UINT64_C(117502000), // SMUADX 388 UINT64_C(23068800), // SMULBB 389 UINT64_C(23068864), // SMULBT 390 UINT64_C(12583056), // SMULL 391 UINT64_C(0), 392 UINT64_C(23068832), // SMULTB 393 UINT64_C(23068896), // SMULTT 394 UINT64_C(18874528), // SMULWB 395 UINT64_C(18874592), // SMULWT 396 UINT64_C(117502032), // SMUSD 397 UINT64_C(117502064), // SMUSDX 398 UINT64_C(0), 399 UINT64_C(4165797120), // SRSDA 400 UINT64_C(4167894272), // SRSDA_UPD 401 UINT64_C(4182574336), // SRSDB 402 UINT64_C(4184671488), // SRSDB_UPD 403 UINT64_C(4174185728), // SRSIA 404 UINT64_C(4176282880), // SRSIA_UPD 405 UINT64_C(4190962944), // SRSIB 406 UINT64_C(4193060096), // SRSIB_UPD 407 UINT64_C(111149072), // SSAT 408 UINT64_C(111152944), // SSAT16 409 UINT64_C(101715792), // SSAX 410 UINT64_C(101715824), // SSUB16 411 UINT64_C(101715952), // SSUB8 412 UINT64_C(4248829952), // STC2L_OFFSET 413 UINT64_C(4240441344), // STC2L_OPTION 414 UINT64_C(4234149888), // STC2L_POST 415 UINT64_C(4250927104), // STC2L_PRE 416 UINT64_C(4244635648), // STC2_OFFSET 417 UINT64_C(4236247040), // STC2_OPTION 418 UINT64_C(4229955584), // STC2_POST 419 UINT64_C(4246732800), // STC2_PRE 420 UINT64_C(222298112), // STCL_OFFSET 421 UINT64_C(213909504), // STCL_OPTION 422 UINT64_C(207618048), // STCL_POST 423 UINT64_C(224395264), // STCL_PRE 424 UINT64_C(218103808), // STC_OFFSET 425 UINT64_C(209715200), // STC_OPTION 426 UINT64_C(203423744), // STC_POST 427 UINT64_C(220200960), // STC_PRE 428 UINT64_C(25230480), // STL 429 UINT64_C(29424784), // STLB 430 UINT64_C(25169552), // STLEX 431 UINT64_C(29363856), // STLEXB 432 UINT64_C(27266704), // STLEXD 433 UINT64_C(31461008), // STLEXH 434 UINT64_C(31521936), // STLH 435 UINT64_C(134217728), // STMDA 436 UINT64_C(136314880), // STMDA_UPD 437 UINT64_C(150994944), // STMDB 438 UINT64_C(153092096), // STMDB_UPD 439 UINT64_C(142606336), // STMIA 440 UINT64_C(144703488), // STMIA_UPD 441 UINT64_C(159383552), // STMIB 442 UINT64_C(161480704), // STMIB_UPD 443 UINT64_C(0), 444 UINT64_C(73400320), // STRBT_POST_IMM 445 UINT64_C(106954752), // STRBT_POST_REG 446 UINT64_C(71303168), // STRB_POST_IMM 447 UINT64_C(104857600), // STRB_POST_REG 448 UINT64_C(90177536), // STRB_PRE_IMM 449 UINT64_C(123731968), // STRB_PRE_REG 450 UINT64_C(88080384), // STRBi12 451 UINT64_C(0), 452 UINT64_C(0), 453 UINT64_C(121634816), // STRBrs 454 UINT64_C(16777456), // STRD 455 UINT64_C(240), // STRD_POST 456 UINT64_C(18874608), // STRD_PRE 457 UINT64_C(25169808), // STREX 458 UINT64_C(29364112), // STREXB 459 UINT64_C(27266960), // STREXD 460 UINT64_C(31461264), // STREXH 461 UINT64_C(16777392), // STRH 462 UINT64_C(6291632), // STRHTi 463 UINT64_C(2097328), // STRHTr 464 UINT64_C(176), // STRH_POST 465 UINT64_C(18874544), // STRH_PRE 466 UINT64_C(0), 467 UINT64_C(0), 468 UINT64_C(69206016), // STRT_POST_IMM 469 UINT64_C(102760448), // STRT_POST_REG 470 UINT64_C(67108864), // STR_POST_IMM 471 UINT64_C(100663296), // STR_POST_REG 472 UINT64_C(85983232), // STR_PRE_IMM 473 UINT64_C(119537664), // STR_PRE_REG 474 UINT64_C(83886080), // STRi12 475 UINT64_C(0), 476 UINT64_C(0), 477 UINT64_C(117440512), // STRrs 478 UINT64_C(0), 479 UINT64_C(0), 480 UINT64_C(0), 481 UINT64_C(0), 482 UINT64_C(0), 483 UINT64_C(37748736), // SUBri 484 UINT64_C(4194304), // SUBrr 485 UINT64_C(4194304), // SUBrsi 486 UINT64_C(4194320), // SUBrsr 487 UINT64_C(251658240), // SVC 488 UINT64_C(16777360), // SWP 489 UINT64_C(20971664), // SWPB 490 UINT64_C(111149168), // SXTAB 491 UINT64_C(109052016), // SXTAB16 492 UINT64_C(112197744), // SXTAH 493 UINT64_C(112132208), // SXTB 494 UINT64_C(110035056), // SXTB16 495 UINT64_C(113180784), // SXTH 496 UINT64_C(0), 497 UINT64_C(0), 498 UINT64_C(0), 499 UINT64_C(0), 500 UINT64_C(53477376), // TEQri 501 UINT64_C(19922944), // TEQrr 502 UINT64_C(19922944), // TEQrsi 503 UINT64_C(19922960), // TEQrsr 504 UINT64_C(0), 505 UINT64_C(3892305662), // TRAP 506 UINT64_C(3892240112), // TRAPNaCl 507 UINT64_C(51380224), // TSTri 508 UINT64_C(17825792), // TSTrr 509 UINT64_C(17825792), // TSTrsi 510 UINT64_C(17825808), // TSTrsr 511 UINT64_C(105910032), // UADD16 512 UINT64_C(105910160), // UADD8 513 UINT64_C(105910064), // UASX 514 UINT64_C(132120656), // UBFX 515 UINT64_C(3891265776), // UDF 516 UINT64_C(120647696), // UDIV 517 UINT64_C(108007184), // UHADD16 518 UINT64_C(108007312), // UHADD8 519 UINT64_C(108007216), // UHASX 520 UINT64_C(108007248), // UHSAX 521 UINT64_C(108007280), // UHSUB16 522 UINT64_C(108007408), // UHSUB8 523 UINT64_C(4194448), // UMAAL 524 UINT64_C(10485904), // UMLAL 525 UINT64_C(0), 526 UINT64_C(8388752), // UMULL 527 UINT64_C(0), 528 UINT64_C(106958608), // UQADD16 529 UINT64_C(106958736), // UQADD8 530 UINT64_C(106958640), // UQASX 531 UINT64_C(106958672), // UQSAX 532 UINT64_C(106958704), // UQSUB16 533 UINT64_C(106958832), // UQSUB8 534 UINT64_C(125890576), // USAD8 535 UINT64_C(125829136), // USADA8 536 UINT64_C(115343376), // USAT 537 UINT64_C(115347248), // USAT16 538 UINT64_C(105910096), // USAX 539 UINT64_C(105910128), // USUB16 540 UINT64_C(105910256), // USUB8 541 UINT64_C(115343472), // UXTAB 542 UINT64_C(113246320), // UXTAB16 543 UINT64_C(116392048), // UXTAH 544 UINT64_C(116326512), // UXTB 545 UINT64_C(114229360), // UXTB16 546 UINT64_C(117375088), // UXTH 547 UINT64_C(4070573312), // VABALsv2i64 548 UINT64_C(4069524736), // VABALsv4i32 549 UINT64_C(4068476160), // VABALsv8i16 550 UINT64_C(4087350528), // VABALuv2i64 551 UINT64_C(4086301952), // VABALuv4i32 552 UINT64_C(4085253376), // VABALuv8i16 553 UINT64_C(4060088144), // VABAsv16i8 554 UINT64_C(4062185232), // VABAsv2i32 555 UINT64_C(4061136656), // VABAsv4i16 556 UINT64_C(4062185296), // VABAsv4i32 557 UINT64_C(4061136720), // VABAsv8i16 558 UINT64_C(4060088080), // VABAsv8i8 559 UINT64_C(4076865360), // VABAuv16i8 560 UINT64_C(4078962448), // VABAuv2i32 561 UINT64_C(4077913872), // VABAuv4i16 562 UINT64_C(4078962512), // VABAuv4i32 563 UINT64_C(4077913936), // VABAuv8i16 564 UINT64_C(4076865296), // VABAuv8i8 565 UINT64_C(4070573824), // VABDLsv2i64 566 UINT64_C(4069525248), // VABDLsv4i32 567 UINT64_C(4068476672), // VABDLsv8i16 568 UINT64_C(4087351040), // VABDLuv2i64 569 UINT64_C(4086302464), // VABDLuv4i32 570 UINT64_C(4085253888), // VABDLuv8i16 571 UINT64_C(4078963968), // VABDfd 572 UINT64_C(4078964032), // VABDfq 573 UINT64_C(4080012544), // VABDhd 574 UINT64_C(4080012608), // VABDhq 575 UINT64_C(4060088128), // VABDsv16i8 576 UINT64_C(4062185216), // VABDsv2i32 577 UINT64_C(4061136640), // VABDsv4i16 578 UINT64_C(4062185280), // VABDsv4i32 579 UINT64_C(4061136704), // VABDsv8i16 580 UINT64_C(4060088064), // VABDsv8i8 581 UINT64_C(4076865344), // VABDuv16i8 582 UINT64_C(4078962432), // VABDuv2i32 583 UINT64_C(4077913856), // VABDuv4i16 584 UINT64_C(4078962496), // VABDuv4i32 585 UINT64_C(4077913920), // VABDuv8i16 586 UINT64_C(4076865280), // VABDuv8i8 587 UINT64_C(246418368), // VABSD 588 UINT64_C(246417856), // VABSH 589 UINT64_C(246418112), // VABSS 590 UINT64_C(4088989440), // VABSfd 591 UINT64_C(4088989504), // VABSfq 592 UINT64_C(4088727296), // VABShd 593 UINT64_C(4088727360), // VABShq 594 UINT64_C(4088464192), // VABSv16i8 595 UINT64_C(4088988416), // VABSv2i32 596 UINT64_C(4088726272), // VABSv4i16 597 UINT64_C(4088988480), // VABSv4i32 598 UINT64_C(4088726336), // VABSv8i16 599 UINT64_C(4088464128), // VABSv8i8 600 UINT64_C(4076867088), // VACGEfd 601 UINT64_C(4076867152), // VACGEfq 602 UINT64_C(4077915664), // VACGEhd 603 UINT64_C(4077915728), // VACGEhq 604 UINT64_C(4078964240), // VACGTfd 605 UINT64_C(4078964304), // VACGTfq 606 UINT64_C(4080012816), // VACGThd 607 UINT64_C(4080012880), // VACGThq 608 UINT64_C(238029568), // VADDD 609 UINT64_C(238029056), // VADDH 610 UINT64_C(4070573056), // VADDHNv2i32 611 UINT64_C(4069524480), // VADDHNv4i16 612 UINT64_C(4068475904), // VADDHNv8i8 613 UINT64_C(4070572032), // VADDLsv2i64 614 UINT64_C(4069523456), // VADDLsv4i32 615 UINT64_C(4068474880), // VADDLsv8i16 616 UINT64_C(4087349248), // VADDLuv2i64 617 UINT64_C(4086300672), // VADDLuv4i32 618 UINT64_C(4085252096), // VADDLuv8i16 619 UINT64_C(238029312), // VADDS 620 UINT64_C(4070572288), // VADDWsv2i64 621 UINT64_C(4069523712), // VADDWsv4i32 622 UINT64_C(4068475136), // VADDWsv8i16 623 UINT64_C(4087349504), // VADDWuv2i64 624 UINT64_C(4086300928), // VADDWuv4i32 625 UINT64_C(4085252352), // VADDWuv8i16 626 UINT64_C(4060089600), // VADDfd 627 UINT64_C(4060089664), // VADDfq 628 UINT64_C(4061138176), // VADDhd 629 UINT64_C(4061138240), // VADDhq 630 UINT64_C(4060088384), // VADDv16i8 631 UINT64_C(4063234048), // VADDv1i64 632 UINT64_C(4062185472), // VADDv2i32 633 UINT64_C(4063234112), // VADDv2i64 634 UINT64_C(4061136896), // VADDv4i16 635 UINT64_C(4062185536), // VADDv4i32 636 UINT64_C(4061136960), // VADDv8i16 637 UINT64_C(4060088320), // VADDv8i8 638 UINT64_C(4060086544), // VANDd 639 UINT64_C(4060086608), // VANDq 640 UINT64_C(4061135120), // VBICd 641 UINT64_C(4068475184), // VBICiv2i32 642 UINT64_C(4068477232), // VBICiv4i16 643 UINT64_C(4068475248), // VBICiv4i32 644 UINT64_C(4068477296), // VBICiv8i16 645 UINT64_C(4061135184), // VBICq 646 UINT64_C(4080009488), // VBIFd 647 UINT64_C(4080009552), // VBIFq 648 UINT64_C(4078960912), // VBITd 649 UINT64_C(4078960976), // VBITq 650 UINT64_C(4077912336), // VBSLd 651 UINT64_C(4077912400), // VBSLq 652 UINT64_C(4060089856), // VCEQfd 653 UINT64_C(4060089920), // VCEQfq 654 UINT64_C(4061138432), // VCEQhd 655 UINT64_C(4061138496), // VCEQhq 656 UINT64_C(4076865616), // VCEQv16i8 657 UINT64_C(4078962704), // VCEQv2i32 658 UINT64_C(4077914128), // VCEQv4i16 659 UINT64_C(4078962768), // VCEQv4i32 660 UINT64_C(4077914192), // VCEQv8i16 661 UINT64_C(4076865552), // VCEQv8i8 662 UINT64_C(4088463680), // VCEQzv16i8 663 UINT64_C(4088988928), // VCEQzv2f32 664 UINT64_C(4088987904), // VCEQzv2i32 665 UINT64_C(4088726784), // VCEQzv4f16 666 UINT64_C(4088988992), // VCEQzv4f32 667 UINT64_C(4088725760), // VCEQzv4i16 668 UINT64_C(4088987968), // VCEQzv4i32 669 UINT64_C(4088726848), // VCEQzv8f16 670 UINT64_C(4088725824), // VCEQzv8i16 671 UINT64_C(4088463616), // VCEQzv8i8 672 UINT64_C(4076867072), // VCGEfd 673 UINT64_C(4076867136), // VCGEfq 674 UINT64_C(4077915648), // VCGEhd 675 UINT64_C(4077915712), // VCGEhq 676 UINT64_C(4060087120), // VCGEsv16i8 677 UINT64_C(4062184208), // VCGEsv2i32 678 UINT64_C(4061135632), // VCGEsv4i16 679 UINT64_C(4062184272), // VCGEsv4i32 680 UINT64_C(4061135696), // VCGEsv8i16 681 UINT64_C(4060087056), // VCGEsv8i8 682 UINT64_C(4076864336), // VCGEuv16i8 683 UINT64_C(4078961424), // VCGEuv2i32 684 UINT64_C(4077912848), // VCGEuv4i16 685 UINT64_C(4078961488), // VCGEuv4i32 686 UINT64_C(4077912912), // VCGEuv8i16 687 UINT64_C(4076864272), // VCGEuv8i8 688 UINT64_C(4088463552), // VCGEzv16i8 689 UINT64_C(4088988800), // VCGEzv2f32 690 UINT64_C(4088987776), // VCGEzv2i32 691 UINT64_C(4088726656), // VCGEzv4f16 692 UINT64_C(4088988864), // VCGEzv4f32 693 UINT64_C(4088725632), // VCGEzv4i16 694 UINT64_C(4088987840), // VCGEzv4i32 695 UINT64_C(4088726720), // VCGEzv8f16 696 UINT64_C(4088725696), // VCGEzv8i16 697 UINT64_C(4088463488), // VCGEzv8i8 698 UINT64_C(4078964224), // VCGTfd 699 UINT64_C(4078964288), // VCGTfq 700 UINT64_C(4080012800), // VCGThd 701 UINT64_C(4080012864), // VCGThq 702 UINT64_C(4060087104), // VCGTsv16i8 703 UINT64_C(4062184192), // VCGTsv2i32 704 UINT64_C(4061135616), // VCGTsv4i16 705 UINT64_C(4062184256), // VCGTsv4i32 706 UINT64_C(4061135680), // VCGTsv8i16 707 UINT64_C(4060087040), // VCGTsv8i8 708 UINT64_C(4076864320), // VCGTuv16i8 709 UINT64_C(4078961408), // VCGTuv2i32 710 UINT64_C(4077912832), // VCGTuv4i16 711 UINT64_C(4078961472), // VCGTuv4i32 712 UINT64_C(4077912896), // VCGTuv8i16 713 UINT64_C(4076864256), // VCGTuv8i8 714 UINT64_C(4088463424), // VCGTzv16i8 715 UINT64_C(4088988672), // VCGTzv2f32 716 UINT64_C(4088987648), // VCGTzv2i32 717 UINT64_C(4088726528), // VCGTzv4f16 718 UINT64_C(4088988736), // VCGTzv4f32 719 UINT64_C(4088725504), // VCGTzv4i16 720 UINT64_C(4088987712), // VCGTzv4i32 721 UINT64_C(4088726592), // VCGTzv8f16 722 UINT64_C(4088725568), // VCGTzv8i16 723 UINT64_C(4088463360), // VCGTzv8i8 724 UINT64_C(4088463808), // VCLEzv16i8 725 UINT64_C(4088989056), // VCLEzv2f32 726 UINT64_C(4088988032), // VCLEzv2i32 727 UINT64_C(4088726912), // VCLEzv4f16 728 UINT64_C(4088989120), // VCLEzv4f32 729 UINT64_C(4088725888), // VCLEzv4i16 730 UINT64_C(4088988096), // VCLEzv4i32 731 UINT64_C(4088726976), // VCLEzv8f16 732 UINT64_C(4088725952), // VCLEzv8i16 733 UINT64_C(4088463744), // VCLEzv8i8 734 UINT64_C(4088398912), // VCLSv16i8 735 UINT64_C(4088923136), // VCLSv2i32 736 UINT64_C(4088660992), // VCLSv4i16 737 UINT64_C(4088923200), // VCLSv4i32 738 UINT64_C(4088661056), // VCLSv8i16 739 UINT64_C(4088398848), // VCLSv8i8 740 UINT64_C(4088463936), // VCLTzv16i8 741 UINT64_C(4088989184), // VCLTzv2f32 742 UINT64_C(4088988160), // VCLTzv2i32 743 UINT64_C(4088727040), // VCLTzv4f16 744 UINT64_C(4088989248), // VCLTzv4f32 745 UINT64_C(4088726016), // VCLTzv4i16 746 UINT64_C(4088988224), // VCLTzv4i32 747 UINT64_C(4088727104), // VCLTzv8f16 748 UINT64_C(4088726080), // VCLTzv8i16 749 UINT64_C(4088463872), // VCLTzv8i8 750 UINT64_C(4088399040), // VCLZv16i8 751 UINT64_C(4088923264), // VCLZv2i32 752 UINT64_C(4088661120), // VCLZv4i16 753 UINT64_C(4088923328), // VCLZv4i32 754 UINT64_C(4088661184), // VCLZv8i16 755 UINT64_C(4088398976), // VCLZv8i8 756 UINT64_C(246680384), // VCMPD 757 UINT64_C(246680512), // VCMPED 758 UINT64_C(246680000), // VCMPEH 759 UINT64_C(246680256), // VCMPES 760 UINT64_C(246746048), // VCMPEZD 761 UINT64_C(246745536), // VCMPEZH 762 UINT64_C(246745792), // VCMPEZS 763 UINT64_C(246679872), // VCMPH 764 UINT64_C(246680128), // VCMPS 765 UINT64_C(246745920), // VCMPZD 766 UINT64_C(246745408), // VCMPZH 767 UINT64_C(246745664), // VCMPZS 768 UINT64_C(4088399104), // VCNTd 769 UINT64_C(4088399168), // VCNTq 770 UINT64_C(4089118720), // VCVTANSDf 771 UINT64_C(4088856576), // VCVTANSDh 772 UINT64_C(4089118784), // VCVTANSQf 773 UINT64_C(4088856640), // VCVTANSQh 774 UINT64_C(4089118848), // VCVTANUDf 775 UINT64_C(4088856704), // VCVTANUDh 776 UINT64_C(4089118912), // VCVTANUQf 777 UINT64_C(4088856768), // VCVTANUQh 778 UINT64_C(4273736640), // VCVTASD 779 UINT64_C(4273736128), // VCVTASH 780 UINT64_C(4273736384), // VCVTASS 781 UINT64_C(4273736512), // VCVTAUD 782 UINT64_C(4273736000), // VCVTAUH 783 UINT64_C(4273736256), // VCVTAUS 784 UINT64_C(246614848), // VCVTBDH 785 UINT64_C(246549312), // VCVTBHD 786 UINT64_C(246549056), // VCVTBHS 787 UINT64_C(246614592), // VCVTBSH 788 UINT64_C(246876864), // VCVTDS 789 UINT64_C(4089119488), // VCVTMNSDf 790 UINT64_C(4088857344), // VCVTMNSDh 791 UINT64_C(4089119552), // VCVTMNSQf 792 UINT64_C(4088857408), // VCVTMNSQh 793 UINT64_C(4089119616), // VCVTMNUDf 794 UINT64_C(4088857472), // VCVTMNUDh 795 UINT64_C(4089119680), // VCVTMNUQf 796 UINT64_C(4088857536), // VCVTMNUQh 797 UINT64_C(4273933248), // VCVTMSD 798 UINT64_C(4273932736), // VCVTMSH 799 UINT64_C(4273932992), // VCVTMSS 800 UINT64_C(4273933120), // VCVTMUD 801 UINT64_C(4273932608), // VCVTMUH 802 UINT64_C(4273932864), // VCVTMUS 803 UINT64_C(4089118976), // VCVTNNSDf 804 UINT64_C(4088856832), // VCVTNNSDh 805 UINT64_C(4089119040), // VCVTNNSQf 806 UINT64_C(4088856896), // VCVTNNSQh 807 UINT64_C(4089119104), // VCVTNNUDf 808 UINT64_C(4088856960), // VCVTNNUDh 809 UINT64_C(4089119168), // VCVTNNUQf 810 UINT64_C(4088857024), // VCVTNNUQh 811 UINT64_C(4273802176), // VCVTNSD 812 UINT64_C(4273801664), // VCVTNSH 813 UINT64_C(4273801920), // VCVTNSS 814 UINT64_C(4273802048), // VCVTNUD 815 UINT64_C(4273801536), // VCVTNUH 816 UINT64_C(4273801792), // VCVTNUS 817 UINT64_C(4089119232), // VCVTPNSDf 818 UINT64_C(4088857088), // VCVTPNSDh 819 UINT64_C(4089119296), // VCVTPNSQf 820 UINT64_C(4088857152), // VCVTPNSQh 821 UINT64_C(4089119360), // VCVTPNUDf 822 UINT64_C(4088857216), // VCVTPNUDh 823 UINT64_C(4089119424), // VCVTPNUQf 824 UINT64_C(4088857280), // VCVTPNUQh 825 UINT64_C(4273867712), // VCVTPSD 826 UINT64_C(4273867200), // VCVTPSH 827 UINT64_C(4273867456), // VCVTPSS 828 UINT64_C(4273867584), // VCVTPUD 829 UINT64_C(4273867072), // VCVTPUH 830 UINT64_C(4273867328), // VCVTPUS 831 UINT64_C(246877120), // VCVTSD 832 UINT64_C(246614976), // VCVTTDH 833 UINT64_C(246549440), // VCVTTHD 834 UINT64_C(246549184), // VCVTTHS 835 UINT64_C(246614720), // VCVTTSH 836 UINT64_C(4088792576), // VCVTf2h 837 UINT64_C(4089120512), // VCVTf2sd 838 UINT64_C(4089120576), // VCVTf2sq 839 UINT64_C(4089120640), // VCVTf2ud 840 UINT64_C(4089120704), // VCVTf2uq 841 UINT64_C(4068478736), // VCVTf2xsd 842 UINT64_C(4068478800), // VCVTf2xsq 843 UINT64_C(4085255952), // VCVTf2xud 844 UINT64_C(4085256016), // VCVTf2xuq 845 UINT64_C(4088792832), // VCVTh2f 846 UINT64_C(4088858368), // VCVTh2sd 847 UINT64_C(4088858432), // VCVTh2sq 848 UINT64_C(4088858496), // VCVTh2ud 849 UINT64_C(4088858560), // VCVTh2uq 850 UINT64_C(4068478224), // VCVTh2xsd 851 UINT64_C(4068478288), // VCVTh2xsq 852 UINT64_C(4085255440), // VCVTh2xud 853 UINT64_C(4085255504), // VCVTh2xuq 854 UINT64_C(4089120256), // VCVTs2fd 855 UINT64_C(4089120320), // VCVTs2fq 856 UINT64_C(4088858112), // VCVTs2hd 857 UINT64_C(4088858176), // VCVTs2hq 858 UINT64_C(4089120384), // VCVTu2fd 859 UINT64_C(4089120448), // VCVTu2fq 860 UINT64_C(4088858240), // VCVTu2hd 861 UINT64_C(4088858304), // VCVTu2hq 862 UINT64_C(4068478480), // VCVTxs2fd 863 UINT64_C(4068478544), // VCVTxs2fq 864 UINT64_C(4068477968), // VCVTxs2hd 865 UINT64_C(4068478032), // VCVTxs2hq 866 UINT64_C(4085255696), // VCVTxu2fd 867 UINT64_C(4085255760), // VCVTxu2fq 868 UINT64_C(4085255184), // VCVTxu2hd 869 UINT64_C(4085255248), // VCVTxu2hq 870 UINT64_C(243272448), // VDIVD 871 UINT64_C(243271936), // VDIVH 872 UINT64_C(243272192), // VDIVS 873 UINT64_C(243272496), // VDUP16d 874 UINT64_C(245369648), // VDUP16q 875 UINT64_C(243272464), // VDUP32d 876 UINT64_C(245369616), // VDUP32q 877 UINT64_C(247466768), // VDUP8d 878 UINT64_C(249563920), // VDUP8q 879 UINT64_C(4088531968), // VDUPLN16d 880 UINT64_C(4088532032), // VDUPLN16q 881 UINT64_C(4088663040), // VDUPLN32d 882 UINT64_C(4088663104), // VDUPLN32q 883 UINT64_C(4088466432), // VDUPLN8d 884 UINT64_C(4088466496), // VDUPLN8q 885 UINT64_C(4076863760), // VEORd 886 UINT64_C(4076863824), // VEORq 887 UINT64_C(4071620608), // VEXTd16 888 UINT64_C(4071620608), // VEXTd32 889 UINT64_C(4071620608), // VEXTd8 890 UINT64_C(4071620672), // VEXTq16 891 UINT64_C(4071620672), // VEXTq32 892 UINT64_C(4071620672), // VEXTq64 893 UINT64_C(4071620672), // VEXTq8 894 UINT64_C(245369600), // VFMAD 895 UINT64_C(245369088), // VFMAH 896 UINT64_C(245369344), // VFMAS 897 UINT64_C(4060089360), // VFMAfd 898 UINT64_C(4060089424), // VFMAfq 899 UINT64_C(4061137936), // VFMAhd 900 UINT64_C(4061138000), // VFMAhq 901 UINT64_C(245369664), // VFMSD 902 UINT64_C(245369152), // VFMSH 903 UINT64_C(245369408), // VFMSS 904 UINT64_C(4062186512), // VFMSfd 905 UINT64_C(4062186576), // VFMSfq 906 UINT64_C(4063235088), // VFMShd 907 UINT64_C(4063235152), // VFMShq 908 UINT64_C(244321088), // VFNMAD 909 UINT64_C(244320576), // VFNMAH 910 UINT64_C(244320832), // VFNMAS 911 UINT64_C(244321024), // VFNMSD 912 UINT64_C(244320512), // VFNMSH 913 UINT64_C(244320768), // VFNMSS 914 UINT64_C(235932432), // VGETLNi32 915 UINT64_C(235932464), // VGETLNs16 916 UINT64_C(240126736), // VGETLNs8 917 UINT64_C(244321072), // VGETLNu16 918 UINT64_C(248515344), // VGETLNu8 919 UINT64_C(4060086336), // VHADDsv16i8 920 UINT64_C(4062183424), // VHADDsv2i32 921 UINT64_C(4061134848), // VHADDsv4i16 922 UINT64_C(4062183488), // VHADDsv4i32 923 UINT64_C(4061134912), // VHADDsv8i16 924 UINT64_C(4060086272), // VHADDsv8i8 925 UINT64_C(4076863552), // VHADDuv16i8 926 UINT64_C(4078960640), // VHADDuv2i32 927 UINT64_C(4077912064), // VHADDuv4i16 928 UINT64_C(4078960704), // VHADDuv4i32 929 UINT64_C(4077912128), // VHADDuv8i16 930 UINT64_C(4076863488), // VHADDuv8i8 931 UINT64_C(4060086848), // VHSUBsv16i8 932 UINT64_C(4062183936), // VHSUBsv2i32 933 UINT64_C(4061135360), // VHSUBsv4i16 934 UINT64_C(4062184000), // VHSUBsv4i32 935 UINT64_C(4061135424), // VHSUBsv8i16 936 UINT64_C(4060086784), // VHSUBsv8i8 937 UINT64_C(4076864064), // VHSUBuv16i8 938 UINT64_C(4078961152), // VHSUBuv2i32 939 UINT64_C(4077912576), // VHSUBuv4i16 940 UINT64_C(4078961216), // VHSUBuv4i32 941 UINT64_C(4077912640), // VHSUBuv8i16 942 UINT64_C(4076864000), // VHSUBuv8i8 943 UINT64_C(4272949952), // VINSH 944 UINT64_C(4104129615), // VLD1DUPd16 945 UINT64_C(4104129613), // VLD1DUPd16wb_fixed 946 UINT64_C(4104129600), // VLD1DUPd16wb_register 947 UINT64_C(4104129679), // VLD1DUPd32 948 UINT64_C(4104129677), // VLD1DUPd32wb_fixed 949 UINT64_C(4104129664), // VLD1DUPd32wb_register 950 UINT64_C(4104129551), // VLD1DUPd8 951 UINT64_C(4104129549), // VLD1DUPd8wb_fixed 952 UINT64_C(4104129536), // VLD1DUPd8wb_register 953 UINT64_C(4104129647), // VLD1DUPq16 954 UINT64_C(4104129645), // VLD1DUPq16wb_fixed 955 UINT64_C(4104129632), // VLD1DUPq16wb_register 956 UINT64_C(4104129711), // VLD1DUPq32 957 UINT64_C(4104129709), // VLD1DUPq32wb_fixed 958 UINT64_C(4104129696), // VLD1DUPq32wb_register 959 UINT64_C(4104129583), // VLD1DUPq8 960 UINT64_C(4104129581), // VLD1DUPq8wb_fixed 961 UINT64_C(4104129568), // VLD1DUPq8wb_register 962 UINT64_C(4104127503), // VLD1LNd16 963 UINT64_C(4104127488), // VLD1LNd16_UPD 964 UINT64_C(4104128527), // VLD1LNd32 965 UINT64_C(4104128512), // VLD1LNd32_UPD 966 UINT64_C(4104126479), // VLD1LNd8 967 UINT64_C(4104126464), // VLD1LNd8_UPD 968 UINT64_C(0), 969 UINT64_C(0), 970 UINT64_C(0), 971 UINT64_C(0), 972 UINT64_C(0), 973 UINT64_C(0), 974 UINT64_C(0), 975 UINT64_C(0), 976 UINT64_C(0), 977 UINT64_C(0), // VLD1LNq16Pseudo 978 UINT64_C(0), // VLD1LNq16Pseudo_UPD 979 UINT64_C(0), // VLD1LNq32Pseudo 980 UINT64_C(0), // VLD1LNq32Pseudo_UPD 981 UINT64_C(0), // VLD1LNq8Pseudo 982 UINT64_C(0), // VLD1LNq8Pseudo_UPD 983 UINT64_C(4095739727), // VLD1d16 984 UINT64_C(4095738447), // VLD1d16Q 985 UINT64_C(4095738445), // VLD1d16Qwb_fixed 986 UINT64_C(4095738432), // VLD1d16Qwb_register 987 UINT64_C(4095739471), // VLD1d16T 988 UINT64_C(4095739469), // VLD1d16Twb_fixed 989 UINT64_C(4095739456), // VLD1d16Twb_register 990 UINT64_C(4095739725), // VLD1d16wb_fixed 991 UINT64_C(4095739712), // VLD1d16wb_register 992 UINT64_C(4095739791), // VLD1d32 993 UINT64_C(4095738511), // VLD1d32Q 994 UINT64_C(4095738509), // VLD1d32Qwb_fixed 995 UINT64_C(4095738496), // VLD1d32Qwb_register 996 UINT64_C(4095739535), // VLD1d32T 997 UINT64_C(4095739533), // VLD1d32Twb_fixed 998 UINT64_C(4095739520), // VLD1d32Twb_register 999 UINT64_C(4095739789), // VLD1d32wb_fixed 1000 UINT64_C(4095739776), // VLD1d32wb_register 1001 UINT64_C(4095739855), // VLD1d64 1002 UINT64_C(4095738575), // VLD1d64Q 1003 UINT64_C(0), // VLD1d64QPseudo 1004 UINT64_C(0), // VLD1d64QPseudoWB_fixed 1005 UINT64_C(0), // VLD1d64QPseudoWB_register 1006 UINT64_C(4095738573), // VLD1d64Qwb_fixed 1007 UINT64_C(4095738560), // VLD1d64Qwb_register 1008 UINT64_C(4095739599), // VLD1d64T 1009 UINT64_C(0), // VLD1d64TPseudo 1010 UINT64_C(0), // VLD1d64TPseudoWB_fixed 1011 UINT64_C(0), // VLD1d64TPseudoWB_register 1012 UINT64_C(4095739597), // VLD1d64Twb_fixed 1013 UINT64_C(4095739584), // VLD1d64Twb_register 1014 UINT64_C(4095739853), // VLD1d64wb_fixed 1015 UINT64_C(4095739840), // VLD1d64wb_register 1016 UINT64_C(4095739663), // VLD1d8 1017 UINT64_C(4095738383), // VLD1d8Q 1018 UINT64_C(4095738381), // VLD1d8Qwb_fixed 1019 UINT64_C(4095738368), // VLD1d8Qwb_register 1020 UINT64_C(4095739407), // VLD1d8T 1021 UINT64_C(4095739405), // VLD1d8Twb_fixed 1022 UINT64_C(4095739392), // VLD1d8Twb_register 1023 UINT64_C(4095739661), // VLD1d8wb_fixed 1024 UINT64_C(4095739648), // VLD1d8wb_register 1025 UINT64_C(4095740495), // VLD1q16 1026 UINT64_C(4095740493), // VLD1q16wb_fixed 1027 UINT64_C(4095740480), // VLD1q16wb_register 1028 UINT64_C(4095740559), // VLD1q32 1029 UINT64_C(4095740557), // VLD1q32wb_fixed 1030 UINT64_C(4095740544), // VLD1q32wb_register 1031 UINT64_C(4095740623), // VLD1q64 1032 UINT64_C(4095740621), // VLD1q64wb_fixed 1033 UINT64_C(4095740608), // VLD1q64wb_register 1034 UINT64_C(4095740431), // VLD1q8 1035 UINT64_C(4095740429), // VLD1q8wb_fixed 1036 UINT64_C(4095740416), // VLD1q8wb_register 1037 UINT64_C(4104129871), // VLD2DUPd16 1038 UINT64_C(4104129869), // VLD2DUPd16wb_fixed 1039 UINT64_C(4104129856), // VLD2DUPd16wb_register 1040 UINT64_C(4104129903), // VLD2DUPd16x2 1041 UINT64_C(4104129901), // VLD2DUPd16x2wb_fixed 1042 UINT64_C(4104129888), // VLD2DUPd16x2wb_register 1043 UINT64_C(4104129935), // VLD2DUPd32 1044 UINT64_C(4104129933), // VLD2DUPd32wb_fixed 1045 UINT64_C(4104129920), // VLD2DUPd32wb_register 1046 UINT64_C(4104129967), // VLD2DUPd32x2 1047 UINT64_C(4104129965), // VLD2DUPd32x2wb_fixed 1048 UINT64_C(4104129952), // VLD2DUPd32x2wb_register 1049 UINT64_C(4104129807), // VLD2DUPd8 1050 UINT64_C(4104129805), // VLD2DUPd8wb_fixed 1051 UINT64_C(4104129792), // VLD2DUPd8wb_register 1052 UINT64_C(4104129839), // VLD2DUPd8x2 1053 UINT64_C(4104129837), // VLD2DUPd8x2wb_fixed 1054 UINT64_C(4104129824), // VLD2DUPd8x2wb_register 1055 UINT64_C(4104127759), // VLD2LNd16 1056 UINT64_C(0), // VLD2LNd16Pseudo 1057 UINT64_C(0), // VLD2LNd16Pseudo_UPD 1058 UINT64_C(4104127744), // VLD2LNd16_UPD 1059 UINT64_C(4104128783), // VLD2LNd32 1060 UINT64_C(0), // VLD2LNd32Pseudo 1061 UINT64_C(0), // VLD2LNd32Pseudo_UPD 1062 UINT64_C(4104128768), // VLD2LNd32_UPD 1063 UINT64_C(4104126735), // VLD2LNd8 1064 UINT64_C(0), // VLD2LNd8Pseudo 1065 UINT64_C(0), // VLD2LNd8Pseudo_UPD 1066 UINT64_C(4104126720), // VLD2LNd8_UPD 1067 UINT64_C(0), 1068 UINT64_C(0), 1069 UINT64_C(0), 1070 UINT64_C(0), 1071 UINT64_C(0), 1072 UINT64_C(0), 1073 UINT64_C(0), 1074 UINT64_C(0), 1075 UINT64_C(0), 1076 UINT64_C(4104127791), // VLD2LNq16 1077 UINT64_C(0), // VLD2LNq16Pseudo 1078 UINT64_C(0), // VLD2LNq16Pseudo_UPD 1079 UINT64_C(4104127776), // VLD2LNq16_UPD 1080 UINT64_C(4104128847), // VLD2LNq32 1081 UINT64_C(0), // VLD2LNq32Pseudo 1082 UINT64_C(0), // VLD2LNq32Pseudo_UPD 1083 UINT64_C(4104128832), // VLD2LNq32_UPD 1084 UINT64_C(0), 1085 UINT64_C(0), 1086 UINT64_C(0), 1087 UINT64_C(0), 1088 UINT64_C(0), 1089 UINT64_C(0), 1090 UINT64_C(4095740239), // VLD2b16 1091 UINT64_C(4095740237), // VLD2b16wb_fixed 1092 UINT64_C(4095740224), // VLD2b16wb_register 1093 UINT64_C(4095740303), // VLD2b32 1094 UINT64_C(4095740301), // VLD2b32wb_fixed 1095 UINT64_C(4095740288), // VLD2b32wb_register 1096 UINT64_C(4095740175), // VLD2b8 1097 UINT64_C(4095740173), // VLD2b8wb_fixed 1098 UINT64_C(4095740160), // VLD2b8wb_register 1099 UINT64_C(4095739983), // VLD2d16 1100 UINT64_C(4095739981), // VLD2d16wb_fixed 1101 UINT64_C(4095739968), // VLD2d16wb_register 1102 UINT64_C(4095740047), // VLD2d32 1103 UINT64_C(4095740045), // VLD2d32wb_fixed 1104 UINT64_C(4095740032), // VLD2d32wb_register 1105 UINT64_C(4095739919), // VLD2d8 1106 UINT64_C(4095739917), // VLD2d8wb_fixed 1107 UINT64_C(4095739904), // VLD2d8wb_register 1108 UINT64_C(4095738703), // VLD2q16 1109 UINT64_C(0), // VLD2q16Pseudo 1110 UINT64_C(0), // VLD2q16PseudoWB_fixed 1111 UINT64_C(0), // VLD2q16PseudoWB_register 1112 UINT64_C(4095738701), // VLD2q16wb_fixed 1113 UINT64_C(4095738688), // VLD2q16wb_register 1114 UINT64_C(4095738767), // VLD2q32 1115 UINT64_C(0), // VLD2q32Pseudo 1116 UINT64_C(0), // VLD2q32PseudoWB_fixed 1117 UINT64_C(0), // VLD2q32PseudoWB_register 1118 UINT64_C(4095738765), // VLD2q32wb_fixed 1119 UINT64_C(4095738752), // VLD2q32wb_register 1120 UINT64_C(4095738639), // VLD2q8 1121 UINT64_C(0), // VLD2q8Pseudo 1122 UINT64_C(0), // VLD2q8PseudoWB_fixed 1123 UINT64_C(0), // VLD2q8PseudoWB_register 1124 UINT64_C(4095738637), // VLD2q8wb_fixed 1125 UINT64_C(4095738624), // VLD2q8wb_register 1126 UINT64_C(4104130127), // VLD3DUPd16 1127 UINT64_C(0), // VLD3DUPd16Pseudo 1128 UINT64_C(0), // VLD3DUPd16Pseudo_UPD 1129 UINT64_C(4104130112), // VLD3DUPd16_UPD 1130 UINT64_C(4104130191), // VLD3DUPd32 1131 UINT64_C(0), // VLD3DUPd32Pseudo 1132 UINT64_C(0), // VLD3DUPd32Pseudo_UPD 1133 UINT64_C(4104130176), // VLD3DUPd32_UPD 1134 UINT64_C(4104130063), // VLD3DUPd8 1135 UINT64_C(0), // VLD3DUPd8Pseudo 1136 UINT64_C(0), // VLD3DUPd8Pseudo_UPD 1137 UINT64_C(4104130048), // VLD3DUPd8_UPD 1138 UINT64_C(0), 1139 UINT64_C(0), 1140 UINT64_C(0), 1141 UINT64_C(0), 1142 UINT64_C(0), 1143 UINT64_C(0), 1144 UINT64_C(0), 1145 UINT64_C(0), 1146 UINT64_C(0), 1147 UINT64_C(4104130159), // VLD3DUPq16 1148 UINT64_C(4104130144), // VLD3DUPq16_UPD 1149 UINT64_C(4104130223), // VLD3DUPq32 1150 UINT64_C(4104130208), // VLD3DUPq32_UPD 1151 UINT64_C(4104130095), // VLD3DUPq8 1152 UINT64_C(4104130080), // VLD3DUPq8_UPD 1153 UINT64_C(0), 1154 UINT64_C(0), 1155 UINT64_C(0), 1156 UINT64_C(0), 1157 UINT64_C(0), 1158 UINT64_C(0), 1159 UINT64_C(0), 1160 UINT64_C(0), 1161 UINT64_C(0), 1162 UINT64_C(4104128015), // VLD3LNd16 1163 UINT64_C(0), // VLD3LNd16Pseudo 1164 UINT64_C(0), // VLD3LNd16Pseudo_UPD 1165 UINT64_C(4104128000), // VLD3LNd16_UPD 1166 UINT64_C(4104129039), // VLD3LNd32 1167 UINT64_C(0), // VLD3LNd32Pseudo 1168 UINT64_C(0), // VLD3LNd32Pseudo_UPD 1169 UINT64_C(4104129024), // VLD3LNd32_UPD 1170 UINT64_C(4104126991), // VLD3LNd8 1171 UINT64_C(0), // VLD3LNd8Pseudo 1172 UINT64_C(0), // VLD3LNd8Pseudo_UPD 1173 UINT64_C(4104126976), // VLD3LNd8_UPD 1174 UINT64_C(0), 1175 UINT64_C(0), 1176 UINT64_C(0), 1177 UINT64_C(0), 1178 UINT64_C(0), 1179 UINT64_C(0), 1180 UINT64_C(0), 1181 UINT64_C(0), 1182 UINT64_C(0), 1183 UINT64_C(4104128047), // VLD3LNq16 1184 UINT64_C(0), // VLD3LNq16Pseudo 1185 UINT64_C(0), // VLD3LNq16Pseudo_UPD 1186 UINT64_C(4104128032), // VLD3LNq16_UPD 1187 UINT64_C(4104129103), // VLD3LNq32 1188 UINT64_C(0), // VLD3LNq32Pseudo 1189 UINT64_C(0), // VLD3LNq32Pseudo_UPD 1190 UINT64_C(4104129088), // VLD3LNq32_UPD 1191 UINT64_C(0), 1192 UINT64_C(0), 1193 UINT64_C(0), 1194 UINT64_C(0), 1195 UINT64_C(0), 1196 UINT64_C(0), 1197 UINT64_C(4095738959), // VLD3d16 1198 UINT64_C(0), // VLD3d16Pseudo 1199 UINT64_C(0), // VLD3d16Pseudo_UPD 1200 UINT64_C(4095738944), // VLD3d16_UPD 1201 UINT64_C(4095739023), // VLD3d32 1202 UINT64_C(0), // VLD3d32Pseudo 1203 UINT64_C(0), // VLD3d32Pseudo_UPD 1204 UINT64_C(4095739008), // VLD3d32_UPD 1205 UINT64_C(4095738895), // VLD3d8 1206 UINT64_C(0), // VLD3d8Pseudo 1207 UINT64_C(0), // VLD3d8Pseudo_UPD 1208 UINT64_C(4095738880), // VLD3d8_UPD 1209 UINT64_C(0), 1210 UINT64_C(0), 1211 UINT64_C(0), 1212 UINT64_C(0), 1213 UINT64_C(0), 1214 UINT64_C(0), 1215 UINT64_C(0), 1216 UINT64_C(0), 1217 UINT64_C(0), 1218 UINT64_C(4095739215), // VLD3q16 1219 UINT64_C(0), // VLD3q16Pseudo_UPD 1220 UINT64_C(4095739200), // VLD3q16_UPD 1221 UINT64_C(0), // VLD3q16oddPseudo 1222 UINT64_C(0), // VLD3q16oddPseudo_UPD 1223 UINT64_C(4095739279), // VLD3q32 1224 UINT64_C(0), // VLD3q32Pseudo_UPD 1225 UINT64_C(4095739264), // VLD3q32_UPD 1226 UINT64_C(0), // VLD3q32oddPseudo 1227 UINT64_C(0), // VLD3q32oddPseudo_UPD 1228 UINT64_C(4095739151), // VLD3q8 1229 UINT64_C(0), // VLD3q8Pseudo_UPD 1230 UINT64_C(4095739136), // VLD3q8_UPD 1231 UINT64_C(0), // VLD3q8oddPseudo 1232 UINT64_C(0), // VLD3q8oddPseudo_UPD 1233 UINT64_C(0), 1234 UINT64_C(0), 1235 UINT64_C(0), 1236 UINT64_C(0), 1237 UINT64_C(0), 1238 UINT64_C(0), 1239 UINT64_C(0), 1240 UINT64_C(0), 1241 UINT64_C(0), 1242 UINT64_C(4104130383), // VLD4DUPd16 1243 UINT64_C(0), // VLD4DUPd16Pseudo 1244 UINT64_C(0), // VLD4DUPd16Pseudo_UPD 1245 UINT64_C(4104130368), // VLD4DUPd16_UPD 1246 UINT64_C(4104130447), // VLD4DUPd32 1247 UINT64_C(0), // VLD4DUPd32Pseudo 1248 UINT64_C(0), // VLD4DUPd32Pseudo_UPD 1249 UINT64_C(4104130432), // VLD4DUPd32_UPD 1250 UINT64_C(4104130319), // VLD4DUPd8 1251 UINT64_C(0), // VLD4DUPd8Pseudo 1252 UINT64_C(0), // VLD4DUPd8Pseudo_UPD 1253 UINT64_C(4104130304), // VLD4DUPd8_UPD 1254 UINT64_C(0), 1255 UINT64_C(0), 1256 UINT64_C(0), 1257 UINT64_C(0), 1258 UINT64_C(0), 1259 UINT64_C(0), 1260 UINT64_C(0), 1261 UINT64_C(0), 1262 UINT64_C(0), 1263 UINT64_C(4104130415), // VLD4DUPq16 1264 UINT64_C(4104130400), // VLD4DUPq16_UPD 1265 UINT64_C(4104130479), // VLD4DUPq32 1266 UINT64_C(4104130464), // VLD4DUPq32_UPD 1267 UINT64_C(4104130351), // VLD4DUPq8 1268 UINT64_C(4104130336), // VLD4DUPq8_UPD 1269 UINT64_C(0), 1270 UINT64_C(0), 1271 UINT64_C(0), 1272 UINT64_C(0), 1273 UINT64_C(0), 1274 UINT64_C(0), 1275 UINT64_C(0), 1276 UINT64_C(0), 1277 UINT64_C(0), 1278 UINT64_C(4104128271), // VLD4LNd16 1279 UINT64_C(0), // VLD4LNd16Pseudo 1280 UINT64_C(0), // VLD4LNd16Pseudo_UPD 1281 UINT64_C(4104128256), // VLD4LNd16_UPD 1282 UINT64_C(4104129295), // VLD4LNd32 1283 UINT64_C(0), // VLD4LNd32Pseudo 1284 UINT64_C(0), // VLD4LNd32Pseudo_UPD 1285 UINT64_C(4104129280), // VLD4LNd32_UPD 1286 UINT64_C(4104127247), // VLD4LNd8 1287 UINT64_C(0), // VLD4LNd8Pseudo 1288 UINT64_C(0), // VLD4LNd8Pseudo_UPD 1289 UINT64_C(4104127232), // VLD4LNd8_UPD 1290 UINT64_C(0), 1291 UINT64_C(0), 1292 UINT64_C(0), 1293 UINT64_C(0), 1294 UINT64_C(0), 1295 UINT64_C(0), 1296 UINT64_C(0), 1297 UINT64_C(0), 1298 UINT64_C(0), 1299 UINT64_C(4104128303), // VLD4LNq16 1300 UINT64_C(0), // VLD4LNq16Pseudo 1301 UINT64_C(0), // VLD4LNq16Pseudo_UPD 1302 UINT64_C(4104128288), // VLD4LNq16_UPD 1303 UINT64_C(4104129359), // VLD4LNq32 1304 UINT64_C(0), // VLD4LNq32Pseudo 1305 UINT64_C(0), // VLD4LNq32Pseudo_UPD 1306 UINT64_C(4104129344), // VLD4LNq32_UPD 1307 UINT64_C(0), 1308 UINT64_C(0), 1309 UINT64_C(0), 1310 UINT64_C(0), 1311 UINT64_C(0), 1312 UINT64_C(0), 1313 UINT64_C(4095737935), // VLD4d16 1314 UINT64_C(0), // VLD4d16Pseudo 1315 UINT64_C(0), // VLD4d16Pseudo_UPD 1316 UINT64_C(4095737920), // VLD4d16_UPD 1317 UINT64_C(4095737999), // VLD4d32 1318 UINT64_C(0), // VLD4d32Pseudo 1319 UINT64_C(0), // VLD4d32Pseudo_UPD 1320 UINT64_C(4095737984), // VLD4d32_UPD 1321 UINT64_C(4095737871), // VLD4d8 1322 UINT64_C(0), // VLD4d8Pseudo 1323 UINT64_C(0), // VLD4d8Pseudo_UPD 1324 UINT64_C(4095737856), // VLD4d8_UPD 1325 UINT64_C(0), 1326 UINT64_C(0), 1327 UINT64_C(0), 1328 UINT64_C(0), 1329 UINT64_C(0), 1330 UINT64_C(0), 1331 UINT64_C(0), 1332 UINT64_C(0), 1333 UINT64_C(0), 1334 UINT64_C(4095738191), // VLD4q16 1335 UINT64_C(0), // VLD4q16Pseudo_UPD 1336 UINT64_C(4095738176), // VLD4q16_UPD 1337 UINT64_C(0), // VLD4q16oddPseudo 1338 UINT64_C(0), // VLD4q16oddPseudo_UPD 1339 UINT64_C(4095738255), // VLD4q32 1340 UINT64_C(0), // VLD4q32Pseudo_UPD 1341 UINT64_C(4095738240), // VLD4q32_UPD 1342 UINT64_C(0), // VLD4q32oddPseudo 1343 UINT64_C(0), // VLD4q32oddPseudo_UPD 1344 UINT64_C(4095738127), // VLD4q8 1345 UINT64_C(0), // VLD4q8Pseudo_UPD 1346 UINT64_C(4095738112), // VLD4q8_UPD 1347 UINT64_C(0), // VLD4q8oddPseudo 1348 UINT64_C(0), // VLD4q8oddPseudo_UPD 1349 UINT64_C(0), 1350 UINT64_C(0), 1351 UINT64_C(0), 1352 UINT64_C(0), 1353 UINT64_C(0), 1354 UINT64_C(0), 1355 UINT64_C(0), 1356 UINT64_C(0), 1357 UINT64_C(0), 1358 UINT64_C(221252352), // VLDMDDB_UPD 1359 UINT64_C(210766592), // VLDMDIA 1360 UINT64_C(212863744), // VLDMDIA_UPD 1361 UINT64_C(0), // VLDMQIA 1362 UINT64_C(221252096), // VLDMSDB_UPD 1363 UINT64_C(210766336), // VLDMSIA 1364 UINT64_C(212863488), // VLDMSIA_UPD 1365 UINT64_C(219155200), // VLDRD 1366 UINT64_C(219154688), // VLDRH 1367 UINT64_C(219154944), // VLDRS 1368 UINT64_C(204474880), // VLLDM 1369 UINT64_C(203426304), // VLSTM 1370 UINT64_C(4269804288), // VMAXNMD 1371 UINT64_C(4269803776), // VMAXNMH 1372 UINT64_C(4076867344), // VMAXNMNDf 1373 UINT64_C(4077915920), // VMAXNMNDh 1374 UINT64_C(4076867408), // VMAXNMNQf 1375 UINT64_C(4077915984), // VMAXNMNQh 1376 UINT64_C(4269804032), // VMAXNMS 1377 UINT64_C(4060090112), // VMAXfd 1378 UINT64_C(4060090176), // VMAXfq 1379 UINT64_C(4061138688), // VMAXhd 1380 UINT64_C(4061138752), // VMAXhq 1381 UINT64_C(4060087872), // VMAXsv16i8 1382 UINT64_C(4062184960), // VMAXsv2i32 1383 UINT64_C(4061136384), // VMAXsv4i16 1384 UINT64_C(4062185024), // VMAXsv4i32 1385 UINT64_C(4061136448), // VMAXsv8i16 1386 UINT64_C(4060087808), // VMAXsv8i8 1387 UINT64_C(4076865088), // VMAXuv16i8 1388 UINT64_C(4078962176), // VMAXuv2i32 1389 UINT64_C(4077913600), // VMAXuv4i16 1390 UINT64_C(4078962240), // VMAXuv4i32 1391 UINT64_C(4077913664), // VMAXuv8i16 1392 UINT64_C(4076865024), // VMAXuv8i8 1393 UINT64_C(4269804352), // VMINNMD 1394 UINT64_C(4269803840), // VMINNMH 1395 UINT64_C(4078964496), // VMINNMNDf 1396 UINT64_C(4080013072), // VMINNMNDh 1397 UINT64_C(4078964560), // VMINNMNQf 1398 UINT64_C(4080013136), // VMINNMNQh 1399 UINT64_C(4269804096), // VMINNMS 1400 UINT64_C(4062187264), // VMINfd 1401 UINT64_C(4062187328), // VMINfq 1402 UINT64_C(4063235840), // VMINhd 1403 UINT64_C(4063235904), // VMINhq 1404 UINT64_C(4060087888), // VMINsv16i8 1405 UINT64_C(4062184976), // VMINsv2i32 1406 UINT64_C(4061136400), // VMINsv4i16 1407 UINT64_C(4062185040), // VMINsv4i32 1408 UINT64_C(4061136464), // VMINsv8i16 1409 UINT64_C(4060087824), // VMINsv8i8 1410 UINT64_C(4076865104), // VMINuv16i8 1411 UINT64_C(4078962192), // VMINuv2i32 1412 UINT64_C(4077913616), // VMINuv4i16 1413 UINT64_C(4078962256), // VMINuv4i32 1414 UINT64_C(4077913680), // VMINuv8i16 1415 UINT64_C(4076865040), // VMINuv8i8 1416 UINT64_C(234883840), // VMLAD 1417 UINT64_C(234883328), // VMLAH 1418 UINT64_C(4070572608), // VMLALslsv2i32 1419 UINT64_C(4069524032), // VMLALslsv4i16 1420 UINT64_C(4087349824), // VMLALsluv2i32 1421 UINT64_C(4086301248), // VMLALsluv4i16 1422 UINT64_C(4070574080), // VMLALsv2i64 1423 UINT64_C(4069525504), // VMLALsv4i32 1424 UINT64_C(4068476928), // VMLALsv8i16 1425 UINT64_C(4087351296), // VMLALuv2i64 1426 UINT64_C(4086302720), // VMLALuv4i32 1427 UINT64_C(4085254144), // VMLALuv8i16 1428 UINT64_C(234883584), // VMLAS 1429 UINT64_C(4060089616), // VMLAfd 1430 UINT64_C(4060089680), // VMLAfq 1431 UINT64_C(4061138192), // VMLAhd 1432 UINT64_C(4061138256), // VMLAhq 1433 UINT64_C(4070572352), // VMLAslfd 1434 UINT64_C(4087349568), // VMLAslfq 1435 UINT64_C(4069523776), // VMLAslhd 1436 UINT64_C(4086300992), // VMLAslhq 1437 UINT64_C(4070572096), // VMLAslv2i32 1438 UINT64_C(4069523520), // VMLAslv4i16 1439 UINT64_C(4087349312), // VMLAslv4i32 1440 UINT64_C(4086300736), // VMLAslv8i16 1441 UINT64_C(4060088640), // VMLAv16i8 1442 UINT64_C(4062185728), // VMLAv2i32 1443 UINT64_C(4061137152), // VMLAv4i16 1444 UINT64_C(4062185792), // VMLAv4i32 1445 UINT64_C(4061137216), // VMLAv8i16 1446 UINT64_C(4060088576), // VMLAv8i8 1447 UINT64_C(234883904), // VMLSD 1448 UINT64_C(234883392), // VMLSH 1449 UINT64_C(4070573632), // VMLSLslsv2i32 1450 UINT64_C(4069525056), // VMLSLslsv4i16 1451 UINT64_C(4087350848), // VMLSLsluv2i32 1452 UINT64_C(4086302272), // VMLSLsluv4i16 1453 UINT64_C(4070574592), // VMLSLsv2i64 1454 UINT64_C(4069526016), // VMLSLsv4i32 1455 UINT64_C(4068477440), // VMLSLsv8i16 1456 UINT64_C(4087351808), // VMLSLuv2i64 1457 UINT64_C(4086303232), // VMLSLuv4i32 1458 UINT64_C(4085254656), // VMLSLuv8i16 1459 UINT64_C(234883648), // VMLSS 1460 UINT64_C(4062186768), // VMLSfd 1461 UINT64_C(4062186832), // VMLSfq 1462 UINT64_C(4063235344), // VMLShd 1463 UINT64_C(4063235408), // VMLShq 1464 UINT64_C(4070573376), // VMLSslfd 1465 UINT64_C(4087350592), // VMLSslfq 1466 UINT64_C(4069524800), // VMLSslhd 1467 UINT64_C(4086302016), // VMLSslhq 1468 UINT64_C(4070573120), // VMLSslv2i32 1469 UINT64_C(4069524544), // VMLSslv4i16 1470 UINT64_C(4087350336), // VMLSslv4i32 1471 UINT64_C(4086301760), // VMLSslv8i16 1472 UINT64_C(4076865856), // VMLSv16i8 1473 UINT64_C(4078962944), // VMLSv2i32 1474 UINT64_C(4077914368), // VMLSv4i16 1475 UINT64_C(4078963008), // VMLSv4i32 1476 UINT64_C(4077914432), // VMLSv8i16 1477 UINT64_C(4076865792), // VMLSv8i8 1478 UINT64_C(246418240), // VMOVD 1479 UINT64_C(0), 1480 UINT64_C(205523728), // VMOVDRR 1481 UINT64_C(0), 1482 UINT64_C(4272949824), // VMOVH 1483 UINT64_C(234883344), // VMOVHR 1484 UINT64_C(4070574608), // VMOVLsv2i64 1485 UINT64_C(4069526032), // VMOVLsv4i32 1486 UINT64_C(4069001744), // VMOVLsv8i16 1487 UINT64_C(4087351824), // VMOVLuv2i64 1488 UINT64_C(4086303248), // VMOVLuv4i32 1489 UINT64_C(4085778960), // VMOVLuv8i16 1490 UINT64_C(4089053696), // VMOVNv2i32 1491 UINT64_C(4088791552), // VMOVNv4i16 1492 UINT64_C(4088529408), // VMOVNv8i8 1493 UINT64_C(0), 1494 UINT64_C(235931920), // VMOVRH 1495 UINT64_C(206572304), // VMOVRRD 1496 UINT64_C(206572048), // VMOVRRS 1497 UINT64_C(235932176), // VMOVRS 1498 UINT64_C(246417984), // VMOVS 1499 UINT64_C(234883600), // VMOVSR 1500 UINT64_C(205523472), // VMOVSRR 1501 UINT64_C(0), 1502 UINT64_C(4068478544), // VMOVv16i8 1503 UINT64_C(4068478512), // VMOVv1i64 1504 UINT64_C(4068478736), // VMOVv2f32 1505 UINT64_C(4068474896), // VMOVv2i32 1506 UINT64_C(4068478576), // VMOVv2i64 1507 UINT64_C(4068478800), // VMOVv4f32 1508 UINT64_C(4068476944), // VMOVv4i16 1509 UINT64_C(4068474960), // VMOVv4i32 1510 UINT64_C(4068477008), // VMOVv8i16 1511 UINT64_C(4068478480), // VMOVv8i8 1512 UINT64_C(250677776), // VMRS 1513 UINT64_C(251136528), // VMRS_FPEXC 1514 UINT64_C(251202064), // VMRS_FPINST 1515 UINT64_C(251267600), // VMRS_FPINST2 1516 UINT64_C(250612240), // VMRS_FPSID 1517 UINT64_C(251070992), // VMRS_MVFR0 1518 UINT64_C(251005456), // VMRS_MVFR1 1519 UINT64_C(250939920), // VMRS_MVFR2 1520 UINT64_C(249629200), // VMSR 1521 UINT64_C(250087952), // VMSR_FPEXC 1522 UINT64_C(250153488), // VMSR_FPINST 1523 UINT64_C(250219024), // VMSR_FPINST2 1524 UINT64_C(249563664), // VMSR_FPSID 1525 UINT64_C(236980992), // VMULD 1526 UINT64_C(236980480), // VMULH 1527 UINT64_C(4070575616), // VMULLp64 1528 UINT64_C(4068478464), // VMULLp8 1529 UINT64_C(4070574656), // VMULLslsv2i32 1530 UINT64_C(4069526080), // VMULLslsv4i16 1531 UINT64_C(4087351872), // VMULLsluv2i32 1532 UINT64_C(4086303296), // VMULLsluv4i16 1533 UINT64_C(4070575104), // VMULLsv2i64 1534 UINT64_C(4069526528), // VMULLsv4i32 1535 UINT64_C(4068477952), // VMULLsv8i16 1536 UINT64_C(4087352320), // VMULLuv2i64 1537 UINT64_C(4086303744), // VMULLuv4i32 1538 UINT64_C(4085255168), // VMULLuv8i16 1539 UINT64_C(236980736), // VMULS 1540 UINT64_C(4076866832), // VMULfd 1541 UINT64_C(4076866896), // VMULfq 1542 UINT64_C(4077915408), // VMULhd 1543 UINT64_C(4077915472), // VMULhq 1544 UINT64_C(4076865808), // VMULpd 1545 UINT64_C(4076865872), // VMULpq 1546 UINT64_C(4070574400), // VMULslfd 1547 UINT64_C(4087351616), // VMULslfq 1548 UINT64_C(4069525824), // VMULslhd 1549 UINT64_C(4086303040), // VMULslhq 1550 UINT64_C(4070574144), // VMULslv2i32 1551 UINT64_C(4069525568), // VMULslv4i16 1552 UINT64_C(4087351360), // VMULslv4i32 1553 UINT64_C(4086302784), // VMULslv8i16 1554 UINT64_C(4060088656), // VMULv16i8 1555 UINT64_C(4062185744), // VMULv2i32 1556 UINT64_C(4061137168), // VMULv4i16 1557 UINT64_C(4062185808), // VMULv4i32 1558 UINT64_C(4061137232), // VMULv8i16 1559 UINT64_C(4060088592), // VMULv8i8 1560 UINT64_C(4088399232), // VMVNd 1561 UINT64_C(4088399296), // VMVNq 1562 UINT64_C(4068474928), // VMVNv2i32 1563 UINT64_C(4068476976), // VMVNv4i16 1564 UINT64_C(4068474992), // VMVNv4i32 1565 UINT64_C(4068477040), // VMVNv8i16 1566 UINT64_C(246483776), // VNEGD 1567 UINT64_C(246483264), // VNEGH 1568 UINT64_C(246483520), // VNEGS 1569 UINT64_C(4088989632), // VNEGf32q 1570 UINT64_C(4088989568), // VNEGfd 1571 UINT64_C(4088727424), // VNEGhd 1572 UINT64_C(4088727488), // VNEGhq 1573 UINT64_C(4088726400), // VNEGs16d 1574 UINT64_C(4088726464), // VNEGs16q 1575 UINT64_C(4088988544), // VNEGs32d 1576 UINT64_C(4088988608), // VNEGs32q 1577 UINT64_C(4088464256), // VNEGs8d 1578 UINT64_C(4088464320), // VNEGs8q 1579 UINT64_C(235932480), // VNMLAD 1580 UINT64_C(235931968), // VNMLAH 1581 UINT64_C(235932224), // VNMLAS 1582 UINT64_C(235932416), // VNMLSD 1583 UINT64_C(235931904), // VNMLSH 1584 UINT64_C(235932160), // VNMLSS 1585 UINT64_C(236981056), // VNMULD 1586 UINT64_C(236980544), // VNMULH 1587 UINT64_C(236980800), // VNMULS 1588 UINT64_C(4063232272), // VORNd 1589 UINT64_C(4063232336), // VORNq 1590 UINT64_C(4062183696), // VORRd 1591 UINT64_C(4068475152), // VORRiv2i32 1592 UINT64_C(4068477200), // VORRiv4i16 1593 UINT64_C(4068475216), // VORRiv4i32 1594 UINT64_C(4068477264), // VORRiv8i16 1595 UINT64_C(4062183760), // VORRq 1596 UINT64_C(4088399424), // VPADALsv16i8 1597 UINT64_C(4088923648), // VPADALsv2i32 1598 UINT64_C(4088661504), // VPADALsv4i16 1599 UINT64_C(4088923712), // VPADALsv4i32 1600 UINT64_C(4088661568), // VPADALsv8i16 1601 UINT64_C(4088399360), // VPADALsv8i8 1602 UINT64_C(4088399552), // VPADALuv16i8 1603 UINT64_C(4088923776), // VPADALuv2i32 1604 UINT64_C(4088661632), // VPADALuv4i16 1605 UINT64_C(4088923840), // VPADALuv4i32 1606 UINT64_C(4088661696), // VPADALuv8i16 1607 UINT64_C(4088399488), // VPADALuv8i8 1608 UINT64_C(4088398400), // VPADDLsv16i8 1609 UINT64_C(4088922624), // VPADDLsv2i32 1610 UINT64_C(4088660480), // VPADDLsv4i16 1611 UINT64_C(4088922688), // VPADDLsv4i32 1612 UINT64_C(4088660544), // VPADDLsv8i16 1613 UINT64_C(4088398336), // VPADDLsv8i8 1614 UINT64_C(4088398528), // VPADDLuv16i8 1615 UINT64_C(4088922752), // VPADDLuv2i32 1616 UINT64_C(4088660608), // VPADDLuv4i16 1617 UINT64_C(4088922816), // VPADDLuv4i32 1618 UINT64_C(4088660672), // VPADDLuv8i16 1619 UINT64_C(4088398464), // VPADDLuv8i8 1620 UINT64_C(4076866816), // VPADDf 1621 UINT64_C(4077915392), // VPADDh 1622 UINT64_C(4061137680), // VPADDi16 1623 UINT64_C(4062186256), // VPADDi32 1624 UINT64_C(4060089104), // VPADDi8 1625 UINT64_C(4076867328), // VPMAXf 1626 UINT64_C(4077915904), // VPMAXh 1627 UINT64_C(4061137408), // VPMAXs16 1628 UINT64_C(4062185984), // VPMAXs32 1629 UINT64_C(4060088832), // VPMAXs8 1630 UINT64_C(4077914624), // VPMAXu16 1631 UINT64_C(4078963200), // VPMAXu32 1632 UINT64_C(4076866048), // VPMAXu8 1633 UINT64_C(4078964480), // VPMINf 1634 UINT64_C(4080013056), // VPMINh 1635 UINT64_C(4061137424), // VPMINs16 1636 UINT64_C(4062186000), // VPMINs32 1637 UINT64_C(4060088848), // VPMINs8 1638 UINT64_C(4077914640), // VPMINu16 1639 UINT64_C(4078963216), // VPMINu32 1640 UINT64_C(4076866064), // VPMINu8 1641 UINT64_C(4088399680), // VQABSv16i8 1642 UINT64_C(4088923904), // VQABSv2i32 1643 UINT64_C(4088661760), // VQABSv4i16 1644 UINT64_C(4088923968), // VQABSv4i32 1645 UINT64_C(4088661824), // VQABSv8i16 1646 UINT64_C(4088399616), // VQABSv8i8 1647 UINT64_C(4060086352), // VQADDsv16i8 1648 UINT64_C(4063232016), // VQADDsv1i64 1649 UINT64_C(4062183440), // VQADDsv2i32 1650 UINT64_C(4063232080), // VQADDsv2i64 1651 UINT64_C(4061134864), // VQADDsv4i16 1652 UINT64_C(4062183504), // VQADDsv4i32 1653 UINT64_C(4061134928), // VQADDsv8i16 1654 UINT64_C(4060086288), // VQADDsv8i8 1655 UINT64_C(4076863568), // VQADDuv16i8 1656 UINT64_C(4080009232), // VQADDuv1i64 1657 UINT64_C(4078960656), // VQADDuv2i32 1658 UINT64_C(4080009296), // VQADDuv2i64 1659 UINT64_C(4077912080), // VQADDuv4i16 1660 UINT64_C(4078960720), // VQADDuv4i32 1661 UINT64_C(4077912144), // VQADDuv8i16 1662 UINT64_C(4076863504), // VQADDuv8i8 1663 UINT64_C(4070572864), // VQDMLALslv2i32 1664 UINT64_C(4069524288), // VQDMLALslv4i16 1665 UINT64_C(4070574336), // VQDMLALv2i64 1666 UINT64_C(4069525760), // VQDMLALv4i32 1667 UINT64_C(4070573888), // VQDMLSLslv2i32 1668 UINT64_C(4069525312), // VQDMLSLslv4i16 1669 UINT64_C(4070574848), // VQDMLSLv2i64 1670 UINT64_C(4069526272), // VQDMLSLv4i32 1671 UINT64_C(4070575168), // VQDMULHslv2i32 1672 UINT64_C(4069526592), // VQDMULHslv4i16 1673 UINT64_C(4087352384), // VQDMULHslv4i32 1674 UINT64_C(4086303808), // VQDMULHslv8i16 1675 UINT64_C(4062186240), // VQDMULHv2i32 1676 UINT64_C(4061137664), // VQDMULHv4i16 1677 UINT64_C(4062186304), // VQDMULHv4i32 1678 UINT64_C(4061137728), // VQDMULHv8i16 1679 UINT64_C(4070574912), // VQDMULLslv2i32 1680 UINT64_C(4069526336), // VQDMULLslv4i16 1681 UINT64_C(4070575360), // VQDMULLv2i64 1682 UINT64_C(4069526784), // VQDMULLv4i32 1683 UINT64_C(4089053760), // VQMOVNsuv2i32 1684 UINT64_C(4088791616), // VQMOVNsuv4i16 1685 UINT64_C(4088529472), // VQMOVNsuv8i8 1686 UINT64_C(4089053824), // VQMOVNsv2i32 1687 UINT64_C(4088791680), // VQMOVNsv4i16 1688 UINT64_C(4088529536), // VQMOVNsv8i8 1689 UINT64_C(4089053888), // VQMOVNuv2i32 1690 UINT64_C(4088791744), // VQMOVNuv4i16 1691 UINT64_C(4088529600), // VQMOVNuv8i8 1692 UINT64_C(4088399808), // VQNEGv16i8 1693 UINT64_C(4088924032), // VQNEGv2i32 1694 UINT64_C(4088661888), // VQNEGv4i16 1695 UINT64_C(4088924096), // VQNEGv4i32 1696 UINT64_C(4088661952), // VQNEGv8i16 1697 UINT64_C(4088399744), // VQNEGv8i8 1698 UINT64_C(4070575680), // VQRDMLAHslv2i32 1699 UINT64_C(4069527104), // VQRDMLAHslv4i16 1700 UINT64_C(4087352896), // VQRDMLAHslv4i32 1701 UINT64_C(4086304320), // VQRDMLAHslv8i16 1702 UINT64_C(4078963472), // VQRDMLAHv2i32 1703 UINT64_C(4077914896), // VQRDMLAHv4i16 1704 UINT64_C(4078963536), // VQRDMLAHv4i32 1705 UINT64_C(4077914960), // VQRDMLAHv8i16 1706 UINT64_C(4070575936), // VQRDMLSHslv2i32 1707 UINT64_C(4069527360), // VQRDMLSHslv4i16 1708 UINT64_C(4087353152), // VQRDMLSHslv4i32 1709 UINT64_C(4086304576), // VQRDMLSHslv8i16 1710 UINT64_C(4078963728), // VQRDMLSHv2i32 1711 UINT64_C(4077915152), // VQRDMLSHv4i16 1712 UINT64_C(4078963792), // VQRDMLSHv4i32 1713 UINT64_C(4077915216), // VQRDMLSHv8i16 1714 UINT64_C(4070575424), // VQRDMULHslv2i32 1715 UINT64_C(4069526848), // VQRDMULHslv4i16 1716 UINT64_C(4087352640), // VQRDMULHslv4i32 1717 UINT64_C(4086304064), // VQRDMULHslv8i16 1718 UINT64_C(4078963456), // VQRDMULHv2i32 1719 UINT64_C(4077914880), // VQRDMULHv4i16 1720 UINT64_C(4078963520), // VQRDMULHv4i32 1721 UINT64_C(4077914944), // VQRDMULHv8i16 1722 UINT64_C(4060087632), // VQRSHLsv16i8 1723 UINT64_C(4063233296), // VQRSHLsv1i64 1724 UINT64_C(4062184720), // VQRSHLsv2i32 1725 UINT64_C(4063233360), // VQRSHLsv2i64 1726 UINT64_C(4061136144), // VQRSHLsv4i16 1727 UINT64_C(4062184784), // VQRSHLsv4i32 1728 UINT64_C(4061136208), // VQRSHLsv8i16 1729 UINT64_C(4060087568), // VQRSHLsv8i8 1730 UINT64_C(4076864848), // VQRSHLuv16i8 1731 UINT64_C(4080010512), // VQRSHLuv1i64 1732 UINT64_C(4078961936), // VQRSHLuv2i32 1733 UINT64_C(4080010576), // VQRSHLuv2i64 1734 UINT64_C(4077913360), // VQRSHLuv4i16 1735 UINT64_C(4078962000), // VQRSHLuv4i32 1736 UINT64_C(4077913424), // VQRSHLuv8i16 1737 UINT64_C(4076864784), // VQRSHLuv8i8 1738 UINT64_C(4070574416), // VQRSHRNsv2i32 1739 UINT64_C(4069525840), // VQRSHRNsv4i16 1740 UINT64_C(4069001552), // VQRSHRNsv8i8 1741 UINT64_C(4087351632), // VQRSHRNuv2i32 1742 UINT64_C(4086303056), // VQRSHRNuv4i16 1743 UINT64_C(4085778768), // VQRSHRNuv8i8 1744 UINT64_C(4087351376), // VQRSHRUNv2i32 1745 UINT64_C(4086302800), // VQRSHRUNv4i16 1746 UINT64_C(4085778512), // VQRSHRUNv8i8 1747 UINT64_C(4069001040), // VQSHLsiv16i8 1748 UINT64_C(4068476816), // VQSHLsiv1i64 1749 UINT64_C(4070573840), // VQSHLsiv2i32 1750 UINT64_C(4068476880), // VQSHLsiv2i64 1751 UINT64_C(4069525264), // VQSHLsiv4i16 1752 UINT64_C(4070573904), // VQSHLsiv4i32 1753 UINT64_C(4069525328), // VQSHLsiv8i16 1754 UINT64_C(4069000976), // VQSHLsiv8i8 1755 UINT64_C(4085778000), // VQSHLsuv16i8 1756 UINT64_C(4085253776), // VQSHLsuv1i64 1757 UINT64_C(4087350800), // VQSHLsuv2i32 1758 UINT64_C(4085253840), // VQSHLsuv2i64 1759 UINT64_C(4086302224), // VQSHLsuv4i16 1760 UINT64_C(4087350864), // VQSHLsuv4i32 1761 UINT64_C(4086302288), // VQSHLsuv8i16 1762 UINT64_C(4085777936), // VQSHLsuv8i8 1763 UINT64_C(4060087376), // VQSHLsv16i8 1764 UINT64_C(4063233040), // VQSHLsv1i64 1765 UINT64_C(4062184464), // VQSHLsv2i32 1766 UINT64_C(4063233104), // VQSHLsv2i64 1767 UINT64_C(4061135888), // VQSHLsv4i16 1768 UINT64_C(4062184528), // VQSHLsv4i32 1769 UINT64_C(4061135952), // VQSHLsv8i16 1770 UINT64_C(4060087312), // VQSHLsv8i8 1771 UINT64_C(4085778256), // VQSHLuiv16i8 1772 UINT64_C(4085254032), // VQSHLuiv1i64 1773 UINT64_C(4087351056), // VQSHLuiv2i32 1774 UINT64_C(4085254096), // VQSHLuiv2i64 1775 UINT64_C(4086302480), // VQSHLuiv4i16 1776 UINT64_C(4087351120), // VQSHLuiv4i32 1777 UINT64_C(4086302544), // VQSHLuiv8i16 1778 UINT64_C(4085778192), // VQSHLuiv8i8 1779 UINT64_C(4076864592), // VQSHLuv16i8 1780 UINT64_C(4080010256), // VQSHLuv1i64 1781 UINT64_C(4078961680), // VQSHLuv2i32 1782 UINT64_C(4080010320), // VQSHLuv2i64 1783 UINT64_C(4077913104), // VQSHLuv4i16 1784 UINT64_C(4078961744), // VQSHLuv4i32 1785 UINT64_C(4077913168), // VQSHLuv8i16 1786 UINT64_C(4076864528), // VQSHLuv8i8 1787 UINT64_C(4070574352), // VQSHRNsv2i32 1788 UINT64_C(4069525776), // VQSHRNsv4i16 1789 UINT64_C(4069001488), // VQSHRNsv8i8 1790 UINT64_C(4087351568), // VQSHRNuv2i32 1791 UINT64_C(4086302992), // VQSHRNuv4i16 1792 UINT64_C(4085778704), // VQSHRNuv8i8 1793 UINT64_C(4087351312), // VQSHRUNv2i32 1794 UINT64_C(4086302736), // VQSHRUNv4i16 1795 UINT64_C(4085778448), // VQSHRUNv8i8 1796 UINT64_C(4060086864), // VQSUBsv16i8 1797 UINT64_C(4063232528), // VQSUBsv1i64 1798 UINT64_C(4062183952), // VQSUBsv2i32 1799 UINT64_C(4063232592), // VQSUBsv2i64 1800 UINT64_C(4061135376), // VQSUBsv4i16 1801 UINT64_C(4062184016), // VQSUBsv4i32 1802 UINT64_C(4061135440), // VQSUBsv8i16 1803 UINT64_C(4060086800), // VQSUBsv8i8 1804 UINT64_C(4076864080), // VQSUBuv16i8 1805 UINT64_C(4080009744), // VQSUBuv1i64 1806 UINT64_C(4078961168), // VQSUBuv2i32 1807 UINT64_C(4080009808), // VQSUBuv2i64 1808 UINT64_C(4077912592), // VQSUBuv4i16 1809 UINT64_C(4078961232), // VQSUBuv4i32 1810 UINT64_C(4077912656), // VQSUBuv8i16 1811 UINT64_C(4076864016), // VQSUBuv8i8 1812 UINT64_C(4087350272), // VRADDHNv2i32 1813 UINT64_C(4086301696), // VRADDHNv4i16 1814 UINT64_C(4085253120), // VRADDHNv8i8 1815 UINT64_C(4089119744), // VRECPEd 1816 UINT64_C(4089120000), // VRECPEfd 1817 UINT64_C(4089120064), // VRECPEfq 1818 UINT64_C(4088857856), // VRECPEhd 1819 UINT64_C(4088857920), // VRECPEhq 1820 UINT64_C(4089119808), // VRECPEq 1821 UINT64_C(4060090128), // VRECPSfd 1822 UINT64_C(4060090192), // VRECPSfq 1823 UINT64_C(4061138704), // VRECPShd 1824 UINT64_C(4061138768), // VRECPShq 1825 UINT64_C(4088398080), // VREV16d8 1826 UINT64_C(4088398144), // VREV16q8 1827 UINT64_C(4088660096), // VREV32d16 1828 UINT64_C(4088397952), // VREV32d8 1829 UINT64_C(4088660160), // VREV32q16 1830 UINT64_C(4088398016), // VREV32q8 1831 UINT64_C(4088659968), // VREV64d16 1832 UINT64_C(4088922112), // VREV64d32 1833 UINT64_C(4088397824), // VREV64d8 1834 UINT64_C(4088660032), // VREV64q16 1835 UINT64_C(4088922176), // VREV64q32 1836 UINT64_C(4088397888), // VREV64q8 1837 UINT64_C(4060086592), // VRHADDsv16i8 1838 UINT64_C(4062183680), // VRHADDsv2i32 1839 UINT64_C(4061135104), // VRHADDsv4i16 1840 UINT64_C(4062183744), // VRHADDsv4i32 1841 UINT64_C(4061135168), // VRHADDsv8i16 1842 UINT64_C(4060086528), // VRHADDsv8i8 1843 UINT64_C(4076863808), // VRHADDuv16i8 1844 UINT64_C(4078960896), // VRHADDuv2i32 1845 UINT64_C(4077912320), // VRHADDuv4i16 1846 UINT64_C(4078960960), // VRHADDuv4i32 1847 UINT64_C(4077912384), // VRHADDuv8i16 1848 UINT64_C(4076863744), // VRHADDuv8i8 1849 UINT64_C(4273474368), // VRINTAD 1850 UINT64_C(4273473856), // VRINTAH 1851 UINT64_C(4089054464), // VRINTANDf 1852 UINT64_C(4088792320), // VRINTANDh 1853 UINT64_C(4089054528), // VRINTANQf 1854 UINT64_C(4088792384), // VRINTANQh 1855 UINT64_C(4273474112), // VRINTAS 1856 UINT64_C(4273670976), // VRINTMD 1857 UINT64_C(4273670464), // VRINTMH 1858 UINT64_C(4089054848), // VRINTMNDf 1859 UINT64_C(4088792704), // VRINTMNDh 1860 UINT64_C(4089054912), // VRINTMNQf 1861 UINT64_C(4088792768), // VRINTMNQh 1862 UINT64_C(4273670720), // VRINTMS 1863 UINT64_C(4273539904), // VRINTND 1864 UINT64_C(4273539392), // VRINTNH 1865 UINT64_C(4089054208), // VRINTNNDf 1866 UINT64_C(4088792064), // VRINTNNDh 1867 UINT64_C(4089054272), // VRINTNNQf 1868 UINT64_C(4088792128), // VRINTNNQh 1869 UINT64_C(4273539648), // VRINTNS 1870 UINT64_C(4273605440), // VRINTPD 1871 UINT64_C(4273604928), // VRINTPH 1872 UINT64_C(4089055104), // VRINTPNDf 1873 UINT64_C(4088792960), // VRINTPNDh 1874 UINT64_C(4089055168), // VRINTPNQf 1875 UINT64_C(4088793024), // VRINTPNQh 1876 UINT64_C(4273605184), // VRINTPS 1877 UINT64_C(246811456), // VRINTRD 1878 UINT64_C(246810944), // VRINTRH 1879 UINT64_C(246811200), // VRINTRS 1880 UINT64_C(246876992), // VRINTXD 1881 UINT64_C(246876480), // VRINTXH 1882 UINT64_C(4089054336), // VRINTXNDf 1883 UINT64_C(4088792192), // VRINTXNDh 1884 UINT64_C(4089054400), // VRINTXNQf 1885 UINT64_C(4088792256), // VRINTXNQh 1886 UINT64_C(246876736), // VRINTXS 1887 UINT64_C(246811584), // VRINTZD 1888 UINT64_C(246811072), // VRINTZH 1889 UINT64_C(4089054592), // VRINTZNDf 1890 UINT64_C(4088792448), // VRINTZNDh 1891 UINT64_C(4089054656), // VRINTZNQf 1892 UINT64_C(4088792512), // VRINTZNQh 1893 UINT64_C(246811328), // VRINTZS 1894 UINT64_C(4060087616), // VRSHLsv16i8 1895 UINT64_C(4063233280), // VRSHLsv1i64 1896 UINT64_C(4062184704), // VRSHLsv2i32 1897 UINT64_C(4063233344), // VRSHLsv2i64 1898 UINT64_C(4061136128), // VRSHLsv4i16 1899 UINT64_C(4062184768), // VRSHLsv4i32 1900 UINT64_C(4061136192), // VRSHLsv8i16 1901 UINT64_C(4060087552), // VRSHLsv8i8 1902 UINT64_C(4076864832), // VRSHLuv16i8 1903 UINT64_C(4080010496), // VRSHLuv1i64 1904 UINT64_C(4078961920), // VRSHLuv2i32 1905 UINT64_C(4080010560), // VRSHLuv2i64 1906 UINT64_C(4077913344), // VRSHLuv4i16 1907 UINT64_C(4078961984), // VRSHLuv4i32 1908 UINT64_C(4077913408), // VRSHLuv8i16 1909 UINT64_C(4076864768), // VRSHLuv8i8 1910 UINT64_C(4070574160), // VRSHRNv2i32 1911 UINT64_C(4069525584), // VRSHRNv4i16 1912 UINT64_C(4069001296), // VRSHRNv8i8 1913 UINT64_C(4068999760), // VRSHRsv16i8 1914 UINT64_C(4068475536), // VRSHRsv1i64 1915 UINT64_C(4070572560), // VRSHRsv2i32 1916 UINT64_C(4068475600), // VRSHRsv2i64 1917 UINT64_C(4069523984), // VRSHRsv4i16 1918 UINT64_C(4070572624), // VRSHRsv4i32 1919 UINT64_C(4069524048), // VRSHRsv8i16 1920 UINT64_C(4068999696), // VRSHRsv8i8 1921 UINT64_C(4085776976), // VRSHRuv16i8 1922 UINT64_C(4085252752), // VRSHRuv1i64 1923 UINT64_C(4087349776), // VRSHRuv2i32 1924 UINT64_C(4085252816), // VRSHRuv2i64 1925 UINT64_C(4086301200), // VRSHRuv4i16 1926 UINT64_C(4087349840), // VRSHRuv4i32 1927 UINT64_C(4086301264), // VRSHRuv8i16 1928 UINT64_C(4085776912), // VRSHRuv8i8 1929 UINT64_C(4089119872), // VRSQRTEd 1930 UINT64_C(4089120128), // VRSQRTEfd 1931 UINT64_C(4089120192), // VRSQRTEfq 1932 UINT64_C(4088857984), // VRSQRTEhd 1933 UINT64_C(4088858048), // VRSQRTEhq 1934 UINT64_C(4089119936), // VRSQRTEq 1935 UINT64_C(4062187280), // VRSQRTSfd 1936 UINT64_C(4062187344), // VRSQRTSfq 1937 UINT64_C(4063235856), // VRSQRTShd 1938 UINT64_C(4063235920), // VRSQRTShq 1939 UINT64_C(4069000016), // VRSRAsv16i8 1940 UINT64_C(4068475792), // VRSRAsv1i64 1941 UINT64_C(4070572816), // VRSRAsv2i32 1942 UINT64_C(4068475856), // VRSRAsv2i64 1943 UINT64_C(4069524240), // VRSRAsv4i16 1944 UINT64_C(4070572880), // VRSRAsv4i32 1945 UINT64_C(4069524304), // VRSRAsv8i16 1946 UINT64_C(4068999952), // VRSRAsv8i8 1947 UINT64_C(4085777232), // VRSRAuv16i8 1948 UINT64_C(4085253008), // VRSRAuv1i64 1949 UINT64_C(4087350032), // VRSRAuv2i32 1950 UINT64_C(4085253072), // VRSRAuv2i64 1951 UINT64_C(4086301456), // VRSRAuv4i16 1952 UINT64_C(4087350096), // VRSRAuv4i32 1953 UINT64_C(4086301520), // VRSRAuv8i16 1954 UINT64_C(4085777168), // VRSRAuv8i8 1955 UINT64_C(4087350784), // VRSUBHNv2i32 1956 UINT64_C(4086302208), // VRSUBHNv4i16 1957 UINT64_C(4085253632), // VRSUBHNv8i8 1958 UINT64_C(4261415680), // VSELEQD 1959 UINT64_C(4261415168), // VSELEQH 1960 UINT64_C(4261415424), // VSELEQS 1961 UINT64_C(4263512832), // VSELGED 1962 UINT64_C(4263512320), // VSELGEH 1963 UINT64_C(4263512576), // VSELGES 1964 UINT64_C(4264561408), // VSELGTD 1965 UINT64_C(4264560896), // VSELGTH 1966 UINT64_C(4264561152), // VSELGTS 1967 UINT64_C(4262464256), // VSELVSD 1968 UINT64_C(4262463744), // VSELVSH 1969 UINT64_C(4262464000), // VSELVSS 1970 UINT64_C(234883888), // VSETLNi16 1971 UINT64_C(234883856), // VSETLNi32 1972 UINT64_C(239078160), // VSETLNi8 1973 UINT64_C(4088791808), // VSHLLi16 1974 UINT64_C(4089053952), // VSHLLi32 1975 UINT64_C(4088529664), // VSHLLi8 1976 UINT64_C(4070574608), // VSHLLsv2i64 1977 UINT64_C(4069526032), // VSHLLsv4i32 1978 UINT64_C(4069001744), // VSHLLsv8i16 1979 UINT64_C(4087351824), // VSHLLuv2i64 1980 UINT64_C(4086303248), // VSHLLuv4i32 1981 UINT64_C(4085778960), // VSHLLuv8i16 1982 UINT64_C(4069000528), // VSHLiv16i8 1983 UINT64_C(4068476304), // VSHLiv1i64 1984 UINT64_C(4070573328), // VSHLiv2i32 1985 UINT64_C(4068476368), // VSHLiv2i64 1986 UINT64_C(4069524752), // VSHLiv4i16 1987 UINT64_C(4070573392), // VSHLiv4i32 1988 UINT64_C(4069524816), // VSHLiv8i16 1989 UINT64_C(4069000464), // VSHLiv8i8 1990 UINT64_C(4060087360), // VSHLsv16i8 1991 UINT64_C(4063233024), // VSHLsv1i64 1992 UINT64_C(4062184448), // VSHLsv2i32 1993 UINT64_C(4063233088), // VSHLsv2i64 1994 UINT64_C(4061135872), // VSHLsv4i16 1995 UINT64_C(4062184512), // VSHLsv4i32 1996 UINT64_C(4061135936), // VSHLsv8i16 1997 UINT64_C(4060087296), // VSHLsv8i8 1998 UINT64_C(4076864576), // VSHLuv16i8 1999 UINT64_C(4080010240), // VSHLuv1i64 2000 UINT64_C(4078961664), // VSHLuv2i32 2001 UINT64_C(4080010304), // VSHLuv2i64 2002 UINT64_C(4077913088), // VSHLuv4i16 2003 UINT64_C(4078961728), // VSHLuv4i32 2004 UINT64_C(4077913152), // VSHLuv8i16 2005 UINT64_C(4076864512), // VSHLuv8i8 2006 UINT64_C(4070574096), // VSHRNv2i32 2007 UINT64_C(4069525520), // VSHRNv4i16 2008 UINT64_C(4069001232), // VSHRNv8i8 2009 UINT64_C(4068999248), // VSHRsv16i8 2010 UINT64_C(4068475024), // VSHRsv1i64 2011 UINT64_C(4070572048), // VSHRsv2i32 2012 UINT64_C(4068475088), // VSHRsv2i64 2013 UINT64_C(4069523472), // VSHRsv4i16 2014 UINT64_C(4070572112), // VSHRsv4i32 2015 UINT64_C(4069523536), // VSHRsv8i16 2016 UINT64_C(4068999184), // VSHRsv8i8 2017 UINT64_C(4085776464), // VSHRuv16i8 2018 UINT64_C(4085252240), // VSHRuv1i64 2019 UINT64_C(4087349264), // VSHRuv2i32 2020 UINT64_C(4085252304), // VSHRuv2i64 2021 UINT64_C(4086300688), // VSHRuv4i16 2022 UINT64_C(4087349328), // VSHRuv4i32 2023 UINT64_C(4086300752), // VSHRuv8i16 2024 UINT64_C(4085776400), // VSHRuv8i8 2025 UINT64_C(247073600), // VSHTOD 2026 UINT64_C(247073088), // VSHTOH 2027 UINT64_C(247073344), // VSHTOS 2028 UINT64_C(246942656), // VSITOD 2029 UINT64_C(246942144), // VSITOH 2030 UINT64_C(246942400), // VSITOS 2031 UINT64_C(4085777744), // VSLIv16i8 2032 UINT64_C(4085253520), // VSLIv1i64 2033 UINT64_C(4087350544), // VSLIv2i32 2034 UINT64_C(4085253584), // VSLIv2i64 2035 UINT64_C(4086301968), // VSLIv4i16 2036 UINT64_C(4087350608), // VSLIv4i32 2037 UINT64_C(4086302032), // VSLIv8i16 2038 UINT64_C(4085777680), // VSLIv8i8 2039 UINT64_C(247073728), // VSLTOD 2040 UINT64_C(247073216), // VSLTOH 2041 UINT64_C(247073472), // VSLTOS 2042 UINT64_C(246483904), // VSQRTD 2043 UINT64_C(246483392), // VSQRTH 2044 UINT64_C(246483648), // VSQRTS 2045 UINT64_C(4068999504), // VSRAsv16i8 2046 UINT64_C(4068475280), // VSRAsv1i64 2047 UINT64_C(4070572304), // VSRAsv2i32 2048 UINT64_C(4068475344), // VSRAsv2i64 2049 UINT64_C(4069523728), // VSRAsv4i16 2050 UINT64_C(4070572368), // VSRAsv4i32 2051 UINT64_C(4069523792), // VSRAsv8i16 2052 UINT64_C(4068999440), // VSRAsv8i8 2053 UINT64_C(4085776720), // VSRAuv16i8 2054 UINT64_C(4085252496), // VSRAuv1i64 2055 UINT64_C(4087349520), // VSRAuv2i32 2056 UINT64_C(4085252560), // VSRAuv2i64 2057 UINT64_C(4086300944), // VSRAuv4i16 2058 UINT64_C(4087349584), // VSRAuv4i32 2059 UINT64_C(4086301008), // VSRAuv8i16 2060 UINT64_C(4085776656), // VSRAuv8i8 2061 UINT64_C(4085777488), // VSRIv16i8 2062 UINT64_C(4085253264), // VSRIv1i64 2063 UINT64_C(4087350288), // VSRIv2i32 2064 UINT64_C(4085253328), // VSRIv2i64 2065 UINT64_C(4086301712), // VSRIv4i16 2066 UINT64_C(4087350352), // VSRIv4i32 2067 UINT64_C(4086301776), // VSRIv8i16 2068 UINT64_C(4085777424), // VSRIv8i8 2069 UINT64_C(4102030351), // VST1LNd16 2070 UINT64_C(4102030336), // VST1LNd16_UPD 2071 UINT64_C(4102031375), // VST1LNd32 2072 UINT64_C(4102031360), // VST1LNd32_UPD 2073 UINT64_C(4102029327), // VST1LNd8 2074 UINT64_C(4102029312), // VST1LNd8_UPD 2075 UINT64_C(0), 2076 UINT64_C(0), 2077 UINT64_C(0), 2078 UINT64_C(0), 2079 UINT64_C(0), 2080 UINT64_C(0), 2081 UINT64_C(0), 2082 UINT64_C(0), 2083 UINT64_C(0), 2084 UINT64_C(0), // VST1LNq16Pseudo 2085 UINT64_C(0), // VST1LNq16Pseudo_UPD 2086 UINT64_C(0), // VST1LNq32Pseudo 2087 UINT64_C(0), // VST1LNq32Pseudo_UPD 2088 UINT64_C(0), // VST1LNq8Pseudo 2089 UINT64_C(0), // VST1LNq8Pseudo_UPD 2090 UINT64_C(4093642575), // VST1d16 2091 UINT64_C(4093641295), // VST1d16Q 2092 UINT64_C(4093641293), // VST1d16Qwb_fixed 2093 UINT64_C(4093641280), // VST1d16Qwb_register 2094 UINT64_C(4093642319), // VST1d16T 2095 UINT64_C(4093642317), // VST1d16Twb_fixed 2096 UINT64_C(4093642304), // VST1d16Twb_register 2097 UINT64_C(4093642573), // VST1d16wb_fixed 2098 UINT64_C(4093642560), // VST1d16wb_register 2099 UINT64_C(4093642639), // VST1d32 2100 UINT64_C(4093641359), // VST1d32Q 2101 UINT64_C(4093641357), // VST1d32Qwb_fixed 2102 UINT64_C(4093641344), // VST1d32Qwb_register 2103 UINT64_C(4093642383), // VST1d32T 2104 UINT64_C(4093642381), // VST1d32Twb_fixed 2105 UINT64_C(4093642368), // VST1d32Twb_register 2106 UINT64_C(4093642637), // VST1d32wb_fixed 2107 UINT64_C(4093642624), // VST1d32wb_register 2108 UINT64_C(4093642703), // VST1d64 2109 UINT64_C(4093641423), // VST1d64Q 2110 UINT64_C(0), // VST1d64QPseudo 2111 UINT64_C(0), // VST1d64QPseudoWB_fixed 2112 UINT64_C(0), // VST1d64QPseudoWB_register 2113 UINT64_C(4093641421), // VST1d64Qwb_fixed 2114 UINT64_C(4093641408), // VST1d64Qwb_register 2115 UINT64_C(4093642447), // VST1d64T 2116 UINT64_C(0), // VST1d64TPseudo 2117 UINT64_C(0), // VST1d64TPseudoWB_fixed 2118 UINT64_C(0), // VST1d64TPseudoWB_register 2119 UINT64_C(4093642445), // VST1d64Twb_fixed 2120 UINT64_C(4093642432), // VST1d64Twb_register 2121 UINT64_C(4093642701), // VST1d64wb_fixed 2122 UINT64_C(4093642688), // VST1d64wb_register 2123 UINT64_C(4093642511), // VST1d8 2124 UINT64_C(4093641231), // VST1d8Q 2125 UINT64_C(4093641229), // VST1d8Qwb_fixed 2126 UINT64_C(4093641216), // VST1d8Qwb_register 2127 UINT64_C(4093642255), // VST1d8T 2128 UINT64_C(4093642253), // VST1d8Twb_fixed 2129 UINT64_C(4093642240), // VST1d8Twb_register 2130 UINT64_C(4093642509), // VST1d8wb_fixed 2131 UINT64_C(4093642496), // VST1d8wb_register 2132 UINT64_C(4093643343), // VST1q16 2133 UINT64_C(4093643341), // VST1q16wb_fixed 2134 UINT64_C(4093643328), // VST1q16wb_register 2135 UINT64_C(4093643407), // VST1q32 2136 UINT64_C(4093643405), // VST1q32wb_fixed 2137 UINT64_C(4093643392), // VST1q32wb_register 2138 UINT64_C(4093643471), // VST1q64 2139 UINT64_C(4093643469), // VST1q64wb_fixed 2140 UINT64_C(4093643456), // VST1q64wb_register 2141 UINT64_C(4093643279), // VST1q8 2142 UINT64_C(4093643277), // VST1q8wb_fixed 2143 UINT64_C(4093643264), // VST1q8wb_register 2144 UINT64_C(4102030607), // VST2LNd16 2145 UINT64_C(0), // VST2LNd16Pseudo 2146 UINT64_C(0), // VST2LNd16Pseudo_UPD 2147 UINT64_C(4102030592), // VST2LNd16_UPD 2148 UINT64_C(4102031631), // VST2LNd32 2149 UINT64_C(0), // VST2LNd32Pseudo 2150 UINT64_C(0), // VST2LNd32Pseudo_UPD 2151 UINT64_C(4102031616), // VST2LNd32_UPD 2152 UINT64_C(4102029583), // VST2LNd8 2153 UINT64_C(0), // VST2LNd8Pseudo 2154 UINT64_C(0), // VST2LNd8Pseudo_UPD 2155 UINT64_C(4102029568), // VST2LNd8_UPD 2156 UINT64_C(0), 2157 UINT64_C(0), 2158 UINT64_C(0), 2159 UINT64_C(0), 2160 UINT64_C(0), 2161 UINT64_C(0), 2162 UINT64_C(0), 2163 UINT64_C(0), 2164 UINT64_C(0), 2165 UINT64_C(4102030639), // VST2LNq16 2166 UINT64_C(0), // VST2LNq16Pseudo 2167 UINT64_C(0), // VST2LNq16Pseudo_UPD 2168 UINT64_C(4102030624), // VST2LNq16_UPD 2169 UINT64_C(4102031695), // VST2LNq32 2170 UINT64_C(0), // VST2LNq32Pseudo 2171 UINT64_C(0), // VST2LNq32Pseudo_UPD 2172 UINT64_C(4102031680), // VST2LNq32_UPD 2173 UINT64_C(0), 2174 UINT64_C(0), 2175 UINT64_C(0), 2176 UINT64_C(0), 2177 UINT64_C(0), 2178 UINT64_C(0), 2179 UINT64_C(4093643087), // VST2b16 2180 UINT64_C(4093643085), // VST2b16wb_fixed 2181 UINT64_C(4093643072), // VST2b16wb_register 2182 UINT64_C(4093643151), // VST2b32 2183 UINT64_C(4093643149), // VST2b32wb_fixed 2184 UINT64_C(4093643136), // VST2b32wb_register 2185 UINT64_C(4093643023), // VST2b8 2186 UINT64_C(4093643021), // VST2b8wb_fixed 2187 UINT64_C(4093643008), // VST2b8wb_register 2188 UINT64_C(4093642831), // VST2d16 2189 UINT64_C(4093642829), // VST2d16wb_fixed 2190 UINT64_C(4093642816), // VST2d16wb_register 2191 UINT64_C(4093642895), // VST2d32 2192 UINT64_C(4093642893), // VST2d32wb_fixed 2193 UINT64_C(4093642880), // VST2d32wb_register 2194 UINT64_C(4093642767), // VST2d8 2195 UINT64_C(4093642765), // VST2d8wb_fixed 2196 UINT64_C(4093642752), // VST2d8wb_register 2197 UINT64_C(4093641551), // VST2q16 2198 UINT64_C(0), // VST2q16Pseudo 2199 UINT64_C(0), // VST2q16PseudoWB_fixed 2200 UINT64_C(0), // VST2q16PseudoWB_register 2201 UINT64_C(4093641549), // VST2q16wb_fixed 2202 UINT64_C(4093641536), // VST2q16wb_register 2203 UINT64_C(4093641615), // VST2q32 2204 UINT64_C(0), // VST2q32Pseudo 2205 UINT64_C(0), // VST2q32PseudoWB_fixed 2206 UINT64_C(0), // VST2q32PseudoWB_register 2207 UINT64_C(4093641613), // VST2q32wb_fixed 2208 UINT64_C(4093641600), // VST2q32wb_register 2209 UINT64_C(4093641487), // VST2q8 2210 UINT64_C(0), // VST2q8Pseudo 2211 UINT64_C(0), // VST2q8PseudoWB_fixed 2212 UINT64_C(0), // VST2q8PseudoWB_register 2213 UINT64_C(4093641485), // VST2q8wb_fixed 2214 UINT64_C(4093641472), // VST2q8wb_register 2215 UINT64_C(4102030863), // VST3LNd16 2216 UINT64_C(0), // VST3LNd16Pseudo 2217 UINT64_C(0), // VST3LNd16Pseudo_UPD 2218 UINT64_C(4102030848), // VST3LNd16_UPD 2219 UINT64_C(4102031887), // VST3LNd32 2220 UINT64_C(0), // VST3LNd32Pseudo 2221 UINT64_C(0), // VST3LNd32Pseudo_UPD 2222 UINT64_C(4102031872), // VST3LNd32_UPD 2223 UINT64_C(4102029839), // VST3LNd8 2224 UINT64_C(0), // VST3LNd8Pseudo 2225 UINT64_C(0), // VST3LNd8Pseudo_UPD 2226 UINT64_C(4102029824), // VST3LNd8_UPD 2227 UINT64_C(0), 2228 UINT64_C(0), 2229 UINT64_C(0), 2230 UINT64_C(0), 2231 UINT64_C(0), 2232 UINT64_C(0), 2233 UINT64_C(0), 2234 UINT64_C(0), 2235 UINT64_C(0), 2236 UINT64_C(4102030895), // VST3LNq16 2237 UINT64_C(0), // VST3LNq16Pseudo 2238 UINT64_C(0), // VST3LNq16Pseudo_UPD 2239 UINT64_C(4102030880), // VST3LNq16_UPD 2240 UINT64_C(4102031951), // VST3LNq32 2241 UINT64_C(0), // VST3LNq32Pseudo 2242 UINT64_C(0), // VST3LNq32Pseudo_UPD 2243 UINT64_C(4102031936), // VST3LNq32_UPD 2244 UINT64_C(0), 2245 UINT64_C(0), 2246 UINT64_C(0), 2247 UINT64_C(0), 2248 UINT64_C(0), 2249 UINT64_C(0), 2250 UINT64_C(4093641807), // VST3d16 2251 UINT64_C(0), // VST3d16Pseudo 2252 UINT64_C(0), // VST3d16Pseudo_UPD 2253 UINT64_C(4093641792), // VST3d16_UPD 2254 UINT64_C(4093641871), // VST3d32 2255 UINT64_C(0), // VST3d32Pseudo 2256 UINT64_C(0), // VST3d32Pseudo_UPD 2257 UINT64_C(4093641856), // VST3d32_UPD 2258 UINT64_C(4093641743), // VST3d8 2259 UINT64_C(0), // VST3d8Pseudo 2260 UINT64_C(0), // VST3d8Pseudo_UPD 2261 UINT64_C(4093641728), // VST3d8_UPD 2262 UINT64_C(0), 2263 UINT64_C(0), 2264 UINT64_C(0), 2265 UINT64_C(0), 2266 UINT64_C(0), 2267 UINT64_C(0), 2268 UINT64_C(0), 2269 UINT64_C(0), 2270 UINT64_C(0), 2271 UINT64_C(4093642063), // VST3q16 2272 UINT64_C(0), // VST3q16Pseudo_UPD 2273 UINT64_C(4093642048), // VST3q16_UPD 2274 UINT64_C(0), // VST3q16oddPseudo 2275 UINT64_C(0), // VST3q16oddPseudo_UPD 2276 UINT64_C(4093642127), // VST3q32 2277 UINT64_C(0), // VST3q32Pseudo_UPD 2278 UINT64_C(4093642112), // VST3q32_UPD 2279 UINT64_C(0), // VST3q32oddPseudo 2280 UINT64_C(0), // VST3q32oddPseudo_UPD 2281 UINT64_C(4093641999), // VST3q8 2282 UINT64_C(0), // VST3q8Pseudo_UPD 2283 UINT64_C(4093641984), // VST3q8_UPD 2284 UINT64_C(0), // VST3q8oddPseudo 2285 UINT64_C(0), // VST3q8oddPseudo_UPD 2286 UINT64_C(0), 2287 UINT64_C(0), 2288 UINT64_C(0), 2289 UINT64_C(0), 2290 UINT64_C(0), 2291 UINT64_C(0), 2292 UINT64_C(0), 2293 UINT64_C(0), 2294 UINT64_C(0), 2295 UINT64_C(4102031119), // VST4LNd16 2296 UINT64_C(0), // VST4LNd16Pseudo 2297 UINT64_C(0), // VST4LNd16Pseudo_UPD 2298 UINT64_C(4102031104), // VST4LNd16_UPD 2299 UINT64_C(4102032143), // VST4LNd32 2300 UINT64_C(0), // VST4LNd32Pseudo 2301 UINT64_C(0), // VST4LNd32Pseudo_UPD 2302 UINT64_C(4102032128), // VST4LNd32_UPD 2303 UINT64_C(4102030095), // VST4LNd8 2304 UINT64_C(0), // VST4LNd8Pseudo 2305 UINT64_C(0), // VST4LNd8Pseudo_UPD 2306 UINT64_C(4102030080), // VST4LNd8_UPD 2307 UINT64_C(0), 2308 UINT64_C(0), 2309 UINT64_C(0), 2310 UINT64_C(0), 2311 UINT64_C(0), 2312 UINT64_C(0), 2313 UINT64_C(0), 2314 UINT64_C(0), 2315 UINT64_C(0), 2316 UINT64_C(4102031151), // VST4LNq16 2317 UINT64_C(0), // VST4LNq16Pseudo 2318 UINT64_C(0), // VST4LNq16Pseudo_UPD 2319 UINT64_C(4102031136), // VST4LNq16_UPD 2320 UINT64_C(4102032207), // VST4LNq32 2321 UINT64_C(0), // VST4LNq32Pseudo 2322 UINT64_C(0), // VST4LNq32Pseudo_UPD 2323 UINT64_C(4102032192), // VST4LNq32_UPD 2324 UINT64_C(0), 2325 UINT64_C(0), 2326 UINT64_C(0), 2327 UINT64_C(0), 2328 UINT64_C(0), 2329 UINT64_C(0), 2330 UINT64_C(4093640783), // VST4d16 2331 UINT64_C(0), // VST4d16Pseudo 2332 UINT64_C(0), // VST4d16Pseudo_UPD 2333 UINT64_C(4093640768), // VST4d16_UPD 2334 UINT64_C(4093640847), // VST4d32 2335 UINT64_C(0), // VST4d32Pseudo 2336 UINT64_C(0), // VST4d32Pseudo_UPD 2337 UINT64_C(4093640832), // VST4d32_UPD 2338 UINT64_C(4093640719), // VST4d8 2339 UINT64_C(0), // VST4d8Pseudo 2340 UINT64_C(0), // VST4d8Pseudo_UPD 2341 UINT64_C(4093640704), // VST4d8_UPD 2342 UINT64_C(0), 2343 UINT64_C(0), 2344 UINT64_C(0), 2345 UINT64_C(0), 2346 UINT64_C(0), 2347 UINT64_C(0), 2348 UINT64_C(0), 2349 UINT64_C(0), 2350 UINT64_C(0), 2351 UINT64_C(4093641039), // VST4q16 2352 UINT64_C(0), // VST4q16Pseudo_UPD 2353 UINT64_C(4093641024), // VST4q16_UPD 2354 UINT64_C(0), // VST4q16oddPseudo 2355 UINT64_C(0), // VST4q16oddPseudo_UPD 2356 UINT64_C(4093641103), // VST4q32 2357 UINT64_C(0), // VST4q32Pseudo_UPD 2358 UINT64_C(4093641088), // VST4q32_UPD 2359 UINT64_C(0), // VST4q32oddPseudo 2360 UINT64_C(0), // VST4q32oddPseudo_UPD 2361 UINT64_C(4093640975), // VST4q8 2362 UINT64_C(0), // VST4q8Pseudo_UPD 2363 UINT64_C(4093640960), // VST4q8_UPD 2364 UINT64_C(0), // VST4q8oddPseudo 2365 UINT64_C(0), // VST4q8oddPseudo_UPD 2366 UINT64_C(0), 2367 UINT64_C(0), 2368 UINT64_C(0), 2369 UINT64_C(0), 2370 UINT64_C(0), 2371 UINT64_C(0), 2372 UINT64_C(0), 2373 UINT64_C(0), 2374 UINT64_C(0), 2375 UINT64_C(220203776), // VSTMDDB_UPD 2376 UINT64_C(209718016), // VSTMDIA 2377 UINT64_C(211815168), // VSTMDIA_UPD 2378 UINT64_C(0), // VSTMQIA 2379 UINT64_C(220203520), // VSTMSDB_UPD 2380 UINT64_C(209717760), // VSTMSIA 2381 UINT64_C(211814912), // VSTMSIA_UPD 2382 UINT64_C(218106624), // VSTRD 2383 UINT64_C(218106112), // VSTRH 2384 UINT64_C(218106368), // VSTRS 2385 UINT64_C(238029632), // VSUBD 2386 UINT64_C(238029120), // VSUBH 2387 UINT64_C(4070573568), // VSUBHNv2i32 2388 UINT64_C(4069524992), // VSUBHNv4i16 2389 UINT64_C(4068476416), // VSUBHNv8i8 2390 UINT64_C(4070572544), // VSUBLsv2i64 2391 UINT64_C(4069523968), // VSUBLsv4i32 2392 UINT64_C(4068475392), // VSUBLsv8i16 2393 UINT64_C(4087349760), // VSUBLuv2i64 2394 UINT64_C(4086301184), // VSUBLuv4i32 2395 UINT64_C(4085252608), // VSUBLuv8i16 2396 UINT64_C(238029376), // VSUBS 2397 UINT64_C(4070572800), // VSUBWsv2i64 2398 UINT64_C(4069524224), // VSUBWsv4i32 2399 UINT64_C(4068475648), // VSUBWsv8i16 2400 UINT64_C(4087350016), // VSUBWuv2i64 2401 UINT64_C(4086301440), // VSUBWuv4i32 2402 UINT64_C(4085252864), // VSUBWuv8i16 2403 UINT64_C(4062186752), // VSUBfd 2404 UINT64_C(4062186816), // VSUBfq 2405 UINT64_C(4063235328), // VSUBhd 2406 UINT64_C(4063235392), // VSUBhq 2407 UINT64_C(4076865600), // VSUBv16i8 2408 UINT64_C(4080011264), // VSUBv1i64 2409 UINT64_C(4078962688), // VSUBv2i32 2410 UINT64_C(4080011328), // VSUBv2i64 2411 UINT64_C(4077914112), // VSUBv4i16 2412 UINT64_C(4078962752), // VSUBv4i32 2413 UINT64_C(4077914176), // VSUBv8i16 2414 UINT64_C(4076865536), // VSUBv8i8 2415 UINT64_C(4088528896), // VSWPd 2416 UINT64_C(4088528960), // VSWPq 2417 UINT64_C(4088399872), // VTBL1 2418 UINT64_C(4088400128), // VTBL2 2419 UINT64_C(4088400384), // VTBL3 2420 UINT64_C(0), // VTBL3Pseudo 2421 UINT64_C(4088400640), // VTBL4 2422 UINT64_C(0), // VTBL4Pseudo 2423 UINT64_C(4088399936), // VTBX1 2424 UINT64_C(4088400192), // VTBX2 2425 UINT64_C(4088400448), // VTBX3 2426 UINT64_C(0), // VTBX3Pseudo 2427 UINT64_C(4088400704), // VTBX4 2428 UINT64_C(0), // VTBX4Pseudo 2429 UINT64_C(247335744), // VTOSHD 2430 UINT64_C(247335232), // VTOSHH 2431 UINT64_C(247335488), // VTOSHS 2432 UINT64_C(247270208), // VTOSIRD 2433 UINT64_C(247269696), // VTOSIRH 2434 UINT64_C(247269952), // VTOSIRS 2435 UINT64_C(247270336), // VTOSIZD 2436 UINT64_C(247269824), // VTOSIZH 2437 UINT64_C(247270080), // VTOSIZS 2438 UINT64_C(247335872), // VTOSLD 2439 UINT64_C(247335360), // VTOSLH 2440 UINT64_C(247335616), // VTOSLS 2441 UINT64_C(247401280), // VTOUHD 2442 UINT64_C(247400768), // VTOUHH 2443 UINT64_C(247401024), // VTOUHS 2444 UINT64_C(247204672), // VTOUIRD 2445 UINT64_C(247204160), // VTOUIRH 2446 UINT64_C(247204416), // VTOUIRS 2447 UINT64_C(247204800), // VTOUIZD 2448 UINT64_C(247204288), // VTOUIZH 2449 UINT64_C(247204544), // VTOUIZS 2450 UINT64_C(247401408), // VTOULD 2451 UINT64_C(247400896), // VTOULH 2452 UINT64_C(247401152), // VTOULS 2453 UINT64_C(4088791168), // VTRNd16 2454 UINT64_C(4089053312), // VTRNd32 2455 UINT64_C(4088529024), // VTRNd8 2456 UINT64_C(4088791232), // VTRNq16 2457 UINT64_C(4089053376), // VTRNq32 2458 UINT64_C(4088529088), // VTRNq8 2459 UINT64_C(4060088400), // VTSTv16i8 2460 UINT64_C(4062185488), // VTSTv2i32 2461 UINT64_C(4061136912), // VTSTv4i16 2462 UINT64_C(4062185552), // VTSTv4i32 2463 UINT64_C(4061136976), // VTSTv8i16 2464 UINT64_C(4060088336), // VTSTv8i8 2465 UINT64_C(247139136), // VUHTOD 2466 UINT64_C(247138624), // VUHTOH 2467 UINT64_C(247138880), // VUHTOS 2468 UINT64_C(246942528), // VUITOD 2469 UINT64_C(246942016), // VUITOH 2470 UINT64_C(246942272), // VUITOS 2471 UINT64_C(247139264), // VULTOD 2472 UINT64_C(247138752), // VULTOH 2473 UINT64_C(247139008), // VULTOS 2474 UINT64_C(4088791296), // VUZPd16 2475 UINT64_C(4088529152), // VUZPd8 2476 UINT64_C(4088791360), // VUZPq16 2477 UINT64_C(4089053504), // VUZPq32 2478 UINT64_C(4088529216), // VUZPq8 2479 UINT64_C(4088791424), // VZIPd16 2480 UINT64_C(4088529280), // VZIPd8 2481 UINT64_C(4088791488), // VZIPq16 2482 UINT64_C(4089053632), // VZIPq32 2483 UINT64_C(4088529344), // VZIPq8 2484 UINT64_C(0), 2485 UINT64_C(0), 2486 UINT64_C(139460608), // sysLDMDA 2487 UINT64_C(141557760), // sysLDMDA_UPD 2488 UINT64_C(156237824), // sysLDMDB 2489 UINT64_C(158334976), // sysLDMDB_UPD 2490 UINT64_C(147849216), // sysLDMIA 2491 UINT64_C(149946368), // sysLDMIA_UPD 2492 UINT64_C(164626432), // sysLDMIB 2493 UINT64_C(166723584), // sysLDMIB_UPD 2494 UINT64_C(138412032), // sysSTMDA 2495 UINT64_C(140509184), // sysSTMDA_UPD 2496 UINT64_C(155189248), // sysSTMDB 2497 UINT64_C(157286400), // sysSTMDB_UPD 2498 UINT64_C(146800640), // sysSTMIA 2499 UINT64_C(148897792), // sysSTMIA_UPD 2500 UINT64_C(163577856), // sysSTMIB 2501 UINT64_C(165675008), // sysSTMIB_UPD 2502 UINT64_C(0), 2503 UINT64_C(4047503360), // t2ADCri 2504 UINT64_C(3946840064), // t2ADCrr 2505 UINT64_C(3946840064), // t2ADCrs 2506 UINT64_C(0), 2507 UINT64_C(0), 2508 UINT64_C(0), 2509 UINT64_C(4043309056), // t2ADDri 2510 UINT64_C(4060086272), // t2ADDri12 2511 UINT64_C(3942645760), // t2ADDrr 2512 UINT64_C(3942645760), // t2ADDrs 2513 UINT64_C(4061069312), // t2ADR 2514 UINT64_C(4026531840), // t2ANDri 2515 UINT64_C(3925868544), // t2ANDrr 2516 UINT64_C(3925868544), // t2ANDrs 2517 UINT64_C(3931045920), // t2ASRri 2518 UINT64_C(4198559744), // t2ASRrr 2519 UINT64_C(4026568704), // t2B 2520 UINT64_C(4084137984), // t2BFC 2521 UINT64_C(4083154944), // t2BFI 2522 UINT64_C(4028628992), // t2BICri 2523 UINT64_C(3927965696), // t2BICrr 2524 UINT64_C(3927965696), // t2BICrs 2525 UINT64_C(0), 2526 UINT64_C(4089483008), // t2BXJ 2527 UINT64_C(4026564608), // t2Bcc 2528 UINT64_C(3992977408), // t2CDP 2529 UINT64_C(4261412864), // t2CDP2 2530 UINT64_C(4089417519), // t2CLREX 2531 UINT64_C(4205899904), // t2CLZ 2532 UINT64_C(4044361472), // t2CMNri 2533 UINT64_C(3943698176), // t2CMNzrr 2534 UINT64_C(3943698176), // t2CMNzrs 2535 UINT64_C(4054847232), // t2CMPri 2536 UINT64_C(3954183936), // t2CMPrr 2537 UINT64_C(3954183936), // t2CMPrs 2538 UINT64_C(4088365312), // t2CPS1p 2539 UINT64_C(4088365056), // t2CPS2p 2540 UINT64_C(4088365312), // t2CPS3p 2541 UINT64_C(4206948480), // t2CRC32B 2542 UINT64_C(4207997056), // t2CRC32CB 2543 UINT64_C(4207997072), // t2CRC32CH 2544 UINT64_C(4207997088), // t2CRC32CW 2545 UINT64_C(4206948496), // t2CRC32H 2546 UINT64_C(4206948512), // t2CRC32W 2547 UINT64_C(4088365296), // t2DBG 2548 UINT64_C(4153376769), // t2DCPS1 2549 UINT64_C(4153376770), // t2DCPS2 2550 UINT64_C(4153376771), // t2DCPS3 2551 UINT64_C(4089417552), // t2DMB 2552 UINT64_C(4089417536), // t2DSB 2553 UINT64_C(4034920448), // t2EORri 2554 UINT64_C(3934257152), // t2EORrr 2555 UINT64_C(3934257152), // t2EORrs 2556 UINT64_C(4088365056), // t2HINT 2557 UINT64_C(4158685184), // t2HVC 2558 UINT64_C(4089417568), // t2ISB 2559 UINT64_C(48896), // t2IT 2560 UINT64_C(0), // t2Int_eh_sjlj_setjmp 2561 UINT64_C(0), // t2Int_eh_sjlj_setjmp_nofp 2562 UINT64_C(3905949615), // t2LDA 2563 UINT64_C(3905949583), // t2LDAB 2564 UINT64_C(3905949679), // t2LDAEX 2565 UINT64_C(3905949647), // t2LDAEXB 2566 UINT64_C(3905945855), // t2LDAEXD 2567 UINT64_C(3905949663), // t2LDAEXH 2568 UINT64_C(3905949599), // t2LDAH 2569 UINT64_C(4249878528), // t2LDC2L_OFFSET 2570 UINT64_C(4241489920), // t2LDC2L_OPTION 2571 UINT64_C(4235198464), // t2LDC2L_POST 2572 UINT64_C(4251975680), // t2LDC2L_PRE 2573 UINT64_C(4245684224), // t2LDC2_OFFSET 2574 UINT64_C(4237295616), // t2LDC2_OPTION 2575 UINT64_C(4231004160), // t2LDC2_POST 2576 UINT64_C(4247781376), // t2LDC2_PRE 2577 UINT64_C(3981443072), // t2LDCL_OFFSET 2578 UINT64_C(3973054464), // t2LDCL_OPTION 2579 UINT64_C(3966763008), // t2LDCL_POST 2580 UINT64_C(3983540224), // t2LDCL_PRE 2581 UINT64_C(3977248768), // t2LDC_OFFSET 2582 UINT64_C(3968860160), // t2LDC_OPTION 2583 UINT64_C(3962568704), // t2LDC_POST 2584 UINT64_C(3979345920), // t2LDC_PRE 2585 UINT64_C(3910139904), // t2LDMDB 2586 UINT64_C(3912237056), // t2LDMDB_UPD 2587 UINT64_C(3901751296), // t2LDMIA 2588 UINT64_C(0), 2589 UINT64_C(3903848448), // t2LDMIA_UPD 2590 UINT64_C(4161801728), // t2LDRBT 2591 UINT64_C(4161800448), // t2LDRB_POST 2592 UINT64_C(4161801472), // t2LDRB_PRE 2593 UINT64_C(4170186752), // t2LDRBi12 2594 UINT64_C(4161801216), // t2LDRBi8 2595 UINT64_C(4162781184), // t2LDRBpci 2596 UINT64_C(0), 2597 UINT64_C(4161798144), // t2LDRBs 2598 UINT64_C(3899654144), // t2LDRD_POST 2599 UINT64_C(3916431360), // t2LDRD_PRE 2600 UINT64_C(3914334208), // t2LDRDi8 2601 UINT64_C(3897560832), // t2LDREX 2602 UINT64_C(3905949519), // t2LDREXB 2603 UINT64_C(3905945727), // t2LDREXD 2604 UINT64_C(3905949535), // t2LDREXH 2605 UINT64_C(4163898880), // t2LDRHT 2606 UINT64_C(4163897600), // t2LDRH_POST 2607 UINT64_C(4163898624), // t2LDRH_PRE 2608 UINT64_C(4172283904), // t2LDRHi12 2609 UINT64_C(4163898368), // t2LDRHi8 2610 UINT64_C(4164878336), // t2LDRHpci 2611 UINT64_C(0), 2612 UINT64_C(4163895296), // t2LDRHs 2613 UINT64_C(4178578944), // t2LDRSBT 2614 UINT64_C(4178577664), // t2LDRSB_POST 2615 UINT64_C(4178578688), // t2LDRSB_PRE 2616 UINT64_C(4186963968), // t2LDRSBi12 2617 UINT64_C(4178578432), // t2LDRSBi8 2618 UINT64_C(4179558400), // t2LDRSBpci 2619 UINT64_C(0), 2620 UINT64_C(4178575360), // t2LDRSBs 2621 UINT64_C(4180676096), // t2LDRSHT 2622 UINT64_C(4180674816), // t2LDRSH_POST 2623 UINT64_C(4180675840), // t2LDRSH_PRE 2624 UINT64_C(4189061120), // t2LDRSHi12 2625 UINT64_C(4180675584), // t2LDRSHi8 2626 UINT64_C(4181655552), // t2LDRSHpci 2627 UINT64_C(0), 2628 UINT64_C(4180672512), // t2LDRSHs 2629 UINT64_C(4165996032), // t2LDRT 2630 UINT64_C(4165994752), // t2LDR_POST 2631 UINT64_C(4165995776), // t2LDR_PRE 2632 UINT64_C(4174381056), // t2LDRi12 2633 UINT64_C(4165995520), // t2LDRi8 2634 UINT64_C(4166975488), // t2LDRpci 2635 UINT64_C(0), 2636 UINT64_C(0), 2637 UINT64_C(4165992448), // t2LDRs 2638 UINT64_C(0), 2639 UINT64_C(0), 2640 UINT64_C(3931045888), // t2LSLri 2641 UINT64_C(4194365440), // t2LSLrr 2642 UINT64_C(3931045904), // t2LSRri 2643 UINT64_C(4196462592), // t2LSRrr 2644 UINT64_C(3992977424), // t2MCR 2645 UINT64_C(4261412880), // t2MCR2 2646 UINT64_C(3963617280), // t2MCRR 2647 UINT64_C(4232052736), // t2MCRR2 2648 UINT64_C(4211081216), // t2MLA 2649 UINT64_C(4211081232), // t2MLS 2650 UINT64_C(0), 2651 UINT64_C(0), 2652 UINT64_C(0), 2653 UINT64_C(0), 2654 UINT64_C(0), 2655 UINT64_C(0), 2656 UINT64_C(0), 2657 UINT64_C(0), 2658 UINT64_C(0), 2659 UINT64_C(0), 2660 UINT64_C(4072669184), // t2MOVTi16 2661 UINT64_C(0), 2662 UINT64_C(0), 2663 UINT64_C(4031709184), // t2MOVi 2664 UINT64_C(4064280576), // t2MOVi16 2665 UINT64_C(0), 2666 UINT64_C(0), 2667 UINT64_C(3931045888), // t2MOVr 2668 UINT64_C(0), 2669 UINT64_C(0), 2670 UINT64_C(3932094560), // t2MOVsra_flag 2671 UINT64_C(3932094544), // t2MOVsrl_flag 2672 UINT64_C(3994026000), // t2MRC 2673 UINT64_C(4262461456), // t2MRC2 2674 UINT64_C(3964665856), // t2MRRC 2675 UINT64_C(4233101312), // t2MRRC2 2676 UINT64_C(4092559360), // t2MRS_AR 2677 UINT64_C(4092559360), // t2MRS_M 2678 UINT64_C(4091576352), // t2MRSbanked 2679 UINT64_C(4093607936), // t2MRSsys_AR 2680 UINT64_C(4085284864), // t2MSR_AR 2681 UINT64_C(4085284864), // t2MSR_M 2682 UINT64_C(4085284896), // t2MSRbanked 2683 UINT64_C(4211142656), // t2MUL 2684 UINT64_C(0), 2685 UINT64_C(4033806336), // t2MVNi 2686 UINT64_C(3933143040), // t2MVNr 2687 UINT64_C(3933143040), // t2MVNs 2688 UINT64_C(4032823296), // t2ORNri 2689 UINT64_C(3932160000), // t2ORNrr 2690 UINT64_C(3932160000), // t2ORNrs 2691 UINT64_C(4030726144), // t2ORRri 2692 UINT64_C(3930062848), // t2ORRrr 2693 UINT64_C(3930062848), // t2ORRrs 2694 UINT64_C(3938451456), // t2PKHBT 2695 UINT64_C(3938451488), // t2PKHTB 2696 UINT64_C(4172345344), // t2PLDWi12 2697 UINT64_C(4163959808), // t2PLDWi8 2698 UINT64_C(4163956736), // t2PLDWs 2699 UINT64_C(4170248192), // t2PLDi12 2700 UINT64_C(4161862656), // t2PLDi8 2701 UINT64_C(4162842624), // t2PLDpci 2702 UINT64_C(4161859584), // t2PLDs 2703 UINT64_C(4187025408), // t2PLIi12 2704 UINT64_C(4178639872), // t2PLIi8 2705 UINT64_C(4179619840), // t2PLIpci 2706 UINT64_C(4178636800), // t2PLIs 2707 UINT64_C(4202754176), // t2QADD 2708 UINT64_C(4203802640), // t2QADD16 2709 UINT64_C(4202754064), // t2QADD8 2710 UINT64_C(4204851216), // t2QASX 2711 UINT64_C(4202754192), // t2QDADD 2712 UINT64_C(4202754224), // t2QDSUB 2713 UINT64_C(4209045520), // t2QSAX 2714 UINT64_C(4202754208), // t2QSUB 2715 UINT64_C(4207996944), // t2QSUB16 2716 UINT64_C(4206948368), // t2QSUB8 2717 UINT64_C(4203802784), // t2RBIT 2718 UINT64_C(4203802752), // t2REV 2719 UINT64_C(4203802768), // t2REV16 2720 UINT64_C(4203802800), // t2REVSH 2721 UINT64_C(3893411840), // t2RFEDB 2722 UINT64_C(3895508992), // t2RFEDBW 2723 UINT64_C(3918577664), // t2RFEIA 2724 UINT64_C(3920674816), // t2RFEIAW 2725 UINT64_C(3931045936), // t2RORri 2726 UINT64_C(4200656896), // t2RORrr 2727 UINT64_C(3931045936), // t2RRX 2728 UINT64_C(0), 2729 UINT64_C(0), 2730 UINT64_C(4055891968), // t2RSBri 2731 UINT64_C(3955228672), // t2RSBrr 2732 UINT64_C(3955228672), // t2RSBrs 2733 UINT64_C(4203802624), // t2SADD16 2734 UINT64_C(4202754048), // t2SADD8 2735 UINT64_C(4204851200), // t2SASX 2736 UINT64_C(4049600512), // t2SBCri 2737 UINT64_C(3948937216), // t2SBCrr 2738 UINT64_C(3948937216), // t2SBCrs 2739 UINT64_C(4081057792), // t2SBFX 2740 UINT64_C(4220580080), // t2SDIV 2741 UINT64_C(4204851328), // t2SEL 2742 UINT64_C(46608), // t2SETPAN 2743 UINT64_C(3917474175), // t2SG 2744 UINT64_C(4203802656), // t2SHADD16 2745 UINT64_C(4202754080), // t2SHADD8 2746 UINT64_C(4204851232), // t2SHASX 2747 UINT64_C(4209045536), // t2SHSAX 2748 UINT64_C(4207996960), // t2SHSUB16 2749 UINT64_C(4206948384), // t2SHSUB8 2750 UINT64_C(4159733760), // t2SMC 2751 UINT64_C(4212129792), // t2SMLABB 2752 UINT64_C(4212129808), // t2SMLABT 2753 UINT64_C(4213178368), // t2SMLAD 2754 UINT64_C(4213178384), // t2SMLADX 2755 UINT64_C(4223664128), // t2SMLAL 2756 UINT64_C(4223664256), // t2SMLALBB 2757 UINT64_C(4223664272), // t2SMLALBT 2758 UINT64_C(4223664320), // t2SMLALD 2759 UINT64_C(4223664336), // t2SMLALDX 2760 UINT64_C(4223664288), // t2SMLALTB 2761 UINT64_C(4223664304), // t2SMLALTT 2762 UINT64_C(4212129824), // t2SMLATB 2763 UINT64_C(4212129840), // t2SMLATT 2764 UINT64_C(4214226944), // t2SMLAWB 2765 UINT64_C(4214226960), // t2SMLAWT 2766 UINT64_C(4215275520), // t2SMLSD 2767 UINT64_C(4215275536), // t2SMLSDX 2768 UINT64_C(4224712896), // t2SMLSLD 2769 UINT64_C(4224712912), // t2SMLSLDX 2770 UINT64_C(4216324096), // t2SMMLA 2771 UINT64_C(4216324112), // t2SMMLAR 2772 UINT64_C(4217372672), // t2SMMLS 2773 UINT64_C(4217372688), // t2SMMLSR 2774 UINT64_C(4216385536), // t2SMMUL 2775 UINT64_C(4216385552), // t2SMMULR 2776 UINT64_C(4213239808), // t2SMUAD 2777 UINT64_C(4213239824), // t2SMUADX 2778 UINT64_C(4212191232), // t2SMULBB 2779 UINT64_C(4212191248), // t2SMULBT 2780 UINT64_C(4219469824), // t2SMULL 2781 UINT64_C(4212191264), // t2SMULTB 2782 UINT64_C(4212191280), // t2SMULTT 2783 UINT64_C(4214288384), // t2SMULWB 2784 UINT64_C(4214288400), // t2SMULWT 2785 UINT64_C(4215336960), // t2SMUSD 2786 UINT64_C(4215336976), // t2SMUSDX 2787 UINT64_C(3893215232), // t2SRSDB 2788 UINT64_C(3895312384), // t2SRSDB_UPD 2789 UINT64_C(3918381056), // t2SRSIA 2790 UINT64_C(3920478208), // t2SRSIA_UPD 2791 UINT64_C(4076863488), // t2SSAT 2792 UINT64_C(4078960640), // t2SSAT16 2793 UINT64_C(4209045504), // t2SSAX 2794 UINT64_C(4207996928), // t2SSUB16 2795 UINT64_C(4206948352), // t2SSUB8 2796 UINT64_C(4248829952), // t2STC2L_OFFSET 2797 UINT64_C(4240441344), // t2STC2L_OPTION 2798 UINT64_C(4234149888), // t2STC2L_POST 2799 UINT64_C(4250927104), // t2STC2L_PRE 2800 UINT64_C(4244635648), // t2STC2_OFFSET 2801 UINT64_C(4236247040), // t2STC2_OPTION 2802 UINT64_C(4229955584), // t2STC2_POST 2803 UINT64_C(4246732800), // t2STC2_PRE 2804 UINT64_C(3980394496), // t2STCL_OFFSET 2805 UINT64_C(3972005888), // t2STCL_OPTION 2806 UINT64_C(3965714432), // t2STCL_POST 2807 UINT64_C(3982491648), // t2STCL_PRE 2808 UINT64_C(3976200192), // t2STC_OFFSET 2809 UINT64_C(3967811584), // t2STC_OPTION 2810 UINT64_C(3961520128), // t2STC_POST 2811 UINT64_C(3978297344), // t2STC_PRE 2812 UINT64_C(3904901039), // t2STL 2813 UINT64_C(3904901007), // t2STLB 2814 UINT64_C(3904901088), // t2STLEX 2815 UINT64_C(3904901056), // t2STLEXB 2816 UINT64_C(3904897264), // t2STLEXD 2817 UINT64_C(3904901072), // t2STLEXH 2818 UINT64_C(3904901023), // t2STLH 2819 UINT64_C(3909091328), // t2STMDB 2820 UINT64_C(3911188480), // t2STMDB_UPD 2821 UINT64_C(3900702720), // t2STMIA 2822 UINT64_C(3902799872), // t2STMIA_UPD 2823 UINT64_C(4160753152), // t2STRBT 2824 UINT64_C(4160751872), // t2STRB_POST 2825 UINT64_C(4160752896), // t2STRB_PRE 2826 UINT64_C(0), 2827 UINT64_C(4169138176), // t2STRBi12 2828 UINT64_C(4160752640), // t2STRBi8 2829 UINT64_C(4160749568), // t2STRBs 2830 UINT64_C(3898605568), // t2STRD_POST 2831 UINT64_C(3915382784), // t2STRD_PRE 2832 UINT64_C(3913285632), // t2STRDi8 2833 UINT64_C(3896508416), // t2STREX 2834 UINT64_C(3904900928), // t2STREXB 2835 UINT64_C(3904897136), // t2STREXD 2836 UINT64_C(3904900944), // t2STREXH 2837 UINT64_C(4162850304), // t2STRHT 2838 UINT64_C(4162849024), // t2STRH_POST 2839 UINT64_C(4162850048), // t2STRH_PRE 2840 UINT64_C(0), 2841 UINT64_C(4171235328), // t2STRHi12 2842 UINT64_C(4162849792), // t2STRHi8 2843 UINT64_C(4162846720), // t2STRHs 2844 UINT64_C(4164947456), // t2STRT 2845 UINT64_C(4164946176), // t2STR_POST 2846 UINT64_C(4164947200), // t2STR_PRE 2847 UINT64_C(0), 2848 UINT64_C(4173332480), // t2STRi12 2849 UINT64_C(4164946944), // t2STRi8 2850 UINT64_C(4164943872), // t2STRs 2851 UINT64_C(4091449088), // t2SUBS_PC_LR 2852 UINT64_C(0), 2853 UINT64_C(0), 2854 UINT64_C(0), 2855 UINT64_C(4053794816), // t2SUBri 2856 UINT64_C(4070572032), // t2SUBri12 2857 UINT64_C(3953131520), // t2SUBrr 2858 UINT64_C(3953131520), // t2SUBrs 2859 UINT64_C(4198559872), // t2SXTAB 2860 UINT64_C(4196462720), // t2SXTAB16 2861 UINT64_C(4194365568), // t2SXTAH 2862 UINT64_C(4199542912), // t2SXTB 2863 UINT64_C(4197445760), // t2SXTB16 2864 UINT64_C(4195348608), // t2SXTH 2865 UINT64_C(3906007040), // t2TBB 2866 UINT64_C(0), 2867 UINT64_C(3906007056), // t2TBH 2868 UINT64_C(0), 2869 UINT64_C(4035972864), // t2TEQri 2870 UINT64_C(3935309568), // t2TEQrr 2871 UINT64_C(3935309568), // t2TEQrs 2872 UINT64_C(4027584256), // t2TSTri 2873 UINT64_C(3926920960), // t2TSTrr 2874 UINT64_C(3926920960), // t2TSTrs 2875 UINT64_C(3896569856), // t2TT 2876 UINT64_C(3896569984), // t2TTA 2877 UINT64_C(3896570048), // t2TTAT 2878 UINT64_C(3896569920), // t2TTT 2879 UINT64_C(4203802688), // t2UADD16 2880 UINT64_C(4202754112), // t2UADD8 2881 UINT64_C(4204851264), // t2UASX 2882 UINT64_C(4089446400), // t2UBFX 2883 UINT64_C(4159741952), // t2UDF 2884 UINT64_C(4222677232), // t2UDIV 2885 UINT64_C(4203802720), // t2UHADD16 2886 UINT64_C(4202754144), // t2UHADD8 2887 UINT64_C(4204851296), // t2UHASX 2888 UINT64_C(4209045600), // t2UHSAX 2889 UINT64_C(4207997024), // t2UHSUB16 2890 UINT64_C(4206948448), // t2UHSUB8 2891 UINT64_C(4225761376), // t2UMAAL 2892 UINT64_C(4225761280), // t2UMLAL 2893 UINT64_C(4221566976), // t2UMULL 2894 UINT64_C(4203802704), // t2UQADD16 2895 UINT64_C(4202754128), // t2UQADD8 2896 UINT64_C(4204851280), // t2UQASX 2897 UINT64_C(4209045584), // t2UQSAX 2898 UINT64_C(4207997008), // t2UQSUB16 2899 UINT64_C(4206948432), // t2UQSUB8 2900 UINT64_C(4218482688), // t2USAD8 2901 UINT64_C(4218421248), // t2USADA8 2902 UINT64_C(4085252096), // t2USAT 2903 UINT64_C(4087349248), // t2USAT16 2904 UINT64_C(4209045568), // t2USAX 2905 UINT64_C(4207996992), // t2USUB16 2906 UINT64_C(4206948416), // t2USUB8 2907 UINT64_C(4199608448), // t2UXTAB 2908 UINT64_C(4197511296), // t2UXTAB16 2909 UINT64_C(4195414144), // t2UXTAH 2910 UINT64_C(4200591488), // t2UXTB 2911 UINT64_C(4198494336), // t2UXTB16 2912 UINT64_C(4196397184), // t2UXTH 2913 UINT64_C(16704), // tADC 2914 UINT64_C(0), 2915 UINT64_C(17408), // tADDhirr 2916 UINT64_C(7168), // tADDi3 2917 UINT64_C(12288), // tADDi8 2918 UINT64_C(17512), // tADDrSP 2919 UINT64_C(43008), // tADDrSPi 2920 UINT64_C(6144), // tADDrr 2921 UINT64_C(45056), // tADDspi 2922 UINT64_C(17541), // tADDspr 2923 UINT64_C(0), 2924 UINT64_C(0), 2925 UINT64_C(40960), // tADR 2926 UINT64_C(16384), // tAND 2927 UINT64_C(4096), // tASRri 2928 UINT64_C(16640), // tASRrr 2929 UINT64_C(57344), // tB 2930 UINT64_C(17280), // tBIC 2931 UINT64_C(48640), // tBKPT 2932 UINT64_C(4026585088), // tBL 2933 UINT64_C(18308), // tBLXNSr 2934 UINT64_C(4026580992), // tBLXi 2935 UINT64_C(18304), // tBLXr 2936 UINT64_C(0), 2937 UINT64_C(0), 2938 UINT64_C(18176), // tBX 2939 UINT64_C(18180), // tBXNS 2940 UINT64_C(0), 2941 UINT64_C(0), 2942 UINT64_C(0), 2943 UINT64_C(53248), // tBcc 2944 UINT64_C(0), 2945 UINT64_C(47360), // tCBNZ 2946 UINT64_C(45312), // tCBZ 2947 UINT64_C(17088), // tCMNz 2948 UINT64_C(17664), // tCMPhir 2949 UINT64_C(10240), // tCMPi8 2950 UINT64_C(17024), // tCMPr 2951 UINT64_C(46688), // tCPS 2952 UINT64_C(16448), // tEOR 2953 UINT64_C(48896), // tHINT 2954 UINT64_C(47744), // tHLT 2955 UINT64_C(0), // tInt_eh_sjlj_longjmp 2956 UINT64_C(0), // tInt_eh_sjlj_setjmp 2957 UINT64_C(51200), // tLDMIA 2958 UINT64_C(0), 2959 UINT64_C(30720), // tLDRBi 2960 UINT64_C(23552), // tLDRBr 2961 UINT64_C(34816), // tLDRHi 2962 UINT64_C(23040), // tLDRHr 2963 UINT64_C(0), 2964 UINT64_C(0), 2965 UINT64_C(22016), // tLDRSB 2966 UINT64_C(24064), // tLDRSH 2967 UINT64_C(26624), // tLDRi 2968 UINT64_C(18432), // tLDRpci 2969 UINT64_C(0), 2970 UINT64_C(22528), // tLDRr 2971 UINT64_C(38912), // tLDRspi 2972 UINT64_C(0), 2973 UINT64_C(0), 2974 UINT64_C(0), // tLSLri 2975 UINT64_C(16512), // tLSLrr 2976 UINT64_C(2048), // tLSRri 2977 UINT64_C(16576), // tLSRrr 2978 UINT64_C(0), 2979 UINT64_C(0), // tMOVSr 2980 UINT64_C(8192), // tMOVi8 2981 UINT64_C(17920), // tMOVr 2982 UINT64_C(17216), // tMUL 2983 UINT64_C(17344), // tMVN 2984 UINT64_C(17152), // tORR 2985 UINT64_C(17528), // tPICADD 2986 UINT64_C(48128), // tPOP 2987 UINT64_C(0), 2988 UINT64_C(46080), // tPUSH 2989 UINT64_C(47616), // tREV 2990 UINT64_C(47680), // tREV16 2991 UINT64_C(47808), // tREVSH 2992 UINT64_C(16832), // tROR 2993 UINT64_C(16960), // tRSB 2994 UINT64_C(16768), // tSBC 2995 UINT64_C(46672), // tSETEND 2996 UINT64_C(49152), // tSTMIA_UPD 2997 UINT64_C(28672), // tSTRBi 2998 UINT64_C(21504), // tSTRBr 2999 UINT64_C(32768), // tSTRHi 3000 UINT64_C(20992), // tSTRHr 3001 UINT64_C(24576), // tSTRi 3002 UINT64_C(20480), // tSTRr 3003 UINT64_C(36864), // tSTRspi 3004 UINT64_C(7680), // tSUBi3 3005 UINT64_C(14336), // tSUBi8 3006 UINT64_C(6656), // tSUBrr 3007 UINT64_C(45184), // tSUBspi 3008 UINT64_C(57088), // tSVC 3009 UINT64_C(45632), // tSXTB 3010 UINT64_C(45568), // tSXTH 3011 UINT64_C(0), 3012 UINT64_C(0), 3013 UINT64_C(0), 3014 UINT64_C(0), 3015 UINT64_C(57086), // tTRAP 3016 UINT64_C(16896), // tTST 3017 UINT64_C(56832), // tUDF 3018 UINT64_C(45760), // tUXTB 3019 UINT64_C(45696), // tUXTH 3020 UINT64_C(0) 3021 }; 3022 const unsigned opcode = MI.getOpcode(); 3023 uint64_t Value = InstBits[opcode]; 3024 uint64_t op = 0; 3025 (void)op; // suppress warning 3026 switch (opcode) { 3027 case ARM::CLREX: 3028 case ARM::TRAP: 3029 case ARM::TRAPNaCl: 3030 case ARM::VLD1LNq16Pseudo: 3031 case ARM::VLD1LNq16Pseudo_UPD: 3032 case ARM::VLD1LNq32Pseudo: 3033 case ARM::VLD1LNq32Pseudo_UPD: 3034 case ARM::VLD1LNq8Pseudo: 3035 case ARM::VLD1LNq8Pseudo_UPD: 3036 case ARM::VLD1d64QPseudo: 3037 case ARM::VLD1d64QPseudoWB_fixed: 3038 case ARM::VLD1d64QPseudoWB_register: 3039 case ARM::VLD1d64TPseudo: 3040 case ARM::VLD1d64TPseudoWB_fixed: 3041 case ARM::VLD1d64TPseudoWB_register: 3042 case ARM::VLD2LNd16Pseudo: 3043 case ARM::VLD2LNd16Pseudo_UPD: 3044 case ARM::VLD2LNd32Pseudo: 3045 case ARM::VLD2LNd32Pseudo_UPD: 3046 case ARM::VLD2LNd8Pseudo: 3047 case ARM::VLD2LNd8Pseudo_UPD: 3048 case ARM::VLD2LNq16Pseudo: 3049 case ARM::VLD2LNq16Pseudo_UPD: 3050 case ARM::VLD2LNq32Pseudo: 3051 case ARM::VLD2LNq32Pseudo_UPD: 3052 case ARM::VLD2q16Pseudo: 3053 case ARM::VLD2q16PseudoWB_fixed: 3054 case ARM::VLD2q16PseudoWB_register: 3055 case ARM::VLD2q32Pseudo: 3056 case ARM::VLD2q32PseudoWB_fixed: 3057 case ARM::VLD2q32PseudoWB_register: 3058 case ARM::VLD2q8Pseudo: 3059 case ARM::VLD2q8PseudoWB_fixed: 3060 case ARM::VLD2q8PseudoWB_register: 3061 case ARM::VLD3DUPd16Pseudo: 3062 case ARM::VLD3DUPd16Pseudo_UPD: 3063 case ARM::VLD3DUPd32Pseudo: 3064 case ARM::VLD3DUPd32Pseudo_UPD: 3065 case ARM::VLD3DUPd8Pseudo: 3066 case ARM::VLD3DUPd8Pseudo_UPD: 3067 case ARM::VLD3LNd16Pseudo: 3068 case ARM::VLD3LNd16Pseudo_UPD: 3069 case ARM::VLD3LNd32Pseudo: 3070 case ARM::VLD3LNd32Pseudo_UPD: 3071 case ARM::VLD3LNd8Pseudo: 3072 case ARM::VLD3LNd8Pseudo_UPD: 3073 case ARM::VLD3LNq16Pseudo: 3074 case ARM::VLD3LNq16Pseudo_UPD: 3075 case ARM::VLD3LNq32Pseudo: 3076 case ARM::VLD3LNq32Pseudo_UPD: 3077 case ARM::VLD3d16Pseudo: 3078 case ARM::VLD3d16Pseudo_UPD: 3079 case ARM::VLD3d32Pseudo: 3080 case ARM::VLD3d32Pseudo_UPD: 3081 case ARM::VLD3d8Pseudo: 3082 case ARM::VLD3d8Pseudo_UPD: 3083 case ARM::VLD3q16Pseudo_UPD: 3084 case ARM::VLD3q16oddPseudo: 3085 case ARM::VLD3q16oddPseudo_UPD: 3086 case ARM::VLD3q32Pseudo_UPD: 3087 case ARM::VLD3q32oddPseudo: 3088 case ARM::VLD3q32oddPseudo_UPD: 3089 case ARM::VLD3q8Pseudo_UPD: 3090 case ARM::VLD3q8oddPseudo: 3091 case ARM::VLD3q8oddPseudo_UPD: 3092 case ARM::VLD4DUPd16Pseudo: 3093 case ARM::VLD4DUPd16Pseudo_UPD: 3094 case ARM::VLD4DUPd32Pseudo: 3095 case ARM::VLD4DUPd32Pseudo_UPD: 3096 case ARM::VLD4DUPd8Pseudo: 3097 case ARM::VLD4DUPd8Pseudo_UPD: 3098 case ARM::VLD4LNd16Pseudo: 3099 case ARM::VLD4LNd16Pseudo_UPD: 3100 case ARM::VLD4LNd32Pseudo: 3101 case ARM::VLD4LNd32Pseudo_UPD: 3102 case ARM::VLD4LNd8Pseudo: 3103 case ARM::VLD4LNd8Pseudo_UPD: 3104 case ARM::VLD4LNq16Pseudo: 3105 case ARM::VLD4LNq16Pseudo_UPD: 3106 case ARM::VLD4LNq32Pseudo: 3107 case ARM::VLD4LNq32Pseudo_UPD: 3108 case ARM::VLD4d16Pseudo: 3109 case ARM::VLD4d16Pseudo_UPD: 3110 case ARM::VLD4d32Pseudo: 3111 case ARM::VLD4d32Pseudo_UPD: 3112 case ARM::VLD4d8Pseudo: 3113 case ARM::VLD4d8Pseudo_UPD: 3114 case ARM::VLD4q16Pseudo_UPD: 3115 case ARM::VLD4q16oddPseudo: 3116 case ARM::VLD4q16oddPseudo_UPD: 3117 case ARM::VLD4q32Pseudo_UPD: 3118 case ARM::VLD4q32oddPseudo: 3119 case ARM::VLD4q32oddPseudo_UPD: 3120 case ARM::VLD4q8Pseudo_UPD: 3121 case ARM::VLD4q8oddPseudo: 3122 case ARM::VLD4q8oddPseudo_UPD: 3123 case ARM::VLDMQIA: 3124 case ARM::VST1LNq16Pseudo: 3125 case ARM::VST1LNq16Pseudo_UPD: 3126 case ARM::VST1LNq32Pseudo: 3127 case ARM::VST1LNq32Pseudo_UPD: 3128 case ARM::VST1LNq8Pseudo: 3129 case ARM::VST1LNq8Pseudo_UPD: 3130 case ARM::VST1d64QPseudo: 3131 case ARM::VST1d64QPseudoWB_fixed: 3132 case ARM::VST1d64QPseudoWB_register: 3133 case ARM::VST1d64TPseudo: 3134 case ARM::VST1d64TPseudoWB_fixed: 3135 case ARM::VST1d64TPseudoWB_register: 3136 case ARM::VST2LNd16Pseudo: 3137 case ARM::VST2LNd16Pseudo_UPD: 3138 case ARM::VST2LNd32Pseudo: 3139 case ARM::VST2LNd32Pseudo_UPD: 3140 case ARM::VST2LNd8Pseudo: 3141 case ARM::VST2LNd8Pseudo_UPD: 3142 case ARM::VST2LNq16Pseudo: 3143 case ARM::VST2LNq16Pseudo_UPD: 3144 case ARM::VST2LNq32Pseudo: 3145 case ARM::VST2LNq32Pseudo_UPD: 3146 case ARM::VST2q16Pseudo: 3147 case ARM::VST2q16PseudoWB_fixed: 3148 case ARM::VST2q16PseudoWB_register: 3149 case ARM::VST2q32Pseudo: 3150 case ARM::VST2q32PseudoWB_fixed: 3151 case ARM::VST2q32PseudoWB_register: 3152 case ARM::VST2q8Pseudo: 3153 case ARM::VST2q8PseudoWB_fixed: 3154 case ARM::VST2q8PseudoWB_register: 3155 case ARM::VST3LNd16Pseudo: 3156 case ARM::VST3LNd16Pseudo_UPD: 3157 case ARM::VST3LNd32Pseudo: 3158 case ARM::VST3LNd32Pseudo_UPD: 3159 case ARM::VST3LNd8Pseudo: 3160 case ARM::VST3LNd8Pseudo_UPD: 3161 case ARM::VST3LNq16Pseudo: 3162 case ARM::VST3LNq16Pseudo_UPD: 3163 case ARM::VST3LNq32Pseudo: 3164 case ARM::VST3LNq32Pseudo_UPD: 3165 case ARM::VST3d16Pseudo: 3166 case ARM::VST3d16Pseudo_UPD: 3167 case ARM::VST3d32Pseudo: 3168 case ARM::VST3d32Pseudo_UPD: 3169 case ARM::VST3d8Pseudo: 3170 case ARM::VST3d8Pseudo_UPD: 3171 case ARM::VST3q16Pseudo_UPD: 3172 case ARM::VST3q16oddPseudo: 3173 case ARM::VST3q16oddPseudo_UPD: 3174 case ARM::VST3q32Pseudo_UPD: 3175 case ARM::VST3q32oddPseudo: 3176 case ARM::VST3q32oddPseudo_UPD: 3177 case ARM::VST3q8Pseudo_UPD: 3178 case ARM::VST3q8oddPseudo: 3179 case ARM::VST3q8oddPseudo_UPD: 3180 case ARM::VST4LNd16Pseudo: 3181 case ARM::VST4LNd16Pseudo_UPD: 3182 case ARM::VST4LNd32Pseudo: 3183 case ARM::VST4LNd32Pseudo_UPD: 3184 case ARM::VST4LNd8Pseudo: 3185 case ARM::VST4LNd8Pseudo_UPD: 3186 case ARM::VST4LNq16Pseudo: 3187 case ARM::VST4LNq16Pseudo_UPD: 3188 case ARM::VST4LNq32Pseudo: 3189 case ARM::VST4LNq32Pseudo_UPD: 3190 case ARM::VST4d16Pseudo: 3191 case ARM::VST4d16Pseudo_UPD: 3192 case ARM::VST4d32Pseudo: 3193 case ARM::VST4d32Pseudo_UPD: 3194 case ARM::VST4d8Pseudo: 3195 case ARM::VST4d8Pseudo_UPD: 3196 case ARM::VST4q16Pseudo_UPD: 3197 case ARM::VST4q16oddPseudo: 3198 case ARM::VST4q16oddPseudo_UPD: 3199 case ARM::VST4q32Pseudo_UPD: 3200 case ARM::VST4q32oddPseudo: 3201 case ARM::VST4q32oddPseudo_UPD: 3202 case ARM::VST4q8Pseudo_UPD: 3203 case ARM::VST4q8oddPseudo: 3204 case ARM::VST4q8oddPseudo_UPD: 3205 case ARM::VSTMQIA: 3206 case ARM::VTBL3Pseudo: 3207 case ARM::VTBL4Pseudo: 3208 case ARM::VTBX3Pseudo: 3209 case ARM::VTBX4Pseudo: 3210 case ARM::t2CLREX: 3211 case ARM::t2DCPS1: 3212 case ARM::t2DCPS2: 3213 case ARM::t2DCPS3: 3214 case ARM::t2Int_eh_sjlj_setjmp: 3215 case ARM::t2Int_eh_sjlj_setjmp_nofp: 3216 case ARM::t2SG: 3217 case ARM::tInt_eh_sjlj_longjmp: 3218 case ARM::tInt_eh_sjlj_setjmp: 3219 case ARM::tTRAP: { 3220 break; 3221 } 3222 case ARM::VRINTAD: 3223 case ARM::VRINTMD: 3224 case ARM::VRINTND: 3225 case ARM::VRINTPD: { 3226 // op: Dd 3227 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3228 Value |= (op & UINT64_C(16)) << 18; 3229 Value |= (op & UINT64_C(15)) << 12; 3230 // op: Dm 3231 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3232 Value |= (op & UINT64_C(16)) << 1; 3233 Value |= op & UINT64_C(15); 3234 break; 3235 } 3236 case ARM::VMAXNMD: 3237 case ARM::VMINNMD: 3238 case ARM::VSELEQD: 3239 case ARM::VSELGED: 3240 case ARM::VSELGTD: 3241 case ARM::VSELVSD: { 3242 // op: Dd 3243 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3244 Value |= (op & UINT64_C(16)) << 18; 3245 Value |= (op & UINT64_C(15)) << 12; 3246 // op: Dn 3247 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3248 Value |= (op & UINT64_C(15)) << 16; 3249 Value |= (op & UINT64_C(16)) << 3; 3250 // op: Dm 3251 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3252 Value |= (op & UINT64_C(16)) << 1; 3253 Value |= op & UINT64_C(15); 3254 break; 3255 } 3256 case ARM::CRC32B: 3257 case ARM::CRC32CB: 3258 case ARM::CRC32CH: 3259 case ARM::CRC32CW: 3260 case ARM::CRC32H: 3261 case ARM::CRC32W: { 3262 // op: Rd 3263 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3264 Value |= (op & UINT64_C(15)) << 12; 3265 // op: Rn 3266 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3267 Value |= (op & UINT64_C(15)) << 16; 3268 // op: Rm 3269 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3270 Value |= op & UINT64_C(15); 3271 break; 3272 } 3273 case ARM::t2MRS_AR: 3274 case ARM::t2MRSsys_AR: { 3275 // op: Rd 3276 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3277 Value |= (op & UINT64_C(15)) << 8; 3278 break; 3279 } 3280 case ARM::t2CLZ: 3281 case ARM::t2RBIT: 3282 case ARM::t2REV: 3283 case ARM::t2REV16: 3284 case ARM::t2REVSH: { 3285 // op: Rd 3286 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3287 Value |= (op & UINT64_C(15)) << 8; 3288 // op: Rm 3289 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3290 Value |= (op & UINT64_C(15)) << 16; 3291 Value |= op & UINT64_C(15); 3292 break; 3293 } 3294 case ARM::t2MOVsra_flag: 3295 case ARM::t2MOVsrl_flag: { 3296 // op: Rd 3297 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3298 Value |= (op & UINT64_C(15)) << 8; 3299 // op: Rm 3300 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3301 Value |= op & UINT64_C(15); 3302 break; 3303 } 3304 case ARM::t2SXTB: 3305 case ARM::t2SXTB16: 3306 case ARM::t2SXTH: 3307 case ARM::t2UXTB: 3308 case ARM::t2UXTB16: 3309 case ARM::t2UXTH: { 3310 // op: Rd 3311 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3312 Value |= (op & UINT64_C(15)) << 8; 3313 // op: Rm 3314 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3315 Value |= op & UINT64_C(15); 3316 // op: rot 3317 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3318 Value |= (op & UINT64_C(3)) << 4; 3319 break; 3320 } 3321 case ARM::t2CRC32B: 3322 case ARM::t2CRC32CB: 3323 case ARM::t2CRC32CH: 3324 case ARM::t2CRC32CW: 3325 case ARM::t2CRC32H: 3326 case ARM::t2CRC32W: 3327 case ARM::t2MUL: 3328 case ARM::t2QADD16: 3329 case ARM::t2QADD8: 3330 case ARM::t2QASX: 3331 case ARM::t2QSAX: 3332 case ARM::t2QSUB16: 3333 case ARM::t2QSUB8: 3334 case ARM::t2SADD16: 3335 case ARM::t2SADD8: 3336 case ARM::t2SASX: 3337 case ARM::t2SDIV: 3338 case ARM::t2SEL: 3339 case ARM::t2SHADD16: 3340 case ARM::t2SHADD8: 3341 case ARM::t2SHASX: 3342 case ARM::t2SHSAX: 3343 case ARM::t2SHSUB16: 3344 case ARM::t2SHSUB8: 3345 case ARM::t2SMMUL: 3346 case ARM::t2SMMULR: 3347 case ARM::t2SMUAD: 3348 case ARM::t2SMUADX: 3349 case ARM::t2SMULBB: 3350 case ARM::t2SMULBT: 3351 case ARM::t2SMULTB: 3352 case ARM::t2SMULTT: 3353 case ARM::t2SMULWB: 3354 case ARM::t2SMULWT: 3355 case ARM::t2SMUSD: 3356 case ARM::t2SMUSDX: 3357 case ARM::t2SSAX: 3358 case ARM::t2SSUB16: 3359 case ARM::t2SSUB8: 3360 case ARM::t2UADD16: 3361 case ARM::t2UADD8: 3362 case ARM::t2UASX: 3363 case ARM::t2UDIV: 3364 case ARM::t2UHADD16: 3365 case ARM::t2UHADD8: 3366 case ARM::t2UHASX: 3367 case ARM::t2UHSAX: 3368 case ARM::t2UHSUB16: 3369 case ARM::t2UHSUB8: 3370 case ARM::t2UQADD16: 3371 case ARM::t2UQADD8: 3372 case ARM::t2UQASX: 3373 case ARM::t2UQSAX: 3374 case ARM::t2UQSUB16: 3375 case ARM::t2UQSUB8: 3376 case ARM::t2USAD8: 3377 case ARM::t2USAX: 3378 case ARM::t2USUB16: 3379 case ARM::t2USUB8: { 3380 // op: Rd 3381 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3382 Value |= (op & UINT64_C(15)) << 8; 3383 // op: Rn 3384 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3385 Value |= (op & UINT64_C(15)) << 16; 3386 // op: Rm 3387 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3388 Value |= op & UINT64_C(15); 3389 break; 3390 } 3391 case ARM::t2MLA: 3392 case ARM::t2MLS: 3393 case ARM::t2SMLABB: 3394 case ARM::t2SMLABT: 3395 case ARM::t2SMLAD: 3396 case ARM::t2SMLADX: 3397 case ARM::t2SMLATB: 3398 case ARM::t2SMLATT: 3399 case ARM::t2SMLAWB: 3400 case ARM::t2SMLAWT: 3401 case ARM::t2SMLSD: 3402 case ARM::t2SMLSDX: 3403 case ARM::t2SMMLA: 3404 case ARM::t2SMMLAR: 3405 case ARM::t2SMMLS: 3406 case ARM::t2SMMLSR: 3407 case ARM::t2USADA8: { 3408 // op: Rd 3409 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3410 Value |= (op & UINT64_C(15)) << 8; 3411 // op: Rn 3412 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3413 Value |= (op & UINT64_C(15)) << 16; 3414 // op: Rm 3415 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3416 Value |= op & UINT64_C(15); 3417 // op: Ra 3418 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 3419 Value |= (op & UINT64_C(15)) << 12; 3420 break; 3421 } 3422 case ARM::t2SXTAB: 3423 case ARM::t2SXTAB16: 3424 case ARM::t2SXTAH: 3425 case ARM::t2UXTAB: 3426 case ARM::t2UXTAB16: 3427 case ARM::t2UXTAH: { 3428 // op: Rd 3429 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3430 Value |= (op & UINT64_C(15)) << 8; 3431 // op: Rn 3432 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3433 Value |= (op & UINT64_C(15)) << 16; 3434 // op: Rm 3435 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3436 Value |= op & UINT64_C(15); 3437 // op: rot 3438 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 3439 Value |= (op & UINT64_C(3)) << 4; 3440 break; 3441 } 3442 case ARM::t2PKHBT: 3443 case ARM::t2PKHTB: { 3444 // op: Rd 3445 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3446 Value |= (op & UINT64_C(15)) << 8; 3447 // op: Rn 3448 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3449 Value |= (op & UINT64_C(15)) << 16; 3450 // op: Rm 3451 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3452 Value |= op & UINT64_C(15); 3453 // op: sh 3454 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 3455 Value |= (op & UINT64_C(28)) << 10; 3456 Value |= (op & UINT64_C(3)) << 6; 3457 break; 3458 } 3459 case ARM::t2ADDri12: 3460 case ARM::t2SUBri12: { 3461 // op: Rd 3462 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3463 Value |= (op & UINT64_C(15)) << 8; 3464 // op: Rn 3465 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3466 Value |= (op & UINT64_C(15)) << 16; 3467 // op: imm 3468 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3469 Value |= (op & UINT64_C(2048)) << 15; 3470 Value |= (op & UINT64_C(1792)) << 4; 3471 Value |= op & UINT64_C(255); 3472 break; 3473 } 3474 case ARM::t2QADD: 3475 case ARM::t2QDADD: 3476 case ARM::t2QDSUB: 3477 case ARM::t2QSUB: { 3478 // op: Rd 3479 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3480 Value |= (op & UINT64_C(15)) << 8; 3481 // op: Rn 3482 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3483 Value |= (op & UINT64_C(15)) << 16; 3484 // op: Rm 3485 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3486 Value |= op & UINT64_C(15); 3487 break; 3488 } 3489 case ARM::t2BFI: { 3490 // op: Rd 3491 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3492 Value |= (op & UINT64_C(15)) << 8; 3493 // op: Rn 3494 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3495 Value |= (op & UINT64_C(15)) << 16; 3496 // op: imm 3497 op = getBitfieldInvertedMaskOpValue(MI, 3, Fixups, STI); 3498 Value |= (op & UINT64_C(28)) << 10; 3499 Value |= (op & UINT64_C(3)) << 6; 3500 Value |= (op & UINT64_C(992)) >> 5; 3501 break; 3502 } 3503 case ARM::t2SSAT16: 3504 case ARM::t2USAT16: { 3505 // op: Rd 3506 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3507 Value |= (op & UINT64_C(15)) << 8; 3508 // op: Rn 3509 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3510 Value |= (op & UINT64_C(15)) << 16; 3511 // op: sat_imm 3512 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3513 Value |= op & UINT64_C(15); 3514 break; 3515 } 3516 case ARM::t2SSAT: 3517 case ARM::t2USAT: { 3518 // op: Rd 3519 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3520 Value |= (op & UINT64_C(15)) << 8; 3521 // op: Rn 3522 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3523 Value |= (op & UINT64_C(15)) << 16; 3524 // op: sat_imm 3525 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3526 Value |= op & UINT64_C(31); 3527 // op: sh 3528 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 3529 Value |= (op & UINT64_C(32)) << 16; 3530 Value |= (op & UINT64_C(28)) << 10; 3531 Value |= (op & UINT64_C(3)) << 6; 3532 break; 3533 } 3534 case ARM::t2STREX: { 3535 // op: Rd 3536 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3537 Value |= (op & UINT64_C(15)) << 8; 3538 // op: Rt 3539 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3540 Value |= (op & UINT64_C(15)) << 12; 3541 // op: addr 3542 op = getT2AddrModeImm0_1020s4OpValue(MI, 2, Fixups, STI); 3543 Value |= (op & UINT64_C(3840)) << 8; 3544 Value |= op & UINT64_C(255); 3545 break; 3546 } 3547 case ARM::t2MRS_M: { 3548 // op: Rd 3549 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3550 Value |= (op & UINT64_C(15)) << 8; 3551 // op: SYSm 3552 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3553 Value |= op & UINT64_C(255); 3554 break; 3555 } 3556 case ARM::t2ADR: { 3557 // op: Rd 3558 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3559 Value |= (op & UINT64_C(15)) << 8; 3560 // op: addr 3561 op = getT2AdrLabelOpValue(MI, 1, Fixups, STI); 3562 Value |= (op & UINT64_C(2048)) << 15; 3563 Value |= (op & UINT64_C(4096)) << 11; 3564 Value |= (op & UINT64_C(4096)) << 9; 3565 Value |= (op & UINT64_C(1792)) << 4; 3566 Value |= op & UINT64_C(255); 3567 break; 3568 } 3569 case ARM::t2BFC: { 3570 // op: Rd 3571 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3572 Value |= (op & UINT64_C(15)) << 8; 3573 // op: imm 3574 op = getBitfieldInvertedMaskOpValue(MI, 2, Fixups, STI); 3575 Value |= (op & UINT64_C(28)) << 10; 3576 Value |= (op & UINT64_C(3)) << 6; 3577 Value |= (op & UINT64_C(992)) >> 5; 3578 break; 3579 } 3580 case ARM::t2MOVi16: { 3581 // op: Rd 3582 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3583 Value |= (op & UINT64_C(15)) << 8; 3584 // op: imm 3585 op = getHiLo16ImmOpValue(MI, 1, Fixups, STI); 3586 Value |= (op & UINT64_C(2048)) << 15; 3587 Value |= (op & UINT64_C(61440)) << 4; 3588 Value |= (op & UINT64_C(1792)) << 4; 3589 Value |= op & UINT64_C(255); 3590 break; 3591 } 3592 case ARM::t2MOVTi16: { 3593 // op: Rd 3594 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3595 Value |= (op & UINT64_C(15)) << 8; 3596 // op: imm 3597 op = getHiLo16ImmOpValue(MI, 2, Fixups, STI); 3598 Value |= (op & UINT64_C(2048)) << 15; 3599 Value |= (op & UINT64_C(61440)) << 4; 3600 Value |= (op & UINT64_C(1792)) << 4; 3601 Value |= op & UINT64_C(255); 3602 break; 3603 } 3604 case ARM::t2SBFX: 3605 case ARM::t2UBFX: { 3606 // op: Rd 3607 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3608 Value |= (op & UINT64_C(15)) << 8; 3609 // op: msb 3610 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 3611 Value |= op & UINT64_C(31); 3612 // op: lsb 3613 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3614 Value |= (op & UINT64_C(28)) << 10; 3615 Value |= (op & UINT64_C(3)) << 6; 3616 // op: Rn 3617 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3618 Value |= (op & UINT64_C(15)) << 16; 3619 break; 3620 } 3621 case ARM::tADR: { 3622 // op: Rd 3623 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3624 Value |= (op & UINT64_C(7)) << 8; 3625 // op: addr 3626 op = getThumbAdrLabelOpValue(MI, 1, Fixups, STI); 3627 Value |= op & UINT64_C(255); 3628 break; 3629 } 3630 case ARM::tMOVi8: { 3631 // op: Rd 3632 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3633 Value |= (op & UINT64_C(7)) << 8; 3634 // op: imm8 3635 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3636 Value |= op & UINT64_C(255); 3637 break; 3638 } 3639 case ARM::tMOVr: { 3640 // op: Rd 3641 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3642 Value |= (op & UINT64_C(8)) << 4; 3643 Value |= op & UINT64_C(7); 3644 // op: Rm 3645 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3646 Value |= (op & UINT64_C(15)) << 3; 3647 break; 3648 } 3649 case ARM::t2STLEX: { 3650 // op: Rd 3651 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3652 Value |= op & UINT64_C(15); 3653 // op: Rt 3654 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3655 Value |= (op & UINT64_C(15)) << 12; 3656 // op: addr 3657 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3658 Value |= (op & UINT64_C(15)) << 16; 3659 break; 3660 } 3661 case ARM::t2STLEXB: 3662 case ARM::t2STLEXH: 3663 case ARM::t2STREXB: 3664 case ARM::t2STREXH: { 3665 // op: Rd 3666 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3667 Value |= op & UINT64_C(15); 3668 // op: addr 3669 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3670 Value |= (op & UINT64_C(15)) << 16; 3671 // op: Rt 3672 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3673 Value |= (op & UINT64_C(15)) << 12; 3674 break; 3675 } 3676 case ARM::t2STLEXD: 3677 case ARM::t2STREXD: { 3678 // op: Rd 3679 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3680 Value |= op & UINT64_C(15); 3681 // op: addr 3682 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 3683 Value |= (op & UINT64_C(15)) << 16; 3684 // op: Rt 3685 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3686 Value |= (op & UINT64_C(15)) << 12; 3687 // op: Rt2 3688 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3689 Value |= (op & UINT64_C(15)) << 8; 3690 break; 3691 } 3692 case ARM::tMOVSr: { 3693 // op: Rd 3694 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3695 Value |= op & UINT64_C(7); 3696 // op: Rm 3697 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3698 Value |= (op & UINT64_C(7)) << 3; 3699 break; 3700 } 3701 case ARM::tADDi3: 3702 case ARM::tSUBi3: { 3703 // op: Rd 3704 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3705 Value |= op & UINT64_C(7); 3706 // op: Rm 3707 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3708 Value |= (op & UINT64_C(7)) << 3; 3709 // op: imm3 3710 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 3711 Value |= (op & UINT64_C(7)) << 6; 3712 break; 3713 } 3714 case ARM::tASRri: 3715 case ARM::tLSLri: 3716 case ARM::tLSRri: { 3717 // op: Rd 3718 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3719 Value |= op & UINT64_C(7); 3720 // op: Rm 3721 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3722 Value |= (op & UINT64_C(7)) << 3; 3723 // op: imm5 3724 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 3725 Value |= (op & UINT64_C(31)) << 6; 3726 break; 3727 } 3728 case ARM::tMUL: 3729 case ARM::tMVN: 3730 case ARM::tRSB: { 3731 // op: Rd 3732 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3733 Value |= op & UINT64_C(7); 3734 // op: Rn 3735 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3736 Value |= (op & UINT64_C(7)) << 3; 3737 break; 3738 } 3739 case ARM::t2SMLALBB: 3740 case ARM::t2SMLALBT: 3741 case ARM::t2SMLALD: 3742 case ARM::t2SMLALDX: 3743 case ARM::t2SMLALTB: 3744 case ARM::t2SMLALTT: 3745 case ARM::t2SMLSLD: { 3746 // op: Rd 3747 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3748 Value |= (op & UINT64_C(15)) << 8; 3749 // op: Rn 3750 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3751 Value |= (op & UINT64_C(15)) << 16; 3752 // op: Rm 3753 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 3754 Value |= op & UINT64_C(15); 3755 // op: Ra 3756 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3757 Value |= (op & UINT64_C(15)) << 12; 3758 break; 3759 } 3760 case ARM::t2SMLSLDX: { 3761 // op: Rd 3762 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3763 Value |= (op & UINT64_C(15)) << 8; 3764 // op: Rn 3765 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 3766 Value |= (op & UINT64_C(15)) << 16; 3767 // op: Rm 3768 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3769 Value |= op & UINT64_C(15); 3770 // op: Ra 3771 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3772 Value |= (op & UINT64_C(15)) << 12; 3773 break; 3774 } 3775 case ARM::t2SMLAL: 3776 case ARM::t2SMULL: 3777 case ARM::t2UMAAL: 3778 case ARM::t2UMLAL: 3779 case ARM::t2UMULL: { 3780 // op: RdLo 3781 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3782 Value |= (op & UINT64_C(15)) << 12; 3783 // op: RdHi 3784 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3785 Value |= (op & UINT64_C(15)) << 8; 3786 // op: Rn 3787 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3788 Value |= (op & UINT64_C(15)) << 16; 3789 // op: Rm 3790 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 3791 Value |= op & UINT64_C(15); 3792 break; 3793 } 3794 case ARM::tADDi8: 3795 case ARM::tSUBi8: { 3796 // op: Rdn 3797 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3798 Value |= (op & UINT64_C(7)) << 8; 3799 // op: imm8 3800 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 3801 Value |= op & UINT64_C(255); 3802 break; 3803 } 3804 case ARM::tADDrSP: { 3805 // op: Rdn 3806 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3807 Value |= (op & UINT64_C(8)) << 4; 3808 Value |= op & UINT64_C(7); 3809 break; 3810 } 3811 case ARM::tADDhirr: { 3812 // op: Rdn 3813 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3814 Value |= (op & UINT64_C(8)) << 4; 3815 Value |= op & UINT64_C(7); 3816 // op: Rm 3817 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3818 Value |= (op & UINT64_C(15)) << 3; 3819 break; 3820 } 3821 case ARM::tADC: 3822 case ARM::tAND: 3823 case ARM::tASRrr: 3824 case ARM::tBIC: 3825 case ARM::tEOR: 3826 case ARM::tLSLrr: 3827 case ARM::tLSRrr: 3828 case ARM::tORR: 3829 case ARM::tROR: 3830 case ARM::tSBC: { 3831 // op: Rdn 3832 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3833 Value |= op & UINT64_C(7); 3834 // op: Rm 3835 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 3836 Value |= (op & UINT64_C(7)) << 3; 3837 break; 3838 } 3839 case ARM::tBX: 3840 case ARM::tBXNS: { 3841 // op: Rm 3842 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3843 Value |= (op & UINT64_C(15)) << 3; 3844 break; 3845 } 3846 case ARM::tCMPhir: { 3847 // op: Rm 3848 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3849 Value |= (op & UINT64_C(15)) << 3; 3850 // op: Rn 3851 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3852 Value |= (op & UINT64_C(8)) << 4; 3853 Value |= op & UINT64_C(7); 3854 break; 3855 } 3856 case ARM::tREV: 3857 case ARM::tREV16: 3858 case ARM::tREVSH: 3859 case ARM::tSXTB: 3860 case ARM::tSXTH: 3861 case ARM::tUXTB: 3862 case ARM::tUXTH: { 3863 // op: Rm 3864 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3865 Value |= (op & UINT64_C(7)) << 3; 3866 // op: Rd 3867 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3868 Value |= op & UINT64_C(7); 3869 break; 3870 } 3871 case ARM::tCMNz: 3872 case ARM::tCMPr: 3873 case ARM::tTST: { 3874 // op: Rm 3875 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3876 Value |= (op & UINT64_C(7)) << 3; 3877 // op: Rn 3878 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3879 Value |= op & UINT64_C(7); 3880 break; 3881 } 3882 case ARM::tADDspr: { 3883 // op: Rm 3884 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3885 Value |= (op & UINT64_C(15)) << 3; 3886 break; 3887 } 3888 case ARM::tADDrr: 3889 case ARM::tSUBrr: { 3890 // op: Rm 3891 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 3892 Value |= (op & UINT64_C(7)) << 6; 3893 // op: Rn 3894 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3895 Value |= (op & UINT64_C(7)) << 3; 3896 // op: Rd 3897 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3898 Value |= op & UINT64_C(7); 3899 break; 3900 } 3901 case ARM::RFEDA: 3902 case ARM::RFEDA_UPD: 3903 case ARM::RFEDB: 3904 case ARM::RFEDB_UPD: 3905 case ARM::RFEIA: 3906 case ARM::RFEIA_UPD: 3907 case ARM::RFEIB: 3908 case ARM::RFEIB_UPD: 3909 case ARM::t2RFEDB: 3910 case ARM::t2RFEDBW: 3911 case ARM::t2RFEIA: 3912 case ARM::t2RFEIAW: { 3913 // op: Rn 3914 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3915 Value |= (op & UINT64_C(15)) << 16; 3916 break; 3917 } 3918 case ARM::t2CMNzrr: 3919 case ARM::t2CMPrr: 3920 case ARM::t2TBB: 3921 case ARM::t2TBH: 3922 case ARM::t2TEQrr: 3923 case ARM::t2TSTrr: { 3924 // op: Rn 3925 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3926 Value |= (op & UINT64_C(15)) << 16; 3927 // op: Rm 3928 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3929 Value |= op & UINT64_C(15); 3930 break; 3931 } 3932 case ARM::t2CMNzrs: 3933 case ARM::t2CMPrs: 3934 case ARM::t2TEQrs: 3935 case ARM::t2TSTrs: { 3936 // op: Rn 3937 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3938 Value |= (op & UINT64_C(15)) << 16; 3939 // op: ShiftedRm 3940 op = getT2SORegOpValue(MI, 1, Fixups, STI); 3941 Value |= (op & UINT64_C(3584)) << 3; 3942 Value |= (op & UINT64_C(480)) >> 1; 3943 Value |= op & UINT64_C(15); 3944 break; 3945 } 3946 case ARM::t2CMNri: 3947 case ARM::t2CMPri: 3948 case ARM::t2TEQri: 3949 case ARM::t2TSTri: { 3950 // op: Rn 3951 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3952 Value |= (op & UINT64_C(15)) << 16; 3953 // op: imm 3954 op = getT2SOImmOpValue(MI, 1, Fixups, STI); 3955 Value |= (op & UINT64_C(2048)) << 15; 3956 Value |= (op & UINT64_C(1792)) << 4; 3957 Value |= op & UINT64_C(255); 3958 break; 3959 } 3960 case ARM::t2STMDB: 3961 case ARM::t2STMIA: { 3962 // op: Rn 3963 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3964 Value |= (op & UINT64_C(15)) << 16; 3965 // op: regs 3966 op = getRegisterListOpValue(MI, 3, Fixups, STI); 3967 Value |= op & UINT64_C(16384); 3968 Value |= op & UINT64_C(8191); 3969 break; 3970 } 3971 case ARM::t2LDMDB: 3972 case ARM::t2LDMIA: { 3973 // op: Rn 3974 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3975 Value |= (op & UINT64_C(15)) << 16; 3976 // op: regs 3977 op = getRegisterListOpValue(MI, 3, Fixups, STI); 3978 Value |= op & UINT64_C(65535); 3979 break; 3980 } 3981 case ARM::tCMPi8: { 3982 // op: Rn 3983 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3984 Value |= (op & UINT64_C(7)) << 8; 3985 // op: imm8 3986 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3987 Value |= op & UINT64_C(255); 3988 break; 3989 } 3990 case ARM::tLDMIA: { 3991 // op: Rn 3992 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3993 Value |= (op & UINT64_C(7)) << 8; 3994 // op: regs 3995 op = getRegisterListOpValue(MI, 3, Fixups, STI); 3996 Value |= op & UINT64_C(255); 3997 break; 3998 } 3999 case ARM::t2TT: 4000 case ARM::t2TTA: 4001 case ARM::t2TTAT: 4002 case ARM::t2TTT: { 4003 // op: Rn 4004 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4005 Value |= (op & UINT64_C(15)) << 16; 4006 // op: Rt 4007 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4008 Value |= (op & UINT64_C(15)) << 8; 4009 break; 4010 } 4011 case ARM::t2STMDB_UPD: 4012 case ARM::t2STMIA_UPD: { 4013 // op: Rn 4014 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4015 Value |= (op & UINT64_C(15)) << 16; 4016 // op: regs 4017 op = getRegisterListOpValue(MI, 4, Fixups, STI); 4018 Value |= op & UINT64_C(16384); 4019 Value |= op & UINT64_C(8191); 4020 break; 4021 } 4022 case ARM::t2LDMDB_UPD: 4023 case ARM::t2LDMIA_UPD: { 4024 // op: Rn 4025 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4026 Value |= (op & UINT64_C(15)) << 16; 4027 // op: regs 4028 op = getRegisterListOpValue(MI, 4, Fixups, STI); 4029 Value |= op & UINT64_C(65535); 4030 break; 4031 } 4032 case ARM::tSTMIA_UPD: { 4033 // op: Rn 4034 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4035 Value |= (op & UINT64_C(7)) << 8; 4036 // op: regs 4037 op = getRegisterListOpValue(MI, 4, Fixups, STI); 4038 Value |= op & UINT64_C(255); 4039 break; 4040 } 4041 case ARM::t2LDRB_POST: 4042 case ARM::t2LDRH_POST: 4043 case ARM::t2LDRSB_POST: 4044 case ARM::t2LDRSH_POST: 4045 case ARM::t2LDR_POST: { 4046 // op: Rt 4047 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4048 Value |= (op & UINT64_C(15)) << 12; 4049 // op: Rn 4050 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4051 Value |= (op & UINT64_C(15)) << 16; 4052 // op: offset 4053 op = getT2AddrModeImm8OffsetOpValue(MI, 3, Fixups, STI); 4054 Value |= (op & UINT64_C(256)) << 1; 4055 Value |= op & UINT64_C(255); 4056 break; 4057 } 4058 case ARM::t2MRRC: 4059 case ARM::t2MRRC2: { 4060 // op: Rt 4061 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4062 Value |= (op & UINT64_C(15)) << 12; 4063 // op: Rt2 4064 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4065 Value |= (op & UINT64_C(15)) << 16; 4066 // op: cop 4067 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4068 Value |= (op & UINT64_C(15)) << 8; 4069 // op: opc1 4070 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4071 Value |= (op & UINT64_C(15)) << 4; 4072 // op: CRm 4073 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 4074 Value |= op & UINT64_C(15); 4075 break; 4076 } 4077 case ARM::t2LDRD_POST: { 4078 // op: Rt 4079 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4080 Value |= (op & UINT64_C(15)) << 12; 4081 // op: Rt2 4082 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4083 Value |= (op & UINT64_C(15)) << 8; 4084 // op: addr 4085 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4086 Value |= (op & UINT64_C(15)) << 16; 4087 // op: imm 4088 op = getT2Imm8s4OpValue(MI, 4, Fixups, STI); 4089 Value |= (op & UINT64_C(256)) << 15; 4090 Value |= op & UINT64_C(255); 4091 break; 4092 } 4093 case ARM::t2LDRDi8: 4094 case ARM::t2STRDi8: { 4095 // op: Rt 4096 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4097 Value |= (op & UINT64_C(15)) << 12; 4098 // op: Rt2 4099 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4100 Value |= (op & UINT64_C(15)) << 8; 4101 // op: addr 4102 op = getT2AddrModeImm8s4OpValue(MI, 2, Fixups, STI); 4103 Value |= (op & UINT64_C(256)) << 15; 4104 Value |= (op & UINT64_C(7680)) << 7; 4105 Value |= op & UINT64_C(255); 4106 break; 4107 } 4108 case ARM::t2LDRD_PRE: { 4109 // op: Rt 4110 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4111 Value |= (op & UINT64_C(15)) << 12; 4112 // op: Rt2 4113 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4114 Value |= (op & UINT64_C(15)) << 8; 4115 // op: addr 4116 op = getT2AddrModeImm8s4OpValue(MI, 3, Fixups, STI); 4117 Value |= (op & UINT64_C(256)) << 15; 4118 Value |= (op & UINT64_C(7680)) << 7; 4119 Value |= op & UINT64_C(255); 4120 break; 4121 } 4122 case ARM::t2LDRBi12: 4123 case ARM::t2LDRHi12: 4124 case ARM::t2LDRSBi12: 4125 case ARM::t2LDRSHi12: 4126 case ARM::t2LDRi12: 4127 case ARM::t2STRBi12: 4128 case ARM::t2STRHi12: 4129 case ARM::t2STRi12: { 4130 // op: Rt 4131 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4132 Value |= (op & UINT64_C(15)) << 12; 4133 // op: addr 4134 op = getAddrModeImm12OpValue(MI, 1, Fixups, STI); 4135 Value |= (op & UINT64_C(122880)) << 3; 4136 Value |= op & UINT64_C(4095); 4137 break; 4138 } 4139 case ARM::t2LDRBpci: 4140 case ARM::t2LDRHpci: 4141 case ARM::t2LDRSBpci: 4142 case ARM::t2LDRSHpci: 4143 case ARM::t2LDRpci: { 4144 // op: Rt 4145 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4146 Value |= (op & UINT64_C(15)) << 12; 4147 // op: addr 4148 op = getAddrModeImm12OpValue(MI, 1, Fixups, STI); 4149 Value |= (op & UINT64_C(4096)) << 11; 4150 Value |= op & UINT64_C(4095); 4151 break; 4152 } 4153 case ARM::t2LDA: 4154 case ARM::t2LDAB: 4155 case ARM::t2LDAEX: 4156 case ARM::t2LDAH: 4157 case ARM::t2STL: 4158 case ARM::t2STLB: 4159 case ARM::t2STLH: { 4160 // op: Rt 4161 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4162 Value |= (op & UINT64_C(15)) << 12; 4163 // op: addr 4164 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4165 Value |= (op & UINT64_C(15)) << 16; 4166 break; 4167 } 4168 case ARM::t2LDREX: { 4169 // op: Rt 4170 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4171 Value |= (op & UINT64_C(15)) << 12; 4172 // op: addr 4173 op = getT2AddrModeImm0_1020s4OpValue(MI, 1, Fixups, STI); 4174 Value |= (op & UINT64_C(3840)) << 8; 4175 Value |= op & UINT64_C(255); 4176 break; 4177 } 4178 case ARM::t2LDRBi8: 4179 case ARM::t2LDRHi8: 4180 case ARM::t2LDRSBi8: 4181 case ARM::t2LDRSHi8: 4182 case ARM::t2LDRi8: 4183 case ARM::t2STRBi8: 4184 case ARM::t2STRHi8: 4185 case ARM::t2STRi8: { 4186 // op: Rt 4187 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4188 Value |= (op & UINT64_C(15)) << 12; 4189 // op: addr 4190 op = getT2AddrModeImm8OpValue(MI, 1, Fixups, STI); 4191 Value |= (op & UINT64_C(7680)) << 7; 4192 Value |= (op & UINT64_C(256)) << 1; 4193 Value |= op & UINT64_C(255); 4194 break; 4195 } 4196 case ARM::t2LDRBT: 4197 case ARM::t2LDRHT: 4198 case ARM::t2LDRSBT: 4199 case ARM::t2LDRSHT: 4200 case ARM::t2LDRT: 4201 case ARM::t2STRBT: 4202 case ARM::t2STRHT: 4203 case ARM::t2STRT: { 4204 // op: Rt 4205 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4206 Value |= (op & UINT64_C(15)) << 12; 4207 // op: addr 4208 op = getT2AddrModeImm8OpValue(MI, 1, Fixups, STI); 4209 Value |= (op & UINT64_C(7680)) << 7; 4210 Value |= op & UINT64_C(255); 4211 break; 4212 } 4213 case ARM::t2LDRB_PRE: 4214 case ARM::t2LDRH_PRE: 4215 case ARM::t2LDRSB_PRE: 4216 case ARM::t2LDRSH_PRE: 4217 case ARM::t2LDR_PRE: { 4218 // op: Rt 4219 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4220 Value |= (op & UINT64_C(15)) << 12; 4221 // op: addr 4222 op = getT2AddrModeImm8OpValue(MI, 2, Fixups, STI); 4223 Value |= (op & UINT64_C(7680)) << 7; 4224 Value |= (op & UINT64_C(256)) << 1; 4225 Value |= op & UINT64_C(255); 4226 break; 4227 } 4228 case ARM::t2LDRBs: 4229 case ARM::t2LDRHs: 4230 case ARM::t2LDRSBs: 4231 case ARM::t2LDRSHs: 4232 case ARM::t2LDRs: 4233 case ARM::t2STRBs: 4234 case ARM::t2STRHs: 4235 case ARM::t2STRs: { 4236 // op: Rt 4237 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4238 Value |= (op & UINT64_C(15)) << 12; 4239 // op: addr 4240 op = getT2AddrModeSORegOpValue(MI, 1, Fixups, STI); 4241 Value |= (op & UINT64_C(960)) << 10; 4242 Value |= (op & UINT64_C(3)) << 4; 4243 Value |= (op & UINT64_C(60)) >> 2; 4244 break; 4245 } 4246 case ARM::MRC2: 4247 case ARM::t2MRC: 4248 case ARM::t2MRC2: { 4249 // op: Rt 4250 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4251 Value |= (op & UINT64_C(15)) << 12; 4252 // op: cop 4253 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4254 Value |= (op & UINT64_C(15)) << 8; 4255 // op: opc1 4256 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4257 Value |= (op & UINT64_C(7)) << 21; 4258 // op: opc2 4259 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 4260 Value |= (op & UINT64_C(7)) << 5; 4261 // op: CRm 4262 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 4263 Value |= op & UINT64_C(15); 4264 // op: CRn 4265 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4266 Value |= (op & UINT64_C(15)) << 16; 4267 break; 4268 } 4269 case ARM::tLDRpci: { 4270 // op: Rt 4271 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4272 Value |= (op & UINT64_C(7)) << 8; 4273 // op: addr 4274 op = getAddrModePCOpValue(MI, 1, Fixups, STI); 4275 Value |= op & UINT64_C(255); 4276 break; 4277 } 4278 case ARM::tLDRspi: 4279 case ARM::tSTRspi: { 4280 // op: Rt 4281 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4282 Value |= (op & UINT64_C(7)) << 8; 4283 // op: addr 4284 op = getAddrModeThumbSPOpValue(MI, 1, Fixups, STI); 4285 Value |= op & UINT64_C(255); 4286 break; 4287 } 4288 case ARM::tLDRBi: 4289 case ARM::tLDRHi: 4290 case ARM::tLDRi: 4291 case ARM::tSTRBi: 4292 case ARM::tSTRHi: 4293 case ARM::tSTRi: { 4294 // op: Rt 4295 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4296 Value |= op & UINT64_C(7); 4297 // op: addr 4298 op = getAddrModeISOpValue(MI, 1, Fixups, STI); 4299 Value |= (op & UINT64_C(255)) << 3; 4300 break; 4301 } 4302 case ARM::tLDRBr: 4303 case ARM::tLDRHr: 4304 case ARM::tLDRSB: 4305 case ARM::tLDRSH: 4306 case ARM::tLDRr: 4307 case ARM::tSTRBr: 4308 case ARM::tSTRHr: 4309 case ARM::tSTRr: { 4310 // op: Rt 4311 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4312 Value |= op & UINT64_C(7); 4313 // op: addr 4314 op = getThumbAddrModeRegRegOpValue(MI, 1, Fixups, STI); 4315 Value |= (op & UINT64_C(63)) << 3; 4316 break; 4317 } 4318 case ARM::t2STRB_POST: 4319 case ARM::t2STRH_POST: 4320 case ARM::t2STR_POST: { 4321 // op: Rt 4322 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4323 Value |= (op & UINT64_C(15)) << 12; 4324 // op: Rn 4325 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4326 Value |= (op & UINT64_C(15)) << 16; 4327 // op: offset 4328 op = getT2AddrModeImm8OffsetOpValue(MI, 3, Fixups, STI); 4329 Value |= (op & UINT64_C(256)) << 1; 4330 Value |= op & UINT64_C(255); 4331 break; 4332 } 4333 case ARM::t2STRD_POST: { 4334 // op: Rt 4335 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4336 Value |= (op & UINT64_C(15)) << 12; 4337 // op: Rt2 4338 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4339 Value |= (op & UINT64_C(15)) << 8; 4340 // op: addr 4341 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4342 Value |= (op & UINT64_C(15)) << 16; 4343 // op: imm 4344 op = getT2Imm8s4OpValue(MI, 4, Fixups, STI); 4345 Value |= (op & UINT64_C(256)) << 15; 4346 Value |= op & UINT64_C(255); 4347 break; 4348 } 4349 case ARM::t2STRD_PRE: { 4350 // op: Rt 4351 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4352 Value |= (op & UINT64_C(15)) << 12; 4353 // op: Rt2 4354 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4355 Value |= (op & UINT64_C(15)) << 8; 4356 // op: addr 4357 op = getT2AddrModeImm8s4OpValue(MI, 3, Fixups, STI); 4358 Value |= (op & UINT64_C(256)) << 15; 4359 Value |= (op & UINT64_C(7680)) << 7; 4360 Value |= op & UINT64_C(255); 4361 break; 4362 } 4363 case ARM::t2STRB_PRE: 4364 case ARM::t2STRH_PRE: 4365 case ARM::t2STR_PRE: { 4366 // op: Rt 4367 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4368 Value |= (op & UINT64_C(15)) << 12; 4369 // op: addr 4370 op = getT2AddrModeImm8OpValue(MI, 2, Fixups, STI); 4371 Value |= (op & UINT64_C(7680)) << 7; 4372 Value |= (op & UINT64_C(256)) << 1; 4373 Value |= op & UINT64_C(255); 4374 break; 4375 } 4376 case ARM::MCRR2: 4377 case ARM::MRRC2: 4378 case ARM::t2MCRR: 4379 case ARM::t2MCRR2: { 4380 // op: Rt 4381 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4382 Value |= (op & UINT64_C(15)) << 12; 4383 // op: Rt2 4384 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4385 Value |= (op & UINT64_C(15)) << 16; 4386 // op: cop 4387 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4388 Value |= (op & UINT64_C(15)) << 8; 4389 // op: opc1 4390 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4391 Value |= (op & UINT64_C(15)) << 4; 4392 // op: CRm 4393 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 4394 Value |= op & UINT64_C(15); 4395 break; 4396 } 4397 case ARM::MCR2: 4398 case ARM::t2MCR: 4399 case ARM::t2MCR2: { 4400 // op: Rt 4401 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4402 Value |= (op & UINT64_C(15)) << 12; 4403 // op: cop 4404 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4405 Value |= (op & UINT64_C(15)) << 8; 4406 // op: opc1 4407 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4408 Value |= (op & UINT64_C(7)) << 21; 4409 // op: opc2 4410 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 4411 Value |= (op & UINT64_C(7)) << 5; 4412 // op: CRm 4413 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 4414 Value |= op & UINT64_C(15); 4415 // op: CRn 4416 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4417 Value |= (op & UINT64_C(15)) << 16; 4418 break; 4419 } 4420 case ARM::t2MSR_M: { 4421 // op: SYSm 4422 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4423 Value |= op & UINT64_C(3072); 4424 Value |= op & UINT64_C(255); 4425 // op: Rn 4426 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4427 Value |= (op & UINT64_C(15)) << 16; 4428 break; 4429 } 4430 case ARM::VCVTASD: 4431 case ARM::VCVTAUD: 4432 case ARM::VCVTMSD: 4433 case ARM::VCVTMUD: 4434 case ARM::VCVTNSD: 4435 case ARM::VCVTNUD: 4436 case ARM::VCVTPSD: 4437 case ARM::VCVTPUD: { 4438 // op: Sd 4439 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4440 Value |= (op & UINT64_C(1)) << 22; 4441 Value |= (op & UINT64_C(30)) << 11; 4442 // op: Dm 4443 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4444 Value |= (op & UINT64_C(16)) << 1; 4445 Value |= op & UINT64_C(15); 4446 break; 4447 } 4448 case ARM::VCVTASH: 4449 case ARM::VCVTASS: 4450 case ARM::VCVTAUH: 4451 case ARM::VCVTAUS: 4452 case ARM::VCVTMSH: 4453 case ARM::VCVTMSS: 4454 case ARM::VCVTMUH: 4455 case ARM::VCVTMUS: 4456 case ARM::VCVTNSH: 4457 case ARM::VCVTNSS: 4458 case ARM::VCVTNUH: 4459 case ARM::VCVTNUS: 4460 case ARM::VCVTPSH: 4461 case ARM::VCVTPSS: 4462 case ARM::VCVTPUH: 4463 case ARM::VCVTPUS: 4464 case ARM::VINSH: 4465 case ARM::VMOVH: 4466 case ARM::VRINTAH: 4467 case ARM::VRINTAS: 4468 case ARM::VRINTMH: 4469 case ARM::VRINTMS: 4470 case ARM::VRINTNH: 4471 case ARM::VRINTNS: 4472 case ARM::VRINTPH: 4473 case ARM::VRINTPS: { 4474 // op: Sd 4475 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4476 Value |= (op & UINT64_C(1)) << 22; 4477 Value |= (op & UINT64_C(30)) << 11; 4478 // op: Sm 4479 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4480 Value |= (op & UINT64_C(1)) << 5; 4481 Value |= (op & UINT64_C(30)) >> 1; 4482 break; 4483 } 4484 case ARM::VMAXNMH: 4485 case ARM::VMAXNMS: 4486 case ARM::VMINNMH: 4487 case ARM::VMINNMS: 4488 case ARM::VSELEQH: 4489 case ARM::VSELEQS: 4490 case ARM::VSELGEH: 4491 case ARM::VSELGES: 4492 case ARM::VSELGTH: 4493 case ARM::VSELGTS: 4494 case ARM::VSELVSH: 4495 case ARM::VSELVSS: { 4496 // op: Sd 4497 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4498 Value |= (op & UINT64_C(1)) << 22; 4499 Value |= (op & UINT64_C(30)) << 11; 4500 // op: Sn 4501 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4502 Value |= (op & UINT64_C(30)) << 15; 4503 Value |= (op & UINT64_C(1)) << 7; 4504 // op: Sm 4505 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4506 Value |= (op & UINT64_C(1)) << 5; 4507 Value |= (op & UINT64_C(30)) >> 1; 4508 break; 4509 } 4510 case ARM::VDUP16d: 4511 case ARM::VDUP16q: 4512 case ARM::VDUP32d: 4513 case ARM::VDUP32q: 4514 case ARM::VDUP8d: 4515 case ARM::VDUP8q: { 4516 // op: V 4517 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4518 Value |= (op & UINT64_C(15)) << 16; 4519 Value |= (op & UINT64_C(16)) << 3; 4520 // op: R 4521 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4522 Value |= (op & UINT64_C(15)) << 12; 4523 // op: p 4524 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4525 Value |= (op & UINT64_C(15)) << 28; 4526 Value = NEONThumb2DupPostEncoder(MI, Value, STI); 4527 break; 4528 } 4529 case ARM::VSETLNi32: { 4530 // op: V 4531 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4532 Value |= (op & UINT64_C(15)) << 16; 4533 Value |= (op & UINT64_C(16)) << 3; 4534 // op: R 4535 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4536 Value |= (op & UINT64_C(15)) << 12; 4537 // op: p 4538 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 4539 Value |= (op & UINT64_C(15)) << 28; 4540 // op: lane 4541 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4542 Value |= (op & UINT64_C(1)) << 21; 4543 Value = NEONThumb2DupPostEncoder(MI, Value, STI); 4544 break; 4545 } 4546 case ARM::VSETLNi16: { 4547 // op: V 4548 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4549 Value |= (op & UINT64_C(15)) << 16; 4550 Value |= (op & UINT64_C(16)) << 3; 4551 // op: R 4552 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4553 Value |= (op & UINT64_C(15)) << 12; 4554 // op: p 4555 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 4556 Value |= (op & UINT64_C(15)) << 28; 4557 // op: lane 4558 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4559 Value |= (op & UINT64_C(2)) << 20; 4560 Value |= (op & UINT64_C(1)) << 6; 4561 Value = NEONThumb2DupPostEncoder(MI, Value, STI); 4562 break; 4563 } 4564 case ARM::VSETLNi8: { 4565 // op: V 4566 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4567 Value |= (op & UINT64_C(15)) << 16; 4568 Value |= (op & UINT64_C(16)) << 3; 4569 // op: R 4570 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4571 Value |= (op & UINT64_C(15)) << 12; 4572 // op: p 4573 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 4574 Value |= (op & UINT64_C(15)) << 28; 4575 // op: lane 4576 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4577 Value |= (op & UINT64_C(4)) << 19; 4578 Value |= (op & UINT64_C(3)) << 5; 4579 Value = NEONThumb2DupPostEncoder(MI, Value, STI); 4580 break; 4581 } 4582 case ARM::VGETLNi32: { 4583 // op: V 4584 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4585 Value |= (op & UINT64_C(15)) << 16; 4586 Value |= (op & UINT64_C(16)) << 3; 4587 // op: R 4588 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4589 Value |= (op & UINT64_C(15)) << 12; 4590 // op: p 4591 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4592 Value |= (op & UINT64_C(15)) << 28; 4593 // op: lane 4594 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4595 Value |= (op & UINT64_C(1)) << 21; 4596 Value = NEONThumb2DupPostEncoder(MI, Value, STI); 4597 break; 4598 } 4599 case ARM::VGETLNs16: 4600 case ARM::VGETLNu16: { 4601 // op: V 4602 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4603 Value |= (op & UINT64_C(15)) << 16; 4604 Value |= (op & UINT64_C(16)) << 3; 4605 // op: R 4606 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4607 Value |= (op & UINT64_C(15)) << 12; 4608 // op: p 4609 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4610 Value |= (op & UINT64_C(15)) << 28; 4611 // op: lane 4612 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4613 Value |= (op & UINT64_C(2)) << 20; 4614 Value |= (op & UINT64_C(1)) << 6; 4615 Value = NEONThumb2DupPostEncoder(MI, Value, STI); 4616 break; 4617 } 4618 case ARM::VGETLNs8: 4619 case ARM::VGETLNu8: { 4620 // op: V 4621 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4622 Value |= (op & UINT64_C(15)) << 16; 4623 Value |= (op & UINT64_C(16)) << 3; 4624 // op: R 4625 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4626 Value |= (op & UINT64_C(15)) << 12; 4627 // op: p 4628 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4629 Value |= (op & UINT64_C(15)) << 28; 4630 // op: lane 4631 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4632 Value |= (op & UINT64_C(4)) << 19; 4633 Value |= (op & UINT64_C(3)) << 5; 4634 Value = NEONThumb2DupPostEncoder(MI, Value, STI); 4635 break; 4636 } 4637 case ARM::VLD1LNd8: { 4638 // op: Vd 4639 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4640 Value |= (op & UINT64_C(16)) << 18; 4641 Value |= (op & UINT64_C(15)) << 12; 4642 // op: Rn 4643 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 4644 Value |= (op & UINT64_C(15)) << 16; 4645 // op: lane 4646 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 4647 Value |= (op & UINT64_C(7)) << 5; 4648 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4649 break; 4650 } 4651 case ARM::VLD1d16: 4652 case ARM::VLD1d16T: 4653 case ARM::VLD1d32: 4654 case ARM::VLD1d32T: 4655 case ARM::VLD1d64: 4656 case ARM::VLD1d64T: 4657 case ARM::VLD1d8: 4658 case ARM::VLD1d8T: { 4659 // op: Vd 4660 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4661 Value |= (op & UINT64_C(16)) << 18; 4662 Value |= (op & UINT64_C(15)) << 12; 4663 // op: Rn 4664 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 4665 Value |= (op & UINT64_C(15)) << 16; 4666 Value |= op & UINT64_C(16); 4667 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4668 break; 4669 } 4670 case ARM::VLD1LNd16: { 4671 // op: Vd 4672 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4673 Value |= (op & UINT64_C(16)) << 18; 4674 Value |= (op & UINT64_C(15)) << 12; 4675 // op: Rn 4676 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 4677 Value |= (op & UINT64_C(15)) << 16; 4678 Value |= op & UINT64_C(48); 4679 // op: lane 4680 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 4681 Value |= (op & UINT64_C(3)) << 6; 4682 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4683 break; 4684 } 4685 case ARM::VLD1d16Q: 4686 case ARM::VLD1d32Q: 4687 case ARM::VLD1d64Q: 4688 case ARM::VLD1d8Q: 4689 case ARM::VLD1q16: 4690 case ARM::VLD1q32: 4691 case ARM::VLD1q64: 4692 case ARM::VLD1q8: 4693 case ARM::VLD2b16: 4694 case ARM::VLD2b32: 4695 case ARM::VLD2b8: 4696 case ARM::VLD2d16: 4697 case ARM::VLD2d32: 4698 case ARM::VLD2d8: 4699 case ARM::VLD2q16: 4700 case ARM::VLD2q32: 4701 case ARM::VLD2q8: { 4702 // op: Vd 4703 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4704 Value |= (op & UINT64_C(16)) << 18; 4705 Value |= (op & UINT64_C(15)) << 12; 4706 // op: Rn 4707 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 4708 Value |= (op & UINT64_C(15)) << 16; 4709 Value |= op & UINT64_C(48); 4710 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4711 break; 4712 } 4713 case ARM::VLD1LNd8_UPD: { 4714 // op: Vd 4715 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4716 Value |= (op & UINT64_C(16)) << 18; 4717 Value |= (op & UINT64_C(15)) << 12; 4718 // op: Rn 4719 op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 4720 Value |= (op & UINT64_C(15)) << 16; 4721 // op: Rm 4722 op = getAddrMode6OffsetOpValue(MI, 4, Fixups, STI); 4723 Value |= op & UINT64_C(15); 4724 // op: lane 4725 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 4726 Value |= (op & UINT64_C(7)) << 5; 4727 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4728 break; 4729 } 4730 case ARM::VLD1LNd32_UPD: { 4731 // op: Vd 4732 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4733 Value |= (op & UINT64_C(16)) << 18; 4734 Value |= (op & UINT64_C(15)) << 12; 4735 // op: Rn 4736 op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 4737 Value |= (op & UINT64_C(15)) << 16; 4738 Value |= (op & UINT64_C(16)) << 1; 4739 Value |= op & UINT64_C(16); 4740 // op: Rm 4741 op = getAddrMode6OffsetOpValue(MI, 4, Fixups, STI); 4742 Value |= op & UINT64_C(15); 4743 // op: lane 4744 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 4745 Value |= (op & UINT64_C(1)) << 7; 4746 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4747 break; 4748 } 4749 case ARM::VLD1LNd16_UPD: { 4750 // op: Vd 4751 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4752 Value |= (op & UINT64_C(16)) << 18; 4753 Value |= (op & UINT64_C(15)) << 12; 4754 // op: Rn 4755 op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 4756 Value |= (op & UINT64_C(15)) << 16; 4757 Value |= op & UINT64_C(16); 4758 // op: Rm 4759 op = getAddrMode6OffsetOpValue(MI, 4, Fixups, STI); 4760 Value |= op & UINT64_C(15); 4761 // op: lane 4762 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 4763 Value |= (op & UINT64_C(3)) << 6; 4764 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4765 break; 4766 } 4767 case ARM::VLD1d16Twb_register: 4768 case ARM::VLD1d16wb_register: 4769 case ARM::VLD1d32Twb_register: 4770 case ARM::VLD1d32wb_register: 4771 case ARM::VLD1d64Twb_register: 4772 case ARM::VLD1d64wb_register: 4773 case ARM::VLD1d8Twb_register: 4774 case ARM::VLD1d8wb_register: { 4775 // op: Vd 4776 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4777 Value |= (op & UINT64_C(16)) << 18; 4778 Value |= (op & UINT64_C(15)) << 12; 4779 // op: Rn 4780 op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 4781 Value |= (op & UINT64_C(15)) << 16; 4782 Value |= op & UINT64_C(16); 4783 // op: Rm 4784 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 4785 Value |= op & UINT64_C(15); 4786 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4787 break; 4788 } 4789 case ARM::VLD2LNd32: 4790 case ARM::VLD2LNq32: { 4791 // op: Vd 4792 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4793 Value |= (op & UINT64_C(16)) << 18; 4794 Value |= (op & UINT64_C(15)) << 12; 4795 // op: Rn 4796 op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 4797 Value |= (op & UINT64_C(15)) << 16; 4798 Value |= op & UINT64_C(16); 4799 // op: lane 4800 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 4801 Value |= (op & UINT64_C(1)) << 7; 4802 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4803 break; 4804 } 4805 case ARM::VLD2LNd16: 4806 case ARM::VLD2LNq16: { 4807 // op: Vd 4808 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4809 Value |= (op & UINT64_C(16)) << 18; 4810 Value |= (op & UINT64_C(15)) << 12; 4811 // op: Rn 4812 op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 4813 Value |= (op & UINT64_C(15)) << 16; 4814 Value |= op & UINT64_C(16); 4815 // op: lane 4816 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 4817 Value |= (op & UINT64_C(3)) << 6; 4818 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4819 break; 4820 } 4821 case ARM::VLD2LNd8: { 4822 // op: Vd 4823 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4824 Value |= (op & UINT64_C(16)) << 18; 4825 Value |= (op & UINT64_C(15)) << 12; 4826 // op: Rn 4827 op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 4828 Value |= (op & UINT64_C(15)) << 16; 4829 Value |= op & UINT64_C(16); 4830 // op: lane 4831 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 4832 Value |= (op & UINT64_C(7)) << 5; 4833 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4834 break; 4835 } 4836 case ARM::VLD1d16Twb_fixed: 4837 case ARM::VLD1d16wb_fixed: 4838 case ARM::VLD1d32Twb_fixed: 4839 case ARM::VLD1d32wb_fixed: 4840 case ARM::VLD1d64Twb_fixed: 4841 case ARM::VLD1d64wb_fixed: 4842 case ARM::VLD1d8Twb_fixed: 4843 case ARM::VLD1d8wb_fixed: { 4844 // op: Vd 4845 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4846 Value |= (op & UINT64_C(16)) << 18; 4847 Value |= (op & UINT64_C(15)) << 12; 4848 // op: Rn 4849 op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 4850 Value |= (op & UINT64_C(15)) << 16; 4851 Value |= op & UINT64_C(16); 4852 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4853 break; 4854 } 4855 case ARM::VLD1d16Qwb_register: 4856 case ARM::VLD1d32Qwb_register: 4857 case ARM::VLD1d64Qwb_register: 4858 case ARM::VLD1d8Qwb_register: 4859 case ARM::VLD1q16wb_register: 4860 case ARM::VLD1q32wb_register: 4861 case ARM::VLD1q64wb_register: 4862 case ARM::VLD1q8wb_register: 4863 case ARM::VLD2b16wb_register: 4864 case ARM::VLD2b32wb_register: 4865 case ARM::VLD2b8wb_register: 4866 case ARM::VLD2d16wb_register: 4867 case ARM::VLD2d32wb_register: 4868 case ARM::VLD2d8wb_register: 4869 case ARM::VLD2q16wb_register: 4870 case ARM::VLD2q32wb_register: 4871 case ARM::VLD2q8wb_register: { 4872 // op: Vd 4873 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4874 Value |= (op & UINT64_C(16)) << 18; 4875 Value |= (op & UINT64_C(15)) << 12; 4876 // op: Rn 4877 op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 4878 Value |= (op & UINT64_C(15)) << 16; 4879 Value |= op & UINT64_C(48); 4880 // op: Rm 4881 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 4882 Value |= op & UINT64_C(15); 4883 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4884 break; 4885 } 4886 case ARM::VLD1d16Qwb_fixed: 4887 case ARM::VLD1d32Qwb_fixed: 4888 case ARM::VLD1d64Qwb_fixed: 4889 case ARM::VLD1d8Qwb_fixed: 4890 case ARM::VLD1q16wb_fixed: 4891 case ARM::VLD1q32wb_fixed: 4892 case ARM::VLD1q64wb_fixed: 4893 case ARM::VLD1q8wb_fixed: 4894 case ARM::VLD2b16wb_fixed: 4895 case ARM::VLD2b32wb_fixed: 4896 case ARM::VLD2b8wb_fixed: 4897 case ARM::VLD2d16wb_fixed: 4898 case ARM::VLD2d32wb_fixed: 4899 case ARM::VLD2d8wb_fixed: 4900 case ARM::VLD2q16wb_fixed: 4901 case ARM::VLD2q32wb_fixed: 4902 case ARM::VLD2q8wb_fixed: { 4903 // op: Vd 4904 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4905 Value |= (op & UINT64_C(16)) << 18; 4906 Value |= (op & UINT64_C(15)) << 12; 4907 // op: Rn 4908 op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 4909 Value |= (op & UINT64_C(15)) << 16; 4910 Value |= op & UINT64_C(48); 4911 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4912 break; 4913 } 4914 case ARM::VLD3LNd32: 4915 case ARM::VLD3LNq32: { 4916 // op: Vd 4917 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4918 Value |= (op & UINT64_C(16)) << 18; 4919 Value |= (op & UINT64_C(15)) << 12; 4920 // op: Rn 4921 op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI); 4922 Value |= (op & UINT64_C(15)) << 16; 4923 // op: lane 4924 op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 4925 Value |= (op & UINT64_C(1)) << 7; 4926 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4927 break; 4928 } 4929 case ARM::VLD3LNd16: 4930 case ARM::VLD3LNq16: { 4931 // op: Vd 4932 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4933 Value |= (op & UINT64_C(16)) << 18; 4934 Value |= (op & UINT64_C(15)) << 12; 4935 // op: Rn 4936 op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI); 4937 Value |= (op & UINT64_C(15)) << 16; 4938 // op: lane 4939 op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 4940 Value |= (op & UINT64_C(3)) << 6; 4941 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4942 break; 4943 } 4944 case ARM::VLD3LNd8: { 4945 // op: Vd 4946 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4947 Value |= (op & UINT64_C(16)) << 18; 4948 Value |= (op & UINT64_C(15)) << 12; 4949 // op: Rn 4950 op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI); 4951 Value |= (op & UINT64_C(15)) << 16; 4952 // op: lane 4953 op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 4954 Value |= (op & UINT64_C(7)) << 5; 4955 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4956 break; 4957 } 4958 case ARM::VLD2LNd32_UPD: 4959 case ARM::VLD2LNq32_UPD: { 4960 // op: Vd 4961 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4962 Value |= (op & UINT64_C(16)) << 18; 4963 Value |= (op & UINT64_C(15)) << 12; 4964 // op: Rn 4965 op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI); 4966 Value |= (op & UINT64_C(15)) << 16; 4967 Value |= op & UINT64_C(16); 4968 // op: Rm 4969 op = getAddrMode6OffsetOpValue(MI, 5, Fixups, STI); 4970 Value |= op & UINT64_C(15); 4971 // op: lane 4972 op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 4973 Value |= (op & UINT64_C(1)) << 7; 4974 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4975 break; 4976 } 4977 case ARM::VLD2LNd16_UPD: 4978 case ARM::VLD2LNq16_UPD: { 4979 // op: Vd 4980 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4981 Value |= (op & UINT64_C(16)) << 18; 4982 Value |= (op & UINT64_C(15)) << 12; 4983 // op: Rn 4984 op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI); 4985 Value |= (op & UINT64_C(15)) << 16; 4986 Value |= op & UINT64_C(16); 4987 // op: Rm 4988 op = getAddrMode6OffsetOpValue(MI, 5, Fixups, STI); 4989 Value |= op & UINT64_C(15); 4990 // op: lane 4991 op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 4992 Value |= (op & UINT64_C(3)) << 6; 4993 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4994 break; 4995 } 4996 case ARM::VLD2LNd8_UPD: { 4997 // op: Vd 4998 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4999 Value |= (op & UINT64_C(16)) << 18; 5000 Value |= (op & UINT64_C(15)) << 12; 5001 // op: Rn 5002 op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI); 5003 Value |= (op & UINT64_C(15)) << 16; 5004 Value |= op & UINT64_C(16); 5005 // op: Rm 5006 op = getAddrMode6OffsetOpValue(MI, 5, Fixups, STI); 5007 Value |= op & UINT64_C(15); 5008 // op: lane 5009 op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 5010 Value |= (op & UINT64_C(7)) << 5; 5011 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5012 break; 5013 } 5014 case ARM::VLD3d16: 5015 case ARM::VLD3d32: 5016 case ARM::VLD3d8: 5017 case ARM::VLD3q16: 5018 case ARM::VLD3q32: 5019 case ARM::VLD3q8: { 5020 // op: Vd 5021 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5022 Value |= (op & UINT64_C(16)) << 18; 5023 Value |= (op & UINT64_C(15)) << 12; 5024 // op: Rn 5025 op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI); 5026 Value |= (op & UINT64_C(15)) << 16; 5027 Value |= op & UINT64_C(16); 5028 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5029 break; 5030 } 5031 case ARM::VLD3LNd32_UPD: 5032 case ARM::VLD3LNq32_UPD: { 5033 // op: Vd 5034 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5035 Value |= (op & UINT64_C(16)) << 18; 5036 Value |= (op & UINT64_C(15)) << 12; 5037 // op: Rn 5038 op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI); 5039 Value |= (op & UINT64_C(15)) << 16; 5040 // op: Rm 5041 op = getAddrMode6OffsetOpValue(MI, 6, Fixups, STI); 5042 Value |= op & UINT64_C(15); 5043 // op: lane 5044 op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI); 5045 Value |= (op & UINT64_C(1)) << 7; 5046 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5047 break; 5048 } 5049 case ARM::VLD3LNd16_UPD: 5050 case ARM::VLD3LNq16_UPD: { 5051 // op: Vd 5052 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5053 Value |= (op & UINT64_C(16)) << 18; 5054 Value |= (op & UINT64_C(15)) << 12; 5055 // op: Rn 5056 op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI); 5057 Value |= (op & UINT64_C(15)) << 16; 5058 // op: Rm 5059 op = getAddrMode6OffsetOpValue(MI, 6, Fixups, STI); 5060 Value |= op & UINT64_C(15); 5061 // op: lane 5062 op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI); 5063 Value |= (op & UINT64_C(3)) << 6; 5064 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5065 break; 5066 } 5067 case ARM::VLD3LNd8_UPD: { 5068 // op: Vd 5069 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5070 Value |= (op & UINT64_C(16)) << 18; 5071 Value |= (op & UINT64_C(15)) << 12; 5072 // op: Rn 5073 op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI); 5074 Value |= (op & UINT64_C(15)) << 16; 5075 // op: Rm 5076 op = getAddrMode6OffsetOpValue(MI, 6, Fixups, STI); 5077 Value |= op & UINT64_C(15); 5078 // op: lane 5079 op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI); 5080 Value |= (op & UINT64_C(7)) << 5; 5081 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5082 break; 5083 } 5084 case ARM::VLD3d16_UPD: 5085 case ARM::VLD3d32_UPD: 5086 case ARM::VLD3d8_UPD: 5087 case ARM::VLD3q16_UPD: 5088 case ARM::VLD3q32_UPD: 5089 case ARM::VLD3q8_UPD: { 5090 // op: Vd 5091 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5092 Value |= (op & UINT64_C(16)) << 18; 5093 Value |= (op & UINT64_C(15)) << 12; 5094 // op: Rn 5095 op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI); 5096 Value |= (op & UINT64_C(15)) << 16; 5097 Value |= op & UINT64_C(16); 5098 // op: Rm 5099 op = getAddrMode6OffsetOpValue(MI, 6, Fixups, STI); 5100 Value |= op & UINT64_C(15); 5101 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5102 break; 5103 } 5104 case ARM::VLD4LNd16: 5105 case ARM::VLD4LNq16: { 5106 // op: Vd 5107 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5108 Value |= (op & UINT64_C(16)) << 18; 5109 Value |= (op & UINT64_C(15)) << 12; 5110 // op: Rn 5111 op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI); 5112 Value |= (op & UINT64_C(15)) << 16; 5113 Value |= op & UINT64_C(16); 5114 // op: lane 5115 op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI); 5116 Value |= (op & UINT64_C(3)) << 6; 5117 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5118 break; 5119 } 5120 case ARM::VLD4LNd8: { 5121 // op: Vd 5122 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5123 Value |= (op & UINT64_C(16)) << 18; 5124 Value |= (op & UINT64_C(15)) << 12; 5125 // op: Rn 5126 op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI); 5127 Value |= (op & UINT64_C(15)) << 16; 5128 Value |= op & UINT64_C(16); 5129 // op: lane 5130 op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI); 5131 Value |= (op & UINT64_C(7)) << 5; 5132 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5133 break; 5134 } 5135 case ARM::VLD4LNd32: 5136 case ARM::VLD4LNq32: { 5137 // op: Vd 5138 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5139 Value |= (op & UINT64_C(16)) << 18; 5140 Value |= (op & UINT64_C(15)) << 12; 5141 // op: Rn 5142 op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI); 5143 Value |= (op & UINT64_C(15)) << 16; 5144 Value |= op & UINT64_C(48); 5145 // op: lane 5146 op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI); 5147 Value |= (op & UINT64_C(1)) << 7; 5148 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5149 break; 5150 } 5151 case ARM::VLD4d16: 5152 case ARM::VLD4d32: 5153 case ARM::VLD4d8: 5154 case ARM::VLD4q16: 5155 case ARM::VLD4q32: 5156 case ARM::VLD4q8: { 5157 // op: Vd 5158 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5159 Value |= (op & UINT64_C(16)) << 18; 5160 Value |= (op & UINT64_C(15)) << 12; 5161 // op: Rn 5162 op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI); 5163 Value |= (op & UINT64_C(15)) << 16; 5164 Value |= op & UINT64_C(48); 5165 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5166 break; 5167 } 5168 case ARM::VLD4LNd16_UPD: 5169 case ARM::VLD4LNq16_UPD: { 5170 // op: Vd 5171 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5172 Value |= (op & UINT64_C(16)) << 18; 5173 Value |= (op & UINT64_C(15)) << 12; 5174 // op: Rn 5175 op = getAddrMode6AddressOpValue(MI, 5, Fixups, STI); 5176 Value |= (op & UINT64_C(15)) << 16; 5177 Value |= op & UINT64_C(16); 5178 // op: Rm 5179 op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI); 5180 Value |= op & UINT64_C(15); 5181 // op: lane 5182 op = getMachineOpValue(MI, MI.getOperand(12), Fixups, STI); 5183 Value |= (op & UINT64_C(3)) << 6; 5184 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5185 break; 5186 } 5187 case ARM::VLD4LNd8_UPD: { 5188 // op: Vd 5189 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5190 Value |= (op & UINT64_C(16)) << 18; 5191 Value |= (op & UINT64_C(15)) << 12; 5192 // op: Rn 5193 op = getAddrMode6AddressOpValue(MI, 5, Fixups, STI); 5194 Value |= (op & UINT64_C(15)) << 16; 5195 Value |= op & UINT64_C(16); 5196 // op: Rm 5197 op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI); 5198 Value |= op & UINT64_C(15); 5199 // op: lane 5200 op = getMachineOpValue(MI, MI.getOperand(12), Fixups, STI); 5201 Value |= (op & UINT64_C(7)) << 5; 5202 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5203 break; 5204 } 5205 case ARM::VLD4LNd32_UPD: 5206 case ARM::VLD4LNq32_UPD: { 5207 // op: Vd 5208 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5209 Value |= (op & UINT64_C(16)) << 18; 5210 Value |= (op & UINT64_C(15)) << 12; 5211 // op: Rn 5212 op = getAddrMode6AddressOpValue(MI, 5, Fixups, STI); 5213 Value |= (op & UINT64_C(15)) << 16; 5214 Value |= op & UINT64_C(48); 5215 // op: Rm 5216 op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI); 5217 Value |= op & UINT64_C(15); 5218 // op: lane 5219 op = getMachineOpValue(MI, MI.getOperand(12), Fixups, STI); 5220 Value |= (op & UINT64_C(1)) << 7; 5221 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5222 break; 5223 } 5224 case ARM::VLD4d16_UPD: 5225 case ARM::VLD4d32_UPD: 5226 case ARM::VLD4d8_UPD: 5227 case ARM::VLD4q16_UPD: 5228 case ARM::VLD4q32_UPD: 5229 case ARM::VLD4q8_UPD: { 5230 // op: Vd 5231 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5232 Value |= (op & UINT64_C(16)) << 18; 5233 Value |= (op & UINT64_C(15)) << 12; 5234 // op: Rn 5235 op = getAddrMode6AddressOpValue(MI, 5, Fixups, STI); 5236 Value |= (op & UINT64_C(15)) << 16; 5237 Value |= op & UINT64_C(48); 5238 // op: Rm 5239 op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI); 5240 Value |= op & UINT64_C(15); 5241 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5242 break; 5243 } 5244 case ARM::VLD1DUPd16: 5245 case ARM::VLD1DUPd32: 5246 case ARM::VLD1DUPd8: 5247 case ARM::VLD1DUPq16: 5248 case ARM::VLD1DUPq32: 5249 case ARM::VLD1DUPq8: 5250 case ARM::VLD2DUPd16: 5251 case ARM::VLD2DUPd16x2: 5252 case ARM::VLD2DUPd32: 5253 case ARM::VLD2DUPd32x2: 5254 case ARM::VLD2DUPd8: 5255 case ARM::VLD2DUPd8x2: { 5256 // op: Vd 5257 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5258 Value |= (op & UINT64_C(16)) << 18; 5259 Value |= (op & UINT64_C(15)) << 12; 5260 // op: Rn 5261 op = getAddrMode6DupAddressOpValue(MI, 1, Fixups, STI); 5262 Value |= (op & UINT64_C(15)) << 16; 5263 Value |= op & UINT64_C(16); 5264 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5265 break; 5266 } 5267 case ARM::VLD1DUPd16wb_register: 5268 case ARM::VLD1DUPd32wb_register: 5269 case ARM::VLD1DUPd8wb_register: 5270 case ARM::VLD1DUPq16wb_register: 5271 case ARM::VLD1DUPq32wb_register: 5272 case ARM::VLD1DUPq8wb_register: 5273 case ARM::VLD2DUPd16wb_register: 5274 case ARM::VLD2DUPd16x2wb_register: 5275 case ARM::VLD2DUPd32wb_register: 5276 case ARM::VLD2DUPd32x2wb_register: 5277 case ARM::VLD2DUPd8wb_register: 5278 case ARM::VLD2DUPd8x2wb_register: { 5279 // op: Vd 5280 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5281 Value |= (op & UINT64_C(16)) << 18; 5282 Value |= (op & UINT64_C(15)) << 12; 5283 // op: Rn 5284 op = getAddrMode6DupAddressOpValue(MI, 2, Fixups, STI); 5285 Value |= (op & UINT64_C(15)) << 16; 5286 Value |= op & UINT64_C(16); 5287 // op: Rm 5288 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 5289 Value |= op & UINT64_C(15); 5290 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5291 break; 5292 } 5293 case ARM::VLD1DUPd16wb_fixed: 5294 case ARM::VLD1DUPd32wb_fixed: 5295 case ARM::VLD1DUPd8wb_fixed: 5296 case ARM::VLD1DUPq16wb_fixed: 5297 case ARM::VLD1DUPq32wb_fixed: 5298 case ARM::VLD1DUPq8wb_fixed: 5299 case ARM::VLD2DUPd16wb_fixed: 5300 case ARM::VLD2DUPd16x2wb_fixed: 5301 case ARM::VLD2DUPd32wb_fixed: 5302 case ARM::VLD2DUPd32x2wb_fixed: 5303 case ARM::VLD2DUPd8wb_fixed: 5304 case ARM::VLD2DUPd8x2wb_fixed: { 5305 // op: Vd 5306 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5307 Value |= (op & UINT64_C(16)) << 18; 5308 Value |= (op & UINT64_C(15)) << 12; 5309 // op: Rn 5310 op = getAddrMode6DupAddressOpValue(MI, 2, Fixups, STI); 5311 Value |= (op & UINT64_C(15)) << 16; 5312 Value |= op & UINT64_C(16); 5313 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5314 break; 5315 } 5316 case ARM::VLD3DUPd16: 5317 case ARM::VLD3DUPd32: 5318 case ARM::VLD3DUPd8: 5319 case ARM::VLD3DUPq16: 5320 case ARM::VLD3DUPq32: 5321 case ARM::VLD3DUPq8: { 5322 // op: Vd 5323 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5324 Value |= (op & UINT64_C(16)) << 18; 5325 Value |= (op & UINT64_C(15)) << 12; 5326 // op: Rn 5327 op = getAddrMode6DupAddressOpValue(MI, 3, Fixups, STI); 5328 Value |= (op & UINT64_C(15)) << 16; 5329 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5330 break; 5331 } 5332 case ARM::VLD3DUPd16_UPD: 5333 case ARM::VLD3DUPd32_UPD: 5334 case ARM::VLD3DUPd8_UPD: 5335 case ARM::VLD3DUPq16_UPD: 5336 case ARM::VLD3DUPq32_UPD: 5337 case ARM::VLD3DUPq8_UPD: { 5338 // op: Vd 5339 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5340 Value |= (op & UINT64_C(16)) << 18; 5341 Value |= (op & UINT64_C(15)) << 12; 5342 // op: Rn 5343 op = getAddrMode6DupAddressOpValue(MI, 4, Fixups, STI); 5344 Value |= (op & UINT64_C(15)) << 16; 5345 // op: Rm 5346 op = getAddrMode6OffsetOpValue(MI, 6, Fixups, STI); 5347 Value |= op & UINT64_C(15); 5348 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5349 break; 5350 } 5351 case ARM::VLD4DUPd32: 5352 case ARM::VLD4DUPq32: { 5353 // op: Vd 5354 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5355 Value |= (op & UINT64_C(16)) << 18; 5356 Value |= (op & UINT64_C(15)) << 12; 5357 // op: Rn 5358 op = getAddrMode6DupAddressOpValue(MI, 4, Fixups, STI); 5359 Value |= (op & UINT64_C(15)) << 16; 5360 Value |= (op & UINT64_C(32)) << 1; 5361 Value |= op & UINT64_C(16); 5362 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5363 break; 5364 } 5365 case ARM::VLD4DUPd16: 5366 case ARM::VLD4DUPd8: 5367 case ARM::VLD4DUPq16: 5368 case ARM::VLD4DUPq8: { 5369 // op: Vd 5370 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5371 Value |= (op & UINT64_C(16)) << 18; 5372 Value |= (op & UINT64_C(15)) << 12; 5373 // op: Rn 5374 op = getAddrMode6DupAddressOpValue(MI, 4, Fixups, STI); 5375 Value |= (op & UINT64_C(15)) << 16; 5376 Value |= op & UINT64_C(16); 5377 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5378 break; 5379 } 5380 case ARM::VLD4DUPd32_UPD: 5381 case ARM::VLD4DUPq32_UPD: { 5382 // op: Vd 5383 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5384 Value |= (op & UINT64_C(16)) << 18; 5385 Value |= (op & UINT64_C(15)) << 12; 5386 // op: Rn 5387 op = getAddrMode6DupAddressOpValue(MI, 5, Fixups, STI); 5388 Value |= (op & UINT64_C(15)) << 16; 5389 Value |= (op & UINT64_C(32)) << 1; 5390 Value |= op & UINT64_C(16); 5391 // op: Rm 5392 op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI); 5393 Value |= op & UINT64_C(15); 5394 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5395 break; 5396 } 5397 case ARM::VLD4DUPd16_UPD: 5398 case ARM::VLD4DUPd8_UPD: 5399 case ARM::VLD4DUPq16_UPD: 5400 case ARM::VLD4DUPq8_UPD: { 5401 // op: Vd 5402 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5403 Value |= (op & UINT64_C(16)) << 18; 5404 Value |= (op & UINT64_C(15)) << 12; 5405 // op: Rn 5406 op = getAddrMode6DupAddressOpValue(MI, 5, Fixups, STI); 5407 Value |= (op & UINT64_C(15)) << 16; 5408 Value |= op & UINT64_C(16); 5409 // op: Rm 5410 op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI); 5411 Value |= op & UINT64_C(15); 5412 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5413 break; 5414 } 5415 case ARM::VLD1LNd32: { 5416 // op: Vd 5417 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5418 Value |= (op & UINT64_C(16)) << 18; 5419 Value |= (op & UINT64_C(15)) << 12; 5420 // op: Rn 5421 op = getAddrMode6OneLane32AddressOpValue(MI, 1, Fixups, STI); 5422 Value |= (op & UINT64_C(15)) << 16; 5423 Value |= op & UINT64_C(48); 5424 // op: lane 5425 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 5426 Value |= (op & UINT64_C(1)) << 7; 5427 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5428 break; 5429 } 5430 case ARM::VMOVv16i8: 5431 case ARM::VMOVv1i64: 5432 case ARM::VMOVv2f32: 5433 case ARM::VMOVv2i64: 5434 case ARM::VMOVv4f32: 5435 case ARM::VMOVv8i8: { 5436 // op: Vd 5437 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5438 Value |= (op & UINT64_C(16)) << 18; 5439 Value |= (op & UINT64_C(15)) << 12; 5440 // op: SIMM 5441 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5442 Value |= (op & UINT64_C(128)) << 17; 5443 Value |= (op & UINT64_C(112)) << 12; 5444 Value |= op & UINT64_C(15); 5445 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5446 break; 5447 } 5448 case ARM::VBICiv2i32: 5449 case ARM::VBICiv4i32: 5450 case ARM::VORRiv2i32: 5451 case ARM::VORRiv4i32: { 5452 // op: Vd 5453 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5454 Value |= (op & UINT64_C(16)) << 18; 5455 Value |= (op & UINT64_C(15)) << 12; 5456 // op: SIMM 5457 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5458 Value |= (op & UINT64_C(128)) << 17; 5459 Value |= (op & UINT64_C(112)) << 12; 5460 Value |= op & UINT64_C(1536); 5461 Value |= op & UINT64_C(15); 5462 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5463 break; 5464 } 5465 case ARM::VMOVv2i32: 5466 case ARM::VMOVv4i32: 5467 case ARM::VMVNv2i32: 5468 case ARM::VMVNv4i32: { 5469 // op: Vd 5470 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5471 Value |= (op & UINT64_C(16)) << 18; 5472 Value |= (op & UINT64_C(15)) << 12; 5473 // op: SIMM 5474 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5475 Value |= (op & UINT64_C(128)) << 17; 5476 Value |= (op & UINT64_C(112)) << 12; 5477 Value |= op & UINT64_C(3840); 5478 Value |= op & UINT64_C(15); 5479 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5480 break; 5481 } 5482 case ARM::VBICiv4i16: 5483 case ARM::VBICiv8i16: 5484 case ARM::VMOVv4i16: 5485 case ARM::VMOVv8i16: 5486 case ARM::VMVNv4i16: 5487 case ARM::VMVNv8i16: 5488 case ARM::VORRiv4i16: 5489 case ARM::VORRiv8i16: { 5490 // op: Vd 5491 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5492 Value |= (op & UINT64_C(16)) << 18; 5493 Value |= (op & UINT64_C(15)) << 12; 5494 // op: SIMM 5495 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5496 Value |= (op & UINT64_C(128)) << 17; 5497 Value |= (op & UINT64_C(112)) << 12; 5498 Value |= op & UINT64_C(512); 5499 Value |= op & UINT64_C(15); 5500 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5501 break; 5502 } 5503 case ARM::VQSHLsiv4i16: 5504 case ARM::VQSHLsiv8i16: 5505 case ARM::VQSHLsuv4i16: 5506 case ARM::VQSHLsuv8i16: 5507 case ARM::VQSHLuiv4i16: 5508 case ARM::VQSHLuiv8i16: 5509 case ARM::VSHLLsv4i32: 5510 case ARM::VSHLLuv4i32: 5511 case ARM::VSHLiv4i16: 5512 case ARM::VSHLiv8i16: { 5513 // op: Vd 5514 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5515 Value |= (op & UINT64_C(16)) << 18; 5516 Value |= (op & UINT64_C(15)) << 12; 5517 // op: Vm 5518 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5519 Value |= (op & UINT64_C(16)) << 1; 5520 Value |= op & UINT64_C(15); 5521 // op: SIMM 5522 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5523 Value |= (op & UINT64_C(15)) << 16; 5524 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5525 break; 5526 } 5527 case ARM::VQSHLsiv2i32: 5528 case ARM::VQSHLsiv4i32: 5529 case ARM::VQSHLsuv2i32: 5530 case ARM::VQSHLsuv4i32: 5531 case ARM::VQSHLuiv2i32: 5532 case ARM::VQSHLuiv4i32: 5533 case ARM::VSHLLsv2i64: 5534 case ARM::VSHLLuv2i64: 5535 case ARM::VSHLiv2i32: 5536 case ARM::VSHLiv4i32: { 5537 // op: Vd 5538 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5539 Value |= (op & UINT64_C(16)) << 18; 5540 Value |= (op & UINT64_C(15)) << 12; 5541 // op: Vm 5542 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5543 Value |= (op & UINT64_C(16)) << 1; 5544 Value |= op & UINT64_C(15); 5545 // op: SIMM 5546 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5547 Value |= (op & UINT64_C(31)) << 16; 5548 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5549 break; 5550 } 5551 case ARM::VQSHLsiv1i64: 5552 case ARM::VQSHLsiv2i64: 5553 case ARM::VQSHLsuv1i64: 5554 case ARM::VQSHLsuv2i64: 5555 case ARM::VQSHLuiv1i64: 5556 case ARM::VQSHLuiv2i64: 5557 case ARM::VSHLiv1i64: 5558 case ARM::VSHLiv2i64: { 5559 // op: Vd 5560 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5561 Value |= (op & UINT64_C(16)) << 18; 5562 Value |= (op & UINT64_C(15)) << 12; 5563 // op: Vm 5564 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5565 Value |= (op & UINT64_C(16)) << 1; 5566 Value |= op & UINT64_C(15); 5567 // op: SIMM 5568 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5569 Value |= (op & UINT64_C(63)) << 16; 5570 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5571 break; 5572 } 5573 case ARM::VQSHLsiv16i8: 5574 case ARM::VQSHLsiv8i8: 5575 case ARM::VQSHLsuv16i8: 5576 case ARM::VQSHLsuv8i8: 5577 case ARM::VQSHLuiv16i8: 5578 case ARM::VQSHLuiv8i8: 5579 case ARM::VSHLLsv8i16: 5580 case ARM::VSHLLuv8i16: 5581 case ARM::VSHLiv16i8: 5582 case ARM::VSHLiv8i8: { 5583 // op: Vd 5584 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5585 Value |= (op & UINT64_C(16)) << 18; 5586 Value |= (op & UINT64_C(15)) << 12; 5587 // op: Vm 5588 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5589 Value |= (op & UINT64_C(16)) << 1; 5590 Value |= op & UINT64_C(15); 5591 // op: SIMM 5592 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5593 Value |= (op & UINT64_C(7)) << 16; 5594 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5595 break; 5596 } 5597 case ARM::VCVTf2xsd: 5598 case ARM::VCVTf2xsq: 5599 case ARM::VCVTf2xud: 5600 case ARM::VCVTf2xuq: 5601 case ARM::VCVTh2xsd: 5602 case ARM::VCVTh2xsq: 5603 case ARM::VCVTh2xud: 5604 case ARM::VCVTh2xuq: 5605 case ARM::VCVTxs2fd: 5606 case ARM::VCVTxs2fq: 5607 case ARM::VCVTxs2hd: 5608 case ARM::VCVTxs2hq: 5609 case ARM::VCVTxu2fd: 5610 case ARM::VCVTxu2fq: 5611 case ARM::VCVTxu2hd: 5612 case ARM::VCVTxu2hq: { 5613 // op: Vd 5614 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5615 Value |= (op & UINT64_C(16)) << 18; 5616 Value |= (op & UINT64_C(15)) << 12; 5617 // op: Vm 5618 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5619 Value |= (op & UINT64_C(16)) << 1; 5620 Value |= op & UINT64_C(15); 5621 // op: SIMM 5622 op = getNEONVcvtImm32OpValue(MI, 2, Fixups, STI); 5623 Value |= (op & UINT64_C(63)) << 16; 5624 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5625 break; 5626 } 5627 case ARM::VQRSHRNsv4i16: 5628 case ARM::VQRSHRNuv4i16: 5629 case ARM::VQRSHRUNv4i16: 5630 case ARM::VQSHRNsv4i16: 5631 case ARM::VQSHRNuv4i16: 5632 case ARM::VQSHRUNv4i16: 5633 case ARM::VRSHRNv4i16: 5634 case ARM::VRSHRsv4i16: 5635 case ARM::VRSHRsv8i16: 5636 case ARM::VRSHRuv4i16: 5637 case ARM::VRSHRuv8i16: 5638 case ARM::VSHRNv4i16: 5639 case ARM::VSHRsv4i16: 5640 case ARM::VSHRsv8i16: 5641 case ARM::VSHRuv4i16: 5642 case ARM::VSHRuv8i16: { 5643 // op: Vd 5644 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5645 Value |= (op & UINT64_C(16)) << 18; 5646 Value |= (op & UINT64_C(15)) << 12; 5647 // op: Vm 5648 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5649 Value |= (op & UINT64_C(16)) << 1; 5650 Value |= op & UINT64_C(15); 5651 // op: SIMM 5652 op = getShiftRight16Imm(MI, 2, Fixups, STI); 5653 Value |= (op & UINT64_C(15)) << 16; 5654 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5655 break; 5656 } 5657 case ARM::VQRSHRNsv2i32: 5658 case ARM::VQRSHRNuv2i32: 5659 case ARM::VQRSHRUNv2i32: 5660 case ARM::VQSHRNsv2i32: 5661 case ARM::VQSHRNuv2i32: 5662 case ARM::VQSHRUNv2i32: 5663 case ARM::VRSHRNv2i32: 5664 case ARM::VRSHRsv2i32: 5665 case ARM::VRSHRsv4i32: 5666 case ARM::VRSHRuv2i32: 5667 case ARM::VRSHRuv4i32: 5668 case ARM::VSHRNv2i32: 5669 case ARM::VSHRsv2i32: 5670 case ARM::VSHRsv4i32: 5671 case ARM::VSHRuv2i32: 5672 case ARM::VSHRuv4i32: { 5673 // op: Vd 5674 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5675 Value |= (op & UINT64_C(16)) << 18; 5676 Value |= (op & UINT64_C(15)) << 12; 5677 // op: Vm 5678 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5679 Value |= (op & UINT64_C(16)) << 1; 5680 Value |= op & UINT64_C(15); 5681 // op: SIMM 5682 op = getShiftRight32Imm(MI, 2, Fixups, STI); 5683 Value |= (op & UINT64_C(31)) << 16; 5684 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5685 break; 5686 } 5687 case ARM::VRSHRsv1i64: 5688 case ARM::VRSHRsv2i64: 5689 case ARM::VRSHRuv1i64: 5690 case ARM::VRSHRuv2i64: 5691 case ARM::VSHRsv1i64: 5692 case ARM::VSHRsv2i64: 5693 case ARM::VSHRuv1i64: 5694 case ARM::VSHRuv2i64: { 5695 // op: Vd 5696 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5697 Value |= (op & UINT64_C(16)) << 18; 5698 Value |= (op & UINT64_C(15)) << 12; 5699 // op: Vm 5700 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5701 Value |= (op & UINT64_C(16)) << 1; 5702 Value |= op & UINT64_C(15); 5703 // op: SIMM 5704 op = getShiftRight64Imm(MI, 2, Fixups, STI); 5705 Value |= (op & UINT64_C(63)) << 16; 5706 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5707 break; 5708 } 5709 case ARM::VQRSHRNsv8i8: 5710 case ARM::VQRSHRNuv8i8: 5711 case ARM::VQRSHRUNv8i8: 5712 case ARM::VQSHRNsv8i8: 5713 case ARM::VQSHRNuv8i8: 5714 case ARM::VQSHRUNv8i8: 5715 case ARM::VRSHRNv8i8: 5716 case ARM::VRSHRsv16i8: 5717 case ARM::VRSHRsv8i8: 5718 case ARM::VRSHRuv16i8: 5719 case ARM::VRSHRuv8i8: 5720 case ARM::VSHRNv8i8: 5721 case ARM::VSHRsv16i8: 5722 case ARM::VSHRsv8i8: 5723 case ARM::VSHRuv16i8: 5724 case ARM::VSHRuv8i8: { 5725 // op: Vd 5726 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5727 Value |= (op & UINT64_C(16)) << 18; 5728 Value |= (op & UINT64_C(15)) << 12; 5729 // op: Vm 5730 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5731 Value |= (op & UINT64_C(16)) << 1; 5732 Value |= op & UINT64_C(15); 5733 // op: SIMM 5734 op = getShiftRight8Imm(MI, 2, Fixups, STI); 5735 Value |= (op & UINT64_C(7)) << 16; 5736 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5737 break; 5738 } 5739 case ARM::VDUPLN32d: 5740 case ARM::VDUPLN32q: { 5741 // op: Vd 5742 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5743 Value |= (op & UINT64_C(16)) << 18; 5744 Value |= (op & UINT64_C(15)) << 12; 5745 // op: Vm 5746 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5747 Value |= (op & UINT64_C(16)) << 1; 5748 Value |= op & UINT64_C(15); 5749 // op: lane 5750 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5751 Value |= (op & UINT64_C(1)) << 19; 5752 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5753 break; 5754 } 5755 case ARM::VDUPLN16d: 5756 case ARM::VDUPLN16q: { 5757 // op: Vd 5758 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5759 Value |= (op & UINT64_C(16)) << 18; 5760 Value |= (op & UINT64_C(15)) << 12; 5761 // op: Vm 5762 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5763 Value |= (op & UINT64_C(16)) << 1; 5764 Value |= op & UINT64_C(15); 5765 // op: lane 5766 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5767 Value |= (op & UINT64_C(3)) << 18; 5768 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5769 break; 5770 } 5771 case ARM::VDUPLN8d: 5772 case ARM::VDUPLN8q: { 5773 // op: Vd 5774 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5775 Value |= (op & UINT64_C(16)) << 18; 5776 Value |= (op & UINT64_C(15)) << 12; 5777 // op: Vm 5778 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5779 Value |= (op & UINT64_C(16)) << 1; 5780 Value |= op & UINT64_C(15); 5781 // op: lane 5782 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5783 Value |= (op & UINT64_C(7)) << 17; 5784 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5785 break; 5786 } 5787 case ARM::AESIMC: 5788 case ARM::AESMC: 5789 case ARM::SHA1H: 5790 case ARM::VABSfd: 5791 case ARM::VABSfq: 5792 case ARM::VABShd: 5793 case ARM::VABShq: 5794 case ARM::VABSv16i8: 5795 case ARM::VABSv2i32: 5796 case ARM::VABSv4i16: 5797 case ARM::VABSv4i32: 5798 case ARM::VABSv8i16: 5799 case ARM::VABSv8i8: 5800 case ARM::VCEQzv16i8: 5801 case ARM::VCEQzv2f32: 5802 case ARM::VCEQzv2i32: 5803 case ARM::VCEQzv4f16: 5804 case ARM::VCEQzv4f32: 5805 case ARM::VCEQzv4i16: 5806 case ARM::VCEQzv4i32: 5807 case ARM::VCEQzv8f16: 5808 case ARM::VCEQzv8i16: 5809 case ARM::VCEQzv8i8: 5810 case ARM::VCGEzv16i8: 5811 case ARM::VCGEzv2f32: 5812 case ARM::VCGEzv2i32: 5813 case ARM::VCGEzv4f16: 5814 case ARM::VCGEzv4f32: 5815 case ARM::VCGEzv4i16: 5816 case ARM::VCGEzv4i32: 5817 case ARM::VCGEzv8f16: 5818 case ARM::VCGEzv8i16: 5819 case ARM::VCGEzv8i8: 5820 case ARM::VCGTzv16i8: 5821 case ARM::VCGTzv2f32: 5822 case ARM::VCGTzv2i32: 5823 case ARM::VCGTzv4f16: 5824 case ARM::VCGTzv4f32: 5825 case ARM::VCGTzv4i16: 5826 case ARM::VCGTzv4i32: 5827 case ARM::VCGTzv8f16: 5828 case ARM::VCGTzv8i16: 5829 case ARM::VCGTzv8i8: 5830 case ARM::VCLEzv16i8: 5831 case ARM::VCLEzv2f32: 5832 case ARM::VCLEzv2i32: 5833 case ARM::VCLEzv4f16: 5834 case ARM::VCLEzv4f32: 5835 case ARM::VCLEzv4i16: 5836 case ARM::VCLEzv4i32: 5837 case ARM::VCLEzv8f16: 5838 case ARM::VCLEzv8i16: 5839 case ARM::VCLEzv8i8: 5840 case ARM::VCLSv16i8: 5841 case ARM::VCLSv2i32: 5842 case ARM::VCLSv4i16: 5843 case ARM::VCLSv4i32: 5844 case ARM::VCLSv8i16: 5845 case ARM::VCLSv8i8: 5846 case ARM::VCLTzv16i8: 5847 case ARM::VCLTzv2f32: 5848 case ARM::VCLTzv2i32: 5849 case ARM::VCLTzv4f16: 5850 case ARM::VCLTzv4f32: 5851 case ARM::VCLTzv4i16: 5852 case ARM::VCLTzv4i32: 5853 case ARM::VCLTzv8f16: 5854 case ARM::VCLTzv8i16: 5855 case ARM::VCLTzv8i8: 5856 case ARM::VCLZv16i8: 5857 case ARM::VCLZv2i32: 5858 case ARM::VCLZv4i16: 5859 case ARM::VCLZv4i32: 5860 case ARM::VCLZv8i16: 5861 case ARM::VCLZv8i8: 5862 case ARM::VCNTd: 5863 case ARM::VCNTq: 5864 case ARM::VCVTf2h: 5865 case ARM::VCVTf2sd: 5866 case ARM::VCVTf2sq: 5867 case ARM::VCVTf2ud: 5868 case ARM::VCVTf2uq: 5869 case ARM::VCVTh2f: 5870 case ARM::VCVTh2sd: 5871 case ARM::VCVTh2sq: 5872 case ARM::VCVTh2ud: 5873 case ARM::VCVTh2uq: 5874 case ARM::VCVTs2fd: 5875 case ARM::VCVTs2fq: 5876 case ARM::VCVTs2hd: 5877 case ARM::VCVTs2hq: 5878 case ARM::VCVTu2fd: 5879 case ARM::VCVTu2fq: 5880 case ARM::VCVTu2hd: 5881 case ARM::VCVTu2hq: 5882 case ARM::VMOVLsv2i64: 5883 case ARM::VMOVLsv4i32: 5884 case ARM::VMOVLsv8i16: 5885 case ARM::VMOVLuv2i64: 5886 case ARM::VMOVLuv4i32: 5887 case ARM::VMOVLuv8i16: 5888 case ARM::VMOVNv2i32: 5889 case ARM::VMOVNv4i16: 5890 case ARM::VMOVNv8i8: 5891 case ARM::VMVNd: 5892 case ARM::VMVNq: 5893 case ARM::VNEGf32q: 5894 case ARM::VNEGfd: 5895 case ARM::VNEGhd: 5896 case ARM::VNEGhq: 5897 case ARM::VNEGs16d: 5898 case ARM::VNEGs16q: 5899 case ARM::VNEGs32d: 5900 case ARM::VNEGs32q: 5901 case ARM::VNEGs8d: 5902 case ARM::VNEGs8q: 5903 case ARM::VPADDLsv16i8: 5904 case ARM::VPADDLsv2i32: 5905 case ARM::VPADDLsv4i16: 5906 case ARM::VPADDLsv4i32: 5907 case ARM::VPADDLsv8i16: 5908 case ARM::VPADDLsv8i8: 5909 case ARM::VPADDLuv16i8: 5910 case ARM::VPADDLuv2i32: 5911 case ARM::VPADDLuv4i16: 5912 case ARM::VPADDLuv4i32: 5913 case ARM::VPADDLuv8i16: 5914 case ARM::VPADDLuv8i8: 5915 case ARM::VQABSv16i8: 5916 case ARM::VQABSv2i32: 5917 case ARM::VQABSv4i16: 5918 case ARM::VQABSv4i32: 5919 case ARM::VQABSv8i16: 5920 case ARM::VQABSv8i8: 5921 case ARM::VQMOVNsuv2i32: 5922 case ARM::VQMOVNsuv4i16: 5923 case ARM::VQMOVNsuv8i8: 5924 case ARM::VQMOVNsv2i32: 5925 case ARM::VQMOVNsv4i16: 5926 case ARM::VQMOVNsv8i8: 5927 case ARM::VQMOVNuv2i32: 5928 case ARM::VQMOVNuv4i16: 5929 case ARM::VQMOVNuv8i8: 5930 case ARM::VQNEGv16i8: 5931 case ARM::VQNEGv2i32: 5932 case ARM::VQNEGv4i16: 5933 case ARM::VQNEGv4i32: 5934 case ARM::VQNEGv8i16: 5935 case ARM::VQNEGv8i8: 5936 case ARM::VRECPEd: 5937 case ARM::VRECPEfd: 5938 case ARM::VRECPEfq: 5939 case ARM::VRECPEhd: 5940 case ARM::VRECPEhq: 5941 case ARM::VRECPEq: 5942 case ARM::VREV16d8: 5943 case ARM::VREV16q8: 5944 case ARM::VREV32d16: 5945 case ARM::VREV32d8: 5946 case ARM::VREV32q16: 5947 case ARM::VREV32q8: 5948 case ARM::VREV64d16: 5949 case ARM::VREV64d32: 5950 case ARM::VREV64d8: 5951 case ARM::VREV64q16: 5952 case ARM::VREV64q32: 5953 case ARM::VREV64q8: 5954 case ARM::VRSQRTEd: 5955 case ARM::VRSQRTEfd: 5956 case ARM::VRSQRTEfq: 5957 case ARM::VRSQRTEhd: 5958 case ARM::VRSQRTEhq: 5959 case ARM::VRSQRTEq: 5960 case ARM::VSHLLi16: 5961 case ARM::VSHLLi32: 5962 case ARM::VSHLLi8: 5963 case ARM::VSWPd: 5964 case ARM::VSWPq: 5965 case ARM::VTRNd16: 5966 case ARM::VTRNd32: 5967 case ARM::VTRNd8: 5968 case ARM::VTRNq16: 5969 case ARM::VTRNq32: 5970 case ARM::VTRNq8: 5971 case ARM::VUZPd16: 5972 case ARM::VUZPd8: 5973 case ARM::VUZPq16: 5974 case ARM::VUZPq32: 5975 case ARM::VUZPq8: 5976 case ARM::VZIPd16: 5977 case ARM::VZIPd8: 5978 case ARM::VZIPq16: 5979 case ARM::VZIPq32: 5980 case ARM::VZIPq8: { 5981 // op: Vd 5982 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5983 Value |= (op & UINT64_C(16)) << 18; 5984 Value |= (op & UINT64_C(15)) << 12; 5985 // op: Vm 5986 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5987 Value |= (op & UINT64_C(16)) << 1; 5988 Value |= op & UINT64_C(15); 5989 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5990 break; 5991 } 5992 case ARM::VCVTANSDf: 5993 case ARM::VCVTANSDh: 5994 case ARM::VCVTANSQf: 5995 case ARM::VCVTANSQh: 5996 case ARM::VCVTANUDf: 5997 case ARM::VCVTANUDh: 5998 case ARM::VCVTANUQf: 5999 case ARM::VCVTANUQh: 6000 case ARM::VCVTMNSDf: 6001 case ARM::VCVTMNSDh: 6002 case ARM::VCVTMNSQf: 6003 case ARM::VCVTMNSQh: 6004 case ARM::VCVTMNUDf: 6005 case ARM::VCVTMNUDh: 6006 case ARM::VCVTMNUQf: 6007 case ARM::VCVTMNUQh: 6008 case ARM::VCVTNNSDf: 6009 case ARM::VCVTNNSDh: 6010 case ARM::VCVTNNSQf: 6011 case ARM::VCVTNNSQh: 6012 case ARM::VCVTNNUDf: 6013 case ARM::VCVTNNUDh: 6014 case ARM::VCVTNNUQf: 6015 case ARM::VCVTNNUQh: 6016 case ARM::VCVTPNSDf: 6017 case ARM::VCVTPNSDh: 6018 case ARM::VCVTPNSQf: 6019 case ARM::VCVTPNSQh: 6020 case ARM::VCVTPNUDf: 6021 case ARM::VCVTPNUDh: 6022 case ARM::VCVTPNUQf: 6023 case ARM::VCVTPNUQh: 6024 case ARM::VRINTANDf: 6025 case ARM::VRINTANDh: 6026 case ARM::VRINTANQf: 6027 case ARM::VRINTANQh: 6028 case ARM::VRINTMNDf: 6029 case ARM::VRINTMNDh: 6030 case ARM::VRINTMNQf: 6031 case ARM::VRINTMNQh: 6032 case ARM::VRINTNNDf: 6033 case ARM::VRINTNNDh: 6034 case ARM::VRINTNNQf: 6035 case ARM::VRINTNNQh: 6036 case ARM::VRINTPNDf: 6037 case ARM::VRINTPNDh: 6038 case ARM::VRINTPNQf: 6039 case ARM::VRINTPNQh: 6040 case ARM::VRINTXNDf: 6041 case ARM::VRINTXNDh: 6042 case ARM::VRINTXNQf: 6043 case ARM::VRINTXNQh: 6044 case ARM::VRINTZNDf: 6045 case ARM::VRINTZNDh: 6046 case ARM::VRINTZNQf: 6047 case ARM::VRINTZNQh: { 6048 // op: Vd 6049 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6050 Value |= (op & UINT64_C(16)) << 18; 6051 Value |= (op & UINT64_C(15)) << 12; 6052 // op: Vm 6053 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6054 Value |= (op & UINT64_C(16)) << 1; 6055 Value |= op & UINT64_C(15); 6056 Value = NEONThumb2V8PostEncoder(MI, Value, STI); 6057 break; 6058 } 6059 case ARM::VSLIv4i16: 6060 case ARM::VSLIv8i16: { 6061 // op: Vd 6062 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6063 Value |= (op & UINT64_C(16)) << 18; 6064 Value |= (op & UINT64_C(15)) << 12; 6065 // op: Vm 6066 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6067 Value |= (op & UINT64_C(16)) << 1; 6068 Value |= op & UINT64_C(15); 6069 // op: SIMM 6070 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6071 Value |= (op & UINT64_C(15)) << 16; 6072 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6073 break; 6074 } 6075 case ARM::VSLIv2i32: 6076 case ARM::VSLIv4i32: { 6077 // op: Vd 6078 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6079 Value |= (op & UINT64_C(16)) << 18; 6080 Value |= (op & UINT64_C(15)) << 12; 6081 // op: Vm 6082 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6083 Value |= (op & UINT64_C(16)) << 1; 6084 Value |= op & UINT64_C(15); 6085 // op: SIMM 6086 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6087 Value |= (op & UINT64_C(31)) << 16; 6088 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6089 break; 6090 } 6091 case ARM::VSLIv1i64: 6092 case ARM::VSLIv2i64: { 6093 // op: Vd 6094 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6095 Value |= (op & UINT64_C(16)) << 18; 6096 Value |= (op & UINT64_C(15)) << 12; 6097 // op: Vm 6098 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6099 Value |= (op & UINT64_C(16)) << 1; 6100 Value |= op & UINT64_C(15); 6101 // op: SIMM 6102 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6103 Value |= (op & UINT64_C(63)) << 16; 6104 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6105 break; 6106 } 6107 case ARM::VSLIv16i8: 6108 case ARM::VSLIv8i8: { 6109 // op: Vd 6110 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6111 Value |= (op & UINT64_C(16)) << 18; 6112 Value |= (op & UINT64_C(15)) << 12; 6113 // op: Vm 6114 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6115 Value |= (op & UINT64_C(16)) << 1; 6116 Value |= op & UINT64_C(15); 6117 // op: SIMM 6118 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6119 Value |= (op & UINT64_C(7)) << 16; 6120 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6121 break; 6122 } 6123 case ARM::VRSRAsv4i16: 6124 case ARM::VRSRAsv8i16: 6125 case ARM::VRSRAuv4i16: 6126 case ARM::VRSRAuv8i16: 6127 case ARM::VSRAsv4i16: 6128 case ARM::VSRAsv8i16: 6129 case ARM::VSRAuv4i16: 6130 case ARM::VSRAuv8i16: 6131 case ARM::VSRIv4i16: 6132 case ARM::VSRIv8i16: { 6133 // op: Vd 6134 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6135 Value |= (op & UINT64_C(16)) << 18; 6136 Value |= (op & UINT64_C(15)) << 12; 6137 // op: Vm 6138 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6139 Value |= (op & UINT64_C(16)) << 1; 6140 Value |= op & UINT64_C(15); 6141 // op: SIMM 6142 op = getShiftRight16Imm(MI, 3, Fixups, STI); 6143 Value |= (op & UINT64_C(15)) << 16; 6144 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6145 break; 6146 } 6147 case ARM::VRSRAsv2i32: 6148 case ARM::VRSRAsv4i32: 6149 case ARM::VRSRAuv2i32: 6150 case ARM::VRSRAuv4i32: 6151 case ARM::VSRAsv2i32: 6152 case ARM::VSRAsv4i32: 6153 case ARM::VSRAuv2i32: 6154 case ARM::VSRAuv4i32: 6155 case ARM::VSRIv2i32: 6156 case ARM::VSRIv4i32: { 6157 // op: Vd 6158 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6159 Value |= (op & UINT64_C(16)) << 18; 6160 Value |= (op & UINT64_C(15)) << 12; 6161 // op: Vm 6162 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6163 Value |= (op & UINT64_C(16)) << 1; 6164 Value |= op & UINT64_C(15); 6165 // op: SIMM 6166 op = getShiftRight32Imm(MI, 3, Fixups, STI); 6167 Value |= (op & UINT64_C(31)) << 16; 6168 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6169 break; 6170 } 6171 case ARM::VRSRAsv1i64: 6172 case ARM::VRSRAsv2i64: 6173 case ARM::VRSRAuv1i64: 6174 case ARM::VRSRAuv2i64: 6175 case ARM::VSRAsv1i64: 6176 case ARM::VSRAsv2i64: 6177 case ARM::VSRAuv1i64: 6178 case ARM::VSRAuv2i64: 6179 case ARM::VSRIv1i64: 6180 case ARM::VSRIv2i64: { 6181 // op: Vd 6182 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6183 Value |= (op & UINT64_C(16)) << 18; 6184 Value |= (op & UINT64_C(15)) << 12; 6185 // op: Vm 6186 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6187 Value |= (op & UINT64_C(16)) << 1; 6188 Value |= op & UINT64_C(15); 6189 // op: SIMM 6190 op = getShiftRight64Imm(MI, 3, Fixups, STI); 6191 Value |= (op & UINT64_C(63)) << 16; 6192 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6193 break; 6194 } 6195 case ARM::VRSRAsv16i8: 6196 case ARM::VRSRAsv8i8: 6197 case ARM::VRSRAuv16i8: 6198 case ARM::VRSRAuv8i8: 6199 case ARM::VSRAsv16i8: 6200 case ARM::VSRAsv8i8: 6201 case ARM::VSRAuv16i8: 6202 case ARM::VSRAuv8i8: 6203 case ARM::VSRIv16i8: 6204 case ARM::VSRIv8i8: { 6205 // op: Vd 6206 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6207 Value |= (op & UINT64_C(16)) << 18; 6208 Value |= (op & UINT64_C(15)) << 12; 6209 // op: Vm 6210 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6211 Value |= (op & UINT64_C(16)) << 1; 6212 Value |= op & UINT64_C(15); 6213 // op: SIMM 6214 op = getShiftRight8Imm(MI, 3, Fixups, STI); 6215 Value |= (op & UINT64_C(7)) << 16; 6216 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6217 break; 6218 } 6219 case ARM::AESD: 6220 case ARM::AESE: 6221 case ARM::SHA1SU1: 6222 case ARM::SHA256SU0: 6223 case ARM::VPADALsv16i8: 6224 case ARM::VPADALsv2i32: 6225 case ARM::VPADALsv4i16: 6226 case ARM::VPADALsv4i32: 6227 case ARM::VPADALsv8i16: 6228 case ARM::VPADALsv8i8: 6229 case ARM::VPADALuv16i8: 6230 case ARM::VPADALuv2i32: 6231 case ARM::VPADALuv4i16: 6232 case ARM::VPADALuv4i32: 6233 case ARM::VPADALuv8i16: 6234 case ARM::VPADALuv8i8: { 6235 // op: Vd 6236 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6237 Value |= (op & UINT64_C(16)) << 18; 6238 Value |= (op & UINT64_C(15)) << 12; 6239 // op: Vm 6240 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6241 Value |= (op & UINT64_C(16)) << 1; 6242 Value |= op & UINT64_C(15); 6243 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6244 break; 6245 } 6246 case ARM::VEXTd32: { 6247 // op: Vd 6248 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6249 Value |= (op & UINT64_C(16)) << 18; 6250 Value |= (op & UINT64_C(15)) << 12; 6251 // op: Vn 6252 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6253 Value |= (op & UINT64_C(15)) << 16; 6254 Value |= (op & UINT64_C(16)) << 3; 6255 // op: Vm 6256 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6257 Value |= (op & UINT64_C(16)) << 1; 6258 Value |= op & UINT64_C(15); 6259 // op: index 6260 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6261 Value |= (op & UINT64_C(1)) << 10; 6262 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6263 break; 6264 } 6265 case ARM::VEXTq64: { 6266 // op: Vd 6267 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6268 Value |= (op & UINT64_C(16)) << 18; 6269 Value |= (op & UINT64_C(15)) << 12; 6270 // op: Vn 6271 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6272 Value |= (op & UINT64_C(15)) << 16; 6273 Value |= (op & UINT64_C(16)) << 3; 6274 // op: Vm 6275 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6276 Value |= (op & UINT64_C(16)) << 1; 6277 Value |= op & UINT64_C(15); 6278 // op: index 6279 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6280 Value |= (op & UINT64_C(1)) << 11; 6281 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6282 break; 6283 } 6284 case ARM::VEXTq8: { 6285 // op: Vd 6286 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6287 Value |= (op & UINT64_C(16)) << 18; 6288 Value |= (op & UINT64_C(15)) << 12; 6289 // op: Vn 6290 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6291 Value |= (op & UINT64_C(15)) << 16; 6292 Value |= (op & UINT64_C(16)) << 3; 6293 // op: Vm 6294 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6295 Value |= (op & UINT64_C(16)) << 1; 6296 Value |= op & UINT64_C(15); 6297 // op: index 6298 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6299 Value |= (op & UINT64_C(15)) << 8; 6300 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6301 break; 6302 } 6303 case ARM::VEXTq32: { 6304 // op: Vd 6305 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6306 Value |= (op & UINT64_C(16)) << 18; 6307 Value |= (op & UINT64_C(15)) << 12; 6308 // op: Vn 6309 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6310 Value |= (op & UINT64_C(15)) << 16; 6311 Value |= (op & UINT64_C(16)) << 3; 6312 // op: Vm 6313 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6314 Value |= (op & UINT64_C(16)) << 1; 6315 Value |= op & UINT64_C(15); 6316 // op: index 6317 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6318 Value |= (op & UINT64_C(3)) << 10; 6319 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6320 break; 6321 } 6322 case ARM::VEXTd16: { 6323 // op: Vd 6324 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6325 Value |= (op & UINT64_C(16)) << 18; 6326 Value |= (op & UINT64_C(15)) << 12; 6327 // op: Vn 6328 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6329 Value |= (op & UINT64_C(15)) << 16; 6330 Value |= (op & UINT64_C(16)) << 3; 6331 // op: Vm 6332 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6333 Value |= (op & UINT64_C(16)) << 1; 6334 Value |= op & UINT64_C(15); 6335 // op: index 6336 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6337 Value |= (op & UINT64_C(3)) << 9; 6338 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6339 break; 6340 } 6341 case ARM::VEXTd8: { 6342 // op: Vd 6343 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6344 Value |= (op & UINT64_C(16)) << 18; 6345 Value |= (op & UINT64_C(15)) << 12; 6346 // op: Vn 6347 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6348 Value |= (op & UINT64_C(15)) << 16; 6349 Value |= (op & UINT64_C(16)) << 3; 6350 // op: Vm 6351 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6352 Value |= (op & UINT64_C(16)) << 1; 6353 Value |= op & UINT64_C(15); 6354 // op: index 6355 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6356 Value |= (op & UINT64_C(7)) << 8; 6357 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6358 break; 6359 } 6360 case ARM::VEXTq16: { 6361 // op: Vd 6362 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6363 Value |= (op & UINT64_C(16)) << 18; 6364 Value |= (op & UINT64_C(15)) << 12; 6365 // op: Vn 6366 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6367 Value |= (op & UINT64_C(15)) << 16; 6368 Value |= (op & UINT64_C(16)) << 3; 6369 // op: Vm 6370 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6371 Value |= (op & UINT64_C(16)) << 1; 6372 Value |= op & UINT64_C(15); 6373 // op: index 6374 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6375 Value |= (op & UINT64_C(7)) << 9; 6376 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6377 break; 6378 } 6379 case ARM::VABDLsv2i64: 6380 case ARM::VABDLsv4i32: 6381 case ARM::VABDLsv8i16: 6382 case ARM::VABDLuv2i64: 6383 case ARM::VABDLuv4i32: 6384 case ARM::VABDLuv8i16: 6385 case ARM::VABDfd: 6386 case ARM::VABDfq: 6387 case ARM::VABDhd: 6388 case ARM::VABDhq: 6389 case ARM::VABDsv16i8: 6390 case ARM::VABDsv2i32: 6391 case ARM::VABDsv4i16: 6392 case ARM::VABDsv4i32: 6393 case ARM::VABDsv8i16: 6394 case ARM::VABDsv8i8: 6395 case ARM::VABDuv16i8: 6396 case ARM::VABDuv2i32: 6397 case ARM::VABDuv4i16: 6398 case ARM::VABDuv4i32: 6399 case ARM::VABDuv8i16: 6400 case ARM::VABDuv8i8: 6401 case ARM::VACGEfd: 6402 case ARM::VACGEfq: 6403 case ARM::VACGEhd: 6404 case ARM::VACGEhq: 6405 case ARM::VACGTfd: 6406 case ARM::VACGTfq: 6407 case ARM::VACGThd: 6408 case ARM::VACGThq: 6409 case ARM::VADDHNv2i32: 6410 case ARM::VADDHNv4i16: 6411 case ARM::VADDHNv8i8: 6412 case ARM::VADDLsv2i64: 6413 case ARM::VADDLsv4i32: 6414 case ARM::VADDLsv8i16: 6415 case ARM::VADDLuv2i64: 6416 case ARM::VADDLuv4i32: 6417 case ARM::VADDLuv8i16: 6418 case ARM::VADDWsv2i64: 6419 case ARM::VADDWsv4i32: 6420 case ARM::VADDWsv8i16: 6421 case ARM::VADDWuv2i64: 6422 case ARM::VADDWuv4i32: 6423 case ARM::VADDWuv8i16: 6424 case ARM::VADDfd: 6425 case ARM::VADDfq: 6426 case ARM::VADDhd: 6427 case ARM::VADDhq: 6428 case ARM::VADDv16i8: 6429 case ARM::VADDv1i64: 6430 case ARM::VADDv2i32: 6431 case ARM::VADDv2i64: 6432 case ARM::VADDv4i16: 6433 case ARM::VADDv4i32: 6434 case ARM::VADDv8i16: 6435 case ARM::VADDv8i8: 6436 case ARM::VANDd: 6437 case ARM::VANDq: 6438 case ARM::VBICd: 6439 case ARM::VBICq: 6440 case ARM::VCEQfd: 6441 case ARM::VCEQfq: 6442 case ARM::VCEQhd: 6443 case ARM::VCEQhq: 6444 case ARM::VCEQv16i8: 6445 case ARM::VCEQv2i32: 6446 case ARM::VCEQv4i16: 6447 case ARM::VCEQv4i32: 6448 case ARM::VCEQv8i16: 6449 case ARM::VCEQv8i8: 6450 case ARM::VCGEfd: 6451 case ARM::VCGEfq: 6452 case ARM::VCGEhd: 6453 case ARM::VCGEhq: 6454 case ARM::VCGEsv16i8: 6455 case ARM::VCGEsv2i32: 6456 case ARM::VCGEsv4i16: 6457 case ARM::VCGEsv4i32: 6458 case ARM::VCGEsv8i16: 6459 case ARM::VCGEsv8i8: 6460 case ARM::VCGEuv16i8: 6461 case ARM::VCGEuv2i32: 6462 case ARM::VCGEuv4i16: 6463 case ARM::VCGEuv4i32: 6464 case ARM::VCGEuv8i16: 6465 case ARM::VCGEuv8i8: 6466 case ARM::VCGTfd: 6467 case ARM::VCGTfq: 6468 case ARM::VCGThd: 6469 case ARM::VCGThq: 6470 case ARM::VCGTsv16i8: 6471 case ARM::VCGTsv2i32: 6472 case ARM::VCGTsv4i16: 6473 case ARM::VCGTsv4i32: 6474 case ARM::VCGTsv8i16: 6475 case ARM::VCGTsv8i8: 6476 case ARM::VCGTuv16i8: 6477 case ARM::VCGTuv2i32: 6478 case ARM::VCGTuv4i16: 6479 case ARM::VCGTuv4i32: 6480 case ARM::VCGTuv8i16: 6481 case ARM::VCGTuv8i8: 6482 case ARM::VEORd: 6483 case ARM::VEORq: 6484 case ARM::VHADDsv16i8: 6485 case ARM::VHADDsv2i32: 6486 case ARM::VHADDsv4i16: 6487 case ARM::VHADDsv4i32: 6488 case ARM::VHADDsv8i16: 6489 case ARM::VHADDsv8i8: 6490 case ARM::VHADDuv16i8: 6491 case ARM::VHADDuv2i32: 6492 case ARM::VHADDuv4i16: 6493 case ARM::VHADDuv4i32: 6494 case ARM::VHADDuv8i16: 6495 case ARM::VHADDuv8i8: 6496 case ARM::VHSUBsv16i8: 6497 case ARM::VHSUBsv2i32: 6498 case ARM::VHSUBsv4i16: 6499 case ARM::VHSUBsv4i32: 6500 case ARM::VHSUBsv8i16: 6501 case ARM::VHSUBsv8i8: 6502 case ARM::VHSUBuv16i8: 6503 case ARM::VHSUBuv2i32: 6504 case ARM::VHSUBuv4i16: 6505 case ARM::VHSUBuv4i32: 6506 case ARM::VHSUBuv8i16: 6507 case ARM::VHSUBuv8i8: 6508 case ARM::VMAXfd: 6509 case ARM::VMAXfq: 6510 case ARM::VMAXhd: 6511 case ARM::VMAXhq: 6512 case ARM::VMAXsv16i8: 6513 case ARM::VMAXsv2i32: 6514 case ARM::VMAXsv4i16: 6515 case ARM::VMAXsv4i32: 6516 case ARM::VMAXsv8i16: 6517 case ARM::VMAXsv8i8: 6518 case ARM::VMAXuv16i8: 6519 case ARM::VMAXuv2i32: 6520 case ARM::VMAXuv4i16: 6521 case ARM::VMAXuv4i32: 6522 case ARM::VMAXuv8i16: 6523 case ARM::VMAXuv8i8: 6524 case ARM::VMINfd: 6525 case ARM::VMINfq: 6526 case ARM::VMINhd: 6527 case ARM::VMINhq: 6528 case ARM::VMINsv16i8: 6529 case ARM::VMINsv2i32: 6530 case ARM::VMINsv4i16: 6531 case ARM::VMINsv4i32: 6532 case ARM::VMINsv8i16: 6533 case ARM::VMINsv8i8: 6534 case ARM::VMINuv16i8: 6535 case ARM::VMINuv2i32: 6536 case ARM::VMINuv4i16: 6537 case ARM::VMINuv4i32: 6538 case ARM::VMINuv8i16: 6539 case ARM::VMINuv8i8: 6540 case ARM::VMULLp64: 6541 case ARM::VMULLp8: 6542 case ARM::VMULLsv2i64: 6543 case ARM::VMULLsv4i32: 6544 case ARM::VMULLsv8i16: 6545 case ARM::VMULLuv2i64: 6546 case ARM::VMULLuv4i32: 6547 case ARM::VMULLuv8i16: 6548 case ARM::VMULfd: 6549 case ARM::VMULfq: 6550 case ARM::VMULhd: 6551 case ARM::VMULhq: 6552 case ARM::VMULpd: 6553 case ARM::VMULpq: 6554 case ARM::VMULv16i8: 6555 case ARM::VMULv2i32: 6556 case ARM::VMULv4i16: 6557 case ARM::VMULv4i32: 6558 case ARM::VMULv8i16: 6559 case ARM::VMULv8i8: 6560 case ARM::VORNd: 6561 case ARM::VORNq: 6562 case ARM::VORRd: 6563 case ARM::VORRq: 6564 case ARM::VPADDf: 6565 case ARM::VPADDh: 6566 case ARM::VPADDi16: 6567 case ARM::VPADDi32: 6568 case ARM::VPADDi8: 6569 case ARM::VPMAXf: 6570 case ARM::VPMAXh: 6571 case ARM::VPMAXs16: 6572 case ARM::VPMAXs32: 6573 case ARM::VPMAXs8: 6574 case ARM::VPMAXu16: 6575 case ARM::VPMAXu32: 6576 case ARM::VPMAXu8: 6577 case ARM::VPMINf: 6578 case ARM::VPMINh: 6579 case ARM::VPMINs16: 6580 case ARM::VPMINs32: 6581 case ARM::VPMINs8: 6582 case ARM::VPMINu16: 6583 case ARM::VPMINu32: 6584 case ARM::VPMINu8: 6585 case ARM::VQADDsv16i8: 6586 case ARM::VQADDsv1i64: 6587 case ARM::VQADDsv2i32: 6588 case ARM::VQADDsv2i64: 6589 case ARM::VQADDsv4i16: 6590 case ARM::VQADDsv4i32: 6591 case ARM::VQADDsv8i16: 6592 case ARM::VQADDsv8i8: 6593 case ARM::VQADDuv16i8: 6594 case ARM::VQADDuv1i64: 6595 case ARM::VQADDuv2i32: 6596 case ARM::VQADDuv2i64: 6597 case ARM::VQADDuv4i16: 6598 case ARM::VQADDuv4i32: 6599 case ARM::VQADDuv8i16: 6600 case ARM::VQADDuv8i8: 6601 case ARM::VQDMULHv2i32: 6602 case ARM::VQDMULHv4i16: 6603 case ARM::VQDMULHv4i32: 6604 case ARM::VQDMULHv8i16: 6605 case ARM::VQDMULLv2i64: 6606 case ARM::VQDMULLv4i32: 6607 case ARM::VQRDMULHv2i32: 6608 case ARM::VQRDMULHv4i16: 6609 case ARM::VQRDMULHv4i32: 6610 case ARM::VQRDMULHv8i16: 6611 case ARM::VQSUBsv16i8: 6612 case ARM::VQSUBsv1i64: 6613 case ARM::VQSUBsv2i32: 6614 case ARM::VQSUBsv2i64: 6615 case ARM::VQSUBsv4i16: 6616 case ARM::VQSUBsv4i32: 6617 case ARM::VQSUBsv8i16: 6618 case ARM::VQSUBsv8i8: 6619 case ARM::VQSUBuv16i8: 6620 case ARM::VQSUBuv1i64: 6621 case ARM::VQSUBuv2i32: 6622 case ARM::VQSUBuv2i64: 6623 case ARM::VQSUBuv4i16: 6624 case ARM::VQSUBuv4i32: 6625 case ARM::VQSUBuv8i16: 6626 case ARM::VQSUBuv8i8: 6627 case ARM::VRADDHNv2i32: 6628 case ARM::VRADDHNv4i16: 6629 case ARM::VRADDHNv8i8: 6630 case ARM::VRECPSfd: 6631 case ARM::VRECPSfq: 6632 case ARM::VRECPShd: 6633 case ARM::VRECPShq: 6634 case ARM::VRHADDsv16i8: 6635 case ARM::VRHADDsv2i32: 6636 case ARM::VRHADDsv4i16: 6637 case ARM::VRHADDsv4i32: 6638 case ARM::VRHADDsv8i16: 6639 case ARM::VRHADDsv8i8: 6640 case ARM::VRHADDuv16i8: 6641 case ARM::VRHADDuv2i32: 6642 case ARM::VRHADDuv4i16: 6643 case ARM::VRHADDuv4i32: 6644 case ARM::VRHADDuv8i16: 6645 case ARM::VRHADDuv8i8: 6646 case ARM::VRSQRTSfd: 6647 case ARM::VRSQRTSfq: 6648 case ARM::VRSQRTShd: 6649 case ARM::VRSQRTShq: 6650 case ARM::VRSUBHNv2i32: 6651 case ARM::VRSUBHNv4i16: 6652 case ARM::VRSUBHNv8i8: 6653 case ARM::VSUBHNv2i32: 6654 case ARM::VSUBHNv4i16: 6655 case ARM::VSUBHNv8i8: 6656 case ARM::VSUBLsv2i64: 6657 case ARM::VSUBLsv4i32: 6658 case ARM::VSUBLsv8i16: 6659 case ARM::VSUBLuv2i64: 6660 case ARM::VSUBLuv4i32: 6661 case ARM::VSUBLuv8i16: 6662 case ARM::VSUBWsv2i64: 6663 case ARM::VSUBWsv4i32: 6664 case ARM::VSUBWsv8i16: 6665 case ARM::VSUBWuv2i64: 6666 case ARM::VSUBWuv4i32: 6667 case ARM::VSUBWuv8i16: 6668 case ARM::VSUBfd: 6669 case ARM::VSUBfq: 6670 case ARM::VSUBhd: 6671 case ARM::VSUBhq: 6672 case ARM::VSUBv16i8: 6673 case ARM::VSUBv1i64: 6674 case ARM::VSUBv2i32: 6675 case ARM::VSUBv2i64: 6676 case ARM::VSUBv4i16: 6677 case ARM::VSUBv4i32: 6678 case ARM::VSUBv8i16: 6679 case ARM::VSUBv8i8: 6680 case ARM::VTBL1: 6681 case ARM::VTBL2: 6682 case ARM::VTBL3: 6683 case ARM::VTBL4: 6684 case ARM::VTSTv16i8: 6685 case ARM::VTSTv2i32: 6686 case ARM::VTSTv4i16: 6687 case ARM::VTSTv4i32: 6688 case ARM::VTSTv8i16: 6689 case ARM::VTSTv8i8: { 6690 // op: Vd 6691 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6692 Value |= (op & UINT64_C(16)) << 18; 6693 Value |= (op & UINT64_C(15)) << 12; 6694 // op: Vn 6695 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6696 Value |= (op & UINT64_C(15)) << 16; 6697 Value |= (op & UINT64_C(16)) << 3; 6698 // op: Vm 6699 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6700 Value |= (op & UINT64_C(16)) << 1; 6701 Value |= op & UINT64_C(15); 6702 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6703 break; 6704 } 6705 case ARM::VMAXNMNDf: 6706 case ARM::VMAXNMNDh: 6707 case ARM::VMAXNMNQf: 6708 case ARM::VMAXNMNQh: 6709 case ARM::VMINNMNDf: 6710 case ARM::VMINNMNDh: 6711 case ARM::VMINNMNQf: 6712 case ARM::VMINNMNQh: { 6713 // op: Vd 6714 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6715 Value |= (op & UINT64_C(16)) << 18; 6716 Value |= (op & UINT64_C(15)) << 12; 6717 // op: Vn 6718 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6719 Value |= (op & UINT64_C(15)) << 16; 6720 Value |= (op & UINT64_C(16)) << 3; 6721 // op: Vm 6722 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6723 Value |= (op & UINT64_C(16)) << 1; 6724 Value |= op & UINT64_C(15); 6725 Value = NEONThumb2V8PostEncoder(MI, Value, STI); 6726 break; 6727 } 6728 case ARM::VMULLslsv2i32: 6729 case ARM::VMULLsluv2i32: 6730 case ARM::VMULslfd: 6731 case ARM::VMULslfq: 6732 case ARM::VMULslv2i32: 6733 case ARM::VMULslv4i32: 6734 case ARM::VQDMULHslv2i32: 6735 case ARM::VQDMULHslv4i32: 6736 case ARM::VQDMULLslv2i32: 6737 case ARM::VQRDMULHslv2i32: 6738 case ARM::VQRDMULHslv4i32: { 6739 // op: Vd 6740 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6741 Value |= (op & UINT64_C(16)) << 18; 6742 Value |= (op & UINT64_C(15)) << 12; 6743 // op: Vn 6744 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6745 Value |= (op & UINT64_C(15)) << 16; 6746 Value |= (op & UINT64_C(16)) << 3; 6747 // op: Vm 6748 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6749 Value |= op & UINT64_C(15); 6750 // op: lane 6751 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6752 Value |= (op & UINT64_C(1)) << 5; 6753 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6754 break; 6755 } 6756 case ARM::VMULLslsv4i16: 6757 case ARM::VMULLsluv4i16: 6758 case ARM::VMULslhd: 6759 case ARM::VMULslhq: 6760 case ARM::VMULslv4i16: 6761 case ARM::VMULslv8i16: 6762 case ARM::VQDMULHslv4i16: 6763 case ARM::VQDMULHslv8i16: 6764 case ARM::VQDMULLslv4i16: 6765 case ARM::VQRDMULHslv4i16: 6766 case ARM::VQRDMULHslv8i16: { 6767 // op: Vd 6768 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6769 Value |= (op & UINT64_C(16)) << 18; 6770 Value |= (op & UINT64_C(15)) << 12; 6771 // op: Vn 6772 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6773 Value |= (op & UINT64_C(15)) << 16; 6774 Value |= (op & UINT64_C(16)) << 3; 6775 // op: Vm 6776 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6777 Value |= op & UINT64_C(7); 6778 // op: lane 6779 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6780 Value |= (op & UINT64_C(2)) << 4; 6781 Value |= (op & UINT64_C(1)) << 3; 6782 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6783 break; 6784 } 6785 case ARM::VQRSHLsv16i8: 6786 case ARM::VQRSHLsv1i64: 6787 case ARM::VQRSHLsv2i32: 6788 case ARM::VQRSHLsv2i64: 6789 case ARM::VQRSHLsv4i16: 6790 case ARM::VQRSHLsv4i32: 6791 case ARM::VQRSHLsv8i16: 6792 case ARM::VQRSHLsv8i8: 6793 case ARM::VQRSHLuv16i8: 6794 case ARM::VQRSHLuv1i64: 6795 case ARM::VQRSHLuv2i32: 6796 case ARM::VQRSHLuv2i64: 6797 case ARM::VQRSHLuv4i16: 6798 case ARM::VQRSHLuv4i32: 6799 case ARM::VQRSHLuv8i16: 6800 case ARM::VQRSHLuv8i8: 6801 case ARM::VQSHLsv16i8: 6802 case ARM::VQSHLsv1i64: 6803 case ARM::VQSHLsv2i32: 6804 case ARM::VQSHLsv2i64: 6805 case ARM::VQSHLsv4i16: 6806 case ARM::VQSHLsv4i32: 6807 case ARM::VQSHLsv8i16: 6808 case ARM::VQSHLsv8i8: 6809 case ARM::VQSHLuv16i8: 6810 case ARM::VQSHLuv1i64: 6811 case ARM::VQSHLuv2i32: 6812 case ARM::VQSHLuv2i64: 6813 case ARM::VQSHLuv4i16: 6814 case ARM::VQSHLuv4i32: 6815 case ARM::VQSHLuv8i16: 6816 case ARM::VQSHLuv8i8: 6817 case ARM::VRSHLsv16i8: 6818 case ARM::VRSHLsv1i64: 6819 case ARM::VRSHLsv2i32: 6820 case ARM::VRSHLsv2i64: 6821 case ARM::VRSHLsv4i16: 6822 case ARM::VRSHLsv4i32: 6823 case ARM::VRSHLsv8i16: 6824 case ARM::VRSHLsv8i8: 6825 case ARM::VRSHLuv16i8: 6826 case ARM::VRSHLuv1i64: 6827 case ARM::VRSHLuv2i32: 6828 case ARM::VRSHLuv2i64: 6829 case ARM::VRSHLuv4i16: 6830 case ARM::VRSHLuv4i32: 6831 case ARM::VRSHLuv8i16: 6832 case ARM::VRSHLuv8i8: 6833 case ARM::VSHLsv16i8: 6834 case ARM::VSHLsv1i64: 6835 case ARM::VSHLsv2i32: 6836 case ARM::VSHLsv2i64: 6837 case ARM::VSHLsv4i16: 6838 case ARM::VSHLsv4i32: 6839 case ARM::VSHLsv8i16: 6840 case ARM::VSHLsv8i8: 6841 case ARM::VSHLuv16i8: 6842 case ARM::VSHLuv1i64: 6843 case ARM::VSHLuv2i32: 6844 case ARM::VSHLuv2i64: 6845 case ARM::VSHLuv4i16: 6846 case ARM::VSHLuv4i32: 6847 case ARM::VSHLuv8i16: 6848 case ARM::VSHLuv8i8: { 6849 // op: Vd 6850 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6851 Value |= (op & UINT64_C(16)) << 18; 6852 Value |= (op & UINT64_C(15)) << 12; 6853 // op: Vn 6854 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6855 Value |= (op & UINT64_C(15)) << 16; 6856 Value |= (op & UINT64_C(16)) << 3; 6857 // op: Vm 6858 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6859 Value |= (op & UINT64_C(16)) << 1; 6860 Value |= op & UINT64_C(15); 6861 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6862 break; 6863 } 6864 case ARM::SHA1C: 6865 case ARM::SHA1M: 6866 case ARM::SHA1P: 6867 case ARM::SHA1SU0: 6868 case ARM::SHA256H: 6869 case ARM::SHA256H2: 6870 case ARM::SHA256SU1: 6871 case ARM::VABALsv2i64: 6872 case ARM::VABALsv4i32: 6873 case ARM::VABALsv8i16: 6874 case ARM::VABALuv2i64: 6875 case ARM::VABALuv4i32: 6876 case ARM::VABALuv8i16: 6877 case ARM::VABAsv16i8: 6878 case ARM::VABAsv2i32: 6879 case ARM::VABAsv4i16: 6880 case ARM::VABAsv4i32: 6881 case ARM::VABAsv8i16: 6882 case ARM::VABAsv8i8: 6883 case ARM::VABAuv16i8: 6884 case ARM::VABAuv2i32: 6885 case ARM::VABAuv4i16: 6886 case ARM::VABAuv4i32: 6887 case ARM::VABAuv8i16: 6888 case ARM::VABAuv8i8: 6889 case ARM::VBIFd: 6890 case ARM::VBIFq: 6891 case ARM::VBITd: 6892 case ARM::VBITq: 6893 case ARM::VBSLd: 6894 case ARM::VBSLq: 6895 case ARM::VFMAfd: 6896 case ARM::VFMAfq: 6897 case ARM::VFMAhd: 6898 case ARM::VFMAhq: 6899 case ARM::VFMSfd: 6900 case ARM::VFMSfq: 6901 case ARM::VFMShd: 6902 case ARM::VFMShq: 6903 case ARM::VMLALsv2i64: 6904 case ARM::VMLALsv4i32: 6905 case ARM::VMLALsv8i16: 6906 case ARM::VMLALuv2i64: 6907 case ARM::VMLALuv4i32: 6908 case ARM::VMLALuv8i16: 6909 case ARM::VMLAfd: 6910 case ARM::VMLAfq: 6911 case ARM::VMLAhd: 6912 case ARM::VMLAhq: 6913 case ARM::VMLAv16i8: 6914 case ARM::VMLAv2i32: 6915 case ARM::VMLAv4i16: 6916 case ARM::VMLAv4i32: 6917 case ARM::VMLAv8i16: 6918 case ARM::VMLAv8i8: 6919 case ARM::VMLSLsv2i64: 6920 case ARM::VMLSLsv4i32: 6921 case ARM::VMLSLsv8i16: 6922 case ARM::VMLSLuv2i64: 6923 case ARM::VMLSLuv4i32: 6924 case ARM::VMLSLuv8i16: 6925 case ARM::VMLSfd: 6926 case ARM::VMLSfq: 6927 case ARM::VMLShd: 6928 case ARM::VMLShq: 6929 case ARM::VMLSv16i8: 6930 case ARM::VMLSv2i32: 6931 case ARM::VMLSv4i16: 6932 case ARM::VMLSv4i32: 6933 case ARM::VMLSv8i16: 6934 case ARM::VMLSv8i8: 6935 case ARM::VQDMLALv2i64: 6936 case ARM::VQDMLALv4i32: 6937 case ARM::VQDMLSLv2i64: 6938 case ARM::VQDMLSLv4i32: 6939 case ARM::VQRDMLAHv2i32: 6940 case ARM::VQRDMLAHv4i16: 6941 case ARM::VQRDMLAHv4i32: 6942 case ARM::VQRDMLAHv8i16: 6943 case ARM::VQRDMLSHv2i32: 6944 case ARM::VQRDMLSHv4i16: 6945 case ARM::VQRDMLSHv4i32: 6946 case ARM::VQRDMLSHv8i16: 6947 case ARM::VTBX1: 6948 case ARM::VTBX2: 6949 case ARM::VTBX3: 6950 case ARM::VTBX4: { 6951 // op: Vd 6952 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6953 Value |= (op & UINT64_C(16)) << 18; 6954 Value |= (op & UINT64_C(15)) << 12; 6955 // op: Vn 6956 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6957 Value |= (op & UINT64_C(15)) << 16; 6958 Value |= (op & UINT64_C(16)) << 3; 6959 // op: Vm 6960 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6961 Value |= (op & UINT64_C(16)) << 1; 6962 Value |= op & UINT64_C(15); 6963 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6964 break; 6965 } 6966 case ARM::VMLALslsv2i32: 6967 case ARM::VMLALsluv2i32: 6968 case ARM::VMLAslfd: 6969 case ARM::VMLAslfq: 6970 case ARM::VMLAslv2i32: 6971 case ARM::VMLAslv4i32: 6972 case ARM::VMLSLslsv2i32: 6973 case ARM::VMLSLsluv2i32: 6974 case ARM::VMLSslfd: 6975 case ARM::VMLSslfq: 6976 case ARM::VMLSslv2i32: 6977 case ARM::VMLSslv4i32: 6978 case ARM::VQDMLALslv2i32: 6979 case ARM::VQDMLSLslv2i32: 6980 case ARM::VQRDMLAHslv2i32: 6981 case ARM::VQRDMLAHslv4i32: 6982 case ARM::VQRDMLSHslv2i32: 6983 case ARM::VQRDMLSHslv4i32: { 6984 // op: Vd 6985 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6986 Value |= (op & UINT64_C(16)) << 18; 6987 Value |= (op & UINT64_C(15)) << 12; 6988 // op: Vn 6989 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6990 Value |= (op & UINT64_C(15)) << 16; 6991 Value |= (op & UINT64_C(16)) << 3; 6992 // op: Vm 6993 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6994 Value |= op & UINT64_C(15); 6995 // op: lane 6996 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 6997 Value |= (op & UINT64_C(1)) << 5; 6998 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6999 break; 7000 } 7001 case ARM::VMLALslsv4i16: 7002 case ARM::VMLALsluv4i16: 7003 case ARM::VMLAslhd: 7004 case ARM::VMLAslhq: 7005 case ARM::VMLAslv4i16: 7006 case ARM::VMLAslv8i16: 7007 case ARM::VMLSLslsv4i16: 7008 case ARM::VMLSLsluv4i16: 7009 case ARM::VMLSslhd: 7010 case ARM::VMLSslhq: 7011 case ARM::VMLSslv4i16: 7012 case ARM::VMLSslv8i16: 7013 case ARM::VQDMLALslv4i16: 7014 case ARM::VQDMLSLslv4i16: 7015 case ARM::VQRDMLAHslv4i16: 7016 case ARM::VQRDMLAHslv8i16: 7017 case ARM::VQRDMLSHslv4i16: 7018 case ARM::VQRDMLSHslv8i16: { 7019 // op: Vd 7020 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7021 Value |= (op & UINT64_C(16)) << 18; 7022 Value |= (op & UINT64_C(15)) << 12; 7023 // op: Vn 7024 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7025 Value |= (op & UINT64_C(15)) << 16; 7026 Value |= (op & UINT64_C(16)) << 3; 7027 // op: Vm 7028 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7029 Value |= op & UINT64_C(7); 7030 // op: lane 7031 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7032 Value |= (op & UINT64_C(2)) << 4; 7033 Value |= (op & UINT64_C(1)) << 3; 7034 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 7035 break; 7036 } 7037 case ARM::VST1LNd8: { 7038 // op: Vd 7039 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7040 Value |= (op & UINT64_C(16)) << 18; 7041 Value |= (op & UINT64_C(15)) << 12; 7042 // op: Rn 7043 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 7044 Value |= (op & UINT64_C(15)) << 16; 7045 // op: lane 7046 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7047 Value |= (op & UINT64_C(7)) << 5; 7048 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7049 break; 7050 } 7051 case ARM::VST3LNd32: 7052 case ARM::VST3LNq32: { 7053 // op: Vd 7054 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7055 Value |= (op & UINT64_C(16)) << 18; 7056 Value |= (op & UINT64_C(15)) << 12; 7057 // op: Rn 7058 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 7059 Value |= (op & UINT64_C(15)) << 16; 7060 // op: lane 7061 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 7062 Value |= (op & UINT64_C(1)) << 7; 7063 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7064 break; 7065 } 7066 case ARM::VST3LNd16: 7067 case ARM::VST3LNq16: { 7068 // op: Vd 7069 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7070 Value |= (op & UINT64_C(16)) << 18; 7071 Value |= (op & UINT64_C(15)) << 12; 7072 // op: Rn 7073 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 7074 Value |= (op & UINT64_C(15)) << 16; 7075 // op: lane 7076 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 7077 Value |= (op & UINT64_C(3)) << 6; 7078 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7079 break; 7080 } 7081 case ARM::VST3LNd8: { 7082 // op: Vd 7083 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7084 Value |= (op & UINT64_C(16)) << 18; 7085 Value |= (op & UINT64_C(15)) << 12; 7086 // op: Rn 7087 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 7088 Value |= (op & UINT64_C(15)) << 16; 7089 // op: lane 7090 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 7091 Value |= (op & UINT64_C(7)) << 5; 7092 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7093 break; 7094 } 7095 case ARM::VST1LNd16: { 7096 // op: Vd 7097 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7098 Value |= (op & UINT64_C(16)) << 18; 7099 Value |= (op & UINT64_C(15)) << 12; 7100 // op: Rn 7101 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 7102 Value |= (op & UINT64_C(15)) << 16; 7103 Value |= op & UINT64_C(16); 7104 // op: lane 7105 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7106 Value |= (op & UINT64_C(3)) << 6; 7107 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7108 break; 7109 } 7110 case ARM::VST2LNd32: 7111 case ARM::VST2LNq32: { 7112 // op: Vd 7113 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7114 Value |= (op & UINT64_C(16)) << 18; 7115 Value |= (op & UINT64_C(15)) << 12; 7116 // op: Rn 7117 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 7118 Value |= (op & UINT64_C(15)) << 16; 7119 Value |= op & UINT64_C(16); 7120 // op: lane 7121 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7122 Value |= (op & UINT64_C(1)) << 7; 7123 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7124 break; 7125 } 7126 case ARM::VST2LNd16: 7127 case ARM::VST2LNq16: { 7128 // op: Vd 7129 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7130 Value |= (op & UINT64_C(16)) << 18; 7131 Value |= (op & UINT64_C(15)) << 12; 7132 // op: Rn 7133 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 7134 Value |= (op & UINT64_C(15)) << 16; 7135 Value |= op & UINT64_C(16); 7136 // op: lane 7137 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7138 Value |= (op & UINT64_C(3)) << 6; 7139 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7140 break; 7141 } 7142 case ARM::VST2LNd8: { 7143 // op: Vd 7144 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7145 Value |= (op & UINT64_C(16)) << 18; 7146 Value |= (op & UINT64_C(15)) << 12; 7147 // op: Rn 7148 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 7149 Value |= (op & UINT64_C(15)) << 16; 7150 Value |= op & UINT64_C(16); 7151 // op: lane 7152 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7153 Value |= (op & UINT64_C(7)) << 5; 7154 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7155 break; 7156 } 7157 case ARM::VST4LNd16: 7158 case ARM::VST4LNq16: { 7159 // op: Vd 7160 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7161 Value |= (op & UINT64_C(16)) << 18; 7162 Value |= (op & UINT64_C(15)) << 12; 7163 // op: Rn 7164 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 7165 Value |= (op & UINT64_C(15)) << 16; 7166 Value |= op & UINT64_C(16); 7167 // op: lane 7168 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 7169 Value |= (op & UINT64_C(3)) << 6; 7170 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7171 break; 7172 } 7173 case ARM::VST4LNd8: { 7174 // op: Vd 7175 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7176 Value |= (op & UINT64_C(16)) << 18; 7177 Value |= (op & UINT64_C(15)) << 12; 7178 // op: Rn 7179 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 7180 Value |= (op & UINT64_C(15)) << 16; 7181 Value |= op & UINT64_C(16); 7182 // op: lane 7183 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 7184 Value |= (op & UINT64_C(7)) << 5; 7185 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7186 break; 7187 } 7188 case ARM::VST1d16: 7189 case ARM::VST1d16T: 7190 case ARM::VST1d32: 7191 case ARM::VST1d32T: 7192 case ARM::VST1d64: 7193 case ARM::VST1d64T: 7194 case ARM::VST1d8: 7195 case ARM::VST1d8T: 7196 case ARM::VST3d16: 7197 case ARM::VST3d32: 7198 case ARM::VST3d8: 7199 case ARM::VST3q16: 7200 case ARM::VST3q32: 7201 case ARM::VST3q8: { 7202 // op: Vd 7203 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7204 Value |= (op & UINT64_C(16)) << 18; 7205 Value |= (op & UINT64_C(15)) << 12; 7206 // op: Rn 7207 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 7208 Value |= (op & UINT64_C(15)) << 16; 7209 Value |= op & UINT64_C(16); 7210 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7211 break; 7212 } 7213 case ARM::VST4LNd32: 7214 case ARM::VST4LNq32: { 7215 // op: Vd 7216 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7217 Value |= (op & UINT64_C(16)) << 18; 7218 Value |= (op & UINT64_C(15)) << 12; 7219 // op: Rn 7220 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 7221 Value |= (op & UINT64_C(15)) << 16; 7222 Value |= op & UINT64_C(48); 7223 // op: lane 7224 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 7225 Value |= (op & UINT64_C(1)) << 7; 7226 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7227 break; 7228 } 7229 case ARM::VST1d16Q: 7230 case ARM::VST1d32Q: 7231 case ARM::VST1d64Q: 7232 case ARM::VST1d8Q: 7233 case ARM::VST1q16: 7234 case ARM::VST1q32: 7235 case ARM::VST1q64: 7236 case ARM::VST1q8: 7237 case ARM::VST2b16: 7238 case ARM::VST2b32: 7239 case ARM::VST2b8: 7240 case ARM::VST2d16: 7241 case ARM::VST2d32: 7242 case ARM::VST2d8: 7243 case ARM::VST2q16: 7244 case ARM::VST2q32: 7245 case ARM::VST2q8: 7246 case ARM::VST4d16: 7247 case ARM::VST4d32: 7248 case ARM::VST4d8: 7249 case ARM::VST4q16: 7250 case ARM::VST4q32: 7251 case ARM::VST4q8: { 7252 // op: Vd 7253 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7254 Value |= (op & UINT64_C(16)) << 18; 7255 Value |= (op & UINT64_C(15)) << 12; 7256 // op: Rn 7257 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 7258 Value |= (op & UINT64_C(15)) << 16; 7259 Value |= op & UINT64_C(48); 7260 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7261 break; 7262 } 7263 case ARM::VST1LNd32: { 7264 // op: Vd 7265 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7266 Value |= (op & UINT64_C(16)) << 18; 7267 Value |= (op & UINT64_C(15)) << 12; 7268 // op: Rn 7269 op = getAddrMode6OneLane32AddressOpValue(MI, 0, Fixups, STI); 7270 Value |= (op & UINT64_C(15)) << 16; 7271 Value |= op & UINT64_C(48); 7272 // op: lane 7273 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7274 Value |= (op & UINT64_C(1)) << 7; 7275 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7276 break; 7277 } 7278 case ARM::VST1d16wb_fixed: 7279 case ARM::VST1d32wb_fixed: 7280 case ARM::VST1d64wb_fixed: 7281 case ARM::VST1d8wb_fixed: { 7282 // op: Vd 7283 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7284 Value |= (op & UINT64_C(16)) << 18; 7285 Value |= (op & UINT64_C(15)) << 12; 7286 // op: Rn 7287 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7288 Value |= (op & UINT64_C(15)) << 16; 7289 Value |= op & UINT64_C(16); 7290 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7291 break; 7292 } 7293 case ARM::VST1d16Qwb_fixed: 7294 case ARM::VST1d16Twb_fixed: 7295 case ARM::VST1d32Qwb_fixed: 7296 case ARM::VST1d32Twb_fixed: 7297 case ARM::VST1d64Qwb_fixed: 7298 case ARM::VST1d64Twb_fixed: 7299 case ARM::VST1d8Qwb_fixed: 7300 case ARM::VST1d8Twb_fixed: 7301 case ARM::VST1q16wb_fixed: 7302 case ARM::VST1q32wb_fixed: 7303 case ARM::VST1q64wb_fixed: 7304 case ARM::VST1q8wb_fixed: 7305 case ARM::VST2b16wb_fixed: 7306 case ARM::VST2b32wb_fixed: 7307 case ARM::VST2b8wb_fixed: 7308 case ARM::VST2d16wb_fixed: 7309 case ARM::VST2d32wb_fixed: 7310 case ARM::VST2d8wb_fixed: 7311 case ARM::VST2q16wb_fixed: 7312 case ARM::VST2q32wb_fixed: 7313 case ARM::VST2q8wb_fixed: { 7314 // op: Vd 7315 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7316 Value |= (op & UINT64_C(16)) << 18; 7317 Value |= (op & UINT64_C(15)) << 12; 7318 // op: Rn 7319 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7320 Value |= (op & UINT64_C(15)) << 16; 7321 Value |= op & UINT64_C(48); 7322 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7323 break; 7324 } 7325 case ARM::VST1LNd8_UPD: { 7326 // op: Vd 7327 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7328 Value |= (op & UINT64_C(16)) << 18; 7329 Value |= (op & UINT64_C(15)) << 12; 7330 // op: Rn 7331 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7332 Value |= (op & UINT64_C(15)) << 16; 7333 // op: Rm 7334 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 7335 Value |= op & UINT64_C(15); 7336 // op: lane 7337 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 7338 Value |= (op & UINT64_C(7)) << 5; 7339 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7340 break; 7341 } 7342 case ARM::VST3LNd32_UPD: 7343 case ARM::VST3LNq32_UPD: { 7344 // op: Vd 7345 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7346 Value |= (op & UINT64_C(16)) << 18; 7347 Value |= (op & UINT64_C(15)) << 12; 7348 // op: Rn 7349 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7350 Value |= (op & UINT64_C(15)) << 16; 7351 // op: Rm 7352 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 7353 Value |= op & UINT64_C(15); 7354 // op: lane 7355 op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI); 7356 Value |= (op & UINT64_C(1)) << 7; 7357 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7358 break; 7359 } 7360 case ARM::VST3LNd16_UPD: 7361 case ARM::VST3LNq16_UPD: { 7362 // op: Vd 7363 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7364 Value |= (op & UINT64_C(16)) << 18; 7365 Value |= (op & UINT64_C(15)) << 12; 7366 // op: Rn 7367 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7368 Value |= (op & UINT64_C(15)) << 16; 7369 // op: Rm 7370 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 7371 Value |= op & UINT64_C(15); 7372 // op: lane 7373 op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI); 7374 Value |= (op & UINT64_C(3)) << 6; 7375 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7376 break; 7377 } 7378 case ARM::VST3LNd8_UPD: { 7379 // op: Vd 7380 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7381 Value |= (op & UINT64_C(16)) << 18; 7382 Value |= (op & UINT64_C(15)) << 12; 7383 // op: Rn 7384 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7385 Value |= (op & UINT64_C(15)) << 16; 7386 // op: Rm 7387 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 7388 Value |= op & UINT64_C(15); 7389 // op: lane 7390 op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI); 7391 Value |= (op & UINT64_C(7)) << 5; 7392 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7393 break; 7394 } 7395 case ARM::VST1LNd16_UPD: { 7396 // op: Vd 7397 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7398 Value |= (op & UINT64_C(16)) << 18; 7399 Value |= (op & UINT64_C(15)) << 12; 7400 // op: Rn 7401 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7402 Value |= (op & UINT64_C(15)) << 16; 7403 Value |= op & UINT64_C(16); 7404 // op: Rm 7405 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 7406 Value |= op & UINT64_C(15); 7407 // op: lane 7408 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 7409 Value |= (op & UINT64_C(3)) << 6; 7410 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7411 break; 7412 } 7413 case ARM::VST2LNd32_UPD: 7414 case ARM::VST2LNq32_UPD: { 7415 // op: Vd 7416 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7417 Value |= (op & UINT64_C(16)) << 18; 7418 Value |= (op & UINT64_C(15)) << 12; 7419 // op: Rn 7420 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7421 Value |= (op & UINT64_C(15)) << 16; 7422 Value |= op & UINT64_C(16); 7423 // op: Rm 7424 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 7425 Value |= op & UINT64_C(15); 7426 // op: lane 7427 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 7428 Value |= (op & UINT64_C(1)) << 7; 7429 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7430 break; 7431 } 7432 case ARM::VST2LNd16_UPD: 7433 case ARM::VST2LNq16_UPD: { 7434 // op: Vd 7435 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7436 Value |= (op & UINT64_C(16)) << 18; 7437 Value |= (op & UINT64_C(15)) << 12; 7438 // op: Rn 7439 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7440 Value |= (op & UINT64_C(15)) << 16; 7441 Value |= op & UINT64_C(16); 7442 // op: Rm 7443 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 7444 Value |= op & UINT64_C(15); 7445 // op: lane 7446 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 7447 Value |= (op & UINT64_C(3)) << 6; 7448 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7449 break; 7450 } 7451 case ARM::VST2LNd8_UPD: { 7452 // op: Vd 7453 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7454 Value |= (op & UINT64_C(16)) << 18; 7455 Value |= (op & UINT64_C(15)) << 12; 7456 // op: Rn 7457 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7458 Value |= (op & UINT64_C(15)) << 16; 7459 Value |= op & UINT64_C(16); 7460 // op: Rm 7461 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 7462 Value |= op & UINT64_C(15); 7463 // op: lane 7464 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 7465 Value |= (op & UINT64_C(7)) << 5; 7466 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7467 break; 7468 } 7469 case ARM::VST4LNd16_UPD: 7470 case ARM::VST4LNq16_UPD: { 7471 // op: Vd 7472 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7473 Value |= (op & UINT64_C(16)) << 18; 7474 Value |= (op & UINT64_C(15)) << 12; 7475 // op: Rn 7476 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7477 Value |= (op & UINT64_C(15)) << 16; 7478 Value |= op & UINT64_C(16); 7479 // op: Rm 7480 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 7481 Value |= op & UINT64_C(15); 7482 // op: lane 7483 op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 7484 Value |= (op & UINT64_C(3)) << 6; 7485 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7486 break; 7487 } 7488 case ARM::VST4LNd8_UPD: { 7489 // op: Vd 7490 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7491 Value |= (op & UINT64_C(16)) << 18; 7492 Value |= (op & UINT64_C(15)) << 12; 7493 // op: Rn 7494 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7495 Value |= (op & UINT64_C(15)) << 16; 7496 Value |= op & UINT64_C(16); 7497 // op: Rm 7498 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 7499 Value |= op & UINT64_C(15); 7500 // op: lane 7501 op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 7502 Value |= (op & UINT64_C(7)) << 5; 7503 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7504 break; 7505 } 7506 case ARM::VST3d16_UPD: 7507 case ARM::VST3d32_UPD: 7508 case ARM::VST3d8_UPD: 7509 case ARM::VST3q16_UPD: 7510 case ARM::VST3q32_UPD: 7511 case ARM::VST3q8_UPD: { 7512 // op: Vd 7513 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7514 Value |= (op & UINT64_C(16)) << 18; 7515 Value |= (op & UINT64_C(15)) << 12; 7516 // op: Rn 7517 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7518 Value |= (op & UINT64_C(15)) << 16; 7519 Value |= op & UINT64_C(16); 7520 // op: Rm 7521 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 7522 Value |= op & UINT64_C(15); 7523 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7524 break; 7525 } 7526 case ARM::VST1d16wb_register: 7527 case ARM::VST1d32wb_register: 7528 case ARM::VST1d64wb_register: 7529 case ARM::VST1d8wb_register: { 7530 // op: Vd 7531 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7532 Value |= (op & UINT64_C(16)) << 18; 7533 Value |= (op & UINT64_C(15)) << 12; 7534 // op: Rn 7535 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7536 Value |= (op & UINT64_C(15)) << 16; 7537 Value |= op & UINT64_C(16); 7538 // op: Rm 7539 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7540 Value |= op & UINT64_C(15); 7541 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7542 break; 7543 } 7544 case ARM::VST4LNd32_UPD: 7545 case ARM::VST4LNq32_UPD: { 7546 // op: Vd 7547 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7548 Value |= (op & UINT64_C(16)) << 18; 7549 Value |= (op & UINT64_C(15)) << 12; 7550 // op: Rn 7551 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7552 Value |= (op & UINT64_C(15)) << 16; 7553 Value |= op & UINT64_C(48); 7554 // op: Rm 7555 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 7556 Value |= op & UINT64_C(15); 7557 // op: lane 7558 op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 7559 Value |= (op & UINT64_C(1)) << 7; 7560 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7561 break; 7562 } 7563 case ARM::VST4d16_UPD: 7564 case ARM::VST4d32_UPD: 7565 case ARM::VST4d8_UPD: 7566 case ARM::VST4q16_UPD: 7567 case ARM::VST4q32_UPD: 7568 case ARM::VST4q8_UPD: { 7569 // op: Vd 7570 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7571 Value |= (op & UINT64_C(16)) << 18; 7572 Value |= (op & UINT64_C(15)) << 12; 7573 // op: Rn 7574 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7575 Value |= (op & UINT64_C(15)) << 16; 7576 Value |= op & UINT64_C(48); 7577 // op: Rm 7578 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 7579 Value |= op & UINT64_C(15); 7580 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7581 break; 7582 } 7583 case ARM::VST1d16Qwb_register: 7584 case ARM::VST1d16Twb_register: 7585 case ARM::VST1d32Qwb_register: 7586 case ARM::VST1d32Twb_register: 7587 case ARM::VST1d64Qwb_register: 7588 case ARM::VST1d64Twb_register: 7589 case ARM::VST1d8Qwb_register: 7590 case ARM::VST1d8Twb_register: 7591 case ARM::VST1q16wb_register: 7592 case ARM::VST1q32wb_register: 7593 case ARM::VST1q64wb_register: 7594 case ARM::VST1q8wb_register: 7595 case ARM::VST2b16wb_register: 7596 case ARM::VST2b32wb_register: 7597 case ARM::VST2b8wb_register: 7598 case ARM::VST2d16wb_register: 7599 case ARM::VST2d32wb_register: 7600 case ARM::VST2d8wb_register: 7601 case ARM::VST2q16wb_register: 7602 case ARM::VST2q32wb_register: 7603 case ARM::VST2q8wb_register: { 7604 // op: Vd 7605 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7606 Value |= (op & UINT64_C(16)) << 18; 7607 Value |= (op & UINT64_C(15)) << 12; 7608 // op: Rn 7609 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7610 Value |= (op & UINT64_C(15)) << 16; 7611 Value |= op & UINT64_C(48); 7612 // op: Rm 7613 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7614 Value |= op & UINT64_C(15); 7615 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7616 break; 7617 } 7618 case ARM::VST1LNd32_UPD: { 7619 // op: Vd 7620 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7621 Value |= (op & UINT64_C(16)) << 18; 7622 Value |= (op & UINT64_C(15)) << 12; 7623 // op: Rn 7624 op = getAddrMode6OneLane32AddressOpValue(MI, 1, Fixups, STI); 7625 Value |= (op & UINT64_C(15)) << 16; 7626 Value |= op & UINT64_C(48); 7627 // op: Rm 7628 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 7629 Value |= op & UINT64_C(15); 7630 // op: lane 7631 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 7632 Value |= (op & UINT64_C(1)) << 7; 7633 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7634 break; 7635 } 7636 case ARM::LDC2L_OFFSET: 7637 case ARM::LDC2L_PRE: 7638 case ARM::LDC2_OFFSET: 7639 case ARM::LDC2_PRE: 7640 case ARM::STC2L_OFFSET: 7641 case ARM::STC2L_PRE: 7642 case ARM::STC2_OFFSET: 7643 case ARM::STC2_PRE: 7644 case ARM::t2LDC2L_OFFSET: 7645 case ARM::t2LDC2L_PRE: 7646 case ARM::t2LDC2_OFFSET: 7647 case ARM::t2LDC2_PRE: 7648 case ARM::t2LDCL_OFFSET: 7649 case ARM::t2LDCL_PRE: 7650 case ARM::t2LDC_OFFSET: 7651 case ARM::t2LDC_PRE: 7652 case ARM::t2STC2L_OFFSET: 7653 case ARM::t2STC2L_PRE: 7654 case ARM::t2STC2_OFFSET: 7655 case ARM::t2STC2_PRE: 7656 case ARM::t2STCL_OFFSET: 7657 case ARM::t2STCL_PRE: 7658 case ARM::t2STC_OFFSET: 7659 case ARM::t2STC_PRE: { 7660 // op: addr 7661 op = getAddrMode5OpValue(MI, 2, Fixups, STI); 7662 Value |= (op & UINT64_C(256)) << 15; 7663 Value |= (op & UINT64_C(7680)) << 7; 7664 Value |= op & UINT64_C(255); 7665 // op: cop 7666 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7667 Value |= (op & UINT64_C(15)) << 8; 7668 // op: CRd 7669 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7670 Value |= (op & UINT64_C(15)) << 12; 7671 break; 7672 } 7673 case ARM::t2PLDWi12: 7674 case ARM::t2PLDi12: 7675 case ARM::t2PLIi12: { 7676 // op: addr 7677 op = getAddrModeImm12OpValue(MI, 0, Fixups, STI); 7678 Value |= (op & UINT64_C(122880)) << 3; 7679 Value |= op & UINT64_C(4095); 7680 break; 7681 } 7682 case ARM::PLDWi12: 7683 case ARM::PLDi12: 7684 case ARM::PLIi12: { 7685 // op: addr 7686 op = getAddrModeImm12OpValue(MI, 0, Fixups, STI); 7687 Value |= (op & UINT64_C(4096)) << 11; 7688 Value |= (op & UINT64_C(122880)) << 3; 7689 Value |= op & UINT64_C(4095); 7690 break; 7691 } 7692 case ARM::t2PLDpci: 7693 case ARM::t2PLIpci: { 7694 // op: addr 7695 op = getAddrModeImm12OpValue(MI, 0, Fixups, STI); 7696 Value |= (op & UINT64_C(4096)) << 11; 7697 Value |= op & UINT64_C(4095); 7698 break; 7699 } 7700 case ARM::t2LDAEXB: 7701 case ARM::t2LDAEXH: 7702 case ARM::t2LDREXB: 7703 case ARM::t2LDREXH: { 7704 // op: addr 7705 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7706 Value |= (op & UINT64_C(15)) << 16; 7707 // op: Rt 7708 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7709 Value |= (op & UINT64_C(15)) << 12; 7710 break; 7711 } 7712 case ARM::t2LDAEXD: 7713 case ARM::t2LDREXD: { 7714 // op: addr 7715 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7716 Value |= (op & UINT64_C(15)) << 16; 7717 // op: Rt 7718 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7719 Value |= (op & UINT64_C(15)) << 12; 7720 // op: Rt2 7721 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7722 Value |= (op & UINT64_C(15)) << 8; 7723 break; 7724 } 7725 case ARM::t2PLDWi8: 7726 case ARM::t2PLDi8: 7727 case ARM::t2PLIi8: { 7728 // op: addr 7729 op = getT2AddrModeImm8OpValue(MI, 0, Fixups, STI); 7730 Value |= (op & UINT64_C(7680)) << 7; 7731 Value |= op & UINT64_C(255); 7732 break; 7733 } 7734 case ARM::t2PLDWs: 7735 case ARM::t2PLDs: 7736 case ARM::t2PLIs: { 7737 // op: addr 7738 op = getT2AddrModeSORegOpValue(MI, 0, Fixups, STI); 7739 Value |= (op & UINT64_C(960)) << 10; 7740 Value |= (op & UINT64_C(3)) << 4; 7741 Value |= (op & UINT64_C(60)) >> 2; 7742 break; 7743 } 7744 case ARM::t2MSRbanked: { 7745 // op: banked 7746 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7747 Value |= (op & UINT64_C(32)) << 15; 7748 Value |= (op & UINT64_C(15)) << 8; 7749 Value |= op & UINT64_C(16); 7750 // op: Rn 7751 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7752 Value |= (op & UINT64_C(15)) << 16; 7753 break; 7754 } 7755 case ARM::t2MRSbanked: { 7756 // op: banked 7757 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7758 Value |= (op & UINT64_C(32)) << 15; 7759 Value |= (op & UINT64_C(15)) << 16; 7760 Value |= op & UINT64_C(16); 7761 // op: Rd 7762 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7763 Value |= (op & UINT64_C(15)) << 8; 7764 break; 7765 } 7766 case ARM::t2IT: { 7767 // op: cc 7768 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7769 Value |= (op & UINT64_C(15)) << 4; 7770 // op: mask 7771 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7772 Value |= op & UINT64_C(15); 7773 break; 7774 } 7775 case ARM::tADDrSPi: { 7776 // op: dst 7777 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7778 Value |= (op & UINT64_C(7)) << 8; 7779 // op: imm 7780 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7781 Value |= op & UINT64_C(255); 7782 break; 7783 } 7784 case ARM::BX: { 7785 // op: dst 7786 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7787 Value |= op & UINT64_C(15); 7788 break; 7789 } 7790 case ARM::tPICADD: { 7791 // op: dst 7792 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7793 Value |= op & UINT64_C(7); 7794 break; 7795 } 7796 case ARM::tSETEND: { 7797 // op: end 7798 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7799 Value |= (op & UINT64_C(1)) << 3; 7800 break; 7801 } 7802 case ARM::SETEND: { 7803 // op: end 7804 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7805 Value |= (op & UINT64_C(1)) << 9; 7806 break; 7807 } 7808 case ARM::BL: { 7809 // op: func 7810 op = getARMBLTargetOpValue(MI, 0, Fixups, STI); 7811 Value |= op & UINT64_C(16777215); 7812 break; 7813 } 7814 case ARM::t2BXJ: { 7815 // op: func 7816 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7817 Value |= (op & UINT64_C(15)) << 16; 7818 break; 7819 } 7820 case ARM::BLX: { 7821 // op: func 7822 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7823 Value |= op & UINT64_C(15); 7824 break; 7825 } 7826 case ARM::tBLXNSr: 7827 case ARM::tBLXr: { 7828 // op: func 7829 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7830 Value |= (op & UINT64_C(15)) << 3; 7831 break; 7832 } 7833 case ARM::tBL: { 7834 // op: func 7835 op = getThumbBLTargetOpValue(MI, 2, Fixups, STI); 7836 Value |= (op & UINT64_C(8388608)) << 3; 7837 Value |= (op & UINT64_C(2095104)) << 5; 7838 Value |= (op & UINT64_C(4194304)) >> 9; 7839 Value |= (op & UINT64_C(2097152)) >> 10; 7840 Value |= op & UINT64_C(2047); 7841 break; 7842 } 7843 case ARM::tBLXi: { 7844 // op: func 7845 op = getThumbBLXTargetOpValue(MI, 2, Fixups, STI); 7846 Value |= (op & UINT64_C(8388608)) << 3; 7847 Value |= (op & UINT64_C(2095104)) << 5; 7848 Value |= (op & UINT64_C(4194304)) >> 9; 7849 Value |= (op & UINT64_C(2097152)) >> 10; 7850 Value |= op & UINT64_C(2046); 7851 break; 7852 } 7853 case ARM::t2SETPAN: { 7854 // op: imm 7855 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7856 Value |= (op & UINT64_C(1)) << 3; 7857 break; 7858 } 7859 case ARM::SETPAN: { 7860 // op: imm 7861 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7862 Value |= (op & UINT64_C(1)) << 9; 7863 break; 7864 } 7865 case ARM::tHINT: { 7866 // op: imm 7867 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7868 Value |= (op & UINT64_C(15)) << 4; 7869 break; 7870 } 7871 case ARM::HVC: { 7872 // op: imm 7873 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7874 Value |= (op & UINT64_C(65520)) << 4; 7875 Value |= op & UINT64_C(15); 7876 break; 7877 } 7878 case ARM::t2HINT: 7879 case ARM::t2SUBS_PC_LR: 7880 case ARM::tSVC: { 7881 // op: imm 7882 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7883 Value |= op & UINT64_C(255); 7884 break; 7885 } 7886 case ARM::tADDspi: 7887 case ARM::tSUBspi: { 7888 // op: imm 7889 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7890 Value |= op & UINT64_C(127); 7891 break; 7892 } 7893 case ARM::t2HVC: 7894 case ARM::t2UDF: { 7895 // op: imm16 7896 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7897 Value |= (op & UINT64_C(61440)) << 4; 7898 Value |= op & UINT64_C(4095); 7899 break; 7900 } 7901 case ARM::UDF: { 7902 // op: imm16 7903 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7904 Value |= (op & UINT64_C(65520)) << 4; 7905 Value |= op & UINT64_C(15); 7906 break; 7907 } 7908 case ARM::tUDF: { 7909 // op: imm8 7910 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7911 Value |= op & UINT64_C(255); 7912 break; 7913 } 7914 case ARM::tCPS: { 7915 // op: imod 7916 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7917 Value |= (op & UINT64_C(1)) << 4; 7918 // op: iflags 7919 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7920 Value |= op & UINT64_C(7); 7921 break; 7922 } 7923 case ARM::CPS2p: { 7924 // op: imod 7925 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7926 Value |= (op & UINT64_C(3)) << 18; 7927 // op: iflags 7928 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7929 Value |= (op & UINT64_C(7)) << 6; 7930 break; 7931 } 7932 case ARM::CPS3p: { 7933 // op: imod 7934 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7935 Value |= (op & UINT64_C(3)) << 18; 7936 // op: iflags 7937 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7938 Value |= (op & UINT64_C(7)) << 6; 7939 // op: mode 7940 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7941 Value |= op & UINT64_C(31); 7942 break; 7943 } 7944 case ARM::t2CPS2p: { 7945 // op: imod 7946 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7947 Value |= (op & UINT64_C(3)) << 9; 7948 // op: iflags 7949 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7950 Value |= (op & UINT64_C(7)) << 5; 7951 break; 7952 } 7953 case ARM::t2CPS3p: { 7954 // op: imod 7955 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7956 Value |= (op & UINT64_C(3)) << 9; 7957 // op: iflags 7958 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7959 Value |= (op & UINT64_C(7)) << 5; 7960 // op: mode 7961 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7962 Value |= op & UINT64_C(31); 7963 break; 7964 } 7965 case ARM::t2MSR_AR: { 7966 // op: mask 7967 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7968 Value |= (op & UINT64_C(16)) << 16; 7969 Value |= (op & UINT64_C(15)) << 8; 7970 // op: Rn 7971 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7972 Value |= (op & UINT64_C(15)) << 16; 7973 break; 7974 } 7975 case ARM::CPS1p: 7976 case ARM::SRSDA: 7977 case ARM::SRSDA_UPD: 7978 case ARM::SRSDB: 7979 case ARM::SRSDB_UPD: 7980 case ARM::SRSIA: 7981 case ARM::SRSIA_UPD: 7982 case ARM::SRSIB: 7983 case ARM::SRSIB_UPD: 7984 case ARM::t2CPS1p: 7985 case ARM::t2SRSDB: 7986 case ARM::t2SRSDB_UPD: 7987 case ARM::t2SRSIA: 7988 case ARM::t2SRSIA_UPD: { 7989 // op: mode 7990 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7991 Value |= op & UINT64_C(31); 7992 break; 7993 } 7994 case ARM::LDC2L_POST: 7995 case ARM::LDC2_POST: 7996 case ARM::STC2L_POST: 7997 case ARM::STC2_POST: 7998 case ARM::t2LDC2L_POST: 7999 case ARM::t2LDC2_POST: 8000 case ARM::t2LDCL_POST: 8001 case ARM::t2LDC_POST: 8002 case ARM::t2STC2L_POST: 8003 case ARM::t2STC2_POST: 8004 case ARM::t2STCL_POST: 8005 case ARM::t2STC_POST: { 8006 // op: offset 8007 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8008 Value |= (op & UINT64_C(256)) << 15; 8009 Value |= op & UINT64_C(255); 8010 // op: addr 8011 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8012 Value |= (op & UINT64_C(15)) << 16; 8013 // op: cop 8014 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8015 Value |= (op & UINT64_C(15)) << 8; 8016 // op: CRd 8017 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8018 Value |= (op & UINT64_C(15)) << 12; 8019 break; 8020 } 8021 case ARM::CDP2: 8022 case ARM::t2CDP: 8023 case ARM::t2CDP2: { 8024 // op: opc1 8025 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8026 Value |= (op & UINT64_C(15)) << 20; 8027 // op: CRn 8028 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8029 Value |= (op & UINT64_C(15)) << 16; 8030 // op: CRd 8031 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8032 Value |= (op & UINT64_C(15)) << 12; 8033 // op: cop 8034 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8035 Value |= (op & UINT64_C(15)) << 8; 8036 // op: opc2 8037 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 8038 Value |= (op & UINT64_C(7)) << 5; 8039 // op: CRm 8040 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 8041 Value |= op & UINT64_C(15); 8042 break; 8043 } 8044 case ARM::t2SMC: { 8045 // op: opt 8046 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8047 Value |= (op & UINT64_C(15)) << 16; 8048 break; 8049 } 8050 case ARM::DMB: 8051 case ARM::DSB: 8052 case ARM::ISB: 8053 case ARM::t2DBG: 8054 case ARM::t2DMB: 8055 case ARM::t2DSB: 8056 case ARM::t2ISB: { 8057 // op: opt 8058 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8059 Value |= op & UINT64_C(15); 8060 break; 8061 } 8062 case ARM::LDC2L_OPTION: 8063 case ARM::LDC2_OPTION: 8064 case ARM::STC2L_OPTION: 8065 case ARM::STC2_OPTION: 8066 case ARM::t2LDC2L_OPTION: 8067 case ARM::t2LDC2_OPTION: 8068 case ARM::t2LDCL_OPTION: 8069 case ARM::t2LDC_OPTION: 8070 case ARM::t2STC2L_OPTION: 8071 case ARM::t2STC2_OPTION: 8072 case ARM::t2STCL_OPTION: 8073 case ARM::t2STC_OPTION: { 8074 // op: option 8075 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8076 Value |= op & UINT64_C(255); 8077 // op: addr 8078 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8079 Value |= (op & UINT64_C(15)) << 16; 8080 // op: cop 8081 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8082 Value |= (op & UINT64_C(15)) << 8; 8083 // op: CRd 8084 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8085 Value |= (op & UINT64_C(15)) << 12; 8086 break; 8087 } 8088 case ARM::BX_RET: 8089 case ARM::ERET: 8090 case ARM::MOVPCLR: { 8091 // op: p 8092 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8093 Value |= (op & UINT64_C(15)) << 28; 8094 break; 8095 } 8096 case ARM::FMSTAT: { 8097 // op: p 8098 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8099 Value |= (op & UINT64_C(15)) << 28; 8100 Value = VFPThumb2PostEncoder(MI, Value, STI); 8101 break; 8102 } 8103 case ARM::t2Bcc: { 8104 // op: p 8105 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8106 Value |= (op & UINT64_C(15)) << 22; 8107 // op: target 8108 op = getBranchTargetOpValue(MI, 0, Fixups, STI); 8109 Value |= (op & UINT64_C(1048576)) << 6; 8110 Value |= (op & UINT64_C(258048)) << 4; 8111 Value |= (op & UINT64_C(262144)) >> 5; 8112 Value |= (op & UINT64_C(524288)) >> 8; 8113 Value |= (op & UINT64_C(4094)) >> 1; 8114 break; 8115 } 8116 case ARM::VCMPEZD: 8117 case ARM::VCMPZD: { 8118 // op: p 8119 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8120 Value |= (op & UINT64_C(15)) << 28; 8121 // op: Dd 8122 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8123 Value |= (op & UINT64_C(16)) << 18; 8124 Value |= (op & UINT64_C(15)) << 12; 8125 Value = VFPThumb2PostEncoder(MI, Value, STI); 8126 break; 8127 } 8128 case ARM::MRS: 8129 case ARM::MRSsys: { 8130 // op: p 8131 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8132 Value |= (op & UINT64_C(15)) << 28; 8133 // op: Rd 8134 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8135 Value |= (op & UINT64_C(15)) << 12; 8136 break; 8137 } 8138 case ARM::VLDMSIA: 8139 case ARM::VSTMSIA: { 8140 // op: p 8141 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8142 Value |= (op & UINT64_C(15)) << 28; 8143 // op: Rn 8144 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8145 Value |= (op & UINT64_C(15)) << 16; 8146 // op: regs 8147 op = getRegisterListOpValue(MI, 3, Fixups, STI); 8148 Value |= (op & UINT64_C(256)) << 14; 8149 Value |= (op & UINT64_C(7680)) << 3; 8150 Value |= op & UINT64_C(255); 8151 Value = VFPThumb2PostEncoder(MI, Value, STI); 8152 break; 8153 } 8154 case ARM::FLDMXIA: 8155 case ARM::FSTMXIA: { 8156 // op: p 8157 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8158 Value |= (op & UINT64_C(15)) << 28; 8159 // op: Rn 8160 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8161 Value |= (op & UINT64_C(15)) << 16; 8162 // op: regs 8163 op = getRegisterListOpValue(MI, 3, Fixups, STI); 8164 Value |= (op & UINT64_C(3840)) << 4; 8165 Value |= op & UINT64_C(254); 8166 Value = VFPThumb2PostEncoder(MI, Value, STI); 8167 break; 8168 } 8169 case ARM::VLDMDIA: 8170 case ARM::VSTMDIA: { 8171 // op: p 8172 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8173 Value |= (op & UINT64_C(15)) << 28; 8174 // op: Rn 8175 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8176 Value |= (op & UINT64_C(15)) << 16; 8177 // op: regs 8178 op = getRegisterListOpValue(MI, 3, Fixups, STI); 8179 Value |= (op & UINT64_C(4096)) << 10; 8180 Value |= (op & UINT64_C(3840)) << 4; 8181 Value |= op & UINT64_C(254); 8182 Value = VFPThumb2PostEncoder(MI, Value, STI); 8183 break; 8184 } 8185 case ARM::VLLDM: 8186 case ARM::VLSTM: { 8187 // op: p 8188 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8189 Value |= (op & UINT64_C(15)) << 28; 8190 // op: Rn 8191 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8192 Value |= (op & UINT64_C(15)) << 16; 8193 Value = VFPThumb2PostEncoder(MI, Value, STI); 8194 break; 8195 } 8196 case ARM::VMRS: 8197 case ARM::VMRS_FPEXC: 8198 case ARM::VMRS_FPINST: 8199 case ARM::VMRS_FPINST2: 8200 case ARM::VMRS_FPSID: 8201 case ARM::VMRS_MVFR0: 8202 case ARM::VMRS_MVFR1: 8203 case ARM::VMRS_MVFR2: { 8204 // op: p 8205 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8206 Value |= (op & UINT64_C(15)) << 28; 8207 // op: Rt 8208 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8209 Value |= (op & UINT64_C(15)) << 12; 8210 Value = VFPThumb2PostEncoder(MI, Value, STI); 8211 break; 8212 } 8213 case ARM::VCMPEZH: 8214 case ARM::VCMPEZS: 8215 case ARM::VCMPZH: 8216 case ARM::VCMPZS: { 8217 // op: p 8218 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8219 Value |= (op & UINT64_C(15)) << 28; 8220 // op: Sd 8221 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8222 Value |= (op & UINT64_C(1)) << 22; 8223 Value |= (op & UINT64_C(30)) << 11; 8224 Value = VFPThumb2PostEncoder(MI, Value, STI); 8225 break; 8226 } 8227 case ARM::BX_pred: { 8228 // op: p 8229 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8230 Value |= (op & UINT64_C(15)) << 28; 8231 // op: dst 8232 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8233 Value |= op & UINT64_C(15); 8234 break; 8235 } 8236 case ARM::BL_pred: { 8237 // op: p 8238 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8239 Value |= (op & UINT64_C(15)) << 28; 8240 // op: func 8241 op = getARMBLTargetOpValue(MI, 0, Fixups, STI); 8242 Value |= op & UINT64_C(16777215); 8243 break; 8244 } 8245 case ARM::BLX_pred: 8246 case ARM::BXJ: { 8247 // op: p 8248 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8249 Value |= (op & UINT64_C(15)) << 28; 8250 // op: func 8251 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8252 Value |= op & UINT64_C(15); 8253 break; 8254 } 8255 case ARM::HINT: { 8256 // op: p 8257 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8258 Value |= (op & UINT64_C(15)) << 28; 8259 // op: imm 8260 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8261 Value |= op & UINT64_C(255); 8262 break; 8263 } 8264 case ARM::DBG: 8265 case ARM::SMC: { 8266 // op: p 8267 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8268 Value |= (op & UINT64_C(15)) << 28; 8269 // op: opt 8270 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8271 Value |= op & UINT64_C(15); 8272 break; 8273 } 8274 case ARM::LDMDA: 8275 case ARM::LDMDB: 8276 case ARM::LDMIA: 8277 case ARM::LDMIB: 8278 case ARM::STMDA: 8279 case ARM::STMDB: 8280 case ARM::STMIA: 8281 case ARM::STMIB: 8282 case ARM::sysLDMDA: 8283 case ARM::sysLDMDB: 8284 case ARM::sysLDMIA: 8285 case ARM::sysLDMIB: 8286 case ARM::sysSTMDA: 8287 case ARM::sysSTMDB: 8288 case ARM::sysSTMIA: 8289 case ARM::sysSTMIB: { 8290 // op: p 8291 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8292 Value |= (op & UINT64_C(15)) << 28; 8293 // op: regs 8294 op = getRegisterListOpValue(MI, 3, Fixups, STI); 8295 Value |= op & UINT64_C(65535); 8296 // op: Rn 8297 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8298 Value |= (op & UINT64_C(15)) << 16; 8299 break; 8300 } 8301 case ARM::VMSR: 8302 case ARM::VMSR_FPEXC: 8303 case ARM::VMSR_FPINST: 8304 case ARM::VMSR_FPINST2: 8305 case ARM::VMSR_FPSID: { 8306 // op: p 8307 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8308 Value |= (op & UINT64_C(15)) << 28; 8309 // op: src 8310 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8311 Value |= (op & UINT64_C(15)) << 12; 8312 Value = VFPThumb2PostEncoder(MI, Value, STI); 8313 break; 8314 } 8315 case ARM::SVC: { 8316 // op: p 8317 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8318 Value |= (op & UINT64_C(15)) << 28; 8319 // op: svc 8320 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8321 Value |= op & UINT64_C(16777215); 8322 break; 8323 } 8324 case ARM::Bcc: { 8325 // op: p 8326 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8327 Value |= (op & UINT64_C(15)) << 28; 8328 // op: target 8329 op = getARMBranchTargetOpValue(MI, 0, Fixups, STI); 8330 Value |= op & UINT64_C(16777215); 8331 break; 8332 } 8333 case ARM::tBcc: { 8334 // op: p 8335 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8336 Value |= (op & UINT64_C(15)) << 8; 8337 // op: target 8338 op = getThumbBCCTargetOpValue(MI, 0, Fixups, STI); 8339 Value |= op & UINT64_C(255); 8340 break; 8341 } 8342 case ARM::VABSD: 8343 case ARM::VCMPD: 8344 case ARM::VCMPED: 8345 case ARM::VMOVD: 8346 case ARM::VNEGD: 8347 case ARM::VRINTRD: 8348 case ARM::VRINTXD: 8349 case ARM::VRINTZD: 8350 case ARM::VSQRTD: { 8351 // op: p 8352 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8353 Value |= (op & UINT64_C(15)) << 28; 8354 // op: Dd 8355 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8356 Value |= (op & UINT64_C(16)) << 18; 8357 Value |= (op & UINT64_C(15)) << 12; 8358 // op: Dm 8359 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8360 Value |= (op & UINT64_C(16)) << 1; 8361 Value |= op & UINT64_C(15); 8362 Value = VFPThumb2PostEncoder(MI, Value, STI); 8363 break; 8364 } 8365 case ARM::VCVTBHD: 8366 case ARM::VCVTTHD: 8367 case ARM::VSITOD: 8368 case ARM::VUITOD: { 8369 // op: p 8370 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8371 Value |= (op & UINT64_C(15)) << 28; 8372 // op: Dd 8373 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8374 Value |= (op & UINT64_C(16)) << 18; 8375 Value |= (op & UINT64_C(15)) << 12; 8376 // op: Sm 8377 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8378 Value |= (op & UINT64_C(1)) << 5; 8379 Value |= (op & UINT64_C(30)) >> 1; 8380 Value = VFPThumb2PostEncoder(MI, Value, STI); 8381 break; 8382 } 8383 case ARM::FCONSTD: { 8384 // op: p 8385 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8386 Value |= (op & UINT64_C(15)) << 28; 8387 // op: Dd 8388 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8389 Value |= (op & UINT64_C(16)) << 18; 8390 Value |= (op & UINT64_C(15)) << 12; 8391 // op: imm 8392 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8393 Value |= (op & UINT64_C(240)) << 12; 8394 Value |= op & UINT64_C(15); 8395 Value = VFPThumb2PostEncoder(MI, Value, STI); 8396 break; 8397 } 8398 case ARM::VCVTBDH: 8399 case ARM::VCVTTDH: { 8400 // op: p 8401 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8402 Value |= (op & UINT64_C(15)) << 28; 8403 // op: Dm 8404 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8405 Value |= (op & UINT64_C(16)) << 1; 8406 Value |= op & UINT64_C(15); 8407 // op: Sd 8408 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8409 Value |= (op & UINT64_C(1)) << 22; 8410 Value |= (op & UINT64_C(30)) << 11; 8411 Value = VFPThumb2PostEncoder(MI, Value, STI); 8412 break; 8413 } 8414 case ARM::CLZ: 8415 case ARM::RBIT: 8416 case ARM::REV: 8417 case ARM::REV16: 8418 case ARM::REVSH: { 8419 // op: p 8420 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8421 Value |= (op & UINT64_C(15)) << 28; 8422 // op: Rd 8423 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8424 Value |= (op & UINT64_C(15)) << 12; 8425 // op: Rm 8426 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8427 Value |= op & UINT64_C(15); 8428 break; 8429 } 8430 case ARM::MOVi16: { 8431 // op: p 8432 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8433 Value |= (op & UINT64_C(15)) << 28; 8434 // op: Rd 8435 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8436 Value |= (op & UINT64_C(15)) << 12; 8437 // op: imm 8438 op = getHiLo16ImmOpValue(MI, 1, Fixups, STI); 8439 Value |= (op & UINT64_C(61440)) << 4; 8440 Value |= op & UINT64_C(4095); 8441 break; 8442 } 8443 case ARM::ADR: { 8444 // op: p 8445 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8446 Value |= (op & UINT64_C(15)) << 28; 8447 // op: Rd 8448 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8449 Value |= (op & UINT64_C(15)) << 12; 8450 // op: label 8451 op = getAdrLabelOpValue(MI, 1, Fixups, STI); 8452 Value |= (op & UINT64_C(12288)) << 10; 8453 Value |= op & UINT64_C(4095); 8454 break; 8455 } 8456 case ARM::CMNzrr: 8457 case ARM::CMPrr: 8458 case ARM::TEQrr: 8459 case ARM::TSTrr: { 8460 // op: p 8461 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8462 Value |= (op & UINT64_C(15)) << 28; 8463 // op: Rn 8464 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8465 Value |= (op & UINT64_C(15)) << 16; 8466 // op: Rm 8467 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8468 Value |= op & UINT64_C(15); 8469 break; 8470 } 8471 case ARM::CMNri: 8472 case ARM::CMPri: 8473 case ARM::TEQri: 8474 case ARM::TSTri: { 8475 // op: p 8476 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8477 Value |= (op & UINT64_C(15)) << 28; 8478 // op: Rn 8479 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8480 Value |= (op & UINT64_C(15)) << 16; 8481 // op: imm 8482 op = getModImmOpValue(MI, 1, Fixups, STI); 8483 Value |= op & UINT64_C(4095); 8484 break; 8485 } 8486 case ARM::VLDMSDB_UPD: 8487 case ARM::VLDMSIA_UPD: 8488 case ARM::VSTMSDB_UPD: 8489 case ARM::VSTMSIA_UPD: { 8490 // op: p 8491 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8492 Value |= (op & UINT64_C(15)) << 28; 8493 // op: Rn 8494 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8495 Value |= (op & UINT64_C(15)) << 16; 8496 // op: regs 8497 op = getRegisterListOpValue(MI, 4, Fixups, STI); 8498 Value |= (op & UINT64_C(256)) << 14; 8499 Value |= (op & UINT64_C(7680)) << 3; 8500 Value |= op & UINT64_C(255); 8501 Value = VFPThumb2PostEncoder(MI, Value, STI); 8502 break; 8503 } 8504 case ARM::FLDMXDB_UPD: 8505 case ARM::FLDMXIA_UPD: 8506 case ARM::FSTMXDB_UPD: 8507 case ARM::FSTMXIA_UPD: { 8508 // op: p 8509 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8510 Value |= (op & UINT64_C(15)) << 28; 8511 // op: Rn 8512 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8513 Value |= (op & UINT64_C(15)) << 16; 8514 // op: regs 8515 op = getRegisterListOpValue(MI, 4, Fixups, STI); 8516 Value |= (op & UINT64_C(3840)) << 4; 8517 Value |= op & UINT64_C(254); 8518 Value = VFPThumb2PostEncoder(MI, Value, STI); 8519 break; 8520 } 8521 case ARM::VLDMDDB_UPD: 8522 case ARM::VLDMDIA_UPD: 8523 case ARM::VSTMDDB_UPD: 8524 case ARM::VSTMDIA_UPD: { 8525 // op: p 8526 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8527 Value |= (op & UINT64_C(15)) << 28; 8528 // op: Rn 8529 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8530 Value |= (op & UINT64_C(15)) << 16; 8531 // op: regs 8532 op = getRegisterListOpValue(MI, 4, Fixups, STI); 8533 Value |= (op & UINT64_C(4096)) << 10; 8534 Value |= (op & UINT64_C(3840)) << 4; 8535 Value |= op & UINT64_C(254); 8536 Value = VFPThumb2PostEncoder(MI, Value, STI); 8537 break; 8538 } 8539 case ARM::VMOVRH: 8540 case ARM::VMOVRS: { 8541 // op: p 8542 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8543 Value |= (op & UINT64_C(15)) << 28; 8544 // op: Rt 8545 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8546 Value |= (op & UINT64_C(15)) << 12; 8547 // op: Sn 8548 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8549 Value |= (op & UINT64_C(30)) << 15; 8550 Value |= (op & UINT64_C(1)) << 7; 8551 Value = VFPThumb2PostEncoder(MI, Value, STI); 8552 break; 8553 } 8554 case ARM::LDA: 8555 case ARM::LDAB: 8556 case ARM::LDAEX: 8557 case ARM::LDAEXB: 8558 case ARM::LDAEXD: 8559 case ARM::LDAEXH: 8560 case ARM::LDAH: 8561 case ARM::LDREX: 8562 case ARM::LDREXB: 8563 case ARM::LDREXD: 8564 case ARM::LDREXH: { 8565 // op: p 8566 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8567 Value |= (op & UINT64_C(15)) << 28; 8568 // op: Rt 8569 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8570 Value |= (op & UINT64_C(15)) << 12; 8571 // op: addr 8572 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8573 Value |= (op & UINT64_C(15)) << 16; 8574 break; 8575 } 8576 case ARM::STL: 8577 case ARM::STLB: 8578 case ARM::STLH: { 8579 // op: p 8580 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8581 Value |= (op & UINT64_C(15)) << 28; 8582 // op: Rt 8583 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8584 Value |= op & UINT64_C(15); 8585 // op: addr 8586 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8587 Value |= (op & UINT64_C(15)) << 16; 8588 break; 8589 } 8590 case ARM::VCVTSD: 8591 case ARM::VTOSIRD: 8592 case ARM::VTOSIZD: 8593 case ARM::VTOUIRD: 8594 case ARM::VTOUIZD: { 8595 // op: p 8596 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8597 Value |= (op & UINT64_C(15)) << 28; 8598 // op: Sd 8599 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8600 Value |= (op & UINT64_C(1)) << 22; 8601 Value |= (op & UINT64_C(30)) << 11; 8602 // op: Dm 8603 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8604 Value |= (op & UINT64_C(16)) << 1; 8605 Value |= op & UINT64_C(15); 8606 Value = VFPThumb2PostEncoder(MI, Value, STI); 8607 break; 8608 } 8609 case ARM::VABSH: 8610 case ARM::VABSS: 8611 case ARM::VCMPEH: 8612 case ARM::VCMPES: 8613 case ARM::VCMPH: 8614 case ARM::VCMPS: 8615 case ARM::VCVTBHS: 8616 case ARM::VCVTBSH: 8617 case ARM::VCVTTHS: 8618 case ARM::VCVTTSH: 8619 case ARM::VMOVS: 8620 case ARM::VNEGH: 8621 case ARM::VNEGS: 8622 case ARM::VRINTRH: 8623 case ARM::VRINTRS: 8624 case ARM::VRINTXH: 8625 case ARM::VRINTXS: 8626 case ARM::VRINTZH: 8627 case ARM::VRINTZS: 8628 case ARM::VSITOH: 8629 case ARM::VSITOS: 8630 case ARM::VSQRTH: 8631 case ARM::VSQRTS: 8632 case ARM::VTOSIRH: 8633 case ARM::VTOSIRS: 8634 case ARM::VTOSIZH: 8635 case ARM::VTOSIZS: 8636 case ARM::VTOUIRH: 8637 case ARM::VTOUIRS: 8638 case ARM::VTOUIZH: 8639 case ARM::VTOUIZS: 8640 case ARM::VUITOH: 8641 case ARM::VUITOS: { 8642 // op: p 8643 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8644 Value |= (op & UINT64_C(15)) << 28; 8645 // op: Sd 8646 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8647 Value |= (op & UINT64_C(1)) << 22; 8648 Value |= (op & UINT64_C(30)) << 11; 8649 // op: Sm 8650 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8651 Value |= (op & UINT64_C(1)) << 5; 8652 Value |= (op & UINT64_C(30)) >> 1; 8653 Value = VFPThumb2PostEncoder(MI, Value, STI); 8654 break; 8655 } 8656 case ARM::FCONSTH: 8657 case ARM::FCONSTS: { 8658 // op: p 8659 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8660 Value |= (op & UINT64_C(15)) << 28; 8661 // op: Sd 8662 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8663 Value |= (op & UINT64_C(1)) << 22; 8664 Value |= (op & UINT64_C(30)) << 11; 8665 // op: imm 8666 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8667 Value |= (op & UINT64_C(240)) << 12; 8668 Value |= op & UINT64_C(15); 8669 Value = VFPThumb2PostEncoder(MI, Value, STI); 8670 break; 8671 } 8672 case ARM::VCVTDS: { 8673 // op: p 8674 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8675 Value |= (op & UINT64_C(15)) << 28; 8676 // op: Sm 8677 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8678 Value |= (op & UINT64_C(1)) << 5; 8679 Value |= (op & UINT64_C(30)) >> 1; 8680 // op: Dd 8681 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8682 Value |= (op & UINT64_C(16)) << 18; 8683 Value |= (op & UINT64_C(15)) << 12; 8684 Value = VFPThumb2PostEncoder(MI, Value, STI); 8685 break; 8686 } 8687 case ARM::VMOVHR: 8688 case ARM::VMOVSR: { 8689 // op: p 8690 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8691 Value |= (op & UINT64_C(15)) << 28; 8692 // op: Sn 8693 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8694 Value |= (op & UINT64_C(30)) << 15; 8695 Value |= (op & UINT64_C(1)) << 7; 8696 // op: Rt 8697 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8698 Value |= (op & UINT64_C(15)) << 12; 8699 Value = VFPThumb2PostEncoder(MI, Value, STI); 8700 break; 8701 } 8702 case ARM::MSRbanked: { 8703 // op: p 8704 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8705 Value |= (op & UINT64_C(15)) << 28; 8706 // op: banked 8707 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8708 Value |= (op & UINT64_C(32)) << 17; 8709 Value |= (op & UINT64_C(15)) << 16; 8710 Value |= (op & UINT64_C(16)) << 4; 8711 // op: Rn 8712 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8713 Value |= op & UINT64_C(15); 8714 break; 8715 } 8716 case ARM::MRSbanked: { 8717 // op: p 8718 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8719 Value |= (op & UINT64_C(15)) << 28; 8720 // op: banked 8721 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8722 Value |= (op & UINT64_C(32)) << 17; 8723 Value |= (op & UINT64_C(15)) << 16; 8724 Value |= (op & UINT64_C(16)) << 4; 8725 // op: Rd 8726 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8727 Value |= (op & UINT64_C(15)) << 12; 8728 break; 8729 } 8730 case ARM::MSR: { 8731 // op: p 8732 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8733 Value |= (op & UINT64_C(15)) << 28; 8734 // op: mask 8735 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8736 Value |= (op & UINT64_C(16)) << 18; 8737 Value |= (op & UINT64_C(15)) << 16; 8738 // op: Rn 8739 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8740 Value |= op & UINT64_C(15); 8741 break; 8742 } 8743 case ARM::MSRi: { 8744 // op: p 8745 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8746 Value |= (op & UINT64_C(15)) << 28; 8747 // op: mask 8748 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8749 Value |= (op & UINT64_C(16)) << 18; 8750 Value |= (op & UINT64_C(15)) << 16; 8751 // op: imm 8752 op = getModImmOpValue(MI, 1, Fixups, STI); 8753 Value |= op & UINT64_C(4095); 8754 break; 8755 } 8756 case ARM::LDMDA_UPD: 8757 case ARM::LDMDB_UPD: 8758 case ARM::LDMIA_UPD: 8759 case ARM::LDMIB_UPD: 8760 case ARM::STMDA_UPD: 8761 case ARM::STMDB_UPD: 8762 case ARM::STMIA_UPD: 8763 case ARM::STMIB_UPD: 8764 case ARM::sysLDMDA_UPD: 8765 case ARM::sysLDMDB_UPD: 8766 case ARM::sysLDMIA_UPD: 8767 case ARM::sysLDMIB_UPD: 8768 case ARM::sysSTMDA_UPD: 8769 case ARM::sysSTMDB_UPD: 8770 case ARM::sysSTMIA_UPD: 8771 case ARM::sysSTMIB_UPD: { 8772 // op: p 8773 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8774 Value |= (op & UINT64_C(15)) << 28; 8775 // op: regs 8776 op = getRegisterListOpValue(MI, 4, Fixups, STI); 8777 Value |= op & UINT64_C(65535); 8778 // op: Rn 8779 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8780 Value |= (op & UINT64_C(15)) << 16; 8781 break; 8782 } 8783 case ARM::MOVr: 8784 case ARM::MOVr_TC: 8785 case ARM::MVNr: { 8786 // op: p 8787 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8788 Value |= (op & UINT64_C(15)) << 28; 8789 // op: s 8790 op = getCCOutOpValue(MI, 4, Fixups, STI); 8791 Value |= (op & UINT64_C(1)) << 20; 8792 // op: Rd 8793 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8794 Value |= (op & UINT64_C(15)) << 12; 8795 // op: Rm 8796 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8797 Value |= op & UINT64_C(15); 8798 break; 8799 } 8800 case ARM::MOVi: 8801 case ARM::MVNi: { 8802 // op: p 8803 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8804 Value |= (op & UINT64_C(15)) << 28; 8805 // op: s 8806 op = getCCOutOpValue(MI, 4, Fixups, STI); 8807 Value |= (op & UINT64_C(1)) << 20; 8808 // op: Rd 8809 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8810 Value |= (op & UINT64_C(15)) << 12; 8811 // op: imm 8812 op = getModImmOpValue(MI, 1, Fixups, STI); 8813 Value |= op & UINT64_C(4095); 8814 break; 8815 } 8816 case ARM::VADDD: 8817 case ARM::VDIVD: 8818 case ARM::VMULD: 8819 case ARM::VNMULD: 8820 case ARM::VSUBD: { 8821 // op: p 8822 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8823 Value |= (op & UINT64_C(15)) << 28; 8824 // op: Dd 8825 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8826 Value |= (op & UINT64_C(16)) << 18; 8827 Value |= (op & UINT64_C(15)) << 12; 8828 // op: Dn 8829 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8830 Value |= (op & UINT64_C(15)) << 16; 8831 Value |= (op & UINT64_C(16)) << 3; 8832 // op: Dm 8833 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8834 Value |= (op & UINT64_C(16)) << 1; 8835 Value |= op & UINT64_C(15); 8836 Value = VFPThumb2PostEncoder(MI, Value, STI); 8837 break; 8838 } 8839 case ARM::VLDRD: 8840 case ARM::VSTRD: { 8841 // op: p 8842 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8843 Value |= (op & UINT64_C(15)) << 28; 8844 // op: Dd 8845 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8846 Value |= (op & UINT64_C(16)) << 18; 8847 Value |= (op & UINT64_C(15)) << 12; 8848 // op: addr 8849 op = getAddrMode5OpValue(MI, 1, Fixups, STI); 8850 Value |= (op & UINT64_C(256)) << 15; 8851 Value |= (op & UINT64_C(7680)) << 7; 8852 Value |= op & UINT64_C(255); 8853 Value = VFPThumb2PostEncoder(MI, Value, STI); 8854 break; 8855 } 8856 case ARM::VMOVDRR: { 8857 // op: p 8858 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8859 Value |= (op & UINT64_C(15)) << 28; 8860 // op: Dm 8861 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8862 Value |= (op & UINT64_C(16)) << 1; 8863 Value |= op & UINT64_C(15); 8864 // op: Rt 8865 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8866 Value |= (op & UINT64_C(15)) << 12; 8867 // op: Rt2 8868 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8869 Value |= (op & UINT64_C(15)) << 16; 8870 Value = VFPThumb2PostEncoder(MI, Value, STI); 8871 break; 8872 } 8873 case ARM::VMOVRRD: { 8874 // op: p 8875 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8876 Value |= (op & UINT64_C(15)) << 28; 8877 // op: Dm 8878 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8879 Value |= (op & UINT64_C(16)) << 1; 8880 Value |= op & UINT64_C(15); 8881 // op: Rt 8882 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8883 Value |= (op & UINT64_C(15)) << 12; 8884 // op: Rt2 8885 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8886 Value |= (op & UINT64_C(15)) << 16; 8887 Value = VFPThumb2PostEncoder(MI, Value, STI); 8888 break; 8889 } 8890 case ARM::SXTB: 8891 case ARM::SXTB16: 8892 case ARM::SXTH: 8893 case ARM::UXTB: 8894 case ARM::UXTB16: 8895 case ARM::UXTH: { 8896 // op: p 8897 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8898 Value |= (op & UINT64_C(15)) << 28; 8899 // op: Rd 8900 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8901 Value |= (op & UINT64_C(15)) << 12; 8902 // op: Rm 8903 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8904 Value |= op & UINT64_C(15); 8905 // op: rot 8906 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8907 Value |= (op & UINT64_C(3)) << 10; 8908 break; 8909 } 8910 case ARM::SEL: { 8911 // op: p 8912 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8913 Value |= (op & UINT64_C(15)) << 28; 8914 // op: Rd 8915 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8916 Value |= (op & UINT64_C(15)) << 12; 8917 // op: Rn 8918 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8919 Value |= (op & UINT64_C(15)) << 16; 8920 // op: Rm 8921 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8922 Value |= op & UINT64_C(15); 8923 break; 8924 } 8925 case ARM::BFC: { 8926 // op: p 8927 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8928 Value |= (op & UINT64_C(15)) << 28; 8929 // op: Rd 8930 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8931 Value |= (op & UINT64_C(15)) << 12; 8932 // op: imm 8933 op = getBitfieldInvertedMaskOpValue(MI, 2, Fixups, STI); 8934 Value |= (op & UINT64_C(992)) << 11; 8935 Value |= (op & UINT64_C(31)) << 7; 8936 break; 8937 } 8938 case ARM::MOVTi16: { 8939 // op: p 8940 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8941 Value |= (op & UINT64_C(15)) << 28; 8942 // op: Rd 8943 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8944 Value |= (op & UINT64_C(15)) << 12; 8945 // op: imm 8946 op = getHiLo16ImmOpValue(MI, 2, Fixups, STI); 8947 Value |= (op & UINT64_C(61440)) << 4; 8948 Value |= op & UINT64_C(4095); 8949 break; 8950 } 8951 case ARM::SSAT16: 8952 case ARM::USAT16: { 8953 // op: p 8954 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8955 Value |= (op & UINT64_C(15)) << 28; 8956 // op: Rd 8957 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8958 Value |= (op & UINT64_C(15)) << 12; 8959 // op: sat_imm 8960 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8961 Value |= (op & UINT64_C(15)) << 16; 8962 // op: Rn 8963 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8964 Value |= op & UINT64_C(15); 8965 break; 8966 } 8967 case ARM::SDIV: 8968 case ARM::SMMUL: 8969 case ARM::SMMULR: 8970 case ARM::UDIV: 8971 case ARM::USAD8: { 8972 // op: p 8973 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8974 Value |= (op & UINT64_C(15)) << 28; 8975 // op: Rd 8976 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8977 Value |= (op & UINT64_C(15)) << 16; 8978 // op: Rn 8979 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8980 Value |= op & UINT64_C(15); 8981 // op: Rm 8982 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8983 Value |= (op & UINT64_C(15)) << 8; 8984 break; 8985 } 8986 case ARM::CMNzrsi: 8987 case ARM::CMPrsi: 8988 case ARM::TEQrsi: 8989 case ARM::TSTrsi: { 8990 // op: p 8991 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8992 Value |= (op & UINT64_C(15)) << 28; 8993 // op: Rn 8994 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8995 Value |= (op & UINT64_C(15)) << 16; 8996 // op: shift 8997 op = getSORegImmOpValue(MI, 1, Fixups, STI); 8998 Value |= op & UINT64_C(4064); 8999 Value |= op & UINT64_C(15); 9000 break; 9001 } 9002 case ARM::QADD16: 9003 case ARM::QADD8: 9004 case ARM::QASX: 9005 case ARM::QSAX: 9006 case ARM::QSUB16: 9007 case ARM::QSUB8: 9008 case ARM::SADD16: 9009 case ARM::SADD8: 9010 case ARM::SASX: 9011 case ARM::SHADD16: 9012 case ARM::SHADD8: 9013 case ARM::SHASX: 9014 case ARM::SHSAX: 9015 case ARM::SHSUB16: 9016 case ARM::SHSUB8: 9017 case ARM::SSAX: 9018 case ARM::SSUB16: 9019 case ARM::SSUB8: 9020 case ARM::UADD16: 9021 case ARM::UADD8: 9022 case ARM::UASX: 9023 case ARM::UHADD16: 9024 case ARM::UHADD8: 9025 case ARM::UHASX: 9026 case ARM::UHSAX: 9027 case ARM::UHSUB16: 9028 case ARM::UHSUB8: 9029 case ARM::UQADD16: 9030 case ARM::UQADD8: 9031 case ARM::UQASX: 9032 case ARM::UQSAX: 9033 case ARM::UQSUB16: 9034 case ARM::UQSUB8: 9035 case ARM::USAX: 9036 case ARM::USUB16: 9037 case ARM::USUB8: { 9038 // op: p 9039 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9040 Value |= (op & UINT64_C(15)) << 28; 9041 // op: Rn 9042 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9043 Value |= (op & UINT64_C(15)) << 16; 9044 // op: Rd 9045 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9046 Value |= (op & UINT64_C(15)) << 12; 9047 // op: Rm 9048 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9049 Value |= op & UINT64_C(15); 9050 break; 9051 } 9052 case ARM::SMUAD: 9053 case ARM::SMUADX: 9054 case ARM::SMULBB: 9055 case ARM::SMULBT: 9056 case ARM::SMULTB: 9057 case ARM::SMULTT: 9058 case ARM::SMULWB: 9059 case ARM::SMULWT: 9060 case ARM::SMUSD: 9061 case ARM::SMUSDX: { 9062 // op: p 9063 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9064 Value |= (op & UINT64_C(15)) << 28; 9065 // op: Rn 9066 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9067 Value |= op & UINT64_C(15); 9068 // op: Rm 9069 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9070 Value |= (op & UINT64_C(15)) << 8; 9071 // op: Rd 9072 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9073 Value |= (op & UINT64_C(15)) << 16; 9074 break; 9075 } 9076 case ARM::QADD: 9077 case ARM::QDADD: 9078 case ARM::QDSUB: 9079 case ARM::QSUB: { 9080 // op: p 9081 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9082 Value |= (op & UINT64_C(15)) << 28; 9083 // op: Rn 9084 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9085 Value |= (op & UINT64_C(15)) << 16; 9086 // op: Rd 9087 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9088 Value |= (op & UINT64_C(15)) << 12; 9089 // op: Rm 9090 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9091 Value |= op & UINT64_C(15); 9092 break; 9093 } 9094 case ARM::SWP: 9095 case ARM::SWPB: { 9096 // op: p 9097 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9098 Value |= (op & UINT64_C(15)) << 28; 9099 // op: Rt 9100 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9101 Value |= (op & UINT64_C(15)) << 12; 9102 // op: Rt2 9103 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9104 Value |= op & UINT64_C(15); 9105 // op: addr 9106 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9107 Value |= (op & UINT64_C(15)) << 16; 9108 break; 9109 } 9110 case ARM::LDRBi12: 9111 case ARM::LDRi12: 9112 case ARM::STRBi12: 9113 case ARM::STRi12: { 9114 // op: p 9115 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9116 Value |= (op & UINT64_C(15)) << 28; 9117 // op: Rt 9118 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9119 Value |= (op & UINT64_C(15)) << 12; 9120 // op: addr 9121 op = getAddrModeImm12OpValue(MI, 1, Fixups, STI); 9122 Value |= (op & UINT64_C(4096)) << 11; 9123 Value |= (op & UINT64_C(122880)) << 3; 9124 Value |= op & UINT64_C(4095); 9125 break; 9126 } 9127 case ARM::LDRcp: { 9128 // op: p 9129 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9130 Value |= (op & UINT64_C(15)) << 28; 9131 // op: Rt 9132 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9133 Value |= (op & UINT64_C(15)) << 12; 9134 // op: addr 9135 op = getAddrModeImm12OpValue(MI, 1, Fixups, STI); 9136 Value |= (op & UINT64_C(4096)) << 11; 9137 Value |= op & UINT64_C(4095); 9138 break; 9139 } 9140 case ARM::STLEX: 9141 case ARM::STLEXB: 9142 case ARM::STLEXD: 9143 case ARM::STLEXH: 9144 case ARM::STREX: 9145 case ARM::STREXB: 9146 case ARM::STREXD: 9147 case ARM::STREXH: { 9148 // op: p 9149 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9150 Value |= (op & UINT64_C(15)) << 28; 9151 // op: Rt 9152 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9153 Value |= op & UINT64_C(15); 9154 // op: addr 9155 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9156 Value |= (op & UINT64_C(15)) << 16; 9157 // op: Rd 9158 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9159 Value |= (op & UINT64_C(15)) << 12; 9160 break; 9161 } 9162 case ARM::VADDH: 9163 case ARM::VADDS: 9164 case ARM::VDIVH: 9165 case ARM::VDIVS: 9166 case ARM::VMULH: 9167 case ARM::VMULS: 9168 case ARM::VNMULH: 9169 case ARM::VNMULS: 9170 case ARM::VSUBH: 9171 case ARM::VSUBS: { 9172 // op: p 9173 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9174 Value |= (op & UINT64_C(15)) << 28; 9175 // op: Sd 9176 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9177 Value |= (op & UINT64_C(1)) << 22; 9178 Value |= (op & UINT64_C(30)) << 11; 9179 // op: Sn 9180 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9181 Value |= (op & UINT64_C(30)) << 15; 9182 Value |= (op & UINT64_C(1)) << 7; 9183 // op: Sm 9184 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9185 Value |= (op & UINT64_C(1)) << 5; 9186 Value |= (op & UINT64_C(30)) >> 1; 9187 Value = VFPThumb2PostEncoder(MI, Value, STI); 9188 break; 9189 } 9190 case ARM::VLDRH: 9191 case ARM::VSTRH: { 9192 // op: p 9193 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9194 Value |= (op & UINT64_C(15)) << 28; 9195 // op: Sd 9196 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9197 Value |= (op & UINT64_C(1)) << 22; 9198 Value |= (op & UINT64_C(30)) << 11; 9199 // op: addr 9200 op = getAddrMode5FP16OpValue(MI, 1, Fixups, STI); 9201 Value |= (op & UINT64_C(256)) << 15; 9202 Value |= (op & UINT64_C(7680)) << 7; 9203 Value |= op & UINT64_C(255); 9204 Value = VFPThumb2PostEncoder(MI, Value, STI); 9205 break; 9206 } 9207 case ARM::VLDRS: 9208 case ARM::VSTRS: { 9209 // op: p 9210 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9211 Value |= (op & UINT64_C(15)) << 28; 9212 // op: Sd 9213 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9214 Value |= (op & UINT64_C(1)) << 22; 9215 Value |= (op & UINT64_C(30)) << 11; 9216 // op: addr 9217 op = getAddrMode5OpValue(MI, 1, Fixups, STI); 9218 Value |= (op & UINT64_C(256)) << 15; 9219 Value |= (op & UINT64_C(7680)) << 7; 9220 Value |= op & UINT64_C(255); 9221 Value = VFPThumb2PostEncoder(MI, Value, STI); 9222 break; 9223 } 9224 case ARM::VSHTOH: 9225 case ARM::VSHTOS: 9226 case ARM::VSLTOH: 9227 case ARM::VSLTOS: 9228 case ARM::VTOSHH: 9229 case ARM::VTOSHS: 9230 case ARM::VTOSLH: 9231 case ARM::VTOSLS: 9232 case ARM::VTOUHH: 9233 case ARM::VTOUHS: 9234 case ARM::VTOULH: 9235 case ARM::VTOULS: 9236 case ARM::VUHTOH: 9237 case ARM::VUHTOS: 9238 case ARM::VULTOH: 9239 case ARM::VULTOS: { 9240 // op: p 9241 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9242 Value |= (op & UINT64_C(15)) << 28; 9243 // op: fbits 9244 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9245 Value |= (op & UINT64_C(1)) << 5; 9246 Value |= (op & UINT64_C(30)) >> 1; 9247 // op: dst 9248 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9249 Value |= (op & UINT64_C(1)) << 22; 9250 Value |= (op & UINT64_C(30)) << 11; 9251 Value = VFPThumb2PostEncoder(MI, Value, STI); 9252 break; 9253 } 9254 case ARM::VSHTOD: 9255 case ARM::VSLTOD: 9256 case ARM::VTOSHD: 9257 case ARM::VTOSLD: 9258 case ARM::VTOUHD: 9259 case ARM::VTOULD: 9260 case ARM::VUHTOD: 9261 case ARM::VULTOD: { 9262 // op: p 9263 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9264 Value |= (op & UINT64_C(15)) << 28; 9265 // op: fbits 9266 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9267 Value |= (op & UINT64_C(1)) << 5; 9268 Value |= (op & UINT64_C(30)) >> 1; 9269 // op: dst 9270 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9271 Value |= (op & UINT64_C(16)) << 18; 9272 Value |= (op & UINT64_C(15)) << 12; 9273 Value = VFPThumb2PostEncoder(MI, Value, STI); 9274 break; 9275 } 9276 case ARM::ADCrr: 9277 case ARM::ADDrr: 9278 case ARM::ANDrr: 9279 case ARM::BICrr: 9280 case ARM::EORrr: 9281 case ARM::ORRrr: 9282 case ARM::RSBrr: 9283 case ARM::RSCrr: 9284 case ARM::SBCrr: 9285 case ARM::SUBrr: { 9286 // op: p 9287 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9288 Value |= (op & UINT64_C(15)) << 28; 9289 // op: s 9290 op = getCCOutOpValue(MI, 5, Fixups, STI); 9291 Value |= (op & UINT64_C(1)) << 20; 9292 // op: Rd 9293 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9294 Value |= (op & UINT64_C(15)) << 12; 9295 // op: Rn 9296 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9297 Value |= (op & UINT64_C(15)) << 16; 9298 // op: Rm 9299 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9300 Value |= op & UINT64_C(15); 9301 break; 9302 } 9303 case ARM::ADCri: 9304 case ARM::ADDri: 9305 case ARM::ANDri: 9306 case ARM::BICri: 9307 case ARM::EORri: 9308 case ARM::ORRri: 9309 case ARM::RSBri: 9310 case ARM::RSCri: 9311 case ARM::SBCri: 9312 case ARM::SUBri: { 9313 // op: p 9314 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9315 Value |= (op & UINT64_C(15)) << 28; 9316 // op: s 9317 op = getCCOutOpValue(MI, 5, Fixups, STI); 9318 Value |= (op & UINT64_C(1)) << 20; 9319 // op: Rd 9320 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9321 Value |= (op & UINT64_C(15)) << 12; 9322 // op: Rn 9323 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9324 Value |= (op & UINT64_C(15)) << 16; 9325 // op: imm 9326 op = getModImmOpValue(MI, 2, Fixups, STI); 9327 Value |= op & UINT64_C(4095); 9328 break; 9329 } 9330 case ARM::MVNsi: { 9331 // op: p 9332 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9333 Value |= (op & UINT64_C(15)) << 28; 9334 // op: s 9335 op = getCCOutOpValue(MI, 5, Fixups, STI); 9336 Value |= (op & UINT64_C(1)) << 20; 9337 // op: Rd 9338 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9339 Value |= (op & UINT64_C(15)) << 12; 9340 // op: shift 9341 op = getSORegImmOpValue(MI, 1, Fixups, STI); 9342 Value |= op & UINT64_C(4064); 9343 Value |= op & UINT64_C(15); 9344 break; 9345 } 9346 case ARM::MOVsi: { 9347 // op: p 9348 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9349 Value |= (op & UINT64_C(15)) << 28; 9350 // op: s 9351 op = getCCOutOpValue(MI, 5, Fixups, STI); 9352 Value |= (op & UINT64_C(1)) << 20; 9353 // op: Rd 9354 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9355 Value |= (op & UINT64_C(15)) << 12; 9356 // op: src 9357 op = getSORegImmOpValue(MI, 1, Fixups, STI); 9358 Value |= op & UINT64_C(4064); 9359 Value |= op & UINT64_C(15); 9360 break; 9361 } 9362 case ARM::MUL: { 9363 // op: p 9364 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9365 Value |= (op & UINT64_C(15)) << 28; 9366 // op: s 9367 op = getCCOutOpValue(MI, 5, Fixups, STI); 9368 Value |= (op & UINT64_C(1)) << 20; 9369 // op: Rd 9370 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9371 Value |= (op & UINT64_C(15)) << 16; 9372 // op: Rm 9373 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9374 Value |= (op & UINT64_C(15)) << 8; 9375 // op: Rn 9376 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9377 Value |= op & UINT64_C(15); 9378 break; 9379 } 9380 case ARM::VFMAD: 9381 case ARM::VFMSD: 9382 case ARM::VFNMAD: 9383 case ARM::VFNMSD: 9384 case ARM::VMLAD: 9385 case ARM::VMLSD: 9386 case ARM::VNMLAD: 9387 case ARM::VNMLSD: { 9388 // op: p 9389 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9390 Value |= (op & UINT64_C(15)) << 28; 9391 // op: Dd 9392 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9393 Value |= (op & UINT64_C(16)) << 18; 9394 Value |= (op & UINT64_C(15)) << 12; 9395 // op: Dn 9396 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9397 Value |= (op & UINT64_C(15)) << 16; 9398 Value |= (op & UINT64_C(16)) << 3; 9399 // op: Dm 9400 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9401 Value |= (op & UINT64_C(16)) << 1; 9402 Value |= op & UINT64_C(15); 9403 Value = VFPThumb2PostEncoder(MI, Value, STI); 9404 break; 9405 } 9406 case ARM::SXTAB: 9407 case ARM::SXTAB16: 9408 case ARM::SXTAH: 9409 case ARM::UXTAB: 9410 case ARM::UXTAB16: 9411 case ARM::UXTAH: { 9412 // op: p 9413 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9414 Value |= (op & UINT64_C(15)) << 28; 9415 // op: Rd 9416 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9417 Value |= (op & UINT64_C(15)) << 12; 9418 // op: Rm 9419 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9420 Value |= op & UINT64_C(15); 9421 // op: Rn 9422 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9423 Value |= (op & UINT64_C(15)) << 16; 9424 // op: rot 9425 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9426 Value |= (op & UINT64_C(3)) << 10; 9427 break; 9428 } 9429 case ARM::PKHBT: 9430 case ARM::PKHTB: { 9431 // op: p 9432 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9433 Value |= (op & UINT64_C(15)) << 28; 9434 // op: Rd 9435 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9436 Value |= (op & UINT64_C(15)) << 12; 9437 // op: Rn 9438 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9439 Value |= (op & UINT64_C(15)) << 16; 9440 // op: Rm 9441 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9442 Value |= op & UINT64_C(15); 9443 // op: sh 9444 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9445 Value |= (op & UINT64_C(31)) << 7; 9446 break; 9447 } 9448 case ARM::SBFX: 9449 case ARM::UBFX: { 9450 // op: p 9451 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9452 Value |= (op & UINT64_C(15)) << 28; 9453 // op: Rd 9454 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9455 Value |= (op & UINT64_C(15)) << 12; 9456 // op: Rn 9457 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9458 Value |= op & UINT64_C(15); 9459 // op: lsb 9460 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9461 Value |= (op & UINT64_C(31)) << 7; 9462 // op: width 9463 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9464 Value |= (op & UINT64_C(31)) << 16; 9465 break; 9466 } 9467 case ARM::BFI: { 9468 // op: p 9469 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9470 Value |= (op & UINT64_C(15)) << 28; 9471 // op: Rd 9472 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9473 Value |= (op & UINT64_C(15)) << 12; 9474 // op: Rn 9475 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9476 Value |= op & UINT64_C(15); 9477 // op: imm 9478 op = getBitfieldInvertedMaskOpValue(MI, 3, Fixups, STI); 9479 Value |= (op & UINT64_C(992)) << 11; 9480 Value |= (op & UINT64_C(31)) << 7; 9481 break; 9482 } 9483 case ARM::SSAT: 9484 case ARM::USAT: { 9485 // op: p 9486 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9487 Value |= (op & UINT64_C(15)) << 28; 9488 // op: Rd 9489 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9490 Value |= (op & UINT64_C(15)) << 12; 9491 // op: sat_imm 9492 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9493 Value |= (op & UINT64_C(31)) << 16; 9494 // op: Rn 9495 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9496 Value |= op & UINT64_C(15); 9497 // op: sh 9498 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9499 Value |= (op & UINT64_C(31)) << 7; 9500 Value |= (op & UINT64_C(32)) << 1; 9501 break; 9502 } 9503 case ARM::MLS: { 9504 // op: p 9505 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9506 Value |= (op & UINT64_C(15)) << 28; 9507 // op: Rd 9508 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9509 Value |= (op & UINT64_C(15)) << 16; 9510 // op: Rm 9511 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9512 Value |= (op & UINT64_C(15)) << 8; 9513 // op: Rn 9514 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9515 Value |= op & UINT64_C(15); 9516 // op: Ra 9517 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9518 Value |= (op & UINT64_C(15)) << 12; 9519 break; 9520 } 9521 case ARM::SMMLA: 9522 case ARM::SMMLAR: 9523 case ARM::SMMLS: 9524 case ARM::SMMLSR: 9525 case ARM::USADA8: { 9526 // op: p 9527 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9528 Value |= (op & UINT64_C(15)) << 28; 9529 // op: Rd 9530 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9531 Value |= (op & UINT64_C(15)) << 16; 9532 // op: Rn 9533 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9534 Value |= op & UINT64_C(15); 9535 // op: Rm 9536 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9537 Value |= (op & UINT64_C(15)) << 8; 9538 // op: Ra 9539 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9540 Value |= (op & UINT64_C(15)) << 12; 9541 break; 9542 } 9543 case ARM::UMAAL: { 9544 // op: p 9545 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9546 Value |= (op & UINT64_C(15)) << 28; 9547 // op: RdLo 9548 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9549 Value |= (op & UINT64_C(15)) << 12; 9550 // op: RdHi 9551 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9552 Value |= (op & UINT64_C(15)) << 16; 9553 // op: Rm 9554 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9555 Value |= (op & UINT64_C(15)) << 8; 9556 // op: Rn 9557 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9558 Value |= op & UINT64_C(15); 9559 break; 9560 } 9561 case ARM::CMNzrsr: 9562 case ARM::CMPrsr: 9563 case ARM::TEQrsr: 9564 case ARM::TSTrsr: { 9565 // op: p 9566 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9567 Value |= (op & UINT64_C(15)) << 28; 9568 // op: Rn 9569 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9570 Value |= (op & UINT64_C(15)) << 16; 9571 // op: shift 9572 op = getSORegRegOpValue(MI, 1, Fixups, STI); 9573 Value |= op & UINT64_C(3840); 9574 Value |= op & UINT64_C(96); 9575 Value |= op & UINT64_C(15); 9576 break; 9577 } 9578 case ARM::SMLAD: 9579 case ARM::SMLADX: 9580 case ARM::SMLSD: 9581 case ARM::SMLSDX: { 9582 // op: p 9583 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9584 Value |= (op & UINT64_C(15)) << 28; 9585 // op: Rn 9586 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9587 Value |= op & UINT64_C(15); 9588 // op: Rm 9589 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9590 Value |= (op & UINT64_C(15)) << 8; 9591 // op: Ra 9592 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9593 Value |= (op & UINT64_C(15)) << 12; 9594 // op: Rd 9595 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9596 Value |= (op & UINT64_C(15)) << 16; 9597 break; 9598 } 9599 case ARM::SMLABB: 9600 case ARM::SMLABT: 9601 case ARM::SMLATB: 9602 case ARM::SMLATT: 9603 case ARM::SMLAWB: 9604 case ARM::SMLAWT: { 9605 // op: p 9606 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9607 Value |= (op & UINT64_C(15)) << 28; 9608 // op: Rn 9609 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9610 Value |= op & UINT64_C(15); 9611 // op: Rm 9612 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9613 Value |= (op & UINT64_C(15)) << 8; 9614 // op: Rd 9615 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9616 Value |= (op & UINT64_C(15)) << 16; 9617 // op: Ra 9618 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9619 Value |= (op & UINT64_C(15)) << 12; 9620 break; 9621 } 9622 case ARM::SMLALBB: 9623 case ARM::SMLALBT: 9624 case ARM::SMLALD: 9625 case ARM::SMLALDX: 9626 case ARM::SMLALTB: 9627 case ARM::SMLALTT: 9628 case ARM::SMLSLD: 9629 case ARM::SMLSLDX: { 9630 // op: p 9631 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9632 Value |= (op & UINT64_C(15)) << 28; 9633 // op: Rn 9634 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9635 Value |= op & UINT64_C(15); 9636 // op: Rm 9637 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9638 Value |= (op & UINT64_C(15)) << 8; 9639 // op: RdLo 9640 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9641 Value |= (op & UINT64_C(15)) << 12; 9642 // op: RdHi 9643 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9644 Value |= (op & UINT64_C(15)) << 16; 9645 break; 9646 } 9647 case ARM::LDRB_PRE_IMM: 9648 case ARM::LDR_PRE_IMM: { 9649 // op: p 9650 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9651 Value |= (op & UINT64_C(15)) << 28; 9652 // op: Rt 9653 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9654 Value |= (op & UINT64_C(15)) << 12; 9655 // op: addr 9656 op = getAddrModeImm12OpValue(MI, 2, Fixups, STI); 9657 Value |= (op & UINT64_C(4096)) << 11; 9658 Value |= (op & UINT64_C(122880)) << 3; 9659 Value |= op & UINT64_C(4095); 9660 break; 9661 } 9662 case ARM::LDRBrs: 9663 case ARM::LDRrs: 9664 case ARM::STRBrs: 9665 case ARM::STRrs: { 9666 // op: p 9667 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9668 Value |= (op & UINT64_C(15)) << 28; 9669 // op: Rt 9670 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9671 Value |= (op & UINT64_C(15)) << 12; 9672 // op: shift 9673 op = getLdStSORegOpValue(MI, 1, Fixups, STI); 9674 Value |= (op & UINT64_C(4096)) << 11; 9675 Value |= (op & UINT64_C(122880)) << 3; 9676 Value |= op & UINT64_C(4064); 9677 Value |= op & UINT64_C(15); 9678 break; 9679 } 9680 case ARM::STRB_PRE_IMM: 9681 case ARM::STR_PRE_IMM: { 9682 // op: p 9683 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9684 Value |= (op & UINT64_C(15)) << 28; 9685 // op: Rt 9686 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9687 Value |= (op & UINT64_C(15)) << 12; 9688 // op: addr 9689 op = getAddrModeImm12OpValue(MI, 2, Fixups, STI); 9690 Value |= (op & UINT64_C(4096)) << 11; 9691 Value |= (op & UINT64_C(122880)) << 3; 9692 Value |= op & UINT64_C(4095); 9693 break; 9694 } 9695 case ARM::VFMAH: 9696 case ARM::VFMAS: 9697 case ARM::VFMSH: 9698 case ARM::VFMSS: 9699 case ARM::VFNMAH: 9700 case ARM::VFNMAS: 9701 case ARM::VFNMSH: 9702 case ARM::VFNMSS: 9703 case ARM::VMLAH: 9704 case ARM::VMLAS: 9705 case ARM::VMLSH: 9706 case ARM::VMLSS: 9707 case ARM::VNMLAH: 9708 case ARM::VNMLAS: 9709 case ARM::VNMLSH: 9710 case ARM::VNMLSS: { 9711 // op: p 9712 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9713 Value |= (op & UINT64_C(15)) << 28; 9714 // op: Sd 9715 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9716 Value |= (op & UINT64_C(1)) << 22; 9717 Value |= (op & UINT64_C(30)) << 11; 9718 // op: Sn 9719 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9720 Value |= (op & UINT64_C(30)) << 15; 9721 Value |= (op & UINT64_C(1)) << 7; 9722 // op: Sm 9723 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9724 Value |= (op & UINT64_C(1)) << 5; 9725 Value |= (op & UINT64_C(30)) >> 1; 9726 Value = VFPThumb2PostEncoder(MI, Value, STI); 9727 break; 9728 } 9729 case ARM::LDRH: 9730 case ARM::LDRSB: 9731 case ARM::LDRSH: 9732 case ARM::STRH: { 9733 // op: p 9734 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9735 Value |= (op & UINT64_C(15)) << 28; 9736 // op: addr 9737 op = getAddrMode3OpValue(MI, 1, Fixups, STI); 9738 Value |= (op & UINT64_C(256)) << 15; 9739 Value |= (op & UINT64_C(8192)) << 9; 9740 Value |= (op & UINT64_C(7680)) << 7; 9741 Value |= (op & UINT64_C(240)) << 4; 9742 Value |= op & UINT64_C(15); 9743 // op: Rt 9744 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9745 Value |= (op & UINT64_C(15)) << 12; 9746 break; 9747 } 9748 case ARM::LDCL_OFFSET: 9749 case ARM::LDCL_PRE: 9750 case ARM::LDC_OFFSET: 9751 case ARM::LDC_PRE: 9752 case ARM::STCL_OFFSET: 9753 case ARM::STCL_PRE: 9754 case ARM::STC_OFFSET: 9755 case ARM::STC_PRE: { 9756 // op: p 9757 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9758 Value |= (op & UINT64_C(15)) << 28; 9759 // op: addr 9760 op = getAddrMode5OpValue(MI, 2, Fixups, STI); 9761 Value |= (op & UINT64_C(256)) << 15; 9762 Value |= (op & UINT64_C(7680)) << 7; 9763 Value |= op & UINT64_C(255); 9764 // op: cop 9765 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9766 Value |= (op & UINT64_C(15)) << 8; 9767 // op: CRd 9768 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9769 Value |= (op & UINT64_C(15)) << 12; 9770 break; 9771 } 9772 case ARM::LDRHTi: 9773 case ARM::LDRSBTi: 9774 case ARM::LDRSHTi: { 9775 // op: p 9776 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9777 Value |= (op & UINT64_C(15)) << 28; 9778 // op: addr 9779 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9780 Value |= (op & UINT64_C(15)) << 16; 9781 // op: Rt 9782 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9783 Value |= (op & UINT64_C(15)) << 12; 9784 // op: offset 9785 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9786 Value |= (op & UINT64_C(256)) << 15; 9787 Value |= (op & UINT64_C(240)) << 4; 9788 Value |= op & UINT64_C(15); 9789 break; 9790 } 9791 case ARM::STRHTi: { 9792 // op: p 9793 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9794 Value |= (op & UINT64_C(15)) << 28; 9795 // op: addr 9796 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9797 Value |= (op & UINT64_C(15)) << 16; 9798 // op: Rt 9799 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9800 Value |= (op & UINT64_C(15)) << 12; 9801 // op: offset 9802 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9803 Value |= (op & UINT64_C(256)) << 15; 9804 Value |= (op & UINT64_C(240)) << 4; 9805 Value |= op & UINT64_C(15); 9806 break; 9807 } 9808 case ARM::VMOVSRR: { 9809 // op: p 9810 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9811 Value |= (op & UINT64_C(15)) << 28; 9812 // op: dst1 9813 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9814 Value |= (op & UINT64_C(1)) << 5; 9815 Value |= (op & UINT64_C(30)) >> 1; 9816 // op: src1 9817 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9818 Value |= (op & UINT64_C(15)) << 12; 9819 // op: src2 9820 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9821 Value |= (op & UINT64_C(15)) << 16; 9822 Value = VFPThumb2PostEncoder(MI, Value, STI); 9823 break; 9824 } 9825 case ARM::LDCL_POST: 9826 case ARM::LDC_POST: 9827 case ARM::STCL_POST: 9828 case ARM::STC_POST: { 9829 // op: p 9830 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9831 Value |= (op & UINT64_C(15)) << 28; 9832 // op: offset 9833 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9834 Value |= (op & UINT64_C(256)) << 15; 9835 Value |= op & UINT64_C(255); 9836 // op: addr 9837 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9838 Value |= (op & UINT64_C(15)) << 16; 9839 // op: cop 9840 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9841 Value |= (op & UINT64_C(15)) << 8; 9842 // op: CRd 9843 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9844 Value |= (op & UINT64_C(15)) << 12; 9845 break; 9846 } 9847 case ARM::LDCL_OPTION: 9848 case ARM::LDC_OPTION: 9849 case ARM::STCL_OPTION: 9850 case ARM::STC_OPTION: { 9851 // op: p 9852 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9853 Value |= (op & UINT64_C(15)) << 28; 9854 // op: option 9855 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9856 Value |= op & UINT64_C(255); 9857 // op: addr 9858 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9859 Value |= (op & UINT64_C(15)) << 16; 9860 // op: cop 9861 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9862 Value |= (op & UINT64_C(15)) << 8; 9863 // op: CRd 9864 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9865 Value |= (op & UINT64_C(15)) << 12; 9866 break; 9867 } 9868 case ARM::ADCrsi: 9869 case ARM::ADDrsi: 9870 case ARM::ANDrsi: 9871 case ARM::BICrsi: 9872 case ARM::EORrsi: 9873 case ARM::ORRrsi: 9874 case ARM::RSBrsi: 9875 case ARM::RSCrsi: 9876 case ARM::SBCrsi: 9877 case ARM::SUBrsi: { 9878 // op: p 9879 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9880 Value |= (op & UINT64_C(15)) << 28; 9881 // op: s 9882 op = getCCOutOpValue(MI, 6, Fixups, STI); 9883 Value |= (op & UINT64_C(1)) << 20; 9884 // op: Rd 9885 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9886 Value |= (op & UINT64_C(15)) << 12; 9887 // op: Rn 9888 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9889 Value |= (op & UINT64_C(15)) << 16; 9890 // op: shift 9891 op = getSORegImmOpValue(MI, 2, Fixups, STI); 9892 Value |= op & UINT64_C(4064); 9893 Value |= op & UINT64_C(15); 9894 break; 9895 } 9896 case ARM::MVNsr: { 9897 // op: p 9898 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9899 Value |= (op & UINT64_C(15)) << 28; 9900 // op: s 9901 op = getCCOutOpValue(MI, 6, Fixups, STI); 9902 Value |= (op & UINT64_C(1)) << 20; 9903 // op: Rd 9904 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9905 Value |= (op & UINT64_C(15)) << 12; 9906 // op: shift 9907 op = getSORegRegOpValue(MI, 1, Fixups, STI); 9908 Value |= op & UINT64_C(3840); 9909 Value |= op & UINT64_C(96); 9910 Value |= op & UINT64_C(15); 9911 break; 9912 } 9913 case ARM::MOVsr: { 9914 // op: p 9915 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9916 Value |= (op & UINT64_C(15)) << 28; 9917 // op: s 9918 op = getCCOutOpValue(MI, 6, Fixups, STI); 9919 Value |= (op & UINT64_C(1)) << 20; 9920 // op: Rd 9921 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9922 Value |= (op & UINT64_C(15)) << 12; 9923 // op: src 9924 op = getSORegRegOpValue(MI, 1, Fixups, STI); 9925 Value |= op & UINT64_C(3840); 9926 Value |= op & UINT64_C(96); 9927 Value |= op & UINT64_C(15); 9928 break; 9929 } 9930 case ARM::MLA: { 9931 // op: p 9932 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9933 Value |= (op & UINT64_C(15)) << 28; 9934 // op: s 9935 op = getCCOutOpValue(MI, 6, Fixups, STI); 9936 Value |= (op & UINT64_C(1)) << 20; 9937 // op: Rd 9938 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9939 Value |= (op & UINT64_C(15)) << 16; 9940 // op: Rm 9941 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9942 Value |= (op & UINT64_C(15)) << 8; 9943 // op: Rn 9944 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9945 Value |= op & UINT64_C(15); 9946 // op: Ra 9947 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9948 Value |= (op & UINT64_C(15)) << 12; 9949 break; 9950 } 9951 case ARM::SMULL: 9952 case ARM::UMULL: { 9953 // op: p 9954 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9955 Value |= (op & UINT64_C(15)) << 28; 9956 // op: s 9957 op = getCCOutOpValue(MI, 6, Fixups, STI); 9958 Value |= (op & UINT64_C(1)) << 20; 9959 // op: RdLo 9960 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9961 Value |= (op & UINT64_C(15)) << 12; 9962 // op: RdHi 9963 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9964 Value |= (op & UINT64_C(15)) << 16; 9965 // op: Rm 9966 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9967 Value |= (op & UINT64_C(15)) << 8; 9968 // op: Rn 9969 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9970 Value |= op & UINT64_C(15); 9971 break; 9972 } 9973 case ARM::VMOVRRS: { 9974 // op: p 9975 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9976 Value |= (op & UINT64_C(15)) << 28; 9977 // op: src1 9978 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9979 Value |= (op & UINT64_C(1)) << 5; 9980 Value |= (op & UINT64_C(30)) >> 1; 9981 // op: Rt 9982 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9983 Value |= (op & UINT64_C(15)) << 12; 9984 // op: Rt2 9985 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9986 Value |= (op & UINT64_C(15)) << 16; 9987 Value = VFPThumb2PostEncoder(MI, Value, STI); 9988 break; 9989 } 9990 case ARM::MRRC: { 9991 // op: p 9992 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 9993 Value |= (op & UINT64_C(15)) << 28; 9994 // op: Rt 9995 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9996 Value |= (op & UINT64_C(15)) << 12; 9997 // op: Rt2 9998 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9999 Value |= (op & UINT64_C(15)) << 16; 10000 // op: cop 10001 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10002 Value |= (op & UINT64_C(15)) << 8; 10003 // op: opc1 10004 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10005 Value |= (op & UINT64_C(15)) << 4; 10006 // op: CRm 10007 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 10008 Value |= op & UINT64_C(15); 10009 break; 10010 } 10011 case ARM::LDRH_PRE: 10012 case ARM::LDRSB_PRE: 10013 case ARM::LDRSH_PRE: { 10014 // op: p 10015 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10016 Value |= (op & UINT64_C(15)) << 28; 10017 // op: Rt 10018 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10019 Value |= (op & UINT64_C(15)) << 12; 10020 // op: addr 10021 op = getAddrMode3OpValue(MI, 2, Fixups, STI); 10022 Value |= (op & UINT64_C(256)) << 15; 10023 Value |= (op & UINT64_C(8192)) << 9; 10024 Value |= (op & UINT64_C(7680)) << 7; 10025 Value |= (op & UINT64_C(240)) << 4; 10026 Value |= op & UINT64_C(15); 10027 break; 10028 } 10029 case ARM::LDRB_PRE_REG: 10030 case ARM::LDR_PRE_REG: { 10031 // op: p 10032 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10033 Value |= (op & UINT64_C(15)) << 28; 10034 // op: Rt 10035 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10036 Value |= (op & UINT64_C(15)) << 12; 10037 // op: addr 10038 op = getLdStSORegOpValue(MI, 2, Fixups, STI); 10039 Value |= (op & UINT64_C(4096)) << 11; 10040 Value |= (op & UINT64_C(122880)) << 3; 10041 Value |= op & UINT64_C(4064); 10042 Value |= op & UINT64_C(15); 10043 break; 10044 } 10045 case ARM::LDRBT_POST_REG: 10046 case ARM::LDRB_POST_REG: 10047 case ARM::LDRT_POST_REG: 10048 case ARM::LDR_POST_REG: { 10049 // op: p 10050 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10051 Value |= (op & UINT64_C(15)) << 28; 10052 // op: Rt 10053 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10054 Value |= (op & UINT64_C(15)) << 12; 10055 // op: offset 10056 op = getAddrMode2OffsetOpValue(MI, 3, Fixups, STI); 10057 Value |= (op & UINT64_C(4096)) << 11; 10058 Value |= op & UINT64_C(4064); 10059 Value |= op & UINT64_C(15); 10060 // op: addr 10061 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10062 Value |= (op & UINT64_C(15)) << 16; 10063 break; 10064 } 10065 case ARM::LDRBT_POST_IMM: 10066 case ARM::LDRB_POST_IMM: 10067 case ARM::LDRT_POST_IMM: 10068 case ARM::LDR_POST_IMM: { 10069 // op: p 10070 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10071 Value |= (op & UINT64_C(15)) << 28; 10072 // op: Rt 10073 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10074 Value |= (op & UINT64_C(15)) << 12; 10075 // op: offset 10076 op = getAddrMode2OffsetOpValue(MI, 3, Fixups, STI); 10077 Value |= (op & UINT64_C(4096)) << 11; 10078 Value |= op & UINT64_C(4095); 10079 // op: addr 10080 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10081 Value |= (op & UINT64_C(15)) << 16; 10082 break; 10083 } 10084 case ARM::LDRH_POST: 10085 case ARM::LDRSB_POST: 10086 case ARM::LDRSH_POST: { 10087 // op: p 10088 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10089 Value |= (op & UINT64_C(15)) << 28; 10090 // op: Rt 10091 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10092 Value |= (op & UINT64_C(15)) << 12; 10093 // op: offset 10094 op = getAddrMode3OffsetOpValue(MI, 3, Fixups, STI); 10095 Value |= (op & UINT64_C(256)) << 15; 10096 Value |= (op & UINT64_C(512)) << 13; 10097 Value |= (op & UINT64_C(240)) << 4; 10098 Value |= op & UINT64_C(15); 10099 // op: addr 10100 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10101 Value |= (op & UINT64_C(15)) << 16; 10102 break; 10103 } 10104 case ARM::STRH_PRE: { 10105 // op: p 10106 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10107 Value |= (op & UINT64_C(15)) << 28; 10108 // op: Rt 10109 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10110 Value |= (op & UINT64_C(15)) << 12; 10111 // op: addr 10112 op = getAddrMode3OpValue(MI, 2, Fixups, STI); 10113 Value |= (op & UINT64_C(256)) << 15; 10114 Value |= (op & UINT64_C(8192)) << 9; 10115 Value |= (op & UINT64_C(7680)) << 7; 10116 Value |= (op & UINT64_C(240)) << 4; 10117 Value |= op & UINT64_C(15); 10118 break; 10119 } 10120 case ARM::STRB_PRE_REG: 10121 case ARM::STR_PRE_REG: { 10122 // op: p 10123 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10124 Value |= (op & UINT64_C(15)) << 28; 10125 // op: Rt 10126 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10127 Value |= (op & UINT64_C(15)) << 12; 10128 // op: addr 10129 op = getLdStSORegOpValue(MI, 2, Fixups, STI); 10130 Value |= (op & UINT64_C(4096)) << 11; 10131 Value |= (op & UINT64_C(122880)) << 3; 10132 Value |= op & UINT64_C(4064); 10133 Value |= op & UINT64_C(15); 10134 break; 10135 } 10136 case ARM::STRBT_POST_REG: 10137 case ARM::STRB_POST_REG: 10138 case ARM::STRT_POST_REG: 10139 case ARM::STR_POST_REG: { 10140 // op: p 10141 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10142 Value |= (op & UINT64_C(15)) << 28; 10143 // op: Rt 10144 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10145 Value |= (op & UINT64_C(15)) << 12; 10146 // op: offset 10147 op = getAddrMode2OffsetOpValue(MI, 3, Fixups, STI); 10148 Value |= (op & UINT64_C(4096)) << 11; 10149 Value |= op & UINT64_C(4064); 10150 Value |= op & UINT64_C(15); 10151 // op: addr 10152 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10153 Value |= (op & UINT64_C(15)) << 16; 10154 break; 10155 } 10156 case ARM::STRBT_POST_IMM: 10157 case ARM::STRB_POST_IMM: 10158 case ARM::STRT_POST_IMM: 10159 case ARM::STR_POST_IMM: { 10160 // op: p 10161 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10162 Value |= (op & UINT64_C(15)) << 28; 10163 // op: Rt 10164 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10165 Value |= (op & UINT64_C(15)) << 12; 10166 // op: offset 10167 op = getAddrMode2OffsetOpValue(MI, 3, Fixups, STI); 10168 Value |= (op & UINT64_C(4096)) << 11; 10169 Value |= op & UINT64_C(4095); 10170 // op: addr 10171 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10172 Value |= (op & UINT64_C(15)) << 16; 10173 break; 10174 } 10175 case ARM::STRH_POST: { 10176 // op: p 10177 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10178 Value |= (op & UINT64_C(15)) << 28; 10179 // op: Rt 10180 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10181 Value |= (op & UINT64_C(15)) << 12; 10182 // op: offset 10183 op = getAddrMode3OffsetOpValue(MI, 3, Fixups, STI); 10184 Value |= (op & UINT64_C(256)) << 15; 10185 Value |= (op & UINT64_C(512)) << 13; 10186 Value |= (op & UINT64_C(240)) << 4; 10187 Value |= op & UINT64_C(15); 10188 // op: addr 10189 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10190 Value |= (op & UINT64_C(15)) << 16; 10191 break; 10192 } 10193 case ARM::MCRR: { 10194 // op: p 10195 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10196 Value |= (op & UINT64_C(15)) << 28; 10197 // op: Rt 10198 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10199 Value |= (op & UINT64_C(15)) << 12; 10200 // op: Rt2 10201 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10202 Value |= (op & UINT64_C(15)) << 16; 10203 // op: cop 10204 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10205 Value |= (op & UINT64_C(15)) << 8; 10206 // op: opc1 10207 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10208 Value |= (op & UINT64_C(15)) << 4; 10209 // op: CRm 10210 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 10211 Value |= op & UINT64_C(15); 10212 break; 10213 } 10214 case ARM::LDRD: 10215 case ARM::STRD: { 10216 // op: p 10217 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10218 Value |= (op & UINT64_C(15)) << 28; 10219 // op: addr 10220 op = getAddrMode3OpValue(MI, 2, Fixups, STI); 10221 Value |= (op & UINT64_C(256)) << 15; 10222 Value |= (op & UINT64_C(8192)) << 9; 10223 Value |= (op & UINT64_C(7680)) << 7; 10224 Value |= (op & UINT64_C(240)) << 4; 10225 Value |= op & UINT64_C(15); 10226 // op: Rt 10227 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10228 Value |= (op & UINT64_C(15)) << 12; 10229 break; 10230 } 10231 case ARM::LDRHTr: 10232 case ARM::LDRSBTr: 10233 case ARM::LDRSHTr: { 10234 // op: p 10235 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10236 Value |= (op & UINT64_C(15)) << 28; 10237 // op: addr 10238 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10239 Value |= (op & UINT64_C(15)) << 16; 10240 // op: Rt 10241 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10242 Value |= (op & UINT64_C(15)) << 12; 10243 // op: Rm 10244 op = getPostIdxRegOpValue(MI, 3, Fixups, STI); 10245 Value |= (op & UINT64_C(16)) << 19; 10246 Value |= op & UINT64_C(15); 10247 break; 10248 } 10249 case ARM::STRHTr: { 10250 // op: p 10251 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10252 Value |= (op & UINT64_C(15)) << 28; 10253 // op: addr 10254 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10255 Value |= (op & UINT64_C(15)) << 16; 10256 // op: Rt 10257 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10258 Value |= (op & UINT64_C(15)) << 12; 10259 // op: Rm 10260 op = getPostIdxRegOpValue(MI, 3, Fixups, STI); 10261 Value |= (op & UINT64_C(16)) << 19; 10262 Value |= op & UINT64_C(15); 10263 break; 10264 } 10265 case ARM::ADCrsr: 10266 case ARM::ADDrsr: 10267 case ARM::ANDrsr: 10268 case ARM::BICrsr: 10269 case ARM::EORrsr: 10270 case ARM::ORRrsr: 10271 case ARM::RSBrsr: 10272 case ARM::RSCrsr: 10273 case ARM::SBCrsr: 10274 case ARM::SUBrsr: { 10275 // op: p 10276 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10277 Value |= (op & UINT64_C(15)) << 28; 10278 // op: s 10279 op = getCCOutOpValue(MI, 7, Fixups, STI); 10280 Value |= (op & UINT64_C(1)) << 20; 10281 // op: Rd 10282 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10283 Value |= (op & UINT64_C(15)) << 12; 10284 // op: Rn 10285 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10286 Value |= (op & UINT64_C(15)) << 16; 10287 // op: shift 10288 op = getSORegRegOpValue(MI, 2, Fixups, STI); 10289 Value |= op & UINT64_C(3840); 10290 Value |= op & UINT64_C(96); 10291 Value |= op & UINT64_C(15); 10292 break; 10293 } 10294 case ARM::LDRD_PRE: { 10295 // op: p 10296 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 10297 Value |= (op & UINT64_C(15)) << 28; 10298 // op: Rt 10299 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10300 Value |= (op & UINT64_C(15)) << 12; 10301 // op: addr 10302 op = getAddrMode3OpValue(MI, 3, Fixups, STI); 10303 Value |= (op & UINT64_C(256)) << 15; 10304 Value |= (op & UINT64_C(8192)) << 9; 10305 Value |= (op & UINT64_C(7680)) << 7; 10306 Value |= (op & UINT64_C(240)) << 4; 10307 Value |= op & UINT64_C(15); 10308 break; 10309 } 10310 case ARM::MRC: { 10311 // op: p 10312 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 10313 Value |= (op & UINT64_C(15)) << 28; 10314 // op: Rt 10315 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10316 Value |= (op & UINT64_C(15)) << 12; 10317 // op: cop 10318 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10319 Value |= (op & UINT64_C(15)) << 8; 10320 // op: opc1 10321 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10322 Value |= (op & UINT64_C(7)) << 21; 10323 // op: opc2 10324 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10325 Value |= (op & UINT64_C(7)) << 5; 10326 // op: CRm 10327 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 10328 Value |= op & UINT64_C(15); 10329 // op: CRn 10330 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10331 Value |= (op & UINT64_C(15)) << 16; 10332 break; 10333 } 10334 case ARM::LDRD_POST: { 10335 // op: p 10336 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 10337 Value |= (op & UINT64_C(15)) << 28; 10338 // op: Rt 10339 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10340 Value |= (op & UINT64_C(15)) << 12; 10341 // op: offset 10342 op = getAddrMode3OffsetOpValue(MI, 4, Fixups, STI); 10343 Value |= (op & UINT64_C(256)) << 15; 10344 Value |= (op & UINT64_C(512)) << 13; 10345 Value |= (op & UINT64_C(240)) << 4; 10346 Value |= op & UINT64_C(15); 10347 // op: addr 10348 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10349 Value |= (op & UINT64_C(15)) << 16; 10350 break; 10351 } 10352 case ARM::STRD_PRE: { 10353 // op: p 10354 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 10355 Value |= (op & UINT64_C(15)) << 28; 10356 // op: Rt 10357 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10358 Value |= (op & UINT64_C(15)) << 12; 10359 // op: addr 10360 op = getAddrMode3OpValue(MI, 3, Fixups, STI); 10361 Value |= (op & UINT64_C(256)) << 15; 10362 Value |= (op & UINT64_C(8192)) << 9; 10363 Value |= (op & UINT64_C(7680)) << 7; 10364 Value |= (op & UINT64_C(240)) << 4; 10365 Value |= op & UINT64_C(15); 10366 break; 10367 } 10368 case ARM::STRD_POST: { 10369 // op: p 10370 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 10371 Value |= (op & UINT64_C(15)) << 28; 10372 // op: Rt 10373 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10374 Value |= (op & UINT64_C(15)) << 12; 10375 // op: offset 10376 op = getAddrMode3OffsetOpValue(MI, 4, Fixups, STI); 10377 Value |= (op & UINT64_C(256)) << 15; 10378 Value |= (op & UINT64_C(512)) << 13; 10379 Value |= (op & UINT64_C(240)) << 4; 10380 Value |= op & UINT64_C(15); 10381 // op: addr 10382 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10383 Value |= (op & UINT64_C(15)) << 16; 10384 break; 10385 } 10386 case ARM::MCR: { 10387 // op: p 10388 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 10389 Value |= (op & UINT64_C(15)) << 28; 10390 // op: Rt 10391 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10392 Value |= (op & UINT64_C(15)) << 12; 10393 // op: cop 10394 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10395 Value |= (op & UINT64_C(15)) << 8; 10396 // op: opc1 10397 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10398 Value |= (op & UINT64_C(7)) << 21; 10399 // op: opc2 10400 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10401 Value |= (op & UINT64_C(7)) << 5; 10402 // op: CRm 10403 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 10404 Value |= op & UINT64_C(15); 10405 // op: CRn 10406 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10407 Value |= (op & UINT64_C(15)) << 16; 10408 break; 10409 } 10410 case ARM::CDP: { 10411 // op: p 10412 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 10413 Value |= (op & UINT64_C(15)) << 28; 10414 // op: opc1 10415 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10416 Value |= (op & UINT64_C(15)) << 20; 10417 // op: CRn 10418 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10419 Value |= (op & UINT64_C(15)) << 16; 10420 // op: CRd 10421 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10422 Value |= (op & UINT64_C(15)) << 12; 10423 // op: cop 10424 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10425 Value |= (op & UINT64_C(15)) << 8; 10426 // op: opc2 10427 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10428 Value |= (op & UINT64_C(7)) << 5; 10429 // op: CRm 10430 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 10431 Value |= op & UINT64_C(15); 10432 break; 10433 } 10434 case ARM::SMLAL: 10435 case ARM::UMLAL: { 10436 // op: p 10437 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 10438 Value |= (op & UINT64_C(15)) << 28; 10439 // op: s 10440 op = getCCOutOpValue(MI, 8, Fixups, STI); 10441 Value |= (op & UINT64_C(1)) << 20; 10442 // op: RdLo 10443 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10444 Value |= (op & UINT64_C(15)) << 12; 10445 // op: RdHi 10446 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10447 Value |= (op & UINT64_C(15)) << 16; 10448 // op: Rm 10449 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10450 Value |= (op & UINT64_C(15)) << 8; 10451 // op: Rn 10452 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10453 Value |= op & UINT64_C(15); 10454 break; 10455 } 10456 case ARM::tPUSH: { 10457 // op: regs 10458 op = getRegisterListOpValue(MI, 2, Fixups, STI); 10459 Value |= (op & UINT64_C(16384)) >> 6; 10460 Value |= op & UINT64_C(255); 10461 break; 10462 } 10463 case ARM::tPOP: { 10464 // op: regs 10465 op = getRegisterListOpValue(MI, 2, Fixups, STI); 10466 Value |= (op & UINT64_C(32768)) >> 7; 10467 Value |= op & UINT64_C(255); 10468 break; 10469 } 10470 case ARM::t2MOVr: 10471 case ARM::t2MVNr: 10472 case ARM::t2RRX: { 10473 // op: s 10474 op = getCCOutOpValue(MI, 4, Fixups, STI); 10475 Value |= (op & UINT64_C(1)) << 20; 10476 // op: Rd 10477 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10478 Value |= (op & UINT64_C(15)) << 8; 10479 // op: Rm 10480 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10481 Value |= op & UINT64_C(15); 10482 break; 10483 } 10484 case ARM::t2MOVi: 10485 case ARM::t2MVNi: { 10486 // op: s 10487 op = getCCOutOpValue(MI, 4, Fixups, STI); 10488 Value |= (op & UINT64_C(1)) << 20; 10489 // op: Rd 10490 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10491 Value |= (op & UINT64_C(15)) << 8; 10492 // op: imm 10493 op = getT2SOImmOpValue(MI, 1, Fixups, STI); 10494 Value |= (op & UINT64_C(2048)) << 15; 10495 Value |= (op & UINT64_C(1792)) << 4; 10496 Value |= op & UINT64_C(255); 10497 break; 10498 } 10499 case ARM::t2ASRri: 10500 case ARM::t2LSLri: 10501 case ARM::t2LSRri: 10502 case ARM::t2RORri: { 10503 // op: s 10504 op = getCCOutOpValue(MI, 5, Fixups, STI); 10505 Value |= (op & UINT64_C(1)) << 20; 10506 // op: Rd 10507 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10508 Value |= (op & UINT64_C(15)) << 8; 10509 // op: Rm 10510 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10511 Value |= op & UINT64_C(15); 10512 // op: imm 10513 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10514 Value |= (op & UINT64_C(28)) << 10; 10515 Value |= (op & UINT64_C(3)) << 6; 10516 break; 10517 } 10518 case ARM::t2ADCrr: 10519 case ARM::t2ADDrr: 10520 case ARM::t2ANDrr: 10521 case ARM::t2ASRrr: 10522 case ARM::t2BICrr: 10523 case ARM::t2EORrr: 10524 case ARM::t2LSLrr: 10525 case ARM::t2LSRrr: 10526 case ARM::t2ORNrr: 10527 case ARM::t2ORRrr: 10528 case ARM::t2RORrr: 10529 case ARM::t2RSBrr: 10530 case ARM::t2SBCrr: 10531 case ARM::t2SUBrr: { 10532 // op: s 10533 op = getCCOutOpValue(MI, 5, Fixups, STI); 10534 Value |= (op & UINT64_C(1)) << 20; 10535 // op: Rd 10536 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10537 Value |= (op & UINT64_C(15)) << 8; 10538 // op: Rn 10539 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10540 Value |= (op & UINT64_C(15)) << 16; 10541 // op: Rm 10542 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10543 Value |= op & UINT64_C(15); 10544 break; 10545 } 10546 case ARM::t2ADCri: 10547 case ARM::t2ADDri: 10548 case ARM::t2ANDri: 10549 case ARM::t2BICri: 10550 case ARM::t2EORri: 10551 case ARM::t2ORNri: 10552 case ARM::t2ORRri: 10553 case ARM::t2RSBri: 10554 case ARM::t2SBCri: 10555 case ARM::t2SUBri: { 10556 // op: s 10557 op = getCCOutOpValue(MI, 5, Fixups, STI); 10558 Value |= (op & UINT64_C(1)) << 20; 10559 // op: Rd 10560 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10561 Value |= (op & UINT64_C(15)) << 8; 10562 // op: Rn 10563 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10564 Value |= (op & UINT64_C(15)) << 16; 10565 // op: imm 10566 op = getT2SOImmOpValue(MI, 2, Fixups, STI); 10567 Value |= (op & UINT64_C(2048)) << 15; 10568 Value |= (op & UINT64_C(1792)) << 4; 10569 Value |= op & UINT64_C(255); 10570 break; 10571 } 10572 case ARM::t2MVNs: { 10573 // op: s 10574 op = getCCOutOpValue(MI, 5, Fixups, STI); 10575 Value |= (op & UINT64_C(1)) << 20; 10576 // op: Rd 10577 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10578 Value |= (op & UINT64_C(15)) << 8; 10579 // op: ShiftedRm 10580 op = getT2SORegOpValue(MI, 1, Fixups, STI); 10581 Value |= (op & UINT64_C(3584)) << 3; 10582 Value |= (op & UINT64_C(480)) >> 1; 10583 Value |= op & UINT64_C(15); 10584 break; 10585 } 10586 case ARM::t2ADCrs: 10587 case ARM::t2ADDrs: 10588 case ARM::t2ANDrs: 10589 case ARM::t2BICrs: 10590 case ARM::t2EORrs: 10591 case ARM::t2ORNrs: 10592 case ARM::t2ORRrs: 10593 case ARM::t2RSBrs: 10594 case ARM::t2SBCrs: 10595 case ARM::t2SUBrs: { 10596 // op: s 10597 op = getCCOutOpValue(MI, 6, Fixups, STI); 10598 Value |= (op & UINT64_C(1)) << 20; 10599 // op: Rd 10600 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10601 Value |= (op & UINT64_C(15)) << 8; 10602 // op: Rn 10603 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10604 Value |= (op & UINT64_C(15)) << 16; 10605 // op: ShiftedRm 10606 op = getT2SORegOpValue(MI, 2, Fixups, STI); 10607 Value |= (op & UINT64_C(3584)) << 3; 10608 Value |= (op & UINT64_C(480)) >> 1; 10609 Value |= op & UINT64_C(15); 10610 break; 10611 } 10612 case ARM::PLDWrs: 10613 case ARM::PLDrs: 10614 case ARM::PLIrs: { 10615 // op: shift 10616 op = getLdStSORegOpValue(MI, 0, Fixups, STI); 10617 Value |= (op & UINT64_C(4096)) << 11; 10618 Value |= (op & UINT64_C(122880)) << 3; 10619 Value |= op & UINT64_C(4064); 10620 Value |= op & UINT64_C(15); 10621 break; 10622 } 10623 case ARM::BLXi: { 10624 // op: target 10625 op = getARMBLXTargetOpValue(MI, 0, Fixups, STI); 10626 Value |= (op & UINT64_C(1)) << 24; 10627 Value |= (op & UINT64_C(33554430)) >> 1; 10628 break; 10629 } 10630 case ARM::tB: { 10631 // op: target 10632 op = getThumbBRTargetOpValue(MI, 0, Fixups, STI); 10633 Value |= op & UINT64_C(2047); 10634 break; 10635 } 10636 case ARM::tCBNZ: 10637 case ARM::tCBZ: { 10638 // op: target 10639 op = getThumbCBTargetOpValue(MI, 1, Fixups, STI); 10640 Value |= (op & UINT64_C(32)) << 4; 10641 Value |= (op & UINT64_C(31)) << 3; 10642 // op: Rn 10643 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10644 Value |= op & UINT64_C(7); 10645 break; 10646 } 10647 case ARM::t2B: { 10648 // op: target 10649 op = getUnconditionalBranchTargetOpValue(MI, 0, Fixups, STI); 10650 Value |= (op & UINT64_C(8388608)) << 3; 10651 Value |= (op & UINT64_C(2095104)) << 5; 10652 Value |= (op & UINT64_C(4194304)) >> 9; 10653 Value |= (op & UINT64_C(2097152)) >> 10; 10654 Value |= op & UINT64_C(2047); 10655 break; 10656 } 10657 case ARM::BKPT: 10658 case ARM::HLT: { 10659 // op: val 10660 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10661 Value |= (op & UINT64_C(65520)) << 4; 10662 Value |= op & UINT64_C(15); 10663 break; 10664 } 10665 case ARM::tBKPT: { 10666 // op: val 10667 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10668 Value |= op & UINT64_C(255); 10669 break; 10670 } 10671 case ARM::tHLT: { 10672 // op: val 10673 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10674 Value |= op & UINT64_C(63); 10675 break; 10676 } 10677 default: 10678 std::string msg; 10679 raw_string_ostream Msg(msg); 10680 Msg << "Not supported instr: " << MI; 10681 report_fatal_error(Msg.str()); 10682 } 10683 return Value; 10684} 10685 10686