1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|*                                                                            *|
3|* Assembly Matcher Source Fragment                                           *|
4|*                                                                            *|
5|* Automatically generated file, do not edit!                                 *|
6|*                                                                            *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_ASSEMBLER_HEADER
11#undef GET_ASSEMBLER_HEADER
12  // This should be included into the middle of the declaration of
13  // your subclasses implementation of MCTargetAsmParser.
14  uint64_t ComputeAvailableFeatures(const FeatureBitset& FB) const;
15  void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
16                       const OperandVector &Operands);
17  void convertToMapAndConstraints(unsigned Kind,
18                           const OperandVector &Operands) override;
19  bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID);
20  unsigned MatchInstructionImpl(const OperandVector &Operands,
21                                MCInst &Inst,
22                                uint64_t &ErrorInfo, bool matchingInlineAsm,
23                                unsigned VariantID = 0);
24
25  enum OperandMatchResultTy {
26    MatchOperand_Success,    // operand matched successfully
27    MatchOperand_NoMatch,    // operand did not match
28    MatchOperand_ParseFail   // operand matched but had errors
29  };
30  OperandMatchResultTy MatchOperandParserImpl(
31    OperandVector &Operands,
32    StringRef Mnemonic);
33  OperandMatchResultTy tryCustomParseOperand(
34    OperandVector &Operands,
35    unsigned MCK);
36
37#endif // GET_ASSEMBLER_HEADER_INFO
38
39
40#ifdef GET_OPERAND_DIAGNOSTIC_TYPES
41#undef GET_OPERAND_DIAGNOSTIC_TYPES
42
43  Match_Immz,
44  Match_SImm6,
45  Match_UImm10_0,
46  Match_UImm16,
47  Match_UImm16_Relaxed,
48  Match_UImm1_0,
49  Match_UImm2_0,
50  Match_UImm2_1,
51  Match_UImm3_0,
52  Match_UImm4_0,
53  Match_UImm5_0,
54  Match_UImm5_0_Report_UImm6,
55  Match_UImm5_1,
56  Match_UImm5_32,
57  Match_UImm5_33,
58  Match_UImm5_Lsl2,
59  Match_UImm6_0,
60  Match_UImm7_0,
61  Match_UImm8_0,
62  END_OPERAND_DIAGNOSTIC_TYPES
63#endif // GET_OPERAND_DIAGNOSTIC_TYPES
64
65
66#ifdef GET_REGISTER_MATCHER
67#undef GET_REGISTER_MATCHER
68
69// Flags for subtarget features that participate in instruction matching.
70enum SubtargetFeatureFlag : uint64_t {
71  Feature_HasMips2 = (1ULL << 8),
72  Feature_HasMips3_32 = (1ULL << 14),
73  Feature_HasMips3_32r2 = (1ULL << 15),
74  Feature_HasMips3 = (1ULL << 9),
75  Feature_HasMips4_32 = (1ULL << 16),
76  Feature_NotMips4_32 = (1ULL << 34),
77  Feature_HasMips4_32r2 = (1ULL << 17),
78  Feature_HasMips5_32r2 = (1ULL << 18),
79  Feature_HasMips32 = (1ULL << 10),
80  Feature_HasMips32r2 = (1ULL << 11),
81  Feature_HasMips32r5 = (1ULL << 12),
82  Feature_HasMips32r6 = (1ULL << 13),
83  Feature_NotMips32r6 = (1ULL << 33),
84  Feature_IsGP64bit = (1ULL << 27),
85  Feature_IsGP32bit = (1ULL << 26),
86  Feature_HasMips64 = (1ULL << 19),
87  Feature_NotMips64 = (1ULL << 35),
88  Feature_HasMips64r2 = (1ULL << 20),
89  Feature_HasMips64r6 = (1ULL << 21),
90  Feature_NotMips64r6 = (1ULL << 36),
91  Feature_HasMicroMips32r6 = (1ULL << 6),
92  Feature_HasMicroMips64r6 = (1ULL << 7),
93  Feature_InMips16Mode = (1ULL << 24),
94  Feature_HasCnMips = (1ULL << 0),
95  Feature_HasStdEnc = (1ULL << 22),
96  Feature_InMicroMips = (1ULL << 23),
97  Feature_NotInMicroMips = (1ULL << 32),
98  Feature_HasEVA = (1ULL << 4),
99  Feature_HasMSA = (1ULL << 5),
100  Feature_IsFP64bit = (1ULL << 25),
101  Feature_NotFP64bit = (1ULL << 31),
102  Feature_IsSingleFloat = (1ULL << 30),
103  Feature_IsNotSingleFloat = (1ULL << 28),
104  Feature_IsNotSoftFloat = (1ULL << 29),
105  Feature_HasDSP = (1ULL << 1),
106  Feature_HasDSPR2 = (1ULL << 2),
107  Feature_HasDSPR3 = (1ULL << 3),
108  Feature_None = 0
109};
110
111#endif // GET_REGISTER_MATCHER
112
113
114#ifdef GET_SUBTARGET_FEATURE_NAME
115#undef GET_SUBTARGET_FEATURE_NAME
116
117// User-level names for subtarget features that participate in
118// instruction matching.
119static const char *getSubtargetFeatureName(uint64_t Val) {
120  switch(Val) {
121  case Feature_HasMips2: return "";
122  case Feature_HasMips3_32: return "";
123  case Feature_HasMips3_32r2: return "";
124  case Feature_HasMips3: return "";
125  case Feature_HasMips4_32: return "";
126  case Feature_NotMips4_32: return "";
127  case Feature_HasMips4_32r2: return "";
128  case Feature_HasMips5_32r2: return "";
129  case Feature_HasMips32: return "";
130  case Feature_HasMips32r2: return "";
131  case Feature_HasMips32r5: return "";
132  case Feature_HasMips32r6: return "";
133  case Feature_NotMips32r6: return "";
134  case Feature_IsGP64bit: return "";
135  case Feature_IsGP32bit: return "";
136  case Feature_HasMips64: return "";
137  case Feature_NotMips64: return "";
138  case Feature_HasMips64r2: return "";
139  case Feature_HasMips64r6: return "";
140  case Feature_NotMips64r6: return "";
141  case Feature_HasMicroMips32r6: return "";
142  case Feature_HasMicroMips64r6: return "";
143  case Feature_InMips16Mode: return "";
144  case Feature_HasCnMips: return "";
145  case Feature_HasStdEnc: return "";
146  case Feature_InMicroMips: return "";
147  case Feature_NotInMicroMips: return "";
148  case Feature_HasEVA: return "";
149  case Feature_HasMSA: return "";
150  case Feature_IsFP64bit: return "";
151  case Feature_NotFP64bit: return "";
152  case Feature_IsSingleFloat: return "";
153  case Feature_IsNotSingleFloat: return "";
154  case Feature_IsNotSoftFloat: return "";
155  case Feature_HasDSP: return "";
156  case Feature_HasDSPR2: return "";
157  case Feature_HasDSPR3: return "";
158  default: return "(unknown)";
159  }
160}
161
162#endif // GET_SUBTARGET_FEATURE_NAME
163
164
165#ifdef GET_MATCHER_IMPLEMENTATION
166#undef GET_MATCHER_IMPLEMENTATION
167
168namespace {
169enum OperatorConversionKind {
170  CVT_Done,
171  CVT_Reg,
172  CVT_Tied,
173  CVT_95_addGPR32AsmRegOperands,
174  CVT_95_addAFGR64AsmRegOperands,
175  CVT_95_addFGR64AsmRegOperands,
176  CVT_95_addFGR32AsmRegOperands,
177  CVT_95_addImmOperands,
178  CVT_95_addMSA128AsmRegOperands,
179  CVT_95_Reg,
180  CVT_95_addGPRMM16AsmRegOperands,
181  CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_,
182  CVT_95_addUImmOperands_LT_16_GT_,
183  CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_,
184  CVT_regZERO,
185  CVT_95_addGPR64AsmRegOperands,
186  CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_,
187  CVT_regFCC0,
188  CVT_95_addFCCAsmRegOperands,
189  CVT_95_addCOP2AsmRegOperands,
190  CVT_imm_95_0,
191  CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_,
192  CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_,
193  CVT_95_addMemOperands,
194  CVT_95_addCCRAsmRegOperands,
195  CVT_95_addMSACtrlAsmRegOperands,
196  CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_,
197  CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_,
198  CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_,
199  CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_,
200  CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_,
201  CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_,
202  CVT_95_addCOP0AsmRegOperands,
203  CVT_regZERO_64,
204  CVT_95_addACC64DSPAsmRegOperands,
205  CVT_95_addConstantUImmOperands_LT_1_GT_,
206  CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_,
207  CVT_regRA,
208  CVT_95_addMicroMipsMemOperands,
209  CVT_95_addCOP3AsmRegOperands,
210  CVT_95_addRegListOperands,
211  CVT_95_addRegPairOperands,
212  CVT_95_addMovePRegPairOperands,
213  CVT_95_addGPRMM16AsmRegMovePOperands,
214  CVT_95_addHI32DSPAsmRegOperands,
215  CVT_95_addLO32DSPAsmRegOperands,
216  CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_,
217  CVT_95_addHWRegsAsmRegOperands,
218  CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_,
219  CVT_95_addGPRMM16AsmRegZeroOperands,
220  CVT_imm_95_2,
221  CVT_imm_95_6,
222  CVT_imm_95_4,
223  CVT_imm_95_5,
224  CVT_imm_95_31,
225  CVT_NUM_CONVERTERS
226};
227
228enum InstructionConversionKind {
229  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1,
230  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1,
231  Convert__FGR64AsmReg1_0__FGR64AsmReg1_1,
232  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1,
233  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1,
234  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__Imm1_1,
235  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2,
236  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__Imm1_2,
237  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2,
238  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_2__AFGR64AsmReg1_1,
239  Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2,
240  Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1,
241  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2,
242  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2,
243  Convert__Imm1_1,
244  Convert__Reg1_0__Imm1_1,
245  Convert__Reg1_0__Imm1_2,
246  Convert__Reg1_0__Reg1_1__Imm1_2,
247  Convert__Reg1_0__Tie0__Imm1_1,
248  Convert__GPR32AsmReg1_0__JumpTarget1_1,
249  Convert__GPRMM16AsmReg1_0__Imm1_1,
250  Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2,
251  Convert__GPR32AsmReg1_0__Tie0__Imm1_1,
252  Convert__Imm1_0,
253  Convert__Reg1_0__Reg1_1__Reg1_2,
254  Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2,
255  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2,
256  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3,
257  Convert__GPR32AsmReg1_0__Imm1_1,
258  Convert__Reg1_0__Tie0__Reg1_1,
259  Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0,
260  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1,
261  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2,
262  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0,
263  Convert__JumpTarget1_0,
264  Convert__regZERO__regZERO__JumpTarget1_0,
265  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1,
266  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2,
267  Convert__regZERO__JumpTarget1_0,
268  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0,
269  Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2,
270  Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2,
271  Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2,
272  Convert__FGR64AsmReg1_0__JumpTarget1_1,
273  Convert__regFCC0__JumpTarget1_0,
274  Convert__FCCAsmReg1_0__JumpTarget1_1,
275  Convert__COP2AsmReg1_0__JumpTarget1_1,
276  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2,
277  Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2,
278  Convert__Reg1_0__JumpTarget1_1,
279  Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1,
280  Convert__GPRMM16AsmReg1_0__JumpTarget1_1,
281  Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2,
282  Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__Imm1_2,
283  Convert__MSA128AsmReg1_0__JumpTarget1_1,
284  Convert__imm_95_0__imm_95_0,
285  Convert_NoOperands,
286  Convert__ConstantUImm10_01_0__imm_95_0,
287  Convert__ConstantUImm10_01_0__ConstantUImm10_01_1,
288  Convert__ConstantUImm4_01_0,
289  Convert__MemOffsetSimm92_1__ConstantUImm5_01_0,
290  Convert__Mem2_1__ConstantUImm5_01_0,
291  Convert__FGR64AsmReg1_0__FGR32AsmReg1_1,
292  Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1,
293  Convert__FGR32AsmReg1_0__FGR64AsmReg1_1,
294  Convert__GPR32AsmReg1_0__CCRAsmReg1_1,
295  Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1,
296  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2,
297  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2,
298  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3,
299  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3,
300  Convert__Reg1_0__Reg1_1,
301  Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2,
302  Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__Imm1_3,
303  Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__Imm1_3,
304  Convert__CCRAsmReg1_1__GPR32AsmReg1_0,
305  Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1,
306  Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1,
307  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1,
308  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2,
309  Convert__GPR64AsmReg1_0__Tie0__Imm1_1,
310  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3,
311  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1,
312  Convert__GPR64AsmReg1_1__GPR64AsmReg1_2,
313  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3,
314  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3,
315  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3,
316  Convert__regZERO,
317  Convert__GPR32AsmReg1_0,
318  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__Imm1_3__Tie0,
319  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__Imm1_3__Tie0,
320  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__Imm1_3__Tie0,
321  Convert__Reg1_1__Reg1_2,
322  Convert__GPR32AsmReg1_1__GPR32AsmReg1_2,
323  Convert__GPR64AsmReg1_0__Imm1_1,
324  Convert__GPR64AsmReg1_0__Mem2_1,
325  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3,
326  Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0,
327  Convert__GPR64AsmReg1_0__COP0AsmReg1_1__UImm161_2,
328  Convert__GPR64AsmReg1_0__FGR64AsmReg1_1,
329  Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0,
330  Convert__GPR64AsmReg1_0__UImm161_1,
331  Convert__GPR64AsmReg1_0__COP2AsmReg1_1__UImm161_2,
332  Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0,
333  Convert__COP0AsmReg1_1__GPR64AsmReg1_0__UImm161_2,
334  Convert__FGR64AsmReg1_1__GPR64AsmReg1_0,
335  Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0,
336  Convert__COP2AsmReg1_1__GPR64AsmReg1_0__UImm161_2,
337  Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0,
338  Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1,
339  Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0,
340  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0,
341  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1,
342  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2,
343  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1,
344  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2,
345  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2,
346  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1,
347  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2,
348  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3,
349  Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2,
350  Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2,
351  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1,
352  Convert__MSA128AsmReg1_0__GPR32AsmReg1_1,
353  Convert__MSA128AsmReg1_0__GPR64AsmReg1_1,
354  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Imm1_3__Tie0,
355  Convert__MSA128AsmReg1_0__Tie0__GPR32AsmReg1_4__Imm1_2,
356  Convert__MSA128AsmReg1_0__Tie0__GPR64AsmReg1_4__Imm1_2,
357  Convert__GPR32AsmReg1_0__Tie0__GPR32AsmReg1_1,
358  Convert__MSA128AsmReg1_0__Tie0__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
359  Convert__MSA128AsmReg1_0__Tie0__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
360  Convert__MSA128AsmReg1_0__Tie0__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
361  Convert__MSA128AsmReg1_0__Tie0__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
362  Convert__regRA__GPR32AsmReg1_0,
363  Convert__Reg1_0,
364  Convert__regZERO__GPR32AsmReg1_0,
365  Convert__regZERO_64__GPR64AsmReg1_0,
366  Convert__UImm5Lsl21_0,
367  Convert__GPR32AsmReg1_0__Mem2_1,
368  Convert__GPR32AsmReg1_0__MemOffsetSimm92_1,
369  Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1,
370  Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
371  Convert__MSA128AsmReg1_0__Mem2_1,
372  Convert__AFGR64AsmReg1_0__Mem2_1,
373  Convert__FGR64AsmReg1_0__Mem2_1,
374  Convert__COP2AsmReg1_0__MemOffsetSimm112_1,
375  Convert__COP2AsmReg1_0__Mem2_1,
376  Convert__COP3AsmReg1_0__Mem2_1,
377  Convert__MSA128AsmReg1_0__Imm1_1,
378  Convert__GPR64AsmReg1_0__Mem2_1__Tie0,
379  Convert__GPR64AsmReg1_0__JumpTarget1_1,
380  Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
381  Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
382  Convert__GPR64AsmReg1_0__MemOffsetSimm92_1,
383  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3,
384  Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3,
385  Convert__GPR32AsmReg1_0__UImm161_1,
386  Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1,
387  Convert__Reg1_0__Imm1_1__imm_95_0,
388  Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1,
389  Convert__GPRMM16AsmReg1_0__Reg1_1__Imm1_2,
390  Convert__Reg1_0__Reg1_3__Imm1_1,
391  Convert__FGR32AsmReg1_0__Mem2_1,
392  Convert__GPR32AsmReg1_0__Mem2_1__Tie0,
393  Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0,
394  Convert__RegList1_0__Mem2_1,
395  Convert__RegList161_0__MemOffsetUimm42_1,
396  Convert__RegPair2_0__Mem2_1,
397  Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
398  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3,
399  Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3,
400  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3,
401  Convert__FGR64AsmReg1_0__Tie0__FGR64AsmReg1_1__FGR64AsmReg1_2,
402  Convert__FGR32AsmReg1_0__Tie0__FGR32AsmReg1_1__FGR32AsmReg1_2,
403  Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0,
404  Convert__GPR32AsmReg1_0__COP0AsmReg1_1__UImm161_2,
405  Convert__GPR32AsmReg1_0__FGR32AsmReg1_1,
406  Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0,
407  Convert__GPR32AsmReg1_0__COP2AsmReg1_1__UImm161_2,
408  Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1,
409  Convert__GPR32AsmReg1_0__FGR64AsmReg1_1,
410  Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1,
411  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO,
412  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64,
413  Convert__MovePRegPair2_0__GPRMM16AsmRegMoveP1_1__GPRMM16AsmRegMoveP1_2,
414  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0,
415  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0,
416  Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0,
417  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0,
418  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0,
419  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0,
420  Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0,
421  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0,
422  Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0,
423  Convert__COP0AsmReg1_1__GPR32AsmReg1_0__UImm161_2,
424  Convert__FGR32AsmReg1_1__GPR32AsmReg1_0,
425  Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0,
426  Convert__COP2AsmReg1_1__GPR32AsmReg1_0__UImm161_2,
427  Convert__AFGR64AsmReg1_1__Tie0__GPR32AsmReg1_0,
428  Convert__FGR64AsmReg1_1__Tie0__GPR32AsmReg1_0,
429  Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0,
430  Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0,
431  Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0,
432  Convert__GPR64AsmReg1_0,
433  Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2,
434  Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1,
435  Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0,
436  Convert__regZERO__regZERO__imm_95_0,
437  Convert__regZERO__regZERO,
438  Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1,
439  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0,
440  Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0,
441  Convert__GPR32AsmReg1_0__ConstantUImm7_01_1,
442  Convert__GPR32AsmReg1_0__ConstantUImm10_01_1,
443  Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1,
444  Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0,
445  Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2,
446  Convert__GPR32AsmReg1_0__ConstantUImm8_01_1,
447  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1,
448  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2,
449  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2,
450  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2,
451  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2,
452  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2,
453  Convert__Reg1_0__Reg1_1__Imm1_2__Reg1_3,
454  Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1,
455  Convert__GPR32AsmReg1_0__Tie0__MemOffsetSimm92_1,
456  Convert__GPR32AsmReg1_0__Tie0__Mem2_1,
457  Convert__GPR64AsmReg1_0__Tie0__MemOffsetSimm92_1,
458  Convert__GPR64AsmReg1_0__Tie0__Mem2_1,
459  Convert__imm_95_0,
460  Convert__Reg1_0__Tie0,
461  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2,
462  Convert__ACC64DSPAsmReg1_0__ConstantSImm61_1__Tie0,
463  Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0,
464  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2,
465  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2,
466  Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__GPR32AsmReg1_3,
467  Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm4_01_3,
468  Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm1_01_3,
469  Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm3_01_3,
470  Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm2_01_3,
471  Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2,
472  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3,
473  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_3,
474  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1,
475  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2,
476  Convert__GPR32AsmReg1_0__MemOffsetSimm9GPR2_1,
477  Convert__MemOffsetSimm162_0,
478  Convert__imm_95_2,
479  Convert__imm_95_6,
480  Convert__imm_95_4,
481  Convert__imm_95_5,
482  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0,
483  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2,
484  Convert__ConstantUImm10_01_0,
485  Convert__GPR32AsmReg1_0__imm_95_31,
486  CVT_NUM_SIGNATURES
487};
488
489} // end anonymous namespace
490
491static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][11] = {
492  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1
493  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
494  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1
495  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
496  // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1
497  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
498  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1
499  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
500  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1
501  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
502  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__Imm1_1
503  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
504  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2
505  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
506  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__Imm1_2
507  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
508  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2
509  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_Done },
510  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_2__AFGR64AsmReg1_1
511  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 3, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
512  // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2
513  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
514  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1
515  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 3, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
516  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2
517  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
518  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2
519  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addMSA128AsmRegOperands, 3, CVT_Done },
520  // Convert__Imm1_1
521  { CVT_95_addImmOperands, 2, CVT_Done },
522  // Convert__Reg1_0__Imm1_1
523  { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
524  // Convert__Reg1_0__Imm1_2
525  { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_Done },
526  // Convert__Reg1_0__Reg1_1__Imm1_2
527  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
528  // Convert__Reg1_0__Tie0__Imm1_1
529  { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_addImmOperands, 2, CVT_Done },
530  // Convert__GPR32AsmReg1_0__JumpTarget1_1
531  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
532  // Convert__GPRMM16AsmReg1_0__Imm1_1
533  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
534  // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2
535  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
536  // Convert__GPR32AsmReg1_0__Tie0__Imm1_1
537  { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addImmOperands, 2, CVT_Done },
538  // Convert__Imm1_0
539  { CVT_95_addImmOperands, 1, CVT_Done },
540  // Convert__Reg1_0__Reg1_1__Reg1_2
541  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
542  // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2
543  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_95_addGPRMM16AsmRegOperands, 3, CVT_Done },
544  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2
545  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
546  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3
547  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
548  // Convert__GPR32AsmReg1_0__Imm1_1
549  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
550  // Convert__Reg1_0__Tie0__Reg1_1
551  { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 2, CVT_Done },
552  // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0
553  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_Tied, 0, CVT_Done },
554  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1
555  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
556  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2
557  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done },
558  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0
559  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Tied, 0, CVT_Done },
560  // Convert__JumpTarget1_0
561  { CVT_95_addImmOperands, 1, CVT_Done },
562  // Convert__regZERO__regZERO__JumpTarget1_0
563  { CVT_regZERO, 0, CVT_regZERO, 0, CVT_95_addImmOperands, 1, CVT_Done },
564  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1
565  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
566  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2
567  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done },
568  // Convert__regZERO__JumpTarget1_0
569  { CVT_regZERO, 0, CVT_95_addImmOperands, 1, CVT_Done },
570  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0
571  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_Tied, 0, CVT_Done },
572  // Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2
573  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done },
574  // Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2
575  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done },
576  // Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2
577  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done },
578  // Convert__FGR64AsmReg1_0__JumpTarget1_1
579  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
580  // Convert__regFCC0__JumpTarget1_0
581  { CVT_regFCC0, 0, CVT_95_addImmOperands, 1, CVT_Done },
582  // Convert__FCCAsmReg1_0__JumpTarget1_1
583  { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
584  // Convert__COP2AsmReg1_0__JumpTarget1_1
585  { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
586  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2
587  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
588  // Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2
589  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
590  // Convert__Reg1_0__JumpTarget1_1
591  { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
592  // Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1
593  { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addImmOperands, 2, CVT_Done },
594  // Convert__GPRMM16AsmReg1_0__JumpTarget1_1
595  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
596  // Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2
597  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addMSA128AsmRegOperands, 3, CVT_Done },
598  // Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__Imm1_2
599  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
600  // Convert__MSA128AsmReg1_0__JumpTarget1_1
601  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
602  // Convert__imm_95_0__imm_95_0
603  { CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
604  // Convert_NoOperands
605  { CVT_Done },
606  // Convert__ConstantUImm10_01_0__imm_95_0
607  { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_imm_95_0, 0, CVT_Done },
608  // Convert__ConstantUImm10_01_0__ConstantUImm10_01_1
609  { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
610  // Convert__ConstantUImm4_01_0
611  { CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 1, CVT_Done },
612  // Convert__MemOffsetSimm92_1__ConstantUImm5_01_0
613  { CVT_95_addMemOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
614  // Convert__Mem2_1__ConstantUImm5_01_0
615  { CVT_95_addMemOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
616  // Convert__FGR64AsmReg1_0__FGR32AsmReg1_1
617  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
618  // Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1
619  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
620  // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1
621  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
622  // Convert__GPR32AsmReg1_0__CCRAsmReg1_1
623  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCCRAsmRegOperands, 2, CVT_Done },
624  // Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1
625  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSACtrlAsmRegOperands, 2, CVT_Done },
626  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2
627  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
628  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2
629  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
630  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3
631  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 4, CVT_Done },
632  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3
633  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 4, CVT_Done },
634  // Convert__Reg1_0__Reg1_1
635  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
636  // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2
637  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
638  // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__Imm1_3
639  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addImmOperands, 4, CVT_Done },
640  // Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__Imm1_3
641  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addImmOperands, 4, CVT_Done },
642  // Convert__CCRAsmReg1_1__GPR32AsmReg1_0
643  { CVT_95_addCCRAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
644  // Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1
645  { CVT_95_addMSACtrlAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
646  // Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1
647  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
648  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1
649  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
650  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2
651  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
652  // Convert__GPR64AsmReg1_0__Tie0__Imm1_1
653  { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addImmOperands, 2, CVT_Done },
654  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3
655  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
656  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1
657  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
658  // Convert__GPR64AsmReg1_1__GPR64AsmReg1_2
659  { CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done },
660  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3
661  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done },
662  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3
663  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_, 4, CVT_Done },
664  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3
665  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done },
666  // Convert__regZERO
667  { CVT_regZERO, 0, CVT_Done },
668  // Convert__GPR32AsmReg1_0
669  { CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
670  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__Imm1_3__Tie0
671  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_95_addImmOperands, 4, CVT_Tied, 0, CVT_Done },
672  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__Imm1_3__Tie0
673  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addImmOperands, 4, CVT_Tied, 0, CVT_Done },
674  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__Imm1_3__Tie0
675  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_, 3, CVT_95_addImmOperands, 4, CVT_Tied, 0, CVT_Done },
676  // Convert__Reg1_1__Reg1_2
677  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
678  // Convert__GPR32AsmReg1_1__GPR32AsmReg1_2
679  { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
680  // Convert__GPR64AsmReg1_0__Imm1_1
681  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
682  // Convert__GPR64AsmReg1_0__Mem2_1
683  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
684  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3
685  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done },
686  // Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0
687  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
688  // Convert__GPR64AsmReg1_0__COP0AsmReg1_1__UImm161_2
689  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done },
690  // Convert__GPR64AsmReg1_0__FGR64AsmReg1_1
691  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
692  // Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0
693  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
694  // Convert__GPR64AsmReg1_0__UImm161_1
695  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
696  // Convert__GPR64AsmReg1_0__COP2AsmReg1_1__UImm161_2
697  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done },
698  // Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0
699  { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
700  // Convert__COP0AsmReg1_1__GPR64AsmReg1_0__UImm161_2
701  { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done },
702  // Convert__FGR64AsmReg1_1__GPR64AsmReg1_0
703  { CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
704  // Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0
705  { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
706  // Convert__COP2AsmReg1_1__GPR64AsmReg1_0__UImm161_2
707  { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done },
708  // Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0
709  { CVT_95_addGPR64AsmRegOperands, 1, CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
710  // Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1
711  { CVT_95_addGPR64AsmRegOperands, 1, CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
712  // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0
713  { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, 0, CVT_Done },
714  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0
715  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
716  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1
717  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 2, CVT_Done },
718  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2
719  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done },
720  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1
721  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_Done },
722  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2
723  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
724  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2
725  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
726  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1
727  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
728  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2
729  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
730  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3
731  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done },
732  // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2
733  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
734  // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2
735  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
736  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1
737  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_Done },
738  // Convert__MSA128AsmReg1_0__GPR32AsmReg1_1
739  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
740  // Convert__MSA128AsmReg1_0__GPR64AsmReg1_1
741  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
742  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Imm1_3__Tie0
743  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addImmOperands, 4, CVT_Tied, 0, CVT_Done },
744  // Convert__MSA128AsmReg1_0__Tie0__GPR32AsmReg1_4__Imm1_2
745  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addImmOperands, 3, CVT_Done },
746  // Convert__MSA128AsmReg1_0__Tie0__GPR64AsmReg1_4__Imm1_2
747  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addGPR64AsmRegOperands, 5, CVT_95_addImmOperands, 3, CVT_Done },
748  // Convert__GPR32AsmReg1_0__Tie0__GPR32AsmReg1_1
749  { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
750  // Convert__MSA128AsmReg1_0__Tie0__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6
751  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
752  // Convert__MSA128AsmReg1_0__Tie0__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6
753  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
754  // Convert__MSA128AsmReg1_0__Tie0__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6
755  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
756  // Convert__MSA128AsmReg1_0__Tie0__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6
757  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
758  // Convert__regRA__GPR32AsmReg1_0
759  { CVT_regRA, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
760  // Convert__Reg1_0
761  { CVT_95_Reg, 1, CVT_Done },
762  // Convert__regZERO__GPR32AsmReg1_0
763  { CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
764  // Convert__regZERO_64__GPR64AsmReg1_0
765  { CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
766  // Convert__UImm5Lsl21_0
767  { CVT_95_addImmOperands, 1, CVT_Done },
768  // Convert__GPR32AsmReg1_0__Mem2_1
769  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
770  // Convert__GPR32AsmReg1_0__MemOffsetSimm92_1
771  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
772  // Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1
773  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addMicroMipsMemOperands, 2, CVT_Done },
774  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
775  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
776  // Convert__MSA128AsmReg1_0__Mem2_1
777  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
778  // Convert__AFGR64AsmReg1_0__Mem2_1
779  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
780  // Convert__FGR64AsmReg1_0__Mem2_1
781  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
782  // Convert__COP2AsmReg1_0__MemOffsetSimm112_1
783  { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
784  // Convert__COP2AsmReg1_0__Mem2_1
785  { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
786  // Convert__COP3AsmReg1_0__Mem2_1
787  { CVT_95_addCOP3AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
788  // Convert__MSA128AsmReg1_0__Imm1_1
789  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
790  // Convert__GPR64AsmReg1_0__Mem2_1__Tie0
791  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, 0, CVT_Done },
792  // Convert__GPR64AsmReg1_0__JumpTarget1_1
793  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
794  // Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
795  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
796  // Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
797  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
798  // Convert__GPR64AsmReg1_0__MemOffsetSimm92_1
799  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
800  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3
801  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done },
802  // Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3
803  { CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done },
804  // Convert__GPR32AsmReg1_0__UImm161_1
805  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
806  // Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1
807  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
808  // Convert__Reg1_0__Imm1_1__imm_95_0
809  { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_Done },
810  // Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1
811  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
812  // Convert__GPRMM16AsmReg1_0__Reg1_1__Imm1_2
813  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
814  // Convert__Reg1_0__Reg1_3__Imm1_1
815  { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
816  // Convert__FGR32AsmReg1_0__Mem2_1
817  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
818  // Convert__GPR32AsmReg1_0__Mem2_1__Tie0
819  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, 0, CVT_Done },
820  // Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0
821  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, 0, CVT_Done },
822  // Convert__RegList1_0__Mem2_1
823  { CVT_95_addRegListOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
824  // Convert__RegList161_0__MemOffsetUimm42_1
825  { CVT_95_addRegListOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
826  // Convert__RegPair2_0__Mem2_1
827  { CVT_95_addRegPairOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
828  // Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
829  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
830  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3
831  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_95_addAFGR64AsmRegOperands, 4, CVT_Done },
832  // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3
833  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_95_addFGR64AsmRegOperands, 4, CVT_Done },
834  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3
835  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_95_addFGR32AsmRegOperands, 4, CVT_Done },
836  // Convert__FGR64AsmReg1_0__Tie0__FGR64AsmReg1_1__FGR64AsmReg1_2
837  { CVT_95_addFGR64AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
838  // Convert__FGR32AsmReg1_0__Tie0__FGR32AsmReg1_1__FGR32AsmReg1_2
839  { CVT_95_addFGR32AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
840  // Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0
841  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
842  // Convert__GPR32AsmReg1_0__COP0AsmReg1_1__UImm161_2
843  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done },
844  // Convert__GPR32AsmReg1_0__FGR32AsmReg1_1
845  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
846  // Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0
847  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
848  // Convert__GPR32AsmReg1_0__COP2AsmReg1_1__UImm161_2
849  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done },
850  // Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1
851  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
852  // Convert__GPR32AsmReg1_0__FGR64AsmReg1_1
853  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
854  // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1
855  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_Done },
856  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO
857  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_regZERO, 0, CVT_Done },
858  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64
859  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_regZERO_64, 0, CVT_Done },
860  // Convert__MovePRegPair2_0__GPRMM16AsmRegMoveP1_1__GPRMM16AsmRegMoveP1_2
861  { CVT_95_addMovePRegPairOperands, 1, CVT_95_addGPRMM16AsmRegMovePOperands, 2, CVT_95_addGPRMM16AsmRegMovePOperands, 3, CVT_Done },
862  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0
863  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, 0, CVT_Done },
864  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0
865  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, 0, CVT_Done },
866  // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0
867  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, 0, CVT_Done },
868  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0
869  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, 0, CVT_Done },
870  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0
871  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, 0, CVT_Done },
872  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0
873  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, 0, CVT_Done },
874  // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0
875  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, 0, CVT_Done },
876  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0
877  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, 0, CVT_Done },
878  // Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0
879  { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
880  // Convert__COP0AsmReg1_1__GPR32AsmReg1_0__UImm161_2
881  { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done },
882  // Convert__FGR32AsmReg1_1__GPR32AsmReg1_0
883  { CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
884  // Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0
885  { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
886  // Convert__COP2AsmReg1_1__GPR32AsmReg1_0__UImm161_2
887  { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done },
888  // Convert__AFGR64AsmReg1_1__Tie0__GPR32AsmReg1_0
889  { CVT_95_addAFGR64AsmRegOperands, 2, CVT_Tied, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
890  // Convert__FGR64AsmReg1_1__Tie0__GPR32AsmReg1_0
891  { CVT_95_addFGR64AsmRegOperands, 2, CVT_Tied, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
892  // Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0
893  { CVT_95_addHI32DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
894  // Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0
895  { CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, 0, CVT_Done },
896  // Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0
897  { CVT_95_addLO32DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
898  // Convert__GPR64AsmReg1_0
899  { CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
900  // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2
901  { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
902  // Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1
903  { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
904  // Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0
905  { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
906  // Convert__regZERO__regZERO__imm_95_0
907  { CVT_regZERO, 0, CVT_regZERO, 0, CVT_imm_95_0, 0, CVT_Done },
908  // Convert__regZERO__regZERO
909  { CVT_regZERO, 0, CVT_regZERO, 0, CVT_Done },
910  // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1
911  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_Done },
912  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0
913  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
914  // Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0
915  { CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
916  // Convert__GPR32AsmReg1_0__ConstantUImm7_01_1
917  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_, 2, CVT_Done },
918  // Convert__GPR32AsmReg1_0__ConstantUImm10_01_1
919  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
920  // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1
921  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_Done },
922  // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0
923  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
924  // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2
925  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
926  // Convert__GPR32AsmReg1_0__ConstantUImm8_01_1
927  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 2, CVT_Done },
928  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1
929  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_Done },
930  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2
931  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
932  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2
933  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
934  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2
935  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done },
936  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2
937  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
938  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2
939  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
940  // Convert__Reg1_0__Reg1_1__Imm1_2__Reg1_3
941  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_Done },
942  // Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1
943  { CVT_95_addGPRMM16AsmRegZeroOperands, 1, CVT_95_addMicroMipsMemOperands, 2, CVT_Done },
944  // Convert__GPR32AsmReg1_0__Tie0__MemOffsetSimm92_1
945  { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_Done },
946  // Convert__GPR32AsmReg1_0__Tie0__Mem2_1
947  { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_Done },
948  // Convert__GPR64AsmReg1_0__Tie0__MemOffsetSimm92_1
949  { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_Done },
950  // Convert__GPR64AsmReg1_0__Tie0__Mem2_1
951  { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_Done },
952  // Convert__imm_95_0
953  { CVT_imm_95_0, 0, CVT_Done },
954  // Convert__Reg1_0__Tie0
955  { CVT_95_Reg, 1, CVT_Tied, 0, CVT_Done },
956  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2
957  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done },
958  // Convert__ACC64DSPAsmReg1_0__ConstantSImm61_1__Tie0
959  { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Tied, 0, CVT_Done },
960  // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0
961  { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Tied, 0, CVT_Done },
962  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2
963  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
964  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2
965  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
966  // Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__GPR32AsmReg1_3
967  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 4, CVT_Done },
968  // Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm4_01_3
969  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done },
970  // Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm1_01_3
971  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done },
972  // Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm3_01_3
973  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
974  // Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm2_01_3
975  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
976  // Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2
977  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
978  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3
979  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 4, CVT_Done },
980  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_3
981  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addImmOperands, 4, CVT_Done },
982  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1
983  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
984  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2
985  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
986  // Convert__GPR32AsmReg1_0__MemOffsetSimm9GPR2_1
987  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
988  // Convert__MemOffsetSimm162_0
989  { CVT_95_addMemOperands, 1, CVT_Done },
990  // Convert__imm_95_2
991  { CVT_imm_95_2, 0, CVT_Done },
992  // Convert__imm_95_6
993  { CVT_imm_95_6, 0, CVT_Done },
994  // Convert__imm_95_4
995  { CVT_imm_95_4, 0, CVT_Done },
996  // Convert__imm_95_5
997  { CVT_imm_95_5, 0, CVT_Done },
998  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0
999  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1000  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2
1001  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 3, CVT_Done },
1002  // Convert__ConstantUImm10_01_0
1003  { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_Done },
1004  // Convert__GPR32AsmReg1_0__imm_95_31
1005  { CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_31, 0, CVT_Done },
1006};
1007
1008void MipsAsmParser::
1009convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
1010                const OperandVector &Operands) {
1011  assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
1012  const uint8_t *Converter = ConversionTable[Kind];
1013  Inst.setOpcode(Opcode);
1014  for (const uint8_t *p = Converter; *p; p+= 2) {
1015    switch (*p) {
1016    default: llvm_unreachable("invalid conversion entry!");
1017    case CVT_Reg:
1018      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addRegOperands(Inst, 1);
1019      break;
1020    case CVT_Tied:
1021      Inst.addOperand(Inst.getOperand(*(p + 1)));
1022      break;
1023    case CVT_95_addGPR32AsmRegOperands:
1024      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addGPR32AsmRegOperands(Inst, 1);
1025      break;
1026    case CVT_95_addAFGR64AsmRegOperands:
1027      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addAFGR64AsmRegOperands(Inst, 1);
1028      break;
1029    case CVT_95_addFGR64AsmRegOperands:
1030      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addFGR64AsmRegOperands(Inst, 1);
1031      break;
1032    case CVT_95_addFGR32AsmRegOperands:
1033      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addFGR32AsmRegOperands(Inst, 1);
1034      break;
1035    case CVT_95_addImmOperands:
1036      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addImmOperands(Inst, 1);
1037      break;
1038    case CVT_95_addMSA128AsmRegOperands:
1039      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addMSA128AsmRegOperands(Inst, 1);
1040      break;
1041    case CVT_95_Reg:
1042      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addRegOperands(Inst, 1);
1043      break;
1044    case CVT_95_addGPRMM16AsmRegOperands:
1045      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addGPRMM16AsmRegOperands(Inst, 1);
1046      break;
1047    case CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_:
1048      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addConstantUImmOperands<2, 0>(Inst, 1);
1049      break;
1050    case CVT_95_addUImmOperands_LT_16_GT_:
1051      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addUImmOperands<16>(Inst, 1);
1052      break;
1053    case CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_:
1054      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addConstantUImmOperands<5, 0>(Inst, 1);
1055      break;
1056    case CVT_regZERO:
1057      Inst.addOperand(MCOperand::createReg(Mips::ZERO));
1058      break;
1059    case CVT_95_addGPR64AsmRegOperands:
1060      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addGPR64AsmRegOperands(Inst, 1);
1061      break;
1062    case CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_:
1063      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addConstantUImmOperands<5, 32, -32>(Inst, 1);
1064      break;
1065    case CVT_regFCC0:
1066      Inst.addOperand(MCOperand::createReg(Mips::FCC0));
1067      break;
1068    case CVT_95_addFCCAsmRegOperands:
1069      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addFCCAsmRegOperands(Inst, 1);
1070      break;
1071    case CVT_95_addCOP2AsmRegOperands:
1072      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addCOP2AsmRegOperands(Inst, 1);
1073      break;
1074    case CVT_imm_95_0:
1075      Inst.addOperand(MCOperand::createImm(0));
1076      break;
1077    case CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_:
1078      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addConstantUImmOperands<10, 0>(Inst, 1);
1079      break;
1080    case CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_:
1081      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addConstantUImmOperands<4, 0>(Inst, 1);
1082      break;
1083    case CVT_95_addMemOperands:
1084      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addMemOperands(Inst, 2);
1085      break;
1086    case CVT_95_addCCRAsmRegOperands:
1087      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addCCRAsmRegOperands(Inst, 1);
1088      break;
1089    case CVT_95_addMSACtrlAsmRegOperands:
1090      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addMSACtrlAsmRegOperands(Inst, 1);
1091      break;
1092    case CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_:
1093      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addConstantUImmOperands<3, 0>(Inst, 1);
1094      break;
1095    case CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_:
1096      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addConstantUImmOperands<5, 1>(Inst, 1);
1097      break;
1098    case CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_:
1099      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addConstantUImmOperands<5, 33>(Inst, 1);
1100      break;
1101    case CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_:
1102      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addConstantUImmOperands<5, 32>(Inst, 1);
1103      break;
1104    case CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_:
1105      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addConstantUImmOperands<6, 0>(Inst, 1);
1106      break;
1107    case CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_:
1108      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addConstantUImmOperands<2, 1>(Inst, 1);
1109      break;
1110    case CVT_95_addCOP0AsmRegOperands:
1111      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addCOP0AsmRegOperands(Inst, 1);
1112      break;
1113    case CVT_regZERO_64:
1114      Inst.addOperand(MCOperand::createReg(Mips::ZERO_64));
1115      break;
1116    case CVT_95_addACC64DSPAsmRegOperands:
1117      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addACC64DSPAsmRegOperands(Inst, 1);
1118      break;
1119    case CVT_95_addConstantUImmOperands_LT_1_GT_:
1120      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addConstantUImmOperands<1>(Inst, 1);
1121      break;
1122    case CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_:
1123      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addConstantUImmOperands<1, 0>(Inst, 1);
1124      break;
1125    case CVT_regRA:
1126      Inst.addOperand(MCOperand::createReg(Mips::RA));
1127      break;
1128    case CVT_95_addMicroMipsMemOperands:
1129      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addMicroMipsMemOperands(Inst, 2);
1130      break;
1131    case CVT_95_addCOP3AsmRegOperands:
1132      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addCOP3AsmRegOperands(Inst, 1);
1133      break;
1134    case CVT_95_addRegListOperands:
1135      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addRegListOperands(Inst, 1);
1136      break;
1137    case CVT_95_addRegPairOperands:
1138      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addRegPairOperands(Inst, 2);
1139      break;
1140    case CVT_95_addMovePRegPairOperands:
1141      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addMovePRegPairOperands(Inst, 2);
1142      break;
1143    case CVT_95_addGPRMM16AsmRegMovePOperands:
1144      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addGPRMM16AsmRegMovePOperands(Inst, 1);
1145      break;
1146    case CVT_95_addHI32DSPAsmRegOperands:
1147      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addHI32DSPAsmRegOperands(Inst, 1);
1148      break;
1149    case CVT_95_addLO32DSPAsmRegOperands:
1150      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addLO32DSPAsmRegOperands(Inst, 1);
1151      break;
1152    case CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_:
1153      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addConstantUImmOperands<7, 0>(Inst, 1);
1154      break;
1155    case CVT_95_addHWRegsAsmRegOperands:
1156      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addHWRegsAsmRegOperands(Inst, 1);
1157      break;
1158    case CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_:
1159      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addConstantUImmOperands<8, 0>(Inst, 1);
1160      break;
1161    case CVT_95_addGPRMM16AsmRegZeroOperands:
1162      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addGPRMM16AsmRegZeroOperands(Inst, 1);
1163      break;
1164    case CVT_imm_95_2:
1165      Inst.addOperand(MCOperand::createImm(2));
1166      break;
1167    case CVT_imm_95_6:
1168      Inst.addOperand(MCOperand::createImm(6));
1169      break;
1170    case CVT_imm_95_4:
1171      Inst.addOperand(MCOperand::createImm(4));
1172      break;
1173    case CVT_imm_95_5:
1174      Inst.addOperand(MCOperand::createImm(5));
1175      break;
1176    case CVT_imm_95_31:
1177      Inst.addOperand(MCOperand::createImm(31));
1178      break;
1179    }
1180  }
1181}
1182
1183void MipsAsmParser::
1184convertToMapAndConstraints(unsigned Kind,
1185                           const OperandVector &Operands) {
1186  assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
1187  unsigned NumMCOperands = 0;
1188  const uint8_t *Converter = ConversionTable[Kind];
1189  for (const uint8_t *p = Converter; *p; p+= 2) {
1190    switch (*p) {
1191    default: llvm_unreachable("invalid conversion entry!");
1192    case CVT_Reg:
1193      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1194      Operands[*(p + 1)]->setConstraint("r");
1195      ++NumMCOperands;
1196      break;
1197    case CVT_Tied:
1198      ++NumMCOperands;
1199      break;
1200    case CVT_95_addGPR32AsmRegOperands:
1201      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1202      Operands[*(p + 1)]->setConstraint("m");
1203      NumMCOperands += 1;
1204      break;
1205    case CVT_95_addAFGR64AsmRegOperands:
1206      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1207      Operands[*(p + 1)]->setConstraint("m");
1208      NumMCOperands += 1;
1209      break;
1210    case CVT_95_addFGR64AsmRegOperands:
1211      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1212      Operands[*(p + 1)]->setConstraint("m");
1213      NumMCOperands += 1;
1214      break;
1215    case CVT_95_addFGR32AsmRegOperands:
1216      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1217      Operands[*(p + 1)]->setConstraint("m");
1218      NumMCOperands += 1;
1219      break;
1220    case CVT_95_addImmOperands:
1221      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1222      Operands[*(p + 1)]->setConstraint("m");
1223      NumMCOperands += 1;
1224      break;
1225    case CVT_95_addMSA128AsmRegOperands:
1226      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1227      Operands[*(p + 1)]->setConstraint("m");
1228      NumMCOperands += 1;
1229      break;
1230    case CVT_95_Reg:
1231      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1232      Operands[*(p + 1)]->setConstraint("r");
1233      NumMCOperands += 1;
1234      break;
1235    case CVT_95_addGPRMM16AsmRegOperands:
1236      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1237      Operands[*(p + 1)]->setConstraint("m");
1238      NumMCOperands += 1;
1239      break;
1240    case CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_:
1241      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1242      Operands[*(p + 1)]->setConstraint("m");
1243      NumMCOperands += 1;
1244      break;
1245    case CVT_95_addUImmOperands_LT_16_GT_:
1246      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1247      Operands[*(p + 1)]->setConstraint("m");
1248      NumMCOperands += 1;
1249      break;
1250    case CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_:
1251      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1252      Operands[*(p + 1)]->setConstraint("m");
1253      NumMCOperands += 1;
1254      break;
1255    case CVT_regZERO:
1256      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1257      Operands[*(p + 1)]->setConstraint("m");
1258      ++NumMCOperands;
1259      break;
1260    case CVT_95_addGPR64AsmRegOperands:
1261      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1262      Operands[*(p + 1)]->setConstraint("m");
1263      NumMCOperands += 1;
1264      break;
1265    case CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_:
1266      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1267      Operands[*(p + 1)]->setConstraint("m");
1268      NumMCOperands += 1;
1269      break;
1270    case CVT_regFCC0:
1271      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1272      Operands[*(p + 1)]->setConstraint("m");
1273      ++NumMCOperands;
1274      break;
1275    case CVT_95_addFCCAsmRegOperands:
1276      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1277      Operands[*(p + 1)]->setConstraint("m");
1278      NumMCOperands += 1;
1279      break;
1280    case CVT_95_addCOP2AsmRegOperands:
1281      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1282      Operands[*(p + 1)]->setConstraint("m");
1283      NumMCOperands += 1;
1284      break;
1285    case CVT_imm_95_0:
1286      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1287      Operands[*(p + 1)]->setConstraint("");
1288      ++NumMCOperands;
1289      break;
1290    case CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_:
1291      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1292      Operands[*(p + 1)]->setConstraint("m");
1293      NumMCOperands += 1;
1294      break;
1295    case CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_:
1296      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1297      Operands[*(p + 1)]->setConstraint("m");
1298      NumMCOperands += 1;
1299      break;
1300    case CVT_95_addMemOperands:
1301      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1302      Operands[*(p + 1)]->setConstraint("m");
1303      NumMCOperands += 2;
1304      break;
1305    case CVT_95_addCCRAsmRegOperands:
1306      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1307      Operands[*(p + 1)]->setConstraint("m");
1308      NumMCOperands += 1;
1309      break;
1310    case CVT_95_addMSACtrlAsmRegOperands:
1311      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1312      Operands[*(p + 1)]->setConstraint("m");
1313      NumMCOperands += 1;
1314      break;
1315    case CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_:
1316      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1317      Operands[*(p + 1)]->setConstraint("m");
1318      NumMCOperands += 1;
1319      break;
1320    case CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_:
1321      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1322      Operands[*(p + 1)]->setConstraint("m");
1323      NumMCOperands += 1;
1324      break;
1325    case CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_:
1326      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1327      Operands[*(p + 1)]->setConstraint("m");
1328      NumMCOperands += 1;
1329      break;
1330    case CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_:
1331      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1332      Operands[*(p + 1)]->setConstraint("m");
1333      NumMCOperands += 1;
1334      break;
1335    case CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_:
1336      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1337      Operands[*(p + 1)]->setConstraint("m");
1338      NumMCOperands += 1;
1339      break;
1340    case CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_:
1341      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1342      Operands[*(p + 1)]->setConstraint("m");
1343      NumMCOperands += 1;
1344      break;
1345    case CVT_95_addCOP0AsmRegOperands:
1346      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1347      Operands[*(p + 1)]->setConstraint("m");
1348      NumMCOperands += 1;
1349      break;
1350    case CVT_regZERO_64:
1351      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1352      Operands[*(p + 1)]->setConstraint("m");
1353      ++NumMCOperands;
1354      break;
1355    case CVT_95_addACC64DSPAsmRegOperands:
1356      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1357      Operands[*(p + 1)]->setConstraint("m");
1358      NumMCOperands += 1;
1359      break;
1360    case CVT_95_addConstantUImmOperands_LT_1_GT_:
1361      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1362      Operands[*(p + 1)]->setConstraint("m");
1363      NumMCOperands += 1;
1364      break;
1365    case CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_:
1366      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1367      Operands[*(p + 1)]->setConstraint("m");
1368      NumMCOperands += 1;
1369      break;
1370    case CVT_regRA:
1371      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1372      Operands[*(p + 1)]->setConstraint("m");
1373      ++NumMCOperands;
1374      break;
1375    case CVT_95_addMicroMipsMemOperands:
1376      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1377      Operands[*(p + 1)]->setConstraint("m");
1378      NumMCOperands += 2;
1379      break;
1380    case CVT_95_addCOP3AsmRegOperands:
1381      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1382      Operands[*(p + 1)]->setConstraint("m");
1383      NumMCOperands += 1;
1384      break;
1385    case CVT_95_addRegListOperands:
1386      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1387      Operands[*(p + 1)]->setConstraint("m");
1388      NumMCOperands += 1;
1389      break;
1390    case CVT_95_addRegPairOperands:
1391      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1392      Operands[*(p + 1)]->setConstraint("m");
1393      NumMCOperands += 2;
1394      break;
1395    case CVT_95_addMovePRegPairOperands:
1396      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1397      Operands[*(p + 1)]->setConstraint("m");
1398      NumMCOperands += 2;
1399      break;
1400    case CVT_95_addGPRMM16AsmRegMovePOperands:
1401      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1402      Operands[*(p + 1)]->setConstraint("m");
1403      NumMCOperands += 1;
1404      break;
1405    case CVT_95_addHI32DSPAsmRegOperands:
1406      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1407      Operands[*(p + 1)]->setConstraint("m");
1408      NumMCOperands += 1;
1409      break;
1410    case CVT_95_addLO32DSPAsmRegOperands:
1411      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1412      Operands[*(p + 1)]->setConstraint("m");
1413      NumMCOperands += 1;
1414      break;
1415    case CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_:
1416      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1417      Operands[*(p + 1)]->setConstraint("m");
1418      NumMCOperands += 1;
1419      break;
1420    case CVT_95_addHWRegsAsmRegOperands:
1421      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1422      Operands[*(p + 1)]->setConstraint("m");
1423      NumMCOperands += 1;
1424      break;
1425    case CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_:
1426      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1427      Operands[*(p + 1)]->setConstraint("m");
1428      NumMCOperands += 1;
1429      break;
1430    case CVT_95_addGPRMM16AsmRegZeroOperands:
1431      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1432      Operands[*(p + 1)]->setConstraint("m");
1433      NumMCOperands += 1;
1434      break;
1435    case CVT_imm_95_2:
1436      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1437      Operands[*(p + 1)]->setConstraint("");
1438      ++NumMCOperands;
1439      break;
1440    case CVT_imm_95_6:
1441      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1442      Operands[*(p + 1)]->setConstraint("");
1443      ++NumMCOperands;
1444      break;
1445    case CVT_imm_95_4:
1446      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1447      Operands[*(p + 1)]->setConstraint("");
1448      ++NumMCOperands;
1449      break;
1450    case CVT_imm_95_5:
1451      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1452      Operands[*(p + 1)]->setConstraint("");
1453      ++NumMCOperands;
1454      break;
1455    case CVT_imm_95_31:
1456      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1457      Operands[*(p + 1)]->setConstraint("");
1458      ++NumMCOperands;
1459      break;
1460    }
1461  }
1462}
1463
1464namespace {
1465
1466/// MatchClassKind - The kinds of classes which participate in
1467/// instruction matching.
1468enum MatchClassKind {
1469  InvalidMatchClass = 0,
1470  MCK__35_, // '#'
1471  MCK__40_, // '('
1472  MCK__41_, // ')'
1473  MCK__41__59_, // ');'
1474  MCK_0, // '0'
1475  MCK_16, // '16'
1476  MCK__91_, // '['
1477  MCK__93_, // ']'
1478  MCK_bit, // 'bit'
1479  MCK_inst, // 'inst'
1480  MCK_Reg22, // derived register class
1481  MCK_Reg21, // derived register class
1482  MCK_ACC128, // register class 'ACC128'
1483  MCK_ACC64, // register class 'ACC64'
1484  MCK_CPURAReg, // register class 'CPURAReg,RA'
1485  MCK_CPUSPReg, // register class 'CPUSPReg,SP'
1486  MCK_DSPCC, // register class 'DSPCC'
1487  MCK_HI32, // register class 'HI32'
1488  MCK_HI64, // register class 'HI64'
1489  MCK_LO32, // register class 'LO32'
1490  MCK_LO64, // register class 'LO64'
1491  MCK_PC, // register class 'PC'
1492  MCK_ZERO, // register class 'ZERO'
1493  MCK_Reg20, // derived register class
1494  MCK_Reg9, // derived register class
1495  MCK_OCTEON_MPL, // register class 'OCTEON_MPL'
1496  MCK_OCTEON_P, // register class 'OCTEON_P'
1497  MCK_Reg19, // derived register class
1498  MCK_Reg15, // derived register class
1499  MCK_Reg8, // derived register class
1500  MCK_Reg4, // derived register class
1501  MCK_ACC64DSP, // register class 'ACC64DSP'
1502  MCK_HI32DSP, // register class 'HI32DSP'
1503  MCK_LO32DSP, // register class 'LO32DSP'
1504  MCK_Reg18, // derived register class
1505  MCK_Reg7, // derived register class
1506  MCK_Reg29, // derived register class
1507  MCK_Reg16, // derived register class
1508  MCK_Reg14, // derived register class
1509  MCK_Reg13, // derived register class
1510  MCK_CPU16Regs, // register class 'CPU16Regs,GPRMM16'
1511  MCK_FCC, // register class 'FCC'
1512  MCK_GPRMM16MoveP, // register class 'GPRMM16MoveP'
1513  MCK_GPRMM16Zero, // register class 'GPRMM16Zero'
1514  MCK_MSACtrl, // register class 'MSACtrl'
1515  MCK_Reg17, // derived register class
1516  MCK_CPU16RegsPlusSP, // register class 'CPU16RegsPlusSP'
1517  MCK_Reg35, // derived register class
1518  MCK_Reg32, // derived register class
1519  MCK_Reg27, // derived register class
1520  MCK_Reg24, // derived register class
1521  MCK_AFGR64, // register class 'AFGR64'
1522  MCK_MSA128WEvens, // register class 'MSA128WEvens'
1523  MCK_Reg30, // derived register class
1524  MCK_CCR, // register class 'CCR'
1525  MCK_COP0, // register class 'COP0'
1526  MCK_COP2, // register class 'COP2'
1527  MCK_COP3, // register class 'COP3'
1528  MCK_DSPR, // register class 'DSPR,GPR32'
1529  MCK_FGR32, // register class 'FGR32,FGRCC'
1530  MCK_FGR64, // register class 'FGR64'
1531  MCK_FGRH32, // register class 'FGRH32'
1532  MCK_GPR64, // register class 'GPR64'
1533  MCK_HWRegs, // register class 'HWRegs'
1534  MCK_MSA128B, // register class 'MSA128B,MSA128D,MSA128H,MSA128W'
1535  MCK_OddSP, // register class 'OddSP'
1536  MCK_ACC64DSPAsmReg, // user defined class 'ACC64DSPAsmOperand'
1537  MCK_AFGR64AsmReg, // user defined class 'AFGR64AsmOperand'
1538  MCK_CCRAsmReg, // user defined class 'CCRAsmOperand'
1539  MCK_COP0AsmReg, // user defined class 'COP0AsmOperand'
1540  MCK_COP2AsmReg, // user defined class 'COP2AsmOperand'
1541  MCK_COP3AsmReg, // user defined class 'COP3AsmOperand'
1542  MCK_FCCAsmReg, // user defined class 'FCCRegsAsmOperand'
1543  MCK_FGR32AsmReg, // user defined class 'FGR32AsmOperand'
1544  MCK_FGR64AsmReg, // user defined class 'FGR64AsmOperand'
1545  MCK_FGRH32AsmReg, // user defined class 'FGRH32AsmOperand'
1546  MCK_GPR32AsmReg, // user defined class 'GPR32AsmOperand'
1547  MCK_GPR64AsmReg, // user defined class 'GPR64AsmOperand'
1548  MCK_GPRMM16AsmReg, // user defined class 'GPRMM16AsmOperand'
1549  MCK_GPRMM16AsmRegMoveP, // user defined class 'GPRMM16AsmOperandMoveP'
1550  MCK_GPRMM16AsmRegZero, // user defined class 'GPRMM16AsmOperandZero'
1551  MCK_HI32DSPAsmReg, // user defined class 'HI32DSPAsmOperand'
1552  MCK_HWRegsAsmReg, // user defined class 'HWRegsAsmOperand'
1553  MCK_Imm, // user defined class 'ImmAsmOperand'
1554  MCK_LO32DSPAsmReg, // user defined class 'LO32DSPAsmOperand'
1555  MCK_MSA128AsmReg, // user defined class 'MSA128AsmOperand'
1556  MCK_MSACtrlAsmReg, // user defined class 'MSACtrlAsmOperand'
1557  MCK_MicroMipsMem, // user defined class 'MicroMipsMemGPRMM16AsmOperand'
1558  MCK_MicroMipsMemSP, // user defined class 'MicroMipsMemSPAsmOperand'
1559  MCK_InvNum, // user defined class 'MipsInvertedImmoperand'
1560  MCK_JumpTarget, // user defined class 'MipsJumpTargetAsmOperand'
1561  MCK_MemOffsetSimm11, // user defined class 'MipsMemSimm11AsmOperand'
1562  MCK_MemOffsetSimm16, // user defined class 'MipsMemSimm16AsmOperand'
1563  MCK_MemOffsetSimm9, // user defined class 'MipsMemSimm9AsmOperand'
1564  MCK_MemOffsetSimm9GPR, // user defined class 'MipsMemSimm9GPRAsmOperand'
1565  MCK_MemOffsetUimm4, // user defined class 'MipsMemUimm4AsmOperand'
1566  MCK_Mem, // user defined class 'MipsMemAsmOperand'
1567  MCK_MovePRegPair, // user defined class 'MovePRegPairAsmOperand'
1568  MCK_RegList16, // user defined class 'RegList16AsmOperand'
1569  MCK_RegList, // user defined class 'RegListAsmOperand'
1570  MCK_RegPair, // user defined class 'RegPairAsmOperand'
1571  MCK_ConstantImmz, // user defined class 'ConstantImmzAsmOperandClass'
1572  MCK_ConstantUImm1_0, // user defined class 'ConstantUImm1AsmOperandClass'
1573  MCK_ConstantUImm2_0, // user defined class 'ConstantUImm2AsmOperandClass'
1574  MCK_ConstantUImm2_1, // user defined class 'ConstantUImm2Plus1AsmOperandClass'
1575  MCK_ConstantUImm3_0, // user defined class 'ConstantUImm3AsmOperandClass'
1576  MCK_ConstantUImm4_0, // user defined class 'ConstantUImm4AsmOperandClass'
1577  MCK_ConstantUImm5_0, // user defined class 'ConstantUImm5AsmOperandClass'
1578  MCK_UImm5Lsl2, // user defined class 'ConstantUImm5Lsl2AsmOperandClass'
1579  MCK_ConstantUImm5_1, // user defined class 'ConstantUImm5Plus1AsmOperandClass'
1580  MCK_ConstantUImm5_32, // user defined class 'ConstantUImm5Plus32AsmOperandClass'
1581  MCK_ConstantUImm5_32_Norm, // user defined class 'ConstantUImm5Plus32NormalizeAsmOperandClass'
1582  MCK_ConstantUImm5_33, // user defined class 'ConstantUImm5Plus33AsmOperandClass'
1583  MCK_ConstantUImm5_0_Report_UImm6, // user defined class 'ConstantUImm5ReportUImm6AsmOperandClass'
1584  MCK_ConstantSImm6, // user defined class 'ConstantSImm6AsmOperandClass'
1585  MCK_ConstantUImm6_0, // user defined class 'ConstantUImm6AsmOperandClass'
1586  MCK_ConstantUImm7_0, // user defined class 'ConstantUImm7AsmOperandClass'
1587  MCK_ConstantUImm8_0, // user defined class 'ConstantUImm8AsmOperandClass'
1588  MCK_ConstantUImm10_0, // user defined class 'ConstantUImm10AsmOperandClass'
1589  MCK_UImm16, // user defined class 'UImm16AsmOperandClass'
1590  MCK_UImm16_Relaxed, // user defined class 'UImm16RelaxedAsmOperandClass'
1591  NumMatchClassKinds
1592};
1593
1594}
1595
1596static MatchClassKind matchTokenString(StringRef Name) {
1597  switch (Name.size()) {
1598  default: break;
1599  case 1:	 // 6 strings to match.
1600    switch (Name[0]) {
1601    default: break;
1602    case '#':	 // 1 string to match.
1603      return MCK__35_;	 // "#"
1604    case '(':	 // 1 string to match.
1605      return MCK__40_;	 // "("
1606    case ')':	 // 1 string to match.
1607      return MCK__41_;	 // ")"
1608    case '0':	 // 1 string to match.
1609      return MCK_0;	 // "0"
1610    case '[':	 // 1 string to match.
1611      return MCK__91_;	 // "["
1612    case ']':	 // 1 string to match.
1613      return MCK__93_;	 // "]"
1614    }
1615    break;
1616  case 2:	 // 2 strings to match.
1617    switch (Name[0]) {
1618    default: break;
1619    case ')':	 // 1 string to match.
1620      if (Name[1] != ';')
1621        break;
1622      return MCK__41__59_;	 // ");"
1623    case '1':	 // 1 string to match.
1624      if (Name[1] != '6')
1625        break;
1626      return MCK_16;	 // "16"
1627    }
1628    break;
1629  case 3:	 // 1 string to match.
1630    if (memcmp(Name.data()+0, "bit", 3))
1631      break;
1632    return MCK_bit;	 // "bit"
1633  case 4:	 // 1 string to match.
1634    if (memcmp(Name.data()+0, "inst", 4))
1635      break;
1636    return MCK_inst;	 // "inst"
1637  }
1638  return InvalidMatchClass;
1639}
1640
1641/// isSubclass - Compute whether \p A is a subclass of \p B.
1642static bool isSubclass(MatchClassKind A, MatchClassKind B) {
1643  if (A == B)
1644    return true;
1645
1646  switch (A) {
1647  default:
1648    return false;
1649
1650  case MCK_Reg22:
1651    return B == MCK_GPR64;
1652
1653  case MCK_Reg21:
1654    switch (B) {
1655    default: return false;
1656    case MCK_Reg17: return true;
1657    case MCK_GPR64: return true;
1658    }
1659
1660  case MCK_ACC64:
1661    return B == MCK_ACC64DSP;
1662
1663  case MCK_CPURAReg:
1664    return B == MCK_DSPR;
1665
1666  case MCK_CPUSPReg:
1667    switch (B) {
1668    default: return false;
1669    case MCK_CPU16RegsPlusSP: return true;
1670    case MCK_DSPR: return true;
1671    }
1672
1673  case MCK_HI32:
1674    return B == MCK_HI32DSP;
1675
1676  case MCK_LO32:
1677    return B == MCK_LO32DSP;
1678
1679  case MCK_ZERO:
1680    switch (B) {
1681    default: return false;
1682    case MCK_Reg4: return true;
1683    case MCK_GPRMM16MoveP: return true;
1684    case MCK_GPRMM16Zero: return true;
1685    case MCK_DSPR: return true;
1686    }
1687
1688  case MCK_Reg20:
1689    switch (B) {
1690    default: return false;
1691    case MCK_Reg19: return true;
1692    case MCK_Reg15: return true;
1693    case MCK_Reg18: return true;
1694    case MCK_Reg16: return true;
1695    case MCK_Reg14: return true;
1696    case MCK_Reg13: return true;
1697    case MCK_Reg17: return true;
1698    case MCK_GPR64: return true;
1699    }
1700
1701  case MCK_Reg9:
1702    switch (B) {
1703    default: return false;
1704    case MCK_Reg8: return true;
1705    case MCK_Reg4: return true;
1706    case MCK_Reg7: return true;
1707    case MCK_CPU16Regs: return true;
1708    case MCK_GPRMM16MoveP: return true;
1709    case MCK_GPRMM16Zero: return true;
1710    case MCK_CPU16RegsPlusSP: return true;
1711    case MCK_DSPR: return true;
1712    }
1713
1714  case MCK_Reg19:
1715    switch (B) {
1716    default: return false;
1717    case MCK_Reg16: return true;
1718    case MCK_Reg14: return true;
1719    case MCK_Reg17: return true;
1720    case MCK_GPR64: return true;
1721    }
1722
1723  case MCK_Reg15:
1724    switch (B) {
1725    default: return false;
1726    case MCK_Reg14: return true;
1727    case MCK_Reg13: return true;
1728    case MCK_GPR64: return true;
1729    }
1730
1731  case MCK_Reg8:
1732    switch (B) {
1733    default: return false;
1734    case MCK_CPU16Regs: return true;
1735    case MCK_GPRMM16MoveP: return true;
1736    case MCK_CPU16RegsPlusSP: return true;
1737    case MCK_DSPR: return true;
1738    }
1739
1740  case MCK_Reg4:
1741    switch (B) {
1742    default: return false;
1743    case MCK_GPRMM16MoveP: return true;
1744    case MCK_GPRMM16Zero: return true;
1745    case MCK_DSPR: return true;
1746    }
1747
1748  case MCK_Reg18:
1749    switch (B) {
1750    default: return false;
1751    case MCK_Reg16: return true;
1752    case MCK_Reg13: return true;
1753    case MCK_Reg17: return true;
1754    case MCK_GPR64: return true;
1755    }
1756
1757  case MCK_Reg7:
1758    switch (B) {
1759    default: return false;
1760    case MCK_CPU16Regs: return true;
1761    case MCK_GPRMM16Zero: return true;
1762    case MCK_CPU16RegsPlusSP: return true;
1763    case MCK_DSPR: return true;
1764    }
1765
1766  case MCK_Reg29:
1767    switch (B) {
1768    default: return false;
1769    case MCK_AFGR64: return true;
1770    case MCK_Reg30: return true;
1771    case MCK_OddSP: return true;
1772    }
1773
1774  case MCK_Reg16:
1775    switch (B) {
1776    default: return false;
1777    case MCK_Reg17: return true;
1778    case MCK_GPR64: return true;
1779    }
1780
1781  case MCK_Reg14:
1782    return B == MCK_GPR64;
1783
1784  case MCK_Reg13:
1785    return B == MCK_GPR64;
1786
1787  case MCK_CPU16Regs:
1788    switch (B) {
1789    default: return false;
1790    case MCK_CPU16RegsPlusSP: return true;
1791    case MCK_DSPR: return true;
1792    }
1793
1794  case MCK_GPRMM16MoveP:
1795    return B == MCK_DSPR;
1796
1797  case MCK_GPRMM16Zero:
1798    return B == MCK_DSPR;
1799
1800  case MCK_Reg17:
1801    return B == MCK_GPR64;
1802
1803  case MCK_CPU16RegsPlusSP:
1804    return B == MCK_DSPR;
1805
1806  case MCK_Reg35:
1807    return B == MCK_MSA128B;
1808
1809  case MCK_Reg32:
1810    switch (B) {
1811    default: return false;
1812    case MCK_Reg30: return true;
1813    case MCK_FGR64: return true;
1814    case MCK_OddSP: return true;
1815    }
1816
1817  case MCK_Reg27:
1818    switch (B) {
1819    default: return false;
1820    case MCK_FGRH32: return true;
1821    case MCK_OddSP: return true;
1822    }
1823
1824  case MCK_Reg24:
1825    switch (B) {
1826    default: return false;
1827    case MCK_FGR32: return true;
1828    case MCK_OddSP: return true;
1829    }
1830
1831  case MCK_MSA128WEvens:
1832    return B == MCK_MSA128B;
1833
1834  case MCK_Reg30:
1835    return B == MCK_OddSP;
1836
1837  case MCK_MemOffsetSimm11:
1838    return B == MCK_Mem;
1839
1840  case MCK_MemOffsetSimm16:
1841    return B == MCK_Mem;
1842
1843  case MCK_MemOffsetSimm9:
1844    return B == MCK_Mem;
1845
1846  case MCK_MemOffsetSimm9GPR:
1847    return B == MCK_Mem;
1848
1849  case MCK_MemOffsetUimm4:
1850    return B == MCK_Mem;
1851
1852  case MCK_ConstantImmz:
1853    switch (B) {
1854    default: return false;
1855    case MCK_ConstantUImm1_0: return true;
1856    case MCK_ConstantUImm2_0: return true;
1857    case MCK_ConstantUImm3_0: return true;
1858    case MCK_ConstantUImm4_0: return true;
1859    case MCK_ConstantUImm5_0: return true;
1860    case MCK_ConstantUImm5_32: return true;
1861    case MCK_ConstantUImm5_32_Norm: return true;
1862    case MCK_ConstantUImm6_0: return true;
1863    case MCK_ConstantUImm7_0: return true;
1864    case MCK_ConstantUImm8_0: return true;
1865    case MCK_ConstantUImm10_0: return true;
1866    case MCK_UImm16: return true;
1867    case MCK_UImm16_Relaxed: return true;
1868    }
1869
1870  case MCK_ConstantUImm1_0:
1871    switch (B) {
1872    default: return false;
1873    case MCK_ConstantUImm2_0: return true;
1874    case MCK_ConstantUImm3_0: return true;
1875    case MCK_ConstantUImm4_0: return true;
1876    case MCK_ConstantUImm5_0: return true;
1877    case MCK_ConstantUImm5_32: return true;
1878    case MCK_ConstantUImm5_32_Norm: return true;
1879    case MCK_ConstantUImm6_0: return true;
1880    case MCK_ConstantUImm7_0: return true;
1881    case MCK_ConstantUImm8_0: return true;
1882    case MCK_ConstantUImm10_0: return true;
1883    case MCK_UImm16: return true;
1884    case MCK_UImm16_Relaxed: return true;
1885    }
1886
1887  case MCK_ConstantUImm2_0:
1888    switch (B) {
1889    default: return false;
1890    case MCK_ConstantUImm3_0: return true;
1891    case MCK_ConstantUImm4_0: return true;
1892    case MCK_ConstantUImm5_0: return true;
1893    case MCK_ConstantUImm5_32: return true;
1894    case MCK_ConstantUImm5_32_Norm: return true;
1895    case MCK_ConstantUImm6_0: return true;
1896    case MCK_ConstantUImm7_0: return true;
1897    case MCK_ConstantUImm8_0: return true;
1898    case MCK_ConstantUImm10_0: return true;
1899    case MCK_UImm16: return true;
1900    case MCK_UImm16_Relaxed: return true;
1901    }
1902
1903  case MCK_ConstantUImm2_1:
1904    switch (B) {
1905    default: return false;
1906    case MCK_ConstantUImm3_0: return true;
1907    case MCK_ConstantUImm4_0: return true;
1908    case MCK_ConstantUImm5_0: return true;
1909    case MCK_ConstantUImm5_32: return true;
1910    case MCK_ConstantUImm5_32_Norm: return true;
1911    case MCK_ConstantUImm6_0: return true;
1912    case MCK_ConstantUImm7_0: return true;
1913    case MCK_ConstantUImm8_0: return true;
1914    case MCK_ConstantUImm10_0: return true;
1915    case MCK_UImm16: return true;
1916    case MCK_UImm16_Relaxed: return true;
1917    }
1918
1919  case MCK_ConstantUImm3_0:
1920    switch (B) {
1921    default: return false;
1922    case MCK_ConstantUImm4_0: return true;
1923    case MCK_ConstantUImm5_0: return true;
1924    case MCK_ConstantUImm5_32: return true;
1925    case MCK_ConstantUImm5_32_Norm: return true;
1926    case MCK_ConstantUImm6_0: return true;
1927    case MCK_ConstantUImm7_0: return true;
1928    case MCK_ConstantUImm8_0: return true;
1929    case MCK_ConstantUImm10_0: return true;
1930    case MCK_UImm16: return true;
1931    case MCK_UImm16_Relaxed: return true;
1932    }
1933
1934  case MCK_ConstantUImm4_0:
1935    switch (B) {
1936    default: return false;
1937    case MCK_ConstantUImm5_0: return true;
1938    case MCK_ConstantUImm5_32: return true;
1939    case MCK_ConstantUImm5_32_Norm: return true;
1940    case MCK_ConstantUImm6_0: return true;
1941    case MCK_ConstantUImm7_0: return true;
1942    case MCK_ConstantUImm8_0: return true;
1943    case MCK_ConstantUImm10_0: return true;
1944    case MCK_UImm16: return true;
1945    case MCK_UImm16_Relaxed: return true;
1946    }
1947
1948  case MCK_ConstantUImm5_0:
1949    switch (B) {
1950    default: return false;
1951    case MCK_ConstantUImm6_0: return true;
1952    case MCK_ConstantUImm7_0: return true;
1953    case MCK_ConstantUImm8_0: return true;
1954    case MCK_ConstantUImm10_0: return true;
1955    case MCK_UImm16: return true;
1956    case MCK_UImm16_Relaxed: return true;
1957    }
1958
1959  case MCK_UImm5Lsl2:
1960    switch (B) {
1961    default: return false;
1962    case MCK_ConstantUImm6_0: return true;
1963    case MCK_ConstantUImm7_0: return true;
1964    case MCK_ConstantUImm8_0: return true;
1965    case MCK_ConstantUImm10_0: return true;
1966    case MCK_UImm16: return true;
1967    case MCK_UImm16_Relaxed: return true;
1968    }
1969
1970  case MCK_ConstantUImm5_1:
1971    switch (B) {
1972    default: return false;
1973    case MCK_ConstantUImm6_0: return true;
1974    case MCK_ConstantUImm7_0: return true;
1975    case MCK_ConstantUImm8_0: return true;
1976    case MCK_ConstantUImm10_0: return true;
1977    case MCK_UImm16: return true;
1978    case MCK_UImm16_Relaxed: return true;
1979    }
1980
1981  case MCK_ConstantUImm5_32:
1982    switch (B) {
1983    default: return false;
1984    case MCK_ConstantUImm6_0: return true;
1985    case MCK_ConstantUImm7_0: return true;
1986    case MCK_ConstantUImm8_0: return true;
1987    case MCK_ConstantUImm10_0: return true;
1988    case MCK_UImm16: return true;
1989    case MCK_UImm16_Relaxed: return true;
1990    }
1991
1992  case MCK_ConstantUImm5_32_Norm:
1993    switch (B) {
1994    default: return false;
1995    case MCK_ConstantUImm6_0: return true;
1996    case MCK_ConstantUImm7_0: return true;
1997    case MCK_ConstantUImm8_0: return true;
1998    case MCK_ConstantUImm10_0: return true;
1999    case MCK_UImm16: return true;
2000    case MCK_UImm16_Relaxed: return true;
2001    }
2002
2003  case MCK_ConstantUImm5_33:
2004    switch (B) {
2005    default: return false;
2006    case MCK_ConstantUImm6_0: return true;
2007    case MCK_ConstantUImm7_0: return true;
2008    case MCK_ConstantUImm8_0: return true;
2009    case MCK_ConstantUImm10_0: return true;
2010    case MCK_UImm16: return true;
2011    case MCK_UImm16_Relaxed: return true;
2012    }
2013
2014  case MCK_ConstantUImm5_0_Report_UImm6:
2015    switch (B) {
2016    default: return false;
2017    case MCK_ConstantUImm6_0: return true;
2018    case MCK_ConstantUImm7_0: return true;
2019    case MCK_ConstantUImm8_0: return true;
2020    case MCK_ConstantUImm10_0: return true;
2021    case MCK_UImm16: return true;
2022    case MCK_UImm16_Relaxed: return true;
2023    }
2024
2025  case MCK_ConstantSImm6:
2026    switch (B) {
2027    default: return false;
2028    case MCK_ConstantUImm7_0: return true;
2029    case MCK_ConstantUImm8_0: return true;
2030    case MCK_ConstantUImm10_0: return true;
2031    case MCK_UImm16: return true;
2032    case MCK_UImm16_Relaxed: return true;
2033    }
2034
2035  case MCK_ConstantUImm6_0:
2036    switch (B) {
2037    default: return false;
2038    case MCK_ConstantUImm7_0: return true;
2039    case MCK_ConstantUImm8_0: return true;
2040    case MCK_ConstantUImm10_0: return true;
2041    case MCK_UImm16: return true;
2042    case MCK_UImm16_Relaxed: return true;
2043    }
2044
2045  case MCK_ConstantUImm7_0:
2046    switch (B) {
2047    default: return false;
2048    case MCK_ConstantUImm8_0: return true;
2049    case MCK_ConstantUImm10_0: return true;
2050    case MCK_UImm16: return true;
2051    case MCK_UImm16_Relaxed: return true;
2052    }
2053
2054  case MCK_ConstantUImm8_0:
2055    switch (B) {
2056    default: return false;
2057    case MCK_ConstantUImm10_0: return true;
2058    case MCK_UImm16: return true;
2059    case MCK_UImm16_Relaxed: return true;
2060    }
2061
2062  case MCK_ConstantUImm10_0:
2063    switch (B) {
2064    default: return false;
2065    case MCK_UImm16: return true;
2066    case MCK_UImm16_Relaxed: return true;
2067    }
2068
2069  case MCK_UImm16:
2070    return B == MCK_UImm16_Relaxed;
2071  }
2072}
2073
2074static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) {
2075  MipsOperand &Operand = (MipsOperand&)GOp;
2076  if (Kind == InvalidMatchClass)
2077    return MCTargetAsmParser::Match_InvalidOperand;
2078
2079  if (Operand.isToken())
2080    return isSubclass(matchTokenString(Operand.getToken()), Kind) ?
2081             MCTargetAsmParser::Match_Success :
2082             MCTargetAsmParser::Match_InvalidOperand;
2083
2084  // 'ACC64DSPAsmReg' class
2085  if (Kind == MCK_ACC64DSPAsmReg) {
2086    if (Operand.isACCAsmReg())
2087      return MCTargetAsmParser::Match_Success;
2088  }
2089
2090  // 'AFGR64AsmReg' class
2091  if (Kind == MCK_AFGR64AsmReg) {
2092    if (Operand.isFGRAsmReg())
2093      return MCTargetAsmParser::Match_Success;
2094  }
2095
2096  // 'CCRAsmReg' class
2097  if (Kind == MCK_CCRAsmReg) {
2098    if (Operand.isCCRAsmReg())
2099      return MCTargetAsmParser::Match_Success;
2100  }
2101
2102  // 'COP0AsmReg' class
2103  if (Kind == MCK_COP0AsmReg) {
2104    if (Operand.isCOP0AsmReg())
2105      return MCTargetAsmParser::Match_Success;
2106  }
2107
2108  // 'COP2AsmReg' class
2109  if (Kind == MCK_COP2AsmReg) {
2110    if (Operand.isCOP2AsmReg())
2111      return MCTargetAsmParser::Match_Success;
2112  }
2113
2114  // 'COP3AsmReg' class
2115  if (Kind == MCK_COP3AsmReg) {
2116    if (Operand.isCOP3AsmReg())
2117      return MCTargetAsmParser::Match_Success;
2118  }
2119
2120  // 'FCCAsmReg' class
2121  if (Kind == MCK_FCCAsmReg) {
2122    if (Operand.isFCCAsmReg())
2123      return MCTargetAsmParser::Match_Success;
2124  }
2125
2126  // 'FGR32AsmReg' class
2127  if (Kind == MCK_FGR32AsmReg) {
2128    if (Operand.isFGRAsmReg())
2129      return MCTargetAsmParser::Match_Success;
2130  }
2131
2132  // 'FGR64AsmReg' class
2133  if (Kind == MCK_FGR64AsmReg) {
2134    if (Operand.isFGRAsmReg())
2135      return MCTargetAsmParser::Match_Success;
2136  }
2137
2138  // 'FGRH32AsmReg' class
2139  if (Kind == MCK_FGRH32AsmReg) {
2140    if (Operand.isFGRAsmReg())
2141      return MCTargetAsmParser::Match_Success;
2142  }
2143
2144  // 'GPR32AsmReg' class
2145  if (Kind == MCK_GPR32AsmReg) {
2146    if (Operand.isGPRAsmReg())
2147      return MCTargetAsmParser::Match_Success;
2148  }
2149
2150  // 'GPR64AsmReg' class
2151  if (Kind == MCK_GPR64AsmReg) {
2152    if (Operand.isGPRAsmReg())
2153      return MCTargetAsmParser::Match_Success;
2154  }
2155
2156  // 'GPRMM16AsmReg' class
2157  if (Kind == MCK_GPRMM16AsmReg) {
2158    if (Operand.isMM16AsmReg())
2159      return MCTargetAsmParser::Match_Success;
2160  }
2161
2162  // 'GPRMM16AsmRegMoveP' class
2163  if (Kind == MCK_GPRMM16AsmRegMoveP) {
2164    if (Operand.isMM16AsmRegMoveP())
2165      return MCTargetAsmParser::Match_Success;
2166  }
2167
2168  // 'GPRMM16AsmRegZero' class
2169  if (Kind == MCK_GPRMM16AsmRegZero) {
2170    if (Operand.isMM16AsmRegZero())
2171      return MCTargetAsmParser::Match_Success;
2172  }
2173
2174  // 'HI32DSPAsmReg' class
2175  if (Kind == MCK_HI32DSPAsmReg) {
2176    if (Operand.isACCAsmReg())
2177      return MCTargetAsmParser::Match_Success;
2178  }
2179
2180  // 'HWRegsAsmReg' class
2181  if (Kind == MCK_HWRegsAsmReg) {
2182    if (Operand.isHWRegsAsmReg())
2183      return MCTargetAsmParser::Match_Success;
2184  }
2185
2186  // 'Imm' class
2187  if (Kind == MCK_Imm) {
2188    if (Operand.isImm())
2189      return MCTargetAsmParser::Match_Success;
2190  }
2191
2192  // 'LO32DSPAsmReg' class
2193  if (Kind == MCK_LO32DSPAsmReg) {
2194    if (Operand.isACCAsmReg())
2195      return MCTargetAsmParser::Match_Success;
2196  }
2197
2198  // 'MSA128AsmReg' class
2199  if (Kind == MCK_MSA128AsmReg) {
2200    if (Operand.isMSA128AsmReg())
2201      return MCTargetAsmParser::Match_Success;
2202  }
2203
2204  // 'MSACtrlAsmReg' class
2205  if (Kind == MCK_MSACtrlAsmReg) {
2206    if (Operand.isMSACtrlAsmReg())
2207      return MCTargetAsmParser::Match_Success;
2208  }
2209
2210  // 'MicroMipsMem' class
2211  if (Kind == MCK_MicroMipsMem) {
2212    if (Operand.isMemWithGRPMM16Base())
2213      return MCTargetAsmParser::Match_Success;
2214  }
2215
2216  // 'MicroMipsMemSP' class
2217  if (Kind == MCK_MicroMipsMemSP) {
2218    if (Operand.isMemWithUimmWordAlignedOffsetSP<7>())
2219      return MCTargetAsmParser::Match_Success;
2220  }
2221
2222  // 'InvNum' class
2223  if (Kind == MCK_InvNum) {
2224    if (Operand.isInvNum())
2225      return MCTargetAsmParser::Match_Success;
2226  }
2227
2228  // 'JumpTarget' class
2229  if (Kind == MCK_JumpTarget) {
2230    if (Operand.isImm())
2231      return MCTargetAsmParser::Match_Success;
2232  }
2233
2234  // 'MemOffsetSimm11' class
2235  if (Kind == MCK_MemOffsetSimm11) {
2236    if (Operand.isMemWithSimmOffset<11>())
2237      return MCTargetAsmParser::Match_Success;
2238  }
2239
2240  // 'MemOffsetSimm16' class
2241  if (Kind == MCK_MemOffsetSimm16) {
2242    if (Operand.isMemWithSimmOffset<16>())
2243      return MCTargetAsmParser::Match_Success;
2244  }
2245
2246  // 'MemOffsetSimm9' class
2247  if (Kind == MCK_MemOffsetSimm9) {
2248    if (Operand.isMemWithSimmOffset<9>())
2249      return MCTargetAsmParser::Match_Success;
2250  }
2251
2252  // 'MemOffsetSimm9GPR' class
2253  if (Kind == MCK_MemOffsetSimm9GPR) {
2254    if (Operand.isMemWithSimmOffsetGPR<9>())
2255      return MCTargetAsmParser::Match_Success;
2256  }
2257
2258  // 'MemOffsetUimm4' class
2259  if (Kind == MCK_MemOffsetUimm4) {
2260    if (Operand.isMemWithUimmOffsetSP<6>())
2261      return MCTargetAsmParser::Match_Success;
2262  }
2263
2264  // 'Mem' class
2265  if (Kind == MCK_Mem) {
2266    if (Operand.isMem())
2267      return MCTargetAsmParser::Match_Success;
2268  }
2269
2270  // 'MovePRegPair' class
2271  if (Kind == MCK_MovePRegPair) {
2272    if (Operand.isMovePRegPair())
2273      return MCTargetAsmParser::Match_Success;
2274  }
2275
2276  // 'RegList16' class
2277  if (Kind == MCK_RegList16) {
2278    if (Operand.isRegList16())
2279      return MCTargetAsmParser::Match_Success;
2280  }
2281
2282  // 'RegList' class
2283  if (Kind == MCK_RegList) {
2284    if (Operand.isRegList())
2285      return MCTargetAsmParser::Match_Success;
2286  }
2287
2288  // 'RegPair' class
2289  if (Kind == MCK_RegPair) {
2290    if (Operand.isRegPair())
2291      return MCTargetAsmParser::Match_Success;
2292  }
2293
2294  // 'ConstantImmz' class
2295  if (Kind == MCK_ConstantImmz) {
2296    if (Operand.isConstantImmz())
2297      return MCTargetAsmParser::Match_Success;
2298    return MipsAsmParser::Match_Immz;
2299  }
2300
2301  // 'ConstantUImm1_0' class
2302  if (Kind == MCK_ConstantUImm1_0) {
2303    if (Operand.isConstantUImm<1, 0>())
2304      return MCTargetAsmParser::Match_Success;
2305    return MipsAsmParser::Match_UImm1_0;
2306  }
2307
2308  // 'ConstantUImm2_0' class
2309  if (Kind == MCK_ConstantUImm2_0) {
2310    if (Operand.isConstantUImm<2, 0>())
2311      return MCTargetAsmParser::Match_Success;
2312    return MipsAsmParser::Match_UImm2_0;
2313  }
2314
2315  // 'ConstantUImm2_1' class
2316  if (Kind == MCK_ConstantUImm2_1) {
2317    if (Operand.isConstantUImm<2, 1>())
2318      return MCTargetAsmParser::Match_Success;
2319    return MipsAsmParser::Match_UImm2_1;
2320  }
2321
2322  // 'ConstantUImm3_0' class
2323  if (Kind == MCK_ConstantUImm3_0) {
2324    if (Operand.isConstantUImm<3, 0>())
2325      return MCTargetAsmParser::Match_Success;
2326    return MipsAsmParser::Match_UImm3_0;
2327  }
2328
2329  // 'ConstantUImm4_0' class
2330  if (Kind == MCK_ConstantUImm4_0) {
2331    if (Operand.isConstantUImm<4, 0>())
2332      return MCTargetAsmParser::Match_Success;
2333    return MipsAsmParser::Match_UImm4_0;
2334  }
2335
2336  // 'ConstantUImm5_0' class
2337  if (Kind == MCK_ConstantUImm5_0) {
2338    if (Operand.isConstantUImm<5, 0>())
2339      return MCTargetAsmParser::Match_Success;
2340    return MipsAsmParser::Match_UImm5_0;
2341  }
2342
2343  // 'UImm5Lsl2' class
2344  if (Kind == MCK_UImm5Lsl2) {
2345    if (Operand.isScaledUImm<5, 2>())
2346      return MCTargetAsmParser::Match_Success;
2347    return MipsAsmParser::Match_UImm5_Lsl2;
2348  }
2349
2350  // 'ConstantUImm5_1' class
2351  if (Kind == MCK_ConstantUImm5_1) {
2352    if (Operand.isConstantUImm<5, 1>())
2353      return MCTargetAsmParser::Match_Success;
2354    return MipsAsmParser::Match_UImm5_1;
2355  }
2356
2357  // 'ConstantUImm5_32' class
2358  if (Kind == MCK_ConstantUImm5_32) {
2359    if (Operand.isConstantUImm<5, 32>())
2360      return MCTargetAsmParser::Match_Success;
2361    return MipsAsmParser::Match_UImm5_32;
2362  }
2363
2364  // 'ConstantUImm5_32_Norm' class
2365  if (Kind == MCK_ConstantUImm5_32_Norm) {
2366    if (Operand.isConstantUImm<5, 32>())
2367      return MCTargetAsmParser::Match_Success;
2368    return MipsAsmParser::Match_UImm5_32;
2369  }
2370
2371  // 'ConstantUImm5_33' class
2372  if (Kind == MCK_ConstantUImm5_33) {
2373    if (Operand.isConstantUImm<5, 33>())
2374      return MCTargetAsmParser::Match_Success;
2375    return MipsAsmParser::Match_UImm5_33;
2376  }
2377
2378  // 'ConstantUImm5_0_Report_UImm6' class
2379  if (Kind == MCK_ConstantUImm5_0_Report_UImm6) {
2380    if (Operand.isConstantUImm<5, 0>())
2381      return MCTargetAsmParser::Match_Success;
2382    return MipsAsmParser::Match_UImm5_0_Report_UImm6;
2383  }
2384
2385  // 'ConstantSImm6' class
2386  if (Kind == MCK_ConstantSImm6) {
2387    if (Operand.isConstantSImm<6>())
2388      return MCTargetAsmParser::Match_Success;
2389    return MipsAsmParser::Match_SImm6;
2390  }
2391
2392  // 'ConstantUImm6_0' class
2393  if (Kind == MCK_ConstantUImm6_0) {
2394    if (Operand.isConstantUImm<6, 0>())
2395      return MCTargetAsmParser::Match_Success;
2396    return MipsAsmParser::Match_UImm6_0;
2397  }
2398
2399  // 'ConstantUImm7_0' class
2400  if (Kind == MCK_ConstantUImm7_0) {
2401    if (Operand.isConstantUImm<7, 0>())
2402      return MCTargetAsmParser::Match_Success;
2403    return MipsAsmParser::Match_UImm7_0;
2404  }
2405
2406  // 'ConstantUImm8_0' class
2407  if (Kind == MCK_ConstantUImm8_0) {
2408    if (Operand.isConstantUImm<8, 0>())
2409      return MCTargetAsmParser::Match_Success;
2410    return MipsAsmParser::Match_UImm8_0;
2411  }
2412
2413  // 'ConstantUImm10_0' class
2414  if (Kind == MCK_ConstantUImm10_0) {
2415    if (Operand.isConstantUImm<10, 0>())
2416      return MCTargetAsmParser::Match_Success;
2417    return MipsAsmParser::Match_UImm10_0;
2418  }
2419
2420  // 'UImm16' class
2421  if (Kind == MCK_UImm16) {
2422    if (Operand.isUImm<16>())
2423      return MCTargetAsmParser::Match_Success;
2424    return MipsAsmParser::Match_UImm16;
2425  }
2426
2427  // 'UImm16_Relaxed' class
2428  if (Kind == MCK_UImm16_Relaxed) {
2429    if (Operand.isAnyImm<16>())
2430      return MCTargetAsmParser::Match_Success;
2431    return MipsAsmParser::Match_UImm16_Relaxed;
2432  }
2433
2434  if (Operand.isReg()) {
2435    MatchClassKind OpKind;
2436    switch (Operand.getReg()) {
2437    default: OpKind = InvalidMatchClass; break;
2438    case Mips::ZERO: OpKind = MCK_ZERO; break;
2439    case Mips::AT: OpKind = MCK_DSPR; break;
2440    case Mips::V0: OpKind = MCK_Reg9; break;
2441    case Mips::V1: OpKind = MCK_Reg9; break;
2442    case Mips::A0: OpKind = MCK_Reg7; break;
2443    case Mips::A1: OpKind = MCK_Reg7; break;
2444    case Mips::A2: OpKind = MCK_Reg7; break;
2445    case Mips::A3: OpKind = MCK_Reg7; break;
2446    case Mips::T0: OpKind = MCK_DSPR; break;
2447    case Mips::T1: OpKind = MCK_DSPR; break;
2448    case Mips::T2: OpKind = MCK_DSPR; break;
2449    case Mips::T3: OpKind = MCK_DSPR; break;
2450    case Mips::T4: OpKind = MCK_DSPR; break;
2451    case Mips::T5: OpKind = MCK_DSPR; break;
2452    case Mips::T6: OpKind = MCK_DSPR; break;
2453    case Mips::T7: OpKind = MCK_DSPR; break;
2454    case Mips::S0: OpKind = MCK_Reg8; break;
2455    case Mips::S1: OpKind = MCK_Reg9; break;
2456    case Mips::S2: OpKind = MCK_GPRMM16MoveP; break;
2457    case Mips::S3: OpKind = MCK_GPRMM16MoveP; break;
2458    case Mips::S4: OpKind = MCK_GPRMM16MoveP; break;
2459    case Mips::S5: OpKind = MCK_DSPR; break;
2460    case Mips::S6: OpKind = MCK_DSPR; break;
2461    case Mips::S7: OpKind = MCK_DSPR; break;
2462    case Mips::T8: OpKind = MCK_DSPR; break;
2463    case Mips::T9: OpKind = MCK_DSPR; break;
2464    case Mips::K0: OpKind = MCK_DSPR; break;
2465    case Mips::K1: OpKind = MCK_DSPR; break;
2466    case Mips::GP: OpKind = MCK_DSPR; break;
2467    case Mips::SP: OpKind = MCK_CPUSPReg; break;
2468    case Mips::FP: OpKind = MCK_DSPR; break;
2469    case Mips::RA: OpKind = MCK_CPURAReg; break;
2470    case Mips::ZERO_64: OpKind = MCK_Reg15; break;
2471    case Mips::AT_64: OpKind = MCK_GPR64; break;
2472    case Mips::V0_64: OpKind = MCK_Reg20; break;
2473    case Mips::V1_64: OpKind = MCK_Reg20; break;
2474    case Mips::A0_64: OpKind = MCK_Reg18; break;
2475    case Mips::A1_64: OpKind = MCK_Reg18; break;
2476    case Mips::A2_64: OpKind = MCK_Reg18; break;
2477    case Mips::A3_64: OpKind = MCK_Reg18; break;
2478    case Mips::T0_64: OpKind = MCK_GPR64; break;
2479    case Mips::T1_64: OpKind = MCK_GPR64; break;
2480    case Mips::T2_64: OpKind = MCK_GPR64; break;
2481    case Mips::T3_64: OpKind = MCK_GPR64; break;
2482    case Mips::T4_64: OpKind = MCK_GPR64; break;
2483    case Mips::T5_64: OpKind = MCK_GPR64; break;
2484    case Mips::T6_64: OpKind = MCK_GPR64; break;
2485    case Mips::T7_64: OpKind = MCK_GPR64; break;
2486    case Mips::S0_64: OpKind = MCK_Reg19; break;
2487    case Mips::S1_64: OpKind = MCK_Reg20; break;
2488    case Mips::S2_64: OpKind = MCK_Reg14; break;
2489    case Mips::S3_64: OpKind = MCK_Reg14; break;
2490    case Mips::S4_64: OpKind = MCK_Reg14; break;
2491    case Mips::S5_64: OpKind = MCK_GPR64; break;
2492    case Mips::S6_64: OpKind = MCK_GPR64; break;
2493    case Mips::S7_64: OpKind = MCK_GPR64; break;
2494    case Mips::T8_64: OpKind = MCK_GPR64; break;
2495    case Mips::T9_64: OpKind = MCK_GPR64; break;
2496    case Mips::K0_64: OpKind = MCK_GPR64; break;
2497    case Mips::K1_64: OpKind = MCK_GPR64; break;
2498    case Mips::GP_64: OpKind = MCK_GPR64; break;
2499    case Mips::SP_64: OpKind = MCK_Reg21; break;
2500    case Mips::FP_64: OpKind = MCK_GPR64; break;
2501    case Mips::RA_64: OpKind = MCK_Reg22; break;
2502    case Mips::F0: OpKind = MCK_FGR32; break;
2503    case Mips::F1: OpKind = MCK_Reg24; break;
2504    case Mips::F2: OpKind = MCK_FGR32; break;
2505    case Mips::F3: OpKind = MCK_Reg24; break;
2506    case Mips::F4: OpKind = MCK_FGR32; break;
2507    case Mips::F5: OpKind = MCK_Reg24; break;
2508    case Mips::F6: OpKind = MCK_FGR32; break;
2509    case Mips::F7: OpKind = MCK_Reg24; break;
2510    case Mips::F8: OpKind = MCK_FGR32; break;
2511    case Mips::F9: OpKind = MCK_Reg24; break;
2512    case Mips::F10: OpKind = MCK_FGR32; break;
2513    case Mips::F11: OpKind = MCK_Reg24; break;
2514    case Mips::F12: OpKind = MCK_FGR32; break;
2515    case Mips::F13: OpKind = MCK_Reg24; break;
2516    case Mips::F14: OpKind = MCK_FGR32; break;
2517    case Mips::F15: OpKind = MCK_Reg24; break;
2518    case Mips::F16: OpKind = MCK_FGR32; break;
2519    case Mips::F17: OpKind = MCK_Reg24; break;
2520    case Mips::F18: OpKind = MCK_FGR32; break;
2521    case Mips::F19: OpKind = MCK_Reg24; break;
2522    case Mips::F20: OpKind = MCK_FGR32; break;
2523    case Mips::F21: OpKind = MCK_Reg24; break;
2524    case Mips::F22: OpKind = MCK_FGR32; break;
2525    case Mips::F23: OpKind = MCK_Reg24; break;
2526    case Mips::F24: OpKind = MCK_FGR32; break;
2527    case Mips::F25: OpKind = MCK_Reg24; break;
2528    case Mips::F26: OpKind = MCK_FGR32; break;
2529    case Mips::F27: OpKind = MCK_Reg24; break;
2530    case Mips::F28: OpKind = MCK_FGR32; break;
2531    case Mips::F29: OpKind = MCK_Reg24; break;
2532    case Mips::F30: OpKind = MCK_FGR32; break;
2533    case Mips::F31: OpKind = MCK_Reg24; break;
2534    case Mips::F_HI0: OpKind = MCK_FGRH32; break;
2535    case Mips::F_HI1: OpKind = MCK_Reg27; break;
2536    case Mips::F_HI2: OpKind = MCK_FGRH32; break;
2537    case Mips::F_HI3: OpKind = MCK_Reg27; break;
2538    case Mips::F_HI4: OpKind = MCK_FGRH32; break;
2539    case Mips::F_HI5: OpKind = MCK_Reg27; break;
2540    case Mips::F_HI6: OpKind = MCK_FGRH32; break;
2541    case Mips::F_HI7: OpKind = MCK_Reg27; break;
2542    case Mips::F_HI8: OpKind = MCK_FGRH32; break;
2543    case Mips::F_HI9: OpKind = MCK_Reg27; break;
2544    case Mips::F_HI10: OpKind = MCK_FGRH32; break;
2545    case Mips::F_HI11: OpKind = MCK_Reg27; break;
2546    case Mips::F_HI12: OpKind = MCK_FGRH32; break;
2547    case Mips::F_HI13: OpKind = MCK_Reg27; break;
2548    case Mips::F_HI14: OpKind = MCK_FGRH32; break;
2549    case Mips::F_HI15: OpKind = MCK_Reg27; break;
2550    case Mips::F_HI16: OpKind = MCK_FGRH32; break;
2551    case Mips::F_HI17: OpKind = MCK_Reg27; break;
2552    case Mips::F_HI18: OpKind = MCK_FGRH32; break;
2553    case Mips::F_HI19: OpKind = MCK_Reg27; break;
2554    case Mips::F_HI20: OpKind = MCK_FGRH32; break;
2555    case Mips::F_HI21: OpKind = MCK_Reg27; break;
2556    case Mips::F_HI22: OpKind = MCK_FGRH32; break;
2557    case Mips::F_HI23: OpKind = MCK_Reg27; break;
2558    case Mips::F_HI24: OpKind = MCK_FGRH32; break;
2559    case Mips::F_HI25: OpKind = MCK_Reg27; break;
2560    case Mips::F_HI26: OpKind = MCK_FGRH32; break;
2561    case Mips::F_HI27: OpKind = MCK_Reg27; break;
2562    case Mips::F_HI28: OpKind = MCK_FGRH32; break;
2563    case Mips::F_HI29: OpKind = MCK_Reg27; break;
2564    case Mips::F_HI30: OpKind = MCK_FGRH32; break;
2565    case Mips::F_HI31: OpKind = MCK_Reg27; break;
2566    case Mips::D0: OpKind = MCK_AFGR64; break;
2567    case Mips::D1: OpKind = MCK_Reg29; break;
2568    case Mips::D2: OpKind = MCK_AFGR64; break;
2569    case Mips::D3: OpKind = MCK_Reg29; break;
2570    case Mips::D4: OpKind = MCK_AFGR64; break;
2571    case Mips::D5: OpKind = MCK_Reg29; break;
2572    case Mips::D6: OpKind = MCK_AFGR64; break;
2573    case Mips::D7: OpKind = MCK_Reg29; break;
2574    case Mips::D8: OpKind = MCK_AFGR64; break;
2575    case Mips::D9: OpKind = MCK_Reg29; break;
2576    case Mips::D10: OpKind = MCK_AFGR64; break;
2577    case Mips::D11: OpKind = MCK_Reg29; break;
2578    case Mips::D12: OpKind = MCK_AFGR64; break;
2579    case Mips::D13: OpKind = MCK_Reg29; break;
2580    case Mips::D14: OpKind = MCK_AFGR64; break;
2581    case Mips::D15: OpKind = MCK_Reg29; break;
2582    case Mips::D0_64: OpKind = MCK_FGR64; break;
2583    case Mips::D1_64: OpKind = MCK_Reg32; break;
2584    case Mips::D2_64: OpKind = MCK_FGR64; break;
2585    case Mips::D3_64: OpKind = MCK_Reg32; break;
2586    case Mips::D4_64: OpKind = MCK_FGR64; break;
2587    case Mips::D5_64: OpKind = MCK_Reg32; break;
2588    case Mips::D6_64: OpKind = MCK_FGR64; break;
2589    case Mips::D7_64: OpKind = MCK_Reg32; break;
2590    case Mips::D8_64: OpKind = MCK_FGR64; break;
2591    case Mips::D9_64: OpKind = MCK_Reg32; break;
2592    case Mips::D10_64: OpKind = MCK_FGR64; break;
2593    case Mips::D11_64: OpKind = MCK_Reg32; break;
2594    case Mips::D12_64: OpKind = MCK_FGR64; break;
2595    case Mips::D13_64: OpKind = MCK_Reg32; break;
2596    case Mips::D14_64: OpKind = MCK_FGR64; break;
2597    case Mips::D15_64: OpKind = MCK_Reg32; break;
2598    case Mips::D16_64: OpKind = MCK_FGR64; break;
2599    case Mips::D17_64: OpKind = MCK_Reg32; break;
2600    case Mips::D18_64: OpKind = MCK_FGR64; break;
2601    case Mips::D19_64: OpKind = MCK_Reg32; break;
2602    case Mips::D20_64: OpKind = MCK_FGR64; break;
2603    case Mips::D21_64: OpKind = MCK_Reg32; break;
2604    case Mips::D22_64: OpKind = MCK_FGR64; break;
2605    case Mips::D23_64: OpKind = MCK_Reg32; break;
2606    case Mips::D24_64: OpKind = MCK_FGR64; break;
2607    case Mips::D25_64: OpKind = MCK_Reg32; break;
2608    case Mips::D26_64: OpKind = MCK_FGR64; break;
2609    case Mips::D27_64: OpKind = MCK_Reg32; break;
2610    case Mips::D28_64: OpKind = MCK_FGR64; break;
2611    case Mips::D29_64: OpKind = MCK_Reg32; break;
2612    case Mips::D30_64: OpKind = MCK_FGR64; break;
2613    case Mips::D31_64: OpKind = MCK_Reg32; break;
2614    case Mips::W0: OpKind = MCK_MSA128WEvens; break;
2615    case Mips::W1: OpKind = MCK_Reg35; break;
2616    case Mips::W2: OpKind = MCK_MSA128WEvens; break;
2617    case Mips::W3: OpKind = MCK_Reg35; break;
2618    case Mips::W4: OpKind = MCK_MSA128WEvens; break;
2619    case Mips::W5: OpKind = MCK_Reg35; break;
2620    case Mips::W6: OpKind = MCK_MSA128WEvens; break;
2621    case Mips::W7: OpKind = MCK_Reg35; break;
2622    case Mips::W8: OpKind = MCK_MSA128WEvens; break;
2623    case Mips::W9: OpKind = MCK_Reg35; break;
2624    case Mips::W10: OpKind = MCK_MSA128WEvens; break;
2625    case Mips::W11: OpKind = MCK_Reg35; break;
2626    case Mips::W12: OpKind = MCK_MSA128WEvens; break;
2627    case Mips::W13: OpKind = MCK_Reg35; break;
2628    case Mips::W14: OpKind = MCK_MSA128WEvens; break;
2629    case Mips::W15: OpKind = MCK_Reg35; break;
2630    case Mips::W16: OpKind = MCK_MSA128WEvens; break;
2631    case Mips::W17: OpKind = MCK_Reg35; break;
2632    case Mips::W18: OpKind = MCK_MSA128WEvens; break;
2633    case Mips::W19: OpKind = MCK_Reg35; break;
2634    case Mips::W20: OpKind = MCK_MSA128WEvens; break;
2635    case Mips::W21: OpKind = MCK_Reg35; break;
2636    case Mips::W22: OpKind = MCK_MSA128WEvens; break;
2637    case Mips::W23: OpKind = MCK_Reg35; break;
2638    case Mips::W24: OpKind = MCK_MSA128WEvens; break;
2639    case Mips::W25: OpKind = MCK_Reg35; break;
2640    case Mips::W26: OpKind = MCK_MSA128WEvens; break;
2641    case Mips::W27: OpKind = MCK_Reg35; break;
2642    case Mips::W28: OpKind = MCK_MSA128WEvens; break;
2643    case Mips::W29: OpKind = MCK_Reg35; break;
2644    case Mips::W30: OpKind = MCK_MSA128WEvens; break;
2645    case Mips::W31: OpKind = MCK_Reg35; break;
2646    case Mips::HI0: OpKind = MCK_HI32; break;
2647    case Mips::HI1: OpKind = MCK_HI32DSP; break;
2648    case Mips::HI2: OpKind = MCK_HI32DSP; break;
2649    case Mips::HI3: OpKind = MCK_HI32DSP; break;
2650    case Mips::LO0: OpKind = MCK_LO32; break;
2651    case Mips::LO1: OpKind = MCK_LO32DSP; break;
2652    case Mips::LO2: OpKind = MCK_LO32DSP; break;
2653    case Mips::LO3: OpKind = MCK_LO32DSP; break;
2654    case Mips::HI0_64: OpKind = MCK_HI64; break;
2655    case Mips::LO0_64: OpKind = MCK_LO64; break;
2656    case Mips::FCR0: OpKind = MCK_CCR; break;
2657    case Mips::FCR1: OpKind = MCK_CCR; break;
2658    case Mips::FCR2: OpKind = MCK_CCR; break;
2659    case Mips::FCR3: OpKind = MCK_CCR; break;
2660    case Mips::FCR4: OpKind = MCK_CCR; break;
2661    case Mips::FCR5: OpKind = MCK_CCR; break;
2662    case Mips::FCR6: OpKind = MCK_CCR; break;
2663    case Mips::FCR7: OpKind = MCK_CCR; break;
2664    case Mips::FCR8: OpKind = MCK_CCR; break;
2665    case Mips::FCR9: OpKind = MCK_CCR; break;
2666    case Mips::FCR10: OpKind = MCK_CCR; break;
2667    case Mips::FCR11: OpKind = MCK_CCR; break;
2668    case Mips::FCR12: OpKind = MCK_CCR; break;
2669    case Mips::FCR13: OpKind = MCK_CCR; break;
2670    case Mips::FCR14: OpKind = MCK_CCR; break;
2671    case Mips::FCR15: OpKind = MCK_CCR; break;
2672    case Mips::FCR16: OpKind = MCK_CCR; break;
2673    case Mips::FCR17: OpKind = MCK_CCR; break;
2674    case Mips::FCR18: OpKind = MCK_CCR; break;
2675    case Mips::FCR19: OpKind = MCK_CCR; break;
2676    case Mips::FCR20: OpKind = MCK_CCR; break;
2677    case Mips::FCR21: OpKind = MCK_CCR; break;
2678    case Mips::FCR22: OpKind = MCK_CCR; break;
2679    case Mips::FCR23: OpKind = MCK_CCR; break;
2680    case Mips::FCR24: OpKind = MCK_CCR; break;
2681    case Mips::FCR25: OpKind = MCK_CCR; break;
2682    case Mips::FCR26: OpKind = MCK_CCR; break;
2683    case Mips::FCR27: OpKind = MCK_CCR; break;
2684    case Mips::FCR28: OpKind = MCK_CCR; break;
2685    case Mips::FCR29: OpKind = MCK_CCR; break;
2686    case Mips::FCR30: OpKind = MCK_CCR; break;
2687    case Mips::FCR31: OpKind = MCK_CCR; break;
2688    case Mips::FCC0: OpKind = MCK_FCC; break;
2689    case Mips::FCC1: OpKind = MCK_FCC; break;
2690    case Mips::FCC2: OpKind = MCK_FCC; break;
2691    case Mips::FCC3: OpKind = MCK_FCC; break;
2692    case Mips::FCC4: OpKind = MCK_FCC; break;
2693    case Mips::FCC5: OpKind = MCK_FCC; break;
2694    case Mips::FCC6: OpKind = MCK_FCC; break;
2695    case Mips::FCC7: OpKind = MCK_FCC; break;
2696    case Mips::COP00: OpKind = MCK_COP0; break;
2697    case Mips::COP01: OpKind = MCK_COP0; break;
2698    case Mips::COP02: OpKind = MCK_COP0; break;
2699    case Mips::COP03: OpKind = MCK_COP0; break;
2700    case Mips::COP04: OpKind = MCK_COP0; break;
2701    case Mips::COP05: OpKind = MCK_COP0; break;
2702    case Mips::COP06: OpKind = MCK_COP0; break;
2703    case Mips::COP07: OpKind = MCK_COP0; break;
2704    case Mips::COP08: OpKind = MCK_COP0; break;
2705    case Mips::COP09: OpKind = MCK_COP0; break;
2706    case Mips::COP010: OpKind = MCK_COP0; break;
2707    case Mips::COP011: OpKind = MCK_COP0; break;
2708    case Mips::COP012: OpKind = MCK_COP0; break;
2709    case Mips::COP013: OpKind = MCK_COP0; break;
2710    case Mips::COP014: OpKind = MCK_COP0; break;
2711    case Mips::COP015: OpKind = MCK_COP0; break;
2712    case Mips::COP016: OpKind = MCK_COP0; break;
2713    case Mips::COP017: OpKind = MCK_COP0; break;
2714    case Mips::COP018: OpKind = MCK_COP0; break;
2715    case Mips::COP019: OpKind = MCK_COP0; break;
2716    case Mips::COP020: OpKind = MCK_COP0; break;
2717    case Mips::COP021: OpKind = MCK_COP0; break;
2718    case Mips::COP022: OpKind = MCK_COP0; break;
2719    case Mips::COP023: OpKind = MCK_COP0; break;
2720    case Mips::COP024: OpKind = MCK_COP0; break;
2721    case Mips::COP025: OpKind = MCK_COP0; break;
2722    case Mips::COP026: OpKind = MCK_COP0; break;
2723    case Mips::COP027: OpKind = MCK_COP0; break;
2724    case Mips::COP028: OpKind = MCK_COP0; break;
2725    case Mips::COP029: OpKind = MCK_COP0; break;
2726    case Mips::COP030: OpKind = MCK_COP0; break;
2727    case Mips::COP031: OpKind = MCK_COP0; break;
2728    case Mips::COP20: OpKind = MCK_COP2; break;
2729    case Mips::COP21: OpKind = MCK_COP2; break;
2730    case Mips::COP22: OpKind = MCK_COP2; break;
2731    case Mips::COP23: OpKind = MCK_COP2; break;
2732    case Mips::COP24: OpKind = MCK_COP2; break;
2733    case Mips::COP25: OpKind = MCK_COP2; break;
2734    case Mips::COP26: OpKind = MCK_COP2; break;
2735    case Mips::COP27: OpKind = MCK_COP2; break;
2736    case Mips::COP28: OpKind = MCK_COP2; break;
2737    case Mips::COP29: OpKind = MCK_COP2; break;
2738    case Mips::COP210: OpKind = MCK_COP2; break;
2739    case Mips::COP211: OpKind = MCK_COP2; break;
2740    case Mips::COP212: OpKind = MCK_COP2; break;
2741    case Mips::COP213: OpKind = MCK_COP2; break;
2742    case Mips::COP214: OpKind = MCK_COP2; break;
2743    case Mips::COP215: OpKind = MCK_COP2; break;
2744    case Mips::COP216: OpKind = MCK_COP2; break;
2745    case Mips::COP217: OpKind = MCK_COP2; break;
2746    case Mips::COP218: OpKind = MCK_COP2; break;
2747    case Mips::COP219: OpKind = MCK_COP2; break;
2748    case Mips::COP220: OpKind = MCK_COP2; break;
2749    case Mips::COP221: OpKind = MCK_COP2; break;
2750    case Mips::COP222: OpKind = MCK_COP2; break;
2751    case Mips::COP223: OpKind = MCK_COP2; break;
2752    case Mips::COP224: OpKind = MCK_COP2; break;
2753    case Mips::COP225: OpKind = MCK_COP2; break;
2754    case Mips::COP226: OpKind = MCK_COP2; break;
2755    case Mips::COP227: OpKind = MCK_COP2; break;
2756    case Mips::COP228: OpKind = MCK_COP2; break;
2757    case Mips::COP229: OpKind = MCK_COP2; break;
2758    case Mips::COP230: OpKind = MCK_COP2; break;
2759    case Mips::COP231: OpKind = MCK_COP2; break;
2760    case Mips::COP30: OpKind = MCK_COP3; break;
2761    case Mips::COP31: OpKind = MCK_COP3; break;
2762    case Mips::COP32: OpKind = MCK_COP3; break;
2763    case Mips::COP33: OpKind = MCK_COP3; break;
2764    case Mips::COP34: OpKind = MCK_COP3; break;
2765    case Mips::COP35: OpKind = MCK_COP3; break;
2766    case Mips::COP36: OpKind = MCK_COP3; break;
2767    case Mips::COP37: OpKind = MCK_COP3; break;
2768    case Mips::COP38: OpKind = MCK_COP3; break;
2769    case Mips::COP39: OpKind = MCK_COP3; break;
2770    case Mips::COP310: OpKind = MCK_COP3; break;
2771    case Mips::COP311: OpKind = MCK_COP3; break;
2772    case Mips::COP312: OpKind = MCK_COP3; break;
2773    case Mips::COP313: OpKind = MCK_COP3; break;
2774    case Mips::COP314: OpKind = MCK_COP3; break;
2775    case Mips::COP315: OpKind = MCK_COP3; break;
2776    case Mips::COP316: OpKind = MCK_COP3; break;
2777    case Mips::COP317: OpKind = MCK_COP3; break;
2778    case Mips::COP318: OpKind = MCK_COP3; break;
2779    case Mips::COP319: OpKind = MCK_COP3; break;
2780    case Mips::COP320: OpKind = MCK_COP3; break;
2781    case Mips::COP321: OpKind = MCK_COP3; break;
2782    case Mips::COP322: OpKind = MCK_COP3; break;
2783    case Mips::COP323: OpKind = MCK_COP3; break;
2784    case Mips::COP324: OpKind = MCK_COP3; break;
2785    case Mips::COP325: OpKind = MCK_COP3; break;
2786    case Mips::COP326: OpKind = MCK_COP3; break;
2787    case Mips::COP327: OpKind = MCK_COP3; break;
2788    case Mips::COP328: OpKind = MCK_COP3; break;
2789    case Mips::COP329: OpKind = MCK_COP3; break;
2790    case Mips::COP330: OpKind = MCK_COP3; break;
2791    case Mips::COP331: OpKind = MCK_COP3; break;
2792    case Mips::PC: OpKind = MCK_PC; break;
2793    case Mips::HWR0: OpKind = MCK_HWRegs; break;
2794    case Mips::HWR1: OpKind = MCK_HWRegs; break;
2795    case Mips::HWR2: OpKind = MCK_HWRegs; break;
2796    case Mips::HWR3: OpKind = MCK_HWRegs; break;
2797    case Mips::HWR4: OpKind = MCK_HWRegs; break;
2798    case Mips::HWR5: OpKind = MCK_HWRegs; break;
2799    case Mips::HWR6: OpKind = MCK_HWRegs; break;
2800    case Mips::HWR7: OpKind = MCK_HWRegs; break;
2801    case Mips::HWR8: OpKind = MCK_HWRegs; break;
2802    case Mips::HWR9: OpKind = MCK_HWRegs; break;
2803    case Mips::HWR10: OpKind = MCK_HWRegs; break;
2804    case Mips::HWR11: OpKind = MCK_HWRegs; break;
2805    case Mips::HWR12: OpKind = MCK_HWRegs; break;
2806    case Mips::HWR13: OpKind = MCK_HWRegs; break;
2807    case Mips::HWR14: OpKind = MCK_HWRegs; break;
2808    case Mips::HWR15: OpKind = MCK_HWRegs; break;
2809    case Mips::HWR16: OpKind = MCK_HWRegs; break;
2810    case Mips::HWR17: OpKind = MCK_HWRegs; break;
2811    case Mips::HWR18: OpKind = MCK_HWRegs; break;
2812    case Mips::HWR19: OpKind = MCK_HWRegs; break;
2813    case Mips::HWR20: OpKind = MCK_HWRegs; break;
2814    case Mips::HWR21: OpKind = MCK_HWRegs; break;
2815    case Mips::HWR22: OpKind = MCK_HWRegs; break;
2816    case Mips::HWR23: OpKind = MCK_HWRegs; break;
2817    case Mips::HWR24: OpKind = MCK_HWRegs; break;
2818    case Mips::HWR25: OpKind = MCK_HWRegs; break;
2819    case Mips::HWR26: OpKind = MCK_HWRegs; break;
2820    case Mips::HWR27: OpKind = MCK_HWRegs; break;
2821    case Mips::HWR28: OpKind = MCK_HWRegs; break;
2822    case Mips::HWR29: OpKind = MCK_HWRegs; break;
2823    case Mips::HWR30: OpKind = MCK_HWRegs; break;
2824    case Mips::HWR31: OpKind = MCK_HWRegs; break;
2825    case Mips::AC0: OpKind = MCK_ACC64; break;
2826    case Mips::AC1: OpKind = MCK_ACC64DSP; break;
2827    case Mips::AC2: OpKind = MCK_ACC64DSP; break;
2828    case Mips::AC3: OpKind = MCK_ACC64DSP; break;
2829    case Mips::AC0_64: OpKind = MCK_ACC128; break;
2830    case Mips::DSPCCond: OpKind = MCK_DSPCC; break;
2831    case Mips::MSAIR: OpKind = MCK_MSACtrl; break;
2832    case Mips::MSACSR: OpKind = MCK_MSACtrl; break;
2833    case Mips::MSAAccess: OpKind = MCK_MSACtrl; break;
2834    case Mips::MSASave: OpKind = MCK_MSACtrl; break;
2835    case Mips::MSAModify: OpKind = MCK_MSACtrl; break;
2836    case Mips::MSARequest: OpKind = MCK_MSACtrl; break;
2837    case Mips::MSAMap: OpKind = MCK_MSACtrl; break;
2838    case Mips::MSAUnmap: OpKind = MCK_MSACtrl; break;
2839    case Mips::MPL0: OpKind = MCK_OCTEON_MPL; break;
2840    case Mips::MPL1: OpKind = MCK_OCTEON_MPL; break;
2841    case Mips::MPL2: OpKind = MCK_OCTEON_MPL; break;
2842    case Mips::P0: OpKind = MCK_OCTEON_P; break;
2843    case Mips::P1: OpKind = MCK_OCTEON_P; break;
2844    case Mips::P2: OpKind = MCK_OCTEON_P; break;
2845    }
2846    return isSubclass(OpKind, Kind) ? MCTargetAsmParser::Match_Success :
2847                                      MCTargetAsmParser::Match_InvalidOperand;
2848  }
2849
2850  return MCTargetAsmParser::Match_InvalidOperand;
2851}
2852
2853uint64_t MipsAsmParser::
2854ComputeAvailableFeatures(const FeatureBitset& FB) const {
2855  uint64_t Features = 0;
2856  if ((FB[Mips::FeatureMips2]))
2857    Features |= Feature_HasMips2;
2858  if ((FB[Mips::FeatureMips3_32]))
2859    Features |= Feature_HasMips3_32;
2860  if ((FB[Mips::FeatureMips3_32r2]))
2861    Features |= Feature_HasMips3_32r2;
2862  if ((FB[Mips::FeatureMips3]))
2863    Features |= Feature_HasMips3;
2864  if ((FB[Mips::FeatureMips4_32]))
2865    Features |= Feature_HasMips4_32;
2866  if ((!FB[Mips::FeatureMips4_32]))
2867    Features |= Feature_NotMips4_32;
2868  if ((FB[Mips::FeatureMips4_32r2]))
2869    Features |= Feature_HasMips4_32r2;
2870  if ((FB[Mips::FeatureMips5_32r2]))
2871    Features |= Feature_HasMips5_32r2;
2872  if ((FB[Mips::FeatureMips32]))
2873    Features |= Feature_HasMips32;
2874  if ((FB[Mips::FeatureMips32r2]))
2875    Features |= Feature_HasMips32r2;
2876  if ((FB[Mips::FeatureMips32r5]))
2877    Features |= Feature_HasMips32r5;
2878  if ((FB[Mips::FeatureMips32r6]))
2879    Features |= Feature_HasMips32r6;
2880  if ((!FB[Mips::FeatureMips32r6]))
2881    Features |= Feature_NotMips32r6;
2882  if ((FB[Mips::FeatureGP64Bit]))
2883    Features |= Feature_IsGP64bit;
2884  if ((!FB[Mips::FeatureGP64Bit]))
2885    Features |= Feature_IsGP32bit;
2886  if ((FB[Mips::FeatureMips64]))
2887    Features |= Feature_HasMips64;
2888  if ((!FB[Mips::FeatureMips64]))
2889    Features |= Feature_NotMips64;
2890  if ((FB[Mips::FeatureMips64r2]))
2891    Features |= Feature_HasMips64r2;
2892  if ((FB[Mips::FeatureMips64r6]))
2893    Features |= Feature_HasMips64r6;
2894  if ((!FB[Mips::FeatureMips64r6]))
2895    Features |= Feature_NotMips64r6;
2896  if ((FB[Mips::FeatureMicroMips]) && (FB[Mips::FeatureMips32r6]))
2897    Features |= Feature_HasMicroMips32r6;
2898  if ((FB[Mips::FeatureMicroMips]) && (FB[Mips::FeatureMips64r6]))
2899    Features |= Feature_HasMicroMips64r6;
2900  if ((FB[Mips::FeatureMips16]))
2901    Features |= Feature_InMips16Mode;
2902  if ((FB[Mips::FeatureCnMips]))
2903    Features |= Feature_HasCnMips;
2904  if ((!FB[Mips::FeatureMips16]))
2905    Features |= Feature_HasStdEnc;
2906  if ((FB[Mips::FeatureMicroMips]))
2907    Features |= Feature_InMicroMips;
2908  if ((!FB[Mips::FeatureMicroMips]))
2909    Features |= Feature_NotInMicroMips;
2910  if ((FB[Mips::FeatureEVA]) && (FB[Mips::FeatureMips32r2]))
2911    Features |= Feature_HasEVA;
2912  if ((FB[Mips::FeatureMSA]))
2913    Features |= Feature_HasMSA;
2914  if ((FB[Mips::FeatureFP64Bit]))
2915    Features |= Feature_IsFP64bit;
2916  if ((!FB[Mips::FeatureFP64Bit]))
2917    Features |= Feature_NotFP64bit;
2918  if ((FB[Mips::FeatureSingleFloat]))
2919    Features |= Feature_IsSingleFloat;
2920  if ((!FB[Mips::FeatureSingleFloat]))
2921    Features |= Feature_IsNotSingleFloat;
2922  if ((!FB[Mips::FeatureSoftFloat]))
2923    Features |= Feature_IsNotSoftFloat;
2924  if ((FB[Mips::FeatureDSP]))
2925    Features |= Feature_HasDSP;
2926  if ((FB[Mips::FeatureDSPR2]))
2927    Features |= Feature_HasDSPR2;
2928  if ((FB[Mips::FeatureDSPR3]))
2929    Features |= Feature_HasDSPR3;
2930  return Features;
2931}
2932
2933static const char *const MnemonicTable =
2934    "\003abs\005abs.d\005abs.s\tabsq_s.ph\tabsq_s.qb\010absq_s.w\003add\005a"
2935    "dd.d\005add.s\007add_a.b\007add_a.d\007add_a.h\007add_a.w\004addi\005ad"
2936    "diu\007addiupc\taddiur1sp\007addiur2\007addius5\007addiusp\007addq.ph\t"
2937    "addq_s.ph\010addq_s.w\010addqh.ph\007addqh.w\naddqh_r.ph\taddqh_r.w\010"
2938    "adds_a.b\010adds_a.d\010adds_a.h\010adds_a.w\010adds_s.b\010adds_s.d\010"
2939    "adds_s.h\010adds_s.w\010adds_u.b\010adds_u.d\010adds_u.h\010adds_u.w\005"
2940    "addsc\004addu\007addu.ph\007addu.qb\006addu16\taddu_s.ph\taddu_s.qb\010"
2941    "adduh.qb\nadduh_r.qb\006addv.b\006addv.d\006addv.h\006addv.w\007addvi.b"
2942    "\007addvi.d\007addvi.h\007addvi.w\005addwc\005align\006aluipc\003and\005"
2943    "and.v\005and16\004andi\006andi.b\006andi16\006append\010asub_s.b\010asu"
2944    "b_s.d\010asub_s.h\010asub_s.w\010asub_u.b\010asub_u.d\010asub_u.h\010as"
2945    "ub_u.w\003aui\005auipc\007ave_s.b\007ave_s.d\007ave_s.h\007ave_s.w\007a"
2946    "ve_u.b\007ave_u.d\007ave_u.h\007ave_u.w\010aver_s.b\010aver_s.d\010aver"
2947    "_s.h\010aver_s.w\010aver_u.b\010aver_u.d\010aver_u.h\010aver_u.w\001b\003"
2948    "b16\005baddu\003bal\004balc\006balign\005bbit0\007bbit032\005bbit1\007b"
2949    "bit132\002bc\004bc16\006bc1eqz\004bc1f\005bc1fl\006bc1nez\004bc1t\005bc"
2950    "1tl\006bc2eqz\006bc2nez\006bclr.b\006bclr.d\006bclr.h\006bclr.w\007bclr"
2951    "i.b\007bclri.d\007bclri.h\007bclri.w\003beq\004beqc\004beql\004beqz\006"
2952    "beqz16\007beqzalc\005beqzc\007beqzc16\005beqzl\003bge\004bgec\004bgel\004"
2953    "bgeu\005bgeuc\005bgeul\004bgez\006bgezal\007bgezalc\007bgezall\007bgeza"
2954    "ls\005bgezc\005bgezl\003bgt\004bgtl\004bgtu\005bgtul\004bgtz\007bgtzalc"
2955    "\005bgtzc\005bgtzl\007binsl.b\007binsl.d\007binsl.h\007binsl.w\010binsl"
2956    "i.b\010binsli.d\010binsli.h\010binsli.w\007binsr.b\007binsr.d\007binsr."
2957    "h\007binsr.w\010binsri.b\010binsri.d\010binsri.h\010binsri.w\006bitrev\007"
2958    "bitswap\003ble\004blel\004bleu\005bleul\004blez\007blezalc\005blezc\005"
2959    "blezl\003blt\004bltc\004bltl\004bltu\005bltuc\005bltul\004bltz\006bltza"
2960    "l\007bltzalc\007bltzall\007bltzals\005bltzc\005bltzl\006bmnz.v\007bmnzi"
2961    ".b\005bmz.v\006bmzi.b\003bne\004bnec\006bneg.b\006bneg.d\006bneg.h\006b"
2962    "neg.w\007bnegi.b\007bnegi.d\007bnegi.h\007bnegi.w\004bnel\004bnez\006bn"
2963    "ez16\007bnezalc\005bnezc\007bnezc16\005bnezl\004bnvc\005bnz.b\005bnz.d\005"
2964    "bnz.h\005bnz.v\005bnz.w\004bovc\010bposge32\005break\007break16\006bsel"
2965    ".v\007bseli.b\006bset.b\006bset.d\006bset.h\006bset.w\007bseti.b\007bse"
2966    "ti.d\007bseti.h\007bseti.w\005bteqz\005btnez\004bz.b\004bz.d\004bz.h\004"
2967    "bz.v\004bz.w\006c.eq.d\006c.eq.s\005c.f.d\005c.f.s\006c.le.d\006c.le.s\006"
2968    "c.lt.d\006c.lt.s\007c.nge.d\007c.nge.s\007c.ngl.d\007c.ngl.s\010c.ngle."
2969    "d\010c.ngle.s\007c.ngt.d\007c.ngt.s\007c.ole.d\007c.ole.s\007c.olt.d\007"
2970    "c.olt.s\007c.seq.d\007c.seq.s\006c.sf.d\006c.sf.s\007c.ueq.d\007c.ueq.s"
2971    "\007c.ule.d\007c.ule.s\007c.ult.d\007c.ult.s\006c.un.d\006c.un.s\005cac"
2972    "he\006cachee\010ceil.l.d\010ceil.l.s\010ceil.w.d\010ceil.w.s\005ceq.b\005"
2973    "ceq.d\005ceq.h\005ceq.w\006ceqi.b\006ceqi.d\006ceqi.h\006ceqi.w\004cfc1"
2974    "\006cfcmsa\004cins\006cins32\007class.d\007class.s\007cle_s.b\007cle_s."
2975    "d\007cle_s.h\007cle_s.w\007cle_u.b\007cle_u.d\007cle_u.h\007cle_u.w\010"
2976    "clei_s.b\010clei_s.d\010clei_s.h\010clei_s.w\010clei_u.b\010clei_u.d\010"
2977    "clei_u.h\010clei_u.w\003clo\007clt_s.b\007clt_s.d\007clt_s.h\007clt_s.w"
2978    "\007clt_u.b\007clt_u.d\007clt_u.h\007clt_u.w\010clti_s.b\010clti_s.d\010"
2979    "clti_s.h\010clti_s.w\010clti_u.b\010clti_u.d\010clti_u.h\010clti_u.w\003"
2980    "clz\003cmp\010cmp.af.d\010cmp.af.s\010cmp.eq.d\tcmp.eq.ph\010cmp.eq.s\010"
2981    "cmp.le.d\tcmp.le.ph\010cmp.le.s\010cmp.lt.d\tcmp.lt.ph\010cmp.lt.s\tcmp"
2982    ".saf.d\tcmp.saf.s\tcmp.seq.d\tcmp.seq.s\tcmp.sle.d\tcmp.sle.s\tcmp.slt."
2983    "d\tcmp.slt.s\ncmp.sueq.d\ncmp.sueq.s\ncmp.sule.d\ncmp.sule.s\ncmp.sult."
2984    "d\ncmp.sult.s\tcmp.sun.d\tcmp.sun.s\tcmp.ueq.d\tcmp.ueq.s\tcmp.ule.d\tc"
2985    "mp.ule.s\tcmp.ult.d\tcmp.ult.s\010cmp.un.d\010cmp.un.s\014cmpgdu.eq.qb\014"
2986    "cmpgdu.le.qb\014cmpgdu.lt.qb\013cmpgu.eq.qb\013cmpgu.le.qb\013cmpgu.lt."
2987    "qb\004cmpi\ncmpu.eq.qb\ncmpu.le.qb\ncmpu.lt.qb\010copy_s.b\010copy_s.d\010"
2988    "copy_s.h\010copy_s.w\010copy_u.b\010copy_u.h\010copy_u.w\004ctc1\006ctc"
2989    "msa\007cvt.d.l\007cvt.d.s\007cvt.d.w\007cvt.l.d\007cvt.l.s\007cvt.s.d\007"
2990    "cvt.s.l\007cvt.s.w\007cvt.w.d\007cvt.w.s\004dadd\005daddi\006daddiu\005"
2991    "daddu\004dahi\006dalign\004dati\004daui\010dbitswap\004dclo\004dclz\004"
2992    "ddiv\005ddivu\005deret\004dext\005dextm\005dextu\002di\004dins\005dinsm"
2993    "\005dinsu\003div\005div.d\005div.s\007div_s.b\007div_s.d\007div_s.h\007"
2994    "div_s.w\007div_u.b\007div_u.d\007div_u.h\007div_u.w\004divu\003dla\003d"
2995    "li\004dlsa\005dmfc0\005dmfc1\005dmfc2\004dmod\005dmodu\005dmtc0\005dmtc"
2996    "1\005dmtc2\004dmuh\005dmuhu\004dmul\005dmult\006dmultu\005dmulu\004dneg"
2997    "\005dnegu\010dotp_s.d\010dotp_s.h\010dotp_s.w\010dotp_u.d\010dotp_u.h\010"
2998    "dotp_u.w\010dpa.w.ph\tdpadd_s.d\tdpadd_s.h\tdpadd_s.w\tdpadd_u.d\tdpadd"
2999    "_u.h\tdpadd_u.w\013dpaq_s.w.ph\013dpaq_sa.l.w\014dpaqx_s.w.ph\015dpaqx_"
3000    "sa.w.ph\ndpau.h.qbl\ndpau.h.qbr\tdpax.w.ph\004dpop\010dps.w.ph\013dpsq_"
3001    "s.w.ph\013dpsq_sa.l.w\014dpsqx_s.w.ph\015dpsqx_sa.w.ph\ndpsu.h.qbl\ndps"
3002    "u.h.qbr\tdpsub_s.d\tdpsub_s.h\tdpsub_s.w\tdpsub_u.d\tdpsub_u.h\tdpsub_u"
3003    ".w\tdpsx.w.ph\004drol\004dror\005drotr\007drotr32\006drotrv\004dsbh\004"
3004    "dshd\004dsll\006dsll32\005dsllv\004dsra\006dsra32\005dsrav\004dsrl\006d"
3005    "srl32\005dsrlv\004dsub\005dsubi\005dsubu\003ehb\002ei\004eret\006eretnc"
3006    "\003ext\004extp\006extpdp\007extpdpv\005extpv\006extr.w\010extr_r.w\tex"
3007    "tr_rs.w\010extr_s.h\007extrv.w\textrv_r.w\nextrv_rs.w\textrv_s.h\004ext"
3008    "s\006exts32\006fadd.d\006fadd.w\006fcaf.d\006fcaf.w\006fceq.d\006fceq.w"
3009    "\010fclass.d\010fclass.w\006fcle.d\006fcle.w\006fclt.d\006fclt.w\006fcn"
3010    "e.d\006fcne.w\006fcor.d\006fcor.w\007fcueq.d\007fcueq.w\007fcule.d\007f"
3011    "cule.w\007fcult.d\007fcult.w\006fcun.d\006fcun.w\007fcune.d\007fcune.w\006"
3012    "fdiv.d\006fdiv.w\007fexdo.h\007fexdo.w\007fexp2.d\007fexp2.w\010fexupl."
3013    "d\010fexupl.w\010fexupr.d\010fexupr.w\tffint_s.d\tffint_s.w\tffint_u.d\t"
3014    "ffint_u.w\006ffql.d\006ffql.w\006ffqr.d\006ffqr.w\006fill.b\006fill.d\006"
3015    "fill.h\006fill.w\007flog2.d\007flog2.w\tfloor.l.d\tfloor.l.s\tfloor.w.d"
3016    "\tfloor.w.s\007fmadd.d\007fmadd.w\006fmax.d\006fmax.w\010fmax_a.d\010fm"
3017    "ax_a.w\006fmin.d\006fmin.w\010fmin_a.d\010fmin_a.w\007fmsub.d\007fmsub."
3018    "w\006fmul.d\006fmul.w\006frcp.d\006frcp.w\007frint.d\007frint.w\010frsq"
3019    "rt.d\010frsqrt.w\006fsaf.d\006fsaf.w\006fseq.d\006fseq.w\006fsle.d\006f"
3020    "sle.w\006fslt.d\006fslt.w\006fsne.d\006fsne.w\006fsor.d\006fsor.w\007fs"
3021    "qrt.d\007fsqrt.w\006fsub.d\006fsub.w\007fsueq.d\007fsueq.w\007fsule.d\007"
3022    "fsule.w\007fsult.d\007fsult.w\006fsun.d\006fsun.w\007fsune.d\007fsune.w"
3023    "\tftint_s.d\tftint_s.w\tftint_u.d\tftint_u.w\005ftq.h\005ftq.w\nftrunc_"
3024    "s.d\nftrunc_s.w\nftrunc_u.d\nftrunc_u.w\010hadd_s.d\010hadd_s.h\010hadd"
3025    "_s.w\010hadd_u.d\010hadd_u.h\010hadd_u.w\010hsub_s.d\010hsub_s.h\010hsu"
3026    "b_s.w\010hsub_u.d\010hsub_u.h\010hsub_u.w\007ilvev.b\007ilvev.d\007ilve"
3027    "v.h\007ilvev.w\006ilvl.b\006ilvl.d\006ilvl.h\006ilvl.w\007ilvod.b\007il"
3028    "vod.d\007ilvod.h\007ilvod.w\006ilvr.b\006ilvr.d\006ilvr.h\006ilvr.w\003"
3029    "ins\010insert.b\010insert.d\010insert.h\010insert.w\004insv\007insve.b\007"
3030    "insve.d\007insve.h\007insve.w\001j\003jal\004jalr\007jalr.hb\005jalrc\005"
3031    "jalrs\007jalrs16\004jals\004jalx\005jialc\003jic\002jr\005jr.hb\004jr16"
3032    "\tjraddiusp\003jrc\005jrc16\njrcaddiusp\002la\002lb\003lbe\003lbu\005lb"
3033    "u16\004lbue\004lbux\002ld\004ld.b\004ld.d\004ld.h\004ld.w\004ldc1\004ld"
3034    "c2\004ldc3\005ldi.b\005ldi.d\005ldi.h\005ldi.w\003ldl\004ldpc\003ldr\005"
3035    "ldxc1\002lh\003lhe\003lhu\005lhu16\004lhue\003lhx\002li\004li16\002ll\003"
3036    "lld\003lle\003lsa\003lui\005luxc1\002lw\004lw16\004lwc1\004lwc2\004lwc3"
3037    "\003lwe\003lwl\004lwle\003lwm\005lwm16\005lwm32\003lwp\004lwpc\003lwr\004"
3038    "lwre\003lwu\005lwupc\003lwx\005lwxc1\004lwxs\004madd\006madd.d\006madd."
3039    "s\010madd_q.h\010madd_q.w\007maddf.d\007maddf.s\tmaddr_q.h\tmaddr_q.w\005"
3040    "maddu\007maddv.b\007maddv.d\007maddv.h\007maddv.w\013maq_s.w.phl\013maq"
3041    "_s.w.phr\014maq_sa.w.phl\014maq_sa.w.phr\005max.d\005max.s\007max_a.b\007"
3042    "max_a.d\007max_a.h\007max_a.w\007max_s.b\007max_s.d\007max_s.h\007max_s"
3043    ".w\007max_u.b\007max_u.d\007max_u.h\007max_u.w\006maxa.d\006maxa.s\010m"
3044    "axi_s.b\010maxi_s.d\010maxi_s.h\010maxi_s.w\010maxi_u.b\010maxi_u.d\010"
3045    "maxi_u.h\010maxi_u.w\004mfc0\004mfc1\004mfc2\005mfhc1\004mfhi\004mflo\005"
3046    "min.d\005min.s\007min_a.b\007min_a.d\007min_a.h\007min_a.w\007min_s.b\007"
3047    "min_s.d\007min_s.h\007min_s.w\007min_u.b\007min_u.d\007min_u.h\007min_u"
3048    ".w\006mina.d\006mina.s\010mini_s.b\010mini_s.d\010mini_s.h\010mini_s.w\010"
3049    "mini_u.b\010mini_u.d\010mini_u.h\010mini_u.w\003mod\007mod_s.b\007mod_s"
3050    ".d\007mod_s.h\007mod_s.w\007mod_u.b\007mod_u.d\007mod_u.h\007mod_u.w\006"
3051    "modsub\004modu\005mov.d\005mov.s\004move\006move.v\006move16\005movep\004"
3052    "movf\006movf.d\006movf.s\004movn\006movn.d\006movn.s\004movt\006movt.d\006"
3053    "movt.s\004movz\006movz.d\006movz.s\004msub\006msub.d\006msub.s\010msub_"
3054    "q.h\010msub_q.w\007msubf.d\007msubf.s\tmsubr_q.h\tmsubr_q.w\005msubu\007"
3055    "msubv.b\007msubv.d\007msubv.h\007msubv.w\004mtc0\004mtc1\004mtc2\005mth"
3056    "c1\004mthi\006mthlip\004mtlo\004mtm0\004mtm1\004mtm2\004mtp0\004mtp1\004"
3057    "mtp2\003muh\004muhu\003mul\005mul.d\006mul.ph\005mul.s\007mul_q.h\007mu"
3058    "l_q.w\010mul_s.ph\015muleq_s.w.phl\015muleq_s.w.phr\016muleu_s.ph.qbl\016"
3059    "muleu_s.ph.qbr\nmulq_rs.ph\tmulq_rs.w\tmulq_s.ph\010mulq_s.w\010mulr_q."
3060    "h\010mulr_q.w\nmulsa.w.ph\015mulsaq_s.w.ph\004mult\005multu\004mulu\006"
3061    "mulv.b\006mulv.d\006mulv.h\006mulv.w\003neg\005neg.d\005neg.s\004negu\006"
3062    "nloc.b\006nloc.d\006nloc.h\006nloc.w\006nlzc.b\006nlzc.d\006nlzc.h\006n"
3063    "lzc.w\007nmadd.d\007nmadd.s\007nmsub.d\007nmsub.s\003nop\003nor\005nor."
3064    "v\006nori.b\003not\005not16\002or\004or.v\004or16\003ori\005ori.b\tpack"
3065    "rl.ph\005pause\007pckev.b\007pckev.d\007pckev.h\007pckev.w\007pckod.b\007"
3066    "pckod.d\007pckod.h\007pckod.w\006pcnt.b\006pcnt.d\006pcnt.h\006pcnt.w\007"
3067    "pick.ph\007pick.qb\003pop\014preceq.w.phl\014preceq.w.phr\016precequ.ph"
3068    ".qbl\017precequ.ph.qbla\016precequ.ph.qbr\017precequ.ph.qbra\015preceu."
3069    "ph.qbl\016preceu.ph.qbla\015preceu.ph.qbr\016preceu.ph.qbra\013precr.qb"
3070    ".ph\016precr_sra.ph.w\020precr_sra_r.ph.w\013precrq.ph.w\014precrq.qb.p"
3071    "h\016precrq_rs.ph.w\017precrqu_s.qb.ph\004pref\005prefe\005prefx\007pre"
3072    "pend\nraddu.w.qb\005rddsp\005rdhwr\006rdpgpr\007recip.d\007recip.s\007r"
3073    "epl.ph\007repl.qb\010replv.ph\010replv.qb\006rint.d\006rint.s\003rol\003"
3074    "ror\004rotr\005rotrv\tround.l.d\tround.l.s\tround.w.d\tround.w.s\007rsq"
3075    "rt.d\007rsqrt.s\007sat_s.b\007sat_s.d\007sat_s.h\007sat_s.w\007sat_u.b\007"
3076    "sat_u.d\007sat_u.h\007sat_u.w\002sb\004sb16\003sbe\002sc\003scd\003sce\002"
3077    "sd\005sdbbp\007sdbbp16\004sdc1\004sdc2\004sdc3\003sdl\003sdr\005sdxc1\003"
3078    "seb\003seh\005sel.d\005sel.s\006seleqz\010seleqz.d\010seleqz.s\006selne"
3079    "z\010selnez.d\010selnez.s\003seq\004seqi\002sh\004sh16\003she\005shf.b\005"
3080    "shf.h\005shf.w\005shilo\006shilov\007shll.ph\007shll.qb\tshll_s.ph\010s"
3081    "hll_s.w\010shllv.ph\010shllv.qb\nshllv_s.ph\tshllv_s.w\007shra.ph\007sh"
3082    "ra.qb\tshra_r.ph\tshra_r.qb\010shra_r.w\010shrav.ph\010shrav.qb\nshrav_"
3083    "r.ph\nshrav_r.qb\tshrav_r.w\007shrl.ph\007shrl.qb\010shrlv.ph\010shrlv."
3084    "qb\005sld.b\005sld.d\005sld.h\005sld.w\006sldi.b\006sldi.d\006sldi.h\006"
3085    "sldi.w\003sll\005sll.b\005sll.d\005sll.h\005sll.w\005sll16\006slli.b\006"
3086    "slli.d\006slli.h\006slli.w\004sllv\003slt\004slti\005sltiu\004sltu\003s"
3087    "ne\004snei\007splat.b\007splat.d\007splat.h\007splat.w\010splati.b\010s"
3088    "plati.d\010splati.h\010splati.w\006sqrt.d\006sqrt.s\003sra\005sra.b\005"
3089    "sra.d\005sra.h\005sra.w\006srai.b\006srai.d\006srai.h\006srai.w\006srar"
3090    ".b\006srar.d\006srar.h\006srar.w\007srari.b\007srari.d\007srari.h\007sr"
3091    "ari.w\004srav\003srl\005srl.b\005srl.d\005srl.h\005srl.w\005srl16\006sr"
3092    "li.b\006srli.d\006srli.h\006srli.w\006srlr.b\006srlr.d\006srlr.h\006srl"
3093    "r.w\007srlri.b\007srlri.d\007srlri.h\007srlri.w\004srlv\005ssnop\004st."
3094    "b\004st.d\004st.h\004st.w\003sub\005sub.d\005sub.s\007subq.ph\tsubq_s.p"
3095    "h\010subq_s.w\010subqh.ph\007subqh.w\nsubqh_r.ph\tsubqh_r.w\010subs_s.b"
3096    "\010subs_s.d\010subs_s.h\010subs_s.w\010subs_u.b\010subs_u.d\010subs_u."
3097    "h\010subs_u.w\nsubsus_u.b\nsubsus_u.d\nsubsus_u.h\nsubsus_u.w\nsubsuu_s"
3098    ".b\nsubsuu_s.d\nsubsuu_s.h\nsubsuu_s.w\004subu\007subu.ph\007subu.qb\006"
3099    "subu16\tsubu_s.ph\tsubu_s.qb\010subuh.qb\nsubuh_r.qb\006subv.b\006subv."
3100    "d\006subv.h\006subv.w\007subvi.b\007subvi.d\007subvi.h\007subvi.w\005su"
3101    "xc1\002sw\004sw16\004swc1\004swc2\004swc3\003swe\003swl\004swle\003swm\005"
3102    "swm16\005swm32\003swp\003swr\004swre\005swxc1\004sync\005synci\nsynciob"
3103    "dma\005syncs\005syncw\006syncws\007syscall\003teq\004teqi\003tge\004tge"
3104    "i\005tgeiu\004tgeu\006tlbinv\007tlbinvf\004tlbp\004tlbr\005tlbwi\005tlb"
3105    "wr\003tlt\004tlti\005tltiu\004tltu\003tne\004tnei\ttrunc.l.d\ttrunc.l.s"
3106    "\ttrunc.w.d\ttrunc.w.s\003ulh\004ulhu\003ulw\006v3mulu\004vmm0\005vmulu"
3107    "\006vshf.b\006vshf.d\006vshf.h\006vshf.w\004wait\005wrdsp\006wrpgpr\004"
3108    "wsbh\003xor\005xor.v\005xor16\004xori\006xori.b";
3109
3110namespace {
3111  struct MatchEntry {
3112    uint16_t Mnemonic;
3113    uint16_t Opcode;
3114    uint16_t ConvertFn;
3115    uint64_t RequiredFeatures;
3116    uint8_t Classes[8];
3117    StringRef getMnemonic() const {
3118      return StringRef(MnemonicTable + Mnemonic + 1,
3119                       MnemonicTable[Mnemonic]);
3120    }
3121  };
3122
3123  // Predicate for searching for an opcode.
3124  struct LessOpcode {
3125    bool operator()(const MatchEntry &LHS, StringRef RHS) {
3126      return LHS.getMnemonic() < RHS;
3127    }
3128    bool operator()(StringRef LHS, const MatchEntry &RHS) {
3129      return LHS < RHS.getMnemonic();
3130    }
3131    bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {
3132      return LHS.getMnemonic() < RHS.getMnemonic();
3133    }
3134  };
3135} // end anonymous namespace.
3136
3137static const MatchEntry MatchTable0[] = {
3138  { 0 /* abs */, Mips::ABSMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3139  { 4 /* abs.d */, Mips::ABS_D_MMR6, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
3140  { 4 /* abs.d */, Mips::FABS_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
3141  { 4 /* abs.d */, Mips::FABS_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3142  { 10 /* abs.s */, Mips::ABS_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3143  { 10 /* abs.s */, Mips::FABS_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3144  { 16 /* absq_s.ph */, Mips::ABSQ_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3145  { 16 /* absq_s.ph */, Mips::ABSQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3146  { 26 /* absq_s.qb */, Mips::ABSQ_S_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3147  { 26 /* absq_s.qb */, Mips::ABSQ_S_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3148  { 36 /* absq_s.w */, Mips::ABSQ_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3149  { 36 /* absq_s.w */, Mips::ABSQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3150  { 45 /* add */, Mips::ADD_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3151  { 45 /* add */, Mips::ADD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3152  { 45 /* add */, Mips::ADD_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3153  { 45 /* add */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__Imm1_1, Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm }, },
3154  { 45 /* add */, Mips::ADD_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3155  { 45 /* add */, Mips::ADD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3156  { 45 /* add */, Mips::ADD_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3157  { 45 /* add */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__Imm1_2, Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_Imm }, },
3158  { 49 /* add.d */, Mips::FADD_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
3159  { 49 /* add.d */, Mips::FADD_D_MMR6, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_2__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
3160  { 49 /* add.d */, Mips::FADD_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3161  { 55 /* add.s */, Mips::FADD_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3162  { 55 /* add.s */, Mips::FADD_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3163  { 61 /* add_a.b */, Mips::ADD_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3164  { 69 /* add_a.d */, Mips::ADD_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3165  { 77 /* add_a.h */, Mips::ADD_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3166  { 85 /* add_a.w */, Mips::ADD_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3167  { 93 /* addi */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__Imm1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm }, },
3168  { 93 /* addi */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__Imm1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Imm }, },
3169  { 93 /* addi */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_Imm }, },
3170  { 93 /* addi */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__Imm1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_Imm }, },
3171  { 98 /* addiu */, Mips::AddiuSpImmX16, Convert__Imm1_1, Feature_InMips16Mode, { MCK_CPUSPReg, MCK_Imm }, },
3172  { 98 /* addiu */, Mips::AddiuRxImmX16, Convert__Reg1_0__Imm1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_Imm }, },
3173  { 98 /* addiu */, Mips::ADDIU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__Imm1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_Imm }, },
3174  { 98 /* addiu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__Imm1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Imm }, },
3175  { 98 /* addiu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__Imm1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Imm }, },
3176  { 98 /* addiu */, Mips::AddiuRxPcImmX16, Convert__Reg1_0__Imm1_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_PC, MCK_Imm }, },
3177  { 98 /* addiu */, Mips::AddiuRxRyOffMemX16, Convert__Reg1_0__Reg1_1__Imm1_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16RegsPlusSP, MCK_Imm }, },
3178  { 98 /* addiu */, Mips::ADDIU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_Imm }, },
3179  { 98 /* addiu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_Imm }, },
3180  { 98 /* addiu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__Imm1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_Imm }, },
3181  { 98 /* addiu */, Mips::AddiuSpImm16, Convert__Imm1_1, Feature_InMips16Mode, { MCK_CPUSPReg, MCK_Imm, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
3182  { 98 /* addiu */, Mips::AddiuRxRxImm16, Convert__Reg1_0__Tie0__Imm1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_Imm, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
3183  { 104 /* addiupc */, Mips::ADDIUPC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3184  { 104 /* addiupc */, Mips::ADDIUPC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3185  { 104 /* addiupc */, Mips::ADDIUPC_MM, Convert__GPRMM16AsmReg1_0__Imm1_1, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_Imm }, },
3186  { 112 /* addiur1sp */, Mips::ADDIUR1SP_MM, Convert__GPRMM16AsmReg1_0__Imm1_1, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_Imm }, },
3187  { 122 /* addiur2 */, Mips::ADDIUR2_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
3188  { 130 /* addius5 */, Mips::ADDIUS5_MM, Convert__GPR32AsmReg1_0__Tie0__Imm1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Imm }, },
3189  { 138 /* addiusp */, Mips::ADDIUSP_MM, Convert__Imm1_0, Feature_InMicroMips, { MCK_Imm }, },
3190  { 146 /* addq.ph */, Mips::ADDQ_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3191  { 146 /* addq.ph */, Mips::ADDQ_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3192  { 154 /* addq_s.ph */, Mips::ADDQ_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3193  { 154 /* addq_s.ph */, Mips::ADDQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3194  { 164 /* addq_s.w */, Mips::ADDQ_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3195  { 164 /* addq_s.w */, Mips::ADDQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3196  { 173 /* addqh.ph */, Mips::ADDQH_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3197  { 173 /* addqh.ph */, Mips::ADDQH_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3198  { 182 /* addqh.w */, Mips::ADDQH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3199  { 182 /* addqh.w */, Mips::ADDQH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3200  { 190 /* addqh_r.ph */, Mips::ADDQH_R_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3201  { 190 /* addqh_r.ph */, Mips::ADDQH_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3202  { 201 /* addqh_r.w */, Mips::ADDQH_R_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3203  { 201 /* addqh_r.w */, Mips::ADDQH_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3204  { 211 /* adds_a.b */, Mips::ADDS_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3205  { 220 /* adds_a.d */, Mips::ADDS_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3206  { 229 /* adds_a.h */, Mips::ADDS_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3207  { 238 /* adds_a.w */, Mips::ADDS_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3208  { 247 /* adds_s.b */, Mips::ADDS_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3209  { 256 /* adds_s.d */, Mips::ADDS_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3210  { 265 /* adds_s.h */, Mips::ADDS_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3211  { 274 /* adds_s.w */, Mips::ADDS_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3212  { 283 /* adds_u.b */, Mips::ADDS_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3213  { 292 /* adds_u.d */, Mips::ADDS_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3214  { 301 /* adds_u.h */, Mips::ADDS_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3215  { 310 /* adds_u.w */, Mips::ADDS_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3216  { 319 /* addsc */, Mips::ADDSC_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3217  { 319 /* addsc */, Mips::ADDSC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3218  { 325 /* addu */, Mips::ADDU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3219  { 325 /* addu */, Mips::ADDu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3220  { 325 /* addu */, Mips::ADDu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3221  { 325 /* addu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__Imm1_1, 0, { MCK_GPR32AsmReg, MCK_Imm }, },
3222  { 325 /* addu */, Mips::AdduRxRyRz16, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_CPU16Regs }, },
3223  { 325 /* addu */, Mips::ADDU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3224  { 325 /* addu */, Mips::ADDu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3225  { 325 /* addu */, Mips::ADDu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3226  { 325 /* addu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__Imm1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_Imm }, },
3227  { 330 /* addu.ph */, Mips::ADDU_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3228  { 330 /* addu.ph */, Mips::ADDU_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3229  { 338 /* addu.qb */, Mips::ADDU_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3230  { 338 /* addu.qb */, Mips::ADDU_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3231  { 346 /* addu16 */, Mips::ADDU16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
3232  { 346 /* addu16 */, Mips::ADDU16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, Feature_HasMicroMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
3233  { 353 /* addu_s.ph */, Mips::ADDU_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3234  { 353 /* addu_s.ph */, Mips::ADDU_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3235  { 363 /* addu_s.qb */, Mips::ADDU_S_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3236  { 363 /* addu_s.qb */, Mips::ADDU_S_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3237  { 373 /* adduh.qb */, Mips::ADDUH_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3238  { 373 /* adduh.qb */, Mips::ADDUH_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3239  { 382 /* adduh_r.qb */, Mips::ADDUH_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3240  { 382 /* adduh_r.qb */, Mips::ADDUH_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3241  { 393 /* addv.b */, Mips::ADDV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3242  { 400 /* addv.d */, Mips::ADDV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3243  { 407 /* addv.h */, Mips::ADDV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3244  { 414 /* addv.w */, Mips::ADDV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3245  { 421 /* addvi.b */, Mips::ADDVI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3246  { 429 /* addvi.d */, Mips::ADDVI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3247  { 437 /* addvi.h */, Mips::ADDVI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3248  { 445 /* addvi.w */, Mips::ADDVI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3249  { 453 /* addwc */, Mips::ADDWC_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3250  { 453 /* addwc */, Mips::ADDWC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3251  { 459 /* align */, Mips::ALIGN, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
3252  { 459 /* align */, Mips::ALIGN_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
3253  { 465 /* aluipc */, Mips::ALUIPC, Convert__GPR32AsmReg1_0__Imm1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Imm }, },
3254  { 465 /* aluipc */, Mips::ALUIPC_MMR6, Convert__GPR32AsmReg1_0__Imm1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_Imm }, },
3255  { 472 /* and */, Mips::AndRxRxRy16, Convert__Reg1_0__Tie0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
3256  { 472 /* and */, Mips::AND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3257  { 472 /* and */, Mips::AND_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3258  { 472 /* and */, Mips::AND_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3259  { 472 /* and */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__Imm1_1, 0, { MCK_GPR32AsmReg, MCK_Imm }, },
3260  { 472 /* and */, Mips::AND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3261  { 472 /* and */, Mips::AND_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3262  { 472 /* and */, Mips::AND_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3263  { 472 /* and */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__Imm1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_Imm }, },
3264  { 476 /* and.v */, Mips::AND_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3265  { 482 /* and16 */, Mips::AND16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0, Feature_InMicroMips|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
3266  { 482 /* and16 */, Mips::AND16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0, Feature_HasMicroMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
3267  { 488 /* andi */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
3268  { 488 /* andi */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16 }, },
3269  { 488 /* andi */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_UImm16 }, },
3270  { 488 /* andi */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
3271  { 488 /* andi */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
3272  { 488 /* andi */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
3273  { 493 /* andi.b */, Mips::ANDI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3274  { 500 /* andi16 */, Mips::ANDI16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
3275  { 500 /* andi16 */, Mips::ANDI16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_HasMicroMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
3276  { 507 /* append */, Mips::APPEND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
3277  { 514 /* asub_s.b */, Mips::ASUB_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3278  { 523 /* asub_s.d */, Mips::ASUB_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3279  { 532 /* asub_s.h */, Mips::ASUB_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3280  { 541 /* asub_s.w */, Mips::ASUB_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3281  { 550 /* asub_u.b */, Mips::ASUB_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3282  { 559 /* asub_u.d */, Mips::ASUB_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3283  { 568 /* asub_u.h */, Mips::ASUB_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3284  { 577 /* asub_u.w */, Mips::ASUB_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3285  { 586 /* aui */, Mips::AUI, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_Imm }, },
3286  { 586 /* aui */, Mips::AUI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_Imm }, },
3287  { 590 /* auipc */, Mips::AUIPC, Convert__GPR32AsmReg1_0__Imm1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Imm }, },
3288  { 590 /* auipc */, Mips::AUIPC_MMR6, Convert__GPR32AsmReg1_0__Imm1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_Imm }, },
3289  { 596 /* ave_s.b */, Mips::AVE_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3290  { 604 /* ave_s.d */, Mips::AVE_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3291  { 612 /* ave_s.h */, Mips::AVE_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3292  { 620 /* ave_s.w */, Mips::AVE_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3293  { 628 /* ave_u.b */, Mips::AVE_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3294  { 636 /* ave_u.d */, Mips::AVE_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3295  { 644 /* ave_u.h */, Mips::AVE_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3296  { 652 /* ave_u.w */, Mips::AVE_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3297  { 660 /* aver_s.b */, Mips::AVER_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3298  { 669 /* aver_s.d */, Mips::AVER_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3299  { 678 /* aver_s.h */, Mips::AVER_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3300  { 687 /* aver_s.w */, Mips::AVER_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3301  { 696 /* aver_u.b */, Mips::AVER_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3302  { 705 /* aver_u.d */, Mips::AVER_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3303  { 714 /* aver_u.h */, Mips::AVER_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3304  { 723 /* aver_u.w */, Mips::AVER_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3305  { 732 /* b */, Mips::B_MM_Pseudo, Convert__JumpTarget1_0, Feature_InMicroMips, { MCK_JumpTarget }, },
3306  { 732 /* b */, Mips::BimmX16, Convert__JumpTarget1_0, Feature_InMips16Mode, { MCK_JumpTarget }, },
3307  { 732 /* b */, Mips::BEQ, Convert__regZERO__regZERO__JumpTarget1_0, Feature_NotInMicroMips, { MCK_JumpTarget }, },
3308  { 732 /* b */, Mips::B_MMR6_Pseudo, Convert__JumpTarget1_0, 0, { MCK_JumpTarget }, },
3309  { 732 /* b */, Mips::Bimm16, Convert__JumpTarget1_0, Feature_InMips16Mode, { MCK_JumpTarget, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
3310  { 734 /* b16 */, Mips::B16_MM, Convert__JumpTarget1_0, Feature_InMicroMips, { MCK_JumpTarget }, },
3311  { 738 /* baddu */, Mips::BADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
3312  { 738 /* baddu */, Mips::BADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
3313  { 744 /* bal */, Mips::BAL, Convert__JumpTarget1_0, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_JumpTarget }, },
3314  { 744 /* bal */, Mips::BGEZAL, Convert__regZERO__JumpTarget1_0, Feature_NotMips32r6|Feature_NotMips64r6, { MCK_JumpTarget }, },
3315  { 748 /* balc */, Mips::BALC, Convert__JumpTarget1_0, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_JumpTarget }, },
3316  { 748 /* balc */, Mips::BALC_MMR6, Convert__JumpTarget1_0, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_JumpTarget }, },
3317  { 753 /* balign */, Mips::BALIGN, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
3318  { 760 /* bbit0 */, Mips::BBIT032, Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_JumpTarget }, },
3319  { 760 /* bbit0 */, Mips::BBIT0, Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0_Report_UImm6, MCK_JumpTarget }, },
3320  { 766 /* bbit032 */, Mips::BBIT032, Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_JumpTarget }, },
3321  { 774 /* bbit1 */, Mips::BBIT132, Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_JumpTarget }, },
3322  { 774 /* bbit1 */, Mips::BBIT1, Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0_Report_UImm6, MCK_JumpTarget }, },
3323  { 780 /* bbit132 */, Mips::BBIT132, Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_JumpTarget }, },
3324  { 788 /* bc */, Mips::BC, Convert__JumpTarget1_0, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_JumpTarget }, },
3325  { 788 /* bc */, Mips::BC_MMR6, Convert__JumpTarget1_0, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_JumpTarget }, },
3326  { 791 /* bc16 */, Mips::BC16_MMR6, Convert__JumpTarget1_0, Feature_HasMicroMips32r6, { MCK_JumpTarget }, },
3327  { 796 /* bc1eqz */, Mips::BC1EQZ, Convert__FGR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_JumpTarget }, },
3328  { 803 /* bc1f */, Mips::BC1F, Convert__regFCC0__JumpTarget1_0, Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_JumpTarget }, },
3329  { 803 /* bc1f */, Mips::BC1F, Convert__FCCAsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_JumpTarget }, },
3330  { 808 /* bc1fl */, Mips::BC1FL, Convert__regFCC0__JumpTarget1_0, Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_JumpTarget }, },
3331  { 808 /* bc1fl */, Mips::BC1FL, Convert__FCCAsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_JumpTarget }, },
3332  { 814 /* bc1nez */, Mips::BC1NEZ, Convert__FGR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_JumpTarget }, },
3333  { 821 /* bc1t */, Mips::BC1T, Convert__regFCC0__JumpTarget1_0, Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_JumpTarget }, },
3334  { 821 /* bc1t */, Mips::BC1T, Convert__FCCAsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_JumpTarget }, },
3335  { 826 /* bc1tl */, Mips::BC1TL, Convert__regFCC0__JumpTarget1_0, Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_JumpTarget }, },
3336  { 826 /* bc1tl */, Mips::BC1TL, Convert__FCCAsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_JumpTarget }, },
3337  { 832 /* bc2eqz */, Mips::BC2EQZ, Convert__COP2AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_COP2AsmReg, MCK_JumpTarget }, },
3338  { 839 /* bc2nez */, Mips::BC2NEZ, Convert__COP2AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_COP2AsmReg, MCK_JumpTarget }, },
3339  { 846 /* bclr.b */, Mips::BCLR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3340  { 853 /* bclr.d */, Mips::BCLR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3341  { 860 /* bclr.h */, Mips::BCLR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3342  { 867 /* bclr.w */, Mips::BCLR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3343  { 874 /* bclri.b */, Mips::BCLRI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3344  { 882 /* bclri.d */, Mips::BCLRI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3345  { 890 /* bclri.h */, Mips::BCLRI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3346  { 898 /* bclri.w */, Mips::BCLRI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3347  { 906 /* beq */, Mips::BEQ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
3348  { 906 /* beq */, Mips::BEQ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
3349  { 906 /* beq */, Mips::BeqImm, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
3350  { 910 /* beqc */, Mips::BEQC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
3351  { 915 /* beql */, Mips::BEQL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
3352  { 920 /* beqz */, Mips::BeqzRxImmX16, Convert__Reg1_0__JumpTarget1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget }, },
3353  { 920 /* beqz */, Mips::BEQ, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, 0, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3354  { 920 /* beqz */, Mips::BeqzRxImm16, Convert__Reg1_0__JumpTarget1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
3355  { 925 /* beqz16 */, Mips::BEQZ16_MM, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
3356  { 932 /* beqzalc */, Mips::BEQZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3357  { 932 /* beqzalc */, Mips::BEQZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3358  { 940 /* beqzc */, Mips::BEQZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3359  { 940 /* beqzc */, Mips::BEQZC_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3360  { 946 /* beqzc16 */, Mips::BEQZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, Feature_HasMicroMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
3361  { 954 /* beqzl */, Mips::BEQL, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, 0, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3362  { 960 /* bge */, Mips::BGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
3363  { 960 /* bge */, Mips::BGEImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
3364  { 964 /* bgec */, Mips::BGEC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
3365  { 969 /* bgel */, Mips::BGEL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
3366  { 969 /* bgel */, Mips::BGELImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
3367  { 974 /* bgeu */, Mips::BGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
3368  { 974 /* bgeu */, Mips::BGEUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
3369  { 979 /* bgeuc */, Mips::BGEUC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
3370  { 985 /* bgeul */, Mips::BGEUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
3371  { 985 /* bgeul */, Mips::BGEULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
3372  { 991 /* bgez */, Mips::BGEZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3373  { 991 /* bgez */, Mips::BGEZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3374  { 996 /* bgezal */, Mips::BGEZAL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3375  { 996 /* bgezal */, Mips::BGEZAL_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3376  { 1003 /* bgezalc */, Mips::BGEZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3377  { 1003 /* bgezalc */, Mips::BGEZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3378  { 1011 /* bgezall */, Mips::BGEZALL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3379  { 1019 /* bgezals */, Mips::BGEZALS_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3380  { 1027 /* bgezc */, Mips::BGEZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3381  { 1033 /* bgezl */, Mips::BGEZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3382  { 1039 /* bgt */, Mips::BGT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
3383  { 1039 /* bgt */, Mips::BGTImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
3384  { 1043 /* bgtl */, Mips::BGTL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
3385  { 1043 /* bgtl */, Mips::BGTLImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
3386  { 1048 /* bgtu */, Mips::BGTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
3387  { 1048 /* bgtu */, Mips::BGTUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
3388  { 1053 /* bgtul */, Mips::BGTUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
3389  { 1053 /* bgtul */, Mips::BGTULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
3390  { 1059 /* bgtz */, Mips::BGTZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3391  { 1059 /* bgtz */, Mips::BGTZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3392  { 1064 /* bgtzalc */, Mips::BGTZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3393  { 1064 /* bgtzalc */, Mips::BGTZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3394  { 1072 /* bgtzc */, Mips::BGTZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3395  { 1078 /* bgtzl */, Mips::BGTZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3396  { 1084 /* binsl.b */, Mips::BINSL_B, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3397  { 1092 /* binsl.d */, Mips::BINSL_D, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3398  { 1100 /* binsl.h */, Mips::BINSL_H, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3399  { 1108 /* binsl.w */, Mips::BINSL_W, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3400  { 1116 /* binsli.b */, Mips::BINSLI_B, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3401  { 1125 /* binsli.d */, Mips::BINSLI_D, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3402  { 1134 /* binsli.h */, Mips::BINSLI_H, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3403  { 1143 /* binsli.w */, Mips::BINSLI_W, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3404  { 1152 /* binsr.b */, Mips::BINSR_B, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3405  { 1160 /* binsr.d */, Mips::BINSR_D, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3406  { 1168 /* binsr.h */, Mips::BINSR_H, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3407  { 1176 /* binsr.w */, Mips::BINSR_W, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3408  { 1184 /* binsri.b */, Mips::BINSRI_B, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3409  { 1193 /* binsri.d */, Mips::BINSRI_D, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3410  { 1202 /* binsri.h */, Mips::BINSRI_H, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3411  { 1211 /* binsri.w */, Mips::BINSRI_W, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3412  { 1220 /* bitrev */, Mips::BITREV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3413  { 1227 /* bitswap */, Mips::BITSWAP, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3414  { 1227 /* bitswap */, Mips::BITSWAP_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3415  { 1235 /* ble */, Mips::BLE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
3416  { 1235 /* ble */, Mips::BLEImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
3417  { 1239 /* blel */, Mips::BLEL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
3418  { 1239 /* blel */, Mips::BLELImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
3419  { 1244 /* bleu */, Mips::BLEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
3420  { 1244 /* bleu */, Mips::BLEUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
3421  { 1249 /* bleul */, Mips::BLEUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
3422  { 1249 /* bleul */, Mips::BLEULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
3423  { 1255 /* blez */, Mips::BLEZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3424  { 1255 /* blez */, Mips::BLEZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3425  { 1260 /* blezalc */, Mips::BLEZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3426  { 1260 /* blezalc */, Mips::BLEZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3427  { 1268 /* blezc */, Mips::BLEZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3428  { 1274 /* blezl */, Mips::BLEZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3429  { 1280 /* blt */, Mips::BLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
3430  { 1280 /* blt */, Mips::BLTImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
3431  { 1284 /* bltc */, Mips::BLTC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
3432  { 1289 /* bltl */, Mips::BLTL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
3433  { 1289 /* bltl */, Mips::BLTLImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
3434  { 1294 /* bltu */, Mips::BLTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
3435  { 1294 /* bltu */, Mips::BLTUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
3436  { 1299 /* bltuc */, Mips::BLTUC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
3437  { 1305 /* bltul */, Mips::BLTUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
3438  { 1305 /* bltul */, Mips::BLTULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
3439  { 1311 /* bltz */, Mips::BLTZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3440  { 1311 /* bltz */, Mips::BLTZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3441  { 1316 /* bltzal */, Mips::BLTZAL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3442  { 1316 /* bltzal */, Mips::BLTZAL_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3443  { 1323 /* bltzalc */, Mips::BLTZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3444  { 1323 /* bltzalc */, Mips::BLTZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3445  { 1331 /* bltzall */, Mips::BLTZALL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3446  { 1339 /* bltzals */, Mips::BLTZALS_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3447  { 1347 /* bltzc */, Mips::BLTZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3448  { 1353 /* bltzl */, Mips::BLTZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3449  { 1359 /* bmnz.v */, Mips::BMNZ_V, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3450  { 1366 /* bmnzi.b */, Mips::BMNZI_B, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3451  { 1374 /* bmz.v */, Mips::BMZ_V, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3452  { 1380 /* bmzi.b */, Mips::BMZI_B, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3453  { 1387 /* bne */, Mips::BNE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
3454  { 1387 /* bne */, Mips::BNE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
3455  { 1387 /* bne */, Mips::BneImm, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
3456  { 1391 /* bnec */, Mips::BNEC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
3457  { 1396 /* bneg.b */, Mips::BNEG_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3458  { 1403 /* bneg.d */, Mips::BNEG_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3459  { 1410 /* bneg.h */, Mips::BNEG_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3460  { 1417 /* bneg.w */, Mips::BNEG_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3461  { 1424 /* bnegi.b */, Mips::BNEGI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3462  { 1432 /* bnegi.d */, Mips::BNEGI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3463  { 1440 /* bnegi.h */, Mips::BNEGI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3464  { 1448 /* bnegi.w */, Mips::BNEGI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3465  { 1456 /* bnel */, Mips::BNEL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
3466  { 1461 /* bnez */, Mips::BnezRxImmX16, Convert__Reg1_0__JumpTarget1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget }, },
3467  { 1461 /* bnez */, Mips::BNE, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, 0, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3468  { 1461 /* bnez */, Mips::BnezRxImm16, Convert__Reg1_0__JumpTarget1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
3469  { 1466 /* bnez16 */, Mips::BNEZ16_MM, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
3470  { 1473 /* bnezalc */, Mips::BNEZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3471  { 1473 /* bnezalc */, Mips::BNEZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3472  { 1481 /* bnezc */, Mips::BNEZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3473  { 1481 /* bnezc */, Mips::BNEZC_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3474  { 1487 /* bnezc16 */, Mips::BNEZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, Feature_HasMicroMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
3475  { 1495 /* bnezl */, Mips::BNEL, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, 0, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
3476  { 1501 /* bnvc */, Mips::BNVC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
3477  { 1506 /* bnz.b */, Mips::BNZ_B, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
3478  { 1512 /* bnz.d */, Mips::BNZ_D, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
3479  { 1518 /* bnz.h */, Mips::BNZ_H, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
3480  { 1524 /* bnz.v */, Mips::BNZ_V, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
3481  { 1530 /* bnz.w */, Mips::BNZ_W, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
3482  { 1536 /* bovc */, Mips::BOVC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
3483  { 1541 /* bposge32 */, Mips::BPOSGE32, Convert__JumpTarget1_0, Feature_HasDSP, { MCK_JumpTarget }, },
3484  { 1550 /* break */, Mips::BREAK, Convert__imm_95_0__imm_95_0, 0, {  }, },
3485  { 1550 /* break */, Mips::Break16, Convert_NoOperands, Feature_InMips16Mode, { MCK_0 }, },
3486  { 1550 /* break */, Mips::BREAK, Convert__ConstantUImm10_01_0__imm_95_0, 0, { MCK_ConstantUImm10_0 }, },
3487  { 1550 /* break */, Mips::BREAK, Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_ConstantUImm10_0, MCK_ConstantUImm10_0 }, },
3488  { 1550 /* break */, Mips::BREAK_MMR6, Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_ConstantUImm10_0, MCK_ConstantUImm10_0 }, },
3489  { 1550 /* break */, Mips::BREAK_MM, Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, Feature_InMicroMips, { MCK_ConstantUImm10_0, MCK_ConstantUImm10_0 }, },
3490  { 1556 /* break16 */, Mips::BREAK16_MM, Convert__ConstantUImm4_01_0, Feature_InMicroMips|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_ConstantUImm4_0 }, },
3491  { 1556 /* break16 */, Mips::BREAK16_MMR6, Convert__ConstantUImm4_01_0, Feature_HasMicroMips32r6, { MCK_ConstantUImm4_0 }, },
3492  { 1564 /* bsel.v */, Mips::BSEL_V, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3493  { 1571 /* bseli.b */, Mips::BSELI_B, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3494  { 1579 /* bset.b */, Mips::BSET_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3495  { 1586 /* bset.d */, Mips::BSET_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3496  { 1593 /* bset.h */, Mips::BSET_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3497  { 1600 /* bset.w */, Mips::BSET_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3498  { 1607 /* bseti.b */, Mips::BSETI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3499  { 1615 /* bseti.d */, Mips::BSETI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3500  { 1623 /* bseti.h */, Mips::BSETI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3501  { 1631 /* bseti.w */, Mips::BSETI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3502  { 1639 /* bteqz */, Mips::BteqzX16, Convert__Imm1_0, Feature_InMips16Mode, { MCK_Imm }, },
3503  { 1639 /* bteqz */, Mips::Bteqz16, Convert__Imm1_0, Feature_InMips16Mode, { MCK_Imm, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
3504  { 1645 /* btnez */, Mips::BtnezX16, Convert__Imm1_0, Feature_InMips16Mode, { MCK_Imm }, },
3505  { 1645 /* btnez */, Mips::Btnez16, Convert__Imm1_0, Feature_InMips16Mode, { MCK_Imm, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
3506  { 1651 /* bz.b */, Mips::BZ_B, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
3507  { 1656 /* bz.d */, Mips::BZ_D, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
3508  { 1661 /* bz.h */, Mips::BZ_H, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
3509  { 1666 /* bz.v */, Mips::BZ_V, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
3510  { 1671 /* bz.w */, Mips::BZ_W, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
3511  { 1676 /* c.eq.d */, Mips::C_EQ_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
3512  { 1676 /* c.eq.d */, Mips::C_EQ_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3513  { 1683 /* c.eq.s */, Mips::C_EQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3514  { 1690 /* c.f.d */, Mips::C_F_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
3515  { 1690 /* c.f.d */, Mips::C_F_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3516  { 1696 /* c.f.s */, Mips::C_F_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3517  { 1702 /* c.le.d */, Mips::C_LE_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
3518  { 1702 /* c.le.d */, Mips::C_LE_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3519  { 1709 /* c.le.s */, Mips::C_LE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3520  { 1716 /* c.lt.d */, Mips::C_LT_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
3521  { 1716 /* c.lt.d */, Mips::C_LT_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3522  { 1723 /* c.lt.s */, Mips::C_LT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3523  { 1730 /* c.nge.d */, Mips::C_NGE_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
3524  { 1730 /* c.nge.d */, Mips::C_NGE_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3525  { 1738 /* c.nge.s */, Mips::C_NGE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3526  { 1746 /* c.ngl.d */, Mips::C_NGL_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
3527  { 1746 /* c.ngl.d */, Mips::C_NGL_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3528  { 1754 /* c.ngl.s */, Mips::C_NGL_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3529  { 1762 /* c.ngle.d */, Mips::C_NGLE_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
3530  { 1762 /* c.ngle.d */, Mips::C_NGLE_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3531  { 1771 /* c.ngle.s */, Mips::C_NGLE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3532  { 1780 /* c.ngt.d */, Mips::C_NGT_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
3533  { 1780 /* c.ngt.d */, Mips::C_NGT_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3534  { 1788 /* c.ngt.s */, Mips::C_NGT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3535  { 1796 /* c.ole.d */, Mips::C_OLE_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
3536  { 1796 /* c.ole.d */, Mips::C_OLE_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3537  { 1804 /* c.ole.s */, Mips::C_OLE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3538  { 1812 /* c.olt.d */, Mips::C_OLT_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
3539  { 1812 /* c.olt.d */, Mips::C_OLT_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3540  { 1820 /* c.olt.s */, Mips::C_OLT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3541  { 1828 /* c.seq.d */, Mips::C_SEQ_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
3542  { 1828 /* c.seq.d */, Mips::C_SEQ_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3543  { 1836 /* c.seq.s */, Mips::C_SEQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3544  { 1844 /* c.sf.d */, Mips::C_SF_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
3545  { 1844 /* c.sf.d */, Mips::C_SF_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3546  { 1851 /* c.sf.s */, Mips::C_SF_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3547  { 1858 /* c.ueq.d */, Mips::C_UEQ_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
3548  { 1858 /* c.ueq.d */, Mips::C_UEQ_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3549  { 1866 /* c.ueq.s */, Mips::C_UEQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3550  { 1874 /* c.ule.d */, Mips::C_ULE_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
3551  { 1874 /* c.ule.d */, Mips::C_ULE_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3552  { 1882 /* c.ule.s */, Mips::C_ULE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3553  { 1890 /* c.ult.d */, Mips::C_ULT_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
3554  { 1890 /* c.ult.d */, Mips::C_ULT_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3555  { 1898 /* c.ult.s */, Mips::C_ULT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3556  { 1906 /* c.un.d */, Mips::C_UN_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
3557  { 1906 /* c.un.d */, Mips::C_UN_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3558  { 1913 /* c.un.s */, Mips::C_UN_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3559  { 1920 /* cache */, Mips::CACHE_R6, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, },
3560  { 1920 /* cache */, Mips::CACHE, Convert__Mem2_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMips3_32|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_ConstantUImm5_0, MCK_Mem }, },
3561  { 1920 /* cache */, Mips::CACHE_MMR6, Convert__Mem2_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, },
3562  { 1920 /* cache */, Mips::CACHE_MM, Convert__Mem2_1__ConstantUImm5_01_0, Feature_InMicroMips, { MCK_ConstantUImm5_0, MCK_Mem }, },
3563  { 1926 /* cachee */, Mips::CACHEE, Convert__Mem2_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasEVA, { MCK_ConstantUImm5_0, MCK_Mem }, },
3564  { 1926 /* cachee */, Mips::CACHEE_MMR6, Convert__Mem2_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, },
3565  { 1926 /* cachee */, Mips::CACHEE_MM, Convert__Mem2_1__ConstantUImm5_01_0, Feature_InMicroMips, { MCK_ConstantUImm5_0, MCK_Mem }, },
3566  { 1933 /* ceil.l.d */, Mips::CEIL_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3567  { 1933 /* ceil.l.d */, Mips::CEIL_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3568  { 1942 /* ceil.l.s */, Mips::CEIL_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
3569  { 1942 /* ceil.l.s */, Mips::CEIL_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
3570  { 1951 /* ceil.w.d */, Mips::CEIL_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
3571  { 1951 /* ceil.w.d */, Mips::CEIL_W_D_MMR6, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
3572  { 1951 /* ceil.w.d */, Mips::CEIL_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
3573  { 1960 /* ceil.w.s */, Mips::CEIL_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3574  { 1960 /* ceil.w.s */, Mips::CEIL_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3575  { 1960 /* ceil.w.s */, Mips::CEIL_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3576  { 1969 /* ceq.b */, Mips::CEQ_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3577  { 1975 /* ceq.d */, Mips::CEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3578  { 1981 /* ceq.h */, Mips::CEQ_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3579  { 1987 /* ceq.w */, Mips::CEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3580  { 1993 /* ceqi.b */, Mips::CEQI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3581  { 2000 /* ceqi.d */, Mips::CEQI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3582  { 2007 /* ceqi.h */, Mips::CEQI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3583  { 2014 /* ceqi.w */, Mips::CEQI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3584  { 2021 /* cfc1 */, Mips::CFC1, Convert__GPR32AsmReg1_0__CCRAsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, },
3585  { 2026 /* cfcmsa */, Mips::CFCMSA, Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_MSACtrlAsmReg }, },
3586  { 2033 /* cins */, Mips::CINS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
3587  { 2033 /* cins */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, },
3588  { 2033 /* cins */, Mips::CINS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
3589  { 2033 /* cins */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, },
3590  { 2038 /* cins32 */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
3591  { 2038 /* cins32 */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
3592  { 2045 /* class.d */, Mips::CLASS_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3593  { 2045 /* class.d */, Mips::CLASS_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3594  { 2053 /* class.s */, Mips::CLASS_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3595  { 2053 /* class.s */, Mips::CLASS_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3596  { 2061 /* cle_s.b */, Mips::CLE_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3597  { 2069 /* cle_s.d */, Mips::CLE_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3598  { 2077 /* cle_s.h */, Mips::CLE_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3599  { 2085 /* cle_s.w */, Mips::CLE_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3600  { 2093 /* cle_u.b */, Mips::CLE_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3601  { 2101 /* cle_u.d */, Mips::CLE_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3602  { 2109 /* cle_u.h */, Mips::CLE_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3603  { 2117 /* cle_u.w */, Mips::CLE_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3604  { 2125 /* clei_s.b */, Mips::CLEI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3605  { 2134 /* clei_s.d */, Mips::CLEI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3606  { 2143 /* clei_s.h */, Mips::CLEI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3607  { 2152 /* clei_s.w */, Mips::CLEI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3608  { 2161 /* clei_u.b */, Mips::CLEI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3609  { 2170 /* clei_u.d */, Mips::CLEI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3610  { 2179 /* clei_u.h */, Mips::CLEI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3611  { 2188 /* clei_u.w */, Mips::CLEI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3612  { 2197 /* clo */, Mips::CLO, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3613  { 2197 /* clo */, Mips::CLO_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3614  { 2197 /* clo */, Mips::CLO_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3615  { 2197 /* clo */, Mips::CLO_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3616  { 2201 /* clt_s.b */, Mips::CLT_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3617  { 2209 /* clt_s.d */, Mips::CLT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3618  { 2217 /* clt_s.h */, Mips::CLT_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3619  { 2225 /* clt_s.w */, Mips::CLT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3620  { 2233 /* clt_u.b */, Mips::CLT_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3621  { 2241 /* clt_u.d */, Mips::CLT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3622  { 2249 /* clt_u.h */, Mips::CLT_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3623  { 2257 /* clt_u.w */, Mips::CLT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3624  { 2265 /* clti_s.b */, Mips::CLTI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3625  { 2274 /* clti_s.d */, Mips::CLTI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3626  { 2283 /* clti_s.h */, Mips::CLTI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3627  { 2292 /* clti_s.w */, Mips::CLTI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3628  { 2301 /* clti_u.b */, Mips::CLTI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3629  { 2310 /* clti_u.d */, Mips::CLTI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3630  { 2319 /* clti_u.h */, Mips::CLTI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3631  { 2328 /* clti_u.w */, Mips::CLTI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
3632  { 2337 /* clz */, Mips::CLZ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3633  { 2337 /* clz */, Mips::CLZ_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3634  { 2337 /* clz */, Mips::CLZ_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3635  { 2337 /* clz */, Mips::CLZ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3636  { 2341 /* cmp */, Mips::CmpRxRy16, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
3637  { 2345 /* cmp.af.d */, Mips::CMP_F_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3638  { 2345 /* cmp.af.d */, Mips::CMP_AF_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3639  { 2354 /* cmp.af.s */, Mips::CMP_F_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3640  { 2354 /* cmp.af.s */, Mips::CMP_AF_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3641  { 2363 /* cmp.eq.d */, Mips::CMP_EQ_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3642  { 2363 /* cmp.eq.d */, Mips::CMP_EQ_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3643  { 2372 /* cmp.eq.ph */, Mips::CMP_EQ_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3644  { 2382 /* cmp.eq.s */, Mips::CMP_EQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3645  { 2382 /* cmp.eq.s */, Mips::CMP_EQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3646  { 2391 /* cmp.le.d */, Mips::CMP_LE_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3647  { 2391 /* cmp.le.d */, Mips::CMP_LE_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3648  { 2400 /* cmp.le.ph */, Mips::CMP_LE_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3649  { 2410 /* cmp.le.s */, Mips::CMP_LE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3650  { 2410 /* cmp.le.s */, Mips::CMP_LE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3651  { 2419 /* cmp.lt.d */, Mips::CMP_LT_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3652  { 2419 /* cmp.lt.d */, Mips::CMP_LT_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3653  { 2428 /* cmp.lt.ph */, Mips::CMP_LT_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3654  { 2438 /* cmp.lt.s */, Mips::CMP_LT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3655  { 2438 /* cmp.lt.s */, Mips::CMP_LT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3656  { 2447 /* cmp.saf.d */, Mips::CMP_SAF_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3657  { 2447 /* cmp.saf.d */, Mips::CMP_SAF_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3658  { 2457 /* cmp.saf.s */, Mips::CMP_SAF_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3659  { 2457 /* cmp.saf.s */, Mips::CMP_SAF_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3660  { 2467 /* cmp.seq.d */, Mips::CMP_SEQ_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3661  { 2467 /* cmp.seq.d */, Mips::CMP_SEQ_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3662  { 2477 /* cmp.seq.s */, Mips::CMP_SEQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3663  { 2477 /* cmp.seq.s */, Mips::CMP_SEQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3664  { 2487 /* cmp.sle.d */, Mips::CMP_SLE_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3665  { 2487 /* cmp.sle.d */, Mips::CMP_SLE_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3666  { 2497 /* cmp.sle.s */, Mips::CMP_SLE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3667  { 2497 /* cmp.sle.s */, Mips::CMP_SLE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3668  { 2507 /* cmp.slt.d */, Mips::CMP_SLT_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3669  { 2507 /* cmp.slt.d */, Mips::CMP_SLT_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3670  { 2517 /* cmp.slt.s */, Mips::CMP_SLT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3671  { 2517 /* cmp.slt.s */, Mips::CMP_SLT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3672  { 2527 /* cmp.sueq.d */, Mips::CMP_SUEQ_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3673  { 2527 /* cmp.sueq.d */, Mips::CMP_SUEQ_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3674  { 2538 /* cmp.sueq.s */, Mips::CMP_SUEQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3675  { 2538 /* cmp.sueq.s */, Mips::CMP_SUEQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3676  { 2549 /* cmp.sule.d */, Mips::CMP_SULE_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3677  { 2549 /* cmp.sule.d */, Mips::CMP_SULE_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3678  { 2560 /* cmp.sule.s */, Mips::CMP_SULE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3679  { 2560 /* cmp.sule.s */, Mips::CMP_SULE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3680  { 2571 /* cmp.sult.d */, Mips::CMP_SULT_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3681  { 2571 /* cmp.sult.d */, Mips::CMP_SULT_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3682  { 2582 /* cmp.sult.s */, Mips::CMP_SULT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3683  { 2582 /* cmp.sult.s */, Mips::CMP_SULT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3684  { 2593 /* cmp.sun.d */, Mips::CMP_SUN_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3685  { 2593 /* cmp.sun.d */, Mips::CMP_SUN_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3686  { 2603 /* cmp.sun.s */, Mips::CMP_SUN_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3687  { 2603 /* cmp.sun.s */, Mips::CMP_SUN_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3688  { 2613 /* cmp.ueq.d */, Mips::CMP_UEQ_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3689  { 2613 /* cmp.ueq.d */, Mips::CMP_UEQ_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3690  { 2623 /* cmp.ueq.s */, Mips::CMP_UEQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3691  { 2623 /* cmp.ueq.s */, Mips::CMP_UEQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3692  { 2633 /* cmp.ule.d */, Mips::CMP_ULE_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3693  { 2633 /* cmp.ule.d */, Mips::CMP_ULE_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3694  { 2643 /* cmp.ule.s */, Mips::CMP_ULE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3695  { 2643 /* cmp.ule.s */, Mips::CMP_ULE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3696  { 2653 /* cmp.ult.d */, Mips::CMP_ULT_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3697  { 2653 /* cmp.ult.d */, Mips::CMP_ULT_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3698  { 2663 /* cmp.ult.s */, Mips::CMP_ULT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3699  { 2663 /* cmp.ult.s */, Mips::CMP_ULT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3700  { 2673 /* cmp.un.d */, Mips::CMP_UN_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3701  { 2673 /* cmp.un.d */, Mips::CMP_UN_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3702  { 2682 /* cmp.un.s */, Mips::CMP_UN_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3703  { 2682 /* cmp.un.s */, Mips::CMP_UN_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3704  { 2691 /* cmpgdu.eq.qb */, Mips::CMPGDU_EQ_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3705  { 2704 /* cmpgdu.le.qb */, Mips::CMPGDU_LE_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3706  { 2717 /* cmpgdu.lt.qb */, Mips::CMPGDU_LT_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3707  { 2730 /* cmpgu.eq.qb */, Mips::CMPGU_EQ_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3708  { 2742 /* cmpgu.le.qb */, Mips::CMPGU_LE_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3709  { 2754 /* cmpgu.lt.qb */, Mips::CMPGU_LT_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3710  { 2766 /* cmpi */, Mips::CmpiRxImmX16, Convert__Reg1_0__Imm1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_Imm }, },
3711  { 2766 /* cmpi */, Mips::CmpiRxImm16, Convert__Reg1_0__Imm1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_Imm, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
3712  { 2771 /* cmpu.eq.qb */, Mips::CMPU_EQ_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3713  { 2782 /* cmpu.le.qb */, Mips::CMPU_LE_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3714  { 2793 /* cmpu.lt.qb */, Mips::CMPU_LT_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3715  { 2804 /* copy_s.b */, Mips::COPY_S_B, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__Imm1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_Imm, MCK__93_ }, },
3716  { 2813 /* copy_s.d */, Mips::COPY_S_D, Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__Imm1_3, Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, { MCK_GPR64AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_Imm, MCK__93_ }, },
3717  { 2822 /* copy_s.h */, Mips::COPY_S_H, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__Imm1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_Imm, MCK__93_ }, },
3718  { 2831 /* copy_s.w */, Mips::COPY_S_W, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__Imm1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_Imm, MCK__93_ }, },
3719  { 2840 /* copy_u.b */, Mips::COPY_U_B, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__Imm1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_Imm, MCK__93_ }, },
3720  { 2849 /* copy_u.h */, Mips::COPY_U_H, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__Imm1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_Imm, MCK__93_ }, },
3721  { 2858 /* copy_u.w */, Mips::COPY_U_W, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__Imm1_3, Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_Imm, MCK__93_ }, },
3722  { 2867 /* ctc1 */, Mips::CTC1, Convert__CCRAsmReg1_1__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, },
3723  { 2872 /* ctcmsa */, Mips::CTCMSA, Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSACtrlAsmReg, MCK_GPR32AsmReg }, },
3724  { 2879 /* cvt.d.l */, Mips::CVT_D_L_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3725  { 2879 /* cvt.d.l */, Mips::CVT_D64_L, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3726  { 2887 /* cvt.d.s */, Mips::CVT_D32_S, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, },
3727  { 2887 /* cvt.d.s */, Mips::CVT_D_S_MMR6, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
3728  { 2887 /* cvt.d.s */, Mips::CVT_D64_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
3729  { 2895 /* cvt.d.w */, Mips::CVT_D32_W, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, },
3730  { 2895 /* cvt.d.w */, Mips::CVT_D_W_MMR6, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
3731  { 2895 /* cvt.d.w */, Mips::CVT_D64_W, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
3732  { 2903 /* cvt.l.d */, Mips::CVT_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3733  { 2903 /* cvt.l.d */, Mips::CVT_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3734  { 2911 /* cvt.l.s */, Mips::CVT_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
3735  { 2911 /* cvt.l.s */, Mips::CVT_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
3736  { 2919 /* cvt.s.d */, Mips::CVT_S_D_MMR6, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, },
3737  { 2919 /* cvt.s.d */, Mips::CVT_S_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
3738  { 2919 /* cvt.s.d */, Mips::CVT_S_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
3739  { 2927 /* cvt.s.l */, Mips::CVT_S_L, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
3740  { 2927 /* cvt.s.l */, Mips::CVT_S_L_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
3741  { 2935 /* cvt.s.w */, Mips::CVT_S_W_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3742  { 2935 /* cvt.s.w */, Mips::CVT_S_W, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3743  { 2943 /* cvt.w.d */, Mips::CVT_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
3744  { 2943 /* cvt.w.d */, Mips::CVT_W_D_MMR6, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
3745  { 2943 /* cvt.w.d */, Mips::CVT_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
3746  { 2951 /* cvt.w.s */, Mips::CVT_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3747  { 2951 /* cvt.w.s */, Mips::CVT_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3748  { 2959 /* dadd */, Mips::DADD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
3749  { 2959 /* dadd */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_Imm }, },
3750  { 2959 /* dadd */, Mips::DADD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
3751  { 2959 /* dadd */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
3752  { 2964 /* daddi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_Imm }, },
3753  { 2964 /* daddi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
3754  { 2970 /* daddiu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_HasStdEnc|Feature_HasMips3, { MCK_GPR64AsmReg, MCK_Imm }, },
3755  { 2970 /* daddiu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMips3, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
3756  { 2977 /* daddu */, Mips::DADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
3757  { 2977 /* daddu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_HasMips3, { MCK_GPR64AsmReg, MCK_Imm }, },
3758  { 2977 /* daddu */, Mips::DADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
3759  { 2977 /* daddu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_HasMips3, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
3760  { 2983 /* dahi */, Mips::DAHI, Convert__GPR64AsmReg1_0__Tie0__Imm1_1, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, },
3761  { 2983 /* dahi */, Mips::DAHI_MM64R6, Convert__GPR64AsmReg1_0__Tie0__Imm1_1, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_Imm }, },
3762  { 2988 /* dalign */, Mips::DALIGN, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm3_0 }, },
3763  { 2988 /* dalign */, Mips::DALIGN_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm3_0 }, },
3764  { 2995 /* dati */, Mips::DATI, Convert__GPR64AsmReg1_0__Tie0__Imm1_1, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, },
3765  { 2995 /* dati */, Mips::DATI_MM64R6, Convert__GPR64AsmReg1_0__Tie0__Imm1_1, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_Imm }, },
3766  { 3000 /* daui */, Mips::DAUI, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
3767  { 3000 /* daui */, Mips::DAUI_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
3768  { 3005 /* dbitswap */, Mips::DBITSWAP, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
3769  { 3014 /* dclo */, Mips::DCLO, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
3770  { 3014 /* dclo */, Mips::DCLO_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
3771  { 3019 /* dclz */, Mips::DCLZ, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
3772  { 3019 /* dclz */, Mips::DCLZ_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
3773  { 3024 /* ddiv */, Mips::DDIV_MM64R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3774  { 3024 /* ddiv */, Mips::DSDivMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3775  { 3024 /* ddiv */, Mips::DSDIV, Convert__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_ZERO, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
3776  { 3024 /* ddiv */, Mips::DDIV_MM64R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3777  { 3024 /* ddiv */, Mips::DDIV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
3778  { 3029 /* ddivu */, Mips::DDIVU_MM64R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3779  { 3029 /* ddivu */, Mips::DUDivMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3780  { 3029 /* ddivu */, Mips::DUDIV, Convert__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_ZERO, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
3781  { 3029 /* ddivu */, Mips::DDIVU_MM64R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3782  { 3029 /* ddivu */, Mips::DDIVU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
3783  { 3035 /* deret */, Mips::DERET, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32|Feature_NotInMicroMips, {  }, },
3784  { 3035 /* deret */, Mips::DERET_MMR6, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMicroMips32r6, {  }, },
3785  { 3035 /* deret */, Mips::DERET_MM, Convert_NoOperands, Feature_InMicroMips, {  }, },
3786  { 3041 /* dext */, Mips::DEXT, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
3787  { 3041 /* dext */, Mips::DEXT_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
3788  { 3046 /* dextm */, Mips::DEXTM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_33 }, },
3789  { 3046 /* dextm */, Mips::DEXTM_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_33 }, },
3790  { 3052 /* dextu */, Mips::DEXTU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, },
3791  { 3052 /* dextu */, Mips::DEXTU_MM64R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, },
3792  { 3058 /* di */, Mips::DI, Convert__regZERO, Feature_HasMips32r2|Feature_NotInMicroMips, {  }, },
3793  { 3058 /* di */, Mips::DI_MM, Convert__regZERO, Feature_InMicroMips, {  }, },
3794  { 3058 /* di */, Mips::DI_MMR6, Convert__regZERO, Feature_HasMicroMips32r6, {  }, },
3795  { 3058 /* di */, Mips::DI, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
3796  { 3058 /* di */, Mips::DI_MMR6, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg }, },
3797  { 3058 /* di */, Mips::DI_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, },
3798  { 3061 /* dins */, Mips::DINS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__Imm1_3__Tie0, Feature_HasStdEnc|Feature_HasMips32r2, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0, MCK_Imm }, },
3799  { 3066 /* dinsm */, Mips::DINSM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__Imm1_3__Tie0, Feature_HasStdEnc|Feature_HasMips32r2, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_Imm }, },
3800  { 3072 /* dinsu */, Mips::DINSU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__Imm1_3__Tie0, Feature_HasStdEnc|Feature_HasMips32r2, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_Imm }, },
3801  { 3078 /* div */, Mips::DIV_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3802  { 3078 /* div */, Mips::SDivMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3803  { 3078 /* div */, Mips::DivRxRy16, Convert__Reg1_1__Reg1_2, Feature_InMips16Mode, { MCK_ZERO, MCK_CPU16Regs, MCK_CPU16Regs }, },
3804  { 3078 /* div */, Mips::SDIV, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3805  { 3078 /* div */, Mips::SDIV_MM, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3806  { 3078 /* div */, Mips::DIV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3807  { 3078 /* div */, Mips::DIV_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3808  { 3082 /* div.d */, Mips::FDIV_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
3809  { 3082 /* div.d */, Mips::FDIV_D_MMR6, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_2__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
3810  { 3082 /* div.d */, Mips::FDIV_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
3811  { 3088 /* div.s */, Mips::FDIV_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3812  { 3088 /* div.s */, Mips::FDIV_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
3813  { 3094 /* div_s.b */, Mips::DIV_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3814  { 3102 /* div_s.d */, Mips::DIV_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3815  { 3110 /* div_s.h */, Mips::DIV_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3816  { 3118 /* div_s.w */, Mips::DIV_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3817  { 3126 /* div_u.b */, Mips::DIV_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3818  { 3134 /* div_u.d */, Mips::DIV_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3819  { 3142 /* div_u.h */, Mips::DIV_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3820  { 3150 /* div_u.w */, Mips::DIV_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3821  { 3158 /* divu */, Mips::DIVU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3822  { 3158 /* divu */, Mips::UDivMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3823  { 3158 /* divu */, Mips::DivuRxRy16, Convert__Reg1_1__Reg1_2, Feature_InMips16Mode, { MCK_ZERO, MCK_CPU16Regs, MCK_CPU16Regs }, },
3824  { 3158 /* divu */, Mips::UDIV, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3825  { 3158 /* divu */, Mips::UDIV_MM, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3826  { 3158 /* divu */, Mips::DIVU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3827  { 3158 /* divu */, Mips::DIVU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3828  { 3163 /* dla */, Mips::LoadAddrImm64, Convert__GPR64AsmReg1_0__Imm1_1, 0, { MCK_GPR64AsmReg, MCK_Imm }, },
3829  { 3163 /* dla */, Mips::LoadAddrReg64, Convert__GPR64AsmReg1_0__Mem2_1, 0, { MCK_GPR64AsmReg, MCK_Mem }, },
3830  { 3167 /* dli */, Mips::LoadImm64, Convert__GPR64AsmReg1_0__Imm1_1, 0, { MCK_GPR64AsmReg, MCK_Imm }, },
3831  { 3171 /* dlsa */, Mips::DLSA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3, Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm2_1 }, },
3832  { 3171 /* dlsa */, Mips::DLSA_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3, Feature_HasStdEnc|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm2_1 }, },
3833  { 3176 /* dmfc0 */, Mips::DMFC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0, 0, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, },
3834  { 3176 /* dmfc0 */, Mips::DMFC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__UImm161_2, Feature_HasMips64, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_UImm16 }, },
3835  { 3182 /* dmfc1 */, Mips::DMFC1, Convert__GPR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_IsNotSoftFloat, { MCK_GPR64AsmReg, MCK_FGR64AsmReg }, },
3836  { 3188 /* dmfc2 */, Mips::DMFC2, Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0, 0, { MCK_GPR64AsmReg, MCK_COP2AsmReg }, },
3837  { 3188 /* dmfc2 */, Mips::DMFC2_OCTEON, Convert__GPR64AsmReg1_0__UImm161_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_UImm16 }, },
3838  { 3188 /* dmfc2 */, Mips::DMFC2, Convert__GPR64AsmReg1_0__COP2AsmReg1_1__UImm161_2, Feature_HasMips64, { MCK_GPR64AsmReg, MCK_COP2AsmReg, MCK_UImm16 }, },
3839  { 3194 /* dmod */, Mips::DMOD_MM64R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3840  { 3194 /* dmod */, Mips::DMOD_MM64R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3841  { 3194 /* dmod */, Mips::DMOD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
3842  { 3199 /* dmodu */, Mips::DMODU_MM64R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3843  { 3199 /* dmodu */, Mips::DMODU_MM64R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3844  { 3199 /* dmodu */, Mips::DMODU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
3845  { 3205 /* dmtc0 */, Mips::DMTC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0, 0, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, },
3846  { 3205 /* dmtc0 */, Mips::DMTC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__UImm161_2, Feature_HasMips64, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_UImm16 }, },
3847  { 3211 /* dmtc1 */, Mips::DMTC1, Convert__FGR64AsmReg1_1__GPR64AsmReg1_0, Feature_HasStdEnc|Feature_HasMips3|Feature_IsNotSoftFloat, { MCK_GPR64AsmReg, MCK_FGR64AsmReg }, },
3848  { 3217 /* dmtc2 */, Mips::DMTC2, Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0, 0, { MCK_GPR64AsmReg, MCK_COP2AsmReg }, },
3849  { 3217 /* dmtc2 */, Mips::DMTC2_OCTEON, Convert__GPR64AsmReg1_0__UImm161_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_UImm16 }, },
3850  { 3217 /* dmtc2 */, Mips::DMTC2, Convert__COP2AsmReg1_1__GPR64AsmReg1_0__UImm161_2, Feature_HasMips64, { MCK_GPR64AsmReg, MCK_COP2AsmReg, MCK_UImm16 }, },
3851  { 3223 /* dmuh */, Mips::DMUH, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
3852  { 3228 /* dmuhu */, Mips::DMUHU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
3853  { 3234 /* dmul */, Mips::DMUL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
3854  { 3234 /* dmul */, Mips::DMUL_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
3855  { 3234 /* dmul */, Mips::DMUL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
3856  { 3239 /* dmult */, Mips::DMULT, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
3857  { 3245 /* dmultu */, Mips::DMULTu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
3858  { 3252 /* dmulu */, Mips::DMULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
3859  { 3258 /* dneg */, Mips::DSUB, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0, Feature_HasMips3, { MCK_GPR64AsmReg }, },
3860  { 3258 /* dneg */, Mips::DSUB, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1, Feature_HasMips3, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
3861  { 3263 /* dnegu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1, Feature_HasMips3, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
3862  { 3269 /* dotp_s.d */, Mips::DOTP_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3863  { 3278 /* dotp_s.h */, Mips::DOTP_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3864  { 3287 /* dotp_s.w */, Mips::DOTP_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3865  { 3296 /* dotp_u.d */, Mips::DOTP_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3866  { 3305 /* dotp_u.h */, Mips::DOTP_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3867  { 3314 /* dotp_u.w */, Mips::DOTP_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3868  { 3323 /* dpa.w.ph */, Mips::DPA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSPR2|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3869  { 3323 /* dpa.w.ph */, Mips::DPA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3870  { 3332 /* dpadd_s.d */, Mips::DPADD_S_D, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3871  { 3342 /* dpadd_s.h */, Mips::DPADD_S_H, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3872  { 3352 /* dpadd_s.w */, Mips::DPADD_S_W, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3873  { 3362 /* dpadd_u.d */, Mips::DPADD_U_D, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3874  { 3372 /* dpadd_u.h */, Mips::DPADD_U_H, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3875  { 3382 /* dpadd_u.w */, Mips::DPADD_U_W, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3876  { 3392 /* dpaq_s.w.ph */, Mips::DPAQ_S_W_PH_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3877  { 3392 /* dpaq_s.w.ph */, Mips::DPAQ_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3878  { 3404 /* dpaq_sa.l.w */, Mips::DPAQ_SA_L_W_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3879  { 3404 /* dpaq_sa.l.w */, Mips::DPAQ_SA_L_W, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3880  { 3416 /* dpaqx_s.w.ph */, Mips::DPAQX_S_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSPR2|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3881  { 3416 /* dpaqx_s.w.ph */, Mips::DPAQX_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3882  { 3429 /* dpaqx_sa.w.ph */, Mips::DPAQX_SA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSPR2|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3883  { 3429 /* dpaqx_sa.w.ph */, Mips::DPAQX_SA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3884  { 3443 /* dpau.h.qbl */, Mips::DPAU_H_QBL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3885  { 3443 /* dpau.h.qbl */, Mips::DPAU_H_QBL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3886  { 3454 /* dpau.h.qbr */, Mips::DPAU_H_QBR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3887  { 3454 /* dpau.h.qbr */, Mips::DPAU_H_QBR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3888  { 3465 /* dpax.w.ph */, Mips::DPAX_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSPR2|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3889  { 3465 /* dpax.w.ph */, Mips::DPAX_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3890  { 3475 /* dpop */, Mips::DPOP, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, },
3891  { 3475 /* dpop */, Mips::DPOP, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
3892  { 3480 /* dps.w.ph */, Mips::DPS_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSPR2|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3893  { 3480 /* dps.w.ph */, Mips::DPS_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3894  { 3489 /* dpsq_s.w.ph */, Mips::DPSQ_S_W_PH_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3895  { 3489 /* dpsq_s.w.ph */, Mips::DPSQ_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3896  { 3501 /* dpsq_sa.l.w */, Mips::DPSQ_SA_L_W_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3897  { 3501 /* dpsq_sa.l.w */, Mips::DPSQ_SA_L_W, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3898  { 3513 /* dpsqx_s.w.ph */, Mips::DPSQX_S_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSPR2|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3899  { 3513 /* dpsqx_s.w.ph */, Mips::DPSQX_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3900  { 3526 /* dpsqx_sa.w.ph */, Mips::DPSQX_SA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSPR2|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3901  { 3526 /* dpsqx_sa.w.ph */, Mips::DPSQX_SA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3902  { 3540 /* dpsu.h.qbl */, Mips::DPSU_H_QBL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3903  { 3540 /* dpsu.h.qbl */, Mips::DPSU_H_QBL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3904  { 3551 /* dpsu.h.qbr */, Mips::DPSU_H_QBR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3905  { 3551 /* dpsu.h.qbr */, Mips::DPSU_H_QBR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3906  { 3562 /* dpsub_s.d */, Mips::DPSUB_S_D, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3907  { 3572 /* dpsub_s.h */, Mips::DPSUB_S_H, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3908  { 3582 /* dpsub_s.w */, Mips::DPSUB_S_W, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3909  { 3592 /* dpsub_u.d */, Mips::DPSUB_U_D, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3910  { 3602 /* dpsub_u.h */, Mips::DPSUB_U_H, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3911  { 3612 /* dpsub_u.w */, Mips::DPSUB_U_W, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
3912  { 3622 /* dpsx.w.ph */, Mips::DPSX_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSPR2|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3913  { 3622 /* dpsx.w.ph */, Mips::DPSX_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3914  { 3632 /* drol */, Mips::DROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3915  { 3632 /* drol */, Mips::DROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__Imm1_1, Feature_HasMips64, { MCK_GPR32AsmReg, MCK_Imm }, },
3916  { 3632 /* drol */, Mips::DROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3917  { 3632 /* drol */, Mips::DROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__Imm1_2, Feature_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_Imm }, },
3918  { 3637 /* dror */, Mips::DROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3919  { 3637 /* dror */, Mips::DRORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__Imm1_1, Feature_HasMips64, { MCK_GPR32AsmReg, MCK_Imm }, },
3920  { 3637 /* dror */, Mips::DROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
3921  { 3637 /* dror */, Mips::DRORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__Imm1_2, Feature_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_Imm }, },
3922  { 3642 /* drotr */, Mips::DROTR, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, Feature_HasStdEnc|Feature_HasMips64r2, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
3923  { 3642 /* drotr */, Mips::DROTR, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMips64r2, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
3924  { 3648 /* drotr32 */, Mips::DROTR32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_HasMips64r2, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
3925  { 3648 /* drotr32 */, Mips::DROTR32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMips64r2, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
3926  { 3656 /* drotrv */, Mips::DROTRV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r2, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
3927  { 3663 /* dsbh */, Mips::DSBH, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64r2, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
3928  { 3668 /* dshd */, Mips::DSHD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64r2, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
3929  { 3673 /* dsll */, Mips::DSLL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, Feature_HasStdEnc|Feature_HasMips3, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
3930  { 3673 /* dsll */, Mips::DSLLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasMips3, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
3931  { 3673 /* dsll */, Mips::DSLL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMips3, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
3932  { 3678 /* dsll32 */, Mips::DSLL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_HasMips3, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
3933  { 3678 /* dsll32 */, Mips::DSLL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMips3, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
3934  { 3685 /* dsllv */, Mips::DSLLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
3935  { 3691 /* dsra */, Mips::DSRA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, Feature_HasStdEnc|Feature_HasMips3, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
3936  { 3691 /* dsra */, Mips::DSRAV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasMips3, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
3937  { 3691 /* dsra */, Mips::DSRA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMips3, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
3938  { 3696 /* dsra32 */, Mips::DSRA32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_HasMips3, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
3939  { 3696 /* dsra32 */, Mips::DSRA32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMips3, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
3940  { 3703 /* dsrav */, Mips::DSRAV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
3941  { 3709 /* dsrl */, Mips::DSRL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, Feature_HasStdEnc|Feature_HasMips3, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
3942  { 3709 /* dsrl */, Mips::DSRLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasMips3, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
3943  { 3709 /* dsrl */, Mips::DSRL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMips3, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
3944  { 3714 /* dsrl32 */, Mips::DSRL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_HasMips3, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
3945  { 3714 /* dsrl32 */, Mips::DSRL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMips3, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
3946  { 3721 /* dsrlv */, Mips::DSRLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
3947  { 3727 /* dsub */, Mips::DSUB, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
3948  { 3727 /* dsub */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_InvNum }, },
3949  { 3727 /* dsub */, Mips::DSUB, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
3950  { 3727 /* dsub */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_InvNum }, },
3951  { 3732 /* dsubi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_InvNum }, },
3952  { 3732 /* dsubi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_InvNum }, },
3953  { 3738 /* dsubu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
3954  { 3738 /* dsubu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, Feature_HasMips3, { MCK_GPR64AsmReg, MCK_InvNum }, },
3955  { 3738 /* dsubu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
3956  { 3738 /* dsubu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, Feature_HasMips3, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_InvNum }, },
3957  { 3744 /* ehb */, Mips::EHB_MMR6, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMicroMips32r6, {  }, },
3958  { 3744 /* ehb */, Mips::EHB, Convert_NoOperands, Feature_HasStdEnc, {  }, },
3959  { 3744 /* ehb */, Mips::EHB_MM, Convert_NoOperands, Feature_InMicroMips, {  }, },
3960  { 3748 /* ei */, Mips::EI, Convert__regZERO, Feature_HasMips32r2|Feature_NotInMicroMips, {  }, },
3961  { 3748 /* ei */, Mips::EI_MM, Convert__regZERO, Feature_InMicroMips, {  }, },
3962  { 3748 /* ei */, Mips::EI_MMR6, Convert__regZERO, Feature_HasMicroMips32r6, {  }, },
3963  { 3748 /* ei */, Mips::EI, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
3964  { 3748 /* ei */, Mips::EI_MMR6, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg }, },
3965  { 3748 /* ei */, Mips::EI_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, },
3966  { 3751 /* eret */, Mips::ERET, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips3_32|Feature_NotInMicroMips, {  }, },
3967  { 3751 /* eret */, Mips::ERET_MMR6, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMicroMips32r6, {  }, },
3968  { 3751 /* eret */, Mips::ERET_MM, Convert_NoOperands, Feature_InMicroMips, {  }, },
3969  { 3756 /* eretnc */, Mips::ERETNC, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r5|Feature_NotInMicroMips, {  }, },
3970  { 3756 /* eretnc */, Mips::ERETNC_MMR6, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMicroMips32r6, {  }, },
3971  { 3763 /* ext */, Mips::EXT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, Feature_HasStdEnc|Feature_HasMips32r2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
3972  { 3763 /* ext */, Mips::EXT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
3973  { 3767 /* extp */, Mips::EXTP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
3974  { 3767 /* extp */, Mips::EXTP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
3975  { 3772 /* extpdp */, Mips::EXTPDP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
3976  { 3772 /* extpdp */, Mips::EXTPDP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
3977  { 3779 /* extpdpv */, Mips::EXTPDPV_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
3978  { 3779 /* extpdpv */, Mips::EXTPDPV, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
3979  { 3787 /* extpv */, Mips::EXTPV_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
3980  { 3787 /* extpv */, Mips::EXTPV, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
3981  { 3793 /* extr.w */, Mips::EXTR_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
3982  { 3793 /* extr.w */, Mips::EXTR_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
3983  { 3800 /* extr_r.w */, Mips::EXTR_R_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
3984  { 3800 /* extr_r.w */, Mips::EXTR_R_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
3985  { 3809 /* extr_rs.w */, Mips::EXTR_RS_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
3986  { 3809 /* extr_rs.w */, Mips::EXTR_RS_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
3987  { 3819 /* extr_s.h */, Mips::EXTR_S_H_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
3988  { 3819 /* extr_s.h */, Mips::EXTR_S_H, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
3989  { 3828 /* extrv.w */, Mips::EXTRV_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
3990  { 3828 /* extrv.w */, Mips::EXTRV_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
3991  { 3836 /* extrv_r.w */, Mips::EXTRV_R_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
3992  { 3836 /* extrv_r.w */, Mips::EXTRV_R_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
3993  { 3846 /* extrv_rs.w */, Mips::EXTRV_RS_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
3994  { 3846 /* extrv_rs.w */, Mips::EXTRV_RS_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
3995  { 3857 /* extrv_s.h */, Mips::EXTRV_S_H_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
3996  { 3857 /* extrv_s.h */, Mips::EXTRV_S_H, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
3997  { 3867 /* exts */, Mips::EXTS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
3998  { 3867 /* exts */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, },
3999  { 3867 /* exts */, Mips::EXTS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
4000  { 3867 /* exts */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, },
4001  { 3872 /* exts32 */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
4002  { 3872 /* exts32 */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
4003  { 3879 /* fadd.d */, Mips::FADD_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4004  { 3886 /* fadd.w */, Mips::FADD_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4005  { 3893 /* fcaf.d */, Mips::FCAF_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4006  { 3900 /* fcaf.w */, Mips::FCAF_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4007  { 3907 /* fceq.d */, Mips::FCEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4008  { 3914 /* fceq.w */, Mips::FCEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4009  { 3921 /* fclass.d */, Mips::FCLASS_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4010  { 3930 /* fclass.w */, Mips::FCLASS_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4011  { 3939 /* fcle.d */, Mips::FCLE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4012  { 3946 /* fcle.w */, Mips::FCLE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4013  { 3953 /* fclt.d */, Mips::FCLT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4014  { 3960 /* fclt.w */, Mips::FCLT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4015  { 3967 /* fcne.d */, Mips::FCNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4016  { 3974 /* fcne.w */, Mips::FCNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4017  { 3981 /* fcor.d */, Mips::FCOR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4018  { 3988 /* fcor.w */, Mips::FCOR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4019  { 3995 /* fcueq.d */, Mips::FCUEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4020  { 4003 /* fcueq.w */, Mips::FCUEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4021  { 4011 /* fcule.d */, Mips::FCULE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4022  { 4019 /* fcule.w */, Mips::FCULE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4023  { 4027 /* fcult.d */, Mips::FCULT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4024  { 4035 /* fcult.w */, Mips::FCULT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4025  { 4043 /* fcun.d */, Mips::FCUN_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4026  { 4050 /* fcun.w */, Mips::FCUN_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4027  { 4057 /* fcune.d */, Mips::FCUNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4028  { 4065 /* fcune.w */, Mips::FCUNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4029  { 4073 /* fdiv.d */, Mips::FDIV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4030  { 4080 /* fdiv.w */, Mips::FDIV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4031  { 4087 /* fexdo.h */, Mips::FEXDO_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4032  { 4095 /* fexdo.w */, Mips::FEXDO_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4033  { 4103 /* fexp2.d */, Mips::FEXP2_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4034  { 4111 /* fexp2.w */, Mips::FEXP2_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4035  { 4119 /* fexupl.d */, Mips::FEXUPL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4036  { 4128 /* fexupl.w */, Mips::FEXUPL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4037  { 4137 /* fexupr.d */, Mips::FEXUPR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4038  { 4146 /* fexupr.w */, Mips::FEXUPR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4039  { 4155 /* ffint_s.d */, Mips::FFINT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4040  { 4165 /* ffint_s.w */, Mips::FFINT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4041  { 4175 /* ffint_u.d */, Mips::FFINT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4042  { 4185 /* ffint_u.w */, Mips::FFINT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4043  { 4195 /* ffql.d */, Mips::FFQL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4044  { 4202 /* ffql.w */, Mips::FFQL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4045  { 4209 /* ffqr.d */, Mips::FFQR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4046  { 4216 /* ffqr.w */, Mips::FFQR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4047  { 4223 /* fill.b */, Mips::FILL_B, Convert__MSA128AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_GPR32AsmReg }, },
4048  { 4230 /* fill.d */, Mips::FILL_D, Convert__MSA128AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, { MCK_MSA128AsmReg, MCK_GPR64AsmReg }, },
4049  { 4237 /* fill.h */, Mips::FILL_H, Convert__MSA128AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_GPR32AsmReg }, },
4050  { 4244 /* fill.w */, Mips::FILL_W, Convert__MSA128AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_GPR32AsmReg }, },
4051  { 4251 /* flog2.d */, Mips::FLOG2_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4052  { 4259 /* flog2.w */, Mips::FLOG2_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4053  { 4267 /* floor.l.d */, Mips::FLOOR_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
4054  { 4267 /* floor.l.d */, Mips::FLOOR_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
4055  { 4277 /* floor.l.s */, Mips::FLOOR_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
4056  { 4277 /* floor.l.s */, Mips::FLOOR_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
4057  { 4287 /* floor.w.d */, Mips::FLOOR_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
4058  { 4287 /* floor.w.d */, Mips::FLOOR_W_D_MMR6, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
4059  { 4287 /* floor.w.d */, Mips::FLOOR_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
4060  { 4297 /* floor.w.s */, Mips::FLOOR_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
4061  { 4297 /* floor.w.s */, Mips::FLOOR_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
4062  { 4297 /* floor.w.s */, Mips::FLOOR_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
4063  { 4307 /* fmadd.d */, Mips::FMADD_D, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4064  { 4315 /* fmadd.w */, Mips::FMADD_W, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4065  { 4323 /* fmax.d */, Mips::FMAX_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4066  { 4330 /* fmax.w */, Mips::FMAX_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4067  { 4337 /* fmax_a.d */, Mips::FMAX_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4068  { 4346 /* fmax_a.w */, Mips::FMAX_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4069  { 4355 /* fmin.d */, Mips::FMIN_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4070  { 4362 /* fmin.w */, Mips::FMIN_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4071  { 4369 /* fmin_a.d */, Mips::FMIN_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4072  { 4378 /* fmin_a.w */, Mips::FMIN_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4073  { 4387 /* fmsub.d */, Mips::FMSUB_D, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4074  { 4395 /* fmsub.w */, Mips::FMSUB_W, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4075  { 4403 /* fmul.d */, Mips::FMUL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4076  { 4410 /* fmul.w */, Mips::FMUL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4077  { 4417 /* frcp.d */, Mips::FRCP_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4078  { 4424 /* frcp.w */, Mips::FRCP_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4079  { 4431 /* frint.d */, Mips::FRINT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4080  { 4439 /* frint.w */, Mips::FRINT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4081  { 4447 /* frsqrt.d */, Mips::FRSQRT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4082  { 4456 /* frsqrt.w */, Mips::FRSQRT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4083  { 4465 /* fsaf.d */, Mips::FSAF_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4084  { 4472 /* fsaf.w */, Mips::FSAF_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4085  { 4479 /* fseq.d */, Mips::FSEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4086  { 4486 /* fseq.w */, Mips::FSEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4087  { 4493 /* fsle.d */, Mips::FSLE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4088  { 4500 /* fsle.w */, Mips::FSLE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4089  { 4507 /* fslt.d */, Mips::FSLT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4090  { 4514 /* fslt.w */, Mips::FSLT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4091  { 4521 /* fsne.d */, Mips::FSNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4092  { 4528 /* fsne.w */, Mips::FSNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4093  { 4535 /* fsor.d */, Mips::FSOR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4094  { 4542 /* fsor.w */, Mips::FSOR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4095  { 4549 /* fsqrt.d */, Mips::FSQRT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4096  { 4557 /* fsqrt.w */, Mips::FSQRT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4097  { 4565 /* fsub.d */, Mips::FSUB_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4098  { 4572 /* fsub.w */, Mips::FSUB_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4099  { 4579 /* fsueq.d */, Mips::FSUEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4100  { 4587 /* fsueq.w */, Mips::FSUEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4101  { 4595 /* fsule.d */, Mips::FSULE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4102  { 4603 /* fsule.w */, Mips::FSULE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4103  { 4611 /* fsult.d */, Mips::FSULT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4104  { 4619 /* fsult.w */, Mips::FSULT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4105  { 4627 /* fsun.d */, Mips::FSUN_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4106  { 4634 /* fsun.w */, Mips::FSUN_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4107  { 4641 /* fsune.d */, Mips::FSUNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4108  { 4649 /* fsune.w */, Mips::FSUNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4109  { 4657 /* ftint_s.d */, Mips::FTINT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4110  { 4667 /* ftint_s.w */, Mips::FTINT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4111  { 4677 /* ftint_u.d */, Mips::FTINT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4112  { 4687 /* ftint_u.w */, Mips::FTINT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4113  { 4697 /* ftq.h */, Mips::FTQ_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4114  { 4703 /* ftq.w */, Mips::FTQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4115  { 4709 /* ftrunc_s.d */, Mips::FTRUNC_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4116  { 4720 /* ftrunc_s.w */, Mips::FTRUNC_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4117  { 4731 /* ftrunc_u.d */, Mips::FTRUNC_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4118  { 4742 /* ftrunc_u.w */, Mips::FTRUNC_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4119  { 4753 /* hadd_s.d */, Mips::HADD_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4120  { 4762 /* hadd_s.h */, Mips::HADD_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4121  { 4771 /* hadd_s.w */, Mips::HADD_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4122  { 4780 /* hadd_u.d */, Mips::HADD_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4123  { 4789 /* hadd_u.h */, Mips::HADD_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4124  { 4798 /* hadd_u.w */, Mips::HADD_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4125  { 4807 /* hsub_s.d */, Mips::HSUB_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4126  { 4816 /* hsub_s.h */, Mips::HSUB_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4127  { 4825 /* hsub_s.w */, Mips::HSUB_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4128  { 4834 /* hsub_u.d */, Mips::HSUB_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4129  { 4843 /* hsub_u.h */, Mips::HSUB_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4130  { 4852 /* hsub_u.w */, Mips::HSUB_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4131  { 4861 /* ilvev.b */, Mips::ILVEV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4132  { 4869 /* ilvev.d */, Mips::ILVEV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4133  { 4877 /* ilvev.h */, Mips::ILVEV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4134  { 4885 /* ilvev.w */, Mips::ILVEV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4135  { 4893 /* ilvl.b */, Mips::ILVL_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4136  { 4900 /* ilvl.d */, Mips::ILVL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4137  { 4907 /* ilvl.h */, Mips::ILVL_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4138  { 4914 /* ilvl.w */, Mips::ILVL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4139  { 4921 /* ilvod.b */, Mips::ILVOD_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4140  { 4929 /* ilvod.d */, Mips::ILVOD_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4141  { 4937 /* ilvod.h */, Mips::ILVOD_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4142  { 4945 /* ilvod.w */, Mips::ILVOD_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4143  { 4953 /* ilvr.b */, Mips::ILVR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4144  { 4960 /* ilvr.d */, Mips::ILVR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4145  { 4967 /* ilvr.h */, Mips::ILVR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4146  { 4974 /* ilvr.w */, Mips::ILVR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4147  { 4981 /* ins */, Mips::INS, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Imm1_3__Tie0, Feature_HasStdEnc|Feature_HasMips32r2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_Imm }, },
4148  { 4981 /* ins */, Mips::INS_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Imm1_3__Tie0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_Imm }, },
4149  { 4985 /* insert.b */, Mips::INSERT_B, Convert__MSA128AsmReg1_0__Tie0__GPR32AsmReg1_4__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_Imm, MCK__93_, MCK_GPR32AsmReg }, },
4150  { 4994 /* insert.d */, Mips::INSERT_D, Convert__MSA128AsmReg1_0__Tie0__GPR64AsmReg1_4__Imm1_2, Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, { MCK_MSA128AsmReg, MCK__91_, MCK_Imm, MCK__93_, MCK_GPR64AsmReg }, },
4151  { 5003 /* insert.h */, Mips::INSERT_H, Convert__MSA128AsmReg1_0__Tie0__GPR32AsmReg1_4__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_Imm, MCK__93_, MCK_GPR32AsmReg }, },
4152  { 5012 /* insert.w */, Mips::INSERT_W, Convert__MSA128AsmReg1_0__Tie0__GPR32AsmReg1_4__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_Imm, MCK__93_, MCK_GPR32AsmReg }, },
4153  { 5021 /* insv */, Mips::INSV_MM, Convert__GPR32AsmReg1_0__Tie0__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4154  { 5021 /* insv */, Mips::INSV, Convert__GPR32AsmReg1_0__Tie0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4155  { 5026 /* insve.b */, Mips::INSVE_B, Convert__MSA128AsmReg1_0__Tie0__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, },
4156  { 5034 /* insve.d */, Mips::INSVE_D, Convert__MSA128AsmReg1_0__Tie0__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, },
4157  { 5042 /* insve.h */, Mips::INSVE_H, Convert__MSA128AsmReg1_0__Tie0__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, },
4158  { 5050 /* insve.w */, Mips::INSVE_W, Convert__MSA128AsmReg1_0__Tie0__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, },
4159  { 5058 /* j */, Mips::JR, Convert__GPR32AsmReg1_0, 0, { MCK_GPR32AsmReg }, },
4160  { 5058 /* j */, Mips::J_MM, Convert__Imm1_0, Feature_InMicroMips, { MCK_Imm }, },
4161  { 5058 /* j */, Mips::J, Convert__JumpTarget1_0, Feature_HasStdEnc, { MCK_JumpTarget }, },
4162  { 5060 /* jal */, Mips::JalOneReg, Convert__GPR32AsmReg1_0, 0, { MCK_GPR32AsmReg }, },
4163  { 5060 /* jal */, Mips::JAL_MM, Convert__Imm1_0, Feature_InMicroMips, { MCK_Imm }, },
4164  { 5060 /* jal */, Mips::JAL, Convert__JumpTarget1_0, Feature_HasStdEnc, { MCK_JumpTarget }, },
4165  { 5060 /* jal */, Mips::JalTwoReg, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4166  { 5064 /* jalr */, Mips::JALR16_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
4167  { 5064 /* jalr */, Mips::JALRC16_MMR6, Convert__GPR32AsmReg1_0, Feature_HasMicroMips32r6, { MCK_GPR32AsmReg }, },
4168  { 5064 /* jalr */, Mips::JALR, Convert__regRA__GPR32AsmReg1_0, Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
4169  { 5064 /* jalr */, Mips::JALR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4170  { 5064 /* jalr */, Mips::JALR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4171  { 5069 /* jalr.hb */, Mips::JALR_HB, Convert__regRA__GPR32AsmReg1_0, Feature_HasMips32, { MCK_GPR32AsmReg }, },
4172  { 5069 /* jalr.hb */, Mips::JALR_HB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4173  { 5077 /* jalrc */, Mips::JumpLinkReg16, Convert__Reg1_0, Feature_InMips16Mode, { MCK_CPU16Regs }, },
4174  { 5083 /* jalrs */, Mips::JALRS_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4175  { 5089 /* jalrs16 */, Mips::JALRS16_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, },
4176  { 5097 /* jals */, Mips::JALS_MM, Convert__Imm1_0, Feature_InMicroMips, { MCK_Imm }, },
4177  { 5102 /* jalx */, Mips::JALX, Convert__JumpTarget1_0, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_JumpTarget }, },
4178  { 5102 /* jalx */, Mips::JALX_MM, Convert__JumpTarget1_0, Feature_InMicroMips, { MCK_JumpTarget }, },
4179  { 5107 /* jialc */, Mips::JIALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
4180  { 5107 /* jialc */, Mips::JIALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
4181  { 5113 /* jic */, Mips::JIC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
4182  { 5113 /* jic */, Mips::JIC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
4183  { 5117 /* jr */, Mips::JrRa16, Convert_NoOperands, Feature_InMips16Mode, { MCK_CPURAReg }, },
4184  { 5117 /* jr */, Mips::JR, Convert__GPR32AsmReg1_0, Feature_HasStdEnc, { MCK_GPR32AsmReg }, },
4185  { 5117 /* jr */, Mips::JR_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, },
4186  { 5117 /* jr */, Mips::JALR, Convert__regZERO__GPR32AsmReg1_0, Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
4187  { 5117 /* jr */, Mips::JALR64, Convert__regZERO_64__GPR64AsmReg1_0, Feature_HasMips64r6, { MCK_GPR64AsmReg }, },
4188  { 5120 /* jr.hb */, Mips::JR_HB, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg }, },
4189  { 5120 /* jr.hb */, Mips::JR_HB_R6, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
4190  { 5126 /* jr16 */, Mips::JR16_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, },
4191  { 5131 /* jraddiusp */, Mips::JRADDIUSP, Convert__UImm5Lsl21_0, Feature_InMicroMips, { MCK_UImm5Lsl2 }, },
4192  { 5141 /* jrc */, Mips::JrcRa16, Convert_NoOperands, Feature_InMips16Mode, { MCK_CPURAReg }, },
4193  { 5141 /* jrc */, Mips::JrcRx16, Convert__Reg1_0, Feature_InMips16Mode, { MCK_CPU16Regs }, },
4194  { 5141 /* jrc */, Mips::JRC16_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, },
4195  { 5145 /* jrc16 */, Mips::JRC16_MMR6, Convert__GPR32AsmReg1_0, Feature_HasMicroMips32r6, { MCK_GPR32AsmReg }, },
4196  { 5151 /* jrcaddiusp */, Mips::JRCADDIUSP_MMR6, Convert__UImm5Lsl21_0, Feature_HasMicroMips32r6, { MCK_UImm5Lsl2 }, },
4197  { 5162 /* la */, Mips::LoadAddrImm32, Convert__GPR32AsmReg1_0__Imm1_1, 0, { MCK_GPR32AsmReg, MCK_Imm }, },
4198  { 5162 /* la */, Mips::LoadAddrReg32, Convert__GPR32AsmReg1_0__Mem2_1, 0, { MCK_GPR32AsmReg, MCK_Mem }, },
4199  { 5165 /* lb */, Mips::LB_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
4200  { 5165 /* lb */, Mips::LB, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_Mem }, },
4201  { 5165 /* lb */, Mips::LB_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
4202  { 5168 /* lbe */, Mips::LBE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
4203  { 5168 /* lbe */, Mips::LBE_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
4204  { 5168 /* lbe */, Mips::LBE_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
4205  { 5172 /* lbu */, Mips::LBU_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
4206  { 5172 /* lbu */, Mips::LBu, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_Mem }, },
4207  { 5172 /* lbu */, Mips::LBu_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
4208  { 5176 /* lbu16 */, Mips::LBU16_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMem }, },
4209  { 5182 /* lbue */, Mips::LBuE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
4210  { 5182 /* lbue */, Mips::LBUE_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
4211  { 5182 /* lbue */, Mips::LBuE_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
4212  { 5187 /* lbux */, Mips::LBUX_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
4213  { 5187 /* lbux */, Mips::LBUX, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
4214  { 5192 /* ld */, Mips::LD, Convert__GPR64AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMips3, { MCK_GPR64AsmReg, MCK_Mem }, },
4215  { 5195 /* ld.b */, Mips::LD_B, Convert__MSA128AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_Mem }, },
4216  { 5200 /* ld.d */, Mips::LD_D, Convert__MSA128AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_Mem }, },
4217  { 5205 /* ld.h */, Mips::LD_H, Convert__MSA128AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_Mem }, },
4218  { 5210 /* ld.w */, Mips::LD_W, Convert__MSA128AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_Mem }, },
4219  { 5215 /* ldc1 */, Mips::LDC1, Convert__AFGR64AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_Mem }, },
4220  { 5215 /* ldc1 */, Mips::LDC164, Convert__FGR64AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_Mem }, },
4221  { 5220 /* ldc2 */, Mips::LDC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
4222  { 5220 /* ldc2 */, Mips::LDC2, Convert__COP2AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_Mem }, },
4223  { 5225 /* ldc3 */, Mips::LDC3, Convert__COP3AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, },
4224  { 5230 /* ldi.b */, Mips::LDI_B, Convert__MSA128AsmReg1_0__Imm1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_Imm }, },
4225  { 5236 /* ldi.d */, Mips::LDI_D, Convert__MSA128AsmReg1_0__Imm1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_Imm }, },
4226  { 5242 /* ldi.h */, Mips::LDI_H, Convert__MSA128AsmReg1_0__Imm1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_Imm }, },
4227  { 5248 /* ldi.w */, Mips::LDI_W, Convert__MSA128AsmReg1_0__Imm1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_Imm }, },
4228  { 5254 /* ldl */, Mips::LDL, Convert__GPR64AsmReg1_0__Mem2_1__Tie0, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, },
4229  { 5258 /* ldpc */, Mips::LDPC, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
4230  { 5263 /* ldr */, Mips::LDR, Convert__GPR64AsmReg1_0__Mem2_1__Tie0, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, },
4231  { 5267 /* ldxc1 */, Mips::LDXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
4232  { 5267 /* ldxc1 */, Mips::LDXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
4233  { 5273 /* lh */, Mips::LH, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_Mem }, },
4234  { 5273 /* lh */, Mips::LH_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
4235  { 5276 /* lhe */, Mips::LHE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
4236  { 5276 /* lhe */, Mips::LHE_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
4237  { 5280 /* lhu */, Mips::LHu, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_Mem }, },
4238  { 5280 /* lhu */, Mips::LHu_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
4239  { 5284 /* lhu16 */, Mips::LHU16_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMem }, },
4240  { 5290 /* lhue */, Mips::LHuE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
4241  { 5290 /* lhue */, Mips::LHuE_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
4242  { 5295 /* lhx */, Mips::LHX_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
4243  { 5295 /* lhx */, Mips::LHX, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
4244  { 5299 /* li */, Mips::LiRxImmX16, Convert__Reg1_0__Imm1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_Imm }, },
4245  { 5299 /* li */, Mips::LoadImm32, Convert__GPR32AsmReg1_0__Imm1_1, 0, { MCK_GPR32AsmReg, MCK_Imm }, },
4246  { 5299 /* li */, Mips::LiRxImm16, Convert__Reg1_0__Imm1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_Imm, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
4247  { 5302 /* li16 */, Mips::LI16_MM, Convert__GPRMM16AsmReg1_0__Imm1_1, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_Imm }, },
4248  { 5302 /* li16 */, Mips::LI16_MMR6, Convert__GPRMM16AsmReg1_0__Imm1_1, Feature_HasMicroMips32r6, { MCK_GPRMM16AsmReg, MCK_Imm }, },
4249  { 5307 /* ll */, Mips::LL_R6, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
4250  { 5307 /* ll */, Mips::LL, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
4251  { 5307 /* ll */, Mips::LL_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
4252  { 5310 /* lld */, Mips::LLD_R6, Convert__GPR64AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR64AsmReg, MCK_MemOffsetSimm9 }, },
4253  { 5310 /* lld */, Mips::LLD, Convert__GPR64AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, },
4254  { 5314 /* lle */, Mips::LLE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
4255  { 5314 /* lle */, Mips::LLE_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
4256  { 5314 /* lle */, Mips::LLE_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
4257  { 5318 /* lsa */, Mips::LSA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_1 }, },
4258  { 5318 /* lsa */, Mips::LSA_MMR6, Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_1 }, },
4259  { 5318 /* lsa */, Mips::LSA_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_1 }, },
4260  { 5322 /* lui */, Mips::LUI_MMR6, Convert__GPR32AsmReg1_0__UImm161_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
4261  { 5322 /* lui */, Mips::LUi, Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_UImm16_Relaxed }, },
4262  { 5322 /* lui */, Mips::LUi_MM, Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_UImm16_Relaxed }, },
4263  { 5326 /* luxc1 */, Mips::LUXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
4264  { 5326 /* luxc1 */, Mips::LUXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
4265  { 5332 /* lw */, Mips::LwRxPcTcpX16, Convert__Reg1_0__Imm1_1__imm_95_0, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_Imm }, },
4266  { 5332 /* lw */, Mips::LWSP_MM, Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MicroMipsMemSP }, },
4267  { 5332 /* lw */, Mips::LW, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
4268  { 5332 /* lw */, Mips::LW_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
4269  { 5332 /* lw */, Mips::LW_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
4270  { 5332 /* lw */, Mips::LWGP_MM, Convert__GPRMM16AsmReg1_0__Reg1_1__Imm1_2, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_CPU16Regs, MCK_Imm }, },
4271  { 5332 /* lw */, Mips::LwRxSpImmX16, Convert__Reg1_0__Reg1_3__Imm1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_Imm, MCK__40_, MCK_CPUSPReg, MCK__41__59_ }, },
4272  { 5332 /* lw */, Mips::LwRxPcTcp16, Convert__Reg1_0__Imm1_1__imm_95_0, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_Imm, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
4273  { 5335 /* lw16 */, Mips::LW16_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMem }, },
4274  { 5340 /* lwc1 */, Mips::LWC1, Convert__FGR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_Mem }, },
4275  { 5345 /* lwc2 */, Mips::LWC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
4276  { 5345 /* lwc2 */, Mips::LWC2, Convert__COP2AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_Mem }, },
4277  { 5350 /* lwc3 */, Mips::LWC3, Convert__COP3AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, },
4278  { 5355 /* lwe */, Mips::LWE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
4279  { 5355 /* lwe */, Mips::LWE_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
4280  { 5355 /* lwe */, Mips::LWE_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
4281  { 5359 /* lwl */, Mips::LWL, Convert__GPR32AsmReg1_0__Mem2_1__Tie0, Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
4282  { 5359 /* lwl */, Mips::LWL_MM, Convert__GPR32AsmReg1_0__Mem2_1__Tie0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
4283  { 5363 /* lwle */, Mips::LWLE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
4284  { 5363 /* lwle */, Mips::LWLE_MM, Convert__GPR32AsmReg1_0__Mem2_1__Tie0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
4285  { 5368 /* lwm */, Mips::LWM_MM, Convert__RegList1_0__Mem2_1, Feature_InMicroMips, { MCK_RegList, MCK_Mem }, },
4286  { 5372 /* lwm16 */, Mips::LWM16_MM, Convert__RegList161_0__MemOffsetUimm42_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, },
4287  { 5372 /* lwm16 */, Mips::LWM16_MMR6, Convert__RegList161_0__MemOffsetUimm42_1, Feature_HasMicroMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, },
4288  { 5378 /* lwm32 */, Mips::LWM32_MM, Convert__RegList1_0__Mem2_1, Feature_InMicroMips, { MCK_RegList, MCK_Mem }, },
4289  { 5384 /* lwp */, Mips::LWP_MM, Convert__RegPair2_0__Mem2_1, Feature_InMicroMips, { MCK_RegPair, MCK_Mem }, },
4290  { 5388 /* lwpc */, Mips::LWPC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
4291  { 5388 /* lwpc */, Mips::LWPC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
4292  { 5393 /* lwr */, Mips::LWR, Convert__GPR32AsmReg1_0__Mem2_1__Tie0, Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
4293  { 5393 /* lwr */, Mips::LWR_MM, Convert__GPR32AsmReg1_0__Mem2_1__Tie0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
4294  { 5397 /* lwre */, Mips::LWRE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
4295  { 5397 /* lwre */, Mips::LWRE_MM, Convert__GPR32AsmReg1_0__Mem2_1__Tie0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
4296  { 5402 /* lwu */, Mips::LWU_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
4297  { 5402 /* lwu */, Mips::LWu, Convert__GPR64AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMips3, { MCK_GPR64AsmReg, MCK_Mem }, },
4298  { 5406 /* lwupc */, Mips::LWUPC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
4299  { 5412 /* lwx */, Mips::LWX_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
4300  { 5412 /* lwx */, Mips::LWX, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
4301  { 5416 /* lwxc1 */, Mips::LWXC1, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
4302  { 5422 /* lwxs */, Mips::LWXS_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
4303  { 5427 /* madd */, Mips::MADD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4304  { 5427 /* madd */, Mips::MADD_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4305  { 5427 /* madd */, Mips::MADD_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4306  { 5427 /* madd */, Mips::MADD_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4307  { 5432 /* madd.d */, Mips::MADD_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
4308  { 5432 /* madd.d */, Mips::MADD_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
4309  { 5439 /* madd.s */, Mips::MADD_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
4310  { 5446 /* madd_q.h */, Mips::MADD_Q_H, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4311  { 5455 /* madd_q.w */, Mips::MADD_Q_W, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4312  { 5464 /* maddf.d */, Mips::MADDF_D, Convert__FGR64AsmReg1_0__Tie0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
4313  { 5464 /* maddf.d */, Mips::MADDF_D_MMR6, Convert__FGR64AsmReg1_0__Tie0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
4314  { 5472 /* maddf.s */, Mips::MADDF_S, Convert__FGR32AsmReg1_0__Tie0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
4315  { 5472 /* maddf.s */, Mips::MADDF_S_MMR6, Convert__FGR32AsmReg1_0__Tie0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
4316  { 5480 /* maddr_q.h */, Mips::MADDR_Q_H, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4317  { 5490 /* maddr_q.w */, Mips::MADDR_Q_W, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4318  { 5500 /* maddu */, Mips::MADDU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4319  { 5500 /* maddu */, Mips::MADDU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4320  { 5500 /* maddu */, Mips::MADDU_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4321  { 5500 /* maddu */, Mips::MADDU_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4322  { 5506 /* maddv.b */, Mips::MADDV_B, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4323  { 5514 /* maddv.d */, Mips::MADDV_D, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4324  { 5522 /* maddv.h */, Mips::MADDV_H, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4325  { 5530 /* maddv.w */, Mips::MADDV_W, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4326  { 5538 /* maq_s.w.phl */, Mips::MAQ_S_W_PHL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4327  { 5538 /* maq_s.w.phl */, Mips::MAQ_S_W_PHL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4328  { 5550 /* maq_s.w.phr */, Mips::MAQ_S_W_PHR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4329  { 5550 /* maq_s.w.phr */, Mips::MAQ_S_W_PHR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4330  { 5562 /* maq_sa.w.phl */, Mips::MAQ_SA_W_PHL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4331  { 5562 /* maq_sa.w.phl */, Mips::MAQ_SA_W_PHL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4332  { 5575 /* maq_sa.w.phr */, Mips::MAQ_SA_W_PHR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4333  { 5575 /* maq_sa.w.phr */, Mips::MAQ_SA_W_PHR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4334  { 5588 /* max.d */, Mips::MAX_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
4335  { 5588 /* max.d */, Mips::MAX_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
4336  { 5594 /* max.s */, Mips::MAX_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
4337  { 5594 /* max.s */, Mips::MAX_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
4338  { 5600 /* max_a.b */, Mips::MAX_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4339  { 5608 /* max_a.d */, Mips::MAX_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4340  { 5616 /* max_a.h */, Mips::MAX_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4341  { 5624 /* max_a.w */, Mips::MAX_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4342  { 5632 /* max_s.b */, Mips::MAX_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4343  { 5640 /* max_s.d */, Mips::MAX_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4344  { 5648 /* max_s.h */, Mips::MAX_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4345  { 5656 /* max_s.w */, Mips::MAX_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4346  { 5664 /* max_u.b */, Mips::MAX_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4347  { 5672 /* max_u.d */, Mips::MAX_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4348  { 5680 /* max_u.h */, Mips::MAX_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4349  { 5688 /* max_u.w */, Mips::MAX_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4350  { 5696 /* maxa.d */, Mips::MAXA_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
4351  { 5696 /* maxa.d */, Mips::MAXA_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
4352  { 5703 /* maxa.s */, Mips::MAXA_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
4353  { 5703 /* maxa.s */, Mips::MAXA_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
4354  { 5710 /* maxi_s.b */, Mips::MAXI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
4355  { 5719 /* maxi_s.d */, Mips::MAXI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
4356  { 5728 /* maxi_s.h */, Mips::MAXI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
4357  { 5737 /* maxi_s.w */, Mips::MAXI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
4358  { 5746 /* maxi_u.b */, Mips::MAXI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
4359  { 5755 /* maxi_u.d */, Mips::MAXI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
4360  { 5764 /* maxi_u.h */, Mips::MAXI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
4361  { 5773 /* maxi_u.w */, Mips::MAXI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
4362  { 5782 /* mfc0 */, Mips::MFC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, 0, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
4363  { 5782 /* mfc0 */, Mips::MFC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__UImm161_2, Feature_HasStdEnc|Feature_HasMips32, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_UImm16 }, },
4364  { 5787 /* mfc1 */, Mips::MFC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
4365  { 5792 /* mfc2 */, Mips::MFC2, Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0, 0, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
4366  { 5792 /* mfc2 */, Mips::MFC2, Convert__GPR32AsmReg1_0__COP2AsmReg1_1__UImm161_2, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_COP2AsmReg, MCK_UImm16 }, },
4367  { 5797 /* mfhc1 */, Mips::MFHC1_D32, Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, },
4368  { 5797 /* mfhc1 */, Mips::MFHC1_D64, Convert__GPR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
4369  { 5803 /* mfhi */, Mips::Mfhi16, Convert__Reg1_0, Feature_InMips16Mode, { MCK_CPU16Regs }, },
4370  { 5803 /* mfhi */, Mips::MFHI, Convert__GPR32AsmReg1_0, Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
4371  { 5803 /* mfhi */, Mips::MFHI16_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, },
4372  { 5803 /* mfhi */, Mips::MFHI_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, },
4373  { 5803 /* mfhi */, Mips::MFHI_DSP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
4374  { 5803 /* mfhi */, Mips::MFHI_DSP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
4375  { 5808 /* mflo */, Mips::Mflo16, Convert__Reg1_0, Feature_InMips16Mode, { MCK_CPU16Regs }, },
4376  { 5808 /* mflo */, Mips::MFLO, Convert__GPR32AsmReg1_0, Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
4377  { 5808 /* mflo */, Mips::MFLO16_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, },
4378  { 5808 /* mflo */, Mips::MFLO_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, },
4379  { 5808 /* mflo */, Mips::MFLO_DSP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
4380  { 5808 /* mflo */, Mips::MFLO_DSP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
4381  { 5813 /* min.d */, Mips::MIN_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
4382  { 5813 /* min.d */, Mips::MIN_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
4383  { 5819 /* min.s */, Mips::MIN_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
4384  { 5819 /* min.s */, Mips::MIN_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
4385  { 5825 /* min_a.b */, Mips::MIN_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4386  { 5833 /* min_a.d */, Mips::MIN_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4387  { 5841 /* min_a.h */, Mips::MIN_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4388  { 5849 /* min_a.w */, Mips::MIN_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4389  { 5857 /* min_s.b */, Mips::MIN_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4390  { 5865 /* min_s.d */, Mips::MIN_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4391  { 5873 /* min_s.h */, Mips::MIN_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4392  { 5881 /* min_s.w */, Mips::MIN_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4393  { 5889 /* min_u.b */, Mips::MIN_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4394  { 5897 /* min_u.d */, Mips::MIN_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4395  { 5905 /* min_u.h */, Mips::MIN_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4396  { 5913 /* min_u.w */, Mips::MIN_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4397  { 5921 /* mina.d */, Mips::MINA_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
4398  { 5921 /* mina.d */, Mips::MINA_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
4399  { 5928 /* mina.s */, Mips::MINA_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
4400  { 5928 /* mina.s */, Mips::MINA_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
4401  { 5935 /* mini_s.b */, Mips::MINI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
4402  { 5944 /* mini_s.d */, Mips::MINI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
4403  { 5953 /* mini_s.h */, Mips::MINI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
4404  { 5962 /* mini_s.w */, Mips::MINI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
4405  { 5971 /* mini_u.b */, Mips::MINI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
4406  { 5980 /* mini_u.d */, Mips::MINI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
4407  { 5989 /* mini_u.h */, Mips::MINI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
4408  { 5998 /* mini_u.w */, Mips::MINI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
4409  { 6007 /* mod */, Mips::MOD_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4410  { 6007 /* mod */, Mips::MOD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4411  { 6007 /* mod */, Mips::MOD_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4412  { 6011 /* mod_s.b */, Mips::MOD_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4413  { 6019 /* mod_s.d */, Mips::MOD_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4414  { 6027 /* mod_s.h */, Mips::MOD_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4415  { 6035 /* mod_s.w */, Mips::MOD_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4416  { 6043 /* mod_u.b */, Mips::MOD_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4417  { 6051 /* mod_u.d */, Mips::MOD_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4418  { 6059 /* mod_u.h */, Mips::MOD_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4419  { 6067 /* mod_u.w */, Mips::MOD_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4420  { 6075 /* modsub */, Mips::MODSUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4421  { 6082 /* modu */, Mips::MODU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4422  { 6082 /* modu */, Mips::MODU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4423  { 6082 /* modu */, Mips::MODU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4424  { 6087 /* mov.d */, Mips::FMOV_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
4425  { 6087 /* mov.d */, Mips::FMOV_D_MMR6, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
4426  { 6087 /* mov.d */, Mips::FMOV_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
4427  { 6093 /* mov.s */, Mips::FMOV_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
4428  { 6093 /* mov.s */, Mips::FMOV_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
4429  { 6099 /* move */, Mips::MoveR3216, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_DSPR }, },
4430  { 6099 /* move */, Mips::Move32R16, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_DSPR, MCK_CPU16Regs }, },
4431  { 6099 /* move */, Mips::OR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4432  { 6099 /* move */, Mips::ADDu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4433  { 6099 /* move */, Mips::MOVE16_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4434  { 6099 /* move */, Mips::OR64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64, Feature_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
4435  { 6099 /* move */, Mips::DADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64, Feature_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
4436  { 6104 /* move.v */, Mips::MOVE_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4437  { 6111 /* move16 */, Mips::MOVE16_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4438  { 6118 /* movep */, Mips::MOVEP_MM, Convert__MovePRegPair2_0__GPRMM16AsmRegMoveP1_1__GPRMM16AsmRegMoveP1_2, Feature_InMicroMips, { MCK_MovePRegPair, MCK_GPRMM16AsmRegMoveP, MCK_GPRMM16AsmRegMoveP }, },
4439  { 6124 /* movf */, Mips::MOVF_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, },
4440  { 6124 /* movf */, Mips::MOVF_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, },
4441  { 6129 /* movf.d */, Mips::MOVF_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, },
4442  { 6129 /* movf.d */, Mips::MOVF_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FCCAsmReg }, },
4443  { 6136 /* movf.s */, Mips::MOVF_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, },
4444  { 6143 /* movn */, Mips::MOVN_I_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4445  { 6143 /* movn */, Mips::MOVN_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4446  { 6148 /* movn.d */, Mips::MOVN_I_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, },
4447  { 6148 /* movn.d */, Mips::MOVN_I_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_GPR32AsmReg }, },
4448  { 6155 /* movn.s */, Mips::MOVN_I_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, },
4449  { 6162 /* movt */, Mips::MOVT_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, },
4450  { 6162 /* movt */, Mips::MOVT_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, },
4451  { 6167 /* movt.d */, Mips::MOVT_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, },
4452  { 6167 /* movt.d */, Mips::MOVT_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FCCAsmReg }, },
4453  { 6174 /* movt.s */, Mips::MOVT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, },
4454  { 6181 /* movz */, Mips::MOVZ_I_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4455  { 6181 /* movz */, Mips::MOVZ_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4456  { 6186 /* movz.d */, Mips::MOVZ_I_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, },
4457  { 6186 /* movz.d */, Mips::MOVZ_I_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_GPR32AsmReg }, },
4458  { 6193 /* movz.s */, Mips::MOVZ_I_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, },
4459  { 6200 /* msub */, Mips::MSUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4460  { 6200 /* msub */, Mips::MSUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4461  { 6200 /* msub */, Mips::MSUB_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4462  { 6200 /* msub */, Mips::MSUB_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4463  { 6205 /* msub.d */, Mips::MSUB_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
4464  { 6205 /* msub.d */, Mips::MSUB_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
4465  { 6212 /* msub.s */, Mips::MSUB_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
4466  { 6219 /* msub_q.h */, Mips::MSUB_Q_H, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4467  { 6228 /* msub_q.w */, Mips::MSUB_Q_W, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4468  { 6237 /* msubf.d */, Mips::MSUBF_D, Convert__FGR64AsmReg1_0__Tie0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
4469  { 6237 /* msubf.d */, Mips::MSUBF_D_MMR6, Convert__FGR64AsmReg1_0__Tie0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
4470  { 6245 /* msubf.s */, Mips::MSUBF_S, Convert__FGR32AsmReg1_0__Tie0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
4471  { 6245 /* msubf.s */, Mips::MSUBF_S_MMR6, Convert__FGR32AsmReg1_0__Tie0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
4472  { 6253 /* msubr_q.h */, Mips::MSUBR_Q_H, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4473  { 6263 /* msubr_q.w */, Mips::MSUBR_Q_W, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4474  { 6273 /* msubu */, Mips::MSUBU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4475  { 6273 /* msubu */, Mips::MSUBU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4476  { 6273 /* msubu */, Mips::MSUBU_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4477  { 6273 /* msubu */, Mips::MSUBU_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4478  { 6279 /* msubv.b */, Mips::MSUBV_B, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4479  { 6287 /* msubv.d */, Mips::MSUBV_D, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4480  { 6295 /* msubv.h */, Mips::MSUBV_H, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4481  { 6303 /* msubv.w */, Mips::MSUBV_W, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4482  { 6311 /* mtc0 */, Mips::MTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, 0, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
4483  { 6311 /* mtc0 */, Mips::MTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__UImm161_2, Feature_HasStdEnc|Feature_HasMips32, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_UImm16 }, },
4484  { 6316 /* mtc1 */, Mips::MTC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
4485  { 6321 /* mtc2 */, Mips::MTC2, Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0, 0, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
4486  { 6321 /* mtc2 */, Mips::MTC2, Convert__COP2AsmReg1_1__GPR32AsmReg1_0__UImm161_2, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_COP2AsmReg, MCK_UImm16 }, },
4487  { 6326 /* mthc1 */, Mips::MTHC1_D32, Convert__AFGR64AsmReg1_1__Tie0__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, },
4488  { 6326 /* mthc1 */, Mips::MTHC1_D64, Convert__FGR64AsmReg1_1__Tie0__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
4489  { 6332 /* mthi */, Mips::MTHI, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg }, },
4490  { 6332 /* mthi */, Mips::MTHI_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, },
4491  { 6332 /* mthi */, Mips::MTHI_DSP_MM, Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_HI32DSPAsmReg }, },
4492  { 6332 /* mthi */, Mips::MTHI_DSP, Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_HI32DSPAsmReg }, },
4493  { 6337 /* mthlip */, Mips::MTHLIP_MM, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
4494  { 6337 /* mthlip */, Mips::MTHLIP, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
4495  { 6344 /* mtlo */, Mips::MTLO, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg }, },
4496  { 6344 /* mtlo */, Mips::MTLO_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, },
4497  { 6344 /* mtlo */, Mips::MTLO_DSP_MM, Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_LO32DSPAsmReg }, },
4498  { 6344 /* mtlo */, Mips::MTLO_DSP, Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_LO32DSPAsmReg }, },
4499  { 6349 /* mtm0 */, Mips::MTM0, Convert__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, },
4500  { 6354 /* mtm1 */, Mips::MTM1, Convert__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, },
4501  { 6359 /* mtm2 */, Mips::MTM2, Convert__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, },
4502  { 6364 /* mtp0 */, Mips::MTP0, Convert__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, },
4503  { 6369 /* mtp1 */, Mips::MTP1, Convert__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, },
4504  { 6374 /* mtp2 */, Mips::MTP2, Convert__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, },
4505  { 6379 /* muh */, Mips::MUH_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4506  { 6379 /* muh */, Mips::MUH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4507  { 6379 /* muh */, Mips::MUH_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4508  { 6383 /* muhu */, Mips::MUHU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4509  { 6383 /* muhu */, Mips::MUHU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4510  { 6383 /* muhu */, Mips::MUHU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4511  { 6388 /* mul */, Mips::MUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4512  { 6388 /* mul */, Mips::MUL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4513  { 6388 /* mul */, Mips::MUL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4514  { 6388 /* mul */, Mips::MUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4515  { 6388 /* mul */, Mips::MUL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4516  { 6388 /* mul */, Mips::MUL_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4517  { 6388 /* mul */, Mips::MUL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4518  { 6392 /* mul.d */, Mips::FMUL_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
4519  { 6392 /* mul.d */, Mips::FMUL_D_MMR6, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_2__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
4520  { 6392 /* mul.d */, Mips::FMUL_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
4521  { 6398 /* mul.ph */, Mips::MUL_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4522  { 6398 /* mul.ph */, Mips::MUL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4523  { 6405 /* mul.s */, Mips::FMUL_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
4524  { 6405 /* mul.s */, Mips::FMUL_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
4525  { 6411 /* mul_q.h */, Mips::MUL_Q_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4526  { 6419 /* mul_q.w */, Mips::MUL_Q_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4527  { 6427 /* mul_s.ph */, Mips::MUL_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4528  { 6427 /* mul_s.ph */, Mips::MUL_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4529  { 6436 /* muleq_s.w.phl */, Mips::MULEQ_S_W_PHL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4530  { 6436 /* muleq_s.w.phl */, Mips::MULEQ_S_W_PHL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4531  { 6450 /* muleq_s.w.phr */, Mips::MULEQ_S_W_PHR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4532  { 6450 /* muleq_s.w.phr */, Mips::MULEQ_S_W_PHR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4533  { 6464 /* muleu_s.ph.qbl */, Mips::MULEU_S_PH_QBL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4534  { 6464 /* muleu_s.ph.qbl */, Mips::MULEU_S_PH_QBL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4535  { 6479 /* muleu_s.ph.qbr */, Mips::MULEU_S_PH_QBR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4536  { 6479 /* muleu_s.ph.qbr */, Mips::MULEU_S_PH_QBR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4537  { 6494 /* mulq_rs.ph */, Mips::MULQ_RS_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4538  { 6494 /* mulq_rs.ph */, Mips::MULQ_RS_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4539  { 6505 /* mulq_rs.w */, Mips::MULQ_RS_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4540  { 6505 /* mulq_rs.w */, Mips::MULQ_RS_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4541  { 6515 /* mulq_s.ph */, Mips::MULQ_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4542  { 6515 /* mulq_s.ph */, Mips::MULQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4543  { 6525 /* mulq_s.w */, Mips::MULQ_S_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4544  { 6525 /* mulq_s.w */, Mips::MULQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4545  { 6534 /* mulr_q.h */, Mips::MULR_Q_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4546  { 6543 /* mulr_q.w */, Mips::MULR_Q_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4547  { 6552 /* mulsa.w.ph */, Mips::MULSA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4548  { 6563 /* mulsaq_s.w.ph */, Mips::MULSAQ_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4549  { 6577 /* mult */, Mips::MULT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4550  { 6577 /* mult */, Mips::MULT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4551  { 6577 /* mult */, Mips::MULT_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4552  { 6577 /* mult */, Mips::MULT_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4553  { 6582 /* multu */, Mips::MULTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4554  { 6582 /* multu */, Mips::MULTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4555  { 6582 /* multu */, Mips::MULTU_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4556  { 6582 /* multu */, Mips::MULTU_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4557  { 6588 /* mulu */, Mips::MULU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4558  { 6588 /* mulu */, Mips::MULU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4559  { 6588 /* mulu */, Mips::MULU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4560  { 6593 /* mulv.b */, Mips::MULV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4561  { 6600 /* mulv.d */, Mips::MULV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4562  { 6607 /* mulv.h */, Mips::MULV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4563  { 6614 /* mulv.w */, Mips::MULV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4564  { 6621 /* neg */, Mips::NegRxRy16, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
4565  { 6621 /* neg */, Mips::SUB, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4566  { 6625 /* neg.d */, Mips::FNEG_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
4567  { 6625 /* neg.d */, Mips::FNEG_D_MMR6, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
4568  { 6625 /* neg.d */, Mips::FNEG_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
4569  { 6631 /* neg.s */, Mips::FNEG_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
4570  { 6631 /* neg.s */, Mips::FNEG_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
4571  { 6637 /* negu */, Mips::SUBu, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, 0, { MCK_GPR32AsmReg }, },
4572  { 6637 /* negu */, Mips::SUBu, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4573  { 6642 /* nloc.b */, Mips::NLOC_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4574  { 6649 /* nloc.d */, Mips::NLOC_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4575  { 6656 /* nloc.h */, Mips::NLOC_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4576  { 6663 /* nloc.w */, Mips::NLOC_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4577  { 6670 /* nlzc.b */, Mips::NLZC_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4578  { 6677 /* nlzc.d */, Mips::NLZC_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4579  { 6684 /* nlzc.h */, Mips::NLZC_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4580  { 6691 /* nlzc.w */, Mips::NLZC_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4581  { 6698 /* nmadd.d */, Mips::NMADD_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
4582  { 6698 /* nmadd.d */, Mips::NMADD_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
4583  { 6706 /* nmadd.s */, Mips::NMADD_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
4584  { 6714 /* nmsub.d */, Mips::NMSUB_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
4585  { 6714 /* nmsub.d */, Mips::NMSUB_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
4586  { 6722 /* nmsub.s */, Mips::NMSUB_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
4587  { 6730 /* nop */, Mips::SLL_MM, Convert__regZERO__regZERO__imm_95_0, Feature_InMicroMips, {  }, },
4588  { 6730 /* nop */, Mips::MOVE16_MM, Convert__regZERO__regZERO, Feature_InMicroMips, {  }, },
4589  { 6730 /* nop */, Mips::SLL_MMR6, Convert__regZERO__regZERO__imm_95_0, Feature_HasMicroMips32r6, {  }, },
4590  { 6730 /* nop */, Mips::SLL, Convert__regZERO__regZERO__imm_95_0, Feature_NotInMicroMips, {  }, },
4591  { 6734 /* nor */, Mips::NOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4592  { 6734 /* nor */, Mips::NOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4593  { 6734 /* nor */, Mips::NOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4594  { 6734 /* nor */, Mips::NOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4595  { 6734 /* nor */, Mips::NORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__Imm1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_Imm }, },
4596  { 6738 /* nor.v */, Mips::NOR_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4597  { 6744 /* nori.b */, Mips::NORI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
4598  { 6751 /* not */, Mips::NotRxRy16, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
4599  { 6751 /* not */, Mips::NOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4600  { 6755 /* not16 */, Mips::NOT16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
4601  { 6755 /* not16 */, Mips::NOT16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1, Feature_HasMicroMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
4602  { 6761 /* or */, Mips::OrRxRxRy16, Convert__Reg1_0__Tie0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
4603  { 6761 /* or */, Mips::OR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4604  { 6761 /* or */, Mips::OR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4605  { 6761 /* or */, Mips::OR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4606  { 6761 /* or */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__Imm1_1, 0, { MCK_GPR32AsmReg, MCK_Imm }, },
4607  { 6761 /* or */, Mips::OR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4608  { 6761 /* or */, Mips::OR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4609  { 6761 /* or */, Mips::OR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4610  { 6761 /* or */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__Imm1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_Imm }, },
4611  { 6764 /* or.v */, Mips::OR_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4612  { 6769 /* or16 */, Mips::OR16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0, Feature_InMicroMips|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
4613  { 6769 /* or16 */, Mips::OR16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
4614  { 6774 /* ori */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
4615  { 6774 /* ori */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_UImm16 }, },
4616  { 6774 /* ori */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_UImm16 }, },
4617  { 6774 /* ori */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
4618  { 6774 /* ori */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
4619  { 6774 /* ori */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
4620  { 6778 /* ori.b */, Mips::ORI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
4621  { 6784 /* packrl.ph */, Mips::PACKRL_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4622  { 6784 /* packrl.ph */, Mips::PACKRL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4623  { 6794 /* pause */, Mips::PAUSE, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r2, {  }, },
4624  { 6794 /* pause */, Mips::PAUSE_MMR6, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMicroMips32r6, {  }, },
4625  { 6794 /* pause */, Mips::PAUSE_MM, Convert_NoOperands, Feature_InMicroMips, {  }, },
4626  { 6800 /* pckev.b */, Mips::PCKEV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4627  { 6808 /* pckev.d */, Mips::PCKEV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4628  { 6816 /* pckev.h */, Mips::PCKEV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4629  { 6824 /* pckev.w */, Mips::PCKEV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4630  { 6832 /* pckod.b */, Mips::PCKOD_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4631  { 6840 /* pckod.d */, Mips::PCKOD_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4632  { 6848 /* pckod.h */, Mips::PCKOD_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4633  { 6856 /* pckod.w */, Mips::PCKOD_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4634  { 6864 /* pcnt.b */, Mips::PCNT_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4635  { 6871 /* pcnt.d */, Mips::PCNT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4636  { 6878 /* pcnt.h */, Mips::PCNT_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4637  { 6885 /* pcnt.w */, Mips::PCNT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4638  { 6892 /* pick.ph */, Mips::PICK_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4639  { 6892 /* pick.ph */, Mips::PICK_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4640  { 6900 /* pick.qb */, Mips::PICK_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4641  { 6900 /* pick.qb */, Mips::PICK_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4642  { 6908 /* pop */, Mips::POP, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, Feature_HasCnMips, { MCK_GPR32AsmReg }, },
4643  { 6908 /* pop */, Mips::POP, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4644  { 6912 /* preceq.w.phl */, Mips::PRECEQ_W_PHL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4645  { 6912 /* preceq.w.phl */, Mips::PRECEQ_W_PHL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4646  { 6925 /* preceq.w.phr */, Mips::PRECEQ_W_PHR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4647  { 6925 /* preceq.w.phr */, Mips::PRECEQ_W_PHR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4648  { 6938 /* precequ.ph.qbl */, Mips::PRECEQU_PH_QBL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4649  { 6938 /* precequ.ph.qbl */, Mips::PRECEQU_PH_QBL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4650  { 6953 /* precequ.ph.qbla */, Mips::PRECEQU_PH_QBLA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4651  { 6953 /* precequ.ph.qbla */, Mips::PRECEQU_PH_QBLA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4652  { 6969 /* precequ.ph.qbr */, Mips::PRECEQU_PH_QBR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4653  { 6969 /* precequ.ph.qbr */, Mips::PRECEQU_PH_QBR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4654  { 6984 /* precequ.ph.qbra */, Mips::PRECEQU_PH_QBRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4655  { 6984 /* precequ.ph.qbra */, Mips::PRECEQU_PH_QBRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4656  { 7000 /* preceu.ph.qbl */, Mips::PRECEU_PH_QBL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4657  { 7000 /* preceu.ph.qbl */, Mips::PRECEU_PH_QBL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4658  { 7014 /* preceu.ph.qbla */, Mips::PRECEU_PH_QBLA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4659  { 7014 /* preceu.ph.qbla */, Mips::PRECEU_PH_QBLA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4660  { 7029 /* preceu.ph.qbr */, Mips::PRECEU_PH_QBR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4661  { 7029 /* preceu.ph.qbr */, Mips::PRECEU_PH_QBR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4662  { 7043 /* preceu.ph.qbra */, Mips::PRECEU_PH_QBRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4663  { 7043 /* preceu.ph.qbra */, Mips::PRECEU_PH_QBRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4664  { 7058 /* precr.qb.ph */, Mips::PRECR_QB_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4665  { 7058 /* precr.qb.ph */, Mips::PRECR_QB_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4666  { 7070 /* precr_sra.ph.w */, Mips::PRECR_SRA_PH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
4667  { 7070 /* precr_sra.ph.w */, Mips::PRECR_SRA_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
4668  { 7085 /* precr_sra_r.ph.w */, Mips::PRECR_SRA_R_PH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
4669  { 7085 /* precr_sra_r.ph.w */, Mips::PRECR_SRA_R_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
4670  { 7102 /* precrq.ph.w */, Mips::PRECRQ_PH_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4671  { 7102 /* precrq.ph.w */, Mips::PRECRQ_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4672  { 7114 /* precrq.qb.ph */, Mips::PRECRQ_QB_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4673  { 7114 /* precrq.qb.ph */, Mips::PRECRQ_QB_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4674  { 7127 /* precrq_rs.ph.w */, Mips::PRECRQ_RS_PH_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4675  { 7127 /* precrq_rs.ph.w */, Mips::PRECRQ_RS_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4676  { 7142 /* precrqu_s.qb.ph */, Mips::PRECRQU_S_QB_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4677  { 7142 /* precrqu_s.qb.ph */, Mips::PRECRQU_S_QB_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4678  { 7158 /* pref */, Mips::PREF_R6, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, },
4679  { 7158 /* pref */, Mips::PREF, Convert__Mem2_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMips3_32|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_ConstantUImm5_0, MCK_Mem }, },
4680  { 7158 /* pref */, Mips::PREF_MMR6, Convert__Mem2_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, },
4681  { 7158 /* pref */, Mips::PREF_MM, Convert__Mem2_1__ConstantUImm5_01_0, Feature_InMicroMips, { MCK_ConstantUImm5_0, MCK_Mem }, },
4682  { 7163 /* prefe */, Mips::PREFE, Convert__Mem2_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasEVA, { MCK_ConstantUImm5_0, MCK_Mem }, },
4683  { 7163 /* prefe */, Mips::PREFE_MMR6, Convert__Mem2_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, },
4684  { 7163 /* prefe */, Mips::PREFE_MM, Convert__Mem2_1__ConstantUImm5_01_0, Feature_InMicroMips, { MCK_ConstantUImm5_0, MCK_Mem }, },
4685  { 7169 /* prefx */, Mips::PREFX_MM, Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0, Feature_InMicroMips, { MCK_ConstantUImm5_0, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
4686  { 7175 /* prepend */, Mips::PREPEND_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
4687  { 7175 /* prepend */, Mips::PREPEND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
4688  { 7183 /* raddu.w.qb */, Mips::RADDU_W_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4689  { 7183 /* raddu.w.qb */, Mips::RADDU_W_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4690  { 7194 /* rddsp */, Mips::RDDSP_MM, Convert__GPR32AsmReg1_0__ConstantUImm7_01_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm7_0 }, },
4691  { 7194 /* rddsp */, Mips::RDDSP, Convert__GPR32AsmReg1_0__ConstantUImm10_01_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
4692  { 7200 /* rdhwr */, Mips::RDHWR_MM, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1, Feature_HasStdEnc|Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg }, },
4693  { 7200 /* rdhwr */, Mips::RDHWR, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg }, },
4694  { 7200 /* rdhwr */, Mips::RDHWR_MMR6, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg }, },
4695  { 7200 /* rdhwr */, Mips::RDHWR_MMR6, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg, MCK_ConstantUImm3_0 }, },
4696  { 7206 /* rdpgpr */, Mips::RDPGPR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4697  { 7213 /* recip.d */, Mips::RECIP_D_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
4698  { 7221 /* recip.s */, Mips::RECIP_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
4699  { 7229 /* repl.ph */, Mips::REPL_PH_MM, Convert__GPR32AsmReg1_0__ConstantUImm10_01_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
4700  { 7229 /* repl.ph */, Mips::REPL_PH, Convert__GPR32AsmReg1_0__ConstantUImm10_01_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
4701  { 7237 /* repl.qb */, Mips::REPL_QB_MM, Convert__GPR32AsmReg1_0__ConstantUImm8_01_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm8_0 }, },
4702  { 7237 /* repl.qb */, Mips::REPL_QB, Convert__GPR32AsmReg1_0__ConstantUImm8_01_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm8_0 }, },
4703  { 7245 /* replv.ph */, Mips::REPLV_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4704  { 7245 /* replv.ph */, Mips::REPLV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4705  { 7254 /* replv.qb */, Mips::REPLV_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4706  { 7254 /* replv.qb */, Mips::REPLV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4707  { 7263 /* rint.d */, Mips::RINT_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
4708  { 7263 /* rint.d */, Mips::RINT_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
4709  { 7270 /* rint.s */, Mips::RINT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
4710  { 7270 /* rint.s */, Mips::RINT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
4711  { 7277 /* rol */, Mips::ROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4712  { 7277 /* rol */, Mips::ROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__Imm1_1, 0, { MCK_GPR32AsmReg, MCK_Imm }, },
4713  { 7277 /* rol */, Mips::ROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4714  { 7277 /* rol */, Mips::ROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__Imm1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_Imm }, },
4715  { 7281 /* ror */, Mips::ROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4716  { 7281 /* ror */, Mips::RORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__Imm1_1, 0, { MCK_GPR32AsmReg, MCK_Imm }, },
4717  { 7281 /* ror */, Mips::ROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4718  { 7281 /* ror */, Mips::RORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__Imm1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_Imm }, },
4719  { 7285 /* rotr */, Mips::ROTR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_HasMips32r2, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
4720  { 7285 /* rotr */, Mips::ROTR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
4721  { 7285 /* rotr */, Mips::ROTR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMips32r2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
4722  { 7285 /* rotr */, Mips::ROTR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
4723  { 7290 /* rotrv */, Mips::ROTRV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4724  { 7290 /* rotrv */, Mips::ROTRV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4725  { 7296 /* round.l.d */, Mips::ROUND_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
4726  { 7296 /* round.l.d */, Mips::ROUND_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
4727  { 7306 /* round.l.s */, Mips::ROUND_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
4728  { 7306 /* round.l.s */, Mips::ROUND_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
4729  { 7316 /* round.w.d */, Mips::ROUND_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
4730  { 7316 /* round.w.d */, Mips::ROUND_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
4731  { 7316 /* round.w.d */, Mips::ROUND_W_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
4732  { 7326 /* round.w.s */, Mips::ROUND_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
4733  { 7326 /* round.w.s */, Mips::ROUND_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
4734  { 7336 /* rsqrt.d */, Mips::RSQRT_D_MMR6, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
4735  { 7344 /* rsqrt.s */, Mips::RSQRT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
4736  { 7352 /* sat_s.b */, Mips::SAT_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
4737  { 7360 /* sat_s.d */, Mips::SAT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
4738  { 7368 /* sat_s.h */, Mips::SAT_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
4739  { 7376 /* sat_s.w */, Mips::SAT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
4740  { 7384 /* sat_u.b */, Mips::SAT_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
4741  { 7392 /* sat_u.d */, Mips::SAT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
4742  { 7400 /* sat_u.h */, Mips::SAT_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
4743  { 7408 /* sat_u.w */, Mips::SAT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
4744  { 7416 /* sb */, Mips::SB_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
4745  { 7416 /* sb */, Mips::SB, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_Mem }, },
4746  { 7416 /* sb */, Mips::SB_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
4747  { 7416 /* sb */, Mips::SbRxRyOffMemX16, Convert__Reg1_0__Reg1_1__Imm1_2__Reg1_3, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_Imm, MCK_CPU16RegsPlusSP }, },
4748  { 7419 /* sb16 */, Mips::SB16_MM, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, Feature_InMicroMips, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
4749  { 7419 /* sb16 */, Mips::SB16_MMR6, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, Feature_HasMicroMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
4750  { 7424 /* sbe */, Mips::SBE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
4751  { 7424 /* sbe */, Mips::SBE_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
4752  { 7424 /* sbe */, Mips::SBE_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
4753  { 7428 /* sc */, Mips::SC_R6, Convert__GPR32AsmReg1_0__Tie0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
4754  { 7428 /* sc */, Mips::SC, Convert__GPR32AsmReg1_0__Tie0__Mem2_1, Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
4755  { 7428 /* sc */, Mips::SC_MM, Convert__GPR32AsmReg1_0__Tie0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
4756  { 7431 /* scd */, Mips::SCD_R6, Convert__GPR64AsmReg1_0__Tie0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR64AsmReg, MCK_MemOffsetSimm9 }, },
4757  { 7431 /* scd */, Mips::SCD, Convert__GPR64AsmReg1_0__Tie0__Mem2_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, },
4758  { 7435 /* sce */, Mips::SCE, Convert__GPR32AsmReg1_0__Tie0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
4759  { 7435 /* sce */, Mips::SCE_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
4760  { 7435 /* sce */, Mips::SCE_MM, Convert__GPR32AsmReg1_0__Tie0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
4761  { 7439 /* sd */, Mips::SD, Convert__GPR64AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMips3, { MCK_GPR64AsmReg, MCK_Mem }, },
4762  { 7442 /* sdbbp */, Mips::SDBBP, Convert__imm_95_0, Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6, {  }, },
4763  { 7442 /* sdbbp */, Mips::SDBBP_R6, Convert__imm_95_0, Feature_HasMips32r6|Feature_NotInMicroMips, {  }, },
4764  { 7442 /* sdbbp */, Mips::SDBBP_MMR6, Convert__imm_95_0, Feature_HasMicroMips32r6, {  }, },
4765  { 7442 /* sdbbp */, Mips::SDBBP, Convert__Imm1_0, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_Imm }, },
4766  { 7442 /* sdbbp */, Mips::SDBBP_R6, Convert__Imm1_0, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_Imm }, },
4767  { 7442 /* sdbbp */, Mips::SDBBP_MMR6, Convert__Imm1_0, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_Imm }, },
4768  { 7442 /* sdbbp */, Mips::SDBBP_MM, Convert__Imm1_0, Feature_InMicroMips, { MCK_Imm }, },
4769  { 7448 /* sdbbp16 */, Mips::SDBBP16_MM, Convert__ConstantUImm4_01_0, Feature_InMicroMips|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_ConstantUImm4_0 }, },
4770  { 7448 /* sdbbp16 */, Mips::SDBBP16_MMR6, Convert__ConstantUImm4_01_0, Feature_HasMicroMips32r6, { MCK_ConstantUImm4_0 }, },
4771  { 7456 /* sdc1 */, Mips::SDC1, Convert__AFGR64AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_Mem }, },
4772  { 7456 /* sdc1 */, Mips::SDC164, Convert__FGR64AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_Mem }, },
4773  { 7461 /* sdc2 */, Mips::SDC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
4774  { 7461 /* sdc2 */, Mips::SDC2, Convert__COP2AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_Mem }, },
4775  { 7466 /* sdc3 */, Mips::SDC3, Convert__COP3AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, },
4776  { 7471 /* sdl */, Mips::SDL, Convert__GPR64AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, },
4777  { 7475 /* sdr */, Mips::SDR, Convert__GPR64AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, },
4778  { 7479 /* sdxc1 */, Mips::SDXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
4779  { 7479 /* sdxc1 */, Mips::SDXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
4780  { 7485 /* seb */, Mips::SebRx16, Convert__Reg1_0__Tie0, Feature_InMips16Mode, { MCK_CPU16Regs }, },
4781  { 7485 /* seb */, Mips::SEB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4782  { 7485 /* seb */, Mips::SEB_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4783  { 7485 /* seb */, Mips::SEB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4784  { 7489 /* seh */, Mips::SehRx16, Convert__Reg1_0__Tie0, Feature_InMips16Mode, { MCK_CPU16Regs }, },
4785  { 7489 /* seh */, Mips::SEH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4786  { 7489 /* seh */, Mips::SEH_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4787  { 7489 /* seh */, Mips::SEH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4788  { 7493 /* sel.d */, Mips::SEL_D, Convert__FGR64AsmReg1_0__Tie0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
4789  { 7493 /* sel.d */, Mips::SEL_D_MMR6, Convert__FGR64AsmReg1_0__Tie0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
4790  { 7499 /* sel.s */, Mips::SEL_S, Convert__FGR32AsmReg1_0__Tie0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
4791  { 7499 /* sel.s */, Mips::SEL_S_MMR6, Convert__FGR32AsmReg1_0__Tie0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
4792  { 7505 /* seleqz */, Mips::SELEQZ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4793  { 7505 /* seleqz */, Mips::SELEQZ_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4794  { 7505 /* seleqz */, Mips::SELEQZ64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips32r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
4795  { 7512 /* seleqz.d */, Mips::SELEQZ_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
4796  { 7512 /* seleqz.d */, Mips::SELEQZ_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
4797  { 7521 /* seleqz.s */, Mips::SELEQZ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
4798  { 7521 /* seleqz.s */, Mips::SELEQZ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
4799  { 7530 /* selnez */, Mips::SELNEZ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4800  { 7530 /* selnez */, Mips::SELNEZ_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4801  { 7530 /* selnez */, Mips::SELNEZ64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips32r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
4802  { 7537 /* selnez.d */, Mips::SELNEZ_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
4803  { 7537 /* selnez.d */, Mips::SELENZ_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
4804  { 7546 /* selnez.s */, Mips::SELNEZ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
4805  { 7546 /* selnez.s */, Mips::SELENZ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
4806  { 7555 /* seq */, Mips::SEQ, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
4807  { 7555 /* seq */, Mips::SEQ, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
4808  { 7559 /* seqi */, Mips::SEQi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_Imm }, },
4809  { 7559 /* seqi */, Mips::SEQi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
4810  { 7564 /* sh */, Mips::SH_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
4811  { 7564 /* sh */, Mips::SH, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_Mem }, },
4812  { 7564 /* sh */, Mips::SH_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
4813  { 7564 /* sh */, Mips::ShRxRyOffMemX16, Convert__Reg1_0__Reg1_1__Imm1_2__Reg1_3, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_Imm, MCK_CPU16RegsPlusSP }, },
4814  { 7567 /* sh16 */, Mips::SH16_MM, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, Feature_InMicroMips, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
4815  { 7567 /* sh16 */, Mips::SH16_MMR6, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, Feature_HasMicroMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
4816  { 7572 /* she */, Mips::SHE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
4817  { 7572 /* she */, Mips::SHE_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
4818  { 7572 /* she */, Mips::SHE_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
4819  { 7576 /* shf.b */, Mips::SHF_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
4820  { 7582 /* shf.h */, Mips::SHF_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
4821  { 7588 /* shf.w */, Mips::SHF_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
4822  { 7594 /* shilo */, Mips::SHILO_MM, Convert__ACC64DSPAsmReg1_0__ConstantSImm61_1__Tie0, Feature_HasDSP|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_ConstantSImm6 }, },
4823  { 7594 /* shilo */, Mips::SHILO, Convert__ACC64DSPAsmReg1_0__ConstantSImm61_1__Tie0, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_ConstantSImm6 }, },
4824  { 7600 /* shilov */, Mips::SHILOV_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0, Feature_HasDSP|Feature_InMicroMips, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
4825  { 7600 /* shilov */, Mips::SHILOV, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
4826  { 7607 /* shll.ph */, Mips::SHLL_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
4827  { 7607 /* shll.ph */, Mips::SHLL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
4828  { 7615 /* shll.qb */, Mips::SHLL_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
4829  { 7615 /* shll.qb */, Mips::SHLL_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
4830  { 7623 /* shll_s.ph */, Mips::SHLL_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
4831  { 7623 /* shll_s.ph */, Mips::SHLL_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
4832  { 7633 /* shll_s.w */, Mips::SHLL_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
4833  { 7633 /* shll_s.w */, Mips::SHLL_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
4834  { 7642 /* shllv.ph */, Mips::SHLLV_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4835  { 7642 /* shllv.ph */, Mips::SHLLV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4836  { 7651 /* shllv.qb */, Mips::SHLLV_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4837  { 7651 /* shllv.qb */, Mips::SHLLV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4838  { 7660 /* shllv_s.ph */, Mips::SHLLV_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4839  { 7660 /* shllv_s.ph */, Mips::SHLLV_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4840  { 7671 /* shllv_s.w */, Mips::SHLLV_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4841  { 7671 /* shllv_s.w */, Mips::SHLLV_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4842  { 7681 /* shra.ph */, Mips::SHRA_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
4843  { 7681 /* shra.ph */, Mips::SHRA_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
4844  { 7689 /* shra.qb */, Mips::SHRA_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
4845  { 7689 /* shra.qb */, Mips::SHRA_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
4846  { 7697 /* shra_r.ph */, Mips::SHRA_R_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
4847  { 7697 /* shra_r.ph */, Mips::SHRA_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
4848  { 7707 /* shra_r.qb */, Mips::SHRA_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
4849  { 7707 /* shra_r.qb */, Mips::SHRA_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
4850  { 7717 /* shra_r.w */, Mips::SHRA_R_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
4851  { 7717 /* shra_r.w */, Mips::SHRA_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
4852  { 7726 /* shrav.ph */, Mips::SHRAV_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4853  { 7726 /* shrav.ph */, Mips::SHRAV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4854  { 7735 /* shrav.qb */, Mips::SHRAV_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4855  { 7735 /* shrav.qb */, Mips::SHRAV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4856  { 7744 /* shrav_r.ph */, Mips::SHRAV_R_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4857  { 7744 /* shrav_r.ph */, Mips::SHRAV_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4858  { 7755 /* shrav_r.qb */, Mips::SHRAV_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4859  { 7755 /* shrav_r.qb */, Mips::SHRAV_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4860  { 7766 /* shrav_r.w */, Mips::SHRAV_R_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4861  { 7766 /* shrav_r.w */, Mips::SHRAV_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4862  { 7776 /* shrl.ph */, Mips::SHRL_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
4863  { 7776 /* shrl.ph */, Mips::SHRL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
4864  { 7784 /* shrl.qb */, Mips::SHRL_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
4865  { 7784 /* shrl.qb */, Mips::SHRL_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
4866  { 7792 /* shrlv.ph */, Mips::SHRLV_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4867  { 7792 /* shrlv.ph */, Mips::SHRLV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4868  { 7801 /* shrlv.qb */, Mips::SHRLV_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4869  { 7801 /* shrlv.qb */, Mips::SHRLV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4870  { 7810 /* sld.b */, Mips::SLD_B, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
4871  { 7816 /* sld.d */, Mips::SLD_D, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
4872  { 7822 /* sld.h */, Mips::SLD_H, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
4873  { 7828 /* sld.w */, Mips::SLD_W, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
4874  { 7834 /* sldi.b */, Mips::SLDI_B, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm4_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, },
4875  { 7841 /* sldi.d */, Mips::SLDI_D, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm1_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_ }, },
4876  { 7848 /* sldi.h */, Mips::SLDI_H, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm3_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, },
4877  { 7855 /* sldi.w */, Mips::SLDI_W, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm2_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, },
4878  { 7862 /* sll */, Mips::SLL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
4879  { 7862 /* sll */, Mips::SLL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
4880  { 7862 /* sll */, Mips::SLL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
4881  { 7862 /* sll */, Mips::SllX16, Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_ConstantUImm5_0 }, },
4882  { 7862 /* sll */, Mips::SLLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4883  { 7862 /* sll */, Mips::SLL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
4884  { 7862 /* sll */, Mips::SLL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
4885  { 7862 /* sll */, Mips::SLL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
4886  { 7866 /* sll.b */, Mips::SLL_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4887  { 7872 /* sll.d */, Mips::SLL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4888  { 7878 /* sll.h */, Mips::SLL_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4889  { 7884 /* sll.w */, Mips::SLL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4890  { 7890 /* sll16 */, Mips::SLL16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
4891  { 7890 /* sll16 */, Mips::SLL16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_HasMicroMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
4892  { 7896 /* slli.b */, Mips::SLLI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
4893  { 7903 /* slli.d */, Mips::SLLI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
4894  { 7910 /* slli.h */, Mips::SLLI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
4895  { 7917 /* slli.w */, Mips::SLLI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
4896  { 7924 /* sllv */, Mips::SllvRxRy16, Convert__Reg1_0__Tie0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
4897  { 7924 /* sllv */, Mips::SLLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4898  { 7924 /* sllv */, Mips::SLLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4899  { 7929 /* slt */, Mips::SltRxRy16, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
4900  { 7929 /* slt */, Mips::SLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4901  { 7929 /* slt */, Mips::SLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4902  { 7929 /* slt */, Mips::SLTi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__Imm1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_Imm }, },
4903  { 7933 /* slti */, Mips::SltiRxImmX16, Convert__Reg1_0__Imm1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_Imm }, },
4904  { 7933 /* slti */, Mips::SLTi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__Imm1_2, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_Imm }, },
4905  { 7933 /* slti */, Mips::SLTi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__Imm1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_Imm }, },
4906  { 7933 /* slti */, Mips::SltiRxImm16, Convert__Reg1_0__Imm1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_Imm, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
4907  { 7938 /* sltiu */, Mips::SltiuRxImmX16, Convert__Reg1_0__Imm1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_Imm }, },
4908  { 7938 /* sltiu */, Mips::SLTiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__Imm1_2, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_Imm }, },
4909  { 7938 /* sltiu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__Imm1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_Imm }, },
4910  { 7938 /* sltiu */, Mips::SltiuRxImm16, Convert__Reg1_0__Imm1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_Imm, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
4911  { 7944 /* sltu */, Mips::SltuRxRy16, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
4912  { 7944 /* sltu */, Mips::SLTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4913  { 7944 /* sltu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4914  { 7944 /* sltu */, Mips::SLTiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__Imm1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_Imm }, },
4915  { 7949 /* sne */, Mips::SNE, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
4916  { 7949 /* sne */, Mips::SNE, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
4917  { 7953 /* snei */, Mips::SNEi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_Imm }, },
4918  { 7953 /* snei */, Mips::SNEi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
4919  { 7958 /* splat.b */, Mips::SPLAT_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
4920  { 7966 /* splat.d */, Mips::SPLAT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
4921  { 7974 /* splat.h */, Mips::SPLAT_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
4922  { 7982 /* splat.w */, Mips::SPLAT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
4923  { 7990 /* splati.b */, Mips::SPLATI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_Imm, MCK__93_ }, },
4924  { 7999 /* splati.d */, Mips::SPLATI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_Imm, MCK__93_ }, },
4925  { 8008 /* splati.h */, Mips::SPLATI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_Imm, MCK__93_ }, },
4926  { 8017 /* splati.w */, Mips::SPLATI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_Imm, MCK__93_ }, },
4927  { 8026 /* sqrt.d */, Mips::FSQRT_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
4928  { 8026 /* sqrt.d */, Mips::SQRT_D_MMR6, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
4929  { 8026 /* sqrt.d */, Mips::FSQRT_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
4930  { 8033 /* sqrt.s */, Mips::FSQRT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
4931  { 8033 /* sqrt.s */, Mips::FSQRT_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
4932  { 8033 /* sqrt.s */, Mips::SQRT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
4933  { 8040 /* sra */, Mips::SRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
4934  { 8040 /* sra */, Mips::SRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
4935  { 8040 /* sra */, Mips::SraX16, Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_ConstantUImm5_0 }, },
4936  { 8040 /* sra */, Mips::SRAV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4937  { 8040 /* sra */, Mips::SRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
4938  { 8040 /* sra */, Mips::SRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
4939  { 8044 /* sra.b */, Mips::SRA_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4940  { 8050 /* sra.d */, Mips::SRA_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4941  { 8056 /* sra.h */, Mips::SRA_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4942  { 8062 /* sra.w */, Mips::SRA_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4943  { 8068 /* srai.b */, Mips::SRAI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
4944  { 8075 /* srai.d */, Mips::SRAI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
4945  { 8082 /* srai.h */, Mips::SRAI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
4946  { 8089 /* srai.w */, Mips::SRAI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
4947  { 8096 /* srar.b */, Mips::SRAR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4948  { 8103 /* srar.d */, Mips::SRAR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4949  { 8110 /* srar.h */, Mips::SRAR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4950  { 8117 /* srar.w */, Mips::SRAR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4951  { 8124 /* srari.b */, Mips::SRARI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
4952  { 8132 /* srari.d */, Mips::SRARI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
4953  { 8140 /* srari.h */, Mips::SRARI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
4954  { 8148 /* srari.w */, Mips::SRARI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
4955  { 8156 /* srav */, Mips::SravRxRy16, Convert__Reg1_0__Tie0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
4956  { 8156 /* srav */, Mips::SRAV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4957  { 8156 /* srav */, Mips::SRAV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4958  { 8161 /* srl */, Mips::SRL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
4959  { 8161 /* srl */, Mips::SRL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
4960  { 8161 /* srl */, Mips::SrlX16, Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_ConstantUImm5_0 }, },
4961  { 8161 /* srl */, Mips::SRLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4962  { 8161 /* srl */, Mips::SRL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
4963  { 8161 /* srl */, Mips::SRL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
4964  { 8165 /* srl.b */, Mips::SRL_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4965  { 8171 /* srl.d */, Mips::SRL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4966  { 8177 /* srl.h */, Mips::SRL_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4967  { 8183 /* srl.w */, Mips::SRL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4968  { 8189 /* srl16 */, Mips::SRL16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
4969  { 8189 /* srl16 */, Mips::SRL16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_HasMicroMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
4970  { 8195 /* srli.b */, Mips::SRLI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
4971  { 8202 /* srli.d */, Mips::SRLI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
4972  { 8209 /* srli.h */, Mips::SRLI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
4973  { 8216 /* srli.w */, Mips::SRLI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
4974  { 8223 /* srlr.b */, Mips::SRLR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4975  { 8230 /* srlr.d */, Mips::SRLR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4976  { 8237 /* srlr.h */, Mips::SRLR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4977  { 8244 /* srlr.w */, Mips::SRLR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
4978  { 8251 /* srlri.b */, Mips::SRLRI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
4979  { 8259 /* srlri.d */, Mips::SRLRI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
4980  { 8267 /* srlri.h */, Mips::SRLRI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
4981  { 8275 /* srlri.w */, Mips::SRLRI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
4982  { 8283 /* srlv */, Mips::SrlvRxRy16, Convert__Reg1_0__Tie0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
4983  { 8283 /* srlv */, Mips::SRLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4984  { 8283 /* srlv */, Mips::SRLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4985  { 8288 /* ssnop */, Mips::SSNOP_MMR6, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMicroMips32r6, {  }, },
4986  { 8288 /* ssnop */, Mips::SSNOP, Convert_NoOperands, Feature_HasStdEnc, {  }, },
4987  { 8288 /* ssnop */, Mips::SSNOP_MM, Convert_NoOperands, Feature_InMicroMips, {  }, },
4988  { 8294 /* st.b */, Mips::ST_B, Convert__MSA128AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_Mem }, },
4989  { 8299 /* st.d */, Mips::ST_D, Convert__MSA128AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_Mem }, },
4990  { 8304 /* st.h */, Mips::ST_H, Convert__MSA128AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_Mem }, },
4991  { 8309 /* st.w */, Mips::ST_W, Convert__MSA128AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_Mem }, },
4992  { 8314 /* sub */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4993  { 8314 /* sub */, Mips::SUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4994  { 8314 /* sub */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4995  { 8314 /* sub */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1, Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_InvNum }, },
4996  { 8314 /* sub */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4997  { 8314 /* sub */, Mips::SUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4998  { 8314 /* sub */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
4999  { 8314 /* sub */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2, Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_InvNum }, },
5000  { 8318 /* sub.d */, Mips::FSUB_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5001  { 8318 /* sub.d */, Mips::FSUB_D_MMR6, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_2__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5002  { 8318 /* sub.d */, Mips::FSUB_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5003  { 8324 /* sub.s */, Mips::FSUB_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5004  { 8324 /* sub.s */, Mips::FSUB_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5005  { 8330 /* subq.ph */, Mips::SUBQ_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5006  { 8330 /* subq.ph */, Mips::SUBQ_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5007  { 8338 /* subq_s.ph */, Mips::SUBQ_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5008  { 8338 /* subq_s.ph */, Mips::SUBQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5009  { 8348 /* subq_s.w */, Mips::SUBQ_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5010  { 8348 /* subq_s.w */, Mips::SUBQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5011  { 8357 /* subqh.ph */, Mips::SUBQH_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5012  { 8357 /* subqh.ph */, Mips::SUBQH_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5013  { 8366 /* subqh.w */, Mips::SUBQH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5014  { 8366 /* subqh.w */, Mips::SUBQH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5015  { 8374 /* subqh_r.ph */, Mips::SUBQH_R_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5016  { 8374 /* subqh_r.ph */, Mips::SUBQH_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5017  { 8385 /* subqh_r.w */, Mips::SUBQH_R_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5018  { 8385 /* subqh_r.w */, Mips::SUBQH_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5019  { 8395 /* subs_s.b */, Mips::SUBS_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5020  { 8404 /* subs_s.d */, Mips::SUBS_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5021  { 8413 /* subs_s.h */, Mips::SUBS_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5022  { 8422 /* subs_s.w */, Mips::SUBS_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5023  { 8431 /* subs_u.b */, Mips::SUBS_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5024  { 8440 /* subs_u.d */, Mips::SUBS_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5025  { 8449 /* subs_u.h */, Mips::SUBS_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5026  { 8458 /* subs_u.w */, Mips::SUBS_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5027  { 8467 /* subsus_u.b */, Mips::SUBSUS_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5028  { 8478 /* subsus_u.d */, Mips::SUBSUS_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5029  { 8489 /* subsus_u.h */, Mips::SUBSUS_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5030  { 8500 /* subsus_u.w */, Mips::SUBSUS_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5031  { 8511 /* subsuu_s.b */, Mips::SUBSUU_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5032  { 8522 /* subsuu_s.d */, Mips::SUBSUU_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5033  { 8533 /* subsuu_s.h */, Mips::SUBSUU_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5034  { 8544 /* subsuu_s.w */, Mips::SUBSUU_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5035  { 8555 /* subu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5036  { 8555 /* subu */, Mips::SUBu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5037  { 8555 /* subu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5038  { 8555 /* subu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1, 0, { MCK_GPR32AsmReg, MCK_InvNum }, },
5039  { 8555 /* subu */, Mips::SubuRxRyRz16, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_CPU16Regs }, },
5040  { 8555 /* subu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5041  { 8555 /* subu */, Mips::SUBu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5042  { 8555 /* subu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5043  { 8555 /* subu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_InvNum }, },
5044  { 8560 /* subu.ph */, Mips::SUBU_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5045  { 8560 /* subu.ph */, Mips::SUBU_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5046  { 8568 /* subu.qb */, Mips::SUBU_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5047  { 8568 /* subu.qb */, Mips::SUBU_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5048  { 8576 /* subu16 */, Mips::SUBU16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
5049  { 8576 /* subu16 */, Mips::SUBU16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, Feature_HasMicroMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
5050  { 8583 /* subu_s.ph */, Mips::SUBU_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5051  { 8583 /* subu_s.ph */, Mips::SUBU_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5052  { 8593 /* subu_s.qb */, Mips::SUBU_S_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5053  { 8593 /* subu_s.qb */, Mips::SUBU_S_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5054  { 8603 /* subuh.qb */, Mips::SUBUH_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5055  { 8603 /* subuh.qb */, Mips::SUBUH_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5056  { 8612 /* subuh_r.qb */, Mips::SUBUH_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5057  { 8612 /* subuh_r.qb */, Mips::SUBUH_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5058  { 8623 /* subv.b */, Mips::SUBV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5059  { 8630 /* subv.d */, Mips::SUBV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5060  { 8637 /* subv.h */, Mips::SUBV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5061  { 8644 /* subv.w */, Mips::SUBV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5062  { 8651 /* subvi.b */, Mips::SUBVI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
5063  { 8659 /* subvi.d */, Mips::SUBVI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
5064  { 8667 /* subvi.h */, Mips::SUBVI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
5065  { 8675 /* subvi.w */, Mips::SUBVI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
5066  { 8683 /* suxc1 */, Mips::SUXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
5067  { 8683 /* suxc1 */, Mips::SUXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
5068  { 8689 /* sw */, Mips::SWSP_MM, Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MicroMipsMemSP }, },
5069  { 8689 /* sw */, Mips::SWSP_MMR6, Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_MicroMipsMemSP }, },
5070  { 8689 /* sw */, Mips::SW, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
5071  { 8689 /* sw */, Mips::SW_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
5072  { 8689 /* sw */, Mips::SW_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
5073  { 8689 /* sw */, Mips::SwRxRyOffMemX16, Convert__Reg1_0__Reg1_1__Imm1_2__Reg1_3, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_Imm, MCK_CPU16RegsPlusSP }, },
5074  { 8689 /* sw */, Mips::SwRxSpImmX16, Convert__Reg1_0__Reg1_3__Imm1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_Imm, MCK__40_, MCK_CPUSPReg, MCK__41__59_ }, },
5075  { 8692 /* sw16 */, Mips::SW16_MM, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, Feature_InMicroMips, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
5076  { 8692 /* sw16 */, Mips::SW16_MMR6, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, Feature_HasMicroMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
5077  { 8697 /* swc1 */, Mips::SWC1, Convert__FGR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_Mem }, },
5078  { 8702 /* swc2 */, Mips::SWC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
5079  { 8702 /* swc2 */, Mips::SWC2, Convert__COP2AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_Mem }, },
5080  { 8707 /* swc3 */, Mips::SWC3, Convert__COP3AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, },
5081  { 8712 /* swe */, Mips::SWE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
5082  { 8712 /* swe */, Mips::SWE_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
5083  { 8712 /* swe */, Mips::SWE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9GPR2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9GPR }, },
5084  { 8716 /* swl */, Mips::SWL, Convert__GPR32AsmReg1_0__Mem2_1, Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
5085  { 8716 /* swl */, Mips::SWL_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
5086  { 8720 /* swle */, Mips::SWLE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
5087  { 8720 /* swle */, Mips::SWLE_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
5088  { 8725 /* swm */, Mips::SWM_MM, Convert__RegList1_0__Mem2_1, Feature_InMicroMips, { MCK_RegList, MCK_Mem }, },
5089  { 8729 /* swm16 */, Mips::SWM16_MM, Convert__RegList161_0__MemOffsetUimm42_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, },
5090  { 8729 /* swm16 */, Mips::SWM16_MMR6, Convert__RegList161_0__MemOffsetUimm42_1, Feature_HasMicroMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, },
5091  { 8735 /* swm32 */, Mips::SWM32_MM, Convert__RegList1_0__Mem2_1, Feature_InMicroMips, { MCK_RegList, MCK_Mem }, },
5092  { 8741 /* swp */, Mips::SWP_MM, Convert__RegPair2_0__Mem2_1, Feature_InMicroMips, { MCK_RegPair, MCK_Mem }, },
5093  { 8745 /* swr */, Mips::SWR, Convert__GPR32AsmReg1_0__Mem2_1, Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
5094  { 8745 /* swr */, Mips::SWR_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
5095  { 8749 /* swre */, Mips::SWRE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
5096  { 8749 /* swre */, Mips::SWRE_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
5097  { 8754 /* swxc1 */, Mips::SWXC1, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
5098  { 8760 /* sync */, Mips::SYNC_MMR6, Convert__imm_95_0, Feature_HasMicroMips32r6, {  }, },
5099  { 8760 /* sync */, Mips::SYNC, Convert__imm_95_0, Feature_HasMips2, {  }, },
5100  { 8760 /* sync */, Mips::SYNC, Convert__Imm1_0, Feature_HasStdEnc|Feature_HasMips32, { MCK_Imm }, },
5101  { 8760 /* sync */, Mips::SYNC_MMR6, Convert__Imm1_0, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_Imm }, },
5102  { 8760 /* sync */, Mips::SYNC_MM, Convert__Imm1_0, Feature_InMicroMips, { MCK_Imm }, },
5103  { 8765 /* synci */, Mips::SYNCI, Convert__MemOffsetSimm162_0, Feature_HasStdEnc|Feature_HasMips32r2, { MCK_MemOffsetSimm16 }, },
5104  { 8765 /* synci */, Mips::SYNCI_MMR6, Convert__MemOffsetSimm162_0, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_MemOffsetSimm16 }, },
5105  { 8771 /* synciobdma */, Mips::SYNC, Convert__imm_95_2, Feature_HasMips64|Feature_HasCnMips, {  }, },
5106  { 8782 /* syncs */, Mips::SYNC, Convert__imm_95_6, Feature_HasMips64|Feature_HasCnMips, {  }, },
5107  { 8788 /* syncw */, Mips::SYNC, Convert__imm_95_4, Feature_HasMips64|Feature_HasCnMips, {  }, },
5108  { 8794 /* syncws */, Mips::SYNC, Convert__imm_95_5, Feature_HasMips64|Feature_HasCnMips, {  }, },
5109  { 8801 /* syscall */, Mips::SYSCALL, Convert__imm_95_0, 0, {  }, },
5110  { 8801 /* syscall */, Mips::SYSCALL, Convert__Imm1_0, Feature_HasStdEnc, { MCK_Imm }, },
5111  { 8801 /* syscall */, Mips::SYSCALL_MM, Convert__Imm1_0, Feature_InMicroMips, { MCK_Imm }, },
5112  { 8809 /* teq */, Mips::TEQ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5113  { 8809 /* teq */, Mips::TEQ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5114  { 8809 /* teq */, Mips::TEQ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
5115  { 8809 /* teq */, Mips::TEQ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
5116  { 8813 /* teqi */, Mips::TEQI, Convert__GPR32AsmReg1_0__Imm1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm }, },
5117  { 8813 /* teqi */, Mips::TEQI_MM, Convert__GPR32AsmReg1_0__Imm1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Imm }, },
5118  { 8818 /* tge */, Mips::TGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5119  { 8818 /* tge */, Mips::TGE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5120  { 8818 /* tge */, Mips::TGE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
5121  { 8818 /* tge */, Mips::TGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
5122  { 8822 /* tgei */, Mips::TGEI, Convert__GPR32AsmReg1_0__Imm1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm }, },
5123  { 8822 /* tgei */, Mips::TGEI_MM, Convert__GPR32AsmReg1_0__Imm1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Imm }, },
5124  { 8827 /* tgeiu */, Mips::TGEIU, Convert__GPR32AsmReg1_0__Imm1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm }, },
5125  { 8827 /* tgeiu */, Mips::TGEIU_MM, Convert__GPR32AsmReg1_0__Imm1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Imm }, },
5126  { 8833 /* tgeu */, Mips::TGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5127  { 8833 /* tgeu */, Mips::TGEU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5128  { 8833 /* tgeu */, Mips::TGEU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
5129  { 8833 /* tgeu */, Mips::TGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
5130  { 8838 /* tlbinv */, Mips::TLBINV, Convert_NoOperands, Feature_HasStdEnc|Feature_HasEVA, {  }, },
5131  { 8845 /* tlbinvf */, Mips::TLBINVF, Convert_NoOperands, Feature_HasStdEnc|Feature_HasEVA, {  }, },
5132  { 8853 /* tlbp */, Mips::TLBP, Convert_NoOperands, Feature_HasStdEnc, {  }, },
5133  { 8853 /* tlbp */, Mips::TLBP_MM, Convert_NoOperands, Feature_InMicroMips, {  }, },
5134  { 8858 /* tlbr */, Mips::TLBR, Convert_NoOperands, Feature_HasStdEnc, {  }, },
5135  { 8858 /* tlbr */, Mips::TLBR_MM, Convert_NoOperands, Feature_InMicroMips, {  }, },
5136  { 8863 /* tlbwi */, Mips::TLBWI, Convert_NoOperands, Feature_HasStdEnc, {  }, },
5137  { 8863 /* tlbwi */, Mips::TLBWI_MM, Convert_NoOperands, Feature_InMicroMips, {  }, },
5138  { 8869 /* tlbwr */, Mips::TLBWR, Convert_NoOperands, Feature_HasStdEnc, {  }, },
5139  { 8869 /* tlbwr */, Mips::TLBWR_MM, Convert_NoOperands, Feature_InMicroMips, {  }, },
5140  { 8875 /* tlt */, Mips::TLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5141  { 8875 /* tlt */, Mips::TLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5142  { 8875 /* tlt */, Mips::TLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
5143  { 8875 /* tlt */, Mips::TLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
5144  { 8879 /* tlti */, Mips::TLTI, Convert__GPR32AsmReg1_0__Imm1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm }, },
5145  { 8879 /* tlti */, Mips::TLTI_MM, Convert__GPR32AsmReg1_0__Imm1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Imm }, },
5146  { 8884 /* tltiu */, Mips::TTLTIU, Convert__GPR32AsmReg1_0__Imm1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm }, },
5147  { 8884 /* tltiu */, Mips::TLTIU_MM, Convert__GPR32AsmReg1_0__Imm1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Imm }, },
5148  { 8890 /* tltu */, Mips::TLTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5149  { 8890 /* tltu */, Mips::TLTU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5150  { 8890 /* tltu */, Mips::TLTU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
5151  { 8890 /* tltu */, Mips::TLTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
5152  { 8895 /* tne */, Mips::TNE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5153  { 8895 /* tne */, Mips::TNE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5154  { 8895 /* tne */, Mips::TNE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
5155  { 8895 /* tne */, Mips::TNE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
5156  { 8899 /* tnei */, Mips::TNEI, Convert__GPR32AsmReg1_0__Imm1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm }, },
5157  { 8899 /* tnei */, Mips::TNEI_MM, Convert__GPR32AsmReg1_0__Imm1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Imm }, },
5158  { 8904 /* trunc.l.d */, Mips::TRUNC_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5159  { 8904 /* trunc.l.d */, Mips::TRUNC_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5160  { 8914 /* trunc.l.s */, Mips::TRUNC_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
5161  { 8914 /* trunc.l.s */, Mips::TRUNC_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
5162  { 8924 /* trunc.w.d */, Mips::TRUNC_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
5163  { 8924 /* trunc.w.d */, Mips::TRUNC_W_D_MMR6, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
5164  { 8924 /* trunc.w.d */, Mips::TRUNC_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
5165  { 8934 /* trunc.w.s */, Mips::TRUNC_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5166  { 8934 /* trunc.w.s */, Mips::TRUNC_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_InMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5167  { 8934 /* trunc.w.s */, Mips::TRUNC_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5168  { 8944 /* ulh */, Mips::Ulh, Convert__GPR32AsmReg1_0__Mem2_1, 0, { MCK_GPR32AsmReg, MCK_Mem }, },
5169  { 8948 /* ulhu */, Mips::Ulhu, Convert__GPR32AsmReg1_0__Mem2_1, 0, { MCK_GPR32AsmReg, MCK_Mem }, },
5170  { 8953 /* ulw */, Mips::Ulw, Convert__GPR32AsmReg1_0__Mem2_1, 0, { MCK_GPR32AsmReg, MCK_Mem }, },
5171  { 8957 /* v3mulu */, Mips::V3MULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
5172  { 8957 /* v3mulu */, Mips::V3MULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
5173  { 8964 /* vmm0 */, Mips::VMM0, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
5174  { 8964 /* vmm0 */, Mips::VMM0, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
5175  { 8969 /* vmulu */, Mips::VMULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
5176  { 8969 /* vmulu */, Mips::VMULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
5177  { 8975 /* vshf.b */, Mips::VSHF_B, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5178  { 8982 /* vshf.d */, Mips::VSHF_D, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5179  { 8989 /* vshf.h */, Mips::VSHF_H, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5180  { 8996 /* vshf.w */, Mips::VSHF_W, Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5181  { 9003 /* wait */, Mips::WAIT, Convert_NoOperands, Feature_NotInMicroMips, {  }, },
5182  { 9003 /* wait */, Mips::WAIT_MM, Convert__imm_95_0, Feature_InMicroMips, {  }, },
5183  { 9003 /* wait */, Mips::WAIT_MMR6, Convert__ConstantUImm10_01_0, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_ConstantUImm10_0 }, },
5184  { 9003 /* wait */, Mips::WAIT_MM, Convert__ConstantUImm10_01_0, Feature_InMicroMips, { MCK_ConstantUImm10_0 }, },
5185  { 9008 /* wrdsp */, Mips::WRDSP, Convert__GPR32AsmReg1_0__imm_95_31, Feature_HasDSP|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
5186  { 9008 /* wrdsp */, Mips::WRDSP_MM, Convert__GPR32AsmReg1_0__imm_95_31, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg }, },
5187  { 9008 /* wrdsp */, Mips::WRDSP_MM, Convert__GPR32AsmReg1_0__ConstantUImm7_01_1, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm7_0 }, },
5188  { 9008 /* wrdsp */, Mips::WRDSP, Convert__GPR32AsmReg1_0__ConstantUImm10_01_1, Feature_HasDSP|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
5189  { 9014 /* wrpgpr */, Mips::WRPGPR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5190  { 9021 /* wsbh */, Mips::WSBH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5191  { 9021 /* wsbh */, Mips::WSBH_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5192  { 9021 /* wsbh */, Mips::WSBH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5193  { 9026 /* xor */, Mips::XorRxRxRy16, Convert__Reg1_0__Tie0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
5194  { 9026 /* xor */, Mips::XOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5195  { 9026 /* xor */, Mips::XOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5196  { 9026 /* xor */, Mips::XOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5197  { 9026 /* xor */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__Imm1_1, 0, { MCK_GPR32AsmReg, MCK_Imm }, },
5198  { 9026 /* xor */, Mips::XOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5199  { 9026 /* xor */, Mips::XOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5200  { 9026 /* xor */, Mips::XOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5201  { 9026 /* xor */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__Imm1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_Imm }, },
5202  { 9030 /* xor.v */, Mips::XOR_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5203  { 9036 /* xor16 */, Mips::XOR16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0, Feature_InMicroMips|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
5204  { 9036 /* xor16 */, Mips::XOR16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0, Feature_HasMicroMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
5205  { 9042 /* xori */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
5206  { 9042 /* xori */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_UImm16 }, },
5207  { 9042 /* xori */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_UImm16 }, },
5208  { 9042 /* xori */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_HasStdEnc|Feature_HasMicroMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
5209  { 9042 /* xori */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_HasStdEnc, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
5210  { 9042 /* xori */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
5211  { 9047 /* xori.b */, Mips::XORI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_Imm }, },
5212};
5213
5214bool MipsAsmParser::
5215mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) {
5216  // Find the appropriate table for this asm variant.
5217  const MatchEntry *Start, *End;
5218  switch (VariantID) {
5219  default: llvm_unreachable("invalid variant!");
5220  case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
5221  }
5222  // Search the table.
5223  auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
5224  return MnemonicRange.first != MnemonicRange.second;
5225}
5226
5227unsigned MipsAsmParser::
5228MatchInstructionImpl(const OperandVector &Operands,
5229                     MCInst &Inst, uint64_t &ErrorInfo,
5230                     bool matchingInlineAsm, unsigned VariantID) {
5231  // Eliminate obvious mismatches.
5232  if (Operands.size() > 9) {
5233    ErrorInfo = 9;
5234    return Match_InvalidOperand;
5235  }
5236
5237  // Get the current feature set.
5238  uint64_t AvailableFeatures = getAvailableFeatures();
5239
5240  // Get the instruction mnemonic, which is the first token.
5241  StringRef Mnemonic = ((MipsOperand&)*Operands[0]).getToken();
5242
5243  // Some state to try to produce better error messages.
5244  bool HadMatchOtherThanFeatures = false;
5245  bool HadMatchOtherThanPredicate = false;
5246  unsigned RetCode = Match_InvalidOperand;
5247  uint64_t MissingFeatures = ~0ULL;
5248  // Set ErrorInfo to the operand that mismatches if it is
5249  // wrong for all instances of the instruction.
5250  ErrorInfo = ~0ULL;
5251  // Find the appropriate table for this asm variant.
5252  const MatchEntry *Start, *End;
5253  switch (VariantID) {
5254  default: llvm_unreachable("invalid variant!");
5255  case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
5256  }
5257  // Search the table.
5258  auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
5259
5260  // Return a more specific error code if no mnemonics match.
5261  if (MnemonicRange.first == MnemonicRange.second)
5262    return Match_MnemonicFail;
5263
5264  for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
5265       it != ie; ++it) {
5266    // equal_range guarantees that instruction mnemonic matches.
5267    assert(Mnemonic == it->getMnemonic());
5268    bool OperandsValid = true;
5269    for (unsigned i = 0; i != 8; ++i) {
5270      auto Formal = static_cast<MatchClassKind>(it->Classes[i]);
5271      if (i+1 >= Operands.size()) {
5272        OperandsValid = (Formal == InvalidMatchClass);
5273        if (!OperandsValid) ErrorInfo = i+1;
5274        break;
5275      }
5276      MCParsedAsmOperand &Actual = *Operands[i+1];
5277      unsigned Diag = validateOperandClass(Actual, Formal);
5278      if (Diag == Match_Success)
5279        continue;
5280      // If the generic handler indicates an invalid operand
5281      // failure, check for a special case.
5282      if (Diag == Match_InvalidOperand) {
5283        Diag = validateTargetOperandClass(Actual, Formal);
5284        if (Diag == Match_Success)
5285          continue;
5286      }
5287      // If this operand is broken for all of the instances of this
5288      // mnemonic, keep track of it so we can report loc info.
5289      // If we already had a match that only failed due to a
5290      // target predicate, that diagnostic is preferred.
5291      if (!HadMatchOtherThanPredicate &&
5292          (it == MnemonicRange.first || ErrorInfo <= i+1)) {
5293        ErrorInfo = i+1;
5294        // InvalidOperand is the default. Prefer specificity.
5295        if (Diag != Match_InvalidOperand)
5296          RetCode = Diag;
5297      }
5298      // Otherwise, just reject this instance of the mnemonic.
5299      OperandsValid = false;
5300      break;
5301    }
5302
5303    if (!OperandsValid) continue;
5304    if ((AvailableFeatures & it->RequiredFeatures) != it->RequiredFeatures) {
5305      HadMatchOtherThanFeatures = true;
5306      uint64_t NewMissingFeatures = it->RequiredFeatures & ~AvailableFeatures;
5307      if (countPopulation(NewMissingFeatures) <=
5308          countPopulation(MissingFeatures))
5309        MissingFeatures = NewMissingFeatures;
5310      continue;
5311    }
5312
5313    Inst.clear();
5314
5315    if (matchingInlineAsm) {
5316      Inst.setOpcode(it->Opcode);
5317      convertToMapAndConstraints(it->ConvertFn, Operands);
5318      return Match_Success;
5319    }
5320
5321    // We have selected a definite instruction, convert the parsed
5322    // operands into the appropriate MCInst.
5323    convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);
5324
5325    // We have a potential match. Check the target predicate to
5326    // handle any context sensitive constraints.
5327    unsigned MatchResult;
5328    if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) {
5329      Inst.clear();
5330      RetCode = MatchResult;
5331      HadMatchOtherThanPredicate = true;
5332      continue;
5333    }
5334
5335    return Match_Success;
5336  }
5337
5338  // Okay, we had no match.  Try to return a useful error code.
5339  if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)
5340    return RetCode;
5341
5342  // Missing feature matches return which features were missing
5343  ErrorInfo = MissingFeatures;
5344  return Match_MissingFeature;
5345}
5346
5347namespace {
5348  struct OperandMatchEntry {
5349    uint64_t RequiredFeatures;
5350    uint16_t Mnemonic;
5351    uint8_t Class;
5352    uint8_t OperandMask;
5353
5354    StringRef getMnemonic() const {
5355      return StringRef(MnemonicTable + Mnemonic + 1,
5356                       MnemonicTable[Mnemonic]);
5357    }
5358  };
5359
5360  // Predicate for searching for an opcode.
5361  struct LessOpcodeOperand {
5362    bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {
5363      return LHS.getMnemonic()  < RHS;
5364    }
5365    bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {
5366      return LHS < RHS.getMnemonic();
5367    }
5368    bool operator()(const OperandMatchEntry &LHS, const OperandMatchEntry &RHS) {
5369      return LHS.getMnemonic() < RHS.getMnemonic();
5370    }
5371  };
5372} // end anonymous namespace.
5373
5374static const OperandMatchEntry OperandMatchTable[2469] = {
5375  /* Operand List Mask, Mnemonic, Operand Class, Features */
5376  { 0, 0 /* abs */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5377  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 4 /* abs.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
5378  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat, 4 /* abs.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
5379  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, 4 /* abs.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
5380  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 10 /* abs.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
5381  { Feature_HasStdEnc|Feature_IsNotSoftFloat, 10 /* abs.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
5382  { Feature_HasDSP|Feature_InMicroMips, 16 /* absq_s.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5383  { Feature_HasDSP, 16 /* absq_s.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5384  { Feature_HasDSPR2|Feature_InMicroMips, 26 /* absq_s.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5385  { Feature_HasDSPR2, 26 /* absq_s.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5386  { Feature_HasDSP|Feature_InMicroMips, 36 /* absq_s.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5387  { Feature_HasDSP, 36 /* absq_s.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5388  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 45 /* add */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5389  { Feature_HasStdEnc, 45 /* add */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5390  { Feature_InMicroMips, 45 /* add */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5391  { Feature_NotMips32r6|Feature_NotMips64r6, 45 /* add */, MCK_GPR32AsmReg, 1 /* 0 */ },
5392  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 45 /* add */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
5393  { Feature_HasStdEnc, 45 /* add */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
5394  { Feature_InMicroMips, 45 /* add */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
5395  { Feature_NotMips32r6|Feature_NotMips64r6, 45 /* add */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5396  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat, 49 /* add.d */, MCK_AFGR64AsmReg, 7 /* 0, 1, 2 */ },
5397  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 49 /* add.d */, MCK_AFGR64AsmReg, 7 /* 0, 1, 2 */ },
5398  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, 49 /* add.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
5399  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 55 /* add.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
5400  { Feature_HasStdEnc|Feature_IsNotSoftFloat, 55 /* add.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
5401  { Feature_HasStdEnc|Feature_HasMSA, 61 /* add_a.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5402  { Feature_HasStdEnc|Feature_HasMSA, 69 /* add_a.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5403  { Feature_HasStdEnc|Feature_HasMSA, 77 /* add_a.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5404  { Feature_HasStdEnc|Feature_HasMSA, 85 /* add_a.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5405  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 93 /* addi */, MCK_GPR32AsmReg, 1 /* 0 */ },
5406  { Feature_InMicroMips, 93 /* addi */, MCK_GPR32AsmReg, 1 /* 0 */ },
5407  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 93 /* addi */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5408  { Feature_InMicroMips, 93 /* addi */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5409  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 98 /* addiu */, MCK_GPR32AsmReg, 1 /* 0 */ },
5410  { Feature_HasStdEnc|Feature_NotInMicroMips, 98 /* addiu */, MCK_GPR32AsmReg, 1 /* 0 */ },
5411  { Feature_InMicroMips, 98 /* addiu */, MCK_GPR32AsmReg, 1 /* 0 */ },
5412  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 98 /* addiu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5413  { Feature_HasStdEnc|Feature_NotInMicroMips, 98 /* addiu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5414  { Feature_InMicroMips, 98 /* addiu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5415  { Feature_HasStdEnc|Feature_HasMips32r6, 104 /* addiupc */, MCK_GPR32AsmReg, 1 /* 0 */ },
5416  { Feature_HasStdEnc|Feature_HasMips32r6, 104 /* addiupc */, MCK_JumpTarget, 2 /* 1 */ },
5417  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 104 /* addiupc */, MCK_GPR32AsmReg, 1 /* 0 */ },
5418  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 104 /* addiupc */, MCK_JumpTarget, 2 /* 1 */ },
5419  { Feature_InMicroMips, 104 /* addiupc */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
5420  { Feature_InMicroMips, 112 /* addiur1sp */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
5421  { Feature_InMicroMips, 122 /* addiur2 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
5422  { Feature_InMicroMips, 130 /* addius5 */, MCK_GPR32AsmReg, 1 /* 0 */ },
5423  { Feature_HasDSP|Feature_InMicroMips, 146 /* addq.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
5424  { Feature_HasDSP, 146 /* addq.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
5425  { Feature_HasDSP|Feature_InMicroMips, 154 /* addq_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
5426  { Feature_HasDSP, 154 /* addq_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
5427  { Feature_HasDSP|Feature_InMicroMips, 164 /* addq_s.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
5428  { Feature_HasDSP, 164 /* addq_s.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
5429  { Feature_HasDSPR2|Feature_InMicroMips, 173 /* addqh.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
5430  { Feature_HasDSPR2, 173 /* addqh.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
5431  { Feature_HasDSPR2|Feature_InMicroMips, 182 /* addqh.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
5432  { Feature_HasDSPR2, 182 /* addqh.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
5433  { Feature_HasDSPR2|Feature_InMicroMips, 190 /* addqh_r.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
5434  { Feature_HasDSPR2, 190 /* addqh_r.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
5435  { Feature_HasDSPR2|Feature_InMicroMips, 201 /* addqh_r.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
5436  { Feature_HasDSPR2, 201 /* addqh_r.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
5437  { Feature_HasStdEnc|Feature_HasMSA, 211 /* adds_a.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5438  { Feature_HasStdEnc|Feature_HasMSA, 220 /* adds_a.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5439  { Feature_HasStdEnc|Feature_HasMSA, 229 /* adds_a.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5440  { Feature_HasStdEnc|Feature_HasMSA, 238 /* adds_a.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5441  { Feature_HasStdEnc|Feature_HasMSA, 247 /* adds_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5442  { Feature_HasStdEnc|Feature_HasMSA, 256 /* adds_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5443  { Feature_HasStdEnc|Feature_HasMSA, 265 /* adds_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5444  { Feature_HasStdEnc|Feature_HasMSA, 274 /* adds_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5445  { Feature_HasStdEnc|Feature_HasMSA, 283 /* adds_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5446  { Feature_HasStdEnc|Feature_HasMSA, 292 /* adds_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5447  { Feature_HasStdEnc|Feature_HasMSA, 301 /* adds_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5448  { Feature_HasStdEnc|Feature_HasMSA, 310 /* adds_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5449  { Feature_HasDSP|Feature_InMicroMips, 319 /* addsc */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
5450  { Feature_HasDSP, 319 /* addsc */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
5451  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 325 /* addu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5452  { Feature_HasStdEnc|Feature_NotInMicroMips, 325 /* addu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5453  { Feature_InMicroMips, 325 /* addu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5454  { 0, 325 /* addu */, MCK_GPR32AsmReg, 1 /* 0 */ },
5455  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 325 /* addu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
5456  { Feature_HasStdEnc|Feature_NotInMicroMips, 325 /* addu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
5457  { Feature_InMicroMips, 325 /* addu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
5458  { 0, 325 /* addu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5459  { Feature_HasDSPR2|Feature_InMicroMips, 330 /* addu.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
5460  { Feature_HasDSPR2, 330 /* addu.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
5461  { Feature_HasDSP|Feature_InMicroMips, 338 /* addu.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
5462  { Feature_HasDSP, 338 /* addu.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
5463  { Feature_InMicroMips|Feature_NotMips32r6|Feature_NotMips64r6, 346 /* addu16 */, MCK_GPRMM16AsmReg, 7 /* 0, 1, 2 */ },
5464  { Feature_HasMicroMips32r6, 346 /* addu16 */, MCK_GPRMM16AsmReg, 7 /* 0, 1, 2 */ },
5465  { Feature_HasDSPR2|Feature_InMicroMips, 353 /* addu_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
5466  { Feature_HasDSPR2, 353 /* addu_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
5467  { Feature_HasDSP|Feature_InMicroMips, 363 /* addu_s.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
5468  { Feature_HasDSP, 363 /* addu_s.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
5469  { Feature_HasDSPR2|Feature_InMicroMips, 373 /* adduh.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
5470  { Feature_HasDSPR2, 373 /* adduh.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
5471  { Feature_HasDSPR2|Feature_InMicroMips, 382 /* adduh_r.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
5472  { Feature_HasDSPR2, 382 /* adduh_r.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
5473  { Feature_HasStdEnc|Feature_HasMSA, 393 /* addv.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5474  { Feature_HasStdEnc|Feature_HasMSA, 400 /* addv.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5475  { Feature_HasStdEnc|Feature_HasMSA, 407 /* addv.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5476  { Feature_HasStdEnc|Feature_HasMSA, 414 /* addv.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5477  { Feature_HasStdEnc|Feature_HasMSA, 421 /* addvi.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5478  { Feature_HasStdEnc|Feature_HasMSA, 429 /* addvi.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5479  { Feature_HasStdEnc|Feature_HasMSA, 437 /* addvi.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5480  { Feature_HasStdEnc|Feature_HasMSA, 445 /* addvi.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5481  { Feature_HasDSP|Feature_InMicroMips, 453 /* addwc */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
5482  { Feature_HasDSP, 453 /* addwc */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
5483  { Feature_HasStdEnc|Feature_HasMips32r6, 459 /* align */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
5484  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 459 /* align */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
5485  { Feature_HasStdEnc|Feature_HasMips32r6, 465 /* aluipc */, MCK_GPR32AsmReg, 1 /* 0 */ },
5486  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 465 /* aluipc */, MCK_GPR32AsmReg, 1 /* 0 */ },
5487  { Feature_HasStdEnc|Feature_NotInMicroMips, 472 /* and */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5488  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 472 /* and */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5489  { Feature_InMicroMips, 472 /* and */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5490  { 0, 472 /* and */, MCK_GPR32AsmReg, 1 /* 0 */ },
5491  { Feature_HasStdEnc|Feature_NotInMicroMips, 472 /* and */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
5492  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 472 /* and */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
5493  { Feature_InMicroMips, 472 /* and */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
5494  { 0, 472 /* and */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5495  { Feature_HasStdEnc|Feature_HasMSA, 476 /* and.v */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5496  { Feature_InMicroMips|Feature_NotMips32r6|Feature_NotMips64r6, 482 /* and16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
5497  { Feature_HasMicroMips32r6, 482 /* and16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
5498  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 488 /* andi */, MCK_GPR32AsmReg, 1 /* 0 */ },
5499  { Feature_HasStdEnc|Feature_NotInMicroMips, 488 /* andi */, MCK_GPR32AsmReg, 1 /* 0 */ },
5500  { Feature_InMicroMips, 488 /* andi */, MCK_GPR32AsmReg, 1 /* 0 */ },
5501  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 488 /* andi */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5502  { Feature_HasStdEnc|Feature_NotInMicroMips, 488 /* andi */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5503  { Feature_InMicroMips, 488 /* andi */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5504  { Feature_HasStdEnc|Feature_HasMSA, 493 /* andi.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5505  { Feature_InMicroMips|Feature_NotMips32r6|Feature_NotMips64r6, 500 /* andi16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
5506  { Feature_HasMicroMips32r6, 500 /* andi16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
5507  { Feature_HasDSPR2, 507 /* append */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5508  { Feature_HasStdEnc|Feature_HasMSA, 514 /* asub_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5509  { Feature_HasStdEnc|Feature_HasMSA, 523 /* asub_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5510  { Feature_HasStdEnc|Feature_HasMSA, 532 /* asub_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5511  { Feature_HasStdEnc|Feature_HasMSA, 541 /* asub_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5512  { Feature_HasStdEnc|Feature_HasMSA, 550 /* asub_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5513  { Feature_HasStdEnc|Feature_HasMSA, 559 /* asub_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5514  { Feature_HasStdEnc|Feature_HasMSA, 568 /* asub_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5515  { Feature_HasStdEnc|Feature_HasMSA, 577 /* asub_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5516  { Feature_HasStdEnc|Feature_HasMips32r6, 586 /* aui */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5517  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 586 /* aui */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5518  { Feature_HasStdEnc|Feature_HasMips32r6, 590 /* auipc */, MCK_GPR32AsmReg, 1 /* 0 */ },
5519  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 590 /* auipc */, MCK_GPR32AsmReg, 1 /* 0 */ },
5520  { Feature_HasStdEnc|Feature_HasMSA, 596 /* ave_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5521  { Feature_HasStdEnc|Feature_HasMSA, 604 /* ave_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5522  { Feature_HasStdEnc|Feature_HasMSA, 612 /* ave_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5523  { Feature_HasStdEnc|Feature_HasMSA, 620 /* ave_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5524  { Feature_HasStdEnc|Feature_HasMSA, 628 /* ave_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5525  { Feature_HasStdEnc|Feature_HasMSA, 636 /* ave_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5526  { Feature_HasStdEnc|Feature_HasMSA, 644 /* ave_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5527  { Feature_HasStdEnc|Feature_HasMSA, 652 /* ave_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5528  { Feature_HasStdEnc|Feature_HasMSA, 660 /* aver_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5529  { Feature_HasStdEnc|Feature_HasMSA, 669 /* aver_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5530  { Feature_HasStdEnc|Feature_HasMSA, 678 /* aver_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5531  { Feature_HasStdEnc|Feature_HasMSA, 687 /* aver_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5532  { Feature_HasStdEnc|Feature_HasMSA, 696 /* aver_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5533  { Feature_HasStdEnc|Feature_HasMSA, 705 /* aver_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5534  { Feature_HasStdEnc|Feature_HasMSA, 714 /* aver_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5535  { Feature_HasStdEnc|Feature_HasMSA, 723 /* aver_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5536  { Feature_InMicroMips, 732 /* b */, MCK_JumpTarget, 1 /* 0 */ },
5537  { Feature_InMips16Mode, 732 /* b */, MCK_JumpTarget, 1 /* 0 */ },
5538  { Feature_NotInMicroMips, 732 /* b */, MCK_JumpTarget, 1 /* 0 */ },
5539  { 0, 732 /* b */, MCK_JumpTarget, 1 /* 0 */ },
5540  { Feature_InMips16Mode, 732 /* b */, MCK_JumpTarget, 1 /* 0 */ },
5541  { Feature_InMicroMips, 734 /* b16 */, MCK_JumpTarget, 1 /* 0 */ },
5542  { Feature_HasCnMips, 738 /* baddu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
5543  { Feature_HasCnMips, 738 /* baddu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
5544  { Feature_HasStdEnc|Feature_HasMips32r6, 744 /* bal */, MCK_JumpTarget, 1 /* 0 */ },
5545  { Feature_NotMips32r6|Feature_NotMips64r6, 744 /* bal */, MCK_JumpTarget, 1 /* 0 */ },
5546  { Feature_HasStdEnc|Feature_HasMips32r6, 748 /* balc */, MCK_JumpTarget, 1 /* 0 */ },
5547  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 748 /* balc */, MCK_JumpTarget, 1 /* 0 */ },
5548  { Feature_HasDSPR2, 753 /* balign */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5549  { Feature_HasCnMips, 760 /* bbit0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
5550  { Feature_HasCnMips, 760 /* bbit0 */, MCK_JumpTarget, 4 /* 2 */ },
5551  { Feature_HasCnMips, 760 /* bbit0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
5552  { Feature_HasCnMips, 760 /* bbit0 */, MCK_JumpTarget, 4 /* 2 */ },
5553  { Feature_HasCnMips, 766 /* bbit032 */, MCK_GPR64AsmReg, 1 /* 0 */ },
5554  { Feature_HasCnMips, 766 /* bbit032 */, MCK_JumpTarget, 4 /* 2 */ },
5555  { Feature_HasCnMips, 774 /* bbit1 */, MCK_GPR64AsmReg, 1 /* 0 */ },
5556  { Feature_HasCnMips, 774 /* bbit1 */, MCK_JumpTarget, 4 /* 2 */ },
5557  { Feature_HasCnMips, 774 /* bbit1 */, MCK_GPR64AsmReg, 1 /* 0 */ },
5558  { Feature_HasCnMips, 774 /* bbit1 */, MCK_JumpTarget, 4 /* 2 */ },
5559  { Feature_HasCnMips, 780 /* bbit132 */, MCK_GPR64AsmReg, 1 /* 0 */ },
5560  { Feature_HasCnMips, 780 /* bbit132 */, MCK_JumpTarget, 4 /* 2 */ },
5561  { Feature_HasStdEnc|Feature_HasMips32r6, 788 /* bc */, MCK_JumpTarget, 1 /* 0 */ },
5562  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 788 /* bc */, MCK_JumpTarget, 1 /* 0 */ },
5563  { Feature_HasMicroMips32r6, 791 /* bc16 */, MCK_JumpTarget, 1 /* 0 */ },
5564  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat, 796 /* bc1eqz */, MCK_FGR64AsmReg, 1 /* 0 */ },
5565  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat, 796 /* bc1eqz */, MCK_JumpTarget, 2 /* 1 */ },
5566  { Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 803 /* bc1f */, MCK_JumpTarget, 1 /* 0 */ },
5567  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 803 /* bc1f */, MCK_FCCAsmReg, 1 /* 0 */ },
5568  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 803 /* bc1f */, MCK_JumpTarget, 2 /* 1 */ },
5569  { Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 808 /* bc1fl */, MCK_JumpTarget, 1 /* 0 */ },
5570  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 808 /* bc1fl */, MCK_FCCAsmReg, 1 /* 0 */ },
5571  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 808 /* bc1fl */, MCK_JumpTarget, 2 /* 1 */ },
5572  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat, 814 /* bc1nez */, MCK_FGR64AsmReg, 1 /* 0 */ },
5573  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat, 814 /* bc1nez */, MCK_JumpTarget, 2 /* 1 */ },
5574  { Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 821 /* bc1t */, MCK_JumpTarget, 1 /* 0 */ },
5575  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 821 /* bc1t */, MCK_FCCAsmReg, 1 /* 0 */ },
5576  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 821 /* bc1t */, MCK_JumpTarget, 2 /* 1 */ },
5577  { Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 826 /* bc1tl */, MCK_JumpTarget, 1 /* 0 */ },
5578  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 826 /* bc1tl */, MCK_FCCAsmReg, 1 /* 0 */ },
5579  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 826 /* bc1tl */, MCK_JumpTarget, 2 /* 1 */ },
5580  { Feature_HasStdEnc|Feature_HasMips32r6, 832 /* bc2eqz */, MCK_COP2AsmReg, 1 /* 0 */ },
5581  { Feature_HasStdEnc|Feature_HasMips32r6, 832 /* bc2eqz */, MCK_JumpTarget, 2 /* 1 */ },
5582  { Feature_HasStdEnc|Feature_HasMips32r6, 839 /* bc2nez */, MCK_COP2AsmReg, 1 /* 0 */ },
5583  { Feature_HasStdEnc|Feature_HasMips32r6, 839 /* bc2nez */, MCK_JumpTarget, 2 /* 1 */ },
5584  { Feature_HasStdEnc|Feature_HasMSA, 846 /* bclr.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5585  { Feature_HasStdEnc|Feature_HasMSA, 853 /* bclr.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5586  { Feature_HasStdEnc|Feature_HasMSA, 860 /* bclr.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5587  { Feature_HasStdEnc|Feature_HasMSA, 867 /* bclr.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5588  { Feature_HasStdEnc|Feature_HasMSA, 874 /* bclri.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5589  { Feature_HasStdEnc|Feature_HasMSA, 882 /* bclri.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5590  { Feature_HasStdEnc|Feature_HasMSA, 890 /* bclri.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5591  { Feature_HasStdEnc|Feature_HasMSA, 898 /* bclri.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5592  { Feature_HasStdEnc, 906 /* beq */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5593  { Feature_HasStdEnc, 906 /* beq */, MCK_JumpTarget, 4 /* 2 */ },
5594  { Feature_InMicroMips, 906 /* beq */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5595  { Feature_InMicroMips, 906 /* beq */, MCK_JumpTarget, 4 /* 2 */ },
5596  { 0, 906 /* beq */, MCK_GPR32AsmReg, 1 /* 0 */ },
5597  { 0, 906 /* beq */, MCK_JumpTarget, 4 /* 2 */ },
5598  { Feature_HasStdEnc|Feature_HasMips32r6, 910 /* beqc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5599  { Feature_HasStdEnc|Feature_HasMips32r6, 910 /* beqc */, MCK_JumpTarget, 4 /* 2 */ },
5600  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 915 /* beql */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5601  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 915 /* beql */, MCK_JumpTarget, 4 /* 2 */ },
5602  { Feature_InMips16Mode, 920 /* beqz */, MCK_JumpTarget, 2 /* 1 */ },
5603  { 0, 920 /* beqz */, MCK_GPR32AsmReg, 1 /* 0 */ },
5604  { 0, 920 /* beqz */, MCK_JumpTarget, 2 /* 1 */ },
5605  { Feature_InMips16Mode, 920 /* beqz */, MCK_JumpTarget, 2 /* 1 */ },
5606  { Feature_InMicroMips, 925 /* beqz16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
5607  { Feature_InMicroMips, 925 /* beqz16 */, MCK_JumpTarget, 2 /* 1 */ },
5608  { Feature_HasStdEnc|Feature_HasMips32r6, 932 /* beqzalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
5609  { Feature_HasStdEnc|Feature_HasMips32r6, 932 /* beqzalc */, MCK_JumpTarget, 2 /* 1 */ },
5610  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 932 /* beqzalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
5611  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 932 /* beqzalc */, MCK_JumpTarget, 2 /* 1 */ },
5612  { Feature_HasStdEnc|Feature_HasMips32r6, 940 /* beqzc */, MCK_GPR32AsmReg, 1 /* 0 */ },
5613  { Feature_HasStdEnc|Feature_HasMips32r6, 940 /* beqzc */, MCK_JumpTarget, 2 /* 1 */ },
5614  { Feature_InMicroMips, 940 /* beqzc */, MCK_GPR32AsmReg, 1 /* 0 */ },
5615  { Feature_InMicroMips, 940 /* beqzc */, MCK_JumpTarget, 2 /* 1 */ },
5616  { Feature_HasMicroMips32r6, 946 /* beqzc16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
5617  { Feature_HasMicroMips32r6, 946 /* beqzc16 */, MCK_JumpTarget, 2 /* 1 */ },
5618  { 0, 954 /* beqzl */, MCK_GPR32AsmReg, 1 /* 0 */ },
5619  { 0, 954 /* beqzl */, MCK_JumpTarget, 2 /* 1 */ },
5620  { 0, 960 /* bge */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5621  { 0, 960 /* bge */, MCK_JumpTarget, 4 /* 2 */ },
5622  { 0, 960 /* bge */, MCK_GPR32AsmReg, 1 /* 0 */ },
5623  { 0, 960 /* bge */, MCK_JumpTarget, 4 /* 2 */ },
5624  { Feature_HasStdEnc|Feature_HasMips32r6, 964 /* bgec */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5625  { Feature_HasStdEnc|Feature_HasMips32r6, 964 /* bgec */, MCK_JumpTarget, 4 /* 2 */ },
5626  { Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 969 /* bgel */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5627  { Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 969 /* bgel */, MCK_JumpTarget, 4 /* 2 */ },
5628  { Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 969 /* bgel */, MCK_GPR32AsmReg, 1 /* 0 */ },
5629  { Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 969 /* bgel */, MCK_JumpTarget, 4 /* 2 */ },
5630  { 0, 974 /* bgeu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5631  { 0, 974 /* bgeu */, MCK_JumpTarget, 4 /* 2 */ },
5632  { 0, 974 /* bgeu */, MCK_GPR32AsmReg, 1 /* 0 */ },
5633  { 0, 974 /* bgeu */, MCK_JumpTarget, 4 /* 2 */ },
5634  { Feature_HasStdEnc|Feature_HasMips32r6, 979 /* bgeuc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5635  { Feature_HasStdEnc|Feature_HasMips32r6, 979 /* bgeuc */, MCK_JumpTarget, 4 /* 2 */ },
5636  { Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 985 /* bgeul */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5637  { Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 985 /* bgeul */, MCK_JumpTarget, 4 /* 2 */ },
5638  { Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 985 /* bgeul */, MCK_GPR32AsmReg, 1 /* 0 */ },
5639  { Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 985 /* bgeul */, MCK_JumpTarget, 4 /* 2 */ },
5640  { Feature_HasStdEnc, 991 /* bgez */, MCK_GPR32AsmReg, 1 /* 0 */ },
5641  { Feature_HasStdEnc, 991 /* bgez */, MCK_JumpTarget, 2 /* 1 */ },
5642  { Feature_InMicroMips, 991 /* bgez */, MCK_GPR32AsmReg, 1 /* 0 */ },
5643  { Feature_InMicroMips, 991 /* bgez */, MCK_JumpTarget, 2 /* 1 */ },
5644  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 996 /* bgezal */, MCK_GPR32AsmReg, 1 /* 0 */ },
5645  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 996 /* bgezal */, MCK_JumpTarget, 2 /* 1 */ },
5646  { Feature_InMicroMips, 996 /* bgezal */, MCK_GPR32AsmReg, 1 /* 0 */ },
5647  { Feature_InMicroMips, 996 /* bgezal */, MCK_JumpTarget, 2 /* 1 */ },
5648  { Feature_HasStdEnc|Feature_HasMips32r6, 1003 /* bgezalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
5649  { Feature_HasStdEnc|Feature_HasMips32r6, 1003 /* bgezalc */, MCK_JumpTarget, 2 /* 1 */ },
5650  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 1003 /* bgezalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
5651  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 1003 /* bgezalc */, MCK_JumpTarget, 2 /* 1 */ },
5652  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1011 /* bgezall */, MCK_GPR32AsmReg, 1 /* 0 */ },
5653  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1011 /* bgezall */, MCK_JumpTarget, 2 /* 1 */ },
5654  { Feature_InMicroMips, 1019 /* bgezals */, MCK_GPR32AsmReg, 1 /* 0 */ },
5655  { Feature_InMicroMips, 1019 /* bgezals */, MCK_JumpTarget, 2 /* 1 */ },
5656  { Feature_HasStdEnc|Feature_HasMips32r6, 1027 /* bgezc */, MCK_GPR32AsmReg, 1 /* 0 */ },
5657  { Feature_HasStdEnc|Feature_HasMips32r6, 1027 /* bgezc */, MCK_JumpTarget, 2 /* 1 */ },
5658  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1033 /* bgezl */, MCK_GPR32AsmReg, 1 /* 0 */ },
5659  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1033 /* bgezl */, MCK_JumpTarget, 2 /* 1 */ },
5660  { 0, 1039 /* bgt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5661  { 0, 1039 /* bgt */, MCK_JumpTarget, 4 /* 2 */ },
5662  { 0, 1039 /* bgt */, MCK_GPR32AsmReg, 1 /* 0 */ },
5663  { 0, 1039 /* bgt */, MCK_JumpTarget, 4 /* 2 */ },
5664  { Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1043 /* bgtl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5665  { Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1043 /* bgtl */, MCK_JumpTarget, 4 /* 2 */ },
5666  { Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1043 /* bgtl */, MCK_GPR32AsmReg, 1 /* 0 */ },
5667  { Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1043 /* bgtl */, MCK_JumpTarget, 4 /* 2 */ },
5668  { 0, 1048 /* bgtu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5669  { 0, 1048 /* bgtu */, MCK_JumpTarget, 4 /* 2 */ },
5670  { 0, 1048 /* bgtu */, MCK_GPR32AsmReg, 1 /* 0 */ },
5671  { 0, 1048 /* bgtu */, MCK_JumpTarget, 4 /* 2 */ },
5672  { Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1053 /* bgtul */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5673  { Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1053 /* bgtul */, MCK_JumpTarget, 4 /* 2 */ },
5674  { Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1053 /* bgtul */, MCK_GPR32AsmReg, 1 /* 0 */ },
5675  { Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1053 /* bgtul */, MCK_JumpTarget, 4 /* 2 */ },
5676  { Feature_HasStdEnc, 1059 /* bgtz */, MCK_GPR32AsmReg, 1 /* 0 */ },
5677  { Feature_HasStdEnc, 1059 /* bgtz */, MCK_JumpTarget, 2 /* 1 */ },
5678  { Feature_InMicroMips, 1059 /* bgtz */, MCK_GPR32AsmReg, 1 /* 0 */ },
5679  { Feature_InMicroMips, 1059 /* bgtz */, MCK_JumpTarget, 2 /* 1 */ },
5680  { Feature_HasStdEnc|Feature_HasMips32r6, 1064 /* bgtzalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
5681  { Feature_HasStdEnc|Feature_HasMips32r6, 1064 /* bgtzalc */, MCK_JumpTarget, 2 /* 1 */ },
5682  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 1064 /* bgtzalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
5683  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 1064 /* bgtzalc */, MCK_JumpTarget, 2 /* 1 */ },
5684  { Feature_HasStdEnc|Feature_HasMips32r6, 1072 /* bgtzc */, MCK_GPR32AsmReg, 1 /* 0 */ },
5685  { Feature_HasStdEnc|Feature_HasMips32r6, 1072 /* bgtzc */, MCK_JumpTarget, 2 /* 1 */ },
5686  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1078 /* bgtzl */, MCK_GPR32AsmReg, 1 /* 0 */ },
5687  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1078 /* bgtzl */, MCK_JumpTarget, 2 /* 1 */ },
5688  { Feature_HasStdEnc|Feature_HasMSA, 1084 /* binsl.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5689  { Feature_HasStdEnc|Feature_HasMSA, 1092 /* binsl.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5690  { Feature_HasStdEnc|Feature_HasMSA, 1100 /* binsl.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5691  { Feature_HasStdEnc|Feature_HasMSA, 1108 /* binsl.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5692  { Feature_HasStdEnc|Feature_HasMSA, 1116 /* binsli.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5693  { Feature_HasStdEnc|Feature_HasMSA, 1125 /* binsli.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5694  { Feature_HasStdEnc|Feature_HasMSA, 1134 /* binsli.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5695  { Feature_HasStdEnc|Feature_HasMSA, 1143 /* binsli.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5696  { Feature_HasStdEnc|Feature_HasMSA, 1152 /* binsr.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5697  { Feature_HasStdEnc|Feature_HasMSA, 1160 /* binsr.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5698  { Feature_HasStdEnc|Feature_HasMSA, 1168 /* binsr.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5699  { Feature_HasStdEnc|Feature_HasMSA, 1176 /* binsr.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5700  { Feature_HasStdEnc|Feature_HasMSA, 1184 /* binsri.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5701  { Feature_HasStdEnc|Feature_HasMSA, 1193 /* binsri.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5702  { Feature_HasStdEnc|Feature_HasMSA, 1202 /* binsri.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5703  { Feature_HasStdEnc|Feature_HasMSA, 1211 /* binsri.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5704  { Feature_HasDSP, 1220 /* bitrev */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5705  { Feature_HasStdEnc|Feature_HasMips32r6, 1227 /* bitswap */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5706  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 1227 /* bitswap */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5707  { 0, 1235 /* ble */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5708  { 0, 1235 /* ble */, MCK_JumpTarget, 4 /* 2 */ },
5709  { 0, 1235 /* ble */, MCK_GPR32AsmReg, 1 /* 0 */ },
5710  { 0, 1235 /* ble */, MCK_JumpTarget, 4 /* 2 */ },
5711  { Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1239 /* blel */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5712  { Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1239 /* blel */, MCK_JumpTarget, 4 /* 2 */ },
5713  { Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1239 /* blel */, MCK_GPR32AsmReg, 1 /* 0 */ },
5714  { Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1239 /* blel */, MCK_JumpTarget, 4 /* 2 */ },
5715  { 0, 1244 /* bleu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5716  { 0, 1244 /* bleu */, MCK_JumpTarget, 4 /* 2 */ },
5717  { 0, 1244 /* bleu */, MCK_GPR32AsmReg, 1 /* 0 */ },
5718  { 0, 1244 /* bleu */, MCK_JumpTarget, 4 /* 2 */ },
5719  { Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1249 /* bleul */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5720  { Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1249 /* bleul */, MCK_JumpTarget, 4 /* 2 */ },
5721  { Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1249 /* bleul */, MCK_GPR32AsmReg, 1 /* 0 */ },
5722  { Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1249 /* bleul */, MCK_JumpTarget, 4 /* 2 */ },
5723  { Feature_HasStdEnc, 1255 /* blez */, MCK_GPR32AsmReg, 1 /* 0 */ },
5724  { Feature_HasStdEnc, 1255 /* blez */, MCK_JumpTarget, 2 /* 1 */ },
5725  { Feature_InMicroMips, 1255 /* blez */, MCK_GPR32AsmReg, 1 /* 0 */ },
5726  { Feature_InMicroMips, 1255 /* blez */, MCK_JumpTarget, 2 /* 1 */ },
5727  { Feature_HasStdEnc|Feature_HasMips32r6, 1260 /* blezalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
5728  { Feature_HasStdEnc|Feature_HasMips32r6, 1260 /* blezalc */, MCK_JumpTarget, 2 /* 1 */ },
5729  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 1260 /* blezalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
5730  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 1260 /* blezalc */, MCK_JumpTarget, 2 /* 1 */ },
5731  { Feature_HasStdEnc|Feature_HasMips32r6, 1268 /* blezc */, MCK_GPR32AsmReg, 1 /* 0 */ },
5732  { Feature_HasStdEnc|Feature_HasMips32r6, 1268 /* blezc */, MCK_JumpTarget, 2 /* 1 */ },
5733  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1274 /* blezl */, MCK_GPR32AsmReg, 1 /* 0 */ },
5734  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1274 /* blezl */, MCK_JumpTarget, 2 /* 1 */ },
5735  { 0, 1280 /* blt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5736  { 0, 1280 /* blt */, MCK_JumpTarget, 4 /* 2 */ },
5737  { 0, 1280 /* blt */, MCK_GPR32AsmReg, 1 /* 0 */ },
5738  { 0, 1280 /* blt */, MCK_JumpTarget, 4 /* 2 */ },
5739  { Feature_HasStdEnc|Feature_HasMips32r6, 1284 /* bltc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5740  { Feature_HasStdEnc|Feature_HasMips32r6, 1284 /* bltc */, MCK_JumpTarget, 4 /* 2 */ },
5741  { Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1289 /* bltl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5742  { Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1289 /* bltl */, MCK_JumpTarget, 4 /* 2 */ },
5743  { Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1289 /* bltl */, MCK_GPR32AsmReg, 1 /* 0 */ },
5744  { Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1289 /* bltl */, MCK_JumpTarget, 4 /* 2 */ },
5745  { 0, 1294 /* bltu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5746  { 0, 1294 /* bltu */, MCK_JumpTarget, 4 /* 2 */ },
5747  { 0, 1294 /* bltu */, MCK_GPR32AsmReg, 1 /* 0 */ },
5748  { 0, 1294 /* bltu */, MCK_JumpTarget, 4 /* 2 */ },
5749  { Feature_HasStdEnc|Feature_HasMips32r6, 1299 /* bltuc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5750  { Feature_HasStdEnc|Feature_HasMips32r6, 1299 /* bltuc */, MCK_JumpTarget, 4 /* 2 */ },
5751  { Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1305 /* bltul */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5752  { Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1305 /* bltul */, MCK_JumpTarget, 4 /* 2 */ },
5753  { Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1305 /* bltul */, MCK_GPR32AsmReg, 1 /* 0 */ },
5754  { Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1305 /* bltul */, MCK_JumpTarget, 4 /* 2 */ },
5755  { Feature_HasStdEnc, 1311 /* bltz */, MCK_GPR32AsmReg, 1 /* 0 */ },
5756  { Feature_HasStdEnc, 1311 /* bltz */, MCK_JumpTarget, 2 /* 1 */ },
5757  { Feature_InMicroMips, 1311 /* bltz */, MCK_GPR32AsmReg, 1 /* 0 */ },
5758  { Feature_InMicroMips, 1311 /* bltz */, MCK_JumpTarget, 2 /* 1 */ },
5759  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 1316 /* bltzal */, MCK_GPR32AsmReg, 1 /* 0 */ },
5760  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 1316 /* bltzal */, MCK_JumpTarget, 2 /* 1 */ },
5761  { Feature_InMicroMips, 1316 /* bltzal */, MCK_GPR32AsmReg, 1 /* 0 */ },
5762  { Feature_InMicroMips, 1316 /* bltzal */, MCK_JumpTarget, 2 /* 1 */ },
5763  { Feature_HasStdEnc|Feature_HasMips32r6, 1323 /* bltzalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
5764  { Feature_HasStdEnc|Feature_HasMips32r6, 1323 /* bltzalc */, MCK_JumpTarget, 2 /* 1 */ },
5765  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 1323 /* bltzalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
5766  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 1323 /* bltzalc */, MCK_JumpTarget, 2 /* 1 */ },
5767  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1331 /* bltzall */, MCK_GPR32AsmReg, 1 /* 0 */ },
5768  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1331 /* bltzall */, MCK_JumpTarget, 2 /* 1 */ },
5769  { Feature_InMicroMips, 1339 /* bltzals */, MCK_GPR32AsmReg, 1 /* 0 */ },
5770  { Feature_InMicroMips, 1339 /* bltzals */, MCK_JumpTarget, 2 /* 1 */ },
5771  { Feature_HasStdEnc|Feature_HasMips32r6, 1347 /* bltzc */, MCK_GPR32AsmReg, 1 /* 0 */ },
5772  { Feature_HasStdEnc|Feature_HasMips32r6, 1347 /* bltzc */, MCK_JumpTarget, 2 /* 1 */ },
5773  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1353 /* bltzl */, MCK_GPR32AsmReg, 1 /* 0 */ },
5774  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1353 /* bltzl */, MCK_JumpTarget, 2 /* 1 */ },
5775  { Feature_HasStdEnc|Feature_HasMSA, 1359 /* bmnz.v */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5776  { Feature_HasStdEnc|Feature_HasMSA, 1366 /* bmnzi.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5777  { Feature_HasStdEnc|Feature_HasMSA, 1374 /* bmz.v */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5778  { Feature_HasStdEnc|Feature_HasMSA, 1380 /* bmzi.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5779  { Feature_HasStdEnc, 1387 /* bne */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5780  { Feature_HasStdEnc, 1387 /* bne */, MCK_JumpTarget, 4 /* 2 */ },
5781  { Feature_InMicroMips, 1387 /* bne */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5782  { Feature_InMicroMips, 1387 /* bne */, MCK_JumpTarget, 4 /* 2 */ },
5783  { 0, 1387 /* bne */, MCK_GPR32AsmReg, 1 /* 0 */ },
5784  { 0, 1387 /* bne */, MCK_JumpTarget, 4 /* 2 */ },
5785  { Feature_HasStdEnc|Feature_HasMips32r6, 1391 /* bnec */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5786  { Feature_HasStdEnc|Feature_HasMips32r6, 1391 /* bnec */, MCK_JumpTarget, 4 /* 2 */ },
5787  { Feature_HasStdEnc|Feature_HasMSA, 1396 /* bneg.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5788  { Feature_HasStdEnc|Feature_HasMSA, 1403 /* bneg.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5789  { Feature_HasStdEnc|Feature_HasMSA, 1410 /* bneg.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5790  { Feature_HasStdEnc|Feature_HasMSA, 1417 /* bneg.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5791  { Feature_HasStdEnc|Feature_HasMSA, 1424 /* bnegi.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5792  { Feature_HasStdEnc|Feature_HasMSA, 1432 /* bnegi.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5793  { Feature_HasStdEnc|Feature_HasMSA, 1440 /* bnegi.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5794  { Feature_HasStdEnc|Feature_HasMSA, 1448 /* bnegi.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5795  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1456 /* bnel */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5796  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1456 /* bnel */, MCK_JumpTarget, 4 /* 2 */ },
5797  { Feature_InMips16Mode, 1461 /* bnez */, MCK_JumpTarget, 2 /* 1 */ },
5798  { 0, 1461 /* bnez */, MCK_GPR32AsmReg, 1 /* 0 */ },
5799  { 0, 1461 /* bnez */, MCK_JumpTarget, 2 /* 1 */ },
5800  { Feature_InMips16Mode, 1461 /* bnez */, MCK_JumpTarget, 2 /* 1 */ },
5801  { Feature_InMicroMips, 1466 /* bnez16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
5802  { Feature_InMicroMips, 1466 /* bnez16 */, MCK_JumpTarget, 2 /* 1 */ },
5803  { Feature_HasStdEnc|Feature_HasMips32r6, 1473 /* bnezalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
5804  { Feature_HasStdEnc|Feature_HasMips32r6, 1473 /* bnezalc */, MCK_JumpTarget, 2 /* 1 */ },
5805  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 1473 /* bnezalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
5806  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 1473 /* bnezalc */, MCK_JumpTarget, 2 /* 1 */ },
5807  { Feature_HasStdEnc|Feature_HasMips32r6, 1481 /* bnezc */, MCK_GPR32AsmReg, 1 /* 0 */ },
5808  { Feature_HasStdEnc|Feature_HasMips32r6, 1481 /* bnezc */, MCK_JumpTarget, 2 /* 1 */ },
5809  { Feature_InMicroMips, 1481 /* bnezc */, MCK_GPR32AsmReg, 1 /* 0 */ },
5810  { Feature_InMicroMips, 1481 /* bnezc */, MCK_JumpTarget, 2 /* 1 */ },
5811  { Feature_HasMicroMips32r6, 1487 /* bnezc16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
5812  { Feature_HasMicroMips32r6, 1487 /* bnezc16 */, MCK_JumpTarget, 2 /* 1 */ },
5813  { 0, 1495 /* bnezl */, MCK_GPR32AsmReg, 1 /* 0 */ },
5814  { 0, 1495 /* bnezl */, MCK_JumpTarget, 2 /* 1 */ },
5815  { Feature_HasStdEnc|Feature_HasMips32r6, 1501 /* bnvc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5816  { Feature_HasStdEnc|Feature_HasMips32r6, 1501 /* bnvc */, MCK_JumpTarget, 4 /* 2 */ },
5817  { Feature_HasStdEnc|Feature_HasMSA, 1506 /* bnz.b */, MCK_MSA128AsmReg, 1 /* 0 */ },
5818  { Feature_HasStdEnc|Feature_HasMSA, 1506 /* bnz.b */, MCK_JumpTarget, 2 /* 1 */ },
5819  { Feature_HasStdEnc|Feature_HasMSA, 1512 /* bnz.d */, MCK_MSA128AsmReg, 1 /* 0 */ },
5820  { Feature_HasStdEnc|Feature_HasMSA, 1512 /* bnz.d */, MCK_JumpTarget, 2 /* 1 */ },
5821  { Feature_HasStdEnc|Feature_HasMSA, 1518 /* bnz.h */, MCK_MSA128AsmReg, 1 /* 0 */ },
5822  { Feature_HasStdEnc|Feature_HasMSA, 1518 /* bnz.h */, MCK_JumpTarget, 2 /* 1 */ },
5823  { Feature_HasStdEnc|Feature_HasMSA, 1524 /* bnz.v */, MCK_MSA128AsmReg, 1 /* 0 */ },
5824  { Feature_HasStdEnc|Feature_HasMSA, 1524 /* bnz.v */, MCK_JumpTarget, 2 /* 1 */ },
5825  { Feature_HasStdEnc|Feature_HasMSA, 1530 /* bnz.w */, MCK_MSA128AsmReg, 1 /* 0 */ },
5826  { Feature_HasStdEnc|Feature_HasMSA, 1530 /* bnz.w */, MCK_JumpTarget, 2 /* 1 */ },
5827  { Feature_HasStdEnc|Feature_HasMips32r6, 1536 /* bovc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5828  { Feature_HasStdEnc|Feature_HasMips32r6, 1536 /* bovc */, MCK_JumpTarget, 4 /* 2 */ },
5829  { Feature_HasDSP, 1541 /* bposge32 */, MCK_JumpTarget, 1 /* 0 */ },
5830  { Feature_HasStdEnc|Feature_HasMSA, 1564 /* bsel.v */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5831  { Feature_HasStdEnc|Feature_HasMSA, 1571 /* bseli.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5832  { Feature_HasStdEnc|Feature_HasMSA, 1579 /* bset.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5833  { Feature_HasStdEnc|Feature_HasMSA, 1586 /* bset.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5834  { Feature_HasStdEnc|Feature_HasMSA, 1593 /* bset.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5835  { Feature_HasStdEnc|Feature_HasMSA, 1600 /* bset.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5836  { Feature_HasStdEnc|Feature_HasMSA, 1607 /* bseti.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5837  { Feature_HasStdEnc|Feature_HasMSA, 1615 /* bseti.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5838  { Feature_HasStdEnc|Feature_HasMSA, 1623 /* bseti.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5839  { Feature_HasStdEnc|Feature_HasMSA, 1631 /* bseti.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5840  { Feature_HasStdEnc|Feature_HasMSA, 1651 /* bz.b */, MCK_MSA128AsmReg, 1 /* 0 */ },
5841  { Feature_HasStdEnc|Feature_HasMSA, 1651 /* bz.b */, MCK_JumpTarget, 2 /* 1 */ },
5842  { Feature_HasStdEnc|Feature_HasMSA, 1656 /* bz.d */, MCK_MSA128AsmReg, 1 /* 0 */ },
5843  { Feature_HasStdEnc|Feature_HasMSA, 1656 /* bz.d */, MCK_JumpTarget, 2 /* 1 */ },
5844  { Feature_HasStdEnc|Feature_HasMSA, 1661 /* bz.h */, MCK_MSA128AsmReg, 1 /* 0 */ },
5845  { Feature_HasStdEnc|Feature_HasMSA, 1661 /* bz.h */, MCK_JumpTarget, 2 /* 1 */ },
5846  { Feature_HasStdEnc|Feature_HasMSA, 1666 /* bz.v */, MCK_MSA128AsmReg, 1 /* 0 */ },
5847  { Feature_HasStdEnc|Feature_HasMSA, 1666 /* bz.v */, MCK_JumpTarget, 2 /* 1 */ },
5848  { Feature_HasStdEnc|Feature_HasMSA, 1671 /* bz.w */, MCK_MSA128AsmReg, 1 /* 0 */ },
5849  { Feature_HasStdEnc|Feature_HasMSA, 1671 /* bz.w */, MCK_JumpTarget, 2 /* 1 */ },
5850  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1676 /* c.eq.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
5851  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1676 /* c.eq.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
5852  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1683 /* c.eq.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
5853  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1690 /* c.f.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
5854  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1690 /* c.f.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
5855  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1696 /* c.f.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
5856  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1702 /* c.le.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
5857  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1702 /* c.le.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
5858  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1709 /* c.le.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
5859  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1716 /* c.lt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
5860  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1716 /* c.lt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
5861  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1723 /* c.lt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
5862  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1730 /* c.nge.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
5863  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1730 /* c.nge.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
5864  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1738 /* c.nge.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
5865  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1746 /* c.ngl.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
5866  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1746 /* c.ngl.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
5867  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1754 /* c.ngl.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
5868  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1762 /* c.ngle.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
5869  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1762 /* c.ngle.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
5870  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1771 /* c.ngle.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
5871  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1780 /* c.ngt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
5872  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1780 /* c.ngt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
5873  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1788 /* c.ngt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
5874  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1796 /* c.ole.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
5875  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1796 /* c.ole.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
5876  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1804 /* c.ole.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
5877  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1812 /* c.olt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
5878  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1812 /* c.olt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
5879  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1820 /* c.olt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
5880  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1828 /* c.seq.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
5881  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1828 /* c.seq.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
5882  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1836 /* c.seq.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
5883  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1844 /* c.sf.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
5884  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1844 /* c.sf.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
5885  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1851 /* c.sf.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
5886  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1858 /* c.ueq.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
5887  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1858 /* c.ueq.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
5888  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1866 /* c.ueq.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
5889  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1874 /* c.ule.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
5890  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1874 /* c.ule.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
5891  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1882 /* c.ule.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
5892  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1890 /* c.ult.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
5893  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1890 /* c.ult.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
5894  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1898 /* c.ult.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
5895  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1906 /* c.un.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
5896  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1906 /* c.un.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
5897  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 1913 /* c.un.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
5898  { Feature_HasStdEnc|Feature_HasMips32r6, 1920 /* cache */, MCK_MemOffsetSimm9, 2 /* 1 */ },
5899  { Feature_HasStdEnc|Feature_HasMips3_32|Feature_NotMips32r6|Feature_NotMips64r6, 1920 /* cache */, MCK_Mem, 2 /* 1 */ },
5900  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 1920 /* cache */, MCK_Mem, 2 /* 1 */ },
5901  { Feature_InMicroMips, 1920 /* cache */, MCK_Mem, 2 /* 1 */ },
5902  { Feature_HasStdEnc|Feature_HasEVA, 1926 /* cachee */, MCK_Mem, 2 /* 1 */ },
5903  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 1926 /* cachee */, MCK_Mem, 2 /* 1 */ },
5904  { Feature_InMicroMips, 1926 /* cachee */, MCK_Mem, 2 /* 1 */ },
5905  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1933 /* ceil.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
5906  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 1933 /* ceil.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
5907  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1942 /* ceil.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
5908  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1942 /* ceil.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
5909  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 1942 /* ceil.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
5910  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 1942 /* ceil.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
5911  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 1951 /* ceil.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
5912  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 1951 /* ceil.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
5913  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 1951 /* ceil.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
5914  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 1951 /* ceil.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
5915  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 1951 /* ceil.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
5916  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 1951 /* ceil.w.d */, MCK_FGR64AsmReg, 2 /* 1 */ },
5917  { Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat, 1960 /* ceil.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
5918  { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_InMicroMips, 1960 /* ceil.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
5919  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 1960 /* ceil.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
5920  { Feature_HasStdEnc|Feature_HasMSA, 1969 /* ceq.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5921  { Feature_HasStdEnc|Feature_HasMSA, 1975 /* ceq.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5922  { Feature_HasStdEnc|Feature_HasMSA, 1981 /* ceq.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5923  { Feature_HasStdEnc|Feature_HasMSA, 1987 /* ceq.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5924  { Feature_HasStdEnc|Feature_HasMSA, 1993 /* ceqi.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5925  { Feature_HasStdEnc|Feature_HasMSA, 2000 /* ceqi.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5926  { Feature_HasStdEnc|Feature_HasMSA, 2007 /* ceqi.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5927  { Feature_HasStdEnc|Feature_HasMSA, 2014 /* ceqi.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5928  { Feature_HasStdEnc|Feature_IsNotSoftFloat, 2021 /* cfc1 */, MCK_CCRAsmReg, 2 /* 1 */ },
5929  { Feature_HasStdEnc|Feature_IsNotSoftFloat, 2021 /* cfc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
5930  { Feature_HasStdEnc|Feature_HasMSA, 2026 /* cfcmsa */, MCK_GPR32AsmReg, 1 /* 0 */ },
5931  { Feature_HasStdEnc|Feature_HasMSA, 2026 /* cfcmsa */, MCK_MSACtrlAsmReg, 2 /* 1 */ },
5932  { Feature_HasCnMips, 2033 /* cins */, MCK_GPR64AsmReg, 1 /* 0 */ },
5933  { Feature_HasCnMips, 2033 /* cins */, MCK_GPR64AsmReg, 1 /* 0 */ },
5934  { Feature_HasCnMips, 2033 /* cins */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
5935  { Feature_HasCnMips, 2033 /* cins */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
5936  { Feature_HasCnMips, 2038 /* cins32 */, MCK_GPR64AsmReg, 1 /* 0 */ },
5937  { Feature_HasCnMips, 2038 /* cins32 */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
5938  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2045 /* class.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
5939  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 2045 /* class.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
5940  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2053 /* class.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
5941  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 2053 /* class.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
5942  { Feature_HasStdEnc|Feature_HasMSA, 2061 /* cle_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5943  { Feature_HasStdEnc|Feature_HasMSA, 2069 /* cle_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5944  { Feature_HasStdEnc|Feature_HasMSA, 2077 /* cle_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5945  { Feature_HasStdEnc|Feature_HasMSA, 2085 /* cle_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5946  { Feature_HasStdEnc|Feature_HasMSA, 2093 /* cle_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5947  { Feature_HasStdEnc|Feature_HasMSA, 2101 /* cle_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5948  { Feature_HasStdEnc|Feature_HasMSA, 2109 /* cle_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5949  { Feature_HasStdEnc|Feature_HasMSA, 2117 /* cle_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5950  { Feature_HasStdEnc|Feature_HasMSA, 2125 /* clei_s.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5951  { Feature_HasStdEnc|Feature_HasMSA, 2134 /* clei_s.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5952  { Feature_HasStdEnc|Feature_HasMSA, 2143 /* clei_s.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5953  { Feature_HasStdEnc|Feature_HasMSA, 2152 /* clei_s.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5954  { Feature_HasStdEnc|Feature_HasMSA, 2161 /* clei_u.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5955  { Feature_HasStdEnc|Feature_HasMSA, 2170 /* clei_u.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5956  { Feature_HasStdEnc|Feature_HasMSA, 2179 /* clei_u.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5957  { Feature_HasStdEnc|Feature_HasMSA, 2188 /* clei_u.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5958  { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6, 2197 /* clo */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5959  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 2197 /* clo */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5960  { Feature_HasStdEnc|Feature_HasMips32r6, 2197 /* clo */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5961  { Feature_InMicroMips, 2197 /* clo */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5962  { Feature_HasStdEnc|Feature_HasMSA, 2201 /* clt_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5963  { Feature_HasStdEnc|Feature_HasMSA, 2209 /* clt_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5964  { Feature_HasStdEnc|Feature_HasMSA, 2217 /* clt_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5965  { Feature_HasStdEnc|Feature_HasMSA, 2225 /* clt_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5966  { Feature_HasStdEnc|Feature_HasMSA, 2233 /* clt_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5967  { Feature_HasStdEnc|Feature_HasMSA, 2241 /* clt_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5968  { Feature_HasStdEnc|Feature_HasMSA, 2249 /* clt_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5969  { Feature_HasStdEnc|Feature_HasMSA, 2257 /* clt_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
5970  { Feature_HasStdEnc|Feature_HasMSA, 2265 /* clti_s.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5971  { Feature_HasStdEnc|Feature_HasMSA, 2274 /* clti_s.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5972  { Feature_HasStdEnc|Feature_HasMSA, 2283 /* clti_s.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5973  { Feature_HasStdEnc|Feature_HasMSA, 2292 /* clti_s.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5974  { Feature_HasStdEnc|Feature_HasMSA, 2301 /* clti_u.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5975  { Feature_HasStdEnc|Feature_HasMSA, 2310 /* clti_u.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5976  { Feature_HasStdEnc|Feature_HasMSA, 2319 /* clti_u.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5977  { Feature_HasStdEnc|Feature_HasMSA, 2328 /* clti_u.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
5978  { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6, 2337 /* clz */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5979  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 2337 /* clz */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5980  { Feature_HasStdEnc|Feature_HasMips32r6, 2337 /* clz */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5981  { Feature_InMicroMips, 2337 /* clz */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5982  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2345 /* cmp.af.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
5983  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2345 /* cmp.af.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
5984  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2345 /* cmp.af.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
5985  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2345 /* cmp.af.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
5986  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2354 /* cmp.af.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
5987  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2354 /* cmp.af.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
5988  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2363 /* cmp.eq.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
5989  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2363 /* cmp.eq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
5990  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2363 /* cmp.eq.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
5991  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2363 /* cmp.eq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
5992  { Feature_HasDSP, 2372 /* cmp.eq.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
5993  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2382 /* cmp.eq.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
5994  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2382 /* cmp.eq.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
5995  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2391 /* cmp.le.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
5996  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2391 /* cmp.le.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
5997  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2391 /* cmp.le.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
5998  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2391 /* cmp.le.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
5999  { Feature_HasDSP, 2400 /* cmp.le.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
6000  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2410 /* cmp.le.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
6001  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2410 /* cmp.le.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
6002  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2419 /* cmp.lt.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
6003  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2419 /* cmp.lt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
6004  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2419 /* cmp.lt.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
6005  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2419 /* cmp.lt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
6006  { Feature_HasDSP, 2428 /* cmp.lt.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
6007  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2438 /* cmp.lt.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
6008  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2438 /* cmp.lt.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
6009  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2447 /* cmp.saf.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
6010  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2447 /* cmp.saf.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
6011  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2447 /* cmp.saf.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
6012  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2447 /* cmp.saf.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
6013  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2457 /* cmp.saf.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
6014  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2457 /* cmp.saf.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
6015  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2467 /* cmp.seq.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
6016  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2467 /* cmp.seq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
6017  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2467 /* cmp.seq.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
6018  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2467 /* cmp.seq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
6019  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2477 /* cmp.seq.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
6020  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2477 /* cmp.seq.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
6021  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2487 /* cmp.sle.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
6022  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2487 /* cmp.sle.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
6023  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2487 /* cmp.sle.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
6024  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2487 /* cmp.sle.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
6025  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2497 /* cmp.sle.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
6026  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2497 /* cmp.sle.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
6027  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2507 /* cmp.slt.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
6028  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2507 /* cmp.slt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
6029  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2507 /* cmp.slt.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
6030  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2507 /* cmp.slt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
6031  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2517 /* cmp.slt.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
6032  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2517 /* cmp.slt.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
6033  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2527 /* cmp.sueq.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
6034  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2527 /* cmp.sueq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
6035  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2527 /* cmp.sueq.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
6036  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2527 /* cmp.sueq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
6037  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2538 /* cmp.sueq.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
6038  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2538 /* cmp.sueq.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
6039  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2549 /* cmp.sule.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
6040  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2549 /* cmp.sule.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
6041  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2549 /* cmp.sule.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
6042  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2549 /* cmp.sule.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
6043  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2560 /* cmp.sule.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
6044  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2560 /* cmp.sule.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
6045  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2571 /* cmp.sult.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
6046  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2571 /* cmp.sult.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
6047  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2571 /* cmp.sult.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
6048  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2571 /* cmp.sult.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
6049  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2582 /* cmp.sult.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
6050  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2582 /* cmp.sult.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
6051  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2593 /* cmp.sun.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
6052  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2593 /* cmp.sun.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
6053  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2593 /* cmp.sun.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
6054  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2593 /* cmp.sun.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
6055  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2603 /* cmp.sun.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
6056  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2603 /* cmp.sun.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
6057  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2613 /* cmp.ueq.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
6058  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2613 /* cmp.ueq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
6059  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2613 /* cmp.ueq.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
6060  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2613 /* cmp.ueq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
6061  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2623 /* cmp.ueq.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
6062  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2623 /* cmp.ueq.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
6063  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2633 /* cmp.ule.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
6064  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2633 /* cmp.ule.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
6065  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2633 /* cmp.ule.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
6066  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2633 /* cmp.ule.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
6067  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2643 /* cmp.ule.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
6068  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2643 /* cmp.ule.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
6069  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2653 /* cmp.ult.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
6070  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2653 /* cmp.ult.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
6071  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2653 /* cmp.ult.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
6072  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2653 /* cmp.ult.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
6073  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2663 /* cmp.ult.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
6074  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2663 /* cmp.ult.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
6075  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2673 /* cmp.un.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
6076  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2673 /* cmp.un.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
6077  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2673 /* cmp.un.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
6078  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2673 /* cmp.un.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
6079  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2682 /* cmp.un.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
6080  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2682 /* cmp.un.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
6081  { Feature_HasDSPR2, 2691 /* cmpgdu.eq.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
6082  { Feature_HasDSPR2, 2704 /* cmpgdu.le.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
6083  { Feature_HasDSPR2, 2717 /* cmpgdu.lt.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
6084  { Feature_HasDSP, 2730 /* cmpgu.eq.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
6085  { Feature_HasDSP, 2742 /* cmpgu.le.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
6086  { Feature_HasDSP, 2754 /* cmpgu.lt.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
6087  { Feature_HasDSP, 2771 /* cmpu.eq.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
6088  { Feature_HasDSP, 2782 /* cmpu.le.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
6089  { Feature_HasDSP, 2793 /* cmpu.lt.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
6090  { Feature_HasStdEnc|Feature_HasMSA, 2804 /* copy_s.b */, MCK_GPR32AsmReg, 1 /* 0 */ },
6091  { Feature_HasStdEnc|Feature_HasMSA, 2804 /* copy_s.b */, MCK_MSA128AsmReg, 2 /* 1 */ },
6092  { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 2813 /* copy_s.d */, MCK_GPR64AsmReg, 1 /* 0 */ },
6093  { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 2813 /* copy_s.d */, MCK_MSA128AsmReg, 2 /* 1 */ },
6094  { Feature_HasStdEnc|Feature_HasMSA, 2822 /* copy_s.h */, MCK_GPR32AsmReg, 1 /* 0 */ },
6095  { Feature_HasStdEnc|Feature_HasMSA, 2822 /* copy_s.h */, MCK_MSA128AsmReg, 2 /* 1 */ },
6096  { Feature_HasStdEnc|Feature_HasMSA, 2831 /* copy_s.w */, MCK_GPR32AsmReg, 1 /* 0 */ },
6097  { Feature_HasStdEnc|Feature_HasMSA, 2831 /* copy_s.w */, MCK_MSA128AsmReg, 2 /* 1 */ },
6098  { Feature_HasStdEnc|Feature_HasMSA, 2840 /* copy_u.b */, MCK_GPR32AsmReg, 1 /* 0 */ },
6099  { Feature_HasStdEnc|Feature_HasMSA, 2840 /* copy_u.b */, MCK_MSA128AsmReg, 2 /* 1 */ },
6100  { Feature_HasStdEnc|Feature_HasMSA, 2849 /* copy_u.h */, MCK_GPR32AsmReg, 1 /* 0 */ },
6101  { Feature_HasStdEnc|Feature_HasMSA, 2849 /* copy_u.h */, MCK_MSA128AsmReg, 2 /* 1 */ },
6102  { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 2858 /* copy_u.w */, MCK_GPR32AsmReg, 1 /* 0 */ },
6103  { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 2858 /* copy_u.w */, MCK_MSA128AsmReg, 2 /* 1 */ },
6104  { Feature_HasStdEnc|Feature_IsNotSoftFloat, 2867 /* ctc1 */, MCK_CCRAsmReg, 2 /* 1 */ },
6105  { Feature_HasStdEnc|Feature_IsNotSoftFloat, 2867 /* ctc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
6106  { Feature_HasStdEnc|Feature_HasMSA, 2872 /* ctcmsa */, MCK_GPR32AsmReg, 2 /* 1 */ },
6107  { Feature_HasStdEnc|Feature_HasMSA, 2872 /* ctcmsa */, MCK_MSACtrlAsmReg, 1 /* 0 */ },
6108  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2879 /* cvt.d.l */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
6109  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, 2879 /* cvt.d.l */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
6110  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat, 2887 /* cvt.d.s */, MCK_AFGR64AsmReg, 1 /* 0 */ },
6111  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat, 2887 /* cvt.d.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
6112  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2887 /* cvt.d.s */, MCK_AFGR64AsmReg, 2 /* 1 */ },
6113  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2887 /* cvt.d.s */, MCK_FGR32AsmReg, 1 /* 0 */ },
6114  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, 2887 /* cvt.d.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
6115  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, 2887 /* cvt.d.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
6116  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat, 2895 /* cvt.d.w */, MCK_AFGR64AsmReg, 1 /* 0 */ },
6117  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat, 2895 /* cvt.d.w */, MCK_FGR32AsmReg, 2 /* 1 */ },
6118  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2895 /* cvt.d.w */, MCK_AFGR64AsmReg, 2 /* 1 */ },
6119  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2895 /* cvt.d.w */, MCK_FGR32AsmReg, 1 /* 0 */ },
6120  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, 2895 /* cvt.d.w */, MCK_FGR32AsmReg, 2 /* 1 */ },
6121  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, 2895 /* cvt.d.w */, MCK_FGR64AsmReg, 1 /* 0 */ },
6122  { Feature_HasStdEnc|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2903 /* cvt.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
6123  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2903 /* cvt.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
6124  { Feature_HasStdEnc|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2911 /* cvt.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
6125  { Feature_HasStdEnc|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2911 /* cvt.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
6126  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2911 /* cvt.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
6127  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2911 /* cvt.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
6128  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2919 /* cvt.s.d */, MCK_AFGR64AsmReg, 1 /* 0 */ },
6129  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2919 /* cvt.s.d */, MCK_FGR32AsmReg, 2 /* 1 */ },
6130  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat, 2919 /* cvt.s.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
6131  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat, 2919 /* cvt.s.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
6132  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, 2919 /* cvt.s.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
6133  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, 2919 /* cvt.s.d */, MCK_FGR64AsmReg, 2 /* 1 */ },
6134  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2927 /* cvt.s.l */, MCK_FGR32AsmReg, 1 /* 0 */ },
6135  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2927 /* cvt.s.l */, MCK_FGR64AsmReg, 2 /* 1 */ },
6136  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2927 /* cvt.s.l */, MCK_FGR32AsmReg, 2 /* 1 */ },
6137  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2927 /* cvt.s.l */, MCK_FGR64AsmReg, 1 /* 0 */ },
6138  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2935 /* cvt.s.w */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
6139  { Feature_HasStdEnc|Feature_IsNotSoftFloat, 2935 /* cvt.s.w */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
6140  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat, 2943 /* cvt.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
6141  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat, 2943 /* cvt.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
6142  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2943 /* cvt.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
6143  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2943 /* cvt.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
6144  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, 2943 /* cvt.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
6145  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, 2943 /* cvt.w.d */, MCK_FGR64AsmReg, 2 /* 1 */ },
6146  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 2951 /* cvt.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
6147  { Feature_HasStdEnc|Feature_IsNotSoftFloat, 2951 /* cvt.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
6148  { Feature_HasStdEnc|Feature_HasMips3, 2959 /* dadd */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6149  { Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 2959 /* dadd */, MCK_GPR64AsmReg, 1 /* 0 */ },
6150  { Feature_HasStdEnc|Feature_HasMips3, 2959 /* dadd */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
6151  { Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 2959 /* dadd */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6152  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 2964 /* daddi */, MCK_GPR64AsmReg, 1 /* 0 */ },
6153  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 2964 /* daddi */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6154  { Feature_HasStdEnc|Feature_HasMips3, 2970 /* daddiu */, MCK_GPR64AsmReg, 1 /* 0 */ },
6155  { Feature_HasStdEnc|Feature_HasMips3, 2970 /* daddiu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6156  { Feature_HasStdEnc|Feature_HasMips3, 2977 /* daddu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6157  { Feature_HasMips3, 2977 /* daddu */, MCK_GPR64AsmReg, 1 /* 0 */ },
6158  { Feature_HasStdEnc|Feature_HasMips3, 2977 /* daddu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
6159  { Feature_HasMips3, 2977 /* daddu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6160  { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 2983 /* dahi */, MCK_GPR64AsmReg, 1 /* 0 */ },
6161  { Feature_HasStdEnc|Feature_HasMicroMips64r6, 2983 /* dahi */, MCK_GPR64AsmReg, 1 /* 0 */ },
6162  { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 2988 /* dalign */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
6163  { Feature_HasStdEnc|Feature_HasMicroMips64r6, 2988 /* dalign */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
6164  { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 2995 /* dati */, MCK_GPR64AsmReg, 1 /* 0 */ },
6165  { Feature_HasStdEnc|Feature_HasMicroMips64r6, 2995 /* dati */, MCK_GPR64AsmReg, 1 /* 0 */ },
6166  { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3000 /* daui */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6167  { Feature_HasStdEnc|Feature_HasMicroMips64r6, 3000 /* daui */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6168  { Feature_HasStdEnc|Feature_HasMips64r6, 3005 /* dbitswap */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6169  { Feature_HasStdEnc|Feature_HasMips64|Feature_NotMips64r6, 3014 /* dclo */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6170  { Feature_HasStdEnc|Feature_HasMips64r6, 3014 /* dclo */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6171  { Feature_HasStdEnc|Feature_HasMips64|Feature_NotMips64r6, 3019 /* dclz */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6172  { Feature_HasStdEnc|Feature_HasMips64r6, 3019 /* dclz */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6173  { Feature_HasStdEnc|Feature_HasMicroMips64r6, 3024 /* ddiv */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
6174  { 0, 3024 /* ddiv */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
6175  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3024 /* ddiv */, MCK_GPR64AsmReg, 6 /* 1, 2 */ },
6176  { Feature_HasStdEnc|Feature_HasMicroMips64r6, 3024 /* ddiv */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
6177  { Feature_HasStdEnc|Feature_HasMips64r6, 3024 /* ddiv */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
6178  { Feature_HasStdEnc|Feature_HasMicroMips64r6, 3029 /* ddivu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
6179  { 0, 3029 /* ddivu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
6180  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3029 /* ddivu */, MCK_GPR64AsmReg, 6 /* 1, 2 */ },
6181  { Feature_HasStdEnc|Feature_HasMicroMips64r6, 3029 /* ddivu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
6182  { Feature_HasStdEnc|Feature_HasMips64r6, 3029 /* ddivu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
6183  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 3041 /* dext */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6184  { Feature_HasStdEnc|Feature_HasMicroMips64r6, 3041 /* dext */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6185  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 3046 /* dextm */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6186  { Feature_HasStdEnc|Feature_HasMicroMips64r6, 3046 /* dextm */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6187  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 3052 /* dextu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6188  { Feature_HasStdEnc|Feature_HasMicroMips64r6, 3052 /* dextu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6189  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 3058 /* di */, MCK_GPR32AsmReg, 1 /* 0 */ },
6190  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 3058 /* di */, MCK_GPR32AsmReg, 1 /* 0 */ },
6191  { Feature_InMicroMips, 3058 /* di */, MCK_GPR32AsmReg, 1 /* 0 */ },
6192  { Feature_HasStdEnc|Feature_HasMips32r2, 3061 /* dins */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6193  { Feature_HasStdEnc|Feature_HasMips32r2, 3066 /* dinsm */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6194  { Feature_HasStdEnc|Feature_HasMips32r2, 3072 /* dinsu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6195  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 3078 /* div */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
6196  { 0, 3078 /* div */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
6197  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3078 /* div */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6198  { Feature_InMicroMips, 3078 /* div */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6199  { Feature_HasStdEnc|Feature_HasMips32r6, 3078 /* div */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
6200  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 3078 /* div */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
6201  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat, 3082 /* div.d */, MCK_AFGR64AsmReg, 7 /* 0, 1, 2 */ },
6202  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 3082 /* div.d */, MCK_AFGR64AsmReg, 7 /* 0, 1, 2 */ },
6203  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3082 /* div.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
6204  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 3088 /* div.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
6205  { Feature_HasStdEnc|Feature_IsNotSoftFloat, 3088 /* div.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
6206  { Feature_HasStdEnc|Feature_HasMSA, 3094 /* div_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6207  { Feature_HasStdEnc|Feature_HasMSA, 3102 /* div_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6208  { Feature_HasStdEnc|Feature_HasMSA, 3110 /* div_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6209  { Feature_HasStdEnc|Feature_HasMSA, 3118 /* div_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6210  { Feature_HasStdEnc|Feature_HasMSA, 3126 /* div_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6211  { Feature_HasStdEnc|Feature_HasMSA, 3134 /* div_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6212  { Feature_HasStdEnc|Feature_HasMSA, 3142 /* div_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6213  { Feature_HasStdEnc|Feature_HasMSA, 3150 /* div_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6214  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 3158 /* divu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
6215  { 0, 3158 /* divu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
6216  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3158 /* divu */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6217  { Feature_InMicroMips, 3158 /* divu */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6218  { Feature_HasStdEnc|Feature_HasMips32r6, 3158 /* divu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
6219  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 3158 /* divu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
6220  { 0, 3163 /* dla */, MCK_GPR64AsmReg, 1 /* 0 */ },
6221  { 0, 3163 /* dla */, MCK_GPR64AsmReg, 1 /* 0 */ },
6222  { 0, 3163 /* dla */, MCK_Mem, 2 /* 1 */ },
6223  { 0, 3167 /* dli */, MCK_GPR64AsmReg, 1 /* 0 */ },
6224  { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 3171 /* dlsa */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
6225  { Feature_HasStdEnc|Feature_HasMips64r6, 3171 /* dlsa */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
6226  { 0, 3176 /* dmfc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
6227  { 0, 3176 /* dmfc0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
6228  { Feature_HasMips64, 3176 /* dmfc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
6229  { Feature_HasMips64, 3176 /* dmfc0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
6230  { Feature_HasStdEnc|Feature_HasMips3|Feature_IsNotSoftFloat, 3182 /* dmfc1 */, MCK_FGR64AsmReg, 2 /* 1 */ },
6231  { Feature_HasStdEnc|Feature_HasMips3|Feature_IsNotSoftFloat, 3182 /* dmfc1 */, MCK_GPR64AsmReg, 1 /* 0 */ },
6232  { 0, 3188 /* dmfc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
6233  { 0, 3188 /* dmfc2 */, MCK_GPR64AsmReg, 1 /* 0 */ },
6234  { Feature_HasCnMips, 3188 /* dmfc2 */, MCK_GPR64AsmReg, 1 /* 0 */ },
6235  { Feature_HasMips64, 3188 /* dmfc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
6236  { Feature_HasMips64, 3188 /* dmfc2 */, MCK_GPR64AsmReg, 1 /* 0 */ },
6237  { Feature_HasStdEnc|Feature_HasMicroMips64r6, 3194 /* dmod */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
6238  { Feature_HasStdEnc|Feature_HasMicroMips64r6, 3194 /* dmod */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
6239  { Feature_HasStdEnc|Feature_HasMips64r6, 3194 /* dmod */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
6240  { Feature_HasStdEnc|Feature_HasMicroMips64r6, 3199 /* dmodu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
6241  { Feature_HasStdEnc|Feature_HasMicroMips64r6, 3199 /* dmodu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
6242  { Feature_HasStdEnc|Feature_HasMips64r6, 3199 /* dmodu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
6243  { 0, 3205 /* dmtc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
6244  { 0, 3205 /* dmtc0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
6245  { Feature_HasMips64, 3205 /* dmtc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
6246  { Feature_HasMips64, 3205 /* dmtc0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
6247  { Feature_HasStdEnc|Feature_HasMips3|Feature_IsNotSoftFloat, 3211 /* dmtc1 */, MCK_FGR64AsmReg, 2 /* 1 */ },
6248  { Feature_HasStdEnc|Feature_HasMips3|Feature_IsNotSoftFloat, 3211 /* dmtc1 */, MCK_GPR64AsmReg, 1 /* 0 */ },
6249  { 0, 3217 /* dmtc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
6250  { 0, 3217 /* dmtc2 */, MCK_GPR64AsmReg, 1 /* 0 */ },
6251  { Feature_HasCnMips, 3217 /* dmtc2 */, MCK_GPR64AsmReg, 1 /* 0 */ },
6252  { Feature_HasMips64, 3217 /* dmtc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
6253  { Feature_HasMips64, 3217 /* dmtc2 */, MCK_GPR64AsmReg, 1 /* 0 */ },
6254  { Feature_HasStdEnc|Feature_HasMips64r6, 3223 /* dmuh */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
6255  { Feature_HasStdEnc|Feature_HasMips64r6, 3228 /* dmuhu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
6256  { Feature_HasCnMips, 3234 /* dmul */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6257  { Feature_HasStdEnc|Feature_HasMips64r6, 3234 /* dmul */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
6258  { Feature_HasCnMips, 3234 /* dmul */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
6259  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3239 /* dmult */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6260  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3245 /* dmultu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6261  { Feature_HasStdEnc|Feature_HasMips64r6, 3252 /* dmulu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
6262  { Feature_HasMips3, 3258 /* dneg */, MCK_GPR64AsmReg, 1 /* 0 */ },
6263  { Feature_HasMips3, 3258 /* dneg */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6264  { Feature_HasMips3, 3263 /* dnegu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6265  { Feature_HasStdEnc|Feature_HasMSA, 3269 /* dotp_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6266  { Feature_HasStdEnc|Feature_HasMSA, 3278 /* dotp_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6267  { Feature_HasStdEnc|Feature_HasMSA, 3287 /* dotp_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6268  { Feature_HasStdEnc|Feature_HasMSA, 3296 /* dotp_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6269  { Feature_HasStdEnc|Feature_HasMSA, 3305 /* dotp_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6270  { Feature_HasStdEnc|Feature_HasMSA, 3314 /* dotp_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6271  { Feature_HasDSPR2|Feature_InMicroMips, 3323 /* dpa.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6272  { Feature_HasDSPR2|Feature_InMicroMips, 3323 /* dpa.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6273  { Feature_HasDSPR2, 3323 /* dpa.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6274  { Feature_HasDSPR2, 3323 /* dpa.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6275  { Feature_HasStdEnc|Feature_HasMSA, 3332 /* dpadd_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6276  { Feature_HasStdEnc|Feature_HasMSA, 3342 /* dpadd_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6277  { Feature_HasStdEnc|Feature_HasMSA, 3352 /* dpadd_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6278  { Feature_HasStdEnc|Feature_HasMSA, 3362 /* dpadd_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6279  { Feature_HasStdEnc|Feature_HasMSA, 3372 /* dpadd_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6280  { Feature_HasStdEnc|Feature_HasMSA, 3382 /* dpadd_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6281  { Feature_HasDSP|Feature_InMicroMips, 3392 /* dpaq_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6282  { Feature_HasDSP|Feature_InMicroMips, 3392 /* dpaq_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6283  { Feature_HasDSP, 3392 /* dpaq_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6284  { Feature_HasDSP, 3392 /* dpaq_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6285  { Feature_HasDSP|Feature_InMicroMips, 3404 /* dpaq_sa.l.w */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6286  { Feature_HasDSP|Feature_InMicroMips, 3404 /* dpaq_sa.l.w */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6287  { Feature_HasDSP, 3404 /* dpaq_sa.l.w */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6288  { Feature_HasDSP, 3404 /* dpaq_sa.l.w */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6289  { Feature_HasDSPR2|Feature_InMicroMips, 3416 /* dpaqx_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6290  { Feature_HasDSPR2|Feature_InMicroMips, 3416 /* dpaqx_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6291  { Feature_HasDSPR2, 3416 /* dpaqx_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6292  { Feature_HasDSPR2, 3416 /* dpaqx_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6293  { Feature_HasDSPR2|Feature_InMicroMips, 3429 /* dpaqx_sa.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6294  { Feature_HasDSPR2|Feature_InMicroMips, 3429 /* dpaqx_sa.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6295  { Feature_HasDSPR2, 3429 /* dpaqx_sa.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6296  { Feature_HasDSPR2, 3429 /* dpaqx_sa.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6297  { Feature_HasDSP|Feature_InMicroMips, 3443 /* dpau.h.qbl */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6298  { Feature_HasDSP|Feature_InMicroMips, 3443 /* dpau.h.qbl */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6299  { Feature_HasDSP, 3443 /* dpau.h.qbl */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6300  { Feature_HasDSP, 3443 /* dpau.h.qbl */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6301  { Feature_HasDSP|Feature_InMicroMips, 3454 /* dpau.h.qbr */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6302  { Feature_HasDSP|Feature_InMicroMips, 3454 /* dpau.h.qbr */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6303  { Feature_HasDSP, 3454 /* dpau.h.qbr */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6304  { Feature_HasDSP, 3454 /* dpau.h.qbr */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6305  { Feature_HasDSPR2|Feature_InMicroMips, 3465 /* dpax.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6306  { Feature_HasDSPR2|Feature_InMicroMips, 3465 /* dpax.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6307  { Feature_HasDSPR2, 3465 /* dpax.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6308  { Feature_HasDSPR2, 3465 /* dpax.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6309  { Feature_HasCnMips, 3475 /* dpop */, MCK_GPR64AsmReg, 1 /* 0 */ },
6310  { Feature_HasCnMips, 3475 /* dpop */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6311  { Feature_HasDSPR2|Feature_InMicroMips, 3480 /* dps.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6312  { Feature_HasDSPR2|Feature_InMicroMips, 3480 /* dps.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6313  { Feature_HasDSPR2, 3480 /* dps.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6314  { Feature_HasDSPR2, 3480 /* dps.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6315  { Feature_HasDSP|Feature_InMicroMips, 3489 /* dpsq_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6316  { Feature_HasDSP|Feature_InMicroMips, 3489 /* dpsq_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6317  { Feature_HasDSP, 3489 /* dpsq_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6318  { Feature_HasDSP, 3489 /* dpsq_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6319  { Feature_HasDSP|Feature_InMicroMips, 3501 /* dpsq_sa.l.w */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6320  { Feature_HasDSP|Feature_InMicroMips, 3501 /* dpsq_sa.l.w */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6321  { Feature_HasDSP, 3501 /* dpsq_sa.l.w */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6322  { Feature_HasDSP, 3501 /* dpsq_sa.l.w */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6323  { Feature_HasDSPR2|Feature_InMicroMips, 3513 /* dpsqx_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6324  { Feature_HasDSPR2|Feature_InMicroMips, 3513 /* dpsqx_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6325  { Feature_HasDSPR2, 3513 /* dpsqx_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6326  { Feature_HasDSPR2, 3513 /* dpsqx_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6327  { Feature_HasDSPR2|Feature_InMicroMips, 3526 /* dpsqx_sa.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6328  { Feature_HasDSPR2|Feature_InMicroMips, 3526 /* dpsqx_sa.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6329  { Feature_HasDSPR2, 3526 /* dpsqx_sa.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6330  { Feature_HasDSPR2, 3526 /* dpsqx_sa.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6331  { Feature_HasDSP|Feature_InMicroMips, 3540 /* dpsu.h.qbl */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6332  { Feature_HasDSP|Feature_InMicroMips, 3540 /* dpsu.h.qbl */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6333  { Feature_HasDSP, 3540 /* dpsu.h.qbl */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6334  { Feature_HasDSP, 3540 /* dpsu.h.qbl */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6335  { Feature_HasDSP|Feature_InMicroMips, 3551 /* dpsu.h.qbr */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6336  { Feature_HasDSP|Feature_InMicroMips, 3551 /* dpsu.h.qbr */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6337  { Feature_HasDSP, 3551 /* dpsu.h.qbr */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6338  { Feature_HasDSP, 3551 /* dpsu.h.qbr */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6339  { Feature_HasStdEnc|Feature_HasMSA, 3562 /* dpsub_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6340  { Feature_HasStdEnc|Feature_HasMSA, 3572 /* dpsub_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6341  { Feature_HasStdEnc|Feature_HasMSA, 3582 /* dpsub_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6342  { Feature_HasStdEnc|Feature_HasMSA, 3592 /* dpsub_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6343  { Feature_HasStdEnc|Feature_HasMSA, 3602 /* dpsub_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6344  { Feature_HasStdEnc|Feature_HasMSA, 3612 /* dpsub_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6345  { Feature_HasDSPR2|Feature_InMicroMips, 3622 /* dpsx.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6346  { Feature_HasDSPR2|Feature_InMicroMips, 3622 /* dpsx.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6347  { Feature_HasDSPR2, 3622 /* dpsx.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6348  { Feature_HasDSPR2, 3622 /* dpsx.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6349  { Feature_HasMips64, 3632 /* drol */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
6350  { Feature_HasMips64, 3632 /* drol */, MCK_GPR32AsmReg, 1 /* 0 */ },
6351  { Feature_HasMips64, 3632 /* drol */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
6352  { Feature_HasMips64, 3632 /* drol */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
6353  { Feature_HasMips64, 3637 /* dror */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
6354  { Feature_HasMips64, 3637 /* dror */, MCK_GPR32AsmReg, 1 /* 0 */ },
6355  { Feature_HasMips64, 3637 /* dror */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
6356  { Feature_HasMips64, 3637 /* dror */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
6357  { Feature_HasStdEnc|Feature_HasMips64r2, 3642 /* drotr */, MCK_GPR64AsmReg, 1 /* 0 */ },
6358  { Feature_HasStdEnc|Feature_HasMips64r2, 3642 /* drotr */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6359  { Feature_HasStdEnc|Feature_HasMips64r2, 3648 /* drotr32 */, MCK_GPR64AsmReg, 1 /* 0 */ },
6360  { Feature_HasStdEnc|Feature_HasMips64r2, 3648 /* drotr32 */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6361  { Feature_HasStdEnc|Feature_HasMips64r2, 3656 /* drotrv */, MCK_GPR32AsmReg, 4 /* 2 */ },
6362  { Feature_HasStdEnc|Feature_HasMips64r2, 3656 /* drotrv */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6363  { Feature_HasStdEnc|Feature_HasMips64r2, 3663 /* dsbh */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6364  { Feature_HasStdEnc|Feature_HasMips64r2, 3668 /* dshd */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6365  { Feature_HasStdEnc|Feature_HasMips3, 3673 /* dsll */, MCK_GPR64AsmReg, 1 /* 0 */ },
6366  { Feature_HasMips3, 3673 /* dsll */, MCK_GPR32AsmReg, 4 /* 2 */ },
6367  { Feature_HasMips3, 3673 /* dsll */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6368  { Feature_HasStdEnc|Feature_HasMips3, 3673 /* dsll */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6369  { Feature_HasStdEnc|Feature_HasMips3, 3678 /* dsll32 */, MCK_GPR64AsmReg, 1 /* 0 */ },
6370  { Feature_HasStdEnc|Feature_HasMips3, 3678 /* dsll32 */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6371  { Feature_HasStdEnc|Feature_HasMips3, 3685 /* dsllv */, MCK_GPR32AsmReg, 4 /* 2 */ },
6372  { Feature_HasStdEnc|Feature_HasMips3, 3685 /* dsllv */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6373  { Feature_HasStdEnc|Feature_HasMips3, 3691 /* dsra */, MCK_GPR64AsmReg, 1 /* 0 */ },
6374  { Feature_HasMips3, 3691 /* dsra */, MCK_GPR32AsmReg, 4 /* 2 */ },
6375  { Feature_HasMips3, 3691 /* dsra */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6376  { Feature_HasStdEnc|Feature_HasMips3, 3691 /* dsra */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6377  { Feature_HasStdEnc|Feature_HasMips3, 3696 /* dsra32 */, MCK_GPR64AsmReg, 1 /* 0 */ },
6378  { Feature_HasStdEnc|Feature_HasMips3, 3696 /* dsra32 */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6379  { Feature_HasStdEnc|Feature_HasMips3, 3703 /* dsrav */, MCK_GPR32AsmReg, 4 /* 2 */ },
6380  { Feature_HasStdEnc|Feature_HasMips3, 3703 /* dsrav */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6381  { Feature_HasStdEnc|Feature_HasMips3, 3709 /* dsrl */, MCK_GPR64AsmReg, 1 /* 0 */ },
6382  { Feature_HasMips3, 3709 /* dsrl */, MCK_GPR32AsmReg, 4 /* 2 */ },
6383  { Feature_HasMips3, 3709 /* dsrl */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6384  { Feature_HasStdEnc|Feature_HasMips3, 3709 /* dsrl */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6385  { Feature_HasStdEnc|Feature_HasMips3, 3714 /* dsrl32 */, MCK_GPR64AsmReg, 1 /* 0 */ },
6386  { Feature_HasStdEnc|Feature_HasMips3, 3714 /* dsrl32 */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6387  { Feature_HasStdEnc|Feature_HasMips3, 3721 /* dsrlv */, MCK_GPR32AsmReg, 4 /* 2 */ },
6388  { Feature_HasStdEnc|Feature_HasMips3, 3721 /* dsrlv */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6389  { Feature_HasStdEnc|Feature_HasMips3, 3727 /* dsub */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6390  { Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3727 /* dsub */, MCK_GPR64AsmReg, 1 /* 0 */ },
6391  { Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3727 /* dsub */, MCK_InvNum, 2 /* 1 */ },
6392  { Feature_HasStdEnc|Feature_HasMips3, 3727 /* dsub */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
6393  { Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3727 /* dsub */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6394  { Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3727 /* dsub */, MCK_InvNum, 4 /* 2 */ },
6395  { Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3732 /* dsubi */, MCK_GPR64AsmReg, 1 /* 0 */ },
6396  { Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3732 /* dsubi */, MCK_InvNum, 2 /* 1 */ },
6397  { Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3732 /* dsubi */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6398  { Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3732 /* dsubi */, MCK_InvNum, 4 /* 2 */ },
6399  { Feature_HasStdEnc|Feature_HasMips3, 3738 /* dsubu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6400  { Feature_HasMips3, 3738 /* dsubu */, MCK_GPR64AsmReg, 1 /* 0 */ },
6401  { Feature_HasMips3, 3738 /* dsubu */, MCK_InvNum, 2 /* 1 */ },
6402  { Feature_HasStdEnc|Feature_HasMips3, 3738 /* dsubu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
6403  { Feature_HasMips3, 3738 /* dsubu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6404  { Feature_HasMips3, 3738 /* dsubu */, MCK_InvNum, 4 /* 2 */ },
6405  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 3748 /* ei */, MCK_GPR32AsmReg, 1 /* 0 */ },
6406  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 3748 /* ei */, MCK_GPR32AsmReg, 1 /* 0 */ },
6407  { Feature_InMicroMips, 3748 /* ei */, MCK_GPR32AsmReg, 1 /* 0 */ },
6408  { Feature_HasStdEnc|Feature_HasMips32r2, 3763 /* ext */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
6409  { Feature_InMicroMips, 3763 /* ext */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
6410  { Feature_HasDSP|Feature_InMicroMips, 3767 /* extp */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
6411  { Feature_HasDSP|Feature_InMicroMips, 3767 /* extp */, MCK_GPR32AsmReg, 1 /* 0 */ },
6412  { Feature_HasDSP, 3767 /* extp */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
6413  { Feature_HasDSP, 3767 /* extp */, MCK_GPR32AsmReg, 1 /* 0 */ },
6414  { Feature_HasDSP|Feature_InMicroMips, 3772 /* extpdp */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
6415  { Feature_HasDSP|Feature_InMicroMips, 3772 /* extpdp */, MCK_GPR32AsmReg, 1 /* 0 */ },
6416  { Feature_HasDSP, 3772 /* extpdp */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
6417  { Feature_HasDSP, 3772 /* extpdp */, MCK_GPR32AsmReg, 1 /* 0 */ },
6418  { Feature_HasDSP|Feature_InMicroMips, 3779 /* extpdpv */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
6419  { Feature_HasDSP|Feature_InMicroMips, 3779 /* extpdpv */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
6420  { Feature_HasDSP, 3779 /* extpdpv */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
6421  { Feature_HasDSP, 3779 /* extpdpv */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
6422  { Feature_HasDSP|Feature_InMicroMips, 3787 /* extpv */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
6423  { Feature_HasDSP|Feature_InMicroMips, 3787 /* extpv */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
6424  { Feature_HasDSP, 3787 /* extpv */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
6425  { Feature_HasDSP, 3787 /* extpv */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
6426  { Feature_HasDSP|Feature_InMicroMips, 3793 /* extr.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
6427  { Feature_HasDSP|Feature_InMicroMips, 3793 /* extr.w */, MCK_GPR32AsmReg, 1 /* 0 */ },
6428  { Feature_HasDSP, 3793 /* extr.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
6429  { Feature_HasDSP, 3793 /* extr.w */, MCK_GPR32AsmReg, 1 /* 0 */ },
6430  { Feature_HasDSP|Feature_InMicroMips, 3800 /* extr_r.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
6431  { Feature_HasDSP|Feature_InMicroMips, 3800 /* extr_r.w */, MCK_GPR32AsmReg, 1 /* 0 */ },
6432  { Feature_HasDSP, 3800 /* extr_r.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
6433  { Feature_HasDSP, 3800 /* extr_r.w */, MCK_GPR32AsmReg, 1 /* 0 */ },
6434  { Feature_HasDSP|Feature_InMicroMips, 3809 /* extr_rs.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
6435  { Feature_HasDSP|Feature_InMicroMips, 3809 /* extr_rs.w */, MCK_GPR32AsmReg, 1 /* 0 */ },
6436  { Feature_HasDSP, 3809 /* extr_rs.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
6437  { Feature_HasDSP, 3809 /* extr_rs.w */, MCK_GPR32AsmReg, 1 /* 0 */ },
6438  { Feature_HasDSP|Feature_InMicroMips, 3819 /* extr_s.h */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
6439  { Feature_HasDSP|Feature_InMicroMips, 3819 /* extr_s.h */, MCK_GPR32AsmReg, 1 /* 0 */ },
6440  { Feature_HasDSP, 3819 /* extr_s.h */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
6441  { Feature_HasDSP, 3819 /* extr_s.h */, MCK_GPR32AsmReg, 1 /* 0 */ },
6442  { Feature_HasDSP|Feature_InMicroMips, 3828 /* extrv.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
6443  { Feature_HasDSP|Feature_InMicroMips, 3828 /* extrv.w */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
6444  { Feature_HasDSP, 3828 /* extrv.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
6445  { Feature_HasDSP, 3828 /* extrv.w */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
6446  { Feature_HasDSP|Feature_InMicroMips, 3836 /* extrv_r.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
6447  { Feature_HasDSP|Feature_InMicroMips, 3836 /* extrv_r.w */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
6448  { Feature_HasDSP, 3836 /* extrv_r.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
6449  { Feature_HasDSP, 3836 /* extrv_r.w */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
6450  { Feature_HasDSP|Feature_InMicroMips, 3846 /* extrv_rs.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
6451  { Feature_HasDSP|Feature_InMicroMips, 3846 /* extrv_rs.w */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
6452  { Feature_HasDSP, 3846 /* extrv_rs.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
6453  { Feature_HasDSP, 3846 /* extrv_rs.w */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
6454  { Feature_HasDSP|Feature_InMicroMips, 3857 /* extrv_s.h */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
6455  { Feature_HasDSP|Feature_InMicroMips, 3857 /* extrv_s.h */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
6456  { Feature_HasDSP, 3857 /* extrv_s.h */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
6457  { Feature_HasDSP, 3857 /* extrv_s.h */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
6458  { Feature_HasCnMips, 3867 /* exts */, MCK_GPR64AsmReg, 1 /* 0 */ },
6459  { Feature_HasCnMips, 3867 /* exts */, MCK_GPR64AsmReg, 1 /* 0 */ },
6460  { Feature_HasCnMips, 3867 /* exts */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6461  { Feature_HasCnMips, 3867 /* exts */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6462  { Feature_HasCnMips, 3872 /* exts32 */, MCK_GPR64AsmReg, 1 /* 0 */ },
6463  { Feature_HasCnMips, 3872 /* exts32 */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6464  { Feature_HasStdEnc|Feature_HasMSA, 3879 /* fadd.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6465  { Feature_HasStdEnc|Feature_HasMSA, 3886 /* fadd.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6466  { Feature_HasStdEnc|Feature_HasMSA, 3893 /* fcaf.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6467  { Feature_HasStdEnc|Feature_HasMSA, 3900 /* fcaf.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6468  { Feature_HasStdEnc|Feature_HasMSA, 3907 /* fceq.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6469  { Feature_HasStdEnc|Feature_HasMSA, 3914 /* fceq.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6470  { Feature_HasStdEnc|Feature_HasMSA, 3921 /* fclass.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6471  { Feature_HasStdEnc|Feature_HasMSA, 3930 /* fclass.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6472  { Feature_HasStdEnc|Feature_HasMSA, 3939 /* fcle.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6473  { Feature_HasStdEnc|Feature_HasMSA, 3946 /* fcle.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6474  { Feature_HasStdEnc|Feature_HasMSA, 3953 /* fclt.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6475  { Feature_HasStdEnc|Feature_HasMSA, 3960 /* fclt.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6476  { Feature_HasStdEnc|Feature_HasMSA, 3967 /* fcne.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6477  { Feature_HasStdEnc|Feature_HasMSA, 3974 /* fcne.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6478  { Feature_HasStdEnc|Feature_HasMSA, 3981 /* fcor.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6479  { Feature_HasStdEnc|Feature_HasMSA, 3988 /* fcor.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6480  { Feature_HasStdEnc|Feature_HasMSA, 3995 /* fcueq.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6481  { Feature_HasStdEnc|Feature_HasMSA, 4003 /* fcueq.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6482  { Feature_HasStdEnc|Feature_HasMSA, 4011 /* fcule.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6483  { Feature_HasStdEnc|Feature_HasMSA, 4019 /* fcule.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6484  { Feature_HasStdEnc|Feature_HasMSA, 4027 /* fcult.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6485  { Feature_HasStdEnc|Feature_HasMSA, 4035 /* fcult.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6486  { Feature_HasStdEnc|Feature_HasMSA, 4043 /* fcun.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6487  { Feature_HasStdEnc|Feature_HasMSA, 4050 /* fcun.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6488  { Feature_HasStdEnc|Feature_HasMSA, 4057 /* fcune.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6489  { Feature_HasStdEnc|Feature_HasMSA, 4065 /* fcune.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6490  { Feature_HasStdEnc|Feature_HasMSA, 4073 /* fdiv.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6491  { Feature_HasStdEnc|Feature_HasMSA, 4080 /* fdiv.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6492  { Feature_HasStdEnc|Feature_HasMSA, 4087 /* fexdo.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6493  { Feature_HasStdEnc|Feature_HasMSA, 4095 /* fexdo.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6494  { Feature_HasStdEnc|Feature_HasMSA, 4103 /* fexp2.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6495  { Feature_HasStdEnc|Feature_HasMSA, 4111 /* fexp2.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6496  { Feature_HasStdEnc|Feature_HasMSA, 4119 /* fexupl.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6497  { Feature_HasStdEnc|Feature_HasMSA, 4128 /* fexupl.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6498  { Feature_HasStdEnc|Feature_HasMSA, 4137 /* fexupr.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6499  { Feature_HasStdEnc|Feature_HasMSA, 4146 /* fexupr.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6500  { Feature_HasStdEnc|Feature_HasMSA, 4155 /* ffint_s.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6501  { Feature_HasStdEnc|Feature_HasMSA, 4165 /* ffint_s.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6502  { Feature_HasStdEnc|Feature_HasMSA, 4175 /* ffint_u.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6503  { Feature_HasStdEnc|Feature_HasMSA, 4185 /* ffint_u.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6504  { Feature_HasStdEnc|Feature_HasMSA, 4195 /* ffql.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6505  { Feature_HasStdEnc|Feature_HasMSA, 4202 /* ffql.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6506  { Feature_HasStdEnc|Feature_HasMSA, 4209 /* ffqr.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6507  { Feature_HasStdEnc|Feature_HasMSA, 4216 /* ffqr.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6508  { Feature_HasStdEnc|Feature_HasMSA, 4223 /* fill.b */, MCK_GPR32AsmReg, 2 /* 1 */ },
6509  { Feature_HasStdEnc|Feature_HasMSA, 4223 /* fill.b */, MCK_MSA128AsmReg, 1 /* 0 */ },
6510  { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 4230 /* fill.d */, MCK_GPR64AsmReg, 2 /* 1 */ },
6511  { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 4230 /* fill.d */, MCK_MSA128AsmReg, 1 /* 0 */ },
6512  { Feature_HasStdEnc|Feature_HasMSA, 4237 /* fill.h */, MCK_GPR32AsmReg, 2 /* 1 */ },
6513  { Feature_HasStdEnc|Feature_HasMSA, 4237 /* fill.h */, MCK_MSA128AsmReg, 1 /* 0 */ },
6514  { Feature_HasStdEnc|Feature_HasMSA, 4244 /* fill.w */, MCK_GPR32AsmReg, 2 /* 1 */ },
6515  { Feature_HasStdEnc|Feature_HasMSA, 4244 /* fill.w */, MCK_MSA128AsmReg, 1 /* 0 */ },
6516  { Feature_HasStdEnc|Feature_HasMSA, 4251 /* flog2.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6517  { Feature_HasStdEnc|Feature_HasMSA, 4259 /* flog2.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6518  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4267 /* floor.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
6519  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 4267 /* floor.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
6520  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4277 /* floor.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
6521  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4277 /* floor.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
6522  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 4277 /* floor.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
6523  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 4277 /* floor.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
6524  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 4287 /* floor.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
6525  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 4287 /* floor.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
6526  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 4287 /* floor.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
6527  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 4287 /* floor.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
6528  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 4287 /* floor.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
6529  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 4287 /* floor.w.d */, MCK_FGR64AsmReg, 2 /* 1 */ },
6530  { Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat, 4297 /* floor.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
6531  { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_InMicroMips, 4297 /* floor.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
6532  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 4297 /* floor.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
6533  { Feature_HasStdEnc|Feature_HasMSA, 4307 /* fmadd.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6534  { Feature_HasStdEnc|Feature_HasMSA, 4315 /* fmadd.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6535  { Feature_HasStdEnc|Feature_HasMSA, 4323 /* fmax.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6536  { Feature_HasStdEnc|Feature_HasMSA, 4330 /* fmax.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6537  { Feature_HasStdEnc|Feature_HasMSA, 4337 /* fmax_a.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6538  { Feature_HasStdEnc|Feature_HasMSA, 4346 /* fmax_a.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6539  { Feature_HasStdEnc|Feature_HasMSA, 4355 /* fmin.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6540  { Feature_HasStdEnc|Feature_HasMSA, 4362 /* fmin.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6541  { Feature_HasStdEnc|Feature_HasMSA, 4369 /* fmin_a.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6542  { Feature_HasStdEnc|Feature_HasMSA, 4378 /* fmin_a.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6543  { Feature_HasStdEnc|Feature_HasMSA, 4387 /* fmsub.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6544  { Feature_HasStdEnc|Feature_HasMSA, 4395 /* fmsub.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6545  { Feature_HasStdEnc|Feature_HasMSA, 4403 /* fmul.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6546  { Feature_HasStdEnc|Feature_HasMSA, 4410 /* fmul.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6547  { Feature_HasStdEnc|Feature_HasMSA, 4417 /* frcp.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6548  { Feature_HasStdEnc|Feature_HasMSA, 4424 /* frcp.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6549  { Feature_HasStdEnc|Feature_HasMSA, 4431 /* frint.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6550  { Feature_HasStdEnc|Feature_HasMSA, 4439 /* frint.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6551  { Feature_HasStdEnc|Feature_HasMSA, 4447 /* frsqrt.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6552  { Feature_HasStdEnc|Feature_HasMSA, 4456 /* frsqrt.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6553  { Feature_HasStdEnc|Feature_HasMSA, 4465 /* fsaf.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6554  { Feature_HasStdEnc|Feature_HasMSA, 4472 /* fsaf.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6555  { Feature_HasStdEnc|Feature_HasMSA, 4479 /* fseq.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6556  { Feature_HasStdEnc|Feature_HasMSA, 4486 /* fseq.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6557  { Feature_HasStdEnc|Feature_HasMSA, 4493 /* fsle.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6558  { Feature_HasStdEnc|Feature_HasMSA, 4500 /* fsle.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6559  { Feature_HasStdEnc|Feature_HasMSA, 4507 /* fslt.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6560  { Feature_HasStdEnc|Feature_HasMSA, 4514 /* fslt.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6561  { Feature_HasStdEnc|Feature_HasMSA, 4521 /* fsne.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6562  { Feature_HasStdEnc|Feature_HasMSA, 4528 /* fsne.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6563  { Feature_HasStdEnc|Feature_HasMSA, 4535 /* fsor.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6564  { Feature_HasStdEnc|Feature_HasMSA, 4542 /* fsor.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6565  { Feature_HasStdEnc|Feature_HasMSA, 4549 /* fsqrt.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6566  { Feature_HasStdEnc|Feature_HasMSA, 4557 /* fsqrt.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6567  { Feature_HasStdEnc|Feature_HasMSA, 4565 /* fsub.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6568  { Feature_HasStdEnc|Feature_HasMSA, 4572 /* fsub.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6569  { Feature_HasStdEnc|Feature_HasMSA, 4579 /* fsueq.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6570  { Feature_HasStdEnc|Feature_HasMSA, 4587 /* fsueq.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6571  { Feature_HasStdEnc|Feature_HasMSA, 4595 /* fsule.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6572  { Feature_HasStdEnc|Feature_HasMSA, 4603 /* fsule.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6573  { Feature_HasStdEnc|Feature_HasMSA, 4611 /* fsult.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6574  { Feature_HasStdEnc|Feature_HasMSA, 4619 /* fsult.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6575  { Feature_HasStdEnc|Feature_HasMSA, 4627 /* fsun.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6576  { Feature_HasStdEnc|Feature_HasMSA, 4634 /* fsun.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6577  { Feature_HasStdEnc|Feature_HasMSA, 4641 /* fsune.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6578  { Feature_HasStdEnc|Feature_HasMSA, 4649 /* fsune.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6579  { Feature_HasStdEnc|Feature_HasMSA, 4657 /* ftint_s.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6580  { Feature_HasStdEnc|Feature_HasMSA, 4667 /* ftint_s.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6581  { Feature_HasStdEnc|Feature_HasMSA, 4677 /* ftint_u.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6582  { Feature_HasStdEnc|Feature_HasMSA, 4687 /* ftint_u.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6583  { Feature_HasStdEnc|Feature_HasMSA, 4697 /* ftq.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6584  { Feature_HasStdEnc|Feature_HasMSA, 4703 /* ftq.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6585  { Feature_HasStdEnc|Feature_HasMSA, 4709 /* ftrunc_s.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6586  { Feature_HasStdEnc|Feature_HasMSA, 4720 /* ftrunc_s.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6587  { Feature_HasStdEnc|Feature_HasMSA, 4731 /* ftrunc_u.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6588  { Feature_HasStdEnc|Feature_HasMSA, 4742 /* ftrunc_u.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6589  { Feature_HasStdEnc|Feature_HasMSA, 4753 /* hadd_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6590  { Feature_HasStdEnc|Feature_HasMSA, 4762 /* hadd_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6591  { Feature_HasStdEnc|Feature_HasMSA, 4771 /* hadd_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6592  { Feature_HasStdEnc|Feature_HasMSA, 4780 /* hadd_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6593  { Feature_HasStdEnc|Feature_HasMSA, 4789 /* hadd_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6594  { Feature_HasStdEnc|Feature_HasMSA, 4798 /* hadd_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6595  { Feature_HasStdEnc|Feature_HasMSA, 4807 /* hsub_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6596  { Feature_HasStdEnc|Feature_HasMSA, 4816 /* hsub_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6597  { Feature_HasStdEnc|Feature_HasMSA, 4825 /* hsub_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6598  { Feature_HasStdEnc|Feature_HasMSA, 4834 /* hsub_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6599  { Feature_HasStdEnc|Feature_HasMSA, 4843 /* hsub_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6600  { Feature_HasStdEnc|Feature_HasMSA, 4852 /* hsub_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6601  { Feature_HasStdEnc|Feature_HasMSA, 4861 /* ilvev.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6602  { Feature_HasStdEnc|Feature_HasMSA, 4869 /* ilvev.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6603  { Feature_HasStdEnc|Feature_HasMSA, 4877 /* ilvev.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6604  { Feature_HasStdEnc|Feature_HasMSA, 4885 /* ilvev.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6605  { Feature_HasStdEnc|Feature_HasMSA, 4893 /* ilvl.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6606  { Feature_HasStdEnc|Feature_HasMSA, 4900 /* ilvl.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6607  { Feature_HasStdEnc|Feature_HasMSA, 4907 /* ilvl.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6608  { Feature_HasStdEnc|Feature_HasMSA, 4914 /* ilvl.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6609  { Feature_HasStdEnc|Feature_HasMSA, 4921 /* ilvod.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6610  { Feature_HasStdEnc|Feature_HasMSA, 4929 /* ilvod.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6611  { Feature_HasStdEnc|Feature_HasMSA, 4937 /* ilvod.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6612  { Feature_HasStdEnc|Feature_HasMSA, 4945 /* ilvod.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6613  { Feature_HasStdEnc|Feature_HasMSA, 4953 /* ilvr.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6614  { Feature_HasStdEnc|Feature_HasMSA, 4960 /* ilvr.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6615  { Feature_HasStdEnc|Feature_HasMSA, 4967 /* ilvr.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6616  { Feature_HasStdEnc|Feature_HasMSA, 4974 /* ilvr.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6617  { Feature_HasStdEnc|Feature_HasMips32r2, 4981 /* ins */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
6618  { Feature_InMicroMips, 4981 /* ins */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
6619  { Feature_HasStdEnc|Feature_HasMSA, 4985 /* insert.b */, MCK_GPR32AsmReg, 16 /* 4 */ },
6620  { Feature_HasStdEnc|Feature_HasMSA, 4985 /* insert.b */, MCK_MSA128AsmReg, 1 /* 0 */ },
6621  { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 4994 /* insert.d */, MCK_GPR64AsmReg, 16 /* 4 */ },
6622  { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 4994 /* insert.d */, MCK_MSA128AsmReg, 1 /* 0 */ },
6623  { Feature_HasStdEnc|Feature_HasMSA, 5003 /* insert.h */, MCK_GPR32AsmReg, 16 /* 4 */ },
6624  { Feature_HasStdEnc|Feature_HasMSA, 5003 /* insert.h */, MCK_MSA128AsmReg, 1 /* 0 */ },
6625  { Feature_HasStdEnc|Feature_HasMSA, 5012 /* insert.w */, MCK_GPR32AsmReg, 16 /* 4 */ },
6626  { Feature_HasStdEnc|Feature_HasMSA, 5012 /* insert.w */, MCK_MSA128AsmReg, 1 /* 0 */ },
6627  { Feature_HasDSP|Feature_InMicroMips, 5021 /* insv */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
6628  { Feature_HasDSP, 5021 /* insv */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
6629  { Feature_HasStdEnc|Feature_HasMSA, 5026 /* insve.b */, MCK_MSA128AsmReg, 17 /* 0, 4 */ },
6630  { Feature_HasStdEnc|Feature_HasMSA, 5034 /* insve.d */, MCK_MSA128AsmReg, 17 /* 0, 4 */ },
6631  { Feature_HasStdEnc|Feature_HasMSA, 5042 /* insve.h */, MCK_MSA128AsmReg, 17 /* 0, 4 */ },
6632  { Feature_HasStdEnc|Feature_HasMSA, 5050 /* insve.w */, MCK_MSA128AsmReg, 17 /* 0, 4 */ },
6633  { 0, 5058 /* j */, MCK_GPR32AsmReg, 1 /* 0 */ },
6634  { Feature_HasStdEnc, 5058 /* j */, MCK_JumpTarget, 1 /* 0 */ },
6635  { 0, 5060 /* jal */, MCK_GPR32AsmReg, 1 /* 0 */ },
6636  { Feature_HasStdEnc, 5060 /* jal */, MCK_JumpTarget, 1 /* 0 */ },
6637  { 0, 5060 /* jal */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
6638  { Feature_InMicroMips|Feature_NotMips32r6, 5064 /* jalr */, MCK_GPR32AsmReg, 1 /* 0 */ },
6639  { Feature_HasMicroMips32r6, 5064 /* jalr */, MCK_GPR32AsmReg, 1 /* 0 */ },
6640  { Feature_NotInMicroMips, 5064 /* jalr */, MCK_GPR32AsmReg, 1 /* 0 */ },
6641  { Feature_HasStdEnc|Feature_NotInMicroMips, 5064 /* jalr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
6642  { Feature_InMicroMips, 5064 /* jalr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
6643  { Feature_HasMips32, 5069 /* jalr.hb */, MCK_GPR32AsmReg, 1 /* 0 */ },
6644  { Feature_HasStdEnc|Feature_HasMips32, 5069 /* jalr.hb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
6645  { Feature_InMicroMips, 5083 /* jalrs */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
6646  { Feature_InMicroMips, 5089 /* jalrs16 */, MCK_GPR32AsmReg, 1 /* 0 */ },
6647  { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6, 5102 /* jalx */, MCK_JumpTarget, 1 /* 0 */ },
6648  { Feature_InMicroMips, 5102 /* jalx */, MCK_JumpTarget, 1 /* 0 */ },
6649  { Feature_HasStdEnc|Feature_HasMips32r6, 5107 /* jialc */, MCK_GPR32AsmReg, 1 /* 0 */ },
6650  { Feature_HasStdEnc|Feature_HasMips32r6, 5107 /* jialc */, MCK_JumpTarget, 2 /* 1 */ },
6651  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 5107 /* jialc */, MCK_GPR32AsmReg, 1 /* 0 */ },
6652  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 5107 /* jialc */, MCK_JumpTarget, 2 /* 1 */ },
6653  { Feature_HasStdEnc|Feature_HasMips32r6, 5113 /* jic */, MCK_GPR32AsmReg, 1 /* 0 */ },
6654  { Feature_HasStdEnc|Feature_HasMips32r6, 5113 /* jic */, MCK_JumpTarget, 2 /* 1 */ },
6655  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 5113 /* jic */, MCK_GPR32AsmReg, 1 /* 0 */ },
6656  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 5113 /* jic */, MCK_JumpTarget, 2 /* 1 */ },
6657  { Feature_HasStdEnc, 5117 /* jr */, MCK_GPR32AsmReg, 1 /* 0 */ },
6658  { Feature_InMicroMips, 5117 /* jr */, MCK_GPR32AsmReg, 1 /* 0 */ },
6659  { Feature_HasMips32r6, 5117 /* jr */, MCK_GPR32AsmReg, 1 /* 0 */ },
6660  { Feature_HasMips64r6, 5117 /* jr */, MCK_GPR64AsmReg, 1 /* 0 */ },
6661  { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6, 5120 /* jr.hb */, MCK_GPR32AsmReg, 1 /* 0 */ },
6662  { Feature_HasStdEnc|Feature_HasMips32r6, 5120 /* jr.hb */, MCK_GPR32AsmReg, 1 /* 0 */ },
6663  { Feature_InMicroMips, 5126 /* jr16 */, MCK_GPR32AsmReg, 1 /* 0 */ },
6664  { Feature_InMicroMips, 5141 /* jrc */, MCK_GPR32AsmReg, 1 /* 0 */ },
6665  { Feature_HasMicroMips32r6, 5145 /* jrc16 */, MCK_GPR32AsmReg, 1 /* 0 */ },
6666  { 0, 5162 /* la */, MCK_GPR32AsmReg, 1 /* 0 */ },
6667  { 0, 5162 /* la */, MCK_GPR32AsmReg, 1 /* 0 */ },
6668  { 0, 5162 /* la */, MCK_Mem, 2 /* 1 */ },
6669  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 5165 /* lb */, MCK_GPR32AsmReg, 1 /* 0 */ },
6670  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 5165 /* lb */, MCK_Mem, 2 /* 1 */ },
6671  { Feature_HasStdEnc, 5165 /* lb */, MCK_GPR32AsmReg, 1 /* 0 */ },
6672  { Feature_HasStdEnc, 5165 /* lb */, MCK_Mem, 2 /* 1 */ },
6673  { Feature_InMicroMips, 5165 /* lb */, MCK_GPR32AsmReg, 1 /* 0 */ },
6674  { Feature_InMicroMips, 5165 /* lb */, MCK_Mem, 2 /* 1 */ },
6675  { Feature_HasStdEnc|Feature_HasEVA, 5168 /* lbe */, MCK_GPR32AsmReg, 1 /* 0 */ },
6676  { Feature_HasStdEnc|Feature_HasEVA, 5168 /* lbe */, MCK_MemOffsetSimm9, 2 /* 1 */ },
6677  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 5168 /* lbe */, MCK_GPR32AsmReg, 1 /* 0 */ },
6678  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 5168 /* lbe */, MCK_Mem, 2 /* 1 */ },
6679  { Feature_InMicroMips, 5168 /* lbe */, MCK_GPR32AsmReg, 1 /* 0 */ },
6680  { Feature_InMicroMips, 5168 /* lbe */, MCK_Mem, 2 /* 1 */ },
6681  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 5172 /* lbu */, MCK_GPR32AsmReg, 1 /* 0 */ },
6682  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 5172 /* lbu */, MCK_Mem, 2 /* 1 */ },
6683  { Feature_HasStdEnc, 5172 /* lbu */, MCK_GPR32AsmReg, 1 /* 0 */ },
6684  { Feature_HasStdEnc, 5172 /* lbu */, MCK_Mem, 2 /* 1 */ },
6685  { Feature_InMicroMips, 5172 /* lbu */, MCK_GPR32AsmReg, 1 /* 0 */ },
6686  { Feature_InMicroMips, 5172 /* lbu */, MCK_Mem, 2 /* 1 */ },
6687  { Feature_InMicroMips, 5176 /* lbu16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
6688  { Feature_InMicroMips, 5176 /* lbu16 */, MCK_MicroMipsMem, 2 /* 1 */ },
6689  { Feature_HasStdEnc|Feature_HasEVA, 5182 /* lbue */, MCK_GPR32AsmReg, 1 /* 0 */ },
6690  { Feature_HasStdEnc|Feature_HasEVA, 5182 /* lbue */, MCK_MemOffsetSimm9, 2 /* 1 */ },
6691  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 5182 /* lbue */, MCK_GPR32AsmReg, 1 /* 0 */ },
6692  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 5182 /* lbue */, MCK_Mem, 2 /* 1 */ },
6693  { Feature_InMicroMips, 5182 /* lbue */, MCK_GPR32AsmReg, 1 /* 0 */ },
6694  { Feature_InMicroMips, 5182 /* lbue */, MCK_Mem, 2 /* 1 */ },
6695  { Feature_HasDSP|Feature_InMicroMips, 5187 /* lbux */, MCK_GPR32AsmReg, 11 /* 0, 1, 3 */ },
6696  { Feature_HasDSP, 5187 /* lbux */, MCK_GPR32AsmReg, 11 /* 0, 1, 3 */ },
6697  { Feature_HasStdEnc|Feature_HasMips3, 5192 /* ld */, MCK_GPR64AsmReg, 1 /* 0 */ },
6698  { Feature_HasStdEnc|Feature_HasMips3, 5192 /* ld */, MCK_Mem, 2 /* 1 */ },
6699  { Feature_HasStdEnc|Feature_HasMSA, 5195 /* ld.b */, MCK_MSA128AsmReg, 1 /* 0 */ },
6700  { Feature_HasStdEnc|Feature_HasMSA, 5195 /* ld.b */, MCK_Mem, 2 /* 1 */ },
6701  { Feature_HasStdEnc|Feature_HasMSA, 5200 /* ld.d */, MCK_MSA128AsmReg, 1 /* 0 */ },
6702  { Feature_HasStdEnc|Feature_HasMSA, 5200 /* ld.d */, MCK_Mem, 2 /* 1 */ },
6703  { Feature_HasStdEnc|Feature_HasMSA, 5205 /* ld.h */, MCK_MSA128AsmReg, 1 /* 0 */ },
6704  { Feature_HasStdEnc|Feature_HasMSA, 5205 /* ld.h */, MCK_Mem, 2 /* 1 */ },
6705  { Feature_HasStdEnc|Feature_HasMSA, 5210 /* ld.w */, MCK_MSA128AsmReg, 1 /* 0 */ },
6706  { Feature_HasStdEnc|Feature_HasMSA, 5210 /* ld.w */, MCK_Mem, 2 /* 1 */ },
6707  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 5215 /* ldc1 */, MCK_AFGR64AsmReg, 1 /* 0 */ },
6708  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 5215 /* ldc1 */, MCK_Mem, 2 /* 1 */ },
6709  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 5215 /* ldc1 */, MCK_FGR64AsmReg, 1 /* 0 */ },
6710  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 5215 /* ldc1 */, MCK_Mem, 2 /* 1 */ },
6711  { Feature_HasStdEnc|Feature_HasMips32r6, 5220 /* ldc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
6712  { Feature_HasStdEnc|Feature_HasMips32r6, 5220 /* ldc2 */, MCK_MemOffsetSimm11, 2 /* 1 */ },
6713  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5220 /* ldc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
6714  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5220 /* ldc2 */, MCK_Mem, 2 /* 1 */ },
6715  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 5225 /* ldc3 */, MCK_COP3AsmReg, 1 /* 0 */ },
6716  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 5225 /* ldc3 */, MCK_Mem, 2 /* 1 */ },
6717  { Feature_HasStdEnc|Feature_HasMSA, 5230 /* ldi.b */, MCK_MSA128AsmReg, 1 /* 0 */ },
6718  { Feature_HasStdEnc|Feature_HasMSA, 5236 /* ldi.d */, MCK_MSA128AsmReg, 1 /* 0 */ },
6719  { Feature_HasStdEnc|Feature_HasMSA, 5242 /* ldi.h */, MCK_MSA128AsmReg, 1 /* 0 */ },
6720  { Feature_HasStdEnc|Feature_HasMSA, 5248 /* ldi.w */, MCK_MSA128AsmReg, 1 /* 0 */ },
6721  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 5254 /* ldl */, MCK_GPR64AsmReg, 1 /* 0 */ },
6722  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 5254 /* ldl */, MCK_Mem, 2 /* 1 */ },
6723  { Feature_HasStdEnc|Feature_HasMips64r6, 5258 /* ldpc */, MCK_GPR64AsmReg, 1 /* 0 */ },
6724  { Feature_HasStdEnc|Feature_HasMips64r6, 5258 /* ldpc */, MCK_JumpTarget, 2 /* 1 */ },
6725  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 5263 /* ldr */, MCK_GPR64AsmReg, 1 /* 0 */ },
6726  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 5263 /* ldr */, MCK_Mem, 2 /* 1 */ },
6727  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5267 /* ldxc1 */, MCK_AFGR64AsmReg, 1 /* 0 */ },
6728  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5267 /* ldxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
6729  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 5267 /* ldxc1 */, MCK_FGR64AsmReg, 1 /* 0 */ },
6730  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 5267 /* ldxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
6731  { Feature_HasStdEnc, 5273 /* lh */, MCK_GPR32AsmReg, 1 /* 0 */ },
6732  { Feature_HasStdEnc, 5273 /* lh */, MCK_Mem, 2 /* 1 */ },
6733  { Feature_InMicroMips, 5273 /* lh */, MCK_GPR32AsmReg, 1 /* 0 */ },
6734  { Feature_InMicroMips, 5273 /* lh */, MCK_Mem, 2 /* 1 */ },
6735  { Feature_HasStdEnc|Feature_HasEVA, 5276 /* lhe */, MCK_GPR32AsmReg, 1 /* 0 */ },
6736  { Feature_HasStdEnc|Feature_HasEVA, 5276 /* lhe */, MCK_MemOffsetSimm9, 2 /* 1 */ },
6737  { Feature_InMicroMips, 5276 /* lhe */, MCK_GPR32AsmReg, 1 /* 0 */ },
6738  { Feature_InMicroMips, 5276 /* lhe */, MCK_Mem, 2 /* 1 */ },
6739  { Feature_HasStdEnc, 5280 /* lhu */, MCK_GPR32AsmReg, 1 /* 0 */ },
6740  { Feature_HasStdEnc, 5280 /* lhu */, MCK_Mem, 2 /* 1 */ },
6741  { Feature_InMicroMips, 5280 /* lhu */, MCK_GPR32AsmReg, 1 /* 0 */ },
6742  { Feature_InMicroMips, 5280 /* lhu */, MCK_Mem, 2 /* 1 */ },
6743  { Feature_InMicroMips, 5284 /* lhu16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
6744  { Feature_InMicroMips, 5284 /* lhu16 */, MCK_MicroMipsMem, 2 /* 1 */ },
6745  { Feature_HasStdEnc|Feature_HasEVA, 5290 /* lhue */, MCK_GPR32AsmReg, 1 /* 0 */ },
6746  { Feature_HasStdEnc|Feature_HasEVA, 5290 /* lhue */, MCK_MemOffsetSimm9, 2 /* 1 */ },
6747  { Feature_InMicroMips, 5290 /* lhue */, MCK_GPR32AsmReg, 1 /* 0 */ },
6748  { Feature_InMicroMips, 5290 /* lhue */, MCK_Mem, 2 /* 1 */ },
6749  { Feature_HasDSP|Feature_InMicroMips, 5295 /* lhx */, MCK_GPR32AsmReg, 11 /* 0, 1, 3 */ },
6750  { Feature_HasDSP, 5295 /* lhx */, MCK_GPR32AsmReg, 11 /* 0, 1, 3 */ },
6751  { 0, 5299 /* li */, MCK_GPR32AsmReg, 1 /* 0 */ },
6752  { Feature_InMicroMips, 5302 /* li16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
6753  { Feature_HasMicroMips32r6, 5302 /* li16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
6754  { Feature_HasStdEnc|Feature_HasMips32r6, 5307 /* ll */, MCK_GPR32AsmReg, 1 /* 0 */ },
6755  { Feature_HasStdEnc|Feature_HasMips32r6, 5307 /* ll */, MCK_MemOffsetSimm9, 2 /* 1 */ },
6756  { Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5307 /* ll */, MCK_GPR32AsmReg, 1 /* 0 */ },
6757  { Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5307 /* ll */, MCK_Mem, 2 /* 1 */ },
6758  { Feature_InMicroMips, 5307 /* ll */, MCK_GPR32AsmReg, 1 /* 0 */ },
6759  { Feature_InMicroMips, 5307 /* ll */, MCK_Mem, 2 /* 1 */ },
6760  { Feature_HasStdEnc|Feature_HasMips32r6, 5310 /* lld */, MCK_GPR64AsmReg, 1 /* 0 */ },
6761  { Feature_HasStdEnc|Feature_HasMips32r6, 5310 /* lld */, MCK_MemOffsetSimm9, 2 /* 1 */ },
6762  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 5310 /* lld */, MCK_GPR64AsmReg, 1 /* 0 */ },
6763  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 5310 /* lld */, MCK_Mem, 2 /* 1 */ },
6764  { Feature_HasStdEnc|Feature_HasEVA|Feature_NotInMicroMips, 5314 /* lle */, MCK_GPR32AsmReg, 1 /* 0 */ },
6765  { Feature_HasStdEnc|Feature_HasEVA|Feature_NotInMicroMips, 5314 /* lle */, MCK_MemOffsetSimm9, 2 /* 1 */ },
6766  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 5314 /* lle */, MCK_GPR32AsmReg, 1 /* 0 */ },
6767  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 5314 /* lle */, MCK_Mem, 2 /* 1 */ },
6768  { Feature_InMicroMips, 5314 /* lle */, MCK_GPR32AsmReg, 1 /* 0 */ },
6769  { Feature_InMicroMips, 5314 /* lle */, MCK_Mem, 2 /* 1 */ },
6770  { Feature_HasStdEnc|Feature_HasMSA, 5318 /* lsa */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
6771  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 5318 /* lsa */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
6772  { Feature_HasStdEnc|Feature_HasMips32r6, 5318 /* lsa */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
6773  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 5322 /* lui */, MCK_GPR32AsmReg, 1 /* 0 */ },
6774  { Feature_HasStdEnc, 5322 /* lui */, MCK_GPR32AsmReg, 1 /* 0 */ },
6775  { Feature_InMicroMips, 5322 /* lui */, MCK_GPR32AsmReg, 1 /* 0 */ },
6776  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 5326 /* luxc1 */, MCK_AFGR64AsmReg, 1 /* 0 */ },
6777  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 5326 /* luxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
6778  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 5326 /* luxc1 */, MCK_FGR64AsmReg, 1 /* 0 */ },
6779  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 5326 /* luxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
6780  { Feature_InMicroMips, 5332 /* lw */, MCK_GPR32AsmReg, 1 /* 0 */ },
6781  { Feature_InMicroMips, 5332 /* lw */, MCK_MicroMipsMemSP, 2 /* 1 */ },
6782  { Feature_HasStdEnc|Feature_NotInMicroMips, 5332 /* lw */, MCK_GPR32AsmReg, 1 /* 0 */ },
6783  { Feature_HasStdEnc|Feature_NotInMicroMips, 5332 /* lw */, MCK_Mem, 2 /* 1 */ },
6784  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 5332 /* lw */, MCK_GPR32AsmReg, 1 /* 0 */ },
6785  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 5332 /* lw */, MCK_Mem, 2 /* 1 */ },
6786  { Feature_InMicroMips, 5332 /* lw */, MCK_GPR32AsmReg, 1 /* 0 */ },
6787  { Feature_InMicroMips, 5332 /* lw */, MCK_Mem, 2 /* 1 */ },
6788  { Feature_InMicroMips, 5332 /* lw */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
6789  { Feature_InMicroMips, 5335 /* lw16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
6790  { Feature_InMicroMips, 5335 /* lw16 */, MCK_MicroMipsMem, 2 /* 1 */ },
6791  { Feature_HasStdEnc|Feature_IsNotSoftFloat, 5340 /* lwc1 */, MCK_FGR32AsmReg, 1 /* 0 */ },
6792  { Feature_HasStdEnc|Feature_IsNotSoftFloat, 5340 /* lwc1 */, MCK_Mem, 2 /* 1 */ },
6793  { Feature_HasStdEnc|Feature_HasMips32r6, 5345 /* lwc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
6794  { Feature_HasStdEnc|Feature_HasMips32r6, 5345 /* lwc2 */, MCK_MemOffsetSimm11, 2 /* 1 */ },
6795  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5345 /* lwc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
6796  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5345 /* lwc2 */, MCK_Mem, 2 /* 1 */ },
6797  { Feature_HasStdEnc|Feature_NotInMicroMips, 5350 /* lwc3 */, MCK_COP3AsmReg, 1 /* 0 */ },
6798  { Feature_HasStdEnc|Feature_NotInMicroMips, 5350 /* lwc3 */, MCK_Mem, 2 /* 1 */ },
6799  { Feature_HasStdEnc|Feature_HasEVA|Feature_NotInMicroMips, 5355 /* lwe */, MCK_GPR32AsmReg, 1 /* 0 */ },
6800  { Feature_HasStdEnc|Feature_HasEVA|Feature_NotInMicroMips, 5355 /* lwe */, MCK_MemOffsetSimm9, 2 /* 1 */ },
6801  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 5355 /* lwe */, MCK_GPR32AsmReg, 1 /* 0 */ },
6802  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 5355 /* lwe */, MCK_Mem, 2 /* 1 */ },
6803  { Feature_InMicroMips, 5355 /* lwe */, MCK_GPR32AsmReg, 1 /* 0 */ },
6804  { Feature_InMicroMips, 5355 /* lwe */, MCK_Mem, 2 /* 1 */ },
6805  { Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5359 /* lwl */, MCK_GPR32AsmReg, 1 /* 0 */ },
6806  { Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5359 /* lwl */, MCK_Mem, 2 /* 1 */ },
6807  { Feature_InMicroMips, 5359 /* lwl */, MCK_GPR32AsmReg, 1 /* 0 */ },
6808  { Feature_InMicroMips, 5359 /* lwl */, MCK_Mem, 2 /* 1 */ },
6809  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, 5363 /* lwle */, MCK_GPR32AsmReg, 1 /* 0 */ },
6810  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, 5363 /* lwle */, MCK_MemOffsetSimm9, 2 /* 1 */ },
6811  { Feature_InMicroMips, 5363 /* lwle */, MCK_GPR32AsmReg, 1 /* 0 */ },
6812  { Feature_InMicroMips, 5363 /* lwle */, MCK_Mem, 2 /* 1 */ },
6813  { Feature_InMicroMips, 5368 /* lwm */, MCK_Mem, 2 /* 1 */ },
6814  { Feature_InMicroMips, 5368 /* lwm */, MCK_RegList, 1 /* 0 */ },
6815  { Feature_InMicroMips|Feature_NotMips32r6, 5372 /* lwm16 */, MCK_MemOffsetUimm4, 2 /* 1 */ },
6816  { Feature_InMicroMips|Feature_NotMips32r6, 5372 /* lwm16 */, MCK_RegList16, 1 /* 0 */ },
6817  { Feature_HasMicroMips32r6, 5372 /* lwm16 */, MCK_MemOffsetUimm4, 2 /* 1 */ },
6818  { Feature_HasMicroMips32r6, 5372 /* lwm16 */, MCK_RegList16, 1 /* 0 */ },
6819  { Feature_InMicroMips, 5378 /* lwm32 */, MCK_Mem, 2 /* 1 */ },
6820  { Feature_InMicroMips, 5378 /* lwm32 */, MCK_RegList, 1 /* 0 */ },
6821  { Feature_InMicroMips, 5384 /* lwp */, MCK_Mem, 2 /* 1 */ },
6822  { Feature_InMicroMips, 5384 /* lwp */, MCK_RegPair, 1 /* 0 */ },
6823  { Feature_HasStdEnc|Feature_HasMips32r6, 5388 /* lwpc */, MCK_GPR32AsmReg, 1 /* 0 */ },
6824  { Feature_HasStdEnc|Feature_HasMips32r6, 5388 /* lwpc */, MCK_JumpTarget, 2 /* 1 */ },
6825  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 5388 /* lwpc */, MCK_GPR32AsmReg, 1 /* 0 */ },
6826  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 5388 /* lwpc */, MCK_JumpTarget, 2 /* 1 */ },
6827  { Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5393 /* lwr */, MCK_GPR32AsmReg, 1 /* 0 */ },
6828  { Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5393 /* lwr */, MCK_Mem, 2 /* 1 */ },
6829  { Feature_InMicroMips, 5393 /* lwr */, MCK_GPR32AsmReg, 1 /* 0 */ },
6830  { Feature_InMicroMips, 5393 /* lwr */, MCK_Mem, 2 /* 1 */ },
6831  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, 5397 /* lwre */, MCK_GPR32AsmReg, 1 /* 0 */ },
6832  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, 5397 /* lwre */, MCK_MemOffsetSimm9, 2 /* 1 */ },
6833  { Feature_InMicroMips, 5397 /* lwre */, MCK_GPR32AsmReg, 1 /* 0 */ },
6834  { Feature_InMicroMips, 5397 /* lwre */, MCK_Mem, 2 /* 1 */ },
6835  { Feature_InMicroMips, 5402 /* lwu */, MCK_GPR32AsmReg, 1 /* 0 */ },
6836  { Feature_InMicroMips, 5402 /* lwu */, MCK_Mem, 2 /* 1 */ },
6837  { Feature_HasStdEnc|Feature_HasMips3, 5402 /* lwu */, MCK_GPR64AsmReg, 1 /* 0 */ },
6838  { Feature_HasStdEnc|Feature_HasMips3, 5402 /* lwu */, MCK_Mem, 2 /* 1 */ },
6839  { Feature_HasStdEnc|Feature_HasMips32r6, 5406 /* lwupc */, MCK_GPR32AsmReg, 1 /* 0 */ },
6840  { Feature_HasStdEnc|Feature_HasMips32r6, 5406 /* lwupc */, MCK_JumpTarget, 2 /* 1 */ },
6841  { Feature_HasDSP|Feature_InMicroMips, 5412 /* lwx */, MCK_GPR32AsmReg, 11 /* 0, 1, 3 */ },
6842  { Feature_HasDSP, 5412 /* lwx */, MCK_GPR32AsmReg, 11 /* 0, 1, 3 */ },
6843  { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 5416 /* lwxc1 */, MCK_FGR32AsmReg, 1 /* 0 */ },
6844  { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 5416 /* lwxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
6845  { Feature_InMicroMips, 5422 /* lwxs */, MCK_GPR32AsmReg, 11 /* 0, 1, 3 */ },
6846  { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6, 5427 /* madd */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
6847  { Feature_InMicroMips, 5427 /* madd */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
6848  { Feature_HasDSP|Feature_InMicroMips, 5427 /* madd */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6849  { Feature_HasDSP|Feature_InMicroMips, 5427 /* madd */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6850  { Feature_HasDSP, 5427 /* madd */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6851  { Feature_HasDSP, 5427 /* madd */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6852  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 5432 /* madd.d */, MCK_AFGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
6853  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 5432 /* madd.d */, MCK_FGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
6854  { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 5439 /* madd.s */, MCK_FGR32AsmReg, 15 /* 0, 1, 2, 3 */ },
6855  { Feature_HasStdEnc|Feature_HasMSA, 5446 /* madd_q.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6856  { Feature_HasStdEnc|Feature_HasMSA, 5455 /* madd_q.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6857  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5464 /* maddf.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
6858  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 5464 /* maddf.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
6859  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5472 /* maddf.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
6860  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 5472 /* maddf.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
6861  { Feature_HasStdEnc|Feature_HasMSA, 5480 /* maddr_q.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6862  { Feature_HasStdEnc|Feature_HasMSA, 5490 /* maddr_q.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6863  { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6, 5500 /* maddu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
6864  { Feature_InMicroMips, 5500 /* maddu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
6865  { Feature_HasDSP|Feature_InMicroMips, 5500 /* maddu */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6866  { Feature_HasDSP|Feature_InMicroMips, 5500 /* maddu */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6867  { Feature_HasDSP, 5500 /* maddu */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6868  { Feature_HasDSP, 5500 /* maddu */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6869  { Feature_HasStdEnc|Feature_HasMSA, 5506 /* maddv.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6870  { Feature_HasStdEnc|Feature_HasMSA, 5514 /* maddv.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6871  { Feature_HasStdEnc|Feature_HasMSA, 5522 /* maddv.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6872  { Feature_HasStdEnc|Feature_HasMSA, 5530 /* maddv.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6873  { Feature_HasDSP|Feature_InMicroMips, 5538 /* maq_s.w.phl */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6874  { Feature_HasDSP|Feature_InMicroMips, 5538 /* maq_s.w.phl */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6875  { Feature_HasDSP, 5538 /* maq_s.w.phl */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6876  { Feature_HasDSP, 5538 /* maq_s.w.phl */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6877  { Feature_HasDSP|Feature_InMicroMips, 5550 /* maq_s.w.phr */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6878  { Feature_HasDSP|Feature_InMicroMips, 5550 /* maq_s.w.phr */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6879  { Feature_HasDSP, 5550 /* maq_s.w.phr */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6880  { Feature_HasDSP, 5550 /* maq_s.w.phr */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6881  { Feature_HasDSP|Feature_InMicroMips, 5562 /* maq_sa.w.phl */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6882  { Feature_HasDSP|Feature_InMicroMips, 5562 /* maq_sa.w.phl */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6883  { Feature_HasDSP, 5562 /* maq_sa.w.phl */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6884  { Feature_HasDSP, 5562 /* maq_sa.w.phl */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6885  { Feature_HasDSP|Feature_InMicroMips, 5575 /* maq_sa.w.phr */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6886  { Feature_HasDSP|Feature_InMicroMips, 5575 /* maq_sa.w.phr */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6887  { Feature_HasDSP, 5575 /* maq_sa.w.phr */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
6888  { Feature_HasDSP, 5575 /* maq_sa.w.phr */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
6889  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5588 /* max.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
6890  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 5588 /* max.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
6891  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5594 /* max.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
6892  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 5594 /* max.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
6893  { Feature_HasStdEnc|Feature_HasMSA, 5600 /* max_a.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6894  { Feature_HasStdEnc|Feature_HasMSA, 5608 /* max_a.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6895  { Feature_HasStdEnc|Feature_HasMSA, 5616 /* max_a.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6896  { Feature_HasStdEnc|Feature_HasMSA, 5624 /* max_a.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6897  { Feature_HasStdEnc|Feature_HasMSA, 5632 /* max_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6898  { Feature_HasStdEnc|Feature_HasMSA, 5640 /* max_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6899  { Feature_HasStdEnc|Feature_HasMSA, 5648 /* max_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6900  { Feature_HasStdEnc|Feature_HasMSA, 5656 /* max_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6901  { Feature_HasStdEnc|Feature_HasMSA, 5664 /* max_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6902  { Feature_HasStdEnc|Feature_HasMSA, 5672 /* max_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6903  { Feature_HasStdEnc|Feature_HasMSA, 5680 /* max_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6904  { Feature_HasStdEnc|Feature_HasMSA, 5688 /* max_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6905  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5696 /* maxa.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
6906  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 5696 /* maxa.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
6907  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5703 /* maxa.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
6908  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 5703 /* maxa.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
6909  { Feature_HasStdEnc|Feature_HasMSA, 5710 /* maxi_s.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6910  { Feature_HasStdEnc|Feature_HasMSA, 5719 /* maxi_s.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6911  { Feature_HasStdEnc|Feature_HasMSA, 5728 /* maxi_s.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6912  { Feature_HasStdEnc|Feature_HasMSA, 5737 /* maxi_s.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6913  { Feature_HasStdEnc|Feature_HasMSA, 5746 /* maxi_u.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6914  { Feature_HasStdEnc|Feature_HasMSA, 5755 /* maxi_u.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6915  { Feature_HasStdEnc|Feature_HasMSA, 5764 /* maxi_u.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6916  { Feature_HasStdEnc|Feature_HasMSA, 5773 /* maxi_u.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6917  { 0, 5782 /* mfc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
6918  { 0, 5782 /* mfc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
6919  { Feature_HasStdEnc|Feature_HasMips32, 5782 /* mfc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
6920  { Feature_HasStdEnc|Feature_HasMips32, 5782 /* mfc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
6921  { Feature_HasStdEnc|Feature_IsNotSoftFloat, 5787 /* mfc1 */, MCK_FGR32AsmReg, 2 /* 1 */ },
6922  { Feature_HasStdEnc|Feature_IsNotSoftFloat, 5787 /* mfc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
6923  { 0, 5792 /* mfc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
6924  { 0, 5792 /* mfc2 */, MCK_GPR32AsmReg, 1 /* 0 */ },
6925  { Feature_HasStdEnc, 5792 /* mfc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
6926  { Feature_HasStdEnc, 5792 /* mfc2 */, MCK_GPR32AsmReg, 1 /* 0 */ },
6927  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat, 5797 /* mfhc1 */, MCK_AFGR64AsmReg, 2 /* 1 */ },
6928  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat, 5797 /* mfhc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
6929  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat, 5797 /* mfhc1 */, MCK_FGR64AsmReg, 2 /* 1 */ },
6930  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat, 5797 /* mfhc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
6931  { Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5803 /* mfhi */, MCK_GPR32AsmReg, 1 /* 0 */ },
6932  { Feature_InMicroMips, 5803 /* mfhi */, MCK_GPR32AsmReg, 1 /* 0 */ },
6933  { Feature_InMicroMips, 5803 /* mfhi */, MCK_GPR32AsmReg, 1 /* 0 */ },
6934  { Feature_HasDSP|Feature_InMicroMips, 5803 /* mfhi */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
6935  { Feature_HasDSP|Feature_InMicroMips, 5803 /* mfhi */, MCK_GPR32AsmReg, 1 /* 0 */ },
6936  { Feature_HasDSP, 5803 /* mfhi */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
6937  { Feature_HasDSP, 5803 /* mfhi */, MCK_GPR32AsmReg, 1 /* 0 */ },
6938  { Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5808 /* mflo */, MCK_GPR32AsmReg, 1 /* 0 */ },
6939  { Feature_InMicroMips, 5808 /* mflo */, MCK_GPR32AsmReg, 1 /* 0 */ },
6940  { Feature_InMicroMips, 5808 /* mflo */, MCK_GPR32AsmReg, 1 /* 0 */ },
6941  { Feature_HasDSP|Feature_InMicroMips, 5808 /* mflo */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
6942  { Feature_HasDSP|Feature_InMicroMips, 5808 /* mflo */, MCK_GPR32AsmReg, 1 /* 0 */ },
6943  { Feature_HasDSP, 5808 /* mflo */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
6944  { Feature_HasDSP, 5808 /* mflo */, MCK_GPR32AsmReg, 1 /* 0 */ },
6945  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5813 /* min.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
6946  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 5813 /* min.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
6947  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5819 /* min.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
6948  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 5819 /* min.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
6949  { Feature_HasStdEnc|Feature_HasMSA, 5825 /* min_a.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6950  { Feature_HasStdEnc|Feature_HasMSA, 5833 /* min_a.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6951  { Feature_HasStdEnc|Feature_HasMSA, 5841 /* min_a.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6952  { Feature_HasStdEnc|Feature_HasMSA, 5849 /* min_a.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6953  { Feature_HasStdEnc|Feature_HasMSA, 5857 /* min_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6954  { Feature_HasStdEnc|Feature_HasMSA, 5865 /* min_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6955  { Feature_HasStdEnc|Feature_HasMSA, 5873 /* min_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6956  { Feature_HasStdEnc|Feature_HasMSA, 5881 /* min_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6957  { Feature_HasStdEnc|Feature_HasMSA, 5889 /* min_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6958  { Feature_HasStdEnc|Feature_HasMSA, 5897 /* min_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6959  { Feature_HasStdEnc|Feature_HasMSA, 5905 /* min_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6960  { Feature_HasStdEnc|Feature_HasMSA, 5913 /* min_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6961  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5921 /* mina.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
6962  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 5921 /* mina.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
6963  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5928 /* mina.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
6964  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 5928 /* mina.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
6965  { Feature_HasStdEnc|Feature_HasMSA, 5935 /* mini_s.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6966  { Feature_HasStdEnc|Feature_HasMSA, 5944 /* mini_s.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6967  { Feature_HasStdEnc|Feature_HasMSA, 5953 /* mini_s.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6968  { Feature_HasStdEnc|Feature_HasMSA, 5962 /* mini_s.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6969  { Feature_HasStdEnc|Feature_HasMSA, 5971 /* mini_u.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6970  { Feature_HasStdEnc|Feature_HasMSA, 5980 /* mini_u.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6971  { Feature_HasStdEnc|Feature_HasMSA, 5989 /* mini_u.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6972  { Feature_HasStdEnc|Feature_HasMSA, 5998 /* mini_u.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6973  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 6007 /* mod */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
6974  { Feature_HasStdEnc|Feature_HasMips32r6, 6007 /* mod */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
6975  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 6007 /* mod */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
6976  { Feature_HasStdEnc|Feature_HasMSA, 6011 /* mod_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6977  { Feature_HasStdEnc|Feature_HasMSA, 6019 /* mod_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6978  { Feature_HasStdEnc|Feature_HasMSA, 6027 /* mod_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6979  { Feature_HasStdEnc|Feature_HasMSA, 6035 /* mod_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6980  { Feature_HasStdEnc|Feature_HasMSA, 6043 /* mod_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6981  { Feature_HasStdEnc|Feature_HasMSA, 6051 /* mod_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6982  { Feature_HasStdEnc|Feature_HasMSA, 6059 /* mod_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6983  { Feature_HasStdEnc|Feature_HasMSA, 6067 /* mod_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
6984  { Feature_HasDSP, 6075 /* modsub */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
6985  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 6082 /* modu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
6986  { Feature_HasStdEnc|Feature_HasMips32r6, 6082 /* modu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
6987  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 6082 /* modu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
6988  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat, 6087 /* mov.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
6989  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 6087 /* mov.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
6990  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, 6087 /* mov.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
6991  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 6093 /* mov.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
6992  { Feature_HasStdEnc|Feature_IsNotSoftFloat, 6093 /* mov.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
6993  { Feature_IsGP32bit|Feature_NotInMicroMips, 6099 /* move */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
6994  { Feature_IsGP32bit|Feature_NotInMicroMips, 6099 /* move */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
6995  { Feature_InMicroMips, 6099 /* move */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
6996  { Feature_IsGP64bit, 6099 /* move */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6997  { Feature_IsGP64bit, 6099 /* move */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
6998  { Feature_HasStdEnc|Feature_HasMSA, 6104 /* move.v */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
6999  { Feature_HasMicroMips32r6, 6111 /* move16 */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7000  { Feature_InMicroMips, 6118 /* movep */, MCK_GPRMM16AsmRegMoveP, 6 /* 1, 2 */ },
7001  { Feature_InMicroMips, 6118 /* movep */, MCK_MovePRegPair, 1 /* 0 */ },
7002  { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 6124 /* movf */, MCK_FCCAsmReg, 4 /* 2 */ },
7003  { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 6124 /* movf */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7004  { Feature_InMicroMips, 6124 /* movf */, MCK_FCCAsmReg, 4 /* 2 */ },
7005  { Feature_InMicroMips, 6124 /* movf */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7006  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 6129 /* movf.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
7007  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 6129 /* movf.d */, MCK_FCCAsmReg, 4 /* 2 */ },
7008  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 6129 /* movf.d */, MCK_FCCAsmReg, 4 /* 2 */ },
7009  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 6129 /* movf.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
7010  { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 6136 /* movf.s */, MCK_FCCAsmReg, 4 /* 2 */ },
7011  { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 6136 /* movf.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
7012  { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6, 6143 /* movn */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7013  { Feature_InMicroMips, 6143 /* movn */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7014  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 6148 /* movn.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
7015  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 6148 /* movn.d */, MCK_GPR32AsmReg, 4 /* 2 */ },
7016  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 6148 /* movn.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
7017  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 6148 /* movn.d */, MCK_GPR32AsmReg, 4 /* 2 */ },
7018  { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 6155 /* movn.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
7019  { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 6155 /* movn.s */, MCK_GPR32AsmReg, 4 /* 2 */ },
7020  { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 6162 /* movt */, MCK_FCCAsmReg, 4 /* 2 */ },
7021  { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 6162 /* movt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7022  { Feature_InMicroMips, 6162 /* movt */, MCK_FCCAsmReg, 4 /* 2 */ },
7023  { Feature_InMicroMips, 6162 /* movt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7024  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 6167 /* movt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
7025  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 6167 /* movt.d */, MCK_FCCAsmReg, 4 /* 2 */ },
7026  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 6167 /* movt.d */, MCK_FCCAsmReg, 4 /* 2 */ },
7027  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 6167 /* movt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
7028  { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 6174 /* movt.s */, MCK_FCCAsmReg, 4 /* 2 */ },
7029  { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 6174 /* movt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
7030  { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6, 6181 /* movz */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7031  { Feature_InMicroMips, 6181 /* movz */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7032  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 6186 /* movz.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
7033  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 6186 /* movz.d */, MCK_GPR32AsmReg, 4 /* 2 */ },
7034  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 6186 /* movz.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
7035  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 6186 /* movz.d */, MCK_GPR32AsmReg, 4 /* 2 */ },
7036  { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 6193 /* movz.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
7037  { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 6193 /* movz.s */, MCK_GPR32AsmReg, 4 /* 2 */ },
7038  { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6, 6200 /* msub */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7039  { Feature_InMicroMips, 6200 /* msub */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7040  { Feature_HasDSP|Feature_InMicroMips, 6200 /* msub */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
7041  { Feature_HasDSP|Feature_InMicroMips, 6200 /* msub */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
7042  { Feature_HasDSP, 6200 /* msub */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
7043  { Feature_HasDSP, 6200 /* msub */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
7044  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 6205 /* msub.d */, MCK_AFGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
7045  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 6205 /* msub.d */, MCK_FGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
7046  { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 6212 /* msub.s */, MCK_FGR32AsmReg, 15 /* 0, 1, 2, 3 */ },
7047  { Feature_HasStdEnc|Feature_HasMSA, 6219 /* msub_q.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7048  { Feature_HasStdEnc|Feature_HasMSA, 6228 /* msub_q.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7049  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6237 /* msubf.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
7050  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 6237 /* msubf.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
7051  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6245 /* msubf.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
7052  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 6245 /* msubf.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
7053  { Feature_HasStdEnc|Feature_HasMSA, 6253 /* msubr_q.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7054  { Feature_HasStdEnc|Feature_HasMSA, 6263 /* msubr_q.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7055  { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6, 6273 /* msubu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7056  { Feature_InMicroMips, 6273 /* msubu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7057  { Feature_HasDSP|Feature_InMicroMips, 6273 /* msubu */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
7058  { Feature_HasDSP|Feature_InMicroMips, 6273 /* msubu */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
7059  { Feature_HasDSP, 6273 /* msubu */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
7060  { Feature_HasDSP, 6273 /* msubu */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
7061  { Feature_HasStdEnc|Feature_HasMSA, 6279 /* msubv.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7062  { Feature_HasStdEnc|Feature_HasMSA, 6287 /* msubv.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7063  { Feature_HasStdEnc|Feature_HasMSA, 6295 /* msubv.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7064  { Feature_HasStdEnc|Feature_HasMSA, 6303 /* msubv.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7065  { 0, 6311 /* mtc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
7066  { 0, 6311 /* mtc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
7067  { Feature_HasStdEnc|Feature_HasMips32, 6311 /* mtc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
7068  { Feature_HasStdEnc|Feature_HasMips32, 6311 /* mtc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
7069  { Feature_HasStdEnc|Feature_IsNotSoftFloat, 6316 /* mtc1 */, MCK_FGR32AsmReg, 2 /* 1 */ },
7070  { Feature_HasStdEnc|Feature_IsNotSoftFloat, 6316 /* mtc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
7071  { 0, 6321 /* mtc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
7072  { 0, 6321 /* mtc2 */, MCK_GPR32AsmReg, 1 /* 0 */ },
7073  { Feature_HasStdEnc, 6321 /* mtc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
7074  { Feature_HasStdEnc, 6321 /* mtc2 */, MCK_GPR32AsmReg, 1 /* 0 */ },
7075  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat, 6326 /* mthc1 */, MCK_AFGR64AsmReg, 2 /* 1 */ },
7076  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat, 6326 /* mthc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
7077  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat, 6326 /* mthc1 */, MCK_FGR64AsmReg, 2 /* 1 */ },
7078  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat, 6326 /* mthc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
7079  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 6332 /* mthi */, MCK_GPR32AsmReg, 1 /* 0 */ },
7080  { Feature_InMicroMips, 6332 /* mthi */, MCK_GPR32AsmReg, 1 /* 0 */ },
7081  { Feature_HasDSP|Feature_InMicroMips, 6332 /* mthi */, MCK_GPR32AsmReg, 1 /* 0 */ },
7082  { Feature_HasDSP|Feature_InMicroMips, 6332 /* mthi */, MCK_HI32DSPAsmReg, 2 /* 1 */ },
7083  { Feature_HasDSP, 6332 /* mthi */, MCK_GPR32AsmReg, 1 /* 0 */ },
7084  { Feature_HasDSP, 6332 /* mthi */, MCK_HI32DSPAsmReg, 2 /* 1 */ },
7085  { Feature_HasDSP|Feature_InMicroMips, 6337 /* mthlip */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
7086  { Feature_HasDSP|Feature_InMicroMips, 6337 /* mthlip */, MCK_GPR32AsmReg, 1 /* 0 */ },
7087  { Feature_HasDSP, 6337 /* mthlip */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
7088  { Feature_HasDSP, 6337 /* mthlip */, MCK_GPR32AsmReg, 1 /* 0 */ },
7089  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 6344 /* mtlo */, MCK_GPR32AsmReg, 1 /* 0 */ },
7090  { Feature_InMicroMips, 6344 /* mtlo */, MCK_GPR32AsmReg, 1 /* 0 */ },
7091  { Feature_HasDSP|Feature_InMicroMips, 6344 /* mtlo */, MCK_GPR32AsmReg, 1 /* 0 */ },
7092  { Feature_HasDSP|Feature_InMicroMips, 6344 /* mtlo */, MCK_LO32DSPAsmReg, 2 /* 1 */ },
7093  { Feature_HasDSP, 6344 /* mtlo */, MCK_GPR32AsmReg, 1 /* 0 */ },
7094  { Feature_HasDSP, 6344 /* mtlo */, MCK_LO32DSPAsmReg, 2 /* 1 */ },
7095  { Feature_HasCnMips, 6349 /* mtm0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
7096  { Feature_HasCnMips, 6354 /* mtm1 */, MCK_GPR64AsmReg, 1 /* 0 */ },
7097  { Feature_HasCnMips, 6359 /* mtm2 */, MCK_GPR64AsmReg, 1 /* 0 */ },
7098  { Feature_HasCnMips, 6364 /* mtp0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
7099  { Feature_HasCnMips, 6369 /* mtp1 */, MCK_GPR64AsmReg, 1 /* 0 */ },
7100  { Feature_HasCnMips, 6374 /* mtp2 */, MCK_GPR64AsmReg, 1 /* 0 */ },
7101  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 6379 /* muh */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7102  { Feature_HasStdEnc|Feature_HasMips32r6, 6379 /* muh */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7103  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 6379 /* muh */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7104  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 6383 /* muhu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7105  { Feature_HasStdEnc|Feature_HasMips32r6, 6383 /* muhu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7106  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 6383 /* muhu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7107  { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6, 6388 /* mul */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7108  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 6388 /* mul */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7109  { Feature_InMicroMips, 6388 /* mul */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7110  { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6, 6388 /* mul */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7111  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 6388 /* mul */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7112  { Feature_HasStdEnc|Feature_HasMips32r6, 6388 /* mul */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7113  { Feature_InMicroMips, 6388 /* mul */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7114  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat, 6392 /* mul.d */, MCK_AFGR64AsmReg, 7 /* 0, 1, 2 */ },
7115  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 6392 /* mul.d */, MCK_AFGR64AsmReg, 7 /* 0, 1, 2 */ },
7116  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, 6392 /* mul.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
7117  { Feature_HasDSPR2|Feature_InMicroMips, 6398 /* mul.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7118  { Feature_HasDSPR2, 6398 /* mul.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7119  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 6405 /* mul.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
7120  { Feature_HasStdEnc|Feature_IsNotSoftFloat, 6405 /* mul.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
7121  { Feature_HasStdEnc|Feature_HasMSA, 6411 /* mul_q.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7122  { Feature_HasStdEnc|Feature_HasMSA, 6419 /* mul_q.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7123  { Feature_HasDSPR2|Feature_InMicroMips, 6427 /* mul_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7124  { Feature_HasDSPR2, 6427 /* mul_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7125  { Feature_HasDSP|Feature_InMicroMips, 6436 /* muleq_s.w.phl */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7126  { Feature_HasDSP, 6436 /* muleq_s.w.phl */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7127  { Feature_HasDSP|Feature_InMicroMips, 6450 /* muleq_s.w.phr */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7128  { Feature_HasDSP, 6450 /* muleq_s.w.phr */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7129  { Feature_HasDSP|Feature_InMicroMips, 6464 /* muleu_s.ph.qbl */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7130  { Feature_HasDSP, 6464 /* muleu_s.ph.qbl */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7131  { Feature_HasDSP|Feature_InMicroMips, 6479 /* muleu_s.ph.qbr */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7132  { Feature_HasDSP, 6479 /* muleu_s.ph.qbr */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7133  { Feature_HasDSP|Feature_InMicroMips, 6494 /* mulq_rs.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7134  { Feature_HasDSP, 6494 /* mulq_rs.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7135  { Feature_HasDSPR2|Feature_InMicroMips, 6505 /* mulq_rs.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7136  { Feature_HasDSPR2, 6505 /* mulq_rs.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7137  { Feature_HasDSPR2|Feature_InMicroMips, 6515 /* mulq_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7138  { Feature_HasDSPR2, 6515 /* mulq_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7139  { Feature_HasDSPR2|Feature_InMicroMips, 6525 /* mulq_s.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7140  { Feature_HasDSPR2, 6525 /* mulq_s.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7141  { Feature_HasStdEnc|Feature_HasMSA, 6534 /* mulr_q.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7142  { Feature_HasStdEnc|Feature_HasMSA, 6543 /* mulr_q.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7143  { Feature_HasDSPR2, 6552 /* mulsa.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
7144  { Feature_HasDSPR2, 6552 /* mulsa.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
7145  { Feature_HasDSP, 6563 /* mulsaq_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
7146  { Feature_HasDSP, 6563 /* mulsaq_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
7147  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 6577 /* mult */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7148  { Feature_InMicroMips, 6577 /* mult */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7149  { Feature_HasDSP|Feature_InMicroMips, 6577 /* mult */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
7150  { Feature_HasDSP|Feature_InMicroMips, 6577 /* mult */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
7151  { Feature_HasDSP, 6577 /* mult */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
7152  { Feature_HasDSP, 6577 /* mult */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
7153  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 6582 /* multu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7154  { Feature_InMicroMips, 6582 /* multu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7155  { Feature_HasDSP|Feature_InMicroMips, 6582 /* multu */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
7156  { Feature_HasDSP|Feature_InMicroMips, 6582 /* multu */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
7157  { Feature_HasDSP, 6582 /* multu */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
7158  { Feature_HasDSP, 6582 /* multu */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
7159  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 6588 /* mulu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7160  { Feature_HasStdEnc|Feature_HasMips32r6, 6588 /* mulu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7161  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 6588 /* mulu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7162  { Feature_HasStdEnc|Feature_HasMSA, 6593 /* mulv.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7163  { Feature_HasStdEnc|Feature_HasMSA, 6600 /* mulv.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7164  { Feature_HasStdEnc|Feature_HasMSA, 6607 /* mulv.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7165  { Feature_HasStdEnc|Feature_HasMSA, 6614 /* mulv.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7166  { 0, 6621 /* neg */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7167  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat, 6625 /* neg.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
7168  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 6625 /* neg.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
7169  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, 6625 /* neg.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
7170  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 6631 /* neg.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
7171  { Feature_HasStdEnc|Feature_IsNotSoftFloat, 6631 /* neg.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
7172  { 0, 6637 /* negu */, MCK_GPR32AsmReg, 1 /* 0 */ },
7173  { 0, 6637 /* negu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7174  { Feature_HasStdEnc|Feature_HasMSA, 6642 /* nloc.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7175  { Feature_HasStdEnc|Feature_HasMSA, 6649 /* nloc.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7176  { Feature_HasStdEnc|Feature_HasMSA, 6656 /* nloc.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7177  { Feature_HasStdEnc|Feature_HasMSA, 6663 /* nloc.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7178  { Feature_HasStdEnc|Feature_HasMSA, 6670 /* nlzc.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7179  { Feature_HasStdEnc|Feature_HasMSA, 6677 /* nlzc.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7180  { Feature_HasStdEnc|Feature_HasMSA, 6684 /* nlzc.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7181  { Feature_HasStdEnc|Feature_HasMSA, 6691 /* nlzc.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7182  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 6698 /* nmadd.d */, MCK_AFGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
7183  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 6698 /* nmadd.d */, MCK_FGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
7184  { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 6706 /* nmadd.s */, MCK_FGR32AsmReg, 15 /* 0, 1, 2, 3 */ },
7185  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 6714 /* nmsub.d */, MCK_AFGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
7186  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 6714 /* nmsub.d */, MCK_FGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
7187  { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 6722 /* nmsub.s */, MCK_FGR32AsmReg, 15 /* 0, 1, 2, 3 */ },
7188  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 6734 /* nor */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7189  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 6734 /* nor */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7190  { Feature_HasStdEnc, 6734 /* nor */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7191  { Feature_InMicroMips, 6734 /* nor */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7192  { 0, 6734 /* nor */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7193  { Feature_HasStdEnc|Feature_HasMSA, 6738 /* nor.v */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7194  { Feature_HasStdEnc|Feature_HasMSA, 6744 /* nori.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7195  { 0, 6751 /* not */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7196  { Feature_InMicroMips|Feature_NotMips32r6|Feature_NotMips64r6, 6755 /* not16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
7197  { Feature_HasMicroMips32r6, 6755 /* not16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
7198  { Feature_HasStdEnc|Feature_NotInMicroMips, 6761 /* or */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7199  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 6761 /* or */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7200  { Feature_InMicroMips, 6761 /* or */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7201  { 0, 6761 /* or */, MCK_GPR32AsmReg, 1 /* 0 */ },
7202  { Feature_HasStdEnc|Feature_NotInMicroMips, 6761 /* or */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7203  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 6761 /* or */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7204  { Feature_InMicroMips, 6761 /* or */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7205  { 0, 6761 /* or */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7206  { Feature_HasStdEnc|Feature_HasMSA, 6764 /* or.v */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7207  { Feature_InMicroMips|Feature_NotMips32r6|Feature_NotMips64r6, 6769 /* or16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
7208  { Feature_InMicroMips, 6769 /* or16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
7209  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 6774 /* ori */, MCK_GPR32AsmReg, 1 /* 0 */ },
7210  { Feature_HasStdEnc, 6774 /* ori */, MCK_GPR32AsmReg, 1 /* 0 */ },
7211  { Feature_InMicroMips, 6774 /* ori */, MCK_GPR32AsmReg, 1 /* 0 */ },
7212  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 6774 /* ori */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7213  { Feature_HasStdEnc, 6774 /* ori */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7214  { Feature_InMicroMips, 6774 /* ori */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7215  { Feature_HasStdEnc|Feature_HasMSA, 6778 /* ori.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7216  { Feature_HasDSP|Feature_InMicroMips, 6784 /* packrl.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7217  { Feature_HasDSP, 6784 /* packrl.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7218  { Feature_HasStdEnc|Feature_HasMSA, 6800 /* pckev.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7219  { Feature_HasStdEnc|Feature_HasMSA, 6808 /* pckev.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7220  { Feature_HasStdEnc|Feature_HasMSA, 6816 /* pckev.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7221  { Feature_HasStdEnc|Feature_HasMSA, 6824 /* pckev.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7222  { Feature_HasStdEnc|Feature_HasMSA, 6832 /* pckod.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7223  { Feature_HasStdEnc|Feature_HasMSA, 6840 /* pckod.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7224  { Feature_HasStdEnc|Feature_HasMSA, 6848 /* pckod.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7225  { Feature_HasStdEnc|Feature_HasMSA, 6856 /* pckod.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7226  { Feature_HasStdEnc|Feature_HasMSA, 6864 /* pcnt.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7227  { Feature_HasStdEnc|Feature_HasMSA, 6871 /* pcnt.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7228  { Feature_HasStdEnc|Feature_HasMSA, 6878 /* pcnt.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7229  { Feature_HasStdEnc|Feature_HasMSA, 6885 /* pcnt.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7230  { Feature_HasDSP|Feature_InMicroMips, 6892 /* pick.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7231  { Feature_HasDSP, 6892 /* pick.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7232  { Feature_HasDSP|Feature_InMicroMips, 6900 /* pick.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7233  { Feature_HasDSP, 6900 /* pick.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7234  { Feature_HasCnMips, 6908 /* pop */, MCK_GPR32AsmReg, 1 /* 0 */ },
7235  { Feature_HasCnMips, 6908 /* pop */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7236  { Feature_HasDSP|Feature_InMicroMips, 6912 /* preceq.w.phl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7237  { Feature_HasDSP, 6912 /* preceq.w.phl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7238  { Feature_HasDSP|Feature_InMicroMips, 6925 /* preceq.w.phr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7239  { Feature_HasDSP, 6925 /* preceq.w.phr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7240  { Feature_HasDSP|Feature_InMicroMips, 6938 /* precequ.ph.qbl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7241  { Feature_HasDSP, 6938 /* precequ.ph.qbl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7242  { Feature_HasDSP|Feature_InMicroMips, 6953 /* precequ.ph.qbla */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7243  { Feature_HasDSP, 6953 /* precequ.ph.qbla */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7244  { Feature_HasDSP|Feature_InMicroMips, 6969 /* precequ.ph.qbr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7245  { Feature_HasDSP, 6969 /* precequ.ph.qbr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7246  { Feature_HasDSP|Feature_InMicroMips, 6984 /* precequ.ph.qbra */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7247  { Feature_HasDSP, 6984 /* precequ.ph.qbra */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7248  { Feature_HasDSP|Feature_InMicroMips, 7000 /* preceu.ph.qbl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7249  { Feature_HasDSP, 7000 /* preceu.ph.qbl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7250  { Feature_HasDSP|Feature_InMicroMips, 7014 /* preceu.ph.qbla */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7251  { Feature_HasDSP, 7014 /* preceu.ph.qbla */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7252  { Feature_HasDSP|Feature_InMicroMips, 7029 /* preceu.ph.qbr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7253  { Feature_HasDSP, 7029 /* preceu.ph.qbr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7254  { Feature_HasDSP|Feature_InMicroMips, 7043 /* preceu.ph.qbra */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7255  { Feature_HasDSP, 7043 /* preceu.ph.qbra */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7256  { Feature_HasDSPR2|Feature_InMicroMips, 7058 /* precr.qb.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7257  { Feature_HasDSPR2, 7058 /* precr.qb.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7258  { Feature_HasDSPR2|Feature_InMicroMips, 7070 /* precr_sra.ph.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7259  { Feature_HasDSPR2, 7070 /* precr_sra.ph.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7260  { Feature_HasDSPR2|Feature_InMicroMips, 7085 /* precr_sra_r.ph.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7261  { Feature_HasDSPR2, 7085 /* precr_sra_r.ph.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7262  { Feature_HasDSP|Feature_InMicroMips, 7102 /* precrq.ph.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7263  { Feature_HasDSP, 7102 /* precrq.ph.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7264  { Feature_HasDSP|Feature_InMicroMips, 7114 /* precrq.qb.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7265  { Feature_HasDSP, 7114 /* precrq.qb.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7266  { Feature_HasDSP|Feature_InMicroMips, 7127 /* precrq_rs.ph.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7267  { Feature_HasDSP, 7127 /* precrq_rs.ph.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7268  { Feature_HasDSP|Feature_InMicroMips, 7142 /* precrqu_s.qb.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7269  { Feature_HasDSP, 7142 /* precrqu_s.qb.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7270  { Feature_HasStdEnc|Feature_HasMips32r6, 7158 /* pref */, MCK_MemOffsetSimm9, 2 /* 1 */ },
7271  { Feature_HasStdEnc|Feature_HasMips3_32|Feature_NotMips32r6|Feature_NotMips64r6, 7158 /* pref */, MCK_Mem, 2 /* 1 */ },
7272  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 7158 /* pref */, MCK_Mem, 2 /* 1 */ },
7273  { Feature_InMicroMips, 7158 /* pref */, MCK_Mem, 2 /* 1 */ },
7274  { Feature_HasStdEnc|Feature_HasEVA, 7163 /* prefe */, MCK_Mem, 2 /* 1 */ },
7275  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 7163 /* prefe */, MCK_Mem, 2 /* 1 */ },
7276  { Feature_InMicroMips, 7163 /* prefe */, MCK_Mem, 2 /* 1 */ },
7277  { Feature_InMicroMips, 7169 /* prefx */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
7278  { Feature_HasDSPR2|Feature_InMicroMips, 7175 /* prepend */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7279  { Feature_HasDSPR2, 7175 /* prepend */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7280  { Feature_HasDSP|Feature_InMicroMips, 7183 /* raddu.w.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7281  { Feature_HasDSP, 7183 /* raddu.w.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7282  { Feature_HasDSP|Feature_InMicroMips, 7194 /* rddsp */, MCK_GPR32AsmReg, 1 /* 0 */ },
7283  { Feature_HasDSP, 7194 /* rddsp */, MCK_GPR32AsmReg, 1 /* 0 */ },
7284  { Feature_HasStdEnc|Feature_InMicroMips|Feature_NotMips32r6, 7200 /* rdhwr */, MCK_GPR32AsmReg, 1 /* 0 */ },
7285  { Feature_HasStdEnc|Feature_InMicroMips|Feature_NotMips32r6, 7200 /* rdhwr */, MCK_HWRegsAsmReg, 2 /* 1 */ },
7286  { Feature_HasStdEnc|Feature_NotInMicroMips, 7200 /* rdhwr */, MCK_GPR32AsmReg, 1 /* 0 */ },
7287  { Feature_HasStdEnc|Feature_NotInMicroMips, 7200 /* rdhwr */, MCK_HWRegsAsmReg, 2 /* 1 */ },
7288  { Feature_HasMicroMips32r6, 7200 /* rdhwr */, MCK_GPR32AsmReg, 1 /* 0 */ },
7289  { Feature_HasMicroMips32r6, 7200 /* rdhwr */, MCK_HWRegsAsmReg, 2 /* 1 */ },
7290  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 7200 /* rdhwr */, MCK_GPR32AsmReg, 1 /* 0 */ },
7291  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 7200 /* rdhwr */, MCK_HWRegsAsmReg, 2 /* 1 */ },
7292  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 7206 /* rdpgpr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7293  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 7213 /* recip.d */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
7294  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 7221 /* recip.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
7295  { Feature_HasDSP|Feature_InMicroMips, 7229 /* repl.ph */, MCK_GPR32AsmReg, 1 /* 0 */ },
7296  { Feature_HasDSP, 7229 /* repl.ph */, MCK_GPR32AsmReg, 1 /* 0 */ },
7297  { Feature_HasDSP|Feature_InMicroMips, 7237 /* repl.qb */, MCK_GPR32AsmReg, 1 /* 0 */ },
7298  { Feature_HasDSP, 7237 /* repl.qb */, MCK_GPR32AsmReg, 1 /* 0 */ },
7299  { Feature_HasDSP|Feature_InMicroMips, 7245 /* replv.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7300  { Feature_HasDSP, 7245 /* replv.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7301  { Feature_HasDSP|Feature_InMicroMips, 7254 /* replv.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7302  { Feature_HasDSP, 7254 /* replv.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7303  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7263 /* rint.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
7304  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 7263 /* rint.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
7305  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7270 /* rint.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
7306  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 7270 /* rint.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
7307  { 0, 7277 /* rol */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7308  { 0, 7277 /* rol */, MCK_GPR32AsmReg, 1 /* 0 */ },
7309  { 0, 7277 /* rol */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7310  { 0, 7277 /* rol */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7311  { 0, 7281 /* ror */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7312  { 0, 7281 /* ror */, MCK_GPR32AsmReg, 1 /* 0 */ },
7313  { 0, 7281 /* ror */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7314  { 0, 7281 /* ror */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7315  { Feature_HasStdEnc|Feature_HasMips32r2, 7285 /* rotr */, MCK_GPR32AsmReg, 1 /* 0 */ },
7316  { Feature_InMicroMips, 7285 /* rotr */, MCK_GPR32AsmReg, 1 /* 0 */ },
7317  { Feature_HasStdEnc|Feature_HasMips32r2, 7285 /* rotr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7318  { Feature_InMicroMips, 7285 /* rotr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7319  { Feature_HasStdEnc|Feature_HasMips32r2, 7290 /* rotrv */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7320  { Feature_InMicroMips, 7290 /* rotrv */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7321  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7296 /* round.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
7322  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 7296 /* round.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
7323  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7306 /* round.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
7324  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7306 /* round.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
7325  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 7306 /* round.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
7326  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 7306 /* round.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
7327  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 7316 /* round.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
7328  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 7316 /* round.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
7329  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 7316 /* round.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
7330  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 7316 /* round.w.d */, MCK_FGR64AsmReg, 2 /* 1 */ },
7331  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 7316 /* round.w.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
7332  { Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat, 7326 /* round.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
7333  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 7326 /* round.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
7334  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 7336 /* rsqrt.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
7335  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 7336 /* rsqrt.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
7336  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 7344 /* rsqrt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
7337  { Feature_HasStdEnc|Feature_HasMSA, 7352 /* sat_s.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7338  { Feature_HasStdEnc|Feature_HasMSA, 7360 /* sat_s.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7339  { Feature_HasStdEnc|Feature_HasMSA, 7368 /* sat_s.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7340  { Feature_HasStdEnc|Feature_HasMSA, 7376 /* sat_s.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7341  { Feature_HasStdEnc|Feature_HasMSA, 7384 /* sat_u.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7342  { Feature_HasStdEnc|Feature_HasMSA, 7392 /* sat_u.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7343  { Feature_HasStdEnc|Feature_HasMSA, 7400 /* sat_u.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7344  { Feature_HasStdEnc|Feature_HasMSA, 7408 /* sat_u.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7345  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 7416 /* sb */, MCK_GPR32AsmReg, 1 /* 0 */ },
7346  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 7416 /* sb */, MCK_Mem, 2 /* 1 */ },
7347  { Feature_HasStdEnc, 7416 /* sb */, MCK_GPR32AsmReg, 1 /* 0 */ },
7348  { Feature_HasStdEnc, 7416 /* sb */, MCK_Mem, 2 /* 1 */ },
7349  { Feature_InMicroMips, 7416 /* sb */, MCK_GPR32AsmReg, 1 /* 0 */ },
7350  { Feature_InMicroMips, 7416 /* sb */, MCK_Mem, 2 /* 1 */ },
7351  { Feature_InMicroMips, 7419 /* sb16 */, MCK_GPRMM16AsmRegZero, 1 /* 0 */ },
7352  { Feature_InMicroMips, 7419 /* sb16 */, MCK_MicroMipsMem, 2 /* 1 */ },
7353  { Feature_HasMicroMips32r6, 7419 /* sb16 */, MCK_GPRMM16AsmRegZero, 1 /* 0 */ },
7354  { Feature_HasMicroMips32r6, 7419 /* sb16 */, MCK_MicroMipsMem, 2 /* 1 */ },
7355  { Feature_HasStdEnc|Feature_HasEVA, 7424 /* sbe */, MCK_GPR32AsmReg, 1 /* 0 */ },
7356  { Feature_HasStdEnc|Feature_HasEVA, 7424 /* sbe */, MCK_MemOffsetSimm9, 2 /* 1 */ },
7357  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 7424 /* sbe */, MCK_GPR32AsmReg, 1 /* 0 */ },
7358  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 7424 /* sbe */, MCK_Mem, 2 /* 1 */ },
7359  { Feature_InMicroMips, 7424 /* sbe */, MCK_GPR32AsmReg, 1 /* 0 */ },
7360  { Feature_InMicroMips, 7424 /* sbe */, MCK_Mem, 2 /* 1 */ },
7361  { Feature_HasStdEnc|Feature_HasMips32r6, 7428 /* sc */, MCK_GPR32AsmReg, 1 /* 0 */ },
7362  { Feature_HasStdEnc|Feature_HasMips32r6, 7428 /* sc */, MCK_MemOffsetSimm9, 2 /* 1 */ },
7363  { Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 7428 /* sc */, MCK_GPR32AsmReg, 1 /* 0 */ },
7364  { Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 7428 /* sc */, MCK_Mem, 2 /* 1 */ },
7365  { Feature_InMicroMips, 7428 /* sc */, MCK_GPR32AsmReg, 1 /* 0 */ },
7366  { Feature_InMicroMips, 7428 /* sc */, MCK_Mem, 2 /* 1 */ },
7367  { Feature_HasStdEnc|Feature_HasMips32r6, 7431 /* scd */, MCK_GPR64AsmReg, 1 /* 0 */ },
7368  { Feature_HasStdEnc|Feature_HasMips32r6, 7431 /* scd */, MCK_MemOffsetSimm9, 2 /* 1 */ },
7369  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 7431 /* scd */, MCK_GPR64AsmReg, 1 /* 0 */ },
7370  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 7431 /* scd */, MCK_Mem, 2 /* 1 */ },
7371  { Feature_HasStdEnc|Feature_HasEVA|Feature_NotInMicroMips, 7435 /* sce */, MCK_GPR32AsmReg, 1 /* 0 */ },
7372  { Feature_HasStdEnc|Feature_HasEVA|Feature_NotInMicroMips, 7435 /* sce */, MCK_MemOffsetSimm9, 2 /* 1 */ },
7373  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 7435 /* sce */, MCK_GPR32AsmReg, 1 /* 0 */ },
7374  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 7435 /* sce */, MCK_Mem, 2 /* 1 */ },
7375  { Feature_InMicroMips, 7435 /* sce */, MCK_GPR32AsmReg, 1 /* 0 */ },
7376  { Feature_InMicroMips, 7435 /* sce */, MCK_Mem, 2 /* 1 */ },
7377  { Feature_HasStdEnc|Feature_HasMips3, 7439 /* sd */, MCK_GPR64AsmReg, 1 /* 0 */ },
7378  { Feature_HasStdEnc|Feature_HasMips3, 7439 /* sd */, MCK_Mem, 2 /* 1 */ },
7379  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 7456 /* sdc1 */, MCK_AFGR64AsmReg, 1 /* 0 */ },
7380  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 7456 /* sdc1 */, MCK_Mem, 2 /* 1 */ },
7381  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 7456 /* sdc1 */, MCK_FGR64AsmReg, 1 /* 0 */ },
7382  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 7456 /* sdc1 */, MCK_Mem, 2 /* 1 */ },
7383  { Feature_HasStdEnc|Feature_HasMips32r6, 7461 /* sdc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
7384  { Feature_HasStdEnc|Feature_HasMips32r6, 7461 /* sdc2 */, MCK_MemOffsetSimm11, 2 /* 1 */ },
7385  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 7461 /* sdc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
7386  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 7461 /* sdc2 */, MCK_Mem, 2 /* 1 */ },
7387  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 7466 /* sdc3 */, MCK_COP3AsmReg, 1 /* 0 */ },
7388  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 7466 /* sdc3 */, MCK_Mem, 2 /* 1 */ },
7389  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 7471 /* sdl */, MCK_GPR64AsmReg, 1 /* 0 */ },
7390  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 7471 /* sdl */, MCK_Mem, 2 /* 1 */ },
7391  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 7475 /* sdr */, MCK_GPR64AsmReg, 1 /* 0 */ },
7392  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 7475 /* sdr */, MCK_Mem, 2 /* 1 */ },
7393  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7479 /* sdxc1 */, MCK_AFGR64AsmReg, 1 /* 0 */ },
7394  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7479 /* sdxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
7395  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 7479 /* sdxc1 */, MCK_FGR64AsmReg, 1 /* 0 */ },
7396  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 7479 /* sdxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
7397  { Feature_HasStdEnc|Feature_HasMips32r2, 7485 /* seb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7398  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 7485 /* seb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7399  { Feature_InMicroMips, 7485 /* seb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7400  { Feature_HasStdEnc|Feature_HasMips32r2, 7489 /* seh */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7401  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 7489 /* seh */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7402  { Feature_InMicroMips, 7489 /* seh */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7403  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7493 /* sel.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
7404  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 7493 /* sel.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
7405  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7499 /* sel.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
7406  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 7499 /* sel.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
7407  { Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6, 7505 /* seleqz */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7408  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 7505 /* seleqz */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7409  { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips32r6, 7505 /* seleqz */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
7410  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7512 /* seleqz.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
7411  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 7512 /* seleqz.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
7412  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7521 /* seleqz.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
7413  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 7521 /* seleqz.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
7414  { Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6, 7530 /* selnez */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7415  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 7530 /* selnez */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7416  { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips32r6, 7530 /* selnez */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
7417  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7537 /* selnez.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
7418  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 7537 /* selnez.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
7419  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7546 /* selnez.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
7420  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 7546 /* selnez.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
7421  { Feature_HasCnMips, 7555 /* seq */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
7422  { Feature_HasCnMips, 7555 /* seq */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
7423  { Feature_HasCnMips, 7559 /* seqi */, MCK_GPR64AsmReg, 1 /* 0 */ },
7424  { Feature_HasCnMips, 7559 /* seqi */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
7425  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 7564 /* sh */, MCK_GPR32AsmReg, 1 /* 0 */ },
7426  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 7564 /* sh */, MCK_Mem, 2 /* 1 */ },
7427  { Feature_HasStdEnc, 7564 /* sh */, MCK_GPR32AsmReg, 1 /* 0 */ },
7428  { Feature_HasStdEnc, 7564 /* sh */, MCK_Mem, 2 /* 1 */ },
7429  { Feature_InMicroMips, 7564 /* sh */, MCK_GPR32AsmReg, 1 /* 0 */ },
7430  { Feature_InMicroMips, 7564 /* sh */, MCK_Mem, 2 /* 1 */ },
7431  { Feature_InMicroMips, 7567 /* sh16 */, MCK_GPRMM16AsmRegZero, 1 /* 0 */ },
7432  { Feature_InMicroMips, 7567 /* sh16 */, MCK_MicroMipsMem, 2 /* 1 */ },
7433  { Feature_HasMicroMips32r6, 7567 /* sh16 */, MCK_GPRMM16AsmRegZero, 1 /* 0 */ },
7434  { Feature_HasMicroMips32r6, 7567 /* sh16 */, MCK_MicroMipsMem, 2 /* 1 */ },
7435  { Feature_HasStdEnc|Feature_HasEVA, 7572 /* she */, MCK_GPR32AsmReg, 1 /* 0 */ },
7436  { Feature_HasStdEnc|Feature_HasEVA, 7572 /* she */, MCK_MemOffsetSimm9, 2 /* 1 */ },
7437  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 7572 /* she */, MCK_GPR32AsmReg, 1 /* 0 */ },
7438  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 7572 /* she */, MCK_Mem, 2 /* 1 */ },
7439  { Feature_InMicroMips, 7572 /* she */, MCK_GPR32AsmReg, 1 /* 0 */ },
7440  { Feature_InMicroMips, 7572 /* she */, MCK_Mem, 2 /* 1 */ },
7441  { Feature_HasStdEnc|Feature_HasMSA, 7576 /* shf.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7442  { Feature_HasStdEnc|Feature_HasMSA, 7582 /* shf.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7443  { Feature_HasStdEnc|Feature_HasMSA, 7588 /* shf.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7444  { Feature_HasDSP|Feature_InMicroMips, 7594 /* shilo */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
7445  { Feature_HasDSP, 7594 /* shilo */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
7446  { Feature_HasDSP|Feature_InMicroMips, 7600 /* shilov */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
7447  { Feature_HasDSP|Feature_InMicroMips, 7600 /* shilov */, MCK_GPR32AsmReg, 2 /* 1 */ },
7448  { Feature_HasDSP, 7600 /* shilov */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
7449  { Feature_HasDSP, 7600 /* shilov */, MCK_GPR32AsmReg, 2 /* 1 */ },
7450  { Feature_HasDSP|Feature_InMicroMips, 7607 /* shll.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7451  { Feature_HasDSP, 7607 /* shll.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7452  { Feature_HasDSP|Feature_InMicroMips, 7615 /* shll.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7453  { Feature_HasDSP, 7615 /* shll.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7454  { Feature_HasDSP|Feature_InMicroMips, 7623 /* shll_s.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7455  { Feature_HasDSP, 7623 /* shll_s.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7456  { Feature_HasDSP|Feature_InMicroMips, 7633 /* shll_s.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7457  { Feature_HasDSP, 7633 /* shll_s.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7458  { Feature_HasDSP|Feature_InMicroMips, 7642 /* shllv.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7459  { Feature_HasDSP, 7642 /* shllv.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7460  { Feature_HasDSP|Feature_InMicroMips, 7651 /* shllv.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7461  { Feature_HasDSP, 7651 /* shllv.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7462  { Feature_HasDSP|Feature_InMicroMips, 7660 /* shllv_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7463  { Feature_HasDSP, 7660 /* shllv_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7464  { Feature_HasDSP|Feature_InMicroMips, 7671 /* shllv_s.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7465  { Feature_HasDSP, 7671 /* shllv_s.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7466  { Feature_HasDSP|Feature_InMicroMips, 7681 /* shra.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7467  { Feature_HasDSP, 7681 /* shra.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7468  { Feature_HasDSPR2|Feature_InMicroMips, 7689 /* shra.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7469  { Feature_HasDSPR2, 7689 /* shra.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7470  { Feature_HasDSP|Feature_InMicroMips, 7697 /* shra_r.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7471  { Feature_HasDSP, 7697 /* shra_r.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7472  { Feature_HasDSPR2|Feature_InMicroMips, 7707 /* shra_r.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7473  { Feature_HasDSPR2, 7707 /* shra_r.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7474  { Feature_HasDSP|Feature_InMicroMips, 7717 /* shra_r.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7475  { Feature_HasDSP, 7717 /* shra_r.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7476  { Feature_HasDSP|Feature_InMicroMips, 7726 /* shrav.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7477  { Feature_HasDSP, 7726 /* shrav.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7478  { Feature_HasDSPR2|Feature_InMicroMips, 7735 /* shrav.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7479  { Feature_HasDSPR2, 7735 /* shrav.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7480  { Feature_HasDSP|Feature_InMicroMips, 7744 /* shrav_r.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7481  { Feature_HasDSP, 7744 /* shrav_r.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7482  { Feature_HasDSPR2|Feature_InMicroMips, 7755 /* shrav_r.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7483  { Feature_HasDSPR2, 7755 /* shrav_r.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7484  { Feature_HasDSP|Feature_InMicroMips, 7766 /* shrav_r.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7485  { Feature_HasDSP, 7766 /* shrav_r.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7486  { Feature_HasDSPR2|Feature_InMicroMips, 7776 /* shrl.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7487  { Feature_HasDSPR2, 7776 /* shrl.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7488  { Feature_HasDSP|Feature_InMicroMips, 7784 /* shrl.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7489  { Feature_HasDSP, 7784 /* shrl.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7490  { Feature_HasDSPR2|Feature_InMicroMips, 7792 /* shrlv.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7491  { Feature_HasDSPR2, 7792 /* shrlv.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7492  { Feature_HasDSP|Feature_InMicroMips, 7801 /* shrlv.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7493  { Feature_HasDSP, 7801 /* shrlv.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7494  { Feature_HasStdEnc|Feature_HasMSA, 7810 /* sld.b */, MCK_GPR32AsmReg, 8 /* 3 */ },
7495  { Feature_HasStdEnc|Feature_HasMSA, 7810 /* sld.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7496  { Feature_HasStdEnc|Feature_HasMSA, 7816 /* sld.d */, MCK_GPR32AsmReg, 8 /* 3 */ },
7497  { Feature_HasStdEnc|Feature_HasMSA, 7816 /* sld.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7498  { Feature_HasStdEnc|Feature_HasMSA, 7822 /* sld.h */, MCK_GPR32AsmReg, 8 /* 3 */ },
7499  { Feature_HasStdEnc|Feature_HasMSA, 7822 /* sld.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7500  { Feature_HasStdEnc|Feature_HasMSA, 7828 /* sld.w */, MCK_GPR32AsmReg, 8 /* 3 */ },
7501  { Feature_HasStdEnc|Feature_HasMSA, 7828 /* sld.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7502  { Feature_HasStdEnc|Feature_HasMSA, 7834 /* sldi.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7503  { Feature_HasStdEnc|Feature_HasMSA, 7841 /* sldi.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7504  { Feature_HasStdEnc|Feature_HasMSA, 7848 /* sldi.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7505  { Feature_HasStdEnc|Feature_HasMSA, 7855 /* sldi.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7506  { Feature_HasStdEnc|Feature_NotInMicroMips, 7862 /* sll */, MCK_GPR32AsmReg, 1 /* 0 */ },
7507  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 7862 /* sll */, MCK_GPR32AsmReg, 1 /* 0 */ },
7508  { Feature_InMicroMips, 7862 /* sll */, MCK_GPR32AsmReg, 1 /* 0 */ },
7509  { 0, 7862 /* sll */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7510  { Feature_HasStdEnc|Feature_NotInMicroMips, 7862 /* sll */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7511  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 7862 /* sll */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7512  { Feature_InMicroMips, 7862 /* sll */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7513  { Feature_HasStdEnc|Feature_HasMSA, 7866 /* sll.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7514  { Feature_HasStdEnc|Feature_HasMSA, 7872 /* sll.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7515  { Feature_HasStdEnc|Feature_HasMSA, 7878 /* sll.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7516  { Feature_HasStdEnc|Feature_HasMSA, 7884 /* sll.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7517  { Feature_InMicroMips|Feature_NotMips32r6|Feature_NotMips64r6, 7890 /* sll16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
7518  { Feature_HasMicroMips32r6, 7890 /* sll16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
7519  { Feature_HasStdEnc|Feature_HasMSA, 7896 /* slli.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7520  { Feature_HasStdEnc|Feature_HasMSA, 7903 /* slli.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7521  { Feature_HasStdEnc|Feature_HasMSA, 7910 /* slli.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7522  { Feature_HasStdEnc|Feature_HasMSA, 7917 /* slli.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7523  { Feature_HasStdEnc, 7924 /* sllv */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7524  { Feature_InMicroMips, 7924 /* sllv */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7525  { Feature_HasStdEnc, 7929 /* slt */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7526  { Feature_InMicroMips, 7929 /* slt */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7527  { 0, 7929 /* slt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7528  { Feature_HasStdEnc, 7933 /* slti */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7529  { Feature_InMicroMips, 7933 /* slti */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7530  { Feature_HasStdEnc, 7938 /* sltiu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7531  { Feature_InMicroMips, 7938 /* sltiu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7532  { Feature_HasStdEnc, 7944 /* sltu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7533  { Feature_InMicroMips, 7944 /* sltu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7534  { 0, 7944 /* sltu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7535  { Feature_HasCnMips, 7949 /* sne */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
7536  { Feature_HasCnMips, 7949 /* sne */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
7537  { Feature_HasCnMips, 7953 /* snei */, MCK_GPR64AsmReg, 1 /* 0 */ },
7538  { Feature_HasCnMips, 7953 /* snei */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
7539  { Feature_HasStdEnc|Feature_HasMSA, 7958 /* splat.b */, MCK_GPR32AsmReg, 8 /* 3 */ },
7540  { Feature_HasStdEnc|Feature_HasMSA, 7958 /* splat.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7541  { Feature_HasStdEnc|Feature_HasMSA, 7966 /* splat.d */, MCK_GPR32AsmReg, 8 /* 3 */ },
7542  { Feature_HasStdEnc|Feature_HasMSA, 7966 /* splat.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7543  { Feature_HasStdEnc|Feature_HasMSA, 7974 /* splat.h */, MCK_GPR32AsmReg, 8 /* 3 */ },
7544  { Feature_HasStdEnc|Feature_HasMSA, 7974 /* splat.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7545  { Feature_HasStdEnc|Feature_HasMSA, 7982 /* splat.w */, MCK_GPR32AsmReg, 8 /* 3 */ },
7546  { Feature_HasStdEnc|Feature_HasMSA, 7982 /* splat.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7547  { Feature_HasStdEnc|Feature_HasMSA, 7990 /* splati.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7548  { Feature_HasStdEnc|Feature_HasMSA, 7999 /* splati.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7549  { Feature_HasStdEnc|Feature_HasMSA, 8008 /* splati.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7550  { Feature_HasStdEnc|Feature_HasMSA, 8017 /* splati.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7551  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 8026 /* sqrt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
7552  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 8026 /* sqrt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
7553  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 8026 /* sqrt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
7554  { Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat, 8033 /* sqrt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
7555  { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_InMicroMips, 8033 /* sqrt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
7556  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 8033 /* sqrt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
7557  { Feature_HasStdEnc, 8040 /* sra */, MCK_GPR32AsmReg, 1 /* 0 */ },
7558  { Feature_InMicroMips, 8040 /* sra */, MCK_GPR32AsmReg, 1 /* 0 */ },
7559  { 0, 8040 /* sra */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7560  { Feature_HasStdEnc, 8040 /* sra */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7561  { Feature_InMicroMips, 8040 /* sra */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7562  { Feature_HasStdEnc|Feature_HasMSA, 8044 /* sra.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7563  { Feature_HasStdEnc|Feature_HasMSA, 8050 /* sra.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7564  { Feature_HasStdEnc|Feature_HasMSA, 8056 /* sra.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7565  { Feature_HasStdEnc|Feature_HasMSA, 8062 /* sra.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7566  { Feature_HasStdEnc|Feature_HasMSA, 8068 /* srai.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7567  { Feature_HasStdEnc|Feature_HasMSA, 8075 /* srai.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7568  { Feature_HasStdEnc|Feature_HasMSA, 8082 /* srai.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7569  { Feature_HasStdEnc|Feature_HasMSA, 8089 /* srai.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7570  { Feature_HasStdEnc|Feature_HasMSA, 8096 /* srar.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7571  { Feature_HasStdEnc|Feature_HasMSA, 8103 /* srar.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7572  { Feature_HasStdEnc|Feature_HasMSA, 8110 /* srar.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7573  { Feature_HasStdEnc|Feature_HasMSA, 8117 /* srar.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7574  { Feature_HasStdEnc|Feature_HasMSA, 8124 /* srari.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7575  { Feature_HasStdEnc|Feature_HasMSA, 8132 /* srari.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7576  { Feature_HasStdEnc|Feature_HasMSA, 8140 /* srari.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7577  { Feature_HasStdEnc|Feature_HasMSA, 8148 /* srari.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7578  { Feature_HasStdEnc, 8156 /* srav */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7579  { Feature_InMicroMips, 8156 /* srav */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7580  { Feature_HasStdEnc|Feature_NotInMicroMips, 8161 /* srl */, MCK_GPR32AsmReg, 1 /* 0 */ },
7581  { Feature_InMicroMips, 8161 /* srl */, MCK_GPR32AsmReg, 1 /* 0 */ },
7582  { 0, 8161 /* srl */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7583  { Feature_HasStdEnc|Feature_NotInMicroMips, 8161 /* srl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7584  { Feature_InMicroMips, 8161 /* srl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7585  { Feature_HasStdEnc|Feature_HasMSA, 8165 /* srl.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7586  { Feature_HasStdEnc|Feature_HasMSA, 8171 /* srl.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7587  { Feature_HasStdEnc|Feature_HasMSA, 8177 /* srl.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7588  { Feature_HasStdEnc|Feature_HasMSA, 8183 /* srl.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7589  { Feature_InMicroMips|Feature_NotMips32r6|Feature_NotMips64r6, 8189 /* srl16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
7590  { Feature_HasMicroMips32r6, 8189 /* srl16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
7591  { Feature_HasStdEnc|Feature_HasMSA, 8195 /* srli.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7592  { Feature_HasStdEnc|Feature_HasMSA, 8202 /* srli.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7593  { Feature_HasStdEnc|Feature_HasMSA, 8209 /* srli.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7594  { Feature_HasStdEnc|Feature_HasMSA, 8216 /* srli.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7595  { Feature_HasStdEnc|Feature_HasMSA, 8223 /* srlr.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7596  { Feature_HasStdEnc|Feature_HasMSA, 8230 /* srlr.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7597  { Feature_HasStdEnc|Feature_HasMSA, 8237 /* srlr.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7598  { Feature_HasStdEnc|Feature_HasMSA, 8244 /* srlr.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7599  { Feature_HasStdEnc|Feature_HasMSA, 8251 /* srlri.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7600  { Feature_HasStdEnc|Feature_HasMSA, 8259 /* srlri.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7601  { Feature_HasStdEnc|Feature_HasMSA, 8267 /* srlri.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7602  { Feature_HasStdEnc|Feature_HasMSA, 8275 /* srlri.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7603  { Feature_HasStdEnc, 8283 /* srlv */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7604  { Feature_InMicroMips, 8283 /* srlv */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7605  { Feature_HasStdEnc|Feature_HasMSA, 8294 /* st.b */, MCK_MSA128AsmReg, 1 /* 0 */ },
7606  { Feature_HasStdEnc|Feature_HasMSA, 8294 /* st.b */, MCK_Mem, 2 /* 1 */ },
7607  { Feature_HasStdEnc|Feature_HasMSA, 8299 /* st.d */, MCK_MSA128AsmReg, 1 /* 0 */ },
7608  { Feature_HasStdEnc|Feature_HasMSA, 8299 /* st.d */, MCK_Mem, 2 /* 1 */ },
7609  { Feature_HasStdEnc|Feature_HasMSA, 8304 /* st.h */, MCK_MSA128AsmReg, 1 /* 0 */ },
7610  { Feature_HasStdEnc|Feature_HasMSA, 8304 /* st.h */, MCK_Mem, 2 /* 1 */ },
7611  { Feature_HasStdEnc|Feature_HasMSA, 8309 /* st.w */, MCK_MSA128AsmReg, 1 /* 0 */ },
7612  { Feature_HasStdEnc|Feature_HasMSA, 8309 /* st.w */, MCK_Mem, 2 /* 1 */ },
7613  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 8314 /* sub */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7614  { Feature_HasStdEnc, 8314 /* sub */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7615  { Feature_InMicroMips, 8314 /* sub */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7616  { Feature_NotMips32r6|Feature_NotMips64r6, 8314 /* sub */, MCK_GPR32AsmReg, 1 /* 0 */ },
7617  { Feature_NotMips32r6|Feature_NotMips64r6, 8314 /* sub */, MCK_InvNum, 2 /* 1 */ },
7618  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 8314 /* sub */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7619  { Feature_HasStdEnc, 8314 /* sub */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7620  { Feature_InMicroMips, 8314 /* sub */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7621  { Feature_NotMips32r6|Feature_NotMips64r6, 8314 /* sub */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7622  { Feature_NotMips32r6|Feature_NotMips64r6, 8314 /* sub */, MCK_InvNum, 4 /* 2 */ },
7623  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat, 8318 /* sub.d */, MCK_AFGR64AsmReg, 7 /* 0, 1, 2 */ },
7624  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 8318 /* sub.d */, MCK_AFGR64AsmReg, 7 /* 0, 1, 2 */ },
7625  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat, 8318 /* sub.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
7626  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 8324 /* sub.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
7627  { Feature_HasStdEnc|Feature_IsNotSoftFloat, 8324 /* sub.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
7628  { Feature_HasDSP|Feature_InMicroMips, 8330 /* subq.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7629  { Feature_HasDSP, 8330 /* subq.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7630  { Feature_HasDSP|Feature_InMicroMips, 8338 /* subq_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7631  { Feature_HasDSP, 8338 /* subq_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7632  { Feature_HasDSP|Feature_InMicroMips, 8348 /* subq_s.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7633  { Feature_HasDSP, 8348 /* subq_s.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7634  { Feature_HasDSPR2|Feature_InMicroMips, 8357 /* subqh.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7635  { Feature_HasDSPR2, 8357 /* subqh.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7636  { Feature_HasDSPR2|Feature_InMicroMips, 8366 /* subqh.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7637  { Feature_HasDSPR2, 8366 /* subqh.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7638  { Feature_HasDSPR2|Feature_InMicroMips, 8374 /* subqh_r.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7639  { Feature_HasDSPR2, 8374 /* subqh_r.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7640  { Feature_HasDSPR2|Feature_InMicroMips, 8385 /* subqh_r.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7641  { Feature_HasDSPR2, 8385 /* subqh_r.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7642  { Feature_HasStdEnc|Feature_HasMSA, 8395 /* subs_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7643  { Feature_HasStdEnc|Feature_HasMSA, 8404 /* subs_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7644  { Feature_HasStdEnc|Feature_HasMSA, 8413 /* subs_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7645  { Feature_HasStdEnc|Feature_HasMSA, 8422 /* subs_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7646  { Feature_HasStdEnc|Feature_HasMSA, 8431 /* subs_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7647  { Feature_HasStdEnc|Feature_HasMSA, 8440 /* subs_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7648  { Feature_HasStdEnc|Feature_HasMSA, 8449 /* subs_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7649  { Feature_HasStdEnc|Feature_HasMSA, 8458 /* subs_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7650  { Feature_HasStdEnc|Feature_HasMSA, 8467 /* subsus_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7651  { Feature_HasStdEnc|Feature_HasMSA, 8478 /* subsus_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7652  { Feature_HasStdEnc|Feature_HasMSA, 8489 /* subsus_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7653  { Feature_HasStdEnc|Feature_HasMSA, 8500 /* subsus_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7654  { Feature_HasStdEnc|Feature_HasMSA, 8511 /* subsuu_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7655  { Feature_HasStdEnc|Feature_HasMSA, 8522 /* subsuu_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7656  { Feature_HasStdEnc|Feature_HasMSA, 8533 /* subsuu_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7657  { Feature_HasStdEnc|Feature_HasMSA, 8544 /* subsuu_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7658  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 8555 /* subu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7659  { Feature_HasStdEnc|Feature_NotInMicroMips, 8555 /* subu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7660  { Feature_InMicroMips, 8555 /* subu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7661  { 0, 8555 /* subu */, MCK_GPR32AsmReg, 1 /* 0 */ },
7662  { 0, 8555 /* subu */, MCK_InvNum, 2 /* 1 */ },
7663  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 8555 /* subu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7664  { Feature_HasStdEnc|Feature_NotInMicroMips, 8555 /* subu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7665  { Feature_InMicroMips, 8555 /* subu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7666  { 0, 8555 /* subu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7667  { 0, 8555 /* subu */, MCK_InvNum, 4 /* 2 */ },
7668  { Feature_HasDSPR2|Feature_InMicroMips, 8560 /* subu.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7669  { Feature_HasDSPR2, 8560 /* subu.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7670  { Feature_HasDSP|Feature_InMicroMips, 8568 /* subu.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7671  { Feature_HasDSP, 8568 /* subu.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7672  { Feature_InMicroMips|Feature_NotMips32r6|Feature_NotMips64r6, 8576 /* subu16 */, MCK_GPRMM16AsmReg, 7 /* 0, 1, 2 */ },
7673  { Feature_HasMicroMips32r6, 8576 /* subu16 */, MCK_GPRMM16AsmReg, 7 /* 0, 1, 2 */ },
7674  { Feature_HasDSPR2|Feature_InMicroMips, 8583 /* subu_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7675  { Feature_HasDSPR2, 8583 /* subu_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7676  { Feature_HasDSP|Feature_InMicroMips, 8593 /* subu_s.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7677  { Feature_HasDSP, 8593 /* subu_s.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7678  { Feature_HasDSPR2|Feature_InMicroMips, 8603 /* subuh.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7679  { Feature_HasDSPR2, 8603 /* subuh.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7680  { Feature_HasDSPR2|Feature_InMicroMips, 8612 /* subuh_r.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7681  { Feature_HasDSPR2, 8612 /* subuh_r.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7682  { Feature_HasStdEnc|Feature_HasMSA, 8623 /* subv.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7683  { Feature_HasStdEnc|Feature_HasMSA, 8630 /* subv.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7684  { Feature_HasStdEnc|Feature_HasMSA, 8637 /* subv.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7685  { Feature_HasStdEnc|Feature_HasMSA, 8644 /* subv.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7686  { Feature_HasStdEnc|Feature_HasMSA, 8651 /* subvi.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7687  { Feature_HasStdEnc|Feature_HasMSA, 8659 /* subvi.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7688  { Feature_HasStdEnc|Feature_HasMSA, 8667 /* subvi.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7689  { Feature_HasStdEnc|Feature_HasMSA, 8675 /* subvi.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7690  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 8683 /* suxc1 */, MCK_AFGR64AsmReg, 1 /* 0 */ },
7691  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 8683 /* suxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
7692  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 8683 /* suxc1 */, MCK_FGR64AsmReg, 1 /* 0 */ },
7693  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 8683 /* suxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
7694  { Feature_InMicroMips, 8689 /* sw */, MCK_GPR32AsmReg, 1 /* 0 */ },
7695  { Feature_InMicroMips, 8689 /* sw */, MCK_MicroMipsMemSP, 2 /* 1 */ },
7696  { Feature_HasMicroMips32r6, 8689 /* sw */, MCK_GPR32AsmReg, 1 /* 0 */ },
7697  { Feature_HasMicroMips32r6, 8689 /* sw */, MCK_MicroMipsMemSP, 2 /* 1 */ },
7698  { Feature_HasStdEnc|Feature_NotInMicroMips, 8689 /* sw */, MCK_GPR32AsmReg, 1 /* 0 */ },
7699  { Feature_HasStdEnc|Feature_NotInMicroMips, 8689 /* sw */, MCK_Mem, 2 /* 1 */ },
7700  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 8689 /* sw */, MCK_GPR32AsmReg, 1 /* 0 */ },
7701  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 8689 /* sw */, MCK_Mem, 2 /* 1 */ },
7702  { Feature_InMicroMips, 8689 /* sw */, MCK_GPR32AsmReg, 1 /* 0 */ },
7703  { Feature_InMicroMips, 8689 /* sw */, MCK_Mem, 2 /* 1 */ },
7704  { Feature_InMicroMips, 8692 /* sw16 */, MCK_GPRMM16AsmRegZero, 1 /* 0 */ },
7705  { Feature_InMicroMips, 8692 /* sw16 */, MCK_MicroMipsMem, 2 /* 1 */ },
7706  { Feature_HasMicroMips32r6, 8692 /* sw16 */, MCK_GPRMM16AsmRegZero, 1 /* 0 */ },
7707  { Feature_HasMicroMips32r6, 8692 /* sw16 */, MCK_MicroMipsMem, 2 /* 1 */ },
7708  { Feature_HasStdEnc|Feature_IsNotSoftFloat, 8697 /* swc1 */, MCK_FGR32AsmReg, 1 /* 0 */ },
7709  { Feature_HasStdEnc|Feature_IsNotSoftFloat, 8697 /* swc1 */, MCK_Mem, 2 /* 1 */ },
7710  { Feature_HasStdEnc|Feature_HasMips32r6, 8702 /* swc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
7711  { Feature_HasStdEnc|Feature_HasMips32r6, 8702 /* swc2 */, MCK_MemOffsetSimm11, 2 /* 1 */ },
7712  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 8702 /* swc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
7713  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 8702 /* swc2 */, MCK_Mem, 2 /* 1 */ },
7714  { Feature_HasStdEnc|Feature_NotInMicroMips, 8707 /* swc3 */, MCK_COP3AsmReg, 1 /* 0 */ },
7715  { Feature_HasStdEnc|Feature_NotInMicroMips, 8707 /* swc3 */, MCK_Mem, 2 /* 1 */ },
7716  { Feature_HasStdEnc|Feature_HasEVA|Feature_NotInMicroMips, 8712 /* swe */, MCK_GPR32AsmReg, 1 /* 0 */ },
7717  { Feature_HasStdEnc|Feature_HasEVA|Feature_NotInMicroMips, 8712 /* swe */, MCK_MemOffsetSimm9, 2 /* 1 */ },
7718  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 8712 /* swe */, MCK_GPR32AsmReg, 1 /* 0 */ },
7719  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 8712 /* swe */, MCK_MemOffsetSimm9, 2 /* 1 */ },
7720  { Feature_InMicroMips, 8712 /* swe */, MCK_GPR32AsmReg, 1 /* 0 */ },
7721  { Feature_InMicroMips, 8712 /* swe */, MCK_MemOffsetSimm9GPR, 2 /* 1 */ },
7722  { Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 8716 /* swl */, MCK_GPR32AsmReg, 1 /* 0 */ },
7723  { Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 8716 /* swl */, MCK_Mem, 2 /* 1 */ },
7724  { Feature_InMicroMips, 8716 /* swl */, MCK_GPR32AsmReg, 1 /* 0 */ },
7725  { Feature_InMicroMips, 8716 /* swl */, MCK_Mem, 2 /* 1 */ },
7726  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, 8720 /* swle */, MCK_GPR32AsmReg, 1 /* 0 */ },
7727  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, 8720 /* swle */, MCK_MemOffsetSimm9, 2 /* 1 */ },
7728  { Feature_InMicroMips, 8720 /* swle */, MCK_GPR32AsmReg, 1 /* 0 */ },
7729  { Feature_InMicroMips, 8720 /* swle */, MCK_Mem, 2 /* 1 */ },
7730  { Feature_InMicroMips, 8725 /* swm */, MCK_Mem, 2 /* 1 */ },
7731  { Feature_InMicroMips, 8725 /* swm */, MCK_RegList, 1 /* 0 */ },
7732  { Feature_InMicroMips|Feature_NotMips32r6, 8729 /* swm16 */, MCK_MemOffsetUimm4, 2 /* 1 */ },
7733  { Feature_InMicroMips|Feature_NotMips32r6, 8729 /* swm16 */, MCK_RegList16, 1 /* 0 */ },
7734  { Feature_HasMicroMips32r6, 8729 /* swm16 */, MCK_MemOffsetUimm4, 2 /* 1 */ },
7735  { Feature_HasMicroMips32r6, 8729 /* swm16 */, MCK_RegList16, 1 /* 0 */ },
7736  { Feature_InMicroMips, 8735 /* swm32 */, MCK_Mem, 2 /* 1 */ },
7737  { Feature_InMicroMips, 8735 /* swm32 */, MCK_RegList, 1 /* 0 */ },
7738  { Feature_InMicroMips, 8741 /* swp */, MCK_Mem, 2 /* 1 */ },
7739  { Feature_InMicroMips, 8741 /* swp */, MCK_RegPair, 1 /* 0 */ },
7740  { Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 8745 /* swr */, MCK_GPR32AsmReg, 1 /* 0 */ },
7741  { Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 8745 /* swr */, MCK_Mem, 2 /* 1 */ },
7742  { Feature_InMicroMips, 8745 /* swr */, MCK_GPR32AsmReg, 1 /* 0 */ },
7743  { Feature_InMicroMips, 8745 /* swr */, MCK_Mem, 2 /* 1 */ },
7744  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, 8749 /* swre */, MCK_GPR32AsmReg, 1 /* 0 */ },
7745  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, 8749 /* swre */, MCK_MemOffsetSimm9, 2 /* 1 */ },
7746  { Feature_InMicroMips, 8749 /* swre */, MCK_GPR32AsmReg, 1 /* 0 */ },
7747  { Feature_InMicroMips, 8749 /* swre */, MCK_Mem, 2 /* 1 */ },
7748  { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 8754 /* swxc1 */, MCK_FGR32AsmReg, 1 /* 0 */ },
7749  { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 8754 /* swxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
7750  { Feature_HasStdEnc|Feature_HasMips32r2, 8765 /* synci */, MCK_MemOffsetSimm16, 1 /* 0 */ },
7751  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 8765 /* synci */, MCK_MemOffsetSimm16, 1 /* 0 */ },
7752  { Feature_HasMips2|Feature_NotInMicroMips, 8809 /* teq */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7753  { Feature_InMicroMips, 8809 /* teq */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7754  { Feature_InMicroMips, 8809 /* teq */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7755  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 8809 /* teq */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7756  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 8813 /* teqi */, MCK_GPR32AsmReg, 1 /* 0 */ },
7757  { Feature_InMicroMips, 8813 /* teqi */, MCK_GPR32AsmReg, 1 /* 0 */ },
7758  { Feature_HasMips2|Feature_NotInMicroMips, 8818 /* tge */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7759  { Feature_InMicroMips, 8818 /* tge */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7760  { Feature_InMicroMips, 8818 /* tge */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7761  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 8818 /* tge */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7762  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 8822 /* tgei */, MCK_GPR32AsmReg, 1 /* 0 */ },
7763  { Feature_InMicroMips, 8822 /* tgei */, MCK_GPR32AsmReg, 1 /* 0 */ },
7764  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 8827 /* tgeiu */, MCK_GPR32AsmReg, 1 /* 0 */ },
7765  { Feature_InMicroMips, 8827 /* tgeiu */, MCK_GPR32AsmReg, 1 /* 0 */ },
7766  { Feature_HasMips2|Feature_NotInMicroMips, 8833 /* tgeu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7767  { Feature_InMicroMips, 8833 /* tgeu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7768  { Feature_InMicroMips, 8833 /* tgeu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7769  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 8833 /* tgeu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7770  { Feature_HasMips2|Feature_NotInMicroMips, 8875 /* tlt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7771  { Feature_InMicroMips, 8875 /* tlt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7772  { Feature_InMicroMips, 8875 /* tlt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7773  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 8875 /* tlt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7774  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 8879 /* tlti */, MCK_GPR32AsmReg, 1 /* 0 */ },
7775  { Feature_InMicroMips, 8879 /* tlti */, MCK_GPR32AsmReg, 1 /* 0 */ },
7776  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 8884 /* tltiu */, MCK_GPR32AsmReg, 1 /* 0 */ },
7777  { Feature_InMicroMips, 8884 /* tltiu */, MCK_GPR32AsmReg, 1 /* 0 */ },
7778  { Feature_HasMips2|Feature_NotInMicroMips, 8890 /* tltu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7779  { Feature_InMicroMips, 8890 /* tltu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7780  { Feature_InMicroMips, 8890 /* tltu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7781  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 8890 /* tltu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7782  { Feature_HasMips2|Feature_NotInMicroMips, 8895 /* tne */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7783  { Feature_InMicroMips, 8895 /* tne */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7784  { Feature_InMicroMips, 8895 /* tne */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7785  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 8895 /* tne */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7786  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 8899 /* tnei */, MCK_GPR32AsmReg, 1 /* 0 */ },
7787  { Feature_InMicroMips, 8899 /* tnei */, MCK_GPR32AsmReg, 1 /* 0 */ },
7788  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 8904 /* trunc.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
7789  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 8904 /* trunc.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
7790  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 8914 /* trunc.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
7791  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 8914 /* trunc.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
7792  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 8914 /* trunc.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
7793  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 8914 /* trunc.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
7794  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 8924 /* trunc.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
7795  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 8924 /* trunc.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
7796  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 8924 /* trunc.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
7797  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 8924 /* trunc.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
7798  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 8924 /* trunc.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
7799  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 8924 /* trunc.w.d */, MCK_FGR64AsmReg, 2 /* 1 */ },
7800  { Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat, 8934 /* trunc.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
7801  { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_InMicroMips, 8934 /* trunc.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
7802  { Feature_HasStdEnc|Feature_HasMicroMips32r6|Feature_IsNotSoftFloat, 8934 /* trunc.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
7803  { 0, 8944 /* ulh */, MCK_GPR32AsmReg, 1 /* 0 */ },
7804  { 0, 8944 /* ulh */, MCK_Mem, 2 /* 1 */ },
7805  { 0, 8948 /* ulhu */, MCK_GPR32AsmReg, 1 /* 0 */ },
7806  { 0, 8948 /* ulhu */, MCK_Mem, 2 /* 1 */ },
7807  { 0, 8953 /* ulw */, MCK_GPR32AsmReg, 1 /* 0 */ },
7808  { 0, 8953 /* ulw */, MCK_Mem, 2 /* 1 */ },
7809  { Feature_HasCnMips, 8957 /* v3mulu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
7810  { Feature_HasCnMips, 8957 /* v3mulu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
7811  { Feature_HasCnMips, 8964 /* vmm0 */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
7812  { Feature_HasCnMips, 8964 /* vmm0 */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
7813  { Feature_HasCnMips, 8969 /* vmulu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
7814  { Feature_HasCnMips, 8969 /* vmulu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
7815  { Feature_HasStdEnc|Feature_HasMSA, 8975 /* vshf.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7816  { Feature_HasStdEnc|Feature_HasMSA, 8982 /* vshf.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7817  { Feature_HasStdEnc|Feature_HasMSA, 8989 /* vshf.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7818  { Feature_HasStdEnc|Feature_HasMSA, 8996 /* vshf.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7819  { Feature_HasDSP|Feature_NotInMicroMips, 9008 /* wrdsp */, MCK_GPR32AsmReg, 1 /* 0 */ },
7820  { Feature_HasDSP|Feature_InMicroMips, 9008 /* wrdsp */, MCK_GPR32AsmReg, 1 /* 0 */ },
7821  { Feature_HasDSP|Feature_InMicroMips, 9008 /* wrdsp */, MCK_GPR32AsmReg, 1 /* 0 */ },
7822  { Feature_HasDSP|Feature_NotInMicroMips, 9008 /* wrdsp */, MCK_GPR32AsmReg, 1 /* 0 */ },
7823  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 9014 /* wrpgpr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7824  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 9021 /* wsbh */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7825  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 9021 /* wsbh */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7826  { Feature_InMicroMips, 9021 /* wsbh */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7827  { Feature_HasStdEnc|Feature_NotInMicroMips, 9026 /* xor */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7828  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 9026 /* xor */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7829  { Feature_InMicroMips, 9026 /* xor */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7830  { 0, 9026 /* xor */, MCK_GPR32AsmReg, 1 /* 0 */ },
7831  { Feature_HasStdEnc|Feature_NotInMicroMips, 9026 /* xor */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7832  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 9026 /* xor */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7833  { Feature_InMicroMips, 9026 /* xor */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
7834  { 0, 9026 /* xor */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7835  { Feature_HasStdEnc|Feature_HasMSA, 9030 /* xor.v */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
7836  { Feature_InMicroMips|Feature_NotMips32r6|Feature_NotMips64r6, 9036 /* xor16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
7837  { Feature_HasMicroMips32r6, 9036 /* xor16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
7838  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 9042 /* xori */, MCK_GPR32AsmReg, 1 /* 0 */ },
7839  { Feature_HasStdEnc, 9042 /* xori */, MCK_GPR32AsmReg, 1 /* 0 */ },
7840  { Feature_InMicroMips, 9042 /* xori */, MCK_GPR32AsmReg, 1 /* 0 */ },
7841  { Feature_HasStdEnc|Feature_HasMicroMips32r6, 9042 /* xori */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7842  { Feature_HasStdEnc, 9042 /* xori */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7843  { Feature_InMicroMips, 9042 /* xori */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
7844  { Feature_HasStdEnc|Feature_HasMSA, 9047 /* xori.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
7845};
7846
7847MipsAsmParser::OperandMatchResultTy MipsAsmParser::
7848tryCustomParseOperand(OperandVector &Operands,
7849                      unsigned MCK) {
7850
7851  switch(MCK) {
7852  case MCK_ACC64DSPAsmReg:
7853    return parseAnyRegister(Operands);
7854  case MCK_AFGR64AsmReg:
7855    return parseAnyRegister(Operands);
7856  case MCK_CCRAsmReg:
7857    return parseAnyRegister(Operands);
7858  case MCK_COP0AsmReg:
7859    return parseAnyRegister(Operands);
7860  case MCK_COP2AsmReg:
7861    return parseAnyRegister(Operands);
7862  case MCK_COP3AsmReg:
7863    return parseAnyRegister(Operands);
7864  case MCK_FCCAsmReg:
7865    return parseAnyRegister(Operands);
7866  case MCK_FGR32AsmReg:
7867    return parseAnyRegister(Operands);
7868  case MCK_FGR64AsmReg:
7869    return parseAnyRegister(Operands);
7870  case MCK_FGRH32AsmReg:
7871    return parseAnyRegister(Operands);
7872  case MCK_GPR32AsmReg:
7873    return parseAnyRegister(Operands);
7874  case MCK_GPR64AsmReg:
7875    return parseAnyRegister(Operands);
7876  case MCK_GPRMM16AsmReg:
7877    return parseAnyRegister(Operands);
7878  case MCK_GPRMM16AsmRegMoveP:
7879    return parseAnyRegister(Operands);
7880  case MCK_GPRMM16AsmRegZero:
7881    return parseAnyRegister(Operands);
7882  case MCK_HI32DSPAsmReg:
7883    return parseAnyRegister(Operands);
7884  case MCK_HWRegsAsmReg:
7885    return parseAnyRegister(Operands);
7886  case MCK_LO32DSPAsmReg:
7887    return parseAnyRegister(Operands);
7888  case MCK_MSA128AsmReg:
7889    return parseAnyRegister(Operands);
7890  case MCK_MSACtrlAsmReg:
7891    return parseAnyRegister(Operands);
7892  case MCK_MicroMipsMem:
7893    return parseMemOperand(Operands);
7894  case MCK_MicroMipsMemSP:
7895    return parseMemOperand(Operands);
7896  case MCK_InvNum:
7897    return parseInvNum(Operands);
7898  case MCK_JumpTarget:
7899    return parseJumpTarget(Operands);
7900  case MCK_MemOffsetSimm11:
7901    return parseMemOperand(Operands);
7902  case MCK_MemOffsetSimm16:
7903    return parseMemOperand(Operands);
7904  case MCK_MemOffsetSimm9:
7905    return parseMemOperand(Operands);
7906  case MCK_MemOffsetSimm9GPR:
7907    return parseMemOperand(Operands);
7908  case MCK_MemOffsetUimm4:
7909    return parseMemOperand(Operands);
7910  case MCK_Mem:
7911    return parseMemOperand(Operands);
7912  case MCK_MovePRegPair:
7913    return parseMovePRegPair(Operands);
7914  case MCK_RegList16:
7915    return parseRegisterList(Operands);
7916  case MCK_RegList:
7917    return parseRegisterList(Operands);
7918  case MCK_RegPair:
7919    return parseRegisterPair(Operands);
7920  default:
7921    return MatchOperand_NoMatch;
7922  }
7923  return MatchOperand_NoMatch;
7924}
7925
7926MipsAsmParser::OperandMatchResultTy MipsAsmParser::
7927MatchOperandParserImpl(OperandVector &Operands,
7928                       StringRef Mnemonic) {
7929  // Get the current feature set.
7930  uint64_t AvailableFeatures = getAvailableFeatures();
7931
7932  // Get the next operand index.
7933  unsigned NextOpNum = Operands.size() - 1;
7934  // Search the table.
7935  auto MnemonicRange =
7936    std::equal_range(std::begin(OperandMatchTable), std::end(OperandMatchTable),
7937                     Mnemonic, LessOpcodeOperand());
7938
7939  if (MnemonicRange.first == MnemonicRange.second)
7940    return MatchOperand_NoMatch;
7941
7942  for (const OperandMatchEntry *it = MnemonicRange.first,
7943       *ie = MnemonicRange.second; it != ie; ++it) {
7944    // equal_range guarantees that instruction mnemonic matches.
7945    assert(Mnemonic == it->getMnemonic());
7946
7947    // check if the available features match
7948    if ((AvailableFeatures & it->RequiredFeatures) != it->RequiredFeatures) {
7949      continue;
7950    }
7951
7952    // check if the operand in question has a custom parser.
7953    if (!(it->OperandMask & (1 << NextOpNum)))
7954      continue;
7955
7956    // call custom parse method to handle the operand
7957    OperandMatchResultTy Result = tryCustomParseOperand(Operands, it->Class);
7958    if (Result != MatchOperand_NoMatch)
7959      return Result;
7960  }
7961
7962  // Okay, we had no match.
7963  return MatchOperand_NoMatch;
7964}
7965
7966#endif // GET_MATCHER_IMPLEMENTATION
7967
7968