1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Subtarget Enumeration Source Fragment *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9 10#ifdef GET_SUBTARGETINFO_ENUM 11#undef GET_SUBTARGETINFO_ENUM 12namespace llvm { 13namespace Mips { 14enum : uint64_t { 15 FeatureCnMips = 0, 16 FeatureDSP = 1, 17 FeatureDSPR2 = 2, 18 FeatureDSPR3 = 3, 19 FeatureEVA = 4, 20 FeatureFP64Bit = 5, 21 FeatureFPXX = 6, 22 FeatureGP64Bit = 7, 23 FeatureMSA = 8, 24 FeatureMicroMips = 9, 25 FeatureMips1 = 10, 26 FeatureMips2 = 11, 27 FeatureMips3 = 12, 28 FeatureMips3_32 = 13, 29 FeatureMips3_32r2 = 14, 30 FeatureMips4 = 15, 31 FeatureMips4_32 = 16, 32 FeatureMips4_32r2 = 17, 33 FeatureMips5 = 18, 34 FeatureMips5_32r2 = 19, 35 FeatureMips16 = 20, 36 FeatureMips32 = 21, 37 FeatureMips32r2 = 22, 38 FeatureMips32r3 = 23, 39 FeatureMips32r5 = 24, 40 FeatureMips32r6 = 25, 41 FeatureMips64 = 26, 42 FeatureMips64r2 = 27, 43 FeatureMips64r3 = 28, 44 FeatureMips64r5 = 29, 45 FeatureMips64r6 = 30, 46 FeatureNaN2008 = 31, 47 FeatureNoABICalls = 32, 48 FeatureNoOddSPReg = 33, 49 FeatureSingleFloat = 34, 50 FeatureSoftFloat = 35, 51 FeatureUseTCCInDIV = 36, 52 FeatureVFPU = 37, 53 ImplP5600 = 38 54}; 55} 56} // end llvm namespace 57#endif // GET_SUBTARGETINFO_ENUM 58 59 60#ifdef GET_SUBTARGETINFO_MC_DESC 61#undef GET_SUBTARGETINFO_MC_DESC 62namespace llvm { 63// Sorted (by key) array of values for CPU features. 64extern const llvm::SubtargetFeatureKV MipsFeatureKV[] = { 65 { "cnmips", "Octeon cnMIPS Support", { Mips::FeatureCnMips }, { Mips::FeatureMips64r2 } }, 66 { "dsp", "Mips DSP ASE", { Mips::FeatureDSP }, { } }, 67 { "dspr2", "Mips DSP-R2 ASE", { Mips::FeatureDSPR2 }, { Mips::FeatureDSP } }, 68 { "dspr3", "Mips DSP-R3 ASE", { Mips::FeatureDSPR3 }, { Mips::FeatureDSP, Mips::FeatureDSPR2 } }, 69 { "eva", "Mips EVA ASE", { Mips::FeatureEVA }, { } }, 70 { "fp64", "Support 64-bit FP registers", { Mips::FeatureFP64Bit }, { } }, 71 { "fpxx", "Support for FPXX", { Mips::FeatureFPXX }, { } }, 72 { "gp64", "General Purpose Registers are 64-bit wide", { Mips::FeatureGP64Bit }, { } }, 73 { "micromips", "microMips mode", { Mips::FeatureMicroMips }, { } }, 74 { "mips1", "Mips I ISA Support [highly experimental]", { Mips::FeatureMips1 }, { } }, 75 { "mips16", "Mips16 mode", { Mips::FeatureMips16 }, { } }, 76 { "mips2", "Mips II ISA Support [highly experimental]", { Mips::FeatureMips2 }, { Mips::FeatureMips1 } }, 77 { "mips3", "MIPS III ISA Support [highly experimental]", { Mips::FeatureMips3 }, { Mips::FeatureMips2, Mips::FeatureMips3_32, Mips::FeatureMips3_32r2, Mips::FeatureGP64Bit, Mips::FeatureFP64Bit } }, 78 { "mips32", "Mips32 ISA Support", { Mips::FeatureMips32 }, { Mips::FeatureMips2, Mips::FeatureMips3_32, Mips::FeatureMips4_32 } }, 79 { "mips32r2", "Mips32r2 ISA Support", { Mips::FeatureMips32r2 }, { Mips::FeatureMips3_32r2, Mips::FeatureMips4_32r2, Mips::FeatureMips5_32r2, Mips::FeatureMips32 } }, 80 { "mips32r3", "Mips32r3 ISA Support", { Mips::FeatureMips32r3 }, { Mips::FeatureMips32r2 } }, 81 { "mips32r5", "Mips32r5 ISA Support", { Mips::FeatureMips32r5 }, { Mips::FeatureMips32r3 } }, 82 { "mips32r6", "Mips32r6 ISA Support [experimental]", { Mips::FeatureMips32r6 }, { Mips::FeatureMips32r5, Mips::FeatureFP64Bit, Mips::FeatureNaN2008 } }, 83 { "mips3_32", "Subset of MIPS-III that is also in MIPS32 [highly experimental]", { Mips::FeatureMips3_32 }, { } }, 84 { "mips3_32r2", "Subset of MIPS-III that is also in MIPS32r2 [highly experimental]", { Mips::FeatureMips3_32r2 }, { } }, 85 { "mips4", "MIPS IV ISA Support", { Mips::FeatureMips4 }, { Mips::FeatureMips3, Mips::FeatureMips4_32, Mips::FeatureMips4_32r2 } }, 86 { "mips4_32", "Subset of MIPS-IV that is also in MIPS32 [highly experimental]", { Mips::FeatureMips4_32 }, { } }, 87 { "mips4_32r2", "Subset of MIPS-IV that is also in MIPS32r2 [highly experimental]", { Mips::FeatureMips4_32r2 }, { } }, 88 { "mips5", "MIPS V ISA Support [highly experimental]", { Mips::FeatureMips5 }, { Mips::FeatureMips4, Mips::FeatureMips5_32r2 } }, 89 { "mips5_32r2", "Subset of MIPS-V that is also in MIPS32r2 [highly experimental]", { Mips::FeatureMips5_32r2 }, { } }, 90 { "mips64", "Mips64 ISA Support", { Mips::FeatureMips64 }, { Mips::FeatureMips5, Mips::FeatureMips32 } }, 91 { "mips64r2", "Mips64r2 ISA Support", { Mips::FeatureMips64r2 }, { Mips::FeatureMips64, Mips::FeatureMips32r2 } }, 92 { "mips64r3", "Mips64r3 ISA Support", { Mips::FeatureMips64r3 }, { Mips::FeatureMips64r2, Mips::FeatureMips32r3 } }, 93 { "mips64r5", "Mips64r5 ISA Support", { Mips::FeatureMips64r5 }, { Mips::FeatureMips64r3, Mips::FeatureMips32r5 } }, 94 { "mips64r6", "Mips64r6 ISA Support [experimental]", { Mips::FeatureMips64r6 }, { Mips::FeatureMips32r6, Mips::FeatureMips64r5, Mips::FeatureNaN2008 } }, 95 { "msa", "Mips MSA ASE", { Mips::FeatureMSA }, { } }, 96 { "nan2008", "IEEE 754-2008 NaN encoding", { Mips::FeatureNaN2008 }, { } }, 97 { "noabicalls", "Disable SVR4-style position-independent code", { Mips::FeatureNoABICalls }, { } }, 98 { "nooddspreg", "Disable odd numbered single-precision registers", { Mips::FeatureNoOddSPReg }, { } }, 99 { "p5600", "The P5600 Processor", { Mips::ImplP5600 }, { Mips::FeatureMips32r5 } }, 100 { "single-float", "Only supports single precision float", { Mips::FeatureSingleFloat }, { } }, 101 { "soft-float", "Does not support floating point instructions", { Mips::FeatureSoftFloat }, { } }, 102 { "use-tcc-in-div", "Force the assembler to use trapping", { Mips::FeatureUseTCCInDIV }, { } }, 103 { "vfpu", "Enable vector FPU instructions", { Mips::FeatureVFPU }, { } } 104}; 105 106// Sorted (by key) array of values for CPU subtype. 107extern const llvm::SubtargetFeatureKV MipsSubTypeKV[] = { 108 { "mips1", "Select the mips1 processor", { Mips::FeatureMips1 }, { } }, 109 { "mips2", "Select the mips2 processor", { Mips::FeatureMips2 }, { } }, 110 { "mips3", "Select the mips3 processor", { Mips::FeatureMips3 }, { } }, 111 { "mips32", "Select the mips32 processor", { Mips::FeatureMips32 }, { } }, 112 { "mips32r2", "Select the mips32r2 processor", { Mips::FeatureMips32r2 }, { } }, 113 { "mips32r3", "Select the mips32r3 processor", { Mips::FeatureMips32r3 }, { } }, 114 { "mips32r5", "Select the mips32r5 processor", { Mips::FeatureMips32r5 }, { } }, 115 { "mips32r6", "Select the mips32r6 processor", { Mips::FeatureMips32r6 }, { } }, 116 { "mips4", "Select the mips4 processor", { Mips::FeatureMips4 }, { } }, 117 { "mips5", "Select the mips5 processor", { Mips::FeatureMips5 }, { } }, 118 { "mips64", "Select the mips64 processor", { Mips::FeatureMips64 }, { } }, 119 { "mips64r2", "Select the mips64r2 processor", { Mips::FeatureMips64r2 }, { } }, 120 { "mips64r3", "Select the mips64r3 processor", { Mips::FeatureMips64r3 }, { } }, 121 { "mips64r5", "Select the mips64r5 processor", { Mips::FeatureMips64r5 }, { } }, 122 { "mips64r6", "Select the mips64r6 processor", { Mips::FeatureMips64r6 }, { } }, 123 { "octeon", "Select the octeon processor", { Mips::FeatureMips64r2, Mips::FeatureCnMips }, { } }, 124 { "p5600", "Select the p5600 processor", { Mips::ImplP5600 }, { } } 125}; 126 127#ifdef DBGFIELD 128#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro" 129#endif 130#ifndef NDEBUG 131#define DBGFIELD(x) x, 132#else 133#define DBGFIELD(x) 134#endif 135 136#undef DBGFIELD 137static inline MCSubtargetInfo *createMipsMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef FS) { 138 return new MCSubtargetInfo(TT, CPU, FS, MipsFeatureKV, MipsSubTypeKV, NULL); 139} 140 141} // end llvm namespace 142#endif // GET_SUBTARGETINFO_MC_DESC 143 144 145#ifdef GET_SUBTARGETINFO_TARGET_DESC 146#undef GET_SUBTARGETINFO_TARGET_DESC 147#include "llvm/Support/Debug.h" 148#include "llvm/Support/raw_ostream.h" 149// ParseSubtargetFeatures - Parses features string setting specified 150// subtarget options. 151void llvm::MipsSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) { 152 DEBUG(dbgs() << "\nFeatures:" << FS); 153 DEBUG(dbgs() << "\nCPU:" << CPU << "\n\n"); 154 InitMCProcessorInfo(CPU, FS); 155 const FeatureBitset& Bits = getFeatureBits(); 156 if (Bits[Mips::FeatureCnMips]) HasCnMips = true; 157 if (Bits[Mips::FeatureDSP]) HasDSP = true; 158 if (Bits[Mips::FeatureDSPR2]) HasDSPR2 = true; 159 if (Bits[Mips::FeatureDSPR3]) HasDSPR3 = true; 160 if (Bits[Mips::FeatureEVA]) HasEVA = true; 161 if (Bits[Mips::FeatureFP64Bit]) IsFP64bit = true; 162 if (Bits[Mips::FeatureFPXX]) IsFPXX = true; 163 if (Bits[Mips::FeatureGP64Bit]) IsGP64bit = true; 164 if (Bits[Mips::FeatureMSA]) HasMSA = true; 165 if (Bits[Mips::FeatureMicroMips]) InMicroMipsMode = true; 166 if (Bits[Mips::FeatureMips1] && MipsArchVersion < Mips1) MipsArchVersion = Mips1; 167 if (Bits[Mips::FeatureMips2] && MipsArchVersion < Mips2) MipsArchVersion = Mips2; 168 if (Bits[Mips::FeatureMips3] && MipsArchVersion < Mips3) MipsArchVersion = Mips3; 169 if (Bits[Mips::FeatureMips3_32]) HasMips3_32 = true; 170 if (Bits[Mips::FeatureMips3_32r2]) HasMips3_32r2 = true; 171 if (Bits[Mips::FeatureMips4] && MipsArchVersion < Mips4) MipsArchVersion = Mips4; 172 if (Bits[Mips::FeatureMips4_32]) HasMips4_32 = true; 173 if (Bits[Mips::FeatureMips4_32r2]) HasMips4_32r2 = true; 174 if (Bits[Mips::FeatureMips5] && MipsArchVersion < Mips5) MipsArchVersion = Mips5; 175 if (Bits[Mips::FeatureMips5_32r2]) HasMips5_32r2 = true; 176 if (Bits[Mips::FeatureMips16]) InMips16Mode = true; 177 if (Bits[Mips::FeatureMips32] && MipsArchVersion < Mips32) MipsArchVersion = Mips32; 178 if (Bits[Mips::FeatureMips32r2] && MipsArchVersion < Mips32r2) MipsArchVersion = Mips32r2; 179 if (Bits[Mips::FeatureMips32r3] && MipsArchVersion < Mips32r3) MipsArchVersion = Mips32r3; 180 if (Bits[Mips::FeatureMips32r5] && MipsArchVersion < Mips32r5) MipsArchVersion = Mips32r5; 181 if (Bits[Mips::FeatureMips32r6] && MipsArchVersion < Mips32r6) MipsArchVersion = Mips32r6; 182 if (Bits[Mips::FeatureMips64] && MipsArchVersion < Mips64) MipsArchVersion = Mips64; 183 if (Bits[Mips::FeatureMips64r2] && MipsArchVersion < Mips64r2) MipsArchVersion = Mips64r2; 184 if (Bits[Mips::FeatureMips64r3] && MipsArchVersion < Mips64r3) MipsArchVersion = Mips64r3; 185 if (Bits[Mips::FeatureMips64r5] && MipsArchVersion < Mips64r5) MipsArchVersion = Mips64r5; 186 if (Bits[Mips::FeatureMips64r6] && MipsArchVersion < Mips64r6) MipsArchVersion = Mips64r6; 187 if (Bits[Mips::FeatureNaN2008]) IsNaN2008bit = true; 188 if (Bits[Mips::FeatureNoABICalls]) NoABICalls = true; 189 if (Bits[Mips::FeatureNoOddSPReg]) UseOddSPReg = false; 190 if (Bits[Mips::FeatureSingleFloat]) IsSingleFloat = true; 191 if (Bits[Mips::FeatureSoftFloat]) IsSoftFloat = true; 192 if (Bits[Mips::FeatureUseTCCInDIV]) UseTCCInDIV = false; 193 if (Bits[Mips::FeatureVFPU]) HasVFPU = true; 194 if (Bits[Mips::ImplP5600] && ProcImpl < MipsSubtarget::CPU::P5600) ProcImpl = MipsSubtarget::CPU::P5600; 195} 196#endif // GET_SUBTARGETINFO_TARGET_DESC 197