1 /* Instruction printing code for the ARM
2 Copyright (C) 1994-2017 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
6 This file is part of libopcodes.
7
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
22
23 #include "sysdep.h"
24
25 #include "disas-asm.h"
26 #include "opcode-arm.h"
27 // #include "opcode/arm.h"
28 #include "opintl.h"
29 // #include "safe-ctype.h"
30 #ifndef _MSC_VER
31 #include "libiberty.h"
32 #else
33 #include <stdlib.h>
34 #define XNEWVEC(T, N) ((T *) malloc (sizeof (T) * (N)))
35 #define XCNEWVEC(T, N) ((T *) calloc ((N), sizeof (T)))
36 #define XNEW(T) ((T *) malloc (sizeof (T)))
37 #define ARRAY_SIZE _countof
38 #endif
39 #include "floatformat.h"
40
41 /* FIXME: This shouldn't be done here. */
42 // #include "coff/internal.h"
43 // #include "libcoff.h"
44 // #include "elf-bfd.h"
45 // #include "elf/internal.h"
46 // #include "elf/arm.h"
47 // #include "mach-o.h"
48 #define abort() exit(1)
49
50 /* FIXME: Belongs in global header. */
51 #ifndef strneq
52 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
53 #endif
54
55 /* Cached mapping symbol state. */
56 enum map_type
57 {
58 MAP_ARM,
59 MAP_THUMB,
60 MAP_DATA
61 };
62
63 struct arm_private_data
64 {
65 /* The features to use when disassembling optional instructions. */
66 arm_feature_set features;
67
68 /* Whether any mapping symbols are present in the provided symbol
69 table. -1 if we do not know yet, otherwise 0 or 1. */
70 int has_mapping_symbols;
71
72 /* Track the last type (although this doesn't seem to be useful) */
73 enum map_type last_type;
74
75 /* Tracking symbol table information */
76 int last_mapping_sym;
77 bfd_vma last_mapping_addr;
78 };
79
80 struct opcode32
81 {
82 arm_feature_set arch; /* Architecture defining this insn. */
83 unsigned long value; /* If arch is 0 then value is a sentinel. */
84 unsigned long mask; /* Recognise insn if (op & mask) == value. */
85 const char * assembler; /* How to disassemble this insn. */
86 };
87
88 struct opcode16
89 {
90 arm_feature_set arch; /* Architecture defining this insn. */
91 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
92 const char *assembler; /* How to disassemble this insn. */
93 };
94
95 /* print_insn_coprocessor recognizes the following format control codes:
96
97 %% %
98
99 %c print condition code (always bits 28-31 in ARM mode)
100 %q print shifter argument
101 %u print condition code (unconditional in ARM mode,
102 UNPREDICTABLE if not AL in Thumb)
103 %A print address for ldc/stc/ldf/stf instruction
104 %B print vstm/vldm register list
105 %I print cirrus signed shift immediate: bits 0..3|4..6
106 %F print the COUNT field of a LFM/SFM instruction.
107 %P print floating point precision in arithmetic insn
108 %Q print floating point precision in ldf/stf insn
109 %R print floating point rounding mode
110
111 %<bitfield>c print as a condition code (for vsel)
112 %<bitfield>r print as an ARM register
113 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
114 %<bitfield>ru as %<>r but each u register must be unique.
115 %<bitfield>d print the bitfield in decimal
116 %<bitfield>k print immediate for VFPv3 conversion instruction
117 %<bitfield>x print the bitfield in hex
118 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
119 %<bitfield>f print a floating point constant if >7 else a
120 floating point register
121 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
122 %<bitfield>g print as an iWMMXt 64-bit register
123 %<bitfield>G print as an iWMMXt general purpose or control register
124 %<bitfield>D print as a NEON D register
125 %<bitfield>Q print as a NEON Q register
126 %<bitfield>V print as a NEON D or Q register
127 %<bitfield>E print a quarter-float immediate value
128
129 %y<code> print a single precision VFP reg.
130 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
131 %z<code> print a double precision VFP reg
132 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
133
134 %<bitfield>'c print specified char iff bitfield is all ones
135 %<bitfield>`c print specified char iff bitfield is all zeroes
136 %<bitfield>?ab... select from array of values in big endian order
137
138 %L print as an iWMMXt N/M width field.
139 %Z print the Immediate of a WSHUFH instruction.
140 %l like 'A' except use byte offsets for 'B' & 'H'
141 versions.
142 %i print 5-bit immediate in bits 8,3..0
143 (print "32" when 0)
144 %r print register offset address for wldt/wstr instruction. */
145
146 enum opcode_sentinel_enum
147 {
148 SENTINEL_IWMMXT_START = 1,
149 SENTINEL_IWMMXT_END,
150 SENTINEL_GENERIC_START
151 } opcode_sentinels;
152
153 #define UNDEFINED_INSTRUCTION " ; <UNDEFINED> instruction: %0-31x"
154 #define UNPREDICTABLE_INSTRUCTION " ; <UNPREDICTABLE>"
155
156 /* Common coprocessor opcodes shared between Arm and Thumb-2. */
157
158 static const struct opcode32 coprocessor_opcodes[] =
159 {
160 /* XScale instructions. */
161 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
162 0x0e200010, 0x0fff0ff0,
163 "mia%c acc0, %0-3r, %12-15r"},
164 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
165 0x0e280010, 0x0fff0ff0,
166 "miaph%c acc0, %0-3r, %12-15r"},
167 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
168 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c acc0, %0-3r, %12-15r"},
169 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
170 0x0c400000, 0x0ff00fff, "mar%c acc0, %12-15r, %16-19r"},
171 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
172 0x0c500000, 0x0ff00fff, "mra%c %12-15r, %16-19r, acc0"},
173
174 /* Intel Wireless MMX technology instructions. */
175 {ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
176 {ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
177 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c %12-15r"},
178 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
179 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c %16-19g, %12-15r"},
180 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
181 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c %12-15r, %0-2d"},
182 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
183 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c %12-15r, %16-19g, %0-2d"},
184 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
185 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c %16-19g, %12-15r, %0-2d"},
186 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
187 0x0e000110, 0x0ff00fff, "tmcr%c %16-19G, %12-15r"},
188 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
189 0x0c400000, 0x0ff00ff0, "tmcrr%c %0-3g, %12-15r, %16-19r"},
190 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
191 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c %5-8g, %0-3r, %12-15r"},
192 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
193 0x0e200010, 0x0fff0e10, "tmia%c %5-8g, %0-3r, %12-15r"},
194 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
195 0x0e280010, 0x0fff0e10, "tmiaph%c %5-8g, %0-3r, %12-15r"},
196 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
197 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c %12-15r, %16-19g"},
198 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
199 0x0e100110, 0x0ff00ff0, "tmrc%c %12-15r, %16-19G"},
200 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
201 0x0c500000, 0x0ff00ff0, "tmrrc%c %12-15r, %16-19r, %0-3g"},
202 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
203 0x0e130150, 0x0f3f0fff, "torc%22-23w%c %12-15r"},
204 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
205 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c %12-15r"},
206 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
207 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c %12-15g, %16-19g"},
208 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
209 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c %12-15g, %16-19g"},
210 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
211 0x0e000180, 0x0f000ff0, "wadd%20-23w%c %12-15g, %16-19g, %0-3g"},
212 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
213 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c %12-15g, %16-19g, %0-3g"},
214 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
215 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c %12-15g, %16-19g, %0-3g"},
216 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
217 0x0e000020, 0x0f800ff0, "waligni%c %12-15g, %16-19g, %0-3g, %20-22d"},
218 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
219 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c %12-15g, %16-19g, %0-3g"},
220 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
221 0x0e200000, 0x0fe00ff0, "wand%20'n%c %12-15g, %16-19g, %0-3g"},
222 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
223 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c %12-15g, %16-19g, %0-3g"},
224 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
225 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c %12-15g, %16-19g, %0-3g"},
226 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
227 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c %12-15g, %16-19g, %0-3g"},
228 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
229 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c %12-15g, %16-19g, %0-3g"},
230 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
231 0xfc500100, 0xfe500f00, "wldrd %12-15g, %r"},
232 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
233 0xfc100100, 0xfe500f00, "wldrw %12-15G, %A"},
234 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
235 0x0c100000, 0x0e100e00, "wldr%L%c %12-15g, %l"},
236 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
237 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c %12-15g, %16-19g, %0-3g"},
238 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
239 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c %12-15g, %16-19g, %0-3g"},
240 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
241 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c %12-15g, %16-19g, %0-3g"},
242 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
243 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c %12-15g, %16-19g, %0-3g"},
244 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
245 0x0e000080, 0x0f100fe0, "wmerge%c %12-15g, %16-19g, %0-3g, %21-23d"},
246 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
247 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c %12-15g, %16-19g, %0-3g"},
248 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
249 0x0e800120, 0x0f800ff0,
250 "wmiaw%21?tb%20?tb%22'n%c %12-15g, %16-19g, %0-3g"},
251 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
252 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c %12-15g, %16-19g, %0-3g"},
253 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
254 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c %12-15g, %16-19g, %0-3g"},
255 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
256 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c %12-15g, %16-19g, %0-3g"},
257 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
258 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c %12-15g, %16-19g, %0-3g"},
259 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
260 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c %12-15g, %16-19g, %0-3g"},
261 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
262 0x0eb000c0, 0x0ff00ff0, "wmulwl%c %12-15g, %16-19g, %0-3g"},
263 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
264 0x0e8000a0, 0x0f800ff0,
265 "wqmia%21?tb%20?tb%22'n%c %12-15g, %16-19g, %0-3g"},
266 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
267 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c %12-15g, %16-19g, %0-3g"},
268 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
269 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c %12-15g, %16-19g, %0-3g"},
270 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
271 0x0e000000, 0x0ff00ff0, "wor%c %12-15g, %16-19g, %0-3g"},
272 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
273 0x0e000080, 0x0f000ff0, "wpack%20-23w%c %12-15g, %16-19g, %0-3g"},
274 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
275 0xfe300040, 0xff300ef0, "wror%22-23w %12-15g, %16-19g, %i"},
276 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
277 0x0e300040, 0x0f300ff0, "wror%22-23w%c %12-15g, %16-19g, %0-3g"},
278 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
279 0x0e300140, 0x0f300ff0, "wror%22-23wg%c %12-15g, %16-19g, %0-3G"},
280 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
281 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c %12-15g, %16-19g, %0-3g"},
282 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
283 0x0e0001e0, 0x0f000ff0, "wshufh%c %12-15g, %16-19g, %Z"},
284 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
285 0xfe100040, 0xff300ef0, "wsll%22-23w %12-15g, %16-19g, %i"},
286 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
287 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c %12-15g, %16-19g, %0-3g"},
288 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
289 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c %12-15g, %16-19g, %0-3G"},
290 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
291 0xfe000040, 0xff300ef0, "wsra%22-23w %12-15g, %16-19g, %i"},
292 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
293 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c %12-15g, %16-19g, %0-3g"},
294 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
295 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c %12-15g, %16-19g, %0-3G"},
296 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
297 0xfe200040, 0xff300ef0, "wsrl%22-23w %12-15g, %16-19g, %i"},
298 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
299 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c %12-15g, %16-19g, %0-3g"},
300 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
301 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c %12-15g, %16-19g, %0-3G"},
302 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
303 0xfc400100, 0xfe500f00, "wstrd %12-15g, %r"},
304 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
305 0xfc000100, 0xfe500f00, "wstrw %12-15G, %A"},
306 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
307 0x0c000000, 0x0e100e00, "wstr%L%c %12-15g, %l"},
308 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
309 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c %12-15g, %16-19g, %0-3g"},
310 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
311 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c %12-15g, %16-19g, %0-3g"},
312 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
313 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c %12-15g, %16-19g, %0-3g"},
314 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
315 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c %12-15g, %16-19g"},
316 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
317 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c %12-15g, %16-19g"},
318 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
319 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c %12-15g, %16-19g"},
320 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
321 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c %12-15g, %16-19g"},
322 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
323 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c %12-15g, %16-19g, %0-3g"},
324 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
325 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c %12-15g, %16-19g, %0-3g"},
326 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
327 0x0e100000, 0x0ff00ff0, "wxor%c %12-15g, %16-19g, %0-3g"},
328 {ARM_FEATURE_CORE_LOW (0),
329 SENTINEL_IWMMXT_END, 0, "" },
330
331 /* Floating point coprocessor (FPA) instructions. */
332 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
333 0x0e000100, 0x0ff08f10, "adf%c%P%R %12-14f, %16-18f, %0-3f"},
334 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
335 0x0e100100, 0x0ff08f10, "muf%c%P%R %12-14f, %16-18f, %0-3f"},
336 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
337 0x0e200100, 0x0ff08f10, "suf%c%P%R %12-14f, %16-18f, %0-3f"},
338 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
339 0x0e300100, 0x0ff08f10, "rsf%c%P%R %12-14f, %16-18f, %0-3f"},
340 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
341 0x0e400100, 0x0ff08f10, "dvf%c%P%R %12-14f, %16-18f, %0-3f"},
342 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
343 0x0e500100, 0x0ff08f10, "rdf%c%P%R %12-14f, %16-18f, %0-3f"},
344 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
345 0x0e600100, 0x0ff08f10, "pow%c%P%R %12-14f, %16-18f, %0-3f"},
346 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
347 0x0e700100, 0x0ff08f10, "rpw%c%P%R %12-14f, %16-18f, %0-3f"},
348 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
349 0x0e800100, 0x0ff08f10, "rmf%c%P%R %12-14f, %16-18f, %0-3f"},
350 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
351 0x0e900100, 0x0ff08f10, "fml%c%P%R %12-14f, %16-18f, %0-3f"},
352 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
353 0x0ea00100, 0x0ff08f10, "fdv%c%P%R %12-14f, %16-18f, %0-3f"},
354 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
355 0x0eb00100, 0x0ff08f10, "frd%c%P%R %12-14f, %16-18f, %0-3f"},
356 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
357 0x0ec00100, 0x0ff08f10, "pol%c%P%R %12-14f, %16-18f, %0-3f"},
358 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
359 0x0e008100, 0x0ff08f10, "mvf%c%P%R %12-14f, %0-3f"},
360 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
361 0x0e108100, 0x0ff08f10, "mnf%c%P%R %12-14f, %0-3f"},
362 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
363 0x0e208100, 0x0ff08f10, "abs%c%P%R %12-14f, %0-3f"},
364 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
365 0x0e308100, 0x0ff08f10, "rnd%c%P%R %12-14f, %0-3f"},
366 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
367 0x0e408100, 0x0ff08f10, "sqt%c%P%R %12-14f, %0-3f"},
368 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
369 0x0e508100, 0x0ff08f10, "log%c%P%R %12-14f, %0-3f"},
370 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
371 0x0e608100, 0x0ff08f10, "lgn%c%P%R %12-14f, %0-3f"},
372 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
373 0x0e708100, 0x0ff08f10, "exp%c%P%R %12-14f, %0-3f"},
374 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
375 0x0e808100, 0x0ff08f10, "sin%c%P%R %12-14f, %0-3f"},
376 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
377 0x0e908100, 0x0ff08f10, "cos%c%P%R %12-14f, %0-3f"},
378 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
379 0x0ea08100, 0x0ff08f10, "tan%c%P%R %12-14f, %0-3f"},
380 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
381 0x0eb08100, 0x0ff08f10, "asn%c%P%R %12-14f, %0-3f"},
382 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
383 0x0ec08100, 0x0ff08f10, "acs%c%P%R %12-14f, %0-3f"},
384 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
385 0x0ed08100, 0x0ff08f10, "atn%c%P%R %12-14f, %0-3f"},
386 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
387 0x0ee08100, 0x0ff08f10, "urd%c%P%R %12-14f, %0-3f"},
388 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
389 0x0ef08100, 0x0ff08f10, "nrm%c%P%R %12-14f, %0-3f"},
390 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
391 0x0e000110, 0x0ff00f1f, "flt%c%P%R %16-18f, %12-15r"},
392 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
393 0x0e100110, 0x0fff0f98, "fix%c%R %12-15r, %0-2f"},
394 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
395 0x0e200110, 0x0fff0fff, "wfs%c %12-15r"},
396 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
397 0x0e300110, 0x0fff0fff, "rfs%c %12-15r"},
398 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
399 0x0e400110, 0x0fff0fff, "wfc%c %12-15r"},
400 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
401 0x0e500110, 0x0fff0fff, "rfc%c %12-15r"},
402 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
403 0x0e90f110, 0x0ff8fff0, "cmf%c %16-18f, %0-3f"},
404 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
405 0x0eb0f110, 0x0ff8fff0, "cnf%c %16-18f, %0-3f"},
406 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
407 0x0ed0f110, 0x0ff8fff0, "cmfe%c %16-18f, %0-3f"},
408 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
409 0x0ef0f110, 0x0ff8fff0, "cnfe%c %16-18f, %0-3f"},
410 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
411 0x0c000100, 0x0e100f00, "stf%c%Q %12-14f, %A"},
412 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
413 0x0c100100, 0x0e100f00, "ldf%c%Q %12-14f, %A"},
414 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
415 0x0c000200, 0x0e100f00, "sfm%c %12-14f, %F, %A"},
416 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
417 0x0c100200, 0x0e100f00, "lfm%c %12-14f, %F, %A"},
418
419 /* ARMv8-M Mainline Security Extensions instructions. */
420 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
421 0xec300a00, 0xfff0ffff, "vlldm %16-19r"},
422 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
423 0xec200a00, 0xfff0ffff, "vlstm %16-19r"},
424
425 /* Register load/store. */
426 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
427 0x0d2d0b00, 0x0fbf0f01, "vpush%c %B"},
428 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
429 0x0d200b00, 0x0fb00f01, "vstmdb%c %16-19r!, %B"},
430 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
431 0x0d300b00, 0x0fb00f01, "vldmdb%c %16-19r!, %B"},
432 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
433 0x0c800b00, 0x0f900f01, "vstmia%c %16-19r%21'!, %B"},
434 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
435 0x0cbd0b00, 0x0fbf0f01, "vpop%c %B"},
436 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
437 0x0c900b00, 0x0f900f01, "vldmia%c %16-19r%21'!, %B"},
438 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
439 0x0d000b00, 0x0f300f00, "vstr%c %12-15,22D, %A"},
440 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
441 0x0d100b00, 0x0f300f00, "vldr%c %12-15,22D, %A"},
442 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
443 0x0d2d0a00, 0x0fbf0f00, "vpush%c %y3"},
444 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
445 0x0d200a00, 0x0fb00f00, "vstmdb%c %16-19r!, %y3"},
446 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
447 0x0d300a00, 0x0fb00f00, "vldmdb%c %16-19r!, %y3"},
448 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
449 0x0c800a00, 0x0f900f00, "vstmia%c %16-19r%21'!, %y3"},
450 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
451 0x0cbd0a00, 0x0fbf0f00, "vpop%c %y3"},
452 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
453 0x0c900a00, 0x0f900f00, "vldmia%c %16-19r%21'!, %y3"},
454 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
455 0x0d000a00, 0x0f300f00, "vstr%c %y1, %A"},
456 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
457 0x0d100a00, 0x0f300f00, "vldr%c %y1, %A"},
458
459 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
460 0x0d200b01, 0x0fb00f01, "fstmdbx%c %16-19r!, %z3 ;@ Deprecated"},
461 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
462 0x0d300b01, 0x0fb00f01, "fldmdbx%c %16-19r!, %z3 ;@ Deprecated"},
463 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
464 0x0c800b01, 0x0f900f01, "fstmiax%c %16-19r%21'!, %z3 ;@ Deprecated"},
465 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
466 0x0c900b01, 0x0f900f01, "fldmiax%c %16-19r%21'!, %z3 ;@ Deprecated"},
467
468 /* Data transfer between ARM and NEON registers. */
469 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
470 0x0e800b10, 0x0ff00f70, "vdup%c.32 %16-19,7D, %12-15r"},
471 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
472 0x0e800b30, 0x0ff00f70, "vdup%c.16 %16-19,7D, %12-15r"},
473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
474 0x0ea00b10, 0x0ff00f70, "vdup%c.32 %16-19,7Q, %12-15r"},
475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
476 0x0ea00b30, 0x0ff00f70, "vdup%c.16 %16-19,7Q, %12-15r"},
477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
478 0x0ec00b10, 0x0ff00f70, "vdup%c.8 %16-19,7D, %12-15r"},
479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
480 0x0ee00b10, 0x0ff00f70, "vdup%c.8 %16-19,7Q, %12-15r"},
481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
482 0x0c400b10, 0x0ff00fd0, "vmov%c %0-3,5D, %12-15r, %16-19r"},
483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
484 0x0c500b10, 0x0ff00fd0, "vmov%c %12-15r, %16-19r, %0-3,5D"},
485 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
486 0x0e000b10, 0x0fd00f70, "vmov%c.32 %16-19,7D[%21d], %12-15r"},
487 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
488 0x0e100b10, 0x0f500f70, "vmov%c.32 %12-15r, %16-19,7D[%21d]"},
489 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
490 0x0e000b30, 0x0fd00f30, "vmov%c.16 %16-19,7D[%6,21d], %12-15r"},
491 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
492 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16 %12-15r, %16-19,7D[%6,21d]"},
493 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
494 0x0e400b10, 0x0fd00f10, "vmov%c.8 %16-19,7D[%5,6,21d], %12-15r"},
495 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
496 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8 %12-15r, %16-19,7D[%5,6,21d]"},
497 /* Half-precision conversion instructions. */
498 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
499 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16 %z1, %y0"},
500 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
501 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64 %y1, %z0"},
502 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
503 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16 %y1, %y0"},
504 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
505 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32 %y1, %y0"},
506
507 /* Floating point coprocessor (VFP) instructions. */
508 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
509 0x0ee00a10, 0x0fff0fff, "vmsr%c fpsid, %12-15r"},
510 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
511 0x0ee10a10, 0x0fff0fff, "vmsr%c fpscr, %12-15r"},
512 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
513 0x0ee60a10, 0x0fff0fff, "vmsr%c mvfr1, %12-15r"},
514 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
515 0x0ee70a10, 0x0fff0fff, "vmsr%c mvfr0, %12-15r"},
516 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
517 0x0ee80a10, 0x0fff0fff, "vmsr%c fpexc, %12-15r"},
518 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
519 0x0ee90a10, 0x0fff0fff, "vmsr%c fpinst, %12-15r @ Impl def"},
520 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
521 0x0eea0a10, 0x0fff0fff, "vmsr%c fpinst2, %12-15r @ Impl def"},
522 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
523 0x0ef00a10, 0x0fff0fff, "vmrs%c %12-15r, fpsid"},
524 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
525 0x0ef1fa10, 0x0fffffff, "vmrs%c APSR_nzcv, fpscr"},
526 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
527 0x0ef10a10, 0x0fff0fff, "vmrs%c %12-15r, fpscr"},
528 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
529 0x0ef60a10, 0x0fff0fff, "vmrs%c %12-15r, mvfr1"},
530 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
531 0x0ef70a10, 0x0fff0fff, "vmrs%c %12-15r, mvfr0"},
532 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
533 0x0ef80a10, 0x0fff0fff, "vmrs%c %12-15r, fpexc"},
534 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
535 0x0ef90a10, 0x0fff0fff, "vmrs%c %12-15r, fpinst @ Impl def"},
536 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
537 0x0efa0a10, 0x0fff0fff, "vmrs%c %12-15r, fpinst2 @ Impl def"},
538 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
539 0x0e000b10, 0x0fd00fff, "vmov%c.32 %z2[%21d], %12-15r"},
540 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
541 0x0e100b10, 0x0fd00fff, "vmov%c.32 %12-15r, %z2[%21d]"},
542 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
543 0x0ee00a10, 0x0ff00fff, "vmsr%c <impl def %16-19x>, %12-15r"},
544 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
545 0x0ef00a10, 0x0ff00fff, "vmrs%c %12-15r, <impl def %16-19x>"},
546 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
547 0x0e000a10, 0x0ff00f7f, "vmov%c %y2, %12-15r"},
548 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
549 0x0e100a10, 0x0ff00f7f, "vmov%c %12-15r, %y2"},
550 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
551 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32 %y1, #0.0"},
552 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
553 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64 %z1, #0.0"},
554 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
555 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32 %y1, %y0"},
556 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
557 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32 %y1, %y0"},
558 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
559 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64 %z1, %z0"},
560 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
561 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64 %z1, %z0"},
562 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
563 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32 %y1, %y0"},
564 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
565 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32 %y1, %y0"},
566 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
567 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64 %z1, %z0"},
568 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
569 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64 %z1, %z0"},
570 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
571 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32 %z1, %y0"},
572 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
573 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64 %y1, %z0"},
574 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
575 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32 %y1, %y0"},
576 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
577 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32 %z1, %y0"},
578 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
579 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32 %y1, %y0"},
580 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
581 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64 %z1, %z0"},
582 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
583 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26 %y1, %y1, %5,0-3k"},
584 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
585 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26 %z1, %z1, %5,0-3k"},
586 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
587 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32 %y1, %y0"},
588 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
589 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64 %y1, %z0"},
590 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
591 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32 %y1, %y1, %5,0-3k"},
592 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
593 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64 %z1, %z1, %5,0-3k"},
594 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
595 0x0c500b10, 0x0fb00ff0, "vmov%c %12-15r, %16-19r, %z0"},
596 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
597 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32 %y1, %0-3,16-19E"},
598 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
599 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64 %z1, %0-3,16-19E"},
600 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
601 0x0c400a10, 0x0ff00fd0, "vmov%c %y4, %12-15r, %16-19r"},
602 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
603 0x0c400b10, 0x0ff00fd0, "vmov%c %z0, %12-15r, %16-19r"},
604 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
605 0x0c500a10, 0x0ff00fd0, "vmov%c %12-15r, %16-19r, %y4"},
606 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
607 0x0e000a00, 0x0fb00f50, "vmla%c.f32 %y1, %y2, %y0"},
608 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
609 0x0e000a40, 0x0fb00f50, "vmls%c.f32 %y1, %y2, %y0"},
610 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
611 0x0e000b00, 0x0fb00f50, "vmla%c.f64 %z1, %z2, %z0"},
612 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
613 0x0e000b40, 0x0fb00f50, "vmls%c.f64 %z1, %z2, %z0"},
614 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
615 0x0e100a00, 0x0fb00f50, "vnmls%c.f32 %y1, %y2, %y0"},
616 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
617 0x0e100a40, 0x0fb00f50, "vnmla%c.f32 %y1, %y2, %y0"},
618 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
619 0x0e100b00, 0x0fb00f50, "vnmls%c.f64 %z1, %z2, %z0"},
620 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
621 0x0e100b40, 0x0fb00f50, "vnmla%c.f64 %z1, %z2, %z0"},
622 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
623 0x0e200a00, 0x0fb00f50, "vmul%c.f32 %y1, %y2, %y0"},
624 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
625 0x0e200a40, 0x0fb00f50, "vnmul%c.f32 %y1, %y2, %y0"},
626 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
627 0x0e200b00, 0x0fb00f50, "vmul%c.f64 %z1, %z2, %z0"},
628 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
629 0x0e200b40, 0x0fb00f50, "vnmul%c.f64 %z1, %z2, %z0"},
630 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
631 0x0e300a00, 0x0fb00f50, "vadd%c.f32 %y1, %y2, %y0"},
632 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
633 0x0e300a40, 0x0fb00f50, "vsub%c.f32 %y1, %y2, %y0"},
634 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
635 0x0e300b00, 0x0fb00f50, "vadd%c.f64 %z1, %z2, %z0"},
636 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
637 0x0e300b40, 0x0fb00f50, "vsub%c.f64 %z1, %z2, %z0"},
638 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
639 0x0e800a00, 0x0fb00f50, "vdiv%c.f32 %y1, %y2, %y0"},
640 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
641 0x0e800b00, 0x0fb00f50, "vdiv%c.f64 %z1, %z2, %z0"},
642
643 /* Cirrus coprocessor instructions. */
644 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
645 0x0d100400, 0x0f500f00, "cfldrs%c mvf%12-15d, %A"},
646 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
647 0x0c100400, 0x0f500f00, "cfldrs%c mvf%12-15d, %A"},
648 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
649 0x0d500400, 0x0f500f00, "cfldrd%c mvd%12-15d, %A"},
650 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
651 0x0c500400, 0x0f500f00, "cfldrd%c mvd%12-15d, %A"},
652 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
653 0x0d100500, 0x0f500f00, "cfldr32%c mvfx%12-15d, %A"},
654 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
655 0x0c100500, 0x0f500f00, "cfldr32%c mvfx%12-15d, %A"},
656 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
657 0x0d500500, 0x0f500f00, "cfldr64%c mvdx%12-15d, %A"},
658 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
659 0x0c500500, 0x0f500f00, "cfldr64%c mvdx%12-15d, %A"},
660 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
661 0x0d000400, 0x0f500f00, "cfstrs%c mvf%12-15d, %A"},
662 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
663 0x0c000400, 0x0f500f00, "cfstrs%c mvf%12-15d, %A"},
664 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
665 0x0d400400, 0x0f500f00, "cfstrd%c mvd%12-15d, %A"},
666 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
667 0x0c400400, 0x0f500f00, "cfstrd%c mvd%12-15d, %A"},
668 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
669 0x0d000500, 0x0f500f00, "cfstr32%c mvfx%12-15d, %A"},
670 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
671 0x0c000500, 0x0f500f00, "cfstr32%c mvfx%12-15d, %A"},
672 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
673 0x0d400500, 0x0f500f00, "cfstr64%c mvdx%12-15d, %A"},
674 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
675 0x0c400500, 0x0f500f00, "cfstr64%c mvdx%12-15d, %A"},
676 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
677 0x0e000450, 0x0ff00ff0, "cfmvsr%c mvf%16-19d, %12-15r"},
678 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
679 0x0e100450, 0x0ff00ff0, "cfmvrs%c %12-15r, mvf%16-19d"},
680 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
681 0x0e000410, 0x0ff00ff0, "cfmvdlr%c mvd%16-19d, %12-15r"},
682 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
683 0x0e100410, 0x0ff00ff0, "cfmvrdl%c %12-15r, mvd%16-19d"},
684 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
685 0x0e000430, 0x0ff00ff0, "cfmvdhr%c mvd%16-19d, %12-15r"},
686 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
687 0x0e100430, 0x0ff00fff, "cfmvrdh%c %12-15r, mvd%16-19d"},
688 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
689 0x0e000510, 0x0ff00fff, "cfmv64lr%c mvdx%16-19d, %12-15r"},
690 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
691 0x0e100510, 0x0ff00fff, "cfmvr64l%c %12-15r, mvdx%16-19d"},
692 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
693 0x0e000530, 0x0ff00fff, "cfmv64hr%c mvdx%16-19d, %12-15r"},
694 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
695 0x0e100530, 0x0ff00fff, "cfmvr64h%c %12-15r, mvdx%16-19d"},
696 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
697 0x0e200440, 0x0ff00fff, "cfmval32%c mvax%12-15d, mvfx%16-19d"},
698 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
699 0x0e100440, 0x0ff00fff, "cfmv32al%c mvfx%12-15d, mvax%16-19d"},
700 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
701 0x0e200460, 0x0ff00fff, "cfmvam32%c mvax%12-15d, mvfx%16-19d"},
702 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
703 0x0e100460, 0x0ff00fff, "cfmv32am%c mvfx%12-15d, mvax%16-19d"},
704 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
705 0x0e200480, 0x0ff00fff, "cfmvah32%c mvax%12-15d, mvfx%16-19d"},
706 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
707 0x0e100480, 0x0ff00fff, "cfmv32ah%c mvfx%12-15d, mvax%16-19d"},
708 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
709 0x0e2004a0, 0x0ff00fff, "cfmva32%c mvax%12-15d, mvfx%16-19d"},
710 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
711 0x0e1004a0, 0x0ff00fff, "cfmv32a%c mvfx%12-15d, mvax%16-19d"},
712 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
713 0x0e2004c0, 0x0ff00fff, "cfmva64%c mvax%12-15d, mvdx%16-19d"},
714 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
715 0x0e1004c0, 0x0ff00fff, "cfmv64a%c mvdx%12-15d, mvax%16-19d"},
716 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
717 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c dspsc, mvdx%12-15d"},
718 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
719 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c mvdx%12-15d, dspsc"},
720 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
721 0x0e000400, 0x0ff00fff, "cfcpys%c mvf%12-15d, mvf%16-19d"},
722 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
723 0x0e000420, 0x0ff00fff, "cfcpyd%c mvd%12-15d, mvd%16-19d"},
724 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
725 0x0e000460, 0x0ff00fff, "cfcvtsd%c mvd%12-15d, mvf%16-19d"},
726 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
727 0x0e000440, 0x0ff00fff, "cfcvtds%c mvf%12-15d, mvd%16-19d"},
728 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
729 0x0e000480, 0x0ff00fff, "cfcvt32s%c mvf%12-15d, mvfx%16-19d"},
730 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
731 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c mvd%12-15d, mvfx%16-19d"},
732 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
733 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c mvf%12-15d, mvdx%16-19d"},
734 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
735 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c mvd%12-15d, mvdx%16-19d"},
736 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
737 0x0e100580, 0x0ff00fff, "cfcvts32%c mvfx%12-15d, mvf%16-19d"},
738 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
739 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c mvfx%12-15d, mvd%16-19d"},
740 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
741 0x0e1005c0, 0x0ff00fff, "cftruncs32%c mvfx%12-15d, mvf%16-19d"},
742 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
743 0x0e1005e0, 0x0ff00fff, "cftruncd32%c mvfx%12-15d, mvd%16-19d"},
744 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
745 0x0e000550, 0x0ff00ff0, "cfrshl32%c mvfx%16-19d, mvfx%0-3d, %12-15r"},
746 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
747 0x0e000570, 0x0ff00ff0, "cfrshl64%c mvdx%16-19d, mvdx%0-3d, %12-15r"},
748 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
749 0x0e000500, 0x0ff00f10, "cfsh32%c mvfx%12-15d, mvfx%16-19d, %I"},
750 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
751 0x0e200500, 0x0ff00f10, "cfsh64%c mvdx%12-15d, mvdx%16-19d, %I"},
752 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
753 0x0e100490, 0x0ff00ff0, "cfcmps%c %12-15r, mvf%16-19d, mvf%0-3d"},
754 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
755 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c %12-15r, mvd%16-19d, mvd%0-3d"},
756 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
757 0x0e100590, 0x0ff00ff0, "cfcmp32%c %12-15r, mvfx%16-19d, mvfx%0-3d"},
758 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
759 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c %12-15r, mvdx%16-19d, mvdx%0-3d"},
760 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
761 0x0e300400, 0x0ff00fff, "cfabss%c mvf%12-15d, mvf%16-19d"},
762 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
763 0x0e300420, 0x0ff00fff, "cfabsd%c mvd%12-15d, mvd%16-19d"},
764 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
765 0x0e300440, 0x0ff00fff, "cfnegs%c mvf%12-15d, mvf%16-19d"},
766 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
767 0x0e300460, 0x0ff00fff, "cfnegd%c mvd%12-15d, mvd%16-19d"},
768 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
769 0x0e300480, 0x0ff00ff0, "cfadds%c mvf%12-15d, mvf%16-19d, mvf%0-3d"},
770 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
771 0x0e3004a0, 0x0ff00ff0, "cfaddd%c mvd%12-15d, mvd%16-19d, mvd%0-3d"},
772 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
773 0x0e3004c0, 0x0ff00ff0, "cfsubs%c mvf%12-15d, mvf%16-19d, mvf%0-3d"},
774 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
775 0x0e3004e0, 0x0ff00ff0, "cfsubd%c mvd%12-15d, mvd%16-19d, mvd%0-3d"},
776 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
777 0x0e100400, 0x0ff00ff0, "cfmuls%c mvf%12-15d, mvf%16-19d, mvf%0-3d"},
778 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
779 0x0e100420, 0x0ff00ff0, "cfmuld%c mvd%12-15d, mvd%16-19d, mvd%0-3d"},
780 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
781 0x0e300500, 0x0ff00fff, "cfabs32%c mvfx%12-15d, mvfx%16-19d"},
782 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
783 0x0e300520, 0x0ff00fff, "cfabs64%c mvdx%12-15d, mvdx%16-19d"},
784 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
785 0x0e300540, 0x0ff00fff, "cfneg32%c mvfx%12-15d, mvfx%16-19d"},
786 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
787 0x0e300560, 0x0ff00fff, "cfneg64%c mvdx%12-15d, mvdx%16-19d"},
788 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
789 0x0e300580, 0x0ff00ff0, "cfadd32%c mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
790 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
791 0x0e3005a0, 0x0ff00ff0, "cfadd64%c mvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
792 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
793 0x0e3005c0, 0x0ff00ff0, "cfsub32%c mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
794 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
795 0x0e3005e0, 0x0ff00ff0, "cfsub64%c mvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
796 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
797 0x0e100500, 0x0ff00ff0, "cfmul32%c mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
798 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
799 0x0e100520, 0x0ff00ff0, "cfmul64%c mvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
800 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
801 0x0e100540, 0x0ff00ff0, "cfmac32%c mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
802 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
803 0x0e100560, 0x0ff00ff0, "cfmsc32%c mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
804 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
805 0x0e000600, 0x0ff00f10,
806 "cfmadd32%c mvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
807 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
808 0x0e100600, 0x0ff00f10,
809 "cfmsub32%c mvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
810 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
811 0x0e200600, 0x0ff00f10,
812 "cfmadda32%c mvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
813 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
814 0x0e300600, 0x0ff00f10,
815 "cfmsuba32%c mvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
816
817 /* VFP Fused multiply add instructions. */
818 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
819 0x0ea00a00, 0x0fb00f50, "vfma%c.f32 %y1, %y2, %y0"},
820 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
821 0x0ea00b00, 0x0fb00f50, "vfma%c.f64 %z1, %z2, %z0"},
822 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823 0x0ea00a40, 0x0fb00f50, "vfms%c.f32 %y1, %y2, %y0"},
824 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
825 0x0ea00b40, 0x0fb00f50, "vfms%c.f64 %z1, %z2, %z0"},
826 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
827 0x0e900a40, 0x0fb00f50, "vfnma%c.f32 %y1, %y2, %y0"},
828 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
829 0x0e900b40, 0x0fb00f50, "vfnma%c.f64 %z1, %z2, %z0"},
830 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
831 0x0e900a00, 0x0fb00f50, "vfnms%c.f32 %y1, %y2, %y0"},
832 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
833 0x0e900b00, 0x0fb00f50, "vfnms%c.f64 %z1, %z2, %z0"},
834
835 /* FP v5. */
836 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
837 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32 %y1, %y2, %y0"},
838 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
839 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64 %z1, %z2, %z0"},
840 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
841 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32 %y1, %y2, %y0"},
842 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
843 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64 %z1, %z2, %z0"},
844 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
845 0xfe800a40, 0xffb00f50, "vminnm%u.f32 %y1, %y2, %y0"},
846 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
847 0xfe800b40, 0xffb00f50, "vminnm%u.f64 %z1, %z2, %z0"},
848 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
849 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32 %y1, %y0"},
850 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
851 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64 %y1, %z0"},
852 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
853 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32 %y1, %y0"},
854 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
855 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64 %z1, %z0"},
856 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
857 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32 %y1, %y0"},
858 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
859 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64 %z1, %z0"},
860
861 /* Generic coprocessor instructions. */
862 {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
864 0x0c400000, 0x0ff00000, "mcrr%c %8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
866 0x0c500000, 0x0ff00000,
867 "mrrc%c %8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
869 0x0e000000, 0x0f000010,
870 "cdp%c %8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
872 0x0e10f010, 0x0f10f010,
873 "mrc%c %8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
875 0x0e100010, 0x0f100010,
876 "mrc%c %8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
878 0x0e000010, 0x0f100010,
879 "mcr%c %8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
881 0x0c000000, 0x0e100000, "stc%22'l%c %8-11d, cr%12-15d, %A"},
882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
883 0x0c100000, 0x0e100000, "ldc%22'l%c %8-11d, cr%12-15d, %A"},
884
885 /* V6 coprocessor instructions. */
886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
887 0xfc500000, 0xfff00000,
888 "mrrc2%c %8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
890 0xfc400000, 0xfff00000,
891 "mcrr2%c %8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
892
893 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
894 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
895 0xfc800800, 0xfeb00f10, "vcadd%c.f16 %12-15,22V, %16-19,7V, %0-3,5V, %24?29%24'70"},
896 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
897 0xfc900800, 0xfeb00f10, "vcadd%c.f32 %12-15,22V, %16-19,7V, %0-3,5V, %24?29%24'70"},
898 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
899 0xfc200800, 0xff300f10, "vcmla%c.f16 %12-15,22V, %16-19,7V, %0-3,5V, %23'90"},
900 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
901 0xfd200800, 0xff300f10, "vcmla%c.f16 %12-15,22V, %16-19,7V, %0-3,5V, %23?21%23?780"},
902 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
903 0xfc300800, 0xff300f10, "vcmla%c.f32 %12-15,22V, %16-19,7V, %0-3,5V, %23'90"},
904 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
905 0xfd300800, 0xff300f10, "vcmla%c.f32 %12-15,22V, %16-19,7V, %0-3,5V, %23?21%23?780"},
906 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
907 0xfe000800, 0xffa00f10, "vcmla%c.f16 %12-15,22V, %16-19,7V, %0-3D[%5?10], %20'90"},
908 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
909 0xfe200800, 0xffa00f10, "vcmla%c.f16 %12-15,22V, %16-19,7V, %0-3D[%5?10], %20?21%20?780"},
910 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
911 0xfe800800, 0xffa00f10, "vcmla%c.f32 %12-15,22V, %16-19,7V, %0-3,5D[0], %20'90"},
912 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
913 0xfea00800, 0xffa00f10, "vcmla%c.f32 %12-15,22V, %16-19,7V, %0-3,5D[0], %20?21%20?780"},
914
915 /* V5 coprocessor instructions. */
916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
917 0xfc100000, 0xfe100000, "ldc2%22'l%c %8-11d, cr%12-15d, %A"},
918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
919 0xfc000000, 0xfe100000, "stc2%22'l%c %8-11d, cr%12-15d, %A"},
920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
921 0xfe000000, 0xff000010,
922 "cdp2%c %8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
924 0xfe000010, 0xff100010,
925 "mcr2%c %8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
927 0xfe100010, 0xff100010,
928 "mrc2%c %8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
929
930 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
931 cp_num: bit <11:8> == 0b1001.
932 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
933 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
934 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16 %y1, %y0"},
935 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
936 0x0e300900, 0x0fb00f50, "vadd%c.f16 %y1, %y2, %y0"},
937 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
938 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16 %y1, %y0"},
939 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
940 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16 %y1, #0.0"},
941 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
942 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26 %y1, %y1, %5,0-3k"},
943 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
944 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16 %y1, %y1, %5,0-3k"},
945 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
946 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16 %y1, %y0"},
947 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
948 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32 %y1, %y0"},
949 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
950 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16 %y1, %y0"},
951 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
952 0x0e800900, 0x0fb00f50, "vdiv%c.f16 %y1, %y2, %y0"},
953 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
954 0x0ea00900, 0x0fb00f50, "vfma%c.f16 %y1, %y2, %y0"},
955 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
956 0x0ea00940, 0x0fb00f50, "vfms%c.f16 %y1, %y2, %y0"},
957 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
958 0x0e900940, 0x0fb00f50, "vfnma%c.f16 %y1, %y2, %y0"},
959 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
960 0x0e900900, 0x0fb00f50, "vfnms%c.f16 %y1, %y2, %y0"},
961 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
962 0xfeb00ac0, 0xffbf0fd0, "vins.f16 %y1, %y0"},
963 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
964 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16 %y1, %y0"},
965 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
966 0x0d100900, 0x0f300f00, "vldr%c.16 %y1, %A"},
967 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
968 0x0d000900, 0x0f300f00, "vstr%c.16 %y1, %A"},
969 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
970 0xfe800900, 0xffb00f50, "vmaxnm%c.f16 %y1, %y2, %y0"},
971 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
972 0xfe800940, 0xffb00f50, "vminnm%c.f16 %y1, %y2, %y0"},
973 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
974 0x0e000900, 0x0fb00f50, "vmla%c.f16 %y1, %y2, %y0"},
975 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
976 0x0e000940, 0x0fb00f50, "vmls%c.f16 %y1, %y2, %y0"},
977 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
978 0x0e100910, 0x0ff00f7f, "vmov%c.f16 %12-15r, %y2"},
979 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
980 0x0e000910, 0x0ff00f7f, "vmov%c.f16 %y2, %12-15r"},
981 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
982 0xeb00900, 0x0fb00ff0, "vmov%c.f16 %y1, %0-3,16-19E"},
983 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
984 0x0e200900, 0x0fb00f50, "vmul%c.f16 %y1, %y2, %y0"},
985 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
986 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16 %y1, %y0"},
987 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
988 0x0e100940, 0x0fb00f50, "vnmla%c.f16 %y1, %y2, %y0"},
989 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
990 0x0e100900, 0x0fb00f50, "vnmls%c.f16 %y1, %y2, %y0"},
991 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
992 0x0e200940, 0x0fb00f50, "vnmul%c.f16 %y1, %y2, %y0"},
993 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
994 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16 %y1, %y0"},
995 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
996 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16 %y1, %y0"},
997 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
998 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16 %y1, %y2, %y0"},
999 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1000 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16 %y1, %y0"},
1001 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1002 0x0e300940, 0x0fb00f50, "vsub%c.f16 %y1, %y2, %y0"},
1003
1004 /* ARMv8.3 javascript conversion instruction. */
1005 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1006 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64 %y1, %z0"},
1007
1008 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1009 };
1010
1011 /* Neon opcode table: This does not encode the top byte -- that is
1012 checked by the print_insn_neon routine, as it depends on whether we are
1013 doing thumb32 or arm32 disassembly. */
1014
1015 /* print_insn_neon recognizes the following format control codes:
1016
1017 %% %
1018
1019 %c print condition code
1020 %u print condition code (unconditional in ARM mode,
1021 UNPREDICTABLE if not AL in Thumb)
1022 %A print v{st,ld}[1234] operands
1023 %B print v{st,ld}[1234] any one operands
1024 %C print v{st,ld}[1234] single->all operands
1025 %D print scalar
1026 %E print vmov, vmvn, vorr, vbic encoded constant
1027 %F print vtbl,vtbx register list
1028
1029 %<bitfield>r print as an ARM register
1030 %<bitfield>d print the bitfield in decimal
1031 %<bitfield>e print the 2^N - bitfield in decimal
1032 %<bitfield>D print as a NEON D register
1033 %<bitfield>Q print as a NEON Q register
1034 %<bitfield>R print as a NEON D or Q register
1035 %<bitfield>Sn print byte scaled width limited by n
1036 %<bitfield>Tn print short scaled width limited by n
1037 %<bitfield>Un print long scaled width limited by n
1038
1039 %<bitfield>'c print specified char iff bitfield is all ones
1040 %<bitfield>`c print specified char iff bitfield is all zeroes
1041 %<bitfield>?ab... select from array of values in big endian order. */
1042
1043 static const struct opcode32 neon_opcodes[] =
1044 {
1045 /* Extract. */
1046 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1047 0xf2b00840, 0xffb00850,
1048 "vext%c.8 %12-15,22R, %16-19,7R, %0-3,5R, %8-11d"},
1049 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1050 0xf2b00000, 0xffb00810,
1051 "vext%c.8 %12-15,22R, %16-19,7R, %0-3,5R, %8-11d"},
1052
1053 /* Move data element to all lanes. */
1054 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1055 0xf3b40c00, 0xffb70f90, "vdup%c.32 %12-15,22R, %0-3,5D[%19d]"},
1056 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1057 0xf3b20c00, 0xffb30f90, "vdup%c.16 %12-15,22R, %0-3,5D[%18-19d]"},
1058 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1059 0xf3b10c00, 0xffb10f90, "vdup%c.8 %12-15,22R, %0-3,5D[%17-19d]"},
1060
1061 /* Table lookup. */
1062 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1063 0xf3b00800, 0xffb00c50, "vtbl%c.8 %12-15,22D, %F, %0-3,5D"},
1064 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1065 0xf3b00840, 0xffb00c50, "vtbx%c.8 %12-15,22D, %F, %0-3,5D"},
1066
1067 /* Half-precision conversions. */
1068 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1069 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32 %12-15,22D, %0-3,5Q"},
1070 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1071 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16 %12-15,22Q, %0-3,5D"},
1072
1073 /* NEON fused multiply add instructions. */
1074 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1075 0xf2000c10, 0xffb00f10, "vfma%c.f32 %12-15,22R, %16-19,7R, %0-3,5R"},
1076 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1077 0xf2100c10, 0xffb00f10, "vfma%c.f16 %12-15,22R, %16-19,7R, %0-3,5R"},
1078 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1079 0xf2200c10, 0xffb00f10, "vfms%c.f32 %12-15,22R, %16-19,7R, %0-3,5R"},
1080 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1081 0xf2300c10, 0xffb00f10, "vfms%c.f16 %12-15,22R, %16-19,7R, %0-3,5R"},
1082
1083 /* Two registers, miscellaneous. */
1084 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1085 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32 %12-15,22R, %0-3,5R"},
1086 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1087 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16 %12-15,22R, %0-3,5R"},
1088 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1089 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32 %12-15,22R, %0-3,5R"},
1090 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1091 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16 %12-15,22R, %0-3,5R"},
1092 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1093 0xf3b00300, 0xffbf0fd0, "aese%u.8 %12-15,22Q, %0-3,5Q"},
1094 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1095 0xf3b00340, 0xffbf0fd0, "aesd%u.8 %12-15,22Q, %0-3,5Q"},
1096 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1097 0xf3b00380, 0xffbf0fd0, "aesmc%u.8 %12-15,22Q, %0-3,5Q"},
1098 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1099 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8 %12-15,22Q, %0-3,5Q"},
1100 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1101 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32 %12-15,22Q, %0-3,5Q"},
1102 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1103 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32 %12-15,22Q, %0-3,5Q"},
1104 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1105 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32 %12-15,22Q, %0-3,5Q"},
1106 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1107 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8 %12-15,22Q, %0-3,5D"},
1108 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1109 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16 %12-15,22Q, %0-3,5D"},
1110 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1111 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32 %12-15,22Q, %0-3,5D"},
1112 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1113 0xf3b00500, 0xffbf0f90, "vcnt%c.8 %12-15,22R, %0-3,5R"},
1114 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1115 0xf3b00580, 0xffbf0f90, "vmvn%c %12-15,22R, %0-3,5R"},
1116 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1117 0xf3b20000, 0xffbf0f90, "vswp%c %12-15,22R, %0-3,5R"},
1118 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1119 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2 %12-15,22D, %0-3,5Q"},
1120 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1121 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2 %12-15,22D, %0-3,5Q"},
1122 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1123 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2 %12-15,22D, %0-3,5Q"},
1124 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1125 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2 %12-15,22D, %0-3,5Q"},
1126 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1127 0xf3b20300, 0xffb30fd0,
1128 "vshll%c.i%18-19S2 %12-15,22Q, %0-3,5D, %18-19S2"},
1129 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1130 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2 %12-15,22R, %0-3,5R"},
1131 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1132 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16 %12-15,22R, %0-3,5R"},
1133 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1134 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2 %12-15,22R, %0-3,5R"},
1135 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1136 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16 %12-15,22R, %0-3,5R"},
1137 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1138 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2 %12-15,22R, %0-3,5R"},
1139 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1140 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2 %12-15,22R, %0-3,5R"},
1141 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1142 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2 %12-15,22R, %0-3,5R"},
1143 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1144 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2 %12-15,22R, %0-3,5R"},
1145 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1146 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2 %12-15,22R, %0-3,5R"},
1147 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1148 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2 %12-15,22R, %0-3,5R"},
1149 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1150 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2 %12-15,22R, %0-3,5R"},
1151 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1152 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2 %12-15,22R, %0-3,5R"},
1153 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1154 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2 %12-15,22R, %0-3,5R"},
1155 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1156 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2 %12-15,22R, %0-3,5R"},
1157 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1158 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2 %12-15,22R, %0-3,5R, #0"},
1159 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1160 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2 %12-15,22R, %0-3,5R, #0"},
1161 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1162 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2 %12-15,22R, %0-3,5R, #0"},
1163 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1164 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2 %12-15,22R, %0-3,5R, #0"},
1165 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1166 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2 %12-15,22R, %0-3,5R, #0"},
1167 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1168 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2 %12-15,22R, %0-3,5R"},
1169 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1170 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2 %12-15,22R, %0-3,5R"},
1171 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1172 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2 %12-15,22R, %0-3,5R"},
1173 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1174 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2 %12-15,22R, %0-3,5R"},
1175 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1176 0xf3bb0600, 0xffbf0e10,
1177 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa %12-15,22R, %0-3,5R"},
1178 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1179 0xf3b70600, 0xffbf0e10,
1180 "vcvt%c.%7-8?usff16.%7-8?ffus16 %12-15,22R, %0-3,5R"},
1181
1182 /* Three registers of the same length. */
1183 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1184 0xf2000c40, 0xffb00f50, "sha1c%u.32 %12-15,22Q, %16-19,7Q, %0-3,5Q"},
1185 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1186 0xf2100c40, 0xffb00f50, "sha1p%u.32 %12-15,22Q, %16-19,7Q, %0-3,5Q"},
1187 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1188 0xf2200c40, 0xffb00f50, "sha1m%u.32 %12-15,22Q, %16-19,7Q, %0-3,5Q"},
1189 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1190 0xf2300c40, 0xffb00f50, "sha1su0%u.32 %12-15,22Q, %16-19,7Q, %0-3,5Q"},
1191 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1192 0xf3000c40, 0xffb00f50, "sha256h%u.32 %12-15,22Q, %16-19,7Q, %0-3,5Q"},
1193 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1194 0xf3100c40, 0xffb00f50, "sha256h2%u.32 %12-15,22Q, %16-19,7Q, %0-3,5Q"},
1195 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1196 0xf3200c40, 0xffb00f50, "sha256su1%u.32 %12-15,22Q, %16-19,7Q, %0-3,5Q"},
1197 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1198 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32 %12-15,22R, %16-19,7R, %0-3,5R"},
1199 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1200 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16 %12-15,22R, %16-19,7R, %0-3,5R"},
1201 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1202 0xf3200f10, 0xffb00f10, "vminnm%u.f32 %12-15,22R, %16-19,7R, %0-3,5R"},
1203 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1204 0xf3300f10, 0xffb00f10, "vminnm%u.f16 %12-15,22R, %16-19,7R, %0-3,5R"},
1205 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1206 0xf2000110, 0xffb00f10, "vand%c %12-15,22R, %16-19,7R, %0-3,5R"},
1207 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1208 0xf2100110, 0xffb00f10, "vbic%c %12-15,22R, %16-19,7R, %0-3,5R"},
1209 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1210 0xf2200110, 0xffb00f10, "vorr%c %12-15,22R, %16-19,7R, %0-3,5R"},
1211 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1212 0xf2300110, 0xffb00f10, "vorn%c %12-15,22R, %16-19,7R, %0-3,5R"},
1213 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1214 0xf3000110, 0xffb00f10, "veor%c %12-15,22R, %16-19,7R, %0-3,5R"},
1215 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1216 0xf3100110, 0xffb00f10, "vbsl%c %12-15,22R, %16-19,7R, %0-3,5R"},
1217 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1218 0xf3200110, 0xffb00f10, "vbit%c %12-15,22R, %16-19,7R, %0-3,5R"},
1219 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1220 0xf3300110, 0xffb00f10, "vbif%c %12-15,22R, %16-19,7R, %0-3,5R"},
1221 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1222 0xf2000d00, 0xffb00f10, "vadd%c.f32 %12-15,22R, %16-19,7R, %0-3,5R"},
1223 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1224 0xf2100d00, 0xffb00f10, "vadd%c.f16 %12-15,22R, %16-19,7R, %0-3,5R"},
1225 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1226 0xf2000d10, 0xffb00f10, "vmla%c.f32 %12-15,22R, %16-19,7R, %0-3,5R"},
1227 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1228 0xf2100d10, 0xffb00f10, "vmla%c.f16 %12-15,22R, %16-19,7R, %0-3,5R"},
1229 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1230 0xf2000e00, 0xffb00f10, "vceq%c.f32 %12-15,22R, %16-19,7R, %0-3,5R"},
1231 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1232 0xf2100e00, 0xffb00f10, "vceq%c.f16 %12-15,22R, %16-19,7R, %0-3,5R"},
1233 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1234 0xf2000f00, 0xffb00f10, "vmax%c.f32 %12-15,22R, %16-19,7R, %0-3,5R"},
1235 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1236 0xf2100f00, 0xffb00f10, "vmax%c.f16 %12-15,22R, %16-19,7R, %0-3,5R"},
1237 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1238 0xf2000f10, 0xffb00f10, "vrecps%c.f32 %12-15,22R, %16-19,7R, %0-3,5R"},
1239 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1240 0xf2100f10, 0xffb00f10, "vrecps%c.f16 %12-15,22R, %16-19,7R, %0-3,5R"},
1241 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1242 0xf2200d00, 0xffb00f10, "vsub%c.f32 %12-15,22R, %16-19,7R, %0-3,5R"},
1243 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1244 0xf2300d00, 0xffb00f10, "vsub%c.f16 %12-15,22R, %16-19,7R, %0-3,5R"},
1245 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1246 0xf2200d10, 0xffb00f10, "vmls%c.f32 %12-15,22R, %16-19,7R, %0-3,5R"},
1247 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1248 0xf2300d10, 0xffb00f10, "vmls%c.f16 %12-15,22R, %16-19,7R, %0-3,5R"},
1249 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1250 0xf2200f00, 0xffb00f10, "vmin%c.f32 %12-15,22R, %16-19,7R, %0-3,5R"},
1251 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1252 0xf2300f00, 0xffb00f10, "vmin%c.f16 %12-15,22R, %16-19,7R, %0-3,5R"},
1253 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1254 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32 %12-15,22R, %16-19,7R, %0-3,5R"},
1255 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1256 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16 %12-15,22R, %16-19,7R, %0-3,5R"},
1257 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1258 0xf3000d00, 0xffb00f10, "vpadd%c.f32 %12-15,22R, %16-19,7R, %0-3,5R"},
1259 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1260 0xf3100d00, 0xffb00f10, "vpadd%c.f16 %12-15,22R, %16-19,7R, %0-3,5R"},
1261 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1262 0xf3000d10, 0xffb00f10, "vmul%c.f32 %12-15,22R, %16-19,7R, %0-3,5R"},
1263 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1264 0xf3100d10, 0xffb00f10, "vmul%c.f16 %12-15,22R, %16-19,7R, %0-3,5R"},
1265 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1266 0xf3000e00, 0xffb00f10, "vcge%c.f32 %12-15,22R, %16-19,7R, %0-3,5R"},
1267 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1268 0xf3100e00, 0xffb00f10, "vcge%c.f16 %12-15,22R, %16-19,7R, %0-3,5R"},
1269 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1270 0xf3000e10, 0xffb00f10, "vacge%c.f32 %12-15,22R, %16-19,7R, %0-3,5R"},
1271 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1272 0xf3100e10, 0xffb00f10, "vacge%c.f16 %12-15,22R, %16-19,7R, %0-3,5R"},
1273 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1274 0xf3000f00, 0xffb00f10, "vpmax%c.f32 %12-15,22R, %16-19,7R, %0-3,5R"},
1275 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1276 0xf3100f00, 0xffb00f10, "vpmax%c.f16 %12-15,22R, %16-19,7R, %0-3,5R"},
1277 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1278 0xf3200d00, 0xffb00f10, "vabd%c.f32 %12-15,22R, %16-19,7R, %0-3,5R"},
1279 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1280 0xf3300d00, 0xffb00f10, "vabd%c.f16 %12-15,22R, %16-19,7R, %0-3,5R"},
1281 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1282 0xf3200e00, 0xffb00f10, "vcgt%c.f32 %12-15,22R, %16-19,7R, %0-3,5R"},
1283 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1284 0xf3300e00, 0xffb00f10, "vcgt%c.f16 %12-15,22R, %16-19,7R, %0-3,5R"},
1285 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1286 0xf3200e10, 0xffb00f10, "vacgt%c.f32 %12-15,22R, %16-19,7R, %0-3,5R"},
1287 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1288 0xf3300e10, 0xffb00f10, "vacgt%c.f16 %12-15,22R, %16-19,7R, %0-3,5R"},
1289 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1290 0xf3200f00, 0xffb00f10, "vpmin%c.f32 %12-15,22R, %16-19,7R, %0-3,5R"},
1291 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1292 0xf3300f00, 0xffb00f10, "vpmin%c.f16 %12-15,22R, %16-19,7R, %0-3,5R"},
1293 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1294 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3 %12-15,22R, %16-19,7R, %0-3,5R"},
1295 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1296 0xf2000810, 0xff800f10, "vtst%c.%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R"},
1297 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1298 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R"},
1299 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1300 0xf2000b00, 0xff800f10,
1301 "vqdmulh%c.s%20-21S6 %12-15,22R, %16-19,7R, %0-3,5R"},
1302 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1303 0xf2000b10, 0xff800f10,
1304 "vpadd%c.i%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R"},
1305 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1306 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3 %12-15,22R, %16-19,7R, %0-3,5R"},
1307 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1308 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R"},
1309 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1310 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R"},
1311 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1312 0xf3000b00, 0xff800f10,
1313 "vqrdmulh%c.s%20-21S6 %12-15,22R, %16-19,7R, %0-3,5R"},
1314 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1315 0xf2000000, 0xfe800f10,
1316 "vhadd%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R"},
1317 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1318 0xf2000010, 0xfe800f10,
1319 "vqadd%c.%24?us%20-21S3 %12-15,22R, %16-19,7R, %0-3,5R"},
1320 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1321 0xf2000100, 0xfe800f10,
1322 "vrhadd%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R"},
1323 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1324 0xf2000200, 0xfe800f10,
1325 "vhsub%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R"},
1326 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1327 0xf2000210, 0xfe800f10,
1328 "vqsub%c.%24?us%20-21S3 %12-15,22R, %16-19,7R, %0-3,5R"},
1329 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1330 0xf2000300, 0xfe800f10,
1331 "vcgt%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R"},
1332 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1333 0xf2000310, 0xfe800f10,
1334 "vcge%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R"},
1335 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1336 0xf2000400, 0xfe800f10,
1337 "vshl%c.%24?us%20-21S3 %12-15,22R, %0-3,5R, %16-19,7R"},
1338 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1339 0xf2000410, 0xfe800f10,
1340 "vqshl%c.%24?us%20-21S3 %12-15,22R, %0-3,5R, %16-19,7R"},
1341 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1342 0xf2000500, 0xfe800f10,
1343 "vrshl%c.%24?us%20-21S3 %12-15,22R, %0-3,5R, %16-19,7R"},
1344 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1345 0xf2000510, 0xfe800f10,
1346 "vqrshl%c.%24?us%20-21S3 %12-15,22R, %0-3,5R, %16-19,7R"},
1347 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1348 0xf2000600, 0xfe800f10,
1349 "vmax%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R"},
1350 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1351 0xf2000610, 0xfe800f10,
1352 "vmin%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R"},
1353 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1354 0xf2000700, 0xfe800f10,
1355 "vabd%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R"},
1356 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1357 0xf2000710, 0xfe800f10,
1358 "vaba%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R"},
1359 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1360 0xf2000910, 0xfe800f10,
1361 "vmul%c.%24?pi%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R"},
1362 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1363 0xf2000a00, 0xfe800f10,
1364 "vpmax%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R"},
1365 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1366 0xf2000a10, 0xfe800f10,
1367 "vpmin%c.%24?us%20-21S2 %12-15,22R, %16-19,7R, %0-3,5R"},
1368 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1369 0xf3000b10, 0xff800f10,
1370 "vqrdmlah%c.s%20-21S6 %12-15,22R, %16-19,7R, %0-3,5R"},
1371 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1372 0xf3000c10, 0xff800f10,
1373 "vqrdmlsh%c.s%20-21S6 %12-15,22R, %16-19,7R, %0-3,5R"},
1374
1375 /* One register and an immediate value. */
1376 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1377 0xf2800e10, 0xfeb80fb0, "vmov%c.i8 %12-15,22R, %E"},
1378 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1379 0xf2800e30, 0xfeb80fb0, "vmov%c.i64 %12-15,22R, %E"},
1380 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1381 0xf2800f10, 0xfeb80fb0, "vmov%c.f32 %12-15,22R, %E"},
1382 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1383 0xf2800810, 0xfeb80db0, "vmov%c.i16 %12-15,22R, %E"},
1384 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1385 0xf2800830, 0xfeb80db0, "vmvn%c.i16 %12-15,22R, %E"},
1386 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1387 0xf2800910, 0xfeb80db0, "vorr%c.i16 %12-15,22R, %E"},
1388 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1389 0xf2800930, 0xfeb80db0, "vbic%c.i16 %12-15,22R, %E"},
1390 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1391 0xf2800c10, 0xfeb80eb0, "vmov%c.i32 %12-15,22R, %E"},
1392 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1393 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32 %12-15,22R, %E"},
1394 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1395 0xf2800110, 0xfeb809b0, "vorr%c.i32 %12-15,22R, %E"},
1396 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1397 0xf2800130, 0xfeb809b0, "vbic%c.i32 %12-15,22R, %E"},
1398 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1399 0xf2800010, 0xfeb808b0, "vmov%c.i32 %12-15,22R, %E"},
1400 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1401 0xf2800030, 0xfeb808b0, "vmvn%c.i32 %12-15,22R, %E"},
1402
1403 /* Two registers and a shift amount. */
1404 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1405 0xf2880810, 0xffb80fd0, "vshrn%c.i16 %12-15,22D, %0-3,5Q, %16-18e"},
1406 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1407 0xf2880850, 0xffb80fd0, "vrshrn%c.i16 %12-15,22D, %0-3,5Q, %16-18e"},
1408 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1409 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16 %12-15,22D, %0-3,5Q, %16-18e"},
1410 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1411 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16 %12-15,22D, %0-3,5Q, %16-18e"},
1412 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1413 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16 %12-15,22D, %0-3,5Q, %16-18e"},
1414 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1415 0xf2880950, 0xfeb80fd0,
1416 "vqrshrn%c.%24?us16 %12-15,22D, %0-3,5Q, %16-18e"},
1417 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1418 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8 %12-15,22Q, %0-3,5D, %16-18d"},
1419 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1420 0xf2900810, 0xffb00fd0, "vshrn%c.i32 %12-15,22D, %0-3,5Q, %16-19e"},
1421 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1422 0xf2900850, 0xffb00fd0, "vrshrn%c.i32 %12-15,22D, %0-3,5Q, %16-19e"},
1423 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1424 0xf2880510, 0xffb80f90, "vshl%c.%24?us8 %12-15,22R, %0-3,5R, %16-18d"},
1425 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1426 0xf3880410, 0xffb80f90, "vsri%c.8 %12-15,22R, %0-3,5R, %16-18e"},
1427 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1428 0xf3880510, 0xffb80f90, "vsli%c.8 %12-15,22R, %0-3,5R, %16-18d"},
1429 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1430 0xf3880610, 0xffb80f90, "vqshlu%c.s8 %12-15,22R, %0-3,5R, %16-18d"},
1431 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1432 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32 %12-15,22D, %0-3,5Q, %16-19e"},
1433 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1434 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32 %12-15,22D, %0-3,5Q, %16-19e"},
1435 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1436 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32 %12-15,22D, %0-3,5Q, %16-19e"},
1437 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1438 0xf2900950, 0xfeb00fd0,
1439 "vqrshrn%c.%24?us32 %12-15,22D, %0-3,5Q, %16-19e"},
1440 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1441 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16 %12-15,22Q, %0-3,5D, %16-19d"},
1442 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1443 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8 %12-15,22R, %0-3,5R, %16-18e"},
1444 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1445 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8 %12-15,22R, %0-3,5R, %16-18e"},
1446 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1447 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8 %12-15,22R, %0-3,5R, %16-18e"},
1448 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1449 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8 %12-15,22R, %0-3,5R, %16-18e"},
1450 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1451 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8 %12-15,22R, %0-3,5R, %16-18d"},
1452 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1453 0xf2a00810, 0xffa00fd0, "vshrn%c.i64 %12-15,22D, %0-3,5Q, %16-20e"},
1454 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1455 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64 %12-15,22D, %0-3,5Q, %16-20e"},
1456 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1457 0xf2900510, 0xffb00f90, "vshl%c.%24?us16 %12-15,22R, %0-3,5R, %16-19d"},
1458 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1459 0xf3900410, 0xffb00f90, "vsri%c.16 %12-15,22R, %0-3,5R, %16-19e"},
1460 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1461 0xf3900510, 0xffb00f90, "vsli%c.16 %12-15,22R, %0-3,5R, %16-19d"},
1462 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1463 0xf3900610, 0xffb00f90, "vqshlu%c.s16 %12-15,22R, %0-3,5R, %16-19d"},
1464 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1465 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32 %12-15,22Q, %0-3,5D, %16-20d"},
1466 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1467 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16 %12-15,22R, %0-3,5R, %16-19e"},
1468 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1469 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16 %12-15,22R, %0-3,5R, %16-19e"},
1470 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1471 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16 %12-15,22R, %0-3,5R, %16-19e"},
1472 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1473 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16 %12-15,22R, %0-3,5R, %16-19e"},
1474 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1475 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16 %12-15,22R, %0-3,5R, %16-19d"},
1476 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1477 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64 %12-15,22D, %0-3,5Q, %16-20e"},
1478 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1479 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64 %12-15,22D, %0-3,5Q, %16-20e"},
1480 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1481 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64 %12-15,22D, %0-3,5Q, %16-20e"},
1482 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1483 0xf2a00950, 0xfea00fd0,
1484 "vqrshrn%c.%24?us64 %12-15,22D, %0-3,5Q, %16-20e"},
1485 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1486 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32 %12-15,22R, %0-3,5R, %16-20d"},
1487 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1488 0xf3a00410, 0xffa00f90, "vsri%c.32 %12-15,22R, %0-3,5R, %16-20e"},
1489 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1490 0xf3a00510, 0xffa00f90, "vsli%c.32 %12-15,22R, %0-3,5R, %16-20d"},
1491 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1492 0xf3a00610, 0xffa00f90, "vqshlu%c.s32 %12-15,22R, %0-3,5R, %16-20d"},
1493 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1494 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32 %12-15,22R, %0-3,5R, %16-20e"},
1495 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1496 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32 %12-15,22R, %0-3,5R, %16-20e"},
1497 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1498 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32 %12-15,22R, %0-3,5R, %16-20e"},
1499 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1500 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32 %12-15,22R, %0-3,5R, %16-20e"},
1501 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1502 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32 %12-15,22R, %0-3,5R, %16-20d"},
1503 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1504 0xf2800590, 0xff800f90, "vshl%c.%24?us64 %12-15,22R, %0-3,5R, %16-21d"},
1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506 0xf3800490, 0xff800f90, "vsri%c.64 %12-15,22R, %0-3,5R, %16-21e"},
1507 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1508 0xf3800590, 0xff800f90, "vsli%c.64 %12-15,22R, %0-3,5R, %16-21d"},
1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1510 0xf3800690, 0xff800f90, "vqshlu%c.s64 %12-15,22R, %0-3,5R, %16-21d"},
1511 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1512 0xf2800090, 0xfe800f90, "vshr%c.%24?us64 %12-15,22R, %0-3,5R, %16-21e"},
1513 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1514 0xf2800190, 0xfe800f90, "vsra%c.%24?us64 %12-15,22R, %0-3,5R, %16-21e"},
1515 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1516 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64 %12-15,22R, %0-3,5R, %16-21e"},
1517 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1518 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64 %12-15,22R, %0-3,5R, %16-21e"},
1519 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1520 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64 %12-15,22R, %0-3,5R, %16-21d"},
1521 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1522 0xf2a00e10, 0xfea00e90,
1523 "vcvt%c.%24,8?usff32.%24,8?ffus32 %12-15,22R, %0-3,5R, %16-20e"},
1524 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1525 0xf2a00c10, 0xfea00e90,
1526 "vcvt%c.%24,8?usff16.%24,8?ffus16 %12-15,22R, %0-3,5R, %16-20e"},
1527
1528 /* Three registers of different lengths. */
1529 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1530 0xf2a00e00, 0xfeb00f50, "vmull%c.p64 %12-15,22Q, %16-19,7D, %0-3,5D"},
1531 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1532 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0 %12-15,22Q, %16-19,7D, %0-3,5D"},
1533 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1534 0xf2800400, 0xff800f50,
1535 "vaddhn%c.i%20-21T2 %12-15,22D, %16-19,7Q, %0-3,5Q"},
1536 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1537 0xf2800600, 0xff800f50,
1538 "vsubhn%c.i%20-21T2 %12-15,22D, %16-19,7Q, %0-3,5Q"},
1539 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1540 0xf2800900, 0xff800f50,
1541 "vqdmlal%c.s%20-21S6 %12-15,22Q, %16-19,7D, %0-3,5D"},
1542 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1543 0xf2800b00, 0xff800f50,
1544 "vqdmlsl%c.s%20-21S6 %12-15,22Q, %16-19,7D, %0-3,5D"},
1545 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1546 0xf2800d00, 0xff800f50,
1547 "vqdmull%c.s%20-21S6 %12-15,22Q, %16-19,7D, %0-3,5D"},
1548 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1549 0xf3800400, 0xff800f50,
1550 "vraddhn%c.i%20-21T2 %12-15,22D, %16-19,7Q, %0-3,5Q"},
1551 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1552 0xf3800600, 0xff800f50,
1553 "vrsubhn%c.i%20-21T2 %12-15,22D, %16-19,7Q, %0-3,5Q"},
1554 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1555 0xf2800000, 0xfe800f50,
1556 "vaddl%c.%24?us%20-21S2 %12-15,22Q, %16-19,7D, %0-3,5D"},
1557 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1558 0xf2800100, 0xfe800f50,
1559 "vaddw%c.%24?us%20-21S2 %12-15,22Q, %16-19,7Q, %0-3,5D"},
1560 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1561 0xf2800200, 0xfe800f50,
1562 "vsubl%c.%24?us%20-21S2 %12-15,22Q, %16-19,7D, %0-3,5D"},
1563 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1564 0xf2800300, 0xfe800f50,
1565 "vsubw%c.%24?us%20-21S2 %12-15,22Q, %16-19,7Q, %0-3,5D"},
1566 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1567 0xf2800500, 0xfe800f50,
1568 "vabal%c.%24?us%20-21S2 %12-15,22Q, %16-19,7D, %0-3,5D"},
1569 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1570 0xf2800700, 0xfe800f50,
1571 "vabdl%c.%24?us%20-21S2 %12-15,22Q, %16-19,7D, %0-3,5D"},
1572 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1573 0xf2800800, 0xfe800f50,
1574 "vmlal%c.%24?us%20-21S2 %12-15,22Q, %16-19,7D, %0-3,5D"},
1575 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1576 0xf2800a00, 0xfe800f50,
1577 "vmlsl%c.%24?us%20-21S2 %12-15,22Q, %16-19,7D, %0-3,5D"},
1578 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1579 0xf2800c00, 0xfe800f50,
1580 "vmull%c.%24?us%20-21S2 %12-15,22Q, %16-19,7D, %0-3,5D"},
1581
1582 /* Two registers and a scalar. */
1583 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1584 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6 %12-15,22D, %16-19,7D, %D"},
1585 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1586 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa %12-15,22D, %16-19,7D, %D"},
1587 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1588 0xf2900140, 0xffb00f50, "vmla%c.f16 %12-15,22D, %16-19,7D, %D"},
1589 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1590 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6 %12-15,22Q, %16-19,7D, %D"},
1591 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1592 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6 %12-15,22D, %16-19,7D, %D"},
1593 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1594 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6 %12-15,22D, %16-19,7D, %D"},
1595 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1596 0xf2900540, 0xffb00f50, "vmls%c.f16 %12-15,22D, %16-19,7D, %D"},
1597 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1598 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6 %12-15,22Q, %16-19,7D, %D"},
1599 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1600 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6 %12-15,22D, %16-19,7D, %D"},
1601 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1602 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa %12-15,22D, %16-19,7D, %D"},
1603 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1604 0xf2900940, 0xffb00f50, "vmul%c.f16 %12-15,22D, %16-19,7D, %D"},
1605 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1606 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6 %12-15,22Q, %16-19,7D, %D"},
1607 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1608 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6 %12-15,22D, %16-19,7D, %D"},
1609 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1610 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6 %12-15,22D, %16-19,7D, %D"},
1611 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1612 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6 %12-15,22Q, %16-19,7Q, %D"},
1613 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1614 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa %12-15,22Q, %16-19,7Q, %D"},
1615 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1616 0xf3900140, 0xffb00f50, "vmla%c.f16 %12-15,22Q, %16-19,7Q, %D"},
1617 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1618 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6 %12-15,22Q, %16-19,7Q, %D"},
1619 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1620 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa %12-15,22Q, %16-19,7Q, %D"},
1621 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1622 0xf3900540, 0xffb00f50, "vmls%c.f16 %12-15,22Q, %16-19,7Q, %D"},
1623 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1624 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6 %12-15,22Q, %16-19,7Q, %D"},
1625 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1626 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa %12-15,22Q, %16-19,7Q, %D"},
1627 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1628 0xf3900940, 0xffb00f50, "vmul%c.f16 %12-15,22Q, %16-19,7Q, %D"},
1629 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1630 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6 %12-15,22Q, %16-19,7Q, %D"},
1631 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1632 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6 %12-15,22Q, %16-19,7Q, %D"},
1633 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1634 0xf2800240, 0xfe800f50,
1635 "vmlal%c.%24?us%20-21S6 %12-15,22Q, %16-19,7D, %D"},
1636 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1637 0xf2800640, 0xfe800f50,
1638 "vmlsl%c.%24?us%20-21S6 %12-15,22Q, %16-19,7D, %D"},
1639 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1640 0xf2800a40, 0xfe800f50,
1641 "vmull%c.%24?us%20-21S6 %12-15,22Q, %16-19,7D, %D"},
1642 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1643 0xf2800e40, 0xff800f50,
1644 "vqrdmlah%c.s%20-21S6 %12-15,22D, %16-19,7D, %D"},
1645 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1646 0xf2800f40, 0xff800f50,
1647 "vqrdmlsh%c.s%20-21S6 %12-15,22D, %16-19,7D, %D"},
1648 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1649 0xf3800e40, 0xff800f50,
1650 "vqrdmlah%c.s%20-21S6 %12-15,22Q, %16-19,7Q, %D"},
1651 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1652 0xf3800f40, 0xff800f50,
1653 "vqrdmlsh%c.s%20-21S6 %12-15,22Q, %16-19,7Q, %D"
1654 },
1655
1656 /* Element and structure load/store. */
1657 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1658 0xf4a00fc0, 0xffb00fc0, "vld4%c.32 %C"},
1659 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1660 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2 %C"},
1661 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1662 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2 %C"},
1663 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1664 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2 %C"},
1665 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1666 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2 %C"},
1667 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1668 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3 %A"},
1669 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1670 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2 %A"},
1671 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1672 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2 %A"},
1673 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1674 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2 %A"},
1675 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1676 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3 %A"},
1677 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1678 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3 %A"},
1679 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1680 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2 %A"},
1681 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1682 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2 %A"},
1683 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1684 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3 %A"},
1685 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1686 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2 %A"},
1687 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1688 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2 %B"},
1689 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1690 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2 %B"},
1691 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1692 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2 %B"},
1693 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1694 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2 %B"},
1695
1696 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
1697 };
1698
1699 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
1700 ordered: they must be searched linearly from the top to obtain a correct
1701 match. */
1702
1703 /* print_insn_arm recognizes the following format control codes:
1704
1705 %% %
1706
1707 %a print address for ldr/str instruction
1708 %s print address for ldr/str halfword/signextend instruction
1709 %S like %s but allow UNPREDICTABLE addressing
1710 %b print branch destination
1711 %c print condition code (always bits 28-31)
1712 %m print register mask for ldm/stm instruction
1713 %o print operand2 (immediate or register + shift)
1714 %p print 'p' iff bits 12-15 are 15
1715 %t print 't' iff bit 21 set and bit 24 clear
1716 %B print arm BLX(1) destination
1717 %C print the PSR sub type.
1718 %U print barrier type.
1719 %P print address for pli instruction.
1720
1721 %<bitfield>r print as an ARM register
1722 %<bitfield>T print as an ARM register + 1
1723 %<bitfield>R as %r but r15 is UNPREDICTABLE
1724 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
1725 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
1726 %<bitfield>d print the bitfield in decimal
1727 %<bitfield>W print the bitfield plus one in decimal
1728 %<bitfield>x print the bitfield in hex
1729 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
1730
1731 %<bitfield>'c print specified char iff bitfield is all ones
1732 %<bitfield>`c print specified char iff bitfield is all zeroes
1733 %<bitfield>?ab... select from array of values in big endian order
1734
1735 %e print arm SMI operand (bits 0..7,8..19).
1736 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
1737 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
1738 %R print the SPSR/CPSR or banked register of an MRS. */
1739
1740 static const struct opcode32 arm_opcodes[] =
1741 {
1742 /* ARM instructions. */
1743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1744 0xe1a00000, 0xffffffff, "nop ; (mov r0, r0)"},
1745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1746 0xe7f000f0, 0xfff000f0, "udf %e"},
1747
1748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
1749 0x012FFF10, 0x0ffffff0, "bx%c %0-3r"},
1750 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1751 0x00000090, 0x0fe000f0, "mul%20's%c %16-19R, %0-3R, %8-11R"},
1752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1753 0x00200090, 0x0fe000f0, "mla%20's%c %16-19R, %0-3R, %8-11R, %12-15R"},
1754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
1755 0x01000090, 0x0fb00ff0, "swp%22'b%c %12-15RU, %0-3Ru, [%16-19RuU]"},
1756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1757 0x00800090, 0x0fa000f0,
1758 "%22?sumull%20's%c %12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1760 0x00a00090, 0x0fa000f0,
1761 "%22?sumlal%20's%c %12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1762
1763 /* V8.2 RAS extension instructions. */
1764 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
1765 0xe320f010, 0xffffffff, "esb"},
1766
1767 /* V8 instructions. */
1768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1769 0x0320f005, 0x0fffffff, "sevl"},
1770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1771 0xe1000070, 0xfff000f0, "hlt 0x%16-19X%12-15X%8-11X%0-3X"},
1772 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
1773 0x01800e90, 0x0ff00ff0, "stlex%c %12-15r, %0-3r, [%16-19R]"},
1774 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1775 0x01900e9f, 0x0ff00fff, "ldaex%c %12-15r, [%16-19R]"},
1776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1777 0x01a00e90, 0x0ff00ff0, "stlexd%c %12-15r, %0-3r, %0-3T, [%16-19R]"},
1778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1779 0x01b00e9f, 0x0ff00fff, "ldaexd%c %12-15r, %12-15T, [%16-19R]"},
1780 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1781 0x01c00e90, 0x0ff00ff0, "stlexb%c %12-15r, %0-3r, [%16-19R]"},
1782 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1783 0x01d00e9f, 0x0ff00fff, "ldaexb%c %12-15r, [%16-19R]"},
1784 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1785 0x01e00e90, 0x0ff00ff0, "stlexh%c %12-15r, %0-3r, [%16-19R]"},
1786 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1787 0x01f00e9f, 0x0ff00fff, "ldaexh%c %12-15r, [%16-19R]"},
1788 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1789 0x0180fc90, 0x0ff0fff0, "stl%c %0-3r, [%16-19R]"},
1790 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1791 0x01900c9f, 0x0ff00fff, "lda%c %12-15r, [%16-19R]"},
1792 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1793 0x01c0fc90, 0x0ff0fff0, "stlb%c %0-3r, [%16-19R]"},
1794 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1795 0x01d00c9f, 0x0ff00fff, "ldab%c %12-15r, [%16-19R]"},
1796 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1797 0x01e0fc90, 0x0ff0fff0, "stlh%c %0-3r, [%16-19R]"},
1798 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1799 0x01f00c9f, 0x0ff00fff, "ldah%c %12-15r, [%16-19R]"},
1800 /* CRC32 instructions. */
1801 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1802 0xe1000040, 0xfff00ff0, "crc32b %12-15R, %16-19R, %0-3R"},
1803 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1804 0xe1200040, 0xfff00ff0, "crc32h %12-15R, %16-19R, %0-3R"},
1805 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1806 0xe1400040, 0xfff00ff0, "crc32w %12-15R, %16-19R, %0-3R"},
1807 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1808 0xe1000240, 0xfff00ff0, "crc32cb %12-15R, %16-19R, %0-3R"},
1809 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1810 0xe1200240, 0xfff00ff0, "crc32ch %12-15R, %16-19R, %0-3R"},
1811 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1812 0xe1400240, 0xfff00ff0, "crc32cw %12-15R, %16-19R, %0-3R"},
1813
1814 /* Privileged Access Never extension instructions. */
1815 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
1816 0xf1100000, 0xfffffdff, "setpan %9-9d"},
1817
1818 /* Virtualization Extension instructions. */
1819 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
1820 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c %e"},
1821
1822 /* Integer Divide Extension instructions. */
1823 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1824 0x0710f010, 0x0ff0f0f0, "sdiv%c %16-19r, %0-3r, %8-11r"},
1825 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1826 0x0730f010, 0x0ff0f0f0, "udiv%c %16-19r, %0-3r, %8-11r"},
1827
1828 /* MP Extension instructions. */
1829 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw %a"},
1830
1831 /* V7 instructions. */
1832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli %P"},
1833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c %0-3d"},
1834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb %U"},
1835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb %U"},
1836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb %U"},
1837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb %U"},
1838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb %U"},
1839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
1840 0x0320f000, 0x0fffffff, "nop%c {%0-7d}"},
1841
1842 /* ARM V6T2 instructions. */
1843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1844 0x07c0001f, 0x0fe0007f, "bfc%c %12-15R, %E"},
1845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1846 0x07c00010, 0x0fe00070, "bfi%c %12-15R, %0-3r, %E"},
1847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1848 0x00600090, 0x0ff000f0, "mls%c %16-19R, %0-3R, %8-11R, %12-15R"},
1849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1850 0x002000b0, 0x0f3000f0, "strht%c %12-15R, %S"},
1851
1852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1853 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
1854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1855 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c %12-15R, %S"},
1856
1857 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
1858 0x03000000, 0x0ff00000, "movw%c %12-15R, %V"},
1859 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
1860 0x03400000, 0x0ff00000, "movt%c %12-15R, %V"},
1861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1862 0x06ff0f30, 0x0fff0ff0, "rbit%c %12-15R, %0-3R"},
1863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1864 0x07a00050, 0x0fa00070, "%22?usbfx%c %12-15r, %0-3r, %7-11d, #%16-20W"},
1865
1866 /* ARM Security extension instructions. */
1867 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
1868 0x01600070, 0x0ff000f0, "smc%c %e"},
1869
1870 /* ARM V6K instructions. */
1871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1872 0xf57ff01f, 0xffffffff, "clrex"},
1873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1874 0x01d00f9f, 0x0ff00fff, "ldrexb%c %12-15R, [%16-19R]"},
1875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1876 0x01b00f9f, 0x0ff00fff, "ldrexd%c %12-15r, [%16-19R]"},
1877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1878 0x01f00f9f, 0x0ff00fff, "ldrexh%c %12-15R, [%16-19R]"},
1879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1880 0x01c00f90, 0x0ff00ff0, "strexb%c %12-15R, %0-3R, [%16-19R]"},
1881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1882 0x01a00f90, 0x0ff00ff0, "strexd%c %12-15R, %0-3r, [%16-19R]"},
1883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1884 0x01e00f90, 0x0ff00ff0, "strexh%c %12-15R, %0-3R, [%16-19R]"},
1885
1886 /* ARM V6K NOP hints. */
1887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1888 0x0320f001, 0x0fffffff, "yield%c"},
1889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1890 0x0320f002, 0x0fffffff, "wfe%c"},
1891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1892 0x0320f003, 0x0fffffff, "wfi%c"},
1893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1894 0x0320f004, 0x0fffffff, "sev%c"},
1895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1896 0x0320f000, 0x0fffff00, "nop%c {%0-7d}"},
1897
1898 /* ARM V6 instructions. */
1899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1900 0xf1080000, 0xfffffe3f, "cpsie %8'a%7'i%6'f"},
1901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1902 0xf10a0000, 0xfffffe20, "cpsie %8'a%7'i%6'f,%0-4d"},
1903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1904 0xf10C0000, 0xfffffe3f, "cpsid %8'a%7'i%6'f"},
1905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1906 0xf10e0000, 0xfffffe20, "cpsid %8'a%7'i%6'f,%0-4d"},
1907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1908 0xf1000000, 0xfff1fe20, "cps %0-4d"},
1909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1910 0x06800010, 0x0ff00ff0, "pkhbt%c %12-15R, %16-19R, %0-3R"},
1911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1912 0x06800010, 0x0ff00070, "pkhbt%c %12-15R, %16-19R, %0-3R, lsl %7-11d"},
1913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1914 0x06800050, 0x0ff00ff0, "pkhtb%c %12-15R, %16-19R, %0-3R, asr #32"},
1915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1916 0x06800050, 0x0ff00070, "pkhtb%c %12-15R, %16-19R, %0-3R, asr %7-11d"},
1917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1918 0x01900f9f, 0x0ff00fff, "ldrex%c r%12-15d, [%16-19R]"},
1919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1920 0x06200f10, 0x0ff00ff0, "qadd16%c %12-15R, %16-19R, %0-3R"},
1921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1922 0x06200f90, 0x0ff00ff0, "qadd8%c %12-15R, %16-19R, %0-3R"},
1923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1924 0x06200f30, 0x0ff00ff0, "qasx%c %12-15R, %16-19R, %0-3R"},
1925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1926 0x06200f70, 0x0ff00ff0, "qsub16%c %12-15R, %16-19R, %0-3R"},
1927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1928 0x06200ff0, 0x0ff00ff0, "qsub8%c %12-15R, %16-19R, %0-3R"},
1929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1930 0x06200f50, 0x0ff00ff0, "qsax%c %12-15R, %16-19R, %0-3R"},
1931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1932 0x06100f10, 0x0ff00ff0, "sadd16%c %12-15R, %16-19R, %0-3R"},
1933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1934 0x06100f90, 0x0ff00ff0, "sadd8%c %12-15R, %16-19R, %0-3R"},
1935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1936 0x06100f30, 0x0ff00ff0, "sasx%c %12-15R, %16-19R, %0-3R"},
1937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1938 0x06300f10, 0x0ff00ff0, "shadd16%c %12-15R, %16-19R, %0-3R"},
1939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1940 0x06300f90, 0x0ff00ff0, "shadd8%c %12-15R, %16-19R, %0-3R"},
1941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1942 0x06300f30, 0x0ff00ff0, "shasx%c %12-15R, %16-19R, %0-3R"},
1943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1944 0x06300f70, 0x0ff00ff0, "shsub16%c %12-15R, %16-19R, %0-3R"},
1945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1946 0x06300ff0, 0x0ff00ff0, "shsub8%c %12-15R, %16-19R, %0-3R"},
1947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1948 0x06300f50, 0x0ff00ff0, "shsax%c %12-15R, %16-19R, %0-3R"},
1949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1950 0x06100f70, 0x0ff00ff0, "ssub16%c %12-15R, %16-19R, %0-3R"},
1951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1952 0x06100ff0, 0x0ff00ff0, "ssub8%c %12-15R, %16-19R, %0-3R"},
1953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1954 0x06100f50, 0x0ff00ff0, "ssax%c %12-15R, %16-19R, %0-3R"},
1955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1956 0x06500f10, 0x0ff00ff0, "uadd16%c %12-15R, %16-19R, %0-3R"},
1957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1958 0x06500f90, 0x0ff00ff0, "uadd8%c %12-15R, %16-19R, %0-3R"},
1959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1960 0x06500f30, 0x0ff00ff0, "uasx%c %12-15R, %16-19R, %0-3R"},
1961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1962 0x06700f10, 0x0ff00ff0, "uhadd16%c %12-15R, %16-19R, %0-3R"},
1963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1964 0x06700f90, 0x0ff00ff0, "uhadd8%c %12-15R, %16-19R, %0-3R"},
1965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1966 0x06700f30, 0x0ff00ff0, "uhasx%c %12-15R, %16-19R, %0-3R"},
1967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1968 0x06700f70, 0x0ff00ff0, "uhsub16%c %12-15R, %16-19R, %0-3R"},
1969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1970 0x06700ff0, 0x0ff00ff0, "uhsub8%c %12-15R, %16-19R, %0-3R"},
1971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1972 0x06700f50, 0x0ff00ff0, "uhsax%c %12-15R, %16-19R, %0-3R"},
1973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1974 0x06600f10, 0x0ff00ff0, "uqadd16%c %12-15R, %16-19R, %0-3R"},
1975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1976 0x06600f90, 0x0ff00ff0, "uqadd8%c %12-15R, %16-19R, %0-3R"},
1977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1978 0x06600f30, 0x0ff00ff0, "uqasx%c %12-15R, %16-19R, %0-3R"},
1979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1980 0x06600f70, 0x0ff00ff0, "uqsub16%c %12-15R, %16-19R, %0-3R"},
1981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1982 0x06600ff0, 0x0ff00ff0, "uqsub8%c %12-15R, %16-19R, %0-3R"},
1983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1984 0x06600f50, 0x0ff00ff0, "uqsax%c %12-15R, %16-19R, %0-3R"},
1985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1986 0x06500f70, 0x0ff00ff0, "usub16%c %12-15R, %16-19R, %0-3R"},
1987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1988 0x06500ff0, 0x0ff00ff0, "usub8%c %12-15R, %16-19R, %0-3R"},
1989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1990 0x06500f50, 0x0ff00ff0, "usax%c %12-15R, %16-19R, %0-3R"},
1991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1992 0x06bf0f30, 0x0fff0ff0, "rev%c %12-15R, %0-3R"},
1993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1994 0x06bf0fb0, 0x0fff0ff0, "rev16%c %12-15R, %0-3R"},
1995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1996 0x06ff0fb0, 0x0fff0ff0, "revsh%c %12-15R, %0-3R"},
1997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1998 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba %16-19r%21'!"},
1999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2000 0x06bf0070, 0x0fff0ff0, "sxth%c %12-15R, %0-3R"},
2001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2002 0x06bf0470, 0x0fff0ff0, "sxth%c %12-15R, %0-3R, ror #8"},
2003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2004 0x06bf0870, 0x0fff0ff0, "sxth%c %12-15R, %0-3R, ror #16"},
2005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2006 0x06bf0c70, 0x0fff0ff0, "sxth%c %12-15R, %0-3R, ror #24"},
2007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2008 0x068f0070, 0x0fff0ff0, "sxtb16%c %12-15R, %0-3R"},
2009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2010 0x068f0470, 0x0fff0ff0, "sxtb16%c %12-15R, %0-3R, ror #8"},
2011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2012 0x068f0870, 0x0fff0ff0, "sxtb16%c %12-15R, %0-3R, ror #16"},
2013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2014 0x068f0c70, 0x0fff0ff0, "sxtb16%c %12-15R, %0-3R, ror #24"},
2015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2016 0x06af0070, 0x0fff0ff0, "sxtb%c %12-15R, %0-3R"},
2017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2018 0x06af0470, 0x0fff0ff0, "sxtb%c %12-15R, %0-3R, ror #8"},
2019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2020 0x06af0870, 0x0fff0ff0, "sxtb%c %12-15R, %0-3R, ror #16"},
2021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2022 0x06af0c70, 0x0fff0ff0, "sxtb%c %12-15R, %0-3R, ror #24"},
2023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2024 0x06ff0070, 0x0fff0ff0, "uxth%c %12-15R, %0-3R"},
2025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2026 0x06ff0470, 0x0fff0ff0, "uxth%c %12-15R, %0-3R, ror #8"},
2027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2028 0x06ff0870, 0x0fff0ff0, "uxth%c %12-15R, %0-3R, ror #16"},
2029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2030 0x06ff0c70, 0x0fff0ff0, "uxth%c %12-15R, %0-3R, ror #24"},
2031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2032 0x06cf0070, 0x0fff0ff0, "uxtb16%c %12-15R, %0-3R"},
2033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2034 0x06cf0470, 0x0fff0ff0, "uxtb16%c %12-15R, %0-3R, ror #8"},
2035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2036 0x06cf0870, 0x0fff0ff0, "uxtb16%c %12-15R, %0-3R, ror #16"},
2037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2038 0x06cf0c70, 0x0fff0ff0, "uxtb16%c %12-15R, %0-3R, ror #24"},
2039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2040 0x06ef0070, 0x0fff0ff0, "uxtb%c %12-15R, %0-3R"},
2041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2042 0x06ef0470, 0x0fff0ff0, "uxtb%c %12-15R, %0-3R, ror #8"},
2043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2044 0x06ef0870, 0x0fff0ff0, "uxtb%c %12-15R, %0-3R, ror #16"},
2045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2046 0x06ef0c70, 0x0fff0ff0, "uxtb%c %12-15R, %0-3R, ror #24"},
2047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2048 0x06b00070, 0x0ff00ff0, "sxtah%c %12-15R, %16-19r, %0-3R"},
2049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2050 0x06b00470, 0x0ff00ff0, "sxtah%c %12-15R, %16-19r, %0-3R, ror #8"},
2051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2052 0x06b00870, 0x0ff00ff0, "sxtah%c %12-15R, %16-19r, %0-3R, ror #16"},
2053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2054 0x06b00c70, 0x0ff00ff0, "sxtah%c %12-15R, %16-19r, %0-3R, ror #24"},
2055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2056 0x06800070, 0x0ff00ff0, "sxtab16%c %12-15R, %16-19r, %0-3R"},
2057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2058 0x06800470, 0x0ff00ff0, "sxtab16%c %12-15R, %16-19r, %0-3R, ror #8"},
2059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2060 0x06800870, 0x0ff00ff0, "sxtab16%c %12-15R, %16-19r, %0-3R, ror #16"},
2061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2062 0x06800c70, 0x0ff00ff0, "sxtab16%c %12-15R, %16-19r, %0-3R, ror #24"},
2063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2064 0x06a00070, 0x0ff00ff0, "sxtab%c %12-15R, %16-19r, %0-3R"},
2065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2066 0x06a00470, 0x0ff00ff0, "sxtab%c %12-15R, %16-19r, %0-3R, ror #8"},
2067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2068 0x06a00870, 0x0ff00ff0, "sxtab%c %12-15R, %16-19r, %0-3R, ror #16"},
2069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2070 0x06a00c70, 0x0ff00ff0, "sxtab%c %12-15R, %16-19r, %0-3R, ror #24"},
2071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2072 0x06f00070, 0x0ff00ff0, "uxtah%c %12-15R, %16-19r, %0-3R"},
2073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2074 0x06f00470, 0x0ff00ff0, "uxtah%c %12-15R, %16-19r, %0-3R, ror #8"},
2075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2076 0x06f00870, 0x0ff00ff0, "uxtah%c %12-15R, %16-19r, %0-3R, ror #16"},
2077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2078 0x06f00c70, 0x0ff00ff0, "uxtah%c %12-15R, %16-19r, %0-3R, ror #24"},
2079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2080 0x06c00070, 0x0ff00ff0, "uxtab16%c %12-15R, %16-19r, %0-3R"},
2081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2082 0x06c00470, 0x0ff00ff0, "uxtab16%c %12-15R, %16-19r, %0-3R, ror #8"},
2083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2084 0x06c00870, 0x0ff00ff0, "uxtab16%c %12-15R, %16-19r, %0-3R, ror #16"},
2085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2086 0x06c00c70, 0x0ff00ff0, "uxtab16%c %12-15R, %16-19r, %0-3R, ROR #24"},
2087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2088 0x06e00070, 0x0ff00ff0, "uxtab%c %12-15R, %16-19r, %0-3R"},
2089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2090 0x06e00470, 0x0ff00ff0, "uxtab%c %12-15R, %16-19r, %0-3R, ror #8"},
2091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2092 0x06e00870, 0x0ff00ff0, "uxtab%c %12-15R, %16-19r, %0-3R, ror #16"},
2093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2094 0x06e00c70, 0x0ff00ff0, "uxtab%c %12-15R, %16-19r, %0-3R, ror #24"},
2095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2096 0x06800fb0, 0x0ff00ff0, "sel%c %12-15R, %16-19R, %0-3R"},
2097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2098 0xf1010000, 0xfffffc00, "setend %9?ble"},
2099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2100 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c %16-19R, %0-3R, %8-11R"},
2101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2102 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c %16-19R, %0-3R, %8-11R"},
2103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2104 0x07000010, 0x0ff000d0, "smlad%5'x%c %16-19R, %0-3R, %8-11R, %12-15R"},
2105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2106 0x07400010, 0x0ff000d0, "smlald%5'x%c %12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2108 0x07000050, 0x0ff000d0, "smlsd%5'x%c %16-19R, %0-3R, %8-11R, %12-15R"},
2109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2110 0x07400050, 0x0ff000d0, "smlsld%5'x%c %12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2112 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c %16-19R, %0-3R, %8-11R"},
2113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2114 0x07500010, 0x0ff000d0, "smmla%5'r%c %16-19R, %0-3R, %8-11R, %12-15R"},
2115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2116 0x075000d0, 0x0ff000d0, "smmls%5'r%c %16-19R, %0-3R, %8-11R, %12-15R"},
2117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2118 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba %16-19r%21'!, %0-4d"},
2119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2120 0x06a00010, 0x0fe00ff0, "ssat%c %12-15R, %16-20W, %0-3R"},
2121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2122 0x06a00010, 0x0fe00070, "ssat%c %12-15R, %16-20W, %0-3R, lsl #%7-11d"},
2123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2124 0x06a00050, 0x0fe00070, "ssat%c %12-15R, %16-20W, %0-3R, asr #%7-11d"},
2125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2126 0x06a00f30, 0x0ff00ff0, "ssat16%c %12-15r, %16-19W, %0-3r"},
2127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2128 0x01800f90, 0x0ff00ff0, "strex%c %12-15R, %0-3R, [%16-19R]"},
2129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2130 0x00400090, 0x0ff000f0, "umaal%c %12-15R, %16-19R, %0-3R, %8-11R"},
2131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2132 0x0780f010, 0x0ff0f0f0, "usad8%c %16-19R, %0-3R, %8-11R"},
2133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2134 0x07800010, 0x0ff000f0, "usada8%c %16-19R, %0-3R, %8-11R, %12-15R"},
2135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2136 0x06e00010, 0x0fe00ff0, "usat%c %12-15R, %16-20d, %0-3R"},
2137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2138 0x06e00010, 0x0fe00070, "usat%c %12-15R, %16-20d, %0-3R, lsl #%7-11d"},
2139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2140 0x06e00050, 0x0fe00070, "usat%c %12-15R, %16-20d, %0-3R, asr #%7-11d"},
2141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2142 0x06e00f30, 0x0ff00ff0, "usat16%c %12-15R, %16-19d, %0-3R"},
2143
2144 /* V5J instruction. */
2145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
2146 0x012fff20, 0x0ffffff0, "bxj%c %0-3R"},
2147
2148 /* V5 Instructions. */
2149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2150 0xe1200070, 0xfff000f0,
2151 "bkpt 0x%16-19X%12-15X%8-11X%0-3X"},
2152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2153 0xfa000000, 0xfe000000, "blx %B"},
2154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2155 0x012fff30, 0x0ffffff0, "blx%c %0-3R"},
2156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2157 0x016f0f10, 0x0fff0ff0, "clz%c %12-15R, %0-3R"},
2158
2159 /* V5E "El Segundo" Instructions. */
2160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2161 0x000000d0, 0x0e1000f0, "ldrd%c %12-15r, %s"},
2162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2163 0x000000f0, 0x0e1000f0, "strd%c %12-15r, %s"},
2164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2165 0xf450f000, 0xfc70f000, "pld %a"},
2166 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2167 0x01000080, 0x0ff000f0, "smlabb%c %16-19R, %0-3R, %8-11R, %12-15R"},
2168 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2169 0x010000a0, 0x0ff000f0, "smlatb%c %16-19R, %0-3R, %8-11R, %12-15R"},
2170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2171 0x010000c0, 0x0ff000f0, "smlabt%c %16-19R, %0-3R, %8-11R, %12-15R"},
2172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2173 0x010000e0, 0x0ff000f0, "smlatt%c %16-19r, %0-3r, %8-11R, %12-15R"},
2174
2175 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2176 0x01200080, 0x0ff000f0, "smlawb%c %16-19R, %0-3R, %8-11R, %12-15R"},
2177 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2178 0x012000c0, 0x0ff000f0, "smlawt%c %16-19R, %0-3r, %8-11R, %12-15R"},
2179
2180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2181 0x01400080, 0x0ff000f0, "smlalbb%c %12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2183 0x014000a0, 0x0ff000f0, "smlaltb%c %12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2185 0x014000c0, 0x0ff000f0, "smlalbt%c %12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2187 0x014000e0, 0x0ff000f0, "smlaltt%c %12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2188
2189 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2190 0x01600080, 0x0ff0f0f0, "smulbb%c %16-19R, %0-3R, %8-11R"},
2191 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2192 0x016000a0, 0x0ff0f0f0, "smultb%c %16-19R, %0-3R, %8-11R"},
2193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2194 0x016000c0, 0x0ff0f0f0, "smulbt%c %16-19R, %0-3R, %8-11R"},
2195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2196 0x016000e0, 0x0ff0f0f0, "smultt%c %16-19R, %0-3R, %8-11R"},
2197
2198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2199 0x012000a0, 0x0ff0f0f0, "smulwb%c %16-19R, %0-3R, %8-11R"},
2200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2201 0x012000e0, 0x0ff0f0f0, "smulwt%c %16-19R, %0-3R, %8-11R"},
2202
2203 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2204 0x01000050, 0x0ff00ff0, "qadd%c %12-15R, %0-3R, %16-19R"},
2205 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2206 0x01400050, 0x0ff00ff0, "qdadd%c %12-15R, %0-3R, %16-19R"},
2207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2208 0x01200050, 0x0ff00ff0, "qsub%c %12-15R, %0-3R, %16-19R"},
2209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2210 0x01600050, 0x0ff00ff0, "qdsub%c %12-15R, %0-3R, %16-19R"},
2211
2212 /* ARM Instructions. */
2213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2214 0x052d0004, 0x0fff0fff, "push%c {%12-15r} ; (str%c %12-15r, %a)"},
2215
2216 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2217 0x04400000, 0x0e500000, "strb%t%c %12-15R, %a"},
2218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2219 0x04000000, 0x0e500000, "str%t%c %12-15r, %a"},
2220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2221 0x06400000, 0x0e500ff0, "strb%t%c %12-15R, %a"},
2222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2223 0x06000000, 0x0e500ff0, "str%t%c %12-15r, %a"},
2224 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2225 0x04400000, 0x0c500010, "strb%t%c %12-15R, %a"},
2226 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2227 0x04000000, 0x0c500010, "str%t%c %12-15r, %a"},
2228
2229 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2230 0x04400000, 0x0e500000, "strb%c %12-15R, %a"},
2231 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2232 0x06400000, 0x0e500010, "strb%c %12-15R, %a"},
2233 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2234 0x004000b0, 0x0e5000f0, "strh%c %12-15R, %s"},
2235 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2236 0x000000b0, 0x0e500ff0, "strh%c %12-15R, %s"},
2237
2238 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2239 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
2240 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2241 0x00500090, 0x0e500090, "ldr%6's%5?hb%c %12-15R, %s"},
2242 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2243 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
2244 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2245 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c %12-15R, %s"},
2246
2247 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2248 0x02000000, 0x0fe00000, "and%20's%c %12-15r, %16-19r, %o"},
2249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2250 0x00000000, 0x0fe00010, "and%20's%c %12-15r, %16-19r, %o"},
2251 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2252 0x00000010, 0x0fe00090, "and%20's%c %12-15R, %16-19R, %o"},
2253
2254 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2255 0x02200000, 0x0fe00000, "eor%20's%c %12-15r, %16-19r, %o"},
2256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2257 0x00200000, 0x0fe00010, "eor%20's%c %12-15r, %16-19r, %o"},
2258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2259 0x00200010, 0x0fe00090, "eor%20's%c %12-15R, %16-19R, %o"},
2260
2261 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2262 0x02400000, 0x0fe00000, "sub%20's%c %12-15r, %16-19r, %o"},
2263 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2264 0x00400000, 0x0fe00010, "sub%20's%c %12-15r, %16-19r, %o"},
2265 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2266 0x00400010, 0x0fe00090, "sub%20's%c %12-15R, %16-19R, %o"},
2267
2268 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2269 0x02600000, 0x0fe00000, "rsb%20's%c %12-15r, %16-19r, %o"},
2270 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2271 0x00600000, 0x0fe00010, "rsb%20's%c %12-15r, %16-19r, %o"},
2272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2273 0x00600010, 0x0fe00090, "rsb%20's%c %12-15R, %16-19R, %o"},
2274
2275 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2276 0x02800000, 0x0fe00000, "add%20's%c %12-15r, %16-19r, %o"},
2277 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2278 0x00800000, 0x0fe00010, "add%20's%c %12-15r, %16-19r, %o"},
2279 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2280 0x00800010, 0x0fe00090, "add%20's%c %12-15R, %16-19R, %o"},
2281
2282 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2283 0x02a00000, 0x0fe00000, "adc%20's%c %12-15r, %16-19r, %o"},
2284 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2285 0x00a00000, 0x0fe00010, "adc%20's%c %12-15r, %16-19r, %o"},
2286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2287 0x00a00010, 0x0fe00090, "adc%20's%c %12-15R, %16-19R, %o"},
2288
2289 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2290 0x02c00000, 0x0fe00000, "sbc%20's%c %12-15r, %16-19r, %o"},
2291 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2292 0x00c00000, 0x0fe00010, "sbc%20's%c %12-15r, %16-19r, %o"},
2293 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2294 0x00c00010, 0x0fe00090, "sbc%20's%c %12-15R, %16-19R, %o"},
2295
2296 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2297 0x02e00000, 0x0fe00000, "rsc%20's%c %12-15r, %16-19r, %o"},
2298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2299 0x00e00000, 0x0fe00010, "rsc%20's%c %12-15r, %16-19r, %o"},
2300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2301 0x00e00010, 0x0fe00090, "rsc%20's%c %12-15R, %16-19R, %o"},
2302
2303 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
2304 0x0120f200, 0x0fb0f200, "msr%c %C, %0-3r"},
2305 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2306 0x0120f000, 0x0db0f000, "msr%c %C, %o"},
2307 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2308 0x01000000, 0x0fb00cff, "mrs%c %12-15R, %R"},
2309
2310 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2311 0x03000000, 0x0fe00000, "tst%p%c %16-19r, %o"},
2312 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2313 0x01000000, 0x0fe00010, "tst%p%c %16-19r, %o"},
2314 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2315 0x01000010, 0x0fe00090, "tst%p%c %16-19R, %o"},
2316
2317 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2318 0x03300000, 0x0ff00000, "teq%p%c %16-19r, %o"},
2319 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2320 0x01300000, 0x0ff00010, "teq%p%c %16-19r, %o"},
2321 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2322 0x01300010, 0x0ff00010, "teq%p%c %16-19R, %o"},
2323 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2324 0x0130f000, 0x0ff0f010, "bx%c %0-3r"},
2325
2326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2327 0x03400000, 0x0fe00000, "cmp%p%c %16-19r, %o"},
2328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2329 0x01400000, 0x0fe00010, "cmp%p%c %16-19r, %o"},
2330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2331 0x01400010, 0x0fe00090, "cmp%p%c %16-19R, %o"},
2332
2333 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2334 0x03600000, 0x0fe00000, "cmn%p%c %16-19r, %o"},
2335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2336 0x01600000, 0x0fe00010, "cmn%p%c %16-19r, %o"},
2337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2338 0x01600010, 0x0fe00090, "cmn%p%c %16-19R, %o"},
2339
2340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2341 0x03800000, 0x0fe00000, "orr%20's%c %12-15r, %16-19r, %o"},
2342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2343 0x01800000, 0x0fe00010, "orr%20's%c %12-15r, %16-19r, %o"},
2344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2345 0x01800010, 0x0fe00090, "orr%20's%c %12-15R, %16-19R, %o"},
2346
2347 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2348 0x03a00000, 0x0fef0000, "mov%20's%c %12-15r, %o"},
2349 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2350 0x01a00000, 0x0def0ff0, "mov%20's%c %12-15r, %0-3r"},
2351 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2352 0x01a00000, 0x0def0060, "lsl%20's%c %12-15R, %q"},
2353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2354 0x01a00020, 0x0def0060, "lsr%20's%c %12-15R, %q"},
2355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2356 0x01a00040, 0x0def0060, "asr%20's%c %12-15R, %q"},
2357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2358 0x01a00060, 0x0def0ff0, "rrx%20's%c %12-15r, %0-3r"},
2359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2360 0x01a00060, 0x0def0060, "ror%20's%c %12-15R, %q"},
2361
2362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2363 0x03c00000, 0x0fe00000, "bic%20's%c %12-15r, %16-19r, %o"},
2364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2365 0x01c00000, 0x0fe00010, "bic%20's%c %12-15r, %16-19r, %o"},
2366 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2367 0x01c00010, 0x0fe00090, "bic%20's%c %12-15R, %16-19R, %o"},
2368
2369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2370 0x03e00000, 0x0fe00000, "mvn%20's%c %12-15r, %o"},
2371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2372 0x01e00000, 0x0fe00010, "mvn%20's%c %12-15r, %o"},
2373 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2374 0x01e00010, 0x0fe00090, "mvn%20's%c %12-15R, %o"},
2375
2376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2377 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
2378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2379 0x049d0004, 0x0fff0fff, "pop%c {%12-15r} ; (ldr%c %12-15r, %a)"},
2380
2381 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2382 0x04500000, 0x0c500000, "ldrb%t%c %12-15R, %a"},
2383
2384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2385 0x04300000, 0x0d700000, "ldrt%c %12-15R, %a"},
2386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2387 0x04100000, 0x0c500000, "ldr%c %12-15r, %a"},
2388
2389 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2390 0x092d0001, 0x0fffffff, "stmfd%c %16-19R!, %m"},
2391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2392 0x092d0002, 0x0fffffff, "stmfd%c %16-19R!, %m"},
2393 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2394 0x092d0004, 0x0fffffff, "stmfd%c %16-19R!, %m"},
2395 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2396 0x092d0008, 0x0fffffff, "stmfd%c %16-19R!, %m"},
2397 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2398 0x092d0010, 0x0fffffff, "stmfd%c %16-19R!, %m"},
2399 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2400 0x092d0020, 0x0fffffff, "stmfd%c %16-19R!, %m"},
2401 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2402 0x092d0040, 0x0fffffff, "stmfd%c %16-19R!, %m"},
2403 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2404 0x092d0080, 0x0fffffff, "stmfd%c %16-19R!, %m"},
2405 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2406 0x092d0100, 0x0fffffff, "stmfd%c %16-19R!, %m"},
2407 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2408 0x092d0200, 0x0fffffff, "stmfd%c %16-19R!, %m"},
2409 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2410 0x092d0400, 0x0fffffff, "stmfd%c %16-19R!, %m"},
2411 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2412 0x092d0800, 0x0fffffff, "stmfd%c %16-19R!, %m"},
2413 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2414 0x092d1000, 0x0fffffff, "stmfd%c %16-19R!, %m"},
2415 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2416 0x092d2000, 0x0fffffff, "stmfd%c %16-19R!, %m"},
2417 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2418 0x092d4000, 0x0fffffff, "stmfd%c %16-19R!, %m"},
2419 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2420 0x092d8000, 0x0fffffff, "stmfd%c %16-19R!, %m"},
2421 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2422 0x092d0000, 0x0fff0000, "push%c %m"},
2423 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2424 0x08800000, 0x0ff00000, "stm%c %16-19R%21'!, %m%22'^"},
2425 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2426 0x08000000, 0x0e100000, "stm%23?id%24?ba%c %16-19R%21'!, %m%22'^"},
2427
2428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2429 0x08bd0001, 0x0fffffff, "ldmfd%c %16-19R!, %m"},
2430 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2431 0x08bd0002, 0x0fffffff, "ldmfd%c %16-19R!, %m"},
2432 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2433 0x08bd0004, 0x0fffffff, "ldmfd%c %16-19R!, %m"},
2434 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2435 0x08bd0008, 0x0fffffff, "ldmfd%c %16-19R!, %m"},
2436 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2437 0x08bd0010, 0x0fffffff, "ldmfd%c %16-19R!, %m"},
2438 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2439 0x08bd0020, 0x0fffffff, "ldmfd%c %16-19R!, %m"},
2440 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2441 0x08bd0040, 0x0fffffff, "ldmfd%c %16-19R!, %m"},
2442 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2443 0x08bd0080, 0x0fffffff, "ldmfd%c %16-19R!, %m"},
2444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2445 0x08bd0100, 0x0fffffff, "ldmfd%c %16-19R!, %m"},
2446 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2447 0x08bd0200, 0x0fffffff, "ldmfd%c %16-19R!, %m"},
2448 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2449 0x08bd0400, 0x0fffffff, "ldmfd%c %16-19R!, %m"},
2450 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2451 0x08bd0800, 0x0fffffff, "ldmfd%c %16-19R!, %m"},
2452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2453 0x08bd1000, 0x0fffffff, "ldmfd%c %16-19R!, %m"},
2454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2455 0x08bd2000, 0x0fffffff, "ldmfd%c %16-19R!, %m"},
2456 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2457 0x08bd4000, 0x0fffffff, "ldmfd%c %16-19R!, %m"},
2458 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2459 0x08bd8000, 0x0fffffff, "ldmfd%c %16-19R!, %m"},
2460 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2461 0x08bd0000, 0x0fff0000, "pop%c %m"},
2462 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2463 0x08900000, 0x0f900000, "ldm%c %16-19R%21'!, %m%22'^"},
2464 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2465 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c %16-19R%21'!, %m%22'^"},
2466
2467 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2468 0x0a000000, 0x0e000000, "b%24'l%c %b"},
2469 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2470 0x0f000000, 0x0f000000, "svc%c %0-23x"},
2471
2472 /* The rest. */
2473 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
2474 0x03200000, 0x0fff00ff, "nop%c {%0-7d}" UNPREDICTABLE_INSTRUCTION},
2475 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2476 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2477 {ARM_FEATURE_CORE_LOW (0),
2478 0x00000000, 0x00000000, 0}
2479 };
2480
2481 /* print_insn_thumb16 recognizes the following format control codes:
2482
2483 %S print Thumb register (bits 3..5 as high number if bit 6 set)
2484 %D print Thumb register (bits 0..2 as high number if bit 7 set)
2485 %<bitfield>I print bitfield as a signed decimal
2486 (top bit of range being the sign bit)
2487 %N print Thumb register mask (with LR)
2488 %O print Thumb register mask (with PC)
2489 %M print Thumb register mask
2490 %b print CZB's 6-bit unsigned branch destination
2491 %s print Thumb right-shift immediate (6..10; 0 == 32).
2492 %c print the condition code
2493 %C print the condition code, or "s" if not conditional
2494 %x print warning if conditional an not at end of IT block"
2495 %X print " ; unpredictable <IT:code>" if conditional
2496 %I print IT instruction suffix and operands
2497 %W print Thumb Writeback indicator for LDMIA
2498 %<bitfield>r print bitfield as an ARM register
2499 %<bitfield>d print bitfield as a decimal
2500 %<bitfield>H print (bitfield * 2) as a decimal
2501 %<bitfield>W print (bitfield * 4) as a decimal
2502 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
2503 %<bitfield>B print Thumb branch destination (signed displacement)
2504 %<bitfield>c print bitfield as a condition code
2505 %<bitnum>'c print specified char iff bit is one
2506 %<bitnum>?ab print a if bit is one else print b. */
2507
2508 static const struct opcode16 thumb_opcodes[] =
2509 {
2510 /* Thumb instructions. */
2511
2512 /* ARMv8-M Security Extensions instructions. */
2513 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns %3-6r"},
2514 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff07, "bxns %3-6r"},
2515
2516 /* ARM V8 instructions. */
2517 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
2518 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt %0-5x"},
2519 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan %3-3d"},
2520
2521 /* ARM V6K no-argument instructions. */
2522 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
2523 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
2524 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
2525 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
2526 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
2527 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c {%4-7d}"},
2528
2529 /* ARM V6T2 instructions. */
2530 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2531 0xb900, 0xfd00, "cbnz %0-2r, %b%X"},
2532 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2533 0xb100, 0xfd00, "cbz %0-2r, %b%X"},
2534 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
2535
2536 /* ARM V6. */
2537 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie %2'a%1'i%0'f%X"},
2538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid %2'a%1'i%0'f%X"},
2539 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c %0-2r, %3-5r"},
2540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c %0-2r, %3-5r"},
2541 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c %0-2r, %3-5r"},
2542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c %0-2r, %3-5r"},
2543 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend %3?ble%X"},
2544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c %0-2r, %3-5r"},
2545 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c %0-2r, %3-5r"},
2546 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c %0-2r, %3-5r"},
2547 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c %0-2r, %3-5r"},
2548
2549 /* ARM V5 ISA extends Thumb. */
2550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2551 0xbe00, 0xff00, "bkpt %0-7x"}, /* Is always unconditional. */
2552 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
2553 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2554 0x4780, 0xff87, "blx%c %3-6r%x"}, /* note: 4 bit register number. */
2555 /* ARM V4T ISA (Thumb v1). */
2556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2557 0x46C0, 0xFFFF, "nop%c ; (mov r8, r8)"},
2558 /* Format 4. */
2559 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C %0-2r, %3-5r"},
2560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C %0-2r, %3-5r"},
2561 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C %0-2r, %3-5r"},
2562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C %0-2r, %3-5r"},
2563 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C %0-2r, %3-5r"},
2564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C %0-2r, %3-5r"},
2565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C %0-2r, %3-5r"},
2566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C %0-2r, %3-5r"},
2567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c %0-2r, %3-5r"},
2568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C %0-2r, %3-5r"},
2569 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c %0-2r, %3-5r"},
2570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c %0-2r, %3-5r"},
2571 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C %0-2r, %3-5r"},
2572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C %0-2r, %3-5r"},
2573 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C %0-2r, %3-5r"},
2574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C %0-2r, %3-5r"},
2575 /* format 13 */
2576 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c sp, %0-6W"},
2577 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c sp, %0-6W"},
2578 /* format 5 */
2579 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c %S%x"},
2580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c %D, %S"},
2581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c %D, %S"},
2582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c %D, %S"},
2583 /* format 14 */
2584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c %N"},
2585 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c %O"},
2586 /* format 2 */
2587 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2588 0x1800, 0xFE00, "add%C %0-2r, %3-5r, %6-8r"},
2589 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2590 0x1A00, 0xFE00, "sub%C %0-2r, %3-5r, %6-8r"},
2591 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2592 0x1C00, 0xFE00, "add%C %0-2r, %3-5r, %6-8d"},
2593 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2594 0x1E00, 0xFE00, "sub%C %0-2r, %3-5r, %6-8d"},
2595 /* format 8 */
2596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2597 0x5200, 0xFE00, "strh%c %0-2r, [%3-5r, %6-8r]"},
2598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2599 0x5A00, 0xFE00, "ldrh%c %0-2r, [%3-5r, %6-8r]"},
2600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2601 0x5600, 0xF600, "ldrs%11?hb%c %0-2r, [%3-5r, %6-8r]"},
2602 /* format 7 */
2603 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2604 0x5000, 0xFA00, "str%10'b%c %0-2r, [%3-5r, %6-8r]"},
2605 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2606 0x5800, 0xFA00, "ldr%10'b%c %0-2r, [%3-5r, %6-8r]"},
2607 /* format 1 */
2608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C %0-2r, %3-5r"},
2609 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2610 0x0000, 0xF800, "lsl%C %0-2r, %3-5r, %6-10d"},
2611 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C %0-2r, %3-5r, %s"},
2612 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C %0-2r, %3-5r, %s"},
2613 /* format 3 */
2614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C %8-10r, %0-7d"},
2615 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c %8-10r, %0-7d"},
2616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C %8-10r, %0-7d"},
2617 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C %8-10r, %0-7d"},
2618 /* format 6 */
2619 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
2620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2621 0x4800, 0xF800,
2622 "ldr%c %8-10r, [pc, %0-7W] ; (%0-7a)"},
2623 /* format 9 */
2624 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2625 0x6000, 0xF800, "str%c %0-2r, [%3-5r, %6-10W]"},
2626 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2627 0x6800, 0xF800, "ldr%c %0-2r, [%3-5r, %6-10W]"},
2628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2629 0x7000, 0xF800, "strb%c %0-2r, [%3-5r, %6-10d]"},
2630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2631 0x7800, 0xF800, "ldrb%c %0-2r, [%3-5r, %6-10d]"},
2632 /* format 10 */
2633 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2634 0x8000, 0xF800, "strh%c %0-2r, [%3-5r, %6-10H]"},
2635 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2636 0x8800, 0xF800, "ldrh%c %0-2r, [%3-5r, %6-10H]"},
2637 /* format 11 */
2638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2639 0x9000, 0xF800, "str%c %8-10r, [sp, %0-7W]"},
2640 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2641 0x9800, 0xF800, "ldr%c %8-10r, [sp, %0-7W]"},
2642 /* format 12 */
2643 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2644 0xA000, 0xF800, "add%c %8-10r, pc, %0-7W ; (adr %8-10r, %0-7a)"},
2645 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2646 0xA800, 0xF800, "add%c %8-10r, sp, %0-7W"},
2647 /* format 15 */
2648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c %8-10r!, %M"},
2649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c %8-10r%W, %M"},
2650 /* format 17 */
2651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c %0-7d"},
2652 /* format 16 */
2653 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c %0-7d"},
2654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
2655 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n %0-7B%X"},
2656 /* format 18 */
2657 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n %0-10B%x"},
2658
2659 /* The E800 .. FFFF range is unconditionally redirected to the
2660 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
2661 are processed via that table. Thus, we can never encounter a
2662 bare "second half of BL/BLX(1)" instruction here. */
2663 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
2664 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2665 };
2666
2667 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
2668 We adopt the convention that hw1 is the high 16 bits of .value and
2669 .mask, hw2 the low 16 bits.
2670
2671 print_insn_thumb32 recognizes the following format control codes:
2672
2673 %% %
2674
2675 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
2676 %M print a modified 12-bit immediate (same location)
2677 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
2678 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
2679 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
2680 %S print a possibly-shifted Rm
2681
2682 %L print address for a ldrd/strd instruction
2683 %a print the address of a plain load/store
2684 %w print the width and signedness of a core load/store
2685 %m print register mask for ldm/stm
2686
2687 %E print the lsb and width fields of a bfc/bfi instruction
2688 %F print the lsb and width fields of a sbfx/ubfx instruction
2689 %b print a conditional branch offset
2690 %B print an unconditional branch offset
2691 %s print the shift field of an SSAT instruction
2692 %R print the rotation field of an SXT instruction
2693 %U print barrier type.
2694 %P print address for pli instruction.
2695 %c print the condition code
2696 %x print warning if conditional an not at end of IT block"
2697 %X print " ; unpredictable <IT:code>" if conditional
2698
2699 %<bitfield>d print bitfield in decimal
2700 %<bitfield>D print bitfield plus one in decimal
2701 %<bitfield>W print bitfield*4 in decimal
2702 %<bitfield>r print bitfield as an ARM register
2703 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
2704 %<bitfield>S as %<>R but r13 is UNPREDICTABLE
2705 %<bitfield>c print bitfield as a condition code
2706
2707 %<bitfield>'c print specified char iff bitfield is all ones
2708 %<bitfield>`c print specified char iff bitfield is all zeroes
2709 %<bitfield>?ab... select from array of values in big endian order
2710
2711 With one exception at the bottom (done because BL and BLX(1) need
2712 to come dead last), this table was machine-sorted first in
2713 decreasing order of number of bits set in the mask, then in
2714 increasing numeric order of mask, then in increasing numeric order
2715 of opcode. This order is not the clearest for a human reader, but
2716 is guaranteed never to catch a special-case bit pattern with a more
2717 general mask, which is important, because this instruction encoding
2718 makes heavy use of special-case bit patterns. */
2719 static const struct opcode32 thumb32_opcodes[] =
2720 {
2721 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
2722 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
2723 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2724 0xe840f000, 0xfff0f0ff, "tt %8-11r, %16-19r"},
2725 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2726 0xe840f040, 0xfff0f0ff, "ttt %8-11r, %16-19r"},
2727 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2728 0xe840f080, 0xfff0f0ff, "tta %8-11r, %16-19r"},
2729 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2730 0xe840f0c0, 0xfff0f0ff, "ttat %8-11r, %16-19r"},
2731
2732 /* ARM V8.2 RAS extension instructions. */
2733 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
2734 0xf3af8010, 0xffffffff, "esb"},
2735
2736 /* V8 instructions. */
2737 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2738 0xf3af8005, 0xffffffff, "sevl%c.w"},
2739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2740 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
2741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2742 0xe8c00f8f, 0xfff00fff, "stlb%c %12-15r, [%16-19R]"},
2743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2744 0xe8c00f9f, 0xfff00fff, "stlh%c %12-15r, [%16-19R]"},
2745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2746 0xe8c00faf, 0xfff00fff, "stl%c %12-15r, [%16-19R]"},
2747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2748 0xe8c00fc0, 0xfff00ff0, "stlexb%c %0-3r, %12-15r, [%16-19R]"},
2749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2750 0xe8c00fd0, 0xfff00ff0, "stlexh%c %0-3r, %12-15r, [%16-19R]"},
2751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2752 0xe8c00fe0, 0xfff00ff0, "stlex%c %0-3r, %12-15r, [%16-19R]"},
2753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2754 0xe8c000f0, 0xfff000f0, "stlexd%c %0-3r, %12-15r, %8-11r, [%16-19R]"},
2755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2756 0xe8d00f8f, 0xfff00fff, "ldab%c %12-15r, [%16-19R]"},
2757 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2758 0xe8d00f9f, 0xfff00fff, "ldah%c %12-15r, [%16-19R]"},
2759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2760 0xe8d00faf, 0xfff00fff, "lda%c %12-15r, [%16-19R]"},
2761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2762 0xe8d00fcf, 0xfff00fff, "ldaexb%c %12-15r, [%16-19R]"},
2763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2764 0xe8d00fdf, 0xfff00fff, "ldaexh%c %12-15r, [%16-19R]"},
2765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2766 0xe8d00fef, 0xfff00fff, "ldaex%c %12-15r, [%16-19R]"},
2767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2768 0xe8d000ff, 0xfff000ff, "ldaexd%c %12-15r, %8-11r, [%16-19R]"},
2769
2770 /* CRC32 instructions. */
2771 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2772 0xfac0f080, 0xfff0f0f0, "crc32b %8-11S, %16-19S, %0-3S"},
2773 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2774 0xfac0f090, 0xfff0f0f0, "crc32h %9-11S, %16-19S, %0-3S"},
2775 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2776 0xfac0f0a0, 0xfff0f0f0, "crc32w %8-11S, %16-19S, %0-3S"},
2777 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2778 0xfad0f080, 0xfff0f0f0, "crc32cb %8-11S, %16-19S, %0-3S"},
2779 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2780 0xfad0f090, 0xfff0f0f0, "crc32ch %8-11S, %16-19S, %0-3S"},
2781 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2782 0xfad0f0a0, 0xfff0f0f0, "crc32cw %8-11S, %16-19S, %0-3S"},
2783
2784 /* V7 instructions. */
2785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c %a"},
2786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c %0-3d"},
2787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c %U"},
2788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c %U"},
2789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c %U"},
2790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c %U"},
2791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c %U"},
2792 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2793 0xfb90f0f0, 0xfff0f0f0, "sdiv%c %8-11r, %16-19r, %0-3r"},
2794 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2795 0xfbb0f0f0, 0xfff0f0f0, "udiv%c %8-11r, %16-19r, %0-3r"},
2796
2797 /* Virtualization Extension instructions. */
2798 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c %V"},
2799 /* We skip ERET as that is SUBS pc, lr, #0. */
2800
2801 /* MP Extension instructions. */
2802 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c %a"},
2803
2804 /* Security extension instructions. */
2805 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c %K"},
2806
2807 /* Instructions defined in the basic V6T2 set. */
2808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
2809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
2810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
2811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
2812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
2813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2814 0xf3af8000, 0xffffff00, "nop%c.w {%0-7d}"},
2815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w %H"},
2816
2817 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2818 0xf3bf8f2f, 0xffffffff, "clrex%c"},
2819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2820 0xf3af8400, 0xffffff1f, "cpsie.w %7'a%6'i%5'f%X"},
2821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2822 0xf3af8600, 0xffffff1f, "cpsid.w %7'a%6'i%5'f%X"},
2823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2824 0xf3c08f00, 0xfff0ffff, "bxj%c %16-19r%x"},
2825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2826 0xe810c000, 0xffd0ffff, "rfedb%c %16-19r%21'!"},
2827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2828 0xe990c000, 0xffd0ffff, "rfeia%c %16-19r%21'!"},
2829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2830 0xf3e08000, 0xffe0f000, "mrs%c %8-11r, %D"},
2831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2832 0xf3af8100, 0xffffffe0, "cps %0-4d%X"},
2833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2834 0xe8d0f000, 0xfff0fff0, "tbb%c [%16-19r, %0-3r]%x"},
2835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2836 0xe8d0f010, 0xfff0fff0, "tbh%c [%16-19r, %0-3r, lsl #1]%x"},
2837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2838 0xf3af8500, 0xffffff00, "cpsie %7'a%6'i%5'f, %0-4d%X"},
2839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2840 0xf3af8700, 0xffffff00, "cpsid %7'a%6'i%5'f, %0-4d%X"},
2841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2842 0xf3de8f00, 0xffffff00, "subs%c pc, lr, %0-7d"},
2843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2844 0xf3808000, 0xffe0f000, "msr%c %C, %16-19r"},
2845 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2846 0xe8500f00, 0xfff00fff, "ldrex%c %12-15r, [%16-19r]"},
2847 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2848 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c %12-15r, [%16-19r]"},
2849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2850 0xe800c000, 0xffd0ffe0, "srsdb%c %16-19r%21'!, %0-4d"},
2851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2852 0xe980c000, 0xffd0ffe0, "srsia%c %16-19r%21'!, %0-4d"},
2853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2854 0xfa0ff080, 0xfffff0c0, "sxth%c.w %8-11r, %0-3r%R"},
2855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2856 0xfa1ff080, 0xfffff0c0, "uxth%c.w %8-11r, %0-3r%R"},
2857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2858 0xfa2ff080, 0xfffff0c0, "sxtb16%c %8-11r, %0-3r%R"},
2859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2860 0xfa3ff080, 0xfffff0c0, "uxtb16%c %8-11r, %0-3r%R"},
2861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2862 0xfa4ff080, 0xfffff0c0, "sxtb%c.w %8-11r, %0-3r%R"},
2863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2864 0xfa5ff080, 0xfffff0c0, "uxtb%c.w %8-11r, %0-3r%R"},
2865 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2866 0xe8400000, 0xfff000ff, "strex%c %8-11r, %12-15r, [%16-19r]"},
2867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2868 0xe8d0007f, 0xfff000ff, "ldrexd%c %12-15r, %8-11r, [%16-19r]"},
2869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2870 0xfa80f000, 0xfff0f0f0, "sadd8%c %8-11r, %16-19r, %0-3r"},
2871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2872 0xfa80f010, 0xfff0f0f0, "qadd8%c %8-11r, %16-19r, %0-3r"},
2873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2874 0xfa80f020, 0xfff0f0f0, "shadd8%c %8-11r, %16-19r, %0-3r"},
2875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2876 0xfa80f040, 0xfff0f0f0, "uadd8%c %8-11r, %16-19r, %0-3r"},
2877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2878 0xfa80f050, 0xfff0f0f0, "uqadd8%c %8-11r, %16-19r, %0-3r"},
2879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2880 0xfa80f060, 0xfff0f0f0, "uhadd8%c %8-11r, %16-19r, %0-3r"},
2881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2882 0xfa80f080, 0xfff0f0f0, "qadd%c %8-11r, %0-3r, %16-19r"},
2883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2884 0xfa80f090, 0xfff0f0f0, "qdadd%c %8-11r, %0-3r, %16-19r"},
2885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2886 0xfa80f0a0, 0xfff0f0f0, "qsub%c %8-11r, %0-3r, %16-19r"},
2887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2888 0xfa80f0b0, 0xfff0f0f0, "qdsub%c %8-11r, %0-3r, %16-19r"},
2889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2890 0xfa90f000, 0xfff0f0f0, "sadd16%c %8-11r, %16-19r, %0-3r"},
2891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2892 0xfa90f010, 0xfff0f0f0, "qadd16%c %8-11r, %16-19r, %0-3r"},
2893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2894 0xfa90f020, 0xfff0f0f0, "shadd16%c %8-11r, %16-19r, %0-3r"},
2895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2896 0xfa90f040, 0xfff0f0f0, "uadd16%c %8-11r, %16-19r, %0-3r"},
2897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2898 0xfa90f050, 0xfff0f0f0, "uqadd16%c %8-11r, %16-19r, %0-3r"},
2899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2900 0xfa90f060, 0xfff0f0f0, "uhadd16%c %8-11r, %16-19r, %0-3r"},
2901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2902 0xfa90f080, 0xfff0f0f0, "rev%c.w %8-11r, %16-19r"},
2903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2904 0xfa90f090, 0xfff0f0f0, "rev16%c.w %8-11r, %16-19r"},
2905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2906 0xfa90f0a0, 0xfff0f0f0, "rbit%c %8-11r, %16-19r"},
2907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2908 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w %8-11r, %16-19r"},
2909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2910 0xfaa0f000, 0xfff0f0f0, "sasx%c %8-11r, %16-19r, %0-3r"},
2911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2912 0xfaa0f010, 0xfff0f0f0, "qasx%c %8-11r, %16-19r, %0-3r"},
2913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2914 0xfaa0f020, 0xfff0f0f0, "shasx%c %8-11r, %16-19r, %0-3r"},
2915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2916 0xfaa0f040, 0xfff0f0f0, "uasx%c %8-11r, %16-19r, %0-3r"},
2917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2918 0xfaa0f050, 0xfff0f0f0, "uqasx%c %8-11r, %16-19r, %0-3r"},
2919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2920 0xfaa0f060, 0xfff0f0f0, "uhasx%c %8-11r, %16-19r, %0-3r"},
2921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2922 0xfaa0f080, 0xfff0f0f0, "sel%c %8-11r, %16-19r, %0-3r"},
2923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2924 0xfab0f080, 0xfff0f0f0, "clz%c %8-11r, %16-19r"},
2925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2926 0xfac0f000, 0xfff0f0f0, "ssub8%c %8-11r, %16-19r, %0-3r"},
2927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2928 0xfac0f010, 0xfff0f0f0, "qsub8%c %8-11r, %16-19r, %0-3r"},
2929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2930 0xfac0f020, 0xfff0f0f0, "shsub8%c %8-11r, %16-19r, %0-3r"},
2931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2932 0xfac0f040, 0xfff0f0f0, "usub8%c %8-11r, %16-19r, %0-3r"},
2933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2934 0xfac0f050, 0xfff0f0f0, "uqsub8%c %8-11r, %16-19r, %0-3r"},
2935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2936 0xfac0f060, 0xfff0f0f0, "uhsub8%c %8-11r, %16-19r, %0-3r"},
2937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2938 0xfad0f000, 0xfff0f0f0, "ssub16%c %8-11r, %16-19r, %0-3r"},
2939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2940 0xfad0f010, 0xfff0f0f0, "qsub16%c %8-11r, %16-19r, %0-3r"},
2941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2942 0xfad0f020, 0xfff0f0f0, "shsub16%c %8-11r, %16-19r, %0-3r"},
2943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2944 0xfad0f040, 0xfff0f0f0, "usub16%c %8-11r, %16-19r, %0-3r"},
2945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2946 0xfad0f050, 0xfff0f0f0, "uqsub16%c %8-11r, %16-19r, %0-3r"},
2947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2948 0xfad0f060, 0xfff0f0f0, "uhsub16%c %8-11r, %16-19r, %0-3r"},
2949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2950 0xfae0f000, 0xfff0f0f0, "ssax%c %8-11r, %16-19r, %0-3r"},
2951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2952 0xfae0f010, 0xfff0f0f0, "qsax%c %8-11r, %16-19r, %0-3r"},
2953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2954 0xfae0f020, 0xfff0f0f0, "shsax%c %8-11r, %16-19r, %0-3r"},
2955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2956 0xfae0f040, 0xfff0f0f0, "usax%c %8-11r, %16-19r, %0-3r"},
2957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2958 0xfae0f050, 0xfff0f0f0, "uqsax%c %8-11r, %16-19r, %0-3r"},
2959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2960 0xfae0f060, 0xfff0f0f0, "uhsax%c %8-11r, %16-19r, %0-3r"},
2961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2962 0xfb00f000, 0xfff0f0f0, "mul%c.w %8-11r, %16-19r, %0-3r"},
2963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2964 0xfb70f000, 0xfff0f0f0, "usad8%c %8-11r, %16-19r, %0-3r"},
2965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2966 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w %8-11R, %16-19R, %0-3R"},
2967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2968 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w %8-11R, %16-19R, %0-3R"},
2969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2970 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w %8-11R, %16-19R, %0-3R"},
2971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2972 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w %8-11r, %16-19r, %0-3r"},
2973 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2974 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c %0-3r, %12-15r, [%16-19r]"},
2975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2976 0xf3200000, 0xfff0f0e0, "ssat16%c %8-11r, %0-4D, %16-19r"},
2977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2978 0xf3a00000, 0xfff0f0e0, "usat16%c %8-11r, %0-4d, %16-19r"},
2979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2980 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c %8-11r, %16-19r, %0-3r"},
2981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2982 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c %8-11r, %16-19r, %0-3r"},
2983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2984 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c %8-11r, %16-19r, %0-3r"},
2985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2986 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c %8-11r, %16-19r, %0-3r"},
2987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2988 0xfa00f080, 0xfff0f0c0, "sxtah%c %8-11r, %16-19r, %0-3r%R"},
2989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2990 0xfa10f080, 0xfff0f0c0, "uxtah%c %8-11r, %16-19r, %0-3r%R"},
2991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2992 0xfa20f080, 0xfff0f0c0, "sxtab16%c %8-11r, %16-19r, %0-3r%R"},
2993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2994 0xfa30f080, 0xfff0f0c0, "uxtab16%c %8-11r, %16-19r, %0-3r%R"},
2995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2996 0xfa40f080, 0xfff0f0c0, "sxtab%c %8-11r, %16-19r, %0-3r%R"},
2997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2998 0xfa50f080, 0xfff0f0c0, "uxtab%c %8-11r, %16-19r, %0-3r%R"},
2999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3000 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c %8-11r, %16-19r, %0-3r"},
3001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3002 0xf36f0000, 0xffff8020, "bfc%c %8-11r, %E"},
3003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3004 0xea100f00, 0xfff08f00, "tst%c.w %16-19r, %S"},
3005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3006 0xea900f00, 0xfff08f00, "teq%c %16-19r, %S"},
3007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3008 0xeb100f00, 0xfff08f00, "cmn%c.w %16-19r, %S"},
3009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3010 0xebb00f00, 0xfff08f00, "cmp%c.w %16-19r, %S"},
3011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3012 0xf0100f00, 0xfbf08f00, "tst%c.w %16-19r, %M"},
3013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3014 0xf0900f00, 0xfbf08f00, "teq%c %16-19r, %M"},
3015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3016 0xf1100f00, 0xfbf08f00, "cmn%c.w %16-19r, %M"},
3017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3018 0xf1b00f00, 0xfbf08f00, "cmp%c.w %16-19r, %M"},
3019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3020 0xea4f0000, 0xffef8000, "mov%20's%c.w %8-11r, %S"},
3021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3022 0xea6f0000, 0xffef8000, "mvn%20's%c.w %8-11r, %S"},
3023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3024 0xe8c00070, 0xfff000f0, "strexd%c %0-3r, %12-15r, %8-11r, [%16-19r]"},
3025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3026 0xfb000000, 0xfff000f0, "mla%c %8-11r, %16-19r, %0-3r, %12-15r"},
3027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3028 0xfb000010, 0xfff000f0, "mls%c %8-11r, %16-19r, %0-3r, %12-15r"},
3029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3030 0xfb700000, 0xfff000f0, "usada8%c %8-11R, %16-19R, %0-3R, %12-15R"},
3031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3032 0xfb800000, 0xfff000f0, "smull%c %12-15R, %8-11R, %16-19R, %0-3R"},
3033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3034 0xfba00000, 0xfff000f0, "umull%c %12-15R, %8-11R, %16-19R, %0-3R"},
3035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3036 0xfbc00000, 0xfff000f0, "smlal%c %12-15R, %8-11R, %16-19R, %0-3R"},
3037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3038 0xfbe00000, 0xfff000f0, "umlal%c %12-15R, %8-11R, %16-19R, %0-3R"},
3039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3040 0xfbe00060, 0xfff000f0, "umaal%c %12-15R, %8-11R, %16-19R, %0-3R"},
3041 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3042 0xe8500f00, 0xfff00f00, "ldrex%c %12-15r, [%16-19r, %0-7W]"},
3043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3044 0xf04f0000, 0xfbef8000, "mov%20's%c.w %8-11r, %M"},
3045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3046 0xf06f0000, 0xfbef8000, "mvn%20's%c.w %8-11r, %M"},
3047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3048 0xf810f000, 0xff70f000, "pld%c %a"},
3049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3050 0xfb200000, 0xfff000e0, "smlad%4'x%c %8-11R, %16-19R, %0-3R, %12-15R"},
3051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3052 0xfb300000, 0xfff000e0, "smlaw%4?tb%c %8-11R, %16-19R, %0-3R, %12-15R"},
3053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3054 0xfb400000, 0xfff000e0, "smlsd%4'x%c %8-11R, %16-19R, %0-3R, %12-15R"},
3055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3056 0xfb500000, 0xfff000e0, "smmla%4'r%c %8-11R, %16-19R, %0-3R, %12-15R"},
3057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3058 0xfb600000, 0xfff000e0, "smmls%4'r%c %8-11R, %16-19R, %0-3R, %12-15R"},
3059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3060 0xfbc000c0, 0xfff000e0, "smlald%4'x%c %12-15R, %8-11R, %16-19R, %0-3R"},
3061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3062 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c %12-15R, %8-11R, %16-19R, %0-3R"},
3063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3064 0xeac00000, 0xfff08030, "pkhbt%c %8-11r, %16-19r, %S"},
3065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3066 0xeac00020, 0xfff08030, "pkhtb%c %8-11r, %16-19r, %S"},
3067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3068 0xf3400000, 0xfff08020, "sbfx%c %8-11r, %16-19r, %F"},
3069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3070 0xf3c00000, 0xfff08020, "ubfx%c %8-11r, %16-19r, %F"},
3071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3072 0xf8000e00, 0xff900f00, "str%wt%c %12-15r, %a"},
3073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3074 0xfb100000, 0xfff000c0,
3075 "smla%5?tb%4?tb%c %8-11r, %16-19r, %0-3r, %12-15r"},
3076 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3077 0xfbc00080, 0xfff000c0,
3078 "smlal%5?tb%4?tb%c %12-15r, %8-11r, %16-19r, %0-3r"},
3079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3080 0xf3600000, 0xfff08020, "bfi%c %8-11r, %16-19r, %E"},
3081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3082 0xf8100e00, 0xfe900f00, "ldr%wt%c %12-15r, %a"},
3083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3084 0xf3000000, 0xffd08020, "ssat%c %8-11r, %0-4D, %16-19r%s"},
3085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3086 0xf3800000, 0xffd08020, "usat%c %8-11r, %0-4d, %16-19r%s"},
3087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3088 0xf2000000, 0xfbf08000, "addw%c %8-11r, %16-19r, %I"},
3089 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3090 0xf2400000, 0xfbf08000, "movw%c %8-11r, %J"},
3091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3092 0xf2a00000, 0xfbf08000, "subw%c %8-11r, %16-19r, %I"},
3093 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3094 0xf2c00000, 0xfbf08000, "movt%c %8-11r, %J"},
3095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3096 0xea000000, 0xffe08000, "and%20's%c.w %8-11r, %16-19r, %S"},
3097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3098 0xea200000, 0xffe08000, "bic%20's%c.w %8-11r, %16-19r, %S"},
3099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3100 0xea400000, 0xffe08000, "orr%20's%c.w %8-11r, %16-19r, %S"},
3101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3102 0xea600000, 0xffe08000, "orn%20's%c %8-11r, %16-19r, %S"},
3103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3104 0xea800000, 0xffe08000, "eor%20's%c.w %8-11r, %16-19r, %S"},
3105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3106 0xeb000000, 0xffe08000, "add%20's%c.w %8-11r, %16-19r, %S"},
3107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3108 0xeb400000, 0xffe08000, "adc%20's%c.w %8-11r, %16-19r, %S"},
3109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3110 0xeb600000, 0xffe08000, "sbc%20's%c.w %8-11r, %16-19r, %S"},
3111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3112 0xeba00000, 0xffe08000, "sub%20's%c.w %8-11r, %16-19r, %S"},
3113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3114 0xebc00000, 0xffe08000, "rsb%20's%c %8-11r, %16-19r, %S"},
3115 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3116 0xe8400000, 0xfff00000, "strex%c %8-11r, %12-15r, [%16-19r, %0-7W]"},
3117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3118 0xf0000000, 0xfbe08000, "and%20's%c.w %8-11r, %16-19r, %M"},
3119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3120 0xf0200000, 0xfbe08000, "bic%20's%c.w %8-11r, %16-19r, %M"},
3121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3122 0xf0400000, 0xfbe08000, "orr%20's%c.w %8-11r, %16-19r, %M"},
3123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3124 0xf0600000, 0xfbe08000, "orn%20's%c %8-11r, %16-19r, %M"},
3125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3126 0xf0800000, 0xfbe08000, "eor%20's%c.w %8-11r, %16-19r, %M"},
3127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3128 0xf1000000, 0xfbe08000, "add%20's%c.w %8-11r, %16-19r, %M"},
3129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3130 0xf1400000, 0xfbe08000, "adc%20's%c.w %8-11r, %16-19r, %M"},
3131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3132 0xf1600000, 0xfbe08000, "sbc%20's%c.w %8-11r, %16-19r, %M"},
3133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3134 0xf1a00000, 0xfbe08000, "sub%20's%c.w %8-11r, %16-19r, %M"},
3135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3136 0xf1c00000, 0xfbe08000, "rsb%20's%c %8-11r, %16-19r, %M"},
3137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3138 0xe8800000, 0xffd00000, "stmia%c.w %16-19r%21'!, %m"},
3139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3140 0xe8900000, 0xffd00000, "ldmia%c.w %16-19r%21'!, %m"},
3141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3142 0xe9000000, 0xffd00000, "stmdb%c %16-19r%21'!, %m"},
3143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3144 0xe9100000, 0xffd00000, "ldmdb%c %16-19r%21'!, %m"},
3145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3146 0xe9c00000, 0xffd000ff, "strd%c %12-15r, %8-11r, [%16-19r]"},
3147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3148 0xe9d00000, 0xffd000ff, "ldrd%c %12-15r, %8-11r, [%16-19r]"},
3149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3150 0xe9400000, 0xff500000,
3151 "strd%c %12-15r, %8-11r, [%16-19r, %23`-%0-7W]%21'!%L"},
3152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3153 0xe9500000, 0xff500000,
3154 "ldrd%c %12-15r, %8-11r, [%16-19r, %23`-%0-7W]%21'!%L"},
3155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3156 0xe8600000, 0xff700000,
3157 "strd%c %12-15r, %8-11r, [%16-19r], %23`-%0-7W%L"},
3158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3159 0xe8700000, 0xff700000,
3160 "ldrd%c %12-15r, %8-11r, [%16-19r], %23`-%0-7W%L"},
3161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3162 0xf8000000, 0xff100000, "str%w%c.w %12-15r, %a"},
3163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3164 0xf8100000, 0xfe100000, "ldr%w%c.w %12-15r, %a"},
3165
3166 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
3167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3168 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
3169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3170 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
3171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3172 0xf0008000, 0xf800d000, "b%22-25c.w %b%X"},
3173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3174 0xf0009000, 0xf800d000, "b%c.w %B%x"},
3175
3176 /* These have been 32-bit since the invention of Thumb. */
3177 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3178 0xf000c000, 0xf800d001, "blx%c %B%x"},
3179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3180 0xf000d000, 0xf800d000, "bl%c %B%x"},
3181
3182 /* Fallback. */
3183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3184 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
3185 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
3186 };
3187
3188 static const char *const arm_conditional[] =
3189 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
3190 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
3191
3192 static const char *const arm_fp_const[] =
3193 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
3194
3195 static const char *const arm_shift[] =
3196 {"lsl", "lsr", "asr", "ror"};
3197
3198 typedef struct
3199 {
3200 const char *name;
3201 const char *description;
3202 const char *reg_names[16];
3203 }
3204 arm_regname;
3205
3206 static const arm_regname regnames[] =
3207 {
3208 { "reg-names-raw", N_("Select raw register names"),
3209 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
3210 { "reg-names-gcc", N_("Select register names used by GCC"),
3211 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
3212 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
3213 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
3214 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
3215 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
3216 { "reg-names-apcs", N_("Select register names used in the APCS"),
3217 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
3218 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
3219 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
3220 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
3221 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
3222 };
3223
3224 static const char *const iwmmxt_wwnames[] =
3225 {"b", "h", "w", "d"};
3226
3227 static const char *const iwmmxt_wwssnames[] =
3228 {"b", "bus", "bc", "bss",
3229 "h", "hus", "hc", "hss",
3230 "w", "wus", "wc", "wss",
3231 "d", "dus", "dc", "dss"
3232 };
3233
3234 static const char *const iwmmxt_regnames[] =
3235 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
3236 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
3237 };
3238
3239 static const char *const iwmmxt_cregnames[] =
3240 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
3241 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
3242 };
3243
3244 /* Default to GCC register name set. */
3245 static unsigned int regname_selected = 1;
3246
3247 #define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
3248 #define arm_regnames regnames[regname_selected].reg_names
3249
3250 static bfd_boolean force_thumb = FALSE;
3251
3252 /* Current IT instruction state. This contains the same state as the IT
3253 bits in the CPSR. */
3254 static unsigned int ifthen_state;
3255 /* IT state for the next instruction. */
3256 static unsigned int ifthen_next_state;
3257 /* The address of the insn for which the IT state is valid. */
3258 static bfd_vma ifthen_address;
3259 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
3260 /* Indicates that the current Conditional state is unconditional or outside
3261 an IT block. */
3262 #define COND_UNCOND 16
3263
3264
3265 /* Functions. */
3266
3267 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
3268 Returns pointer to following character of the format string and
3269 fills in *VALUEP and *WIDTHP with the extracted value and number of
3270 bits extracted. WIDTHP can be NULL. */
3271
3272 static const char *
arm_decode_bitfield(const char * ptr,unsigned long insn,unsigned long * valuep,int * widthp)3273 arm_decode_bitfield (const char *ptr,
3274 unsigned long insn,
3275 unsigned long *valuep,
3276 int *widthp)
3277 {
3278 unsigned long value = 0;
3279 int width = 0;
3280
3281 do
3282 {
3283 int start, end;
3284 int bits;
3285
3286 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++) {
3287 start = start * 10 + *ptr - '0';
3288 }
3289 if (*ptr == '-') {
3290 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++) {
3291 end = end * 10 + *ptr - '0';
3292 }
3293 } else {
3294 end = start;
3295 }
3296 bits = end - start;
3297 if (bits < 0) {
3298 return NULL;
3299 }
3300 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
3301 width += bits + 1;
3302 }
3303 while (*ptr++ == ',');
3304 *valuep = value;
3305 if (widthp) {
3306 *widthp = width;
3307 }
3308 return ptr - 1;
3309 }
3310
3311 static void
arm_decode_shift(long given,fprintf_ftype func,void * stream,bfd_boolean print_shift)3312 arm_decode_shift (long given, fprintf_ftype func, void *stream,
3313 bfd_boolean print_shift)
3314 {
3315 func (stream, "%s", arm_regnames[given & 0xf]);
3316
3317 if ((given & 0xff0) != 0)
3318 {
3319 if ((given & 0x10) == 0)
3320 {
3321 int amount = (given & 0xf80) >> 7;
3322 int shift = (given & 0x60) >> 5;
3323
3324 if (amount == 0)
3325 {
3326 if (shift == 3)
3327 {
3328 func (stream, ", rrx");
3329 return;
3330 }
3331
3332 amount = 32;
3333 }
3334
3335 if (print_shift) {
3336 func (stream, ", %s %d", arm_shift[shift], amount);
3337 } else {
3338 func (stream, ", %d", amount);
3339 }
3340 } else if ((given & 0x80) == 0x80) {
3341 func (stream, " ; <illegal shifter operand>");
3342 } else if (print_shift) {
3343 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
3344 arm_regnames[(given & 0xf00) >> 8]);
3345 } else {
3346 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
3347 }
3348 }
3349 }
3350
3351 #define W_BIT 21
3352 #define I_BIT 22
3353 #define U_BIT 23
3354 #define P_BIT 24
3355
3356 #define WRITEBACK_BIT_SET (given & (1 << W_BIT))
3357 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
3358 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
3359 #define PRE_BIT_SET (given & (1 << P_BIT))
3360
3361 /* Print one coprocessor instruction on INFO->STREAM.
3362 Return TRUE if the instuction matched, FALSE if this is not a
3363 recognised coprocessor instruction. */
3364
3365 static bfd_boolean
print_insn_coprocessor(bfd_vma pc,struct disassemble_info * info,long given,bfd_boolean thumb)3366 print_insn_coprocessor (bfd_vma pc,
3367 struct disassemble_info *info,
3368 long given,
3369 bfd_boolean thumb)
3370 {
3371 const struct opcode32 *insn;
3372 void *stream = info->stream;
3373 fprintf_ftype func = info->fprintf_func;
3374 unsigned long mask;
3375 unsigned long value = 0;
3376 int cond;
3377 int cp_num;
3378 struct arm_private_data *private_data = info->private_data;
3379 arm_feature_set allowed_arches = ARM_ARCH_NONE;
3380
3381 ARM_FEATURE_COPY (allowed_arches, private_data->features);
3382
3383 for (insn = coprocessor_opcodes; insn->assembler; insn++)
3384 {
3385 unsigned long u_reg = 16;
3386 bfd_boolean is_unpredictable = FALSE;
3387 // long value_in_comment = 0;
3388 const char *c;
3389
3390 if (ARM_FEATURE_ZERO (insn->arch)) {
3391 switch (insn->value) {
3392 case SENTINEL_IWMMXT_START:
3393 if (info->mach != bfd_mach_arm_XScale && info->mach != bfd_mach_arm_iWMMXt && info->mach != bfd_mach_arm_iWMMXt2) {
3394 do {
3395 insn++;
3396 } while ((!ARM_FEATURE_ZERO (insn->arch)) && insn->value != SENTINEL_IWMMXT_END);
3397 }
3398 continue;
3399
3400 case SENTINEL_IWMMXT_END:
3401 continue;
3402
3403 case SENTINEL_GENERIC_START:
3404 ARM_FEATURE_COPY (allowed_arches, private_data->features);
3405 continue;
3406 }
3407 }
3408
3409 mask = insn->mask;
3410 value = insn->value;
3411 cp_num = (given >> 8) & 0xf;
3412
3413 if (thumb)
3414 {
3415 /* The high 4 bits are 0xe for Arm conditional instructions, and
3416 0xe for arm unconditional instructions. The rest of the
3417 encoding is the same. */
3418 mask |= 0xf0000000;
3419 value |= 0xe0000000;
3420 if (ifthen_state) {
3421 cond = IFTHEN_COND;
3422 } else {
3423 cond = COND_UNCOND;
3424 }
3425 }
3426 else
3427 {
3428 /* Only match unconditional instuctions against unconditional
3429 patterns. */
3430 if ((given & 0xf0000000) == 0xf0000000)
3431 {
3432 mask |= 0xf0000000;
3433 cond = COND_UNCOND;
3434 }
3435 else
3436 {
3437 cond = (given >> 28) & 0xf;
3438 if (cond == 0xe) {
3439 cond = COND_UNCOND;
3440 }
3441 }
3442 }
3443
3444 if ((given & mask) != value) {
3445 continue;
3446 }
3447
3448 if (!ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches)) {
3449 continue;
3450 }
3451
3452 if (insn->value == 0xfe000010 /* mcr2 */
3453 || insn->value == 0xfe100010 /* mrc2 */
3454 || insn->value == 0xfc100000 /* ldc2 */
3455 || insn->value == 0xfc000000) /* stc2 */
3456 {
3457 if (cp_num == 9 || cp_num == 10 || cp_num == 11) {
3458 is_unpredictable = TRUE;
3459 }
3460 }
3461 else if (insn->value == 0x0e000000 /* cdp */
3462 || insn->value == 0xfe000000 /* cdp2 */
3463 || insn->value == 0x0e000010 /* mcr */
3464 || insn->value == 0x0e100010 /* mrc */
3465 || insn->value == 0x0c100000 /* ldc */
3466 || insn->value == 0x0c000000) /* stc */
3467 {
3468 /* Floating-point instructions. */
3469 if (cp_num == 9 || cp_num == 10 || cp_num == 11) {
3470 continue;
3471 }
3472 }
3473
3474 for (c = insn->assembler; *c; c++)
3475 {
3476 if (*c == '%')
3477 {
3478 switch (*++c)
3479 {
3480 case '%':
3481 func (stream, "%%");
3482 break;
3483
3484 case 'A':
3485 {
3486 int rn = (given >> 16) & 0xf;
3487 bfd_vma offset = given & 0xff;
3488
3489 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3490
3491 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
3492 {
3493 /* Not unindexed. The offset is scaled. */
3494 if (cp_num == 9) {
3495 /* vldr.16/vstr.16 will shift the address
3496 left by 1 bit only. */
3497 offset = offset * 2;
3498 } else {
3499 offset = offset * 4;
3500 }
3501
3502 if (NEGATIVE_BIT_SET) {
3503 offset = -offset;
3504 }
3505 // if (rn != 15)
3506 // value_in_comment = offset;
3507 }
3508
3509 if (PRE_BIT_SET)
3510 {
3511 if (offset) {
3512 func (stream, ", 0x%x]%s",
3513 (int)offset,
3514 WRITEBACK_BIT_SET ? "!" : "");
3515 } else if (NEGATIVE_BIT_SET) {
3516 func (stream, ", #-0]");
3517 } else {
3518 func (stream, "]");
3519 }
3520 }
3521 else
3522 {
3523 func (stream, "]");
3524
3525 if (WRITEBACK_BIT_SET)
3526 {
3527 if (offset) {
3528 func (stream, ", 0x%x", (int)offset);
3529 } else if (NEGATIVE_BIT_SET) {
3530 func (stream, ", #-0");
3531 }
3532 }
3533 else
3534 {
3535 func (stream, ", {%s%d}",
3536 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
3537 (int) offset);
3538 // value_in_comment = offset;
3539 }
3540 }
3541 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
3542 {
3543 func (stream, " ; ");
3544 /* For unaligned PCs, apply off-by-alignment
3545 correction. */
3546 info->print_address_func (offset + pc
3547 + info->bytes_per_chunk * 2
3548 - (pc & 3),
3549 info);
3550 }
3551 }
3552 break;
3553
3554 case 'B':
3555 {
3556 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
3557 int offset = (given >> 1) & 0x3f;
3558
3559 if (offset == 1) {
3560 func (stream, "{d%d}", regno);
3561 } else if (regno + offset > 32) {
3562 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
3563 } else {
3564 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
3565 }
3566 }
3567 break;
3568
3569 case 'u':
3570 if (cond != COND_UNCOND) {
3571 is_unpredictable = TRUE;
3572 }
3573
3574 /* Fall through. */
3575 case 'c':
3576 if (cond != COND_UNCOND && cp_num == 9) {
3577 is_unpredictable = TRUE;
3578 }
3579
3580 func (stream, "%s", arm_conditional[cond]);
3581 break;
3582
3583 case 'I':
3584 /* Print a Cirrus/DSP shift immediate. */
3585 /* Immediates are 7bit signed ints with bits 0..3 in
3586 bits 0..3 of opcode and bits 4..6 in bits 5..7
3587 of opcode. */
3588 {
3589 int imm;
3590
3591 imm = (given & 0xf) | ((given & 0xe0) >> 1);
3592
3593 /* Is ``imm'' a negative number? */
3594 if (imm & 0x40) {
3595 imm -= 0x80;
3596 }
3597
3598 func (stream, "%d", imm);
3599 }
3600
3601 break;
3602
3603 case 'F':
3604 switch (given & 0x00408000)
3605 {
3606 case 0:
3607 func (stream, "4");
3608 break;
3609 case 0x8000:
3610 func (stream, "1");
3611 break;
3612 case 0x00400000:
3613 func (stream, "2");
3614 break;
3615 default:
3616 func (stream, "3");
3617 }
3618 break;
3619
3620 case 'P':
3621 switch (given & 0x00080080)
3622 {
3623 case 0:
3624 func (stream, "s");
3625 break;
3626 case 0x80:
3627 func (stream, "d");
3628 break;
3629 case 0x00080000:
3630 func (stream, "e");
3631 break;
3632 default:
3633 func (stream, _("<illegal precision>"));
3634 break;
3635 }
3636 break;
3637
3638 case 'Q':
3639 switch (given & 0x00408000)
3640 {
3641 case 0:
3642 func (stream, "s");
3643 break;
3644 case 0x8000:
3645 func (stream, "d");
3646 break;
3647 case 0x00400000:
3648 func (stream, "e");
3649 break;
3650 default:
3651 func (stream, "p");
3652 break;
3653 }
3654 break;
3655
3656 case 'R':
3657 switch (given & 0x60)
3658 {
3659 case 0:
3660 break;
3661 case 0x20:
3662 func (stream, "p");
3663 break;
3664 case 0x40:
3665 func (stream, "m");
3666 break;
3667 default:
3668 func (stream, "z");
3669 break;
3670 }
3671 break;
3672
3673 case '0': case '1': case '2': case '3': case '4':
3674 case '5': case '6': case '7': case '8': case '9':
3675 {
3676 int width;
3677
3678 c = arm_decode_bitfield (c, given, &value, &width);
3679
3680 switch (*c)
3681 {
3682 case 'R':
3683 if (value == 15) {
3684 is_unpredictable = TRUE;
3685 }
3686 /* Fall through. */
3687 case 'r':
3688 if (c[1] == 'u')
3689 {
3690 /* Eat the 'u' character. */
3691 ++ c;
3692
3693 if (u_reg == value) {
3694 is_unpredictable = TRUE;
3695 }
3696 u_reg = value;
3697 }
3698 func (stream, "%s", arm_regnames [value & 0xf]);
3699
3700 break;
3701 case 'V':
3702 if (given & (1 << 6)) {
3703 goto Q;
3704 }
3705 /* FALLTHROUGH */
3706 case 'D':
3707 func (stream, "d%ld", value);
3708 break;
3709 case 'Q':
3710 Q:
3711 if (value & 1) {
3712 func (stream, "<illegal reg q%ld.5>", value >> 1);
3713 } else {
3714 func (stream, "q%ld", value >> 1);
3715 }
3716 break;
3717 case 'd':
3718 func (stream, "%ld", value);
3719 // value_in_comment = value;
3720 break;
3721 case 'E':
3722 {
3723 /* Converts immediate 8 bit back to float value. */
3724 unsigned floatVal = (value & 0x80) << 24
3725 | (value & 0x3F) << 19
3726 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
3727
3728 /* Quarter float have a maximum value of 31.0.
3729 Get floating point value multiplied by 1e7.
3730 The maximum value stays in limit of a 32-bit int. */
3731 unsigned decVal =
3732 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
3733 (16 + (value & 0xF));
3734
3735 if (!(decVal % 1000000)) {
3736 func (stream, "%ld ; 0x%08x %c%u.%01u", value,
3737 floatVal, value & 0x80 ? '-' : ' ',
3738 decVal / 10000000,
3739 decVal % 10000000 / 1000000);
3740 } else if (!(decVal % 10000)) {
3741 func (stream, "%ld ; 0x%08x %c%u.%03u", value,
3742 floatVal, value & 0x80 ? '-' : ' ',
3743 decVal / 10000000,
3744 decVal % 10000000 / 10000);
3745 } else {
3746 func (stream, "%ld ; 0x%08x %c%u.%07u", value,
3747 floatVal, value & 0x80 ? '-' : ' ',
3748 decVal / 10000000, decVal % 10000000);
3749 }
3750 break;
3751 }
3752 case 'k':
3753 {
3754 int from = (given & (1 << 7)) ? 32 : 16;
3755 func (stream, "%ld", from - value);
3756 }
3757 break;
3758
3759 case 'f':
3760 if (value > 7) {
3761 func (stream, "%s", arm_fp_const[value & 7]);
3762 } else {
3763 func (stream, "f%ld", value);
3764 }
3765 break;
3766
3767 case 'w':
3768 if (width == 2) {
3769 func (stream, "%s", iwmmxt_wwnames[value]);
3770 } else {
3771 func (stream, "%s", iwmmxt_wwssnames[value]);
3772 }
3773 break;
3774
3775 case 'g':
3776 func (stream, "%s", iwmmxt_regnames[value]);
3777 break;
3778 case 'G':
3779 func (stream, "%s", iwmmxt_cregnames[value]);
3780 break;
3781
3782 case 'x':
3783 func (stream, "0x%lx", (value & 0xffffffffUL));
3784 break;
3785
3786 case 'c':
3787 switch (value)
3788 {
3789 case 0:
3790 func (stream, "eq");
3791 break;
3792
3793 case 1:
3794 func (stream, "vs");
3795 break;
3796
3797 case 2:
3798 func (stream, "ge");
3799 break;
3800
3801 case 3:
3802 func (stream, "gt");
3803 break;
3804
3805 default:
3806 func (stream, "??");
3807 break;
3808 }
3809 break;
3810
3811 case '`':
3812 c++;
3813 if (value == 0) {
3814 func (stream, "%c", *c);
3815 }
3816 break;
3817 case '\'':
3818 c++;
3819 if (value == ((1ul << width) - 1)) {
3820 func (stream, "%c", *c);
3821 }
3822 break;
3823 case '?':
3824 func (stream, "%c", c[(1 << width) - (int) value]);
3825 c += 1 << width;
3826 break;
3827 default:
3828 return 0;
3829 }
3830 break;
3831
3832 case 'y':
3833 case 'z':
3834 {
3835 int single = *c++ == 'y';
3836 int regno;
3837
3838 switch (*c)
3839 {
3840 case '4': /* Sm pair */
3841 case '0': /* Sm, Dm */
3842 regno = given & 0x0000000f;
3843 if (single)
3844 {
3845 regno <<= 1;
3846 regno += (given >> 5) & 1;
3847 } else {
3848 regno += ((given >> 5) & 1) << 4;
3849 }
3850 break;
3851
3852 case '1': /* Sd, Dd */
3853 regno = (given >> 12) & 0x0000000f;
3854 if (single)
3855 {
3856 regno <<= 1;
3857 regno += (given >> 22) & 1;
3858 } else {
3859 regno += ((given >> 22) & 1) << 4;
3860 }
3861 break;
3862
3863 case '2': /* Sn, Dn */
3864 regno = (given >> 16) & 0x0000000f;
3865 if (single)
3866 {
3867 regno <<= 1;
3868 regno += (given >> 7) & 1;
3869 } else {
3870 regno += ((given >> 7) & 1) << 4;
3871 }
3872 break;
3873
3874 case '3': /* List */
3875 func (stream, "{");
3876 regno = (given >> 12) & 0x0000000f;
3877 if (single)
3878 {
3879 regno <<= 1;
3880 regno += (given >> 22) & 1;
3881 } else {
3882 regno += ((given >> 22) & 1) << 4;
3883 }
3884 break;
3885
3886 default:
3887 return 0;
3888 }
3889
3890 func (stream, "%c%d", single ? 's' : 'd', regno);
3891
3892 if (*c == '3')
3893 {
3894 int count = given & 0xff;
3895
3896 if (single == 0) {
3897 count >>= 1;
3898 }
3899
3900 if (--count)
3901 {
3902 func (stream, "-%c%d",
3903 single ? 's' : 'd',
3904 regno + count);
3905 }
3906
3907 func (stream, "}");
3908 } else if (*c == '4') {
3909 func (stream, ", %c%d", single ? 's' : 'd',
3910 regno + 1);
3911 }
3912 }
3913 break;
3914
3915 case 'L':
3916 switch (given & 0x00400100)
3917 {
3918 case 0x00000000: func (stream, "b"); break;
3919 case 0x00400000: func (stream, "h"); break;
3920 case 0x00000100: func (stream, "w"); break;
3921 case 0x00400100: func (stream, "d"); break;
3922 default:
3923 break;
3924 }
3925 break;
3926
3927 case 'Z':
3928 {
3929 /* given (20, 23) | given (0, 3) */
3930 value = ((given >> 16) & 0xf0) | (given & 0xf);
3931 func (stream, "%d", (int) value);
3932 }
3933 break;
3934
3935 case 'l':
3936 /* This is like the 'A' operator, except that if
3937 the width field "M" is zero, then the offset is
3938 *not* multiplied by four. */
3939 {
3940 int offset = given & 0xff;
3941 int multiplier = (given & 0x00000100) ? 4 : 1;
3942
3943 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3944
3945 #if 0
3946 if (multiplier > 1)
3947 {
3948 value_in_comment = offset * multiplier;
3949 if (NEGATIVE_BIT_SET)
3950 value_in_comment = -value_in_comment;
3951 }
3952 #endif
3953
3954 if (offset)
3955 {
3956 if (PRE_BIT_SET) {
3957 func (stream, ", %s%d]%s",
3958 NEGATIVE_BIT_SET ? "-" : "",
3959 offset * multiplier,
3960 WRITEBACK_BIT_SET ? "!" : "");
3961 } else {
3962 func (stream, "], %s%d",
3963 NEGATIVE_BIT_SET ? "-" : "",
3964 offset * multiplier);
3965 }
3966 } else {
3967 func (stream, "]");
3968 }
3969 }
3970 break;
3971
3972 case 'r':
3973 {
3974 int imm4 = (given >> 4) & 0xf;
3975 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
3976 int ubit = ! NEGATIVE_BIT_SET;
3977 const char *rm = arm_regnames [given & 0xf];
3978 const char *rn = arm_regnames [(given >> 16) & 0xf];
3979
3980 switch (puw_bits)
3981 {
3982 case 1:
3983 case 3:
3984 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
3985 if (imm4) {
3986 func (stream, ", lsl %d", imm4);
3987 }
3988 break;
3989
3990 case 4:
3991 case 5:
3992 case 6:
3993 case 7:
3994 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
3995 if (imm4 > 0) {
3996 func (stream, ", lsl %d", imm4);
3997 }
3998 func (stream, "]");
3999 if (puw_bits == 5 || puw_bits == 7) {
4000 func (stream, "!");
4001 }
4002 break;
4003
4004 default:
4005 func (stream, "INVALID");
4006 }
4007 }
4008 break;
4009
4010 case 'i':
4011 {
4012 long imm5;
4013 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
4014 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
4015 }
4016 break;
4017 }
4018 }
4019 } else {
4020 func (stream, "%c", *c);
4021 }
4022 }
4023
4024 #if 0
4025 if (value_in_comment > 32 || value_in_comment < -16)
4026 func (stream, " ; 0x%lx", (value_in_comment & 0xffffffffUL));
4027 #endif
4028
4029 if (is_unpredictable) {
4030 func (stream, UNPREDICTABLE_INSTRUCTION);
4031 }
4032
4033 return TRUE;
4034 }
4035 return FALSE;
4036 }
4037
4038 /* Decodes and prints ARM addressing modes. Returns the offset
4039 used in the address, if any, if it is worthwhile printing the
4040 offset as a hexadecimal value in a comment at the end of the
4041 line of disassembly. */
4042
4043 static signed long
print_arm_address(bfd_vma pc,struct disassemble_info * info,long given)4044 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
4045 {
4046 void *stream = info->stream;
4047 fprintf_ftype func = info->fprintf_func;
4048 bfd_vma offset = 0;
4049
4050 if (((given & 0x000f0000) == 0x000f0000)
4051 && ((given & 0x02000000) == 0))
4052 {
4053 offset = given & 0xfff;
4054
4055 func (stream, "[pc");
4056
4057 if (PRE_BIT_SET)
4058 {
4059 /* Pre-indexed. Elide offset of positive zero when
4060 non-writeback. */
4061 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset) {
4062 func (stream, ", %s%d", NEGATIVE_BIT_SET ? "-" : "", (int)offset);
4063 }
4064
4065 if (NEGATIVE_BIT_SET) {
4066 offset = -offset;
4067 }
4068
4069 offset += pc + 8;
4070
4071 /* Cope with the possibility of write-back
4072 being used. Probably a very dangerous thing
4073 for the programmer to do, but who are we to
4074 argue ? */
4075 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
4076 }
4077 else /* Post indexed. */
4078 {
4079 func (stream, "], %s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4080
4081 /* Ie ignore the offset. */
4082 offset = pc + 8;
4083 }
4084
4085 func (stream, " ; ");
4086 info->print_address_func (offset, info);
4087 offset = 0;
4088 }
4089 else
4090 {
4091 func (stream, "[%s",
4092 arm_regnames[(given >> 16) & 0xf]);
4093
4094 if (PRE_BIT_SET)
4095 {
4096 if ((given & 0x02000000) == 0)
4097 {
4098 /* Elide offset of positive zero when non-writeback. */
4099 offset = given & 0xfff;
4100 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset) {
4101 func (stream, ", %s%d", NEGATIVE_BIT_SET ? "-" : "", (int)offset);
4102 }
4103 }
4104 else
4105 {
4106 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
4107 arm_decode_shift (given, func, stream, TRUE);
4108 }
4109
4110 func (stream, "]%s",
4111 WRITEBACK_BIT_SET ? "!" : "");
4112 }
4113 else
4114 {
4115 if ((given & 0x02000000) == 0)
4116 {
4117 /* Always show offset. */
4118 offset = given & 0xfff;
4119 func (stream, "], %s%d",
4120 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4121 }
4122 else
4123 {
4124 func (stream, "], %s",
4125 NEGATIVE_BIT_SET ? "-" : "");
4126 arm_decode_shift (given, func, stream, TRUE);
4127 }
4128 }
4129 if (NEGATIVE_BIT_SET) {
4130 offset = -offset;
4131 }
4132 }
4133
4134 return (signed long) offset;
4135 }
4136
4137 /* Print one neon instruction on INFO->STREAM.
4138 Return TRUE if the instuction matched, FALSE if this is not a
4139 recognised neon instruction. */
4140
4141 static bfd_boolean
print_insn_neon(struct disassemble_info * info,long given,bfd_boolean thumb)4142 print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
4143 {
4144 const struct opcode32 *insn;
4145 void *stream = info->stream;
4146 fprintf_ftype func = info->fprintf_func;
4147
4148 if (thumb)
4149 {
4150 if ((given & 0xef000000) == 0xef000000)
4151 {
4152 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
4153 unsigned long bit28 = given & (1 << 28);
4154
4155 given &= 0x00ffffff;
4156 if (bit28) {
4157 given |= 0xf3000000;
4158 } else {
4159 given |= 0xf2000000;
4160 }
4161 } else if ((given & 0xff000000) == 0xf9000000) {
4162 given ^= 0xf9000000 ^ 0xf4000000;
4163 } else {
4164 return FALSE;
4165 }
4166 }
4167
4168 for (insn = neon_opcodes; insn->assembler; insn++)
4169 {
4170 if ((given & insn->mask) == insn->value)
4171 {
4172 // signed long value_in_comment = 0;
4173 bfd_boolean is_unpredictable = FALSE;
4174 const char *c;
4175
4176 for (c = insn->assembler; *c; c++)
4177 {
4178 if (*c == '%')
4179 {
4180 switch (*++c)
4181 {
4182 case '%':
4183 func (stream, "%%");
4184 break;
4185
4186 case 'u':
4187 if (thumb && ifthen_state) {
4188 is_unpredictable = TRUE;
4189 }
4190
4191 /* Fall through. */
4192 case 'c':
4193 if (thumb && ifthen_state) {
4194 func (stream, "%s", arm_conditional[IFTHEN_COND]);
4195 }
4196 break;
4197
4198 case 'A':
4199 {
4200 static const unsigned char enc[16] =
4201 {
4202 0x4, 0x14, /* st4 0,1 */
4203 0x4, /* st1 2 */
4204 0x4, /* st2 3 */
4205 0x3, /* st3 4 */
4206 0x13, /* st3 5 */
4207 0x3, /* st1 6 */
4208 0x1, /* st1 7 */
4209 0x2, /* st2 8 */
4210 0x12, /* st2 9 */
4211 0x2, /* st1 10 */
4212 0, 0, 0, 0, 0
4213 };
4214 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4215 int rn = ((given >> 16) & 0xf);
4216 int rm = ((given >> 0) & 0xf);
4217 int align = ((given >> 4) & 0x3);
4218 int type = ((given >> 8) & 0xf);
4219 int n = enc[type] & 0xf;
4220 int stride = (enc[type] >> 4) + 1;
4221 int ix;
4222
4223 func (stream, "{");
4224 if (stride > 1) {
4225 for (ix = 0; ix != n; ix++) {
4226 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
4227 }
4228 } else if (n == 1) {
4229 func (stream, "d%d", rd);
4230 } else {
4231 func (stream, "d%d-d%d", rd, rd + n - 1);
4232 }
4233 func (stream, "}, [%s", arm_regnames[rn]);
4234 if (align) {
4235 func (stream, " :%d", 32 << align);
4236 }
4237 func (stream, "]");
4238 if (rm == 0xd) {
4239 func (stream, "!");
4240 } else if (rm != 0xf) {
4241 func (stream, ", %s", arm_regnames[rm]);
4242 }
4243 }
4244 break;
4245
4246 case 'B':
4247 {
4248 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4249 int rn = ((given >> 16) & 0xf);
4250 int rm = ((given >> 0) & 0xf);
4251 int idx_align = ((given >> 4) & 0xf);
4252 int align = 0;
4253 int size = ((given >> 10) & 0x3);
4254 int idx = idx_align >> (size + 1);
4255 int length = ((given >> 8) & 3) + 1;
4256 int stride = 1;
4257 int i;
4258
4259 if (length > 1 && size > 0) {
4260 stride = (idx_align & (1 << size)) ? 2 : 1;
4261 }
4262
4263 switch (length)
4264 {
4265 case 1:
4266 {
4267 int amask = (1 << size) - 1;
4268 if ((idx_align & (1 << size)) != 0) {
4269 return FALSE;
4270 }
4271 if (size > 0)
4272 {
4273 if ((idx_align & amask) == amask) {
4274 align = 8 << size;
4275 } else if ((idx_align & amask) != 0) {
4276 return FALSE;
4277 }
4278 }
4279 }
4280 break;
4281
4282 case 2:
4283 if (size == 2 && (idx_align & 2) != 0) {
4284 return FALSE;
4285 }
4286 align = (idx_align & 1) ? 16 << size : 0;
4287 break;
4288
4289 case 3:
4290 if ((size == 2 && (idx_align & 3) != 0) || (idx_align & 1) != 0) {
4291 return FALSE;
4292 }
4293 break;
4294
4295 case 4:
4296 if (size == 2)
4297 {
4298 if ((idx_align & 3) == 3) {
4299 return FALSE;
4300 }
4301 align = (idx_align & 3) * 64;
4302 } else {
4303 align = (idx_align & 1) ? 32 << size : 0;
4304 }
4305 break;
4306 }
4307
4308 func (stream, "{");
4309 for (i = 0; i < length; i++) {
4310 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
4311 rd + i * stride, idx);
4312 }
4313 func (stream, "}, [%s", arm_regnames[rn]);
4314 if (align) {
4315 func (stream, " :%d", align);
4316 }
4317 func (stream, "]");
4318 if (rm == 0xd) {
4319 func (stream, "!");
4320 } else if (rm != 0xf) {
4321 func (stream, ", %s", arm_regnames[rm]);
4322 }
4323 }
4324 break;
4325
4326 case 'C':
4327 {
4328 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4329 int rn = ((given >> 16) & 0xf);
4330 int rm = ((given >> 0) & 0xf);
4331 int align = ((given >> 4) & 0x1);
4332 int size = ((given >> 6) & 0x3);
4333 int type = ((given >> 8) & 0x3);
4334 int n = type + 1;
4335 int stride = ((given >> 5) & 0x1);
4336 int ix;
4337
4338 if (stride && (n == 1)) {
4339 n++;
4340 } else {
4341 stride++;
4342 }
4343
4344 func (stream, "{");
4345 if (stride > 1) {
4346 for (ix = 0; ix != n; ix++) {
4347 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
4348 }
4349 } else if (n == 1) {
4350 func (stream, "d%d[]", rd);
4351 } else {
4352 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
4353 }
4354 func (stream, "}, [%s", arm_regnames[rn]);
4355 if (align)
4356 {
4357 align = (8 * (type + 1)) << size;
4358 if (type == 3) {
4359 align = (size > 1) ? align >> 1 : align;
4360 }
4361 if (type == 2 || (type == 0 && !size)) {
4362 func (stream, " :<bad align %d>", align);
4363 } else {
4364 func (stream, " :%d", align);
4365 }
4366 }
4367 func (stream, "]");
4368 if (rm == 0xd) {
4369 func (stream, "!");
4370 } else if (rm != 0xf) {
4371 func (stream, ", %s", arm_regnames[rm]);
4372 }
4373 }
4374 break;
4375
4376 case 'D':
4377 {
4378 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
4379 int size = (given >> 20) & 3;
4380 int reg = raw_reg & ((4 << size) - 1);
4381 int ix = raw_reg >> size >> 2;
4382
4383 func (stream, "d%d[%d]", reg, ix);
4384 }
4385 break;
4386
4387 case 'E':
4388 /* Neon encoded constant for mov, mvn, vorr, vbic. */
4389 {
4390 int bits = 0;
4391 int cmode = (given >> 8) & 0xf;
4392 int op = (given >> 5) & 0x1;
4393 unsigned long value = 0, hival = 0;
4394 unsigned shift;
4395 int size = 0;
4396 int isfloat = 0;
4397
4398 bits |= ((given >> 24) & 1) << 7;
4399 bits |= ((given >> 16) & 7) << 4;
4400 bits |= ((given >> 0) & 15) << 0;
4401
4402 if (cmode < 8)
4403 {
4404 shift = (cmode >> 1) & 3;
4405 value = (unsigned long) bits << (8 * shift);
4406 size = 32;
4407 }
4408 else if (cmode < 12)
4409 {
4410 shift = (cmode >> 1) & 1;
4411 value = (unsigned long) bits << (8 * shift);
4412 size = 16;
4413 }
4414 else if (cmode < 14)
4415 {
4416 shift = (cmode & 1) + 1;
4417 value = (unsigned long) bits << (8 * shift);
4418 value |= (1ul << (8 * shift)) - 1;
4419 size = 32;
4420 }
4421 else if (cmode == 14)
4422 {
4423 if (op)
4424 {
4425 /* Bit replication into bytes. */
4426 int ix;
4427 unsigned long mask;
4428
4429 value = 0;
4430 hival = 0;
4431 for (ix = 7; ix >= 0; ix--)
4432 {
4433 mask = ((bits >> ix) & 1) ? 0xff : 0;
4434 if (ix <= 3) {
4435 value = (value << 8) | mask;
4436 } else {
4437 hival = (hival << 8) | mask;
4438 }
4439 }
4440 size = 64;
4441 }
4442 else
4443 {
4444 /* Byte replication. */
4445 value = (unsigned long) bits;
4446 size = 8;
4447 }
4448 }
4449 else if (!op)
4450 {
4451 /* Floating point encoding. */
4452 int tmp;
4453
4454 value = (unsigned long) (bits & 0x7f) << 19;
4455 value |= (unsigned long) (bits & 0x80) << 24;
4456 tmp = bits & 0x40 ? 0x3c : 0x40;
4457 value |= (unsigned long) tmp << 24;
4458 size = 32;
4459 isfloat = 1;
4460 }
4461 else
4462 {
4463 func (stream, "<illegal constant %.8x:%x:%x>",
4464 bits, cmode, op);
4465 size = 32;
4466 break;
4467 }
4468 switch (size)
4469 {
4470 case 8:
4471 // func (stream, "%ld ; 0x%.2lx", value, value);
4472 func (stream, "%ld", value);
4473 break;
4474
4475 case 16:
4476 // func (stream, "%ld ; 0x%.4lx", value, value);
4477 func (stream, "%ld", value);
4478 break;
4479
4480 case 32:
4481 if (isfloat)
4482 {
4483 unsigned char valbytes[4];
4484 double fvalue;
4485
4486 /* Do this a byte at a time so we don't have to
4487 worry about the host's endianness. */
4488 valbytes[0] = value & 0xff;
4489 valbytes[1] = (value >> 8) & 0xff;
4490 valbytes[2] = (value >> 16) & 0xff;
4491 valbytes[3] = (value >> 24) & 0xff;
4492
4493 floatformat_to_double
4494 (& floatformat_ieee_single_little, valbytes,
4495 & fvalue);
4496
4497 func (stream, "%.7g ; 0x%.8lx", fvalue,
4498 value);
4499 } else {
4500 func (stream, "%ld ; 0x%.8lx",
4501 (long)(((value & 0x80000000L) != 0)
4502 ? value | ~0xffffffffL
4503 : value),
4504 value);
4505 }
4506 break;
4507
4508 case 64:
4509 func (stream, "#0x%.8lx%.8lx", hival, value);
4510 break;
4511 }
4512 }
4513 break;
4514
4515 case 'F':
4516 {
4517 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
4518 int num = (given >> 8) & 0x3;
4519
4520 if (!num) {
4521 func (stream, "{d%d}", regno);
4522 } else if (num + regno >= 32) {
4523 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
4524 } else {
4525 func (stream, "{d%d-d%d}", regno, regno + num);
4526 }
4527 }
4528 break;
4529
4530
4531 case '0': case '1': case '2': case '3': case '4':
4532 case '5': case '6': case '7': case '8': case '9':
4533 {
4534 int width;
4535 unsigned long value;
4536
4537 c = arm_decode_bitfield (c, given, &value, &width);
4538
4539 switch (*c)
4540 {
4541 case 'r':
4542 func (stream, "%s", arm_regnames[value]);
4543 break;
4544 case 'd':
4545 func (stream, "%ld", value);
4546 // value_in_comment = value;
4547 break;
4548 case 'e':
4549 func (stream, "%ld", (1ul << width) - value);
4550 break;
4551
4552 case 'S':
4553 case 'T':
4554 case 'U':
4555 /* Various width encodings. */
4556 {
4557 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
4558 int limit;
4559 unsigned low, high;
4560
4561 c++;
4562 if (*c >= '0' && *c <= '9') {
4563 limit = *c - '0';
4564 } else if (*c >= 'a' && *c <= 'f') {
4565 limit = *c - 'a' + 10;
4566 } else {
4567 return FALSE;
4568 }
4569 low = limit >> 2;
4570 high = limit & 3;
4571
4572 if (value < low || value > high) {
4573 func (stream, "<illegal width %d>", base << value);
4574 } else {
4575 func (stream, "%d", base << value);
4576 }
4577 }
4578 break;
4579 case 'R':
4580 if (given & (1 << 6)) {
4581 goto Q;
4582 }
4583 /* FALLTHROUGH */
4584 case 'D':
4585 func (stream, "d%ld", value);
4586 break;
4587 case 'Q':
4588 Q:
4589 if (value & 1) {
4590 func (stream, "<illegal reg q%ld.5>", value >> 1);
4591 } else {
4592 func (stream, "q%ld", value >> 1);
4593 }
4594 break;
4595
4596 case '`':
4597 c++;
4598 if (value == 0) {
4599 func (stream, "%c", *c);
4600 }
4601 break;
4602 case '\'':
4603 c++;
4604 if (value == ((1ul << width) - 1)) {
4605 func (stream, "%c", *c);
4606 }
4607 break;
4608 case '?':
4609 func (stream, "%c", c[(1 << width) - (int) value]);
4610 c += 1 << width;
4611 break;
4612 default:
4613 return FALSE;
4614 }
4615 break;
4616
4617 default:
4618 return FALSE;
4619 }
4620 }
4621 } else {
4622 func (stream, "%c", *c);
4623 }
4624 }
4625
4626 #if 0
4627 if (value_in_comment > 32 || value_in_comment < -16)
4628 func (stream, " ; 0x%lx", value_in_comment);
4629 #endif
4630
4631 if (is_unpredictable) {
4632 func (stream, UNPREDICTABLE_INSTRUCTION);
4633 }
4634
4635 return TRUE;
4636 }
4637 }
4638 return FALSE;
4639 }
4640
4641 /* Return the name of a v7A special register. */
4642
4643 static const char *
banked_regname(unsigned reg)4644 banked_regname (unsigned reg)
4645 {
4646 switch (reg)
4647 {
4648 case 15: return "CPSR";
4649 case 32: return "R8_usr";
4650 case 33: return "R9_usr";
4651 case 34: return "R10_usr";
4652 case 35: return "R11_usr";
4653 case 36: return "R12_usr";
4654 case 37: return "SP_usr";
4655 case 38: return "LR_usr";
4656 case 40: return "R8_fiq";
4657 case 41: return "R9_fiq";
4658 case 42: return "R10_fiq";
4659 case 43: return "R11_fiq";
4660 case 44: return "R12_fiq";
4661 case 45: return "SP_fiq";
4662 case 46: return "LR_fiq";
4663 case 48: return "LR_irq";
4664 case 49: return "SP_irq";
4665 case 50: return "LR_svc";
4666 case 51: return "SP_svc";
4667 case 52: return "LR_abt";
4668 case 53: return "SP_abt";
4669 case 54: return "LR_und";
4670 case 55: return "SP_und";
4671 case 60: return "LR_mon";
4672 case 61: return "SP_mon";
4673 case 62: return "ELR_hyp";
4674 case 63: return "SP_hyp";
4675 case 79: return "SPSR";
4676 case 110: return "SPSR_fiq";
4677 case 112: return "SPSR_irq";
4678 case 114: return "SPSR_svc";
4679 case 116: return "SPSR_abt";
4680 case 118: return "SPSR_und";
4681 case 124: return "SPSR_mon";
4682 case 126: return "SPSR_hyp";
4683 default: return NULL;
4684 }
4685 }
4686
4687 /* Return the name of the DMB/DSB option. */
4688 static const char *
data_barrier_option(unsigned option)4689 data_barrier_option (unsigned option)
4690 {
4691 switch (option & 0xf)
4692 {
4693 case 0xf: return "sy";
4694 case 0xe: return "st";
4695 case 0xd: return "ld";
4696 case 0xb: return "ish";
4697 case 0xa: return "ishst";
4698 case 0x9: return "ishld";
4699 case 0x7: return "un";
4700 case 0x6: return "unst";
4701 case 0x5: return "nshld";
4702 case 0x3: return "osh";
4703 case 0x2: return "oshst";
4704 case 0x1: return "oshld";
4705 default: return NULL;
4706 }
4707 }
4708
4709 /* Print one ARM instruction from PC on INFO->STREAM. */
4710
4711 static void
print_insn_arm(bfd_vma pc,struct disassemble_info * info,long given)4712 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
4713 {
4714 const struct opcode32 *insn;
4715 void *stream = info->stream;
4716 fprintf_ftype func = info->fprintf_func;
4717 struct arm_private_data *private_data = info->private_data;
4718
4719 if (print_insn_coprocessor (pc, info, given, FALSE)) {
4720 return;
4721 }
4722
4723 if (print_insn_neon (info, given, FALSE)) {
4724 return;
4725 }
4726
4727 for (insn = arm_opcodes; insn->assembler; insn++)
4728 {
4729 if ((given & insn->mask) != insn->value) {
4730 continue;
4731 }
4732
4733 if (!ARM_CPU_HAS_FEATURE (insn->arch, private_data->features)) {
4734 continue;
4735 }
4736
4737 /* Special case: an instruction with all bits set in the condition field
4738 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
4739 or by the catchall at the end of the table. */
4740 if ((given & 0xF0000000) != 0xF0000000 || (insn->mask & 0xF0000000) == 0xF0000000 || (insn->mask == 0 && insn->value == 0)) {
4741 unsigned long u_reg = 16;
4742 unsigned long U_reg = 16;
4743 bfd_boolean is_unpredictable = FALSE;
4744 signed long value_in_comment = 0;
4745 const char *c;
4746
4747 for (c = insn->assembler; *c; c++) {
4748 if (*c == '%') {
4749 bfd_boolean allow_unpredictable = FALSE;
4750
4751 switch (*++c) {
4752 case '%':
4753 func (stream, "%%");
4754 break;
4755
4756 case 'a':
4757 value_in_comment = print_arm_address (pc, info, given);
4758 break;
4759
4760 case 'P':
4761 /* Set P address bit and use normal address
4762 printing routine. */
4763 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
4764 break;
4765
4766 case 'S':
4767 allow_unpredictable = TRUE;
4768 /* Fall through. */
4769 case 's':
4770 if ((given & 0x004f0000) == 0x004f0000) {
4771 /* PC relative with immediate offset. */
4772 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
4773
4774 if (PRE_BIT_SET) {
4775 /* Elide positive zero offset. */
4776 if (offset || NEGATIVE_BIT_SET) {
4777 func (stream, "[pc, %s%d] ; ",
4778 NEGATIVE_BIT_SET ? "-" : "", (int)offset);
4779 } else {
4780 func (stream, "[pc] ; ");
4781 }
4782 if (NEGATIVE_BIT_SET) {
4783 offset = -offset;
4784 }
4785 info->print_address_func (offset + pc + 8, info);
4786 } else {
4787 /* Always show the offset. */
4788 func (stream, "[pc], %s%d",
4789 NEGATIVE_BIT_SET ? "-" : "", (int)offset);
4790 if (!allow_unpredictable) {
4791 is_unpredictable = TRUE;
4792 }
4793 }
4794 } else {
4795 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
4796
4797 func (stream, "[%s",
4798 arm_regnames[(given >> 16) & 0xf]);
4799
4800 if (PRE_BIT_SET) {
4801 if (IMMEDIATE_BIT_SET) {
4802 /* Elide offset for non-writeback
4803 positive zero. */
4804 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset) {
4805 func (stream, ", %s%d",
4806 NEGATIVE_BIT_SET ? "-" : "", offset);
4807 }
4808
4809 if (NEGATIVE_BIT_SET) {
4810 offset = -offset;
4811 }
4812
4813 value_in_comment = offset;
4814 } else {
4815 /* Register Offset or Register Pre-Indexed. */
4816 func (stream, ", %s%s",
4817 NEGATIVE_BIT_SET ? "-" : "",
4818 arm_regnames[given & 0xf]);
4819
4820 /* Writing back to the register that is the source/
4821 destination of the load/store is unpredictable. */
4822 if (!allow_unpredictable && WRITEBACK_BIT_SET && ((given & 0xf) == ((given >> 12) & 0xf))) {
4823 is_unpredictable = TRUE;
4824 }
4825 }
4826
4827 func (stream, "]%s",
4828 WRITEBACK_BIT_SET ? "!" : "");
4829 } else {
4830 if (IMMEDIATE_BIT_SET) {
4831 /* Immediate Post-indexed. */
4832 /* PR 10924: Offset must be printed, even if it is zero. */
4833 func (stream, "], %s%d",
4834 NEGATIVE_BIT_SET ? "-" : "", offset);
4835 if (NEGATIVE_BIT_SET) {
4836 offset = -offset;
4837 }
4838 value_in_comment = offset;
4839 } else {
4840 /* Register Post-indexed. */
4841 func (stream, "], %s%s",
4842 NEGATIVE_BIT_SET ? "-" : "",
4843 arm_regnames[given & 0xf]);
4844
4845 /* Writing back to the register that is the source/
4846 destination of the load/store is unpredictable. */
4847 if (!allow_unpredictable && (given & 0xf) == ((given >> 12) & 0xf)) {
4848 is_unpredictable = TRUE;
4849 }
4850 }
4851
4852 if (!allow_unpredictable) {
4853 /* Writeback is automatically implied by post- addressing.
4854 Setting the W bit is unnecessary and ARM specify it as
4855 being unpredictable. */
4856 if (WRITEBACK_BIT_SET
4857 /* Specifying the PC register as the post-indexed
4858 registers is also unpredictable. */
4859 || (!IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf))) {
4860 is_unpredictable = TRUE;
4861 }
4862 }
4863 }
4864 }
4865 break;
4866
4867 case 'b': {
4868 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
4869 info->print_address_func (disp * 4 + pc + 8, info);
4870 } break;
4871
4872 case 'c':
4873 if (((given >> 28) & 0xf) != 0xe) {
4874 func (stream, "%s",
4875 arm_conditional[(given >> 28) & 0xf]);
4876 }
4877 break;
4878
4879 case 'm': {
4880 int started = 0;
4881 int reg;
4882
4883 func (stream, "{");
4884 for (reg = 0; reg < 16; reg++) {
4885 if ((given & (1 << reg)) != 0) {
4886 if (started) {
4887 func (stream, ", ");
4888 }
4889 started = 1;
4890 func (stream, "%s", arm_regnames[reg]);
4891 }
4892 }
4893 func (stream, "}");
4894 if (!started) {
4895 is_unpredictable = TRUE;
4896 }
4897 } break;
4898
4899 case 'q':
4900 arm_decode_shift (given, func, stream, FALSE);
4901 break;
4902
4903 case 'o':
4904 if ((given & 0x02000000) != 0) {
4905 unsigned int rotate = (given & 0xf00) >> 7;
4906 unsigned int immed = (given & 0xff);
4907 unsigned int a, i;
4908
4909 a = (((immed << (32 - rotate)) | (immed >> rotate)) & 0xffffffff);
4910 /* If there is another encoding with smaller rotate,
4911 the rotate should be specified directly. */
4912 for (i = 0; i < 32; i += 2) {
4913 if ((a << i | a >> (32 - i)) <= 0xff) {
4914 break;
4915 }
4916 }
4917
4918 if (i != rotate) {
4919 func (stream, "%d, %d", immed, rotate);
4920 } else {
4921 func (stream, "%d", a);
4922 }
4923 value_in_comment = a;
4924 } else {
4925 arm_decode_shift (given, func, stream, TRUE);
4926 }
4927 break;
4928
4929 case 'p':
4930 if ((given & 0x0000f000) == 0x0000f000) {
4931 arm_feature_set arm_ext_v6 =
4932 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
4933
4934 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
4935 mechanism for setting PSR flag bits. They are
4936 obsolete in V6 onwards. */
4937 if (!ARM_CPU_HAS_FEATURE (private_data->features,
4938 arm_ext_v6)) {
4939 func (stream, "p");
4940 } else {
4941 is_unpredictable = TRUE;
4942 }
4943 }
4944 break;
4945
4946 case 't':
4947 if ((given & 0x01200000) == 0x00200000) {
4948 func (stream, "t");
4949 }
4950 break;
4951
4952 case 'A': {
4953 int offset = given & 0xff;
4954
4955 value_in_comment = offset * 4;
4956 if (NEGATIVE_BIT_SET) {
4957 value_in_comment = -value_in_comment;
4958 }
4959
4960 func (stream, "[%s", arm_regnames[(given >> 16) & 0xf]);
4961
4962 if (PRE_BIT_SET) {
4963 if (offset) {
4964 func (stream, ", %d]%s",
4965 (int)value_in_comment,
4966 WRITEBACK_BIT_SET ? "!" : "");
4967 } else {
4968 func (stream, "]");
4969 }
4970 } else {
4971 func (stream, "]");
4972
4973 if (WRITEBACK_BIT_SET) {
4974 if (offset) {
4975 func (stream, ", %d", (int)value_in_comment);
4976 }
4977 } else {
4978 func (stream, ", {%d}", (int)offset);
4979 value_in_comment = offset;
4980 }
4981 }
4982 } break;
4983
4984 case 'B':
4985 /* Print ARM V5 BLX(1) address: pc+25 bits. */
4986 {
4987 bfd_vma address;
4988 bfd_vma offset = 0;
4989
4990 if (!NEGATIVE_BIT_SET) {
4991 /* Is signed, hi bits should be ones. */
4992 offset = (-1) ^ 0x00ffffff;
4993 }
4994
4995 /* Offset is (SignExtend(offset field)<<2). */
4996 offset += given & 0x00ffffff;
4997 offset <<= 2;
4998 address = offset + pc + 8;
4999
5000 if (given & 0x01000000) {
5001 /* H bit allows addressing to 2-byte boundaries. */
5002 address += 2;
5003 }
5004
5005 info->print_address_func (address, info);
5006 }
5007 break;
5008
5009 case 'C':
5010 if ((given & 0x02000200) == 0x200) {
5011 const char *name;
5012 unsigned sysm = (given & 0x004f0000) >> 16;
5013
5014 sysm |= (given & 0x300) >> 4;
5015 name = banked_regname (sysm);
5016
5017 if (name != NULL) {
5018 func (stream, "%s", name);
5019 } else {
5020 func (stream, "(UNDEF: %lu)", (unsigned long)sysm);
5021 }
5022 } else {
5023 func (stream, "%cPSR_",
5024 (given & 0x00400000) ? 'S' : 'C');
5025 if (given & 0x80000) {
5026 func (stream, "f");
5027 }
5028 if (given & 0x40000) {
5029 func (stream, "s");
5030 }
5031 if (given & 0x20000) {
5032 func (stream, "x");
5033 }
5034 if (given & 0x10000) {
5035 func (stream, "c");
5036 }
5037 }
5038 break;
5039
5040 case 'U':
5041 if ((given & 0xf0) == 0x60) {
5042 switch (given & 0xf) {
5043 case 0xf: func (stream, "sy"); break;
5044 default:
5045 func (stream, "%d", (int)given & 0xf);
5046 break;
5047 }
5048 } else {
5049 const char *opt = data_barrier_option (given & 0xf);
5050 if (opt != NULL) {
5051 func (stream, "%s", opt);
5052 } else {
5053 func (stream, "%d", (int)given & 0xf);
5054 }
5055 }
5056 break;
5057
5058 case '0':
5059 case '1':
5060 case '2':
5061 case '3':
5062 case '4':
5063 case '5':
5064 case '6':
5065 case '7':
5066 case '8':
5067 case '9': {
5068 int width;
5069 unsigned long value;
5070
5071 c = arm_decode_bitfield (c, given, &value, &width);
5072
5073 switch (*c) {
5074 case 'R':
5075 if (value == 15) {
5076 is_unpredictable = TRUE;
5077 }
5078 /* Fall through. */
5079 case 'r':
5080 case 'T':
5081 /* We want register + 1 when decoding T. */
5082 if (*c == 'T') {
5083 ++value;
5084 }
5085
5086 if (c[1] == 'u') {
5087 /* Eat the 'u' character. */
5088 ++c;
5089
5090 if (u_reg == value) {
5091 is_unpredictable = TRUE;
5092 }
5093 u_reg = value;
5094 }
5095 if (c[1] == 'U') {
5096 /* Eat the 'U' character. */
5097 ++c;
5098
5099 if (U_reg == value) {
5100 is_unpredictable = TRUE;
5101 }
5102 U_reg = value;
5103 }
5104 func (stream, "%s", arm_regnames[value]);
5105 break;
5106 case 'd':
5107 func (stream, "%ld", value);
5108 value_in_comment = value;
5109 break;
5110 case 'b':
5111 func (stream, "%ld", value * 8);
5112 value_in_comment = value * 8;
5113 break;
5114 case 'W':
5115 func (stream, "%ld", value + 1);
5116 value_in_comment = value + 1;
5117 break;
5118 case 'x':
5119 func (stream, "0x%08lx", value);
5120
5121 /* Some SWI instructions have special
5122 meanings. */
5123 if ((given & 0x0fffffff) == 0x0FF00000) {
5124 func (stream, " ; IMB");
5125 } else if ((given & 0x0fffffff) == 0x0FF00001) {
5126 func (stream, " ; IMBRange");
5127 }
5128 break;
5129 case 'X':
5130 func (stream, "%01lx", value & 0xf);
5131 value_in_comment = value;
5132 break;
5133 case '`':
5134 c++;
5135 if (value == 0) {
5136 func (stream, "%c", *c);
5137 }
5138 break;
5139 case '\'':
5140 c++;
5141 if (value == ((1ul << width) - 1)) {
5142 func (stream, "%c", *c);
5143 }
5144 break;
5145 case '?':
5146 func (stream, "%c", c[(1 << width) - (int)value]);
5147 c += 1 << width;
5148 break;
5149 default:
5150 return;
5151 }
5152 break;
5153
5154 case 'e': {
5155 int imm;
5156
5157 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
5158 func (stream, "%d", imm);
5159 value_in_comment = imm;
5160 } break;
5161
5162 case 'E':
5163 /* LSB and WIDTH fields of BFI or BFC. The machine-
5164 language instruction encodes LSB and MSB. */
5165 {
5166 long msb = (given & 0x001f0000) >> 16;
5167 long lsb = (given & 0x00000f80) >> 7;
5168 long w = msb - lsb + 1;
5169
5170 if (w > 0) {
5171 func (stream, "%lu, %lu", lsb, w);
5172 } else {
5173 func (stream, "(invalid: %lu:%lu)", lsb, msb);
5174 }
5175 }
5176 break;
5177
5178 case 'R':
5179 /* Get the PSR/banked register name. */
5180 {
5181 const char *name;
5182 unsigned sysm = (given & 0x004f0000) >> 16;
5183
5184 sysm |= (given & 0x300) >> 4;
5185 name = banked_regname (sysm);
5186
5187 if (name != NULL) {
5188 func (stream, "%s", name);
5189 } else {
5190 func (stream, "(UNDEF: %lu)", (unsigned long)sysm);
5191 }
5192 }
5193 break;
5194
5195 case 'V':
5196 /* 16-bit unsigned immediate from a MOVT or MOVW
5197 instruction, encoded in bits 0:11 and 15:19. */
5198 {
5199 long hi = (given & 0x000f0000) >> 4;
5200 long lo = (given & 0x00000fff);
5201 long imm16 = hi | lo;
5202
5203 func (stream, "%lu", imm16);
5204 value_in_comment = imm16;
5205 }
5206 break;
5207 }
5208 }
5209 } else {
5210 func (stream, "%c", *c);
5211 }
5212 }
5213
5214 #if 0
5215 if (value_in_comment > 32 || value_in_comment < -16)
5216 func (stream, " ; 0x%lx", (value_in_comment & 0xffffffffUL));
5217 #endif
5218
5219 if (is_unpredictable) {
5220 func (stream, UNPREDICTABLE_INSTRUCTION);
5221 }
5222
5223 return;
5224 }
5225 }
5226 }
5227
5228 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
5229
5230 static void
print_insn_thumb16(bfd_vma pc,struct disassemble_info * info,long given)5231 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
5232 {
5233 const struct opcode16 *insn;
5234 void *stream = info->stream;
5235 fprintf_ftype func = info->fprintf_func;
5236
5237 for (insn = thumb_opcodes; insn->assembler; insn++) {
5238 if ((given & insn->mask) == insn->value) {
5239 // signed long value_in_comment = 0;
5240 const char *c = insn->assembler;
5241
5242 for (; *c; c++) {
5243 int domaskpc = 0;
5244 int domasklr = 0;
5245
5246 if (*c != '%') {
5247 func (stream, "%c", *c);
5248 continue;
5249 }
5250
5251 switch (*++c) {
5252 case '%':
5253 func (stream, "%%");
5254 break;
5255
5256 case 'c':
5257 if (ifthen_state) {
5258 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5259 }
5260 break;
5261
5262 case 'C':
5263 if (ifthen_state) {
5264 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5265 } else {
5266 func (stream, "s");
5267 }
5268 break;
5269
5270 case 'I': {
5271 unsigned int tmp;
5272
5273 ifthen_next_state = given & 0xff;
5274 for (tmp = given << 1; tmp & 0xf; tmp <<= 1) {
5275 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
5276 }
5277 func (stream, " %s", arm_conditional[(given >> 4) & 0xf]);
5278 } break;
5279
5280 case 'x':
5281 if (ifthen_next_state) {
5282 func (stream, " ; unpredictable branch in IT block\n");
5283 }
5284 break;
5285
5286 case 'X':
5287 if (ifthen_state) {
5288 func (stream, " ; unpredictable <IT:%s>",
5289 arm_conditional[IFTHEN_COND]);
5290 }
5291 break;
5292
5293 case 'S': {
5294 long reg;
5295
5296 reg = (given >> 3) & 0x7;
5297 if (given & (1 << 6)) {
5298 reg += 8;
5299 }
5300
5301 func (stream, "%s", arm_regnames[reg]);
5302 } break;
5303
5304 case 'D': {
5305 long reg;
5306
5307 reg = given & 0x7;
5308 if (given & (1 << 7)) {
5309 reg += 8;
5310 }
5311
5312 func (stream, "%s", arm_regnames[reg]);
5313 } break;
5314
5315 case 'N':
5316 if (given & (1 << 8)) {
5317 domasklr = 1;
5318 }
5319 /* Fall through. */
5320 case 'O':
5321 if (*c == 'O' && (given & (1 << 8))) {
5322 domaskpc = 1;
5323 }
5324 /* Fall through. */
5325 case 'M': {
5326 int started = 0;
5327 int reg;
5328
5329 func (stream, "{");
5330
5331 /* It would be nice if we could spot
5332 ranges, and generate the rS-rE format: */
5333 for (reg = 0; (reg < 8); reg++) {
5334 if ((given & (1 << reg)) != 0) {
5335 if (started) {
5336 func (stream, ", ");
5337 }
5338 started = 1;
5339 func (stream, "%s", arm_regnames[reg]);
5340 }
5341 }
5342
5343 if (domasklr) {
5344 if (started) {
5345 func (stream, ", ");
5346 }
5347 started = 1;
5348 func (stream, "%s", arm_regnames[14] /* "lr" */);
5349 }
5350
5351 if (domaskpc) {
5352 if (started) {
5353 func (stream, ", ");
5354 }
5355 func (stream, "%s", arm_regnames[15] /* "pc" */);
5356 }
5357
5358 func (stream, "}");
5359 } break;
5360
5361 case 'W':
5362 /* Print writeback indicator for a LDMIA. We are doing a
5363 writeback if the base register is not in the register
5364 mask. */
5365 if ((given & (1 << ((given & 0x0700) >> 8))) == 0) {
5366 func (stream, "!");
5367 }
5368 break;
5369
5370 case 'b':
5371 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
5372 {
5373 bfd_vma address = (pc + 4 + ((given & 0x00f8) >> 2) + ((given & 0x0200) >> 3));
5374 info->print_address_func (address, info);
5375 }
5376 break;
5377
5378 case 's':
5379 /* Right shift immediate -- bits 6..10; 1-31 print
5380 as themselves, 0 prints as 32. */
5381 {
5382 long imm = (given & 0x07c0) >> 6;
5383 if (imm == 0) {
5384 imm = 32;
5385 }
5386 func (stream, "%ld", imm);
5387 }
5388 break;
5389
5390 case '0':
5391 case '1':
5392 case '2':
5393 case '3':
5394 case '4':
5395 case '5':
5396 case '6':
5397 case '7':
5398 case '8':
5399 case '9': {
5400 int bitstart = *c++ - '0';
5401 int bitend = 0;
5402
5403 while (*c >= '0' && *c <= '9') {
5404 bitstart = (bitstart * 10) + *c++ - '0';
5405 }
5406
5407 switch (*c) {
5408 case '-': {
5409 bfd_vma reg;
5410
5411 c++;
5412 while (*c >= '0' && *c <= '9') {
5413 bitend = (bitend * 10) + *c++ - '0';
5414 }
5415 if (!bitend) {
5416 return;
5417 }
5418 reg = given >> bitstart;
5419 reg &= (2 << (bitend - bitstart)) - 1;
5420
5421 switch (*c) {
5422 case 'r':
5423 func (stream, "%s", arm_regnames[reg]);
5424 break;
5425
5426 case 'd':
5427 func (stream, "%ld", (long)reg);
5428 // value_in_comment = reg;
5429 break;
5430
5431 case 'H':
5432 func (stream, "%ld", (long)(reg << 1));
5433 // value_in_comment = reg << 1;
5434 break;
5435
5436 case 'W':
5437 func (stream, "%ld", (long)(reg << 2));
5438 // value_in_comment = reg << 2;
5439 break;
5440
5441 case 'a':
5442 /* PC-relative address -- the bottom two
5443 bits of the address are dropped
5444 before the calculation. */
5445 info->print_address_func (((pc + 4) & ~3) + (reg << 2), info);
5446 //value_in_comment = 0;
5447 break;
5448
5449 case 'x':
5450 func (stream, "0x%04lx", (long)reg);
5451 break;
5452
5453 case 'B':
5454 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
5455 info->print_address_func (reg * 2 + pc + 4, info);
5456 //value_in_comment = 0;
5457 break;
5458
5459 case 'c':
5460 func (stream, "%s", arm_conditional[reg]);
5461 break;
5462 }
5463 } break;
5464
5465 case '\'':
5466 c++;
5467 if ((given & (1 << bitstart)) != 0) {
5468 func (stream, "%c", *c);
5469 }
5470 break;
5471
5472 case '?':
5473 ++c;
5474 if ((given & (1 << bitstart)) != 0) {
5475 func (stream, "%c", *c++);
5476 } else {
5477 func (stream, "%c", *++c);
5478 }
5479 break;
5480 }
5481 } break;
5482 }
5483 }
5484 #if 0
5485 if (value_in_comment > 32 || value_in_comment < -16)
5486 func (stream, " ; 0x%lx", value_in_comment);
5487 #endif
5488 return;
5489 }
5490 }
5491 }
5492
5493 /* Return the name of an V7M special register. */
5494
5495 static const char *
psr_name(int regno)5496 psr_name (int regno)
5497 {
5498 switch (regno)
5499 {
5500 case 0x0: return "APSR";
5501 case 0x1: return "IAPSR";
5502 case 0x2: return "EAPSR";
5503 case 0x3: return "PSR";
5504 case 0x5: return "IPSR";
5505 case 0x6: return "EPSR";
5506 case 0x7: return "IEPSR";
5507 case 0x8: return "MSP";
5508 case 0x9: return "PSP";
5509 case 0xa: return "MSPLIM";
5510 case 0xb: return "PSPLIM";
5511 case 0x10: return "PRIMASK";
5512 case 0x11: return "BASEPRI";
5513 case 0x12: return "BASEPRI_MAX";
5514 case 0x13: return "FAULTMASK";
5515 case 0x14: return "CONTROL";
5516 case 0x88: return "MSP_NS";
5517 case 0x89: return "PSP_NS";
5518 case 0x8a: return "MSPLIM_NS";
5519 case 0x8b: return "PSPLIM_NS";
5520 case 0x90: return "PRIMASK_NS";
5521 case 0x91: return "BASEPRI_NS";
5522 case 0x93: return "FAULTMASK_NS";
5523 case 0x94: return "CONTROL_NS";
5524 case 0x98: return "SP_NS";
5525 default: return "<unknown>";
5526 }
5527 }
5528
5529 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
5530
5531 static void
print_insn_thumb32(bfd_vma pc,struct disassemble_info * info,long given)5532 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
5533 {
5534 const struct opcode32 *insn;
5535 void *stream = info->stream;
5536 fprintf_ftype func = info->fprintf_func;
5537
5538 if (print_insn_coprocessor (pc, info, given, TRUE)) {
5539 return;
5540 }
5541
5542 if (print_insn_neon (info, given, TRUE)) {
5543 return;
5544 }
5545
5546 for (insn = thumb32_opcodes; insn->assembler; insn++) {
5547 if ((given & insn->mask) == insn->value) {
5548 bfd_boolean is_unpredictable = FALSE;
5549 // signed long value_in_comment = 0;
5550 const char *c = insn->assembler;
5551
5552 for (; *c; c++) {
5553 if (*c != '%') {
5554 func (stream, "%c", *c);
5555 continue;
5556 }
5557
5558 switch (*++c) {
5559 case '%':
5560 func (stream, "%%");
5561 break;
5562
5563 case 'c':
5564 if (ifthen_state) {
5565 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5566 }
5567 break;
5568
5569 case 'x':
5570 if (ifthen_next_state) {
5571 func (stream, " ; unpredictable branch in IT block\n");
5572 }
5573 break;
5574
5575 case 'X':
5576 if (ifthen_state) {
5577 func (stream, " ; unpredictable <IT:%s>",
5578 arm_conditional[IFTHEN_COND]);
5579 }
5580 break;
5581
5582 case 'I': {
5583 unsigned int imm12 = 0;
5584
5585 imm12 |= (given & 0x000000ffu);
5586 imm12 |= (given & 0x00007000u) >> 4;
5587 imm12 |= (given & 0x04000000u) >> 15;
5588 func (stream, "%u", imm12);
5589 //value_in_comment = imm12;
5590 } break;
5591
5592 case 'M': {
5593 unsigned int bits = 0, imm, imm8, mod;
5594
5595 bits |= (given & 0x000000ffu);
5596 bits |= (given & 0x00007000u) >> 4;
5597 bits |= (given & 0x04000000u) >> 15;
5598 imm8 = (bits & 0x0ff);
5599 mod = (bits & 0xf00) >> 8;
5600 switch (mod) {
5601 case 0: imm = imm8; break;
5602 case 1: imm = ((imm8 << 16) | imm8); break;
5603 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
5604 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
5605 default:
5606 mod = (bits & 0xf80) >> 7;
5607 imm8 = (bits & 0x07f) | 0x80;
5608 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
5609 }
5610 func (stream, "%u", imm);
5611 //value_in_comment = imm;
5612 } break;
5613
5614 case 'J': {
5615 unsigned int imm = 0;
5616
5617 imm |= (given & 0x000000ffu);
5618 imm |= (given & 0x00007000u) >> 4;
5619 imm |= (given & 0x04000000u) >> 15;
5620 imm |= (given & 0x000f0000u) >> 4;
5621 func (stream, "%u", imm);
5622 //value_in_comment = imm;
5623 } break;
5624
5625 case 'K': {
5626 unsigned int imm = 0;
5627
5628 imm |= (given & 0x000f0000u) >> 16;
5629 imm |= (given & 0x00000ff0u) >> 0;
5630 imm |= (given & 0x0000000fu) << 12;
5631 func (stream, "%u", imm);
5632 //value_in_comment = imm;
5633 } break;
5634
5635 case 'H': {
5636 unsigned int imm = 0;
5637
5638 imm |= (given & 0x000f0000u) >> 4;
5639 imm |= (given & 0x00000fffu) >> 0;
5640 func (stream, "%u", imm);
5641 //value_in_comment = imm;
5642 } break;
5643
5644 case 'V': {
5645 unsigned int imm = 0;
5646
5647 imm |= (given & 0x00000fffu);
5648 imm |= (given & 0x000f0000u) >> 4;
5649 func (stream, "%u", imm);
5650 //value_in_comment = imm;
5651 } break;
5652
5653 case 'S': {
5654 unsigned int reg = (given & 0x0000000fu);
5655 unsigned int stp = (given & 0x00000030u) >> 4;
5656 unsigned int imm = 0;
5657 imm |= (given & 0x000000c0u) >> 6;
5658 imm |= (given & 0x00007000u) >> 10;
5659
5660 func (stream, "%s", arm_regnames[reg]);
5661 switch (stp) {
5662 case 0:
5663 if (imm > 0) {
5664 func (stream, ", lsl %u", imm);
5665 }
5666 break;
5667
5668 case 1:
5669 if (imm == 0) {
5670 imm = 32;
5671 }
5672 func (stream, ", lsr %u", imm);
5673 break;
5674
5675 case 2:
5676 if (imm == 0) {
5677 imm = 32;
5678 }
5679 func (stream, ", asr %u", imm);
5680 break;
5681
5682 case 3:
5683 if (imm == 0) {
5684 func (stream, ", rrx");
5685 } else {
5686 func (stream, ", ror %u", imm);
5687 }
5688 }
5689 } break;
5690
5691 case 'a': {
5692 unsigned int Rn = (given & 0x000f0000) >> 16;
5693 unsigned int U = !NEGATIVE_BIT_SET;
5694 unsigned int op = (given & 0x00000f00) >> 8;
5695 unsigned int i12 = (given & 0x00000fff);
5696 unsigned int i8 = (given & 0x000000ff);
5697 bfd_boolean writeback = FALSE, postind = FALSE;
5698 bfd_vma offset = 0;
5699
5700 func (stream, "[%s", arm_regnames[Rn]);
5701 if (U) /* 12-bit positive immediate offset. */
5702 {
5703 offset = i12;
5704 if (Rn != 15) {
5705 // value_in_comment = offset;
5706 }
5707 } else if (Rn == 15) { /* 12-bit negative immediate offset. */
5708 offset = -(int)i12;
5709 } else if (op == 0x0) /* Shifted register offset. */
5710 {
5711 unsigned int Rm = (i8 & 0x0f);
5712 unsigned int sh = (i8 & 0x30) >> 4;
5713
5714 func (stream, ", %s", arm_regnames[Rm]);
5715 if (sh) {
5716 func (stream, ", lsl %u", sh);
5717 }
5718 func (stream, "]");
5719 break;
5720 } else {
5721 switch (op) {
5722 case 0xE: /* 8-bit positive immediate offset. */
5723 offset = i8;
5724 break;
5725
5726 case 0xC: /* 8-bit negative immediate offset. */
5727 offset = -i8;
5728 break;
5729
5730 case 0xF: /* 8-bit + preindex with wb. */
5731 offset = i8;
5732 writeback = TRUE;
5733 break;
5734
5735 case 0xD: /* 8-bit - preindex with wb. */
5736 offset = -i8;
5737 writeback = TRUE;
5738 break;
5739
5740 case 0xB: /* 8-bit + postindex. */
5741 offset = i8;
5742 postind = TRUE;
5743 break;
5744
5745 case 0x9: /* 8-bit - postindex. */
5746 offset = -i8;
5747 postind = TRUE;
5748 break;
5749
5750 default:
5751 func (stream, ", <undefined>]");
5752 goto skip;
5753 }
5754 }
5755
5756 if (postind) {
5757 func (stream, "], %d", (int)offset);
5758 } else {
5759 if (offset) {
5760 func (stream, ", %d", (int)offset);
5761 }
5762 func (stream, writeback ? "]!" : "]");
5763 }
5764
5765 if (Rn == 15) {
5766 func (stream, " ; ");
5767 info->print_address_func (((pc + 4) & ~3) + offset, info);
5768 }
5769 }
5770 skip:
5771 break;
5772
5773 case 'A': {
5774 unsigned int U = !NEGATIVE_BIT_SET;
5775 unsigned int W = WRITEBACK_BIT_SET;
5776 unsigned int Rn = (given & 0x000f0000) >> 16;
5777 unsigned int off = (given & 0x000000ff);
5778
5779 func (stream, "[%s", arm_regnames[Rn]);
5780
5781 if (PRE_BIT_SET) {
5782 if (off || !U) {
5783 func (stream, ", %c%u", U ? '+' : '-', off * 4);
5784 //value_in_comment = (off && U) ? 1 : -1;
5785 }
5786 func (stream, "]");
5787 if (W) {
5788 func (stream, "!");
5789 }
5790 } else {
5791 func (stream, "], ");
5792 if (W) {
5793 func (stream, "%c%u", U ? '+' : '-', off * 4);
5794 //value_in_comment = (off && U) ? 1 : -1;
5795 } else {
5796 func (stream, "{%u}", off);
5797 // value_in_comment = off;
5798 }
5799 }
5800 } break;
5801
5802 case 'w': {
5803 unsigned int Sbit = (given & 0x01000000) >> 24;
5804 unsigned int type = (given & 0x00600000) >> 21;
5805
5806 switch (type) {
5807 case 0: func (stream, Sbit ? "sb" : "b"); break;
5808 case 1: func (stream, Sbit ? "sh" : "h"); break;
5809 case 2:
5810 if (Sbit) {
5811 func (stream, "??");
5812 }
5813 break;
5814 case 3:
5815 func (stream, "??");
5816 break;
5817 }
5818 } break;
5819
5820 case 'm': {
5821 int started = 0;
5822 int reg;
5823
5824 func (stream, "{");
5825 for (reg = 0; reg < 16; reg++) {
5826 if ((given & (1 << reg)) != 0) {
5827 if (started) {
5828 func (stream, ", ");
5829 }
5830 started = 1;
5831 func (stream, "%s", arm_regnames[reg]);
5832 }
5833 }
5834 func (stream, "}");
5835 } break;
5836
5837 case 'E': {
5838 unsigned int msb = (given & 0x0000001f);
5839 unsigned int lsb = 0;
5840
5841 lsb |= (given & 0x000000c0u) >> 6;
5842 lsb |= (given & 0x00007000u) >> 10;
5843 func (stream, "%u, %u", lsb, msb - lsb + 1);
5844 } break;
5845
5846 case 'F': {
5847 unsigned int width = (given & 0x0000001f) + 1;
5848 unsigned int lsb = 0;
5849
5850 lsb |= (given & 0x000000c0u) >> 6;
5851 lsb |= (given & 0x00007000u) >> 10;
5852 func (stream, "%u, %u", lsb, width);
5853 } break;
5854
5855 case 'b': {
5856 unsigned int S = (given & 0x04000000u) >> 26;
5857 unsigned int J1 = (given & 0x00002000u) >> 13;
5858 unsigned int J2 = (given & 0x00000800u) >> 11;
5859 bfd_vma offset = 0;
5860
5861 offset |= !S << 20;
5862 offset |= J2 << 19;
5863 offset |= J1 << 18;
5864 offset |= (given & 0x003f0000) >> 4;
5865 offset |= (given & 0x000007ff) << 1;
5866 offset -= (1 << 20);
5867
5868 info->print_address_func (pc + 4 + offset, info);
5869 } break;
5870
5871 case 'B': {
5872 unsigned int S = (given & 0x04000000u) >> 26;
5873 unsigned int I1 = (given & 0x00002000u) >> 13;
5874 unsigned int I2 = (given & 0x00000800u) >> 11;
5875 bfd_vma offset = 0;
5876
5877 offset |= !S << 24;
5878 offset |= !(I1 ^ S) << 23;
5879 offset |= !(I2 ^ S) << 22;
5880 offset |= (given & 0x03ff0000u) >> 4;
5881 offset |= (given & 0x000007ffu) << 1;
5882 offset -= (1 << 24);
5883 offset += pc + 4;
5884
5885 /* BLX target addresses are always word aligned. */
5886 if ((given & 0x00001000u) == 0) {
5887 offset &= ~2u;
5888 }
5889
5890 info->print_address_func (offset, info);
5891 } break;
5892
5893 case 's': {
5894 unsigned int shift = 0;
5895
5896 shift |= (given & 0x000000c0u) >> 6;
5897 shift |= (given & 0x00007000u) >> 10;
5898 if (WRITEBACK_BIT_SET) {
5899 func (stream, ", asr %u", shift);
5900 } else if (shift) {
5901 func (stream, ", lsl %u", shift);
5902 }
5903 /* else print nothing - lsl #0 */
5904 } break;
5905
5906 case 'R': {
5907 unsigned int rot = (given & 0x00000030) >> 4;
5908
5909 if (rot) {
5910 func (stream, ", ror %u", rot * 8);
5911 }
5912 } break;
5913
5914 case 'U':
5915 if ((given & 0xf0) == 0x60) {
5916 switch (given & 0xf) {
5917 case 0xf: func (stream, "sy"); break;
5918 default:
5919 func (stream, "%d", (int)given & 0xf);
5920 break;
5921 }
5922 } else {
5923 const char *opt = data_barrier_option (given & 0xf);
5924 if (opt != NULL) {
5925 func (stream, "%s", opt);
5926 } else {
5927 func (stream, "%d", (int)given & 0xf);
5928 }
5929 }
5930 break;
5931
5932 case 'C':
5933 if ((given & 0xff) == 0) {
5934 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
5935 if (given & 0x800) {
5936 func (stream, "f");
5937 }
5938 if (given & 0x400) {
5939 func (stream, "s");
5940 }
5941 if (given & 0x200) {
5942 func (stream, "x");
5943 }
5944 if (given & 0x100) {
5945 func (stream, "c");
5946 }
5947 } else if ((given & 0x20) == 0x20) {
5948 char const *name;
5949 unsigned sysm = (given & 0xf00) >> 8;
5950
5951 sysm |= (given & 0x30);
5952 sysm |= (given & 0x00100000) >> 14;
5953 name = banked_regname (sysm);
5954
5955 if (name != NULL) {
5956 func (stream, "%s", name);
5957 } else {
5958 func (stream, "(UNDEF: %lu)", (unsigned long)sysm);
5959 }
5960 } else {
5961 func (stream, "%s", psr_name (given & 0xff));
5962 }
5963 break;
5964
5965 case 'D':
5966 if (((given & 0xff) == 0) || ((given & 0x20) == 0x20)) {
5967 char const *name;
5968 unsigned sm = (given & 0xf0000) >> 16;
5969
5970 sm |= (given & 0x30);
5971 sm |= (given & 0x00100000) >> 14;
5972 name = banked_regname (sm);
5973
5974 if (name != NULL) {
5975 func (stream, "%s", name);
5976 } else {
5977 func (stream, "(UNDEF: %lu)", (unsigned long)sm);
5978 }
5979 } else {
5980 func (stream, "%s", psr_name (given & 0xff));
5981 }
5982 break;
5983
5984 case '0':
5985 case '1':
5986 case '2':
5987 case '3':
5988 case '4':
5989 case '5':
5990 case '6':
5991 case '7':
5992 case '8':
5993 case '9': {
5994 int width;
5995 unsigned long val;
5996
5997 c = arm_decode_bitfield (c, given, &val, &width);
5998
5999 switch (*c) {
6000 case 'd':
6001 func (stream, "%lu", val);
6002 //value_in_comment = val;
6003 break;
6004
6005 case 'D':
6006 func (stream, "%lu", val + 1);
6007 // value_in_comment = val + 1;
6008 break;
6009
6010 case 'W':
6011 func (stream, "%lu", val * 4);
6012 // value_in_comment = val * 4;
6013 break;
6014
6015 case 'S':
6016 if (val == 13) {
6017 is_unpredictable = TRUE;
6018 }
6019 /* Fall through. */
6020 case 'R':
6021 if (val == 15) {
6022 is_unpredictable = TRUE;
6023 }
6024 /* Fall through. */
6025 case 'r':
6026 func (stream, "%s", arm_regnames[val]);
6027 break;
6028
6029 case 'c':
6030 func (stream, "%s", arm_conditional[val]);
6031 break;
6032
6033 case '\'':
6034 c++;
6035 if (val == ((1ul << width) - 1)) {
6036 func (stream, "%c", *c);
6037 }
6038 break;
6039
6040 case '`':
6041 c++;
6042 if (val == 0) {
6043 func (stream, "%c", *c);
6044 }
6045 break;
6046
6047 case '?':
6048 func (stream, "%c", c[(1 << width) - (int)val]);
6049 c += 1 << width;
6050 break;
6051
6052 case 'x':
6053 func (stream, "0x%lx", val & 0xffffffffUL);
6054 break;
6055 }
6056 } break;
6057
6058 case 'L':
6059 /* PR binutils/12534
6060 If we have a PC relative offset in an LDRD or STRD
6061 instructions then display the decoded address. */
6062 if (((given >> 16) & 0xf) == 0xf) {
6063 bfd_vma offset = (given & 0xff) * 4;
6064
6065 if ((given & (1 << 23)) == 0) {
6066 offset = -offset;
6067 }
6068 func (stream, " ; ");
6069 info->print_address_func ((pc & ~3) + 4 + offset, info);
6070 }
6071 break;
6072 }
6073 }
6074
6075 #if 0
6076 if (value_in_comment > 32 || value_in_comment < -16)
6077 func (stream, " ; 0x%lx", value_in_comment);
6078 #endif
6079
6080 if (is_unpredictable) {
6081 func (stream, UNPREDICTABLE_INSTRUCTION);
6082 }
6083
6084 return;
6085 }
6086 }
6087
6088 /* No match. */
6089 }
6090
6091 /* Print data bytes on INFO->STREAM. */
6092
6093 static void
print_insn_data(bfd_vma pc ATTRIBUTE_UNUSED,struct disassemble_info * info,long given)6094 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
6095 struct disassemble_info *info,
6096 long given)
6097 {
6098 switch (info->bytes_per_chunk)
6099 {
6100 case 1:
6101 info->fprintf_func (info->stream, ".byte 0x%02lx", given);
6102 break;
6103 case 2:
6104 info->fprintf_func (info->stream, ".short 0x%04lx", given);
6105 break;
6106 case 4:
6107 info->fprintf_func (info->stream, ".word 0x%08lx", given);
6108 break;
6109 }
6110 }
6111
6112 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
6113 being displayed in symbol relative addresses.
6114
6115 Also disallow private symbol, with __tagsym$$ prefix,
6116 from ARM RVCT toolchain being displayed. */
6117
6118 bfd_boolean
arm_symbol_is_valid(asymbol * sym,struct disassemble_info * info ATTRIBUTE_UNUSED)6119 arm_symbol_is_valid (asymbol * sym,
6120 struct disassemble_info * info ATTRIBUTE_UNUSED)
6121 {
6122 const char * name;
6123
6124 if (sym == NULL) {
6125 return FALSE;
6126 }
6127
6128 name = bfd_asymbol_name (sym);
6129
6130 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
6131 }
6132
6133 /* Parse the string of disassembler options. */
6134
6135 /* Like STRCMP, but treat ',' the same as '\0' so that we match
6136 strings like "foobar" against "foobar,xxyyzz,...". */
6137
6138 int
disassembler_options_cmp(const char * s1,const char * s2)6139 disassembler_options_cmp (const char *s1, const char *s2)
6140 {
6141 unsigned char c1, c2;
6142
6143 do
6144 {
6145 c1 = (unsigned char) *s1++;
6146 if (c1 == ',') {
6147 c1 = '\0';
6148 }
6149 c2 = (unsigned char) *s2++;
6150 if (c2 == ',') {
6151 c2 = '\0';
6152 }
6153 if (c1 == '\0') {
6154 return c1 - c2;
6155 }
6156 }
6157 while (c1 == c2);
6158
6159 return c1 - c2;
6160 }
6161
6162 static void
parse_arm_disassembler_options(char * options)6163 parse_arm_disassembler_options (char *options)
6164 {
6165 char *opt;
6166
6167 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
6168 {
6169 if (CONST_STRNEQ (opt, "reg-names-"))
6170 {
6171 unsigned int i;
6172 for (i = 0; i < NUM_ARM_OPTIONS; i++) {
6173 if (disassembler_options_cmp (opt, regnames[i].name) == 0) {
6174 regname_selected = i;
6175 break;
6176 }
6177 }
6178
6179 if (i >= NUM_ARM_OPTIONS) {
6180 fprintf (stderr, _ ("Unrecognised register name set: %s\n"), opt);
6181 }
6182 } else if (CONST_STRNEQ (opt, "force-thumb")) {
6183 force_thumb = 1;
6184 } else if (CONST_STRNEQ (opt, "no-force-thumb")) {
6185 force_thumb = 0;
6186 } else {
6187 fprintf (stderr, _ ("Unrecognised disassembler option: %s\n"), opt);
6188 }
6189 }
6190
6191 return;
6192 }
6193
6194 static bfd_boolean
6195 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6196 enum map_type *map_symbol);
6197
6198 /* Search back through the insn stream to determine if this instruction is
6199 conditionally executed. */
6200
6201 static void
find_ifthen_state(bfd_vma pc,struct disassemble_info * info,bfd_boolean little)6202 find_ifthen_state (bfd_vma pc,
6203 struct disassemble_info *info,
6204 bfd_boolean little)
6205 {
6206 unsigned char b[2];
6207 unsigned int insn;
6208 int status;
6209 /* COUNT is twice the number of instructions seen. It will be odd if we
6210 just crossed an instruction boundary. */
6211 int count;
6212 int it_count;
6213 unsigned int seen_it;
6214 bfd_vma addr;
6215
6216 ifthen_address = pc;
6217 ifthen_state = 0;
6218
6219 addr = pc;
6220 count = 1;
6221 it_count = 0;
6222 seen_it = 0;
6223 /* Scan backwards looking for IT instructions, keeping track of where
6224 instruction boundaries are. We don't know if something is actually an
6225 IT instruction until we find a definite instruction boundary. */
6226 for (;;)
6227 {
6228 if (addr == 0 || info->symbol_at_address_func (addr, info))
6229 {
6230 /* A symbol must be on an instruction boundary, and will not
6231 be within an IT block. */
6232 if (seen_it && (count & 1)) {
6233 break;
6234 }
6235
6236 return;
6237 }
6238 addr -= 2;
6239 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
6240 if (status) {
6241 return;
6242 }
6243
6244 if (little) {
6245 insn = (b[0]) | (b[1] << 8);
6246 } else {
6247 insn = (b[1]) | (b[0] << 8);
6248 }
6249 if (seen_it)
6250 {
6251 if ((insn & 0xf800) < 0xe800)
6252 {
6253 /* Addr + 2 is an instruction boundary. See if this matches
6254 the expected boundary based on the position of the last
6255 IT candidate. */
6256 if (count & 1) {
6257 break;
6258 }
6259 seen_it = 0;
6260 }
6261 }
6262 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
6263 {
6264 enum map_type type = MAP_ARM;
6265 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
6266
6267 if (!found || (found && type == MAP_THUMB))
6268 {
6269 /* This could be an IT instruction. */
6270 seen_it = insn;
6271 it_count = count >> 1;
6272 }
6273 }
6274 if ((insn & 0xf800) >= 0xe800) {
6275 count++;
6276 } else {
6277 count = (count + 2) | 1;
6278 }
6279 /* IT blocks contain at most 4 instructions. */
6280 if (count >= 8 && !seen_it) {
6281 return;
6282 }
6283 }
6284 /* We found an IT instruction. */
6285 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
6286 if ((ifthen_state & 0xf) == 0) {
6287 ifthen_state = 0;
6288 }
6289 }
6290
6291 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
6292 mapping symbol. */
6293
6294 static int
is_mapping_symbol(struct disassemble_info * info,int n,enum map_type * map_type)6295 is_mapping_symbol (struct disassemble_info *info, int n,
6296 enum map_type *map_type)
6297 {
6298 const char *name;
6299
6300 name = bfd_asymbol_name (info->symtab[n]);
6301 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
6302 && (name[2] == 0 || name[2] == '.'))
6303 {
6304 *map_type = ((name[1] == 'a') ? MAP_ARM
6305 : (name[1] == 't') ? MAP_THUMB
6306 : MAP_DATA);
6307 return TRUE;
6308 }
6309
6310 return FALSE;
6311 }
6312
6313 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
6314 Returns nonzero if *MAP_TYPE was set. */
6315
6316 static int
get_map_sym_type(struct disassemble_info * info,int n,enum map_type * map_type)6317 get_map_sym_type (struct disassemble_info *info,
6318 int n,
6319 enum map_type *map_type)
6320 {
6321 /* If the symbol is in a different section, ignore it. */
6322 if (info->section != NULL && info->section != info->symtab[n]->section) {
6323 return FALSE;
6324 }
6325
6326 return is_mapping_symbol (info, n, map_type);
6327 }
6328
6329 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
6330 Returns nonzero if *MAP_TYPE was set. */
6331
6332 static int
get_sym_code_type(struct disassemble_info * info,int n,enum map_type * map_type)6333 get_sym_code_type (struct disassemble_info *info,
6334 int n,
6335 enum map_type *map_type)
6336 {
6337 return FALSE;
6338 #if 0
6339 elf_symbol_type *es;
6340 unsigned int type;
6341
6342 /* If the symbol is in a different section, ignore it. */
6343 if (info->section != NULL && info->section != info->symtab[n]->section)
6344 return FALSE;
6345
6346 es = *(elf_symbol_type **)(info->symtab + n);
6347 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6348
6349 /* If the symbol has function type then use that. */
6350 if (type == STT_FUNC || type == STT_GNU_IFUNC)
6351 {
6352 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
6353 == ST_BRANCH_TO_THUMB)
6354 *map_type = MAP_THUMB;
6355 else
6356 *map_type = MAP_ARM;
6357 return TRUE;
6358 }
6359
6360 return FALSE;
6361 #endif
6362 }
6363
6364 /* Search the mapping symbol state for instruction at pc. This is only
6365 applicable for elf target.
6366
6367 There is an assumption Here, info->private_data contains the correct AND
6368 up-to-date information about current scan process. The information will be
6369 used to speed this search process.
6370
6371 Return TRUE if the mapping state can be determined, and map_symbol
6372 will be updated accordingly. Otherwise, return FALSE. */
6373
6374 static bfd_boolean
mapping_symbol_for_insn(bfd_vma pc,struct disassemble_info * info,enum map_type * map_symbol)6375 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6376 enum map_type *map_symbol)
6377 {
6378 bfd_vma addr;
6379 int n, start = 0;
6380 bfd_boolean found = FALSE;
6381 enum map_type type = MAP_ARM;
6382 struct arm_private_data *private_data;
6383
6384 if (info->private_data == NULL || info->symtab_size == 0 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour) {
6385 return FALSE;
6386 }
6387
6388 private_data = info->private_data;
6389 if (pc == 0) {
6390 start = 0;
6391 } else {
6392 start = private_data->last_mapping_sym;
6393 }
6394
6395 start = (start == -1)? 0 : start;
6396 addr = bfd_asymbol_value (info->symtab[start]);
6397
6398 if (pc >= addr)
6399 {
6400 if (get_map_sym_type (info, start, &type)) {
6401 found = TRUE;
6402 }
6403 }
6404 else
6405 {
6406 for (n = start - 1; n >= 0; n--)
6407 {
6408 if (get_map_sym_type (info, n, &type))
6409 {
6410 found = TRUE;
6411 break;
6412 }
6413 }
6414 }
6415
6416 /* No mapping symbols were found. A leading $d may be
6417 omitted for sections which start with data; but for
6418 compatibility with legacy and stripped binaries, only
6419 assume the leading $d if there is at least one mapping
6420 symbol in the file. */
6421 if (!found && private_data->has_mapping_symbols == 1)
6422 {
6423 type = MAP_DATA;
6424 found = TRUE;
6425 }
6426
6427 *map_symbol = type;
6428 return found;
6429 }
6430
6431 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
6432 of the supplied arm_feature_set structure with bitmasks indicating
6433 the support base architectures and coprocessor extensions.
6434
6435 FIXME: This could more efficiently implemented as a constant array,
6436 although it would also be less robust. */
6437
6438 #define ARM_MERGE_FEATURE_SETS(TARG,F1,F2) \
6439 do { \
6440 (TARG).core[0] = (F1).core[0] | (F2).core[0];\
6441 (TARG).core[1] = (F1).core[1] | (F2).core[1];\
6442 (TARG).coproc = (F1).coproc | (F2).coproc; \
6443 } while (0)
6444
6445
6446 static void
select_arm_features(unsigned long mach,arm_feature_set * features)6447 select_arm_features (unsigned long mach,
6448 arm_feature_set * features)
6449 {
6450 #undef ARM_SET_FEATURES2
6451 //ARM_FEATURE (0, 0, FPU_ARCH_VFP_V4D16) ;
6452 #define ARM_SET_FEATURES2(FSET) \
6453 { \
6454 const arm_feature_set fset = FSET; \
6455 arm_feature_set tmp = FPU_ARCH_VFP_V4D16; \
6456 ARM_MERGE_FEATURE_SETS (*features, tmp, fset); \
6457 }
6458 #undef ARM_SET_FEATURES
6459 #define ARM_SET_FEATURES(FSET) \
6460 { \
6461 const arm_feature_set fset = FSET; \
6462 arm_feature_set tmp = ARM_FEATURE (0, 0, FPU_FPA) ; \
6463 ARM_MERGE_FEATURE_SETS (*features, tmp, fset); \
6464 }
6465
6466 #if 0
6467 // ARM_SET_FEATURES (ARM_FEATURE_ALL);
6468 ARM_SET_FEATURES2(ARM_ARCH_V7EM); //, FPU_ARCH_VFP_V4D16);
6469 return;
6470 #if 0
6471 FPU_ARCH_VFP_V4D16
6472 return;
6473 #endif
6474 #endif
6475
6476 switch (mach)
6477 {
6478 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
6479 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
6480 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
6481 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
6482 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
6483 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
6484 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
6485 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
6486 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
6487 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
6488 case bfd_mach_arm_ep9312:
6489 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
6490 ARM_CEXT_MAVERICK | FPU_MAVERICK));
6491 break;
6492 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
6493 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
6494 /* If the machine type is unknown allow all
6495 architecture types and all extensions. */
6496 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
6497 }
6498
6499 #undef ARM_SET_FEATURES
6500 }
6501
6502
6503 /* NOTE: There are no checks in these routines that
6504 the relevant number of data bytes exist. */
6505
6506 static int
print_insn(bfd_vma pc,struct disassemble_info * info,bfd_boolean little)6507 print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
6508 {
6509 unsigned char b[4];
6510 long given;
6511 int status;
6512 int is_thumb = FALSE;
6513 int is_data = FALSE;
6514 int little_code;
6515 unsigned int size = 4;
6516 void (*printer) (bfd_vma, struct disassemble_info *, long);
6517 bfd_boolean found = FALSE;
6518 struct arm_private_data *private_data;
6519
6520 if (info->disassembler_options)
6521 {
6522 parse_arm_disassembler_options (info->disassembler_options);
6523
6524 /* To avoid repeated parsing of these options, we remove them here. */
6525 info->disassembler_options = NULL;
6526 }
6527
6528 /* PR 10288: Control which instructions will be disassembled. */
6529 if (info->private_data == NULL)
6530 {
6531 static struct arm_private_data private;
6532
6533 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0) {
6534 /* If the user did not use the -m command line switch then default to
6535 disassembling all types of ARM instruction.
6536
6537 The info->mach value has to be ignored as this will be based on
6538 the default archictecture for the target and/or hints in the notes
6539 section, but it will never be greater than the current largest arm
6540 machine value (iWMMXt2), which is only equivalent to the V5TE
6541 architecture. ARM architectures have advanced beyond the machine
6542 value encoding, and these newer architectures would be ignored if
6543 the machine value was used.
6544
6545 Ie the -m switch is used to restrict which instructions will be
6546 disassembled. If it is necessary to use the -m switch to tell
6547 objdump that an ARM binary is being disassembled, eg because the
6548 input is a raw binary file, but it is also desired to disassemble
6549 all ARM instructions then use "-marm". This will select the
6550 "unknown" arm architecture which is compatible with any ARM
6551 instruction. */
6552 info->mach = bfd_mach_arm_unknown;
6553 }
6554
6555 /* Compute the architecture bitmask from the machine number.
6556 Note: This assumes that the machine number will not change
6557 during disassembly.... */
6558 select_arm_features (info->mach, & private.features);
6559
6560 private.has_mapping_symbols = -1;
6561 private.last_mapping_sym = -1;
6562 private.last_mapping_addr = 0;
6563
6564 info->private_data = & private;
6565 }
6566
6567 private_data = info->private_data;
6568
6569 /* Decide if our code is going to be little-endian, despite what the
6570 function argument might say. */
6571 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
6572
6573 /* For ELF, consult the symbol table to determine what kind of code
6574 or data we have. */
6575 if (info->symtab_size != 0
6576 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
6577 {
6578 bfd_vma addr;
6579 int n, start;
6580 int last_sym = -1;
6581 enum map_type type = MAP_ARM;
6582
6583 /* Start scanning at the start of the function, or wherever
6584 we finished last time. */
6585 /* PR 14006. When the address is 0 we are either at the start of the
6586 very first function, or else the first function in a new, unlinked
6587 executable section (eg because of -ffunction-sections). Either way
6588 start scanning from the beginning of the symbol table, not where we
6589 left off last time. */
6590 if (pc == 0) {
6591 start = 0;
6592 } else {
6593 start = info->symtab_pos + 1;
6594 if (start < private_data->last_mapping_sym) {
6595 start = private_data->last_mapping_sym;
6596 }
6597 }
6598 found = FALSE;
6599
6600 /* First, look for mapping symbols. */
6601 if (private_data->has_mapping_symbols != 0)
6602 {
6603 /* Scan up to the location being disassembled. */
6604 for (n = start; n < info->symtab_size; n++)
6605 {
6606 addr = bfd_asymbol_value (info->symtab[n]);
6607 if (addr > pc) {
6608 break;
6609 }
6610 if (get_map_sym_type (info, n, &type))
6611 {
6612 last_sym = n;
6613 found = TRUE;
6614 }
6615 }
6616
6617 if (!found)
6618 {
6619 /* No mapping symbol found at this address. Look backwards
6620 for a preceding one. */
6621 for (n = start - 1; n >= 0; n--)
6622 {
6623 if (get_map_sym_type (info, n, &type))
6624 {
6625 last_sym = n;
6626 found = TRUE;
6627 break;
6628 }
6629 }
6630 }
6631
6632 if (found) {
6633 private_data->has_mapping_symbols = 1;
6634 }
6635
6636 /* No mapping symbols were found. A leading $d may be
6637 omitted for sections which start with data; but for
6638 compatibility with legacy and stripped binaries, only
6639 assume the leading $d if there is at least one mapping
6640 symbol in the file. */
6641 if (!found && private_data->has_mapping_symbols == -1) {
6642 /* Look for mapping symbols, in any section. */
6643 for (n = 0; n < info->symtab_size; n++) {
6644 if (is_mapping_symbol (info, n, &type)) {
6645 private_data->has_mapping_symbols = 1;
6646 break;
6647 }
6648 }
6649 if (private_data->has_mapping_symbols == -1) {
6650 private_data->has_mapping_symbols = 0;
6651 }
6652 }
6653
6654 if (!found && private_data->has_mapping_symbols == 1)
6655 {
6656 type = MAP_DATA;
6657 found = TRUE;
6658 }
6659 }
6660
6661 /* Next search for function symbols to separate ARM from Thumb
6662 in binaries without mapping symbols. */
6663 if (!found)
6664 {
6665 /* Scan up to the location being disassembled. */
6666 for (n = start; n < info->symtab_size; n++)
6667 {
6668 addr = bfd_asymbol_value (info->symtab[n]);
6669 if (addr > pc) {
6670 break;
6671 }
6672 if (get_sym_code_type (info, n, &type))
6673 {
6674 last_sym = n;
6675 found = TRUE;
6676 }
6677 }
6678
6679 if (!found)
6680 {
6681 /* No mapping symbol found at this address. Look backwards
6682 for a preceding one. */
6683 for (n = start - 1; n >= 0; n--)
6684 {
6685 if (get_sym_code_type (info, n, &type))
6686 {
6687 last_sym = n;
6688 found = TRUE;
6689 break;
6690 }
6691 }
6692 }
6693 }
6694
6695 private_data->last_mapping_sym = last_sym;
6696 private_data->last_type = type;
6697 is_thumb = (private_data->last_type == MAP_THUMB);
6698 is_data = (private_data->last_type == MAP_DATA);
6699
6700 /* Look a little bit ahead to see if we should print out
6701 two or four bytes of data. If there's a symbol,
6702 mapping or otherwise, after two bytes then don't
6703 print more. */
6704 if (is_data)
6705 {
6706 size = 4 - (pc & 3);
6707 for (n = last_sym + 1; n < info->symtab_size; n++)
6708 {
6709 addr = bfd_asymbol_value (info->symtab[n]);
6710 if (addr > pc
6711 && (info->section == NULL
6712 || info->section == info->symtab[n]->section))
6713 {
6714 if (addr - pc < size) {
6715 size = addr - pc;
6716 }
6717 break;
6718 }
6719 }
6720 /* If the next symbol is after three bytes, we need to
6721 print only part of the data, so that we can use either
6722 .byte or .short. */
6723 if (size == 3) {
6724 size = (pc & 1) ? 1 : 2;
6725 }
6726 }
6727 }
6728
6729 if (force_thumb) {
6730 is_thumb = TRUE;
6731 }
6732
6733 if (is_data) {
6734 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6735 } else {
6736 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6737 }
6738
6739 info->bytes_per_line = 4;
6740
6741 /* PR 10263: Disassemble data if requested to do so by the user. */
6742 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0)) {
6743 int i;
6744
6745 /* Size was already set above. */
6746 info->bytes_per_chunk = size;
6747 printer = print_insn_data;
6748
6749 status = info->read_memory_func (pc, (bfd_byte *)b, size, info);
6750 given = 0;
6751 if (little) {
6752 for (i = size - 1; i >= 0; i--) {
6753 given = b[i] | (given << 8);
6754 }
6755 } else {
6756 for (i = 0; i < (int)size; i++) {
6757 given = b[i] | (given << 8);
6758 }
6759 }
6760 }
6761 else if (!is_thumb)
6762 {
6763 /* In ARM mode endianness is a straightforward issue: the instruction
6764 is four bytes long and is either ordered 0123 or 3210. */
6765 printer = print_insn_arm;
6766 info->bytes_per_chunk = 4;
6767 size = 4;
6768
6769 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
6770 #define N(x) (((unsigned long long )(b[x])) & 0xff)
6771 if (little_code) {
6772 given = N(0) | N(1) <<8 | N(2) << 16 | N(3) << 24;
6773 } else {
6774 given = N(3) | N(2) <<8 | N(1) << 16 | N(0) << 24;
6775 }
6776 }
6777 else
6778 {
6779 /* In Thumb mode we have the additional wrinkle of two
6780 instruction lengths. Fortunately, the bits that determine
6781 the length of the current instruction are always to be found
6782 in the first two bytes. */
6783 printer = print_insn_thumb16;
6784 info->bytes_per_chunk = 2;
6785 size = 2;
6786
6787 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
6788 if (little_code) {
6789 given = (b[0]) | (b[1] << 8);
6790 } else {
6791 given = (b[1]) | (b[0] << 8);
6792 }
6793
6794 if (!status)
6795 {
6796 /* These bit patterns signal a four-byte Thumb
6797 instruction. */
6798 if ((given & 0xF800) == 0xF800
6799 || (given & 0xF800) == 0xF000
6800 || (given & 0xF800) == 0xE800)
6801 {
6802 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
6803 if (little_code) {
6804 given = (b[0]) | (b[1] << 8) | (given << 16);
6805 } else {
6806 given = (b[1]) | (b[0] << 8) | (given << 16);
6807 }
6808
6809 printer = print_insn_thumb32;
6810 size = 4;
6811 }
6812 }
6813
6814 if (ifthen_address != pc) {
6815 find_ifthen_state (pc, info, little_code);
6816 }
6817
6818 if (ifthen_state) {
6819 if ((ifthen_state & 0xf) == 0x8) {
6820 ifthen_next_state = 0;
6821 } else {
6822 ifthen_next_state = (ifthen_state & 0xe0) | ((ifthen_state & 0xf) << 1);
6823 }
6824 }
6825 }
6826
6827 if (status)
6828 {
6829 info->memory_error_func (status, pc, info);
6830 return -1;
6831 }
6832 if (info->flags & INSN_HAS_RELOC) {
6833 /* If the instruction has a reloc associated with it, then
6834 the offset field in the instruction will actually be the
6835 addend for the reloc. (We are using REL type relocs).
6836 In such cases, we can ignore the pc when computing
6837 addresses, since the addend is not currently pc-relative. */
6838 pc = 0;
6839 }
6840
6841 printer (pc, info, given);
6842
6843 if (is_thumb) {
6844 ifthen_state = ifthen_next_state;
6845 ifthen_address += size;
6846 }
6847 return size;
6848 }
6849
6850 int
print_insn_big_arm(bfd_vma pc,struct disassemble_info * info)6851 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
6852 {
6853 /* Detect BE8-ness and record it in the disassembler info. */
6854 #if 0
6855 if (info->flavour == bfd_target_elf_flavour
6856 && info->section != NULL
6857 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
6858 info->endian_code = BFD_ENDIAN_LITTLE;
6859 #endif
6860
6861 return print_insn (pc, info, FALSE);
6862 }
6863
6864 int
print_insn_little_arm(bfd_vma pc,struct disassemble_info * info)6865 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
6866 {
6867 return print_insn (pc, info, TRUE);
6868 }
6869
6870 const disasm_options_t *
disassembler_options_arm(void)6871 disassembler_options_arm (void)
6872 {
6873 static disasm_options_t *opts = NULL;
6874
6875 if (opts == NULL)
6876 {
6877 unsigned int i;
6878 opts = XNEW (disasm_options_t);
6879 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
6880 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
6881 for (i = 0; i < NUM_ARM_OPTIONS; i++)
6882 {
6883 opts->name[i] = regnames[i].name;
6884 if (regnames[i].description != NULL) {
6885 opts->description[i] = _ (regnames[i].description);
6886 } else {
6887 opts->description[i] = NULL;
6888 }
6889 }
6890 /* The array we return must be NULL terminated. */
6891 opts->name[i] = NULL;
6892 opts->description[i] = NULL;
6893 }
6894
6895 return opts;
6896 }
6897
6898 void
print_arm_disassembler_options(FILE * stream)6899 print_arm_disassembler_options (FILE *stream)
6900 {
6901 unsigned int i, max_len = 0;
6902 fprintf (stream, _("\n\
6903 The following ARM specific disassembler options are supported for use with\n\
6904 the -M switch:\n"));
6905
6906 for (i = 0; i < NUM_ARM_OPTIONS; i++)
6907 {
6908 unsigned int len = strlen (regnames[i].name);
6909 if (max_len < len) {
6910 max_len = len;
6911 }
6912 }
6913
6914 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++) {
6915 fprintf (stream, " %s%*c %s\n",
6916 regnames[i].name,
6917 (int)(max_len - strlen (regnames[i].name)), ' ',
6918 _ (regnames[i].description));
6919 }
6920 }
6921