1;; ARM Cortex-M4 FPU pipeline description
2;; Copyright (C) 2010-2018 Free Software Foundation, Inc.
3;; Contributed by CodeSourcery.
4;;
5;; This file is part of GCC.
6;;
7;; GCC is free software; you can redistribute it and/or modify it
8;; under the terms of the GNU General Public License as published by
9;; the Free Software Foundation; either version 3, or (at your option)
10;; any later version.
11;;
12;; GCC is distributed in the hope that it will be useful, but
13;; WITHOUT ANY WARRANTY; without even the implied warranty of
14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15;; General Public License for more details.
16;;
17;; You should have received a copy of the GNU General Public License
18;; along with GCC; see the file COPYING3.  If not see
19;; <http://www.gnu.org/licenses/>.
20
21;; Use two artificial units to model FPU.
22(define_cpu_unit "cortex_m4_v_a" "cortex_m4")
23(define_cpu_unit "cortex_m4_v_b" "cortex_m4")
24
25(define_reservation "cortex_m4_v" "cortex_m4_v_a+cortex_m4_v_b")
26(define_reservation "cortex_m4_ex_v" "cortex_m4_ex+cortex_m4_v")
27(define_reservation "cortex_m4_exa_va" "cortex_m4_a+cortex_m4_v_a")
28(define_reservation "cortex_m4_exb_vb" "cortex_m4_b+cortex_m4_v_b")
29
30;; Integer instructions following VDIV or VSQRT complete out-of-order.
31(define_insn_reservation "cortex_m4_fdivs" 15
32  (and (eq_attr "tune" "cortexm4")
33       (eq_attr "type" "fdivs, fsqrts"))
34  "cortex_m4_ex_v,cortex_m4_v*13")
35
36(define_insn_reservation "cortex_m4_vmov_1" 1
37  (and (eq_attr "tune" "cortexm4")
38       (eq_attr "type" "fmov,fconsts"))
39  "cortex_m4_ex_v")
40
41(define_insn_reservation "cortex_m4_vmov_2" 2
42  (and (eq_attr "tune" "cortexm4")
43       (eq_attr "type" "f_mrc,f_mrrc,f_mcr,f_mcrr"))
44  "cortex_m4_ex_v*2")
45
46(define_insn_reservation "cortex_m4_fmuls" 2
47  (and (eq_attr "tune" "cortexm4")
48       (eq_attr "type" "fmuls"))
49  "cortex_m4_ex_v")
50
51;; Integer instructions following multiply-accumulate instructions
52;; complete out-of-order.
53(define_insn_reservation "cortex_m4_fmacs" 4
54  (and (eq_attr "tune" "cortexm4")
55       (eq_attr "type" "fmacs,ffmas"))
56  "cortex_m4_ex_v,cortex_m4_v*2")
57
58(define_insn_reservation "cortex_m4_ffariths" 1
59  (and (eq_attr "tune" "cortexm4")
60       (eq_attr "type" "ffariths"))
61  "cortex_m4_ex_v")
62
63(define_insn_reservation "cortex_m4_fadds" 2
64  (and (eq_attr "tune" "cortexm4")
65       (eq_attr "type" "fadds"))
66  "cortex_m4_ex_v")
67
68(define_insn_reservation "cortex_m4_fcmps" 1
69  (and (eq_attr "tune" "cortexm4")
70       (eq_attr "type" "fcmps"))
71  "cortex_m4_ex_v")
72
73(define_insn_reservation "cortex_m4_f_flag" 1
74  (and (eq_attr "tune" "cortexm4")
75       (eq_attr "type" "f_flag"))
76  "cortex_m4_ex_v")
77
78(define_insn_reservation "cortex_m4_f_cvt" 2
79  (and (eq_attr "tune" "cortexm4")
80       (eq_attr "type" "f_cvt,f_cvtf2i,f_cvti2f"))
81  "cortex_m4_ex_v")
82
83(define_insn_reservation "cortex_m4_f_load" 2
84  (and (eq_attr "tune" "cortexm4")
85       (eq_attr "type" "f_loads"))
86  "cortex_m4_exa_va,cortex_m4_exb_vb")
87
88(define_insn_reservation "cortex_m4_f_store" 1
89  (and (eq_attr "tune" "cortexm4")
90       (eq_attr "type" "f_stores"))
91  "cortex_m4_exa_va")
92
93(define_insn_reservation "cortex_m4_f_loadd" 3
94  (and (eq_attr "tune" "cortexm4")
95       (eq_attr "type" "f_loadd"))
96  "cortex_m4_ex_v*3")
97
98(define_insn_reservation "cortex_m4_f_stored" 3
99  (and (eq_attr "tune" "cortexm4")
100       (eq_attr "type" "f_stored"))
101  "cortex_m4_ex_v*3")
102
103;; MAC instructions consume their addend one cycle later. If the result
104;; of an arithmetic instruction is consumed as the addend of the following
105;; MAC instruction, the latency can be decreased by one.
106
107(define_bypass 1 "cortex_m4_fadds,cortex_m4_fmuls,cortex_m4_f_cvt"
108		 "cortex_m4_fmacs"
109		 "arm_no_early_mul_dep")
110
111(define_bypass 3 "cortex_m4_fmacs"
112		 "cortex_m4_fmacs"
113		 "arm_no_early_mul_dep")
114
115(define_bypass 14 "cortex_m4_fdivs"
116		  "cortex_m4_fmacs"
117		  "arm_no_early_mul_dep")
118