1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2018 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
10 version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20
21
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
24 split.
25
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
33
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
37 allocations;
38 o some heuristics to choose insn alternative to improve the
39 inheritance;
40 o early clobbers etc.
41
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
45 changed.
46
47 There is special code for preventing all LRA and this pass cycling
48 in case of bugs.
49
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
54
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
57 traversal of EBBs.
58
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
62
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
65 ... => ...
66 reload_p2 <- p reload_p2 <- new_p
67
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
70 pseudo*.
71
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
75
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
82 insns.
83
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
86
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
89 ... =>
90 ... r <- s (new insn -- restore)
91 ... <- r ... <- r
92
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
95
96 Splitting is done:
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
101
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
106
107 #undef REG_OK_STRICT
108
109 #include "config.h"
110 #include "system.h"
111 #include "coretypes.h"
112 #include "backend.h"
113 #include "target.h"
114 #include "rtl.h"
115 #include "tree.h"
116 #include "predict.h"
117 #include "df.h"
118 #include "memmodel.h"
119 #include "tm_p.h"
120 #include "expmed.h"
121 #include "optabs.h"
122 #include "regs.h"
123 #include "ira.h"
124 #include "recog.h"
125 #include "output.h"
126 #include "addresses.h"
127 #include "expr.h"
128 #include "cfgrtl.h"
129 #include "rtl-error.h"
130 #include "params.h"
131 #include "lra.h"
132 #include "lra-int.h"
133 #include "print-rtl.h"
134
135 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
136 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
137 reload insns. */
138 static int bb_reload_num;
139
140 /* The current insn being processed and corresponding its single set
141 (NULL otherwise), its data (basic block, the insn data, the insn
142 static data, and the mode of each operand). */
143 static rtx_insn *curr_insn;
144 static rtx curr_insn_set;
145 static basic_block curr_bb;
146 static lra_insn_recog_data_t curr_id;
147 static struct lra_static_insn_data *curr_static_id;
148 static machine_mode curr_operand_mode[MAX_RECOG_OPERANDS];
149 /* Mode of the register substituted by its equivalence with VOIDmode
150 (e.g. constant) and whose subreg is given operand of the current
151 insn. VOIDmode in all other cases. */
152 static machine_mode original_subreg_reg_mode[MAX_RECOG_OPERANDS];
153
154
155
156 /* Start numbers for new registers and insns at the current constraints
157 pass start. */
158 static int new_regno_start;
159 static int new_insn_uid_start;
160
161 /* If LOC is nonnull, strip any outer subreg from it. */
162 static inline rtx *
strip_subreg(rtx * loc)163 strip_subreg (rtx *loc)
164 {
165 return loc && GET_CODE (*loc) == SUBREG ? &SUBREG_REG (*loc) : loc;
166 }
167
168 /* Return hard regno of REGNO or if it is was not assigned to a hard
169 register, use a hard register from its allocno class. */
170 static int
get_try_hard_regno(int regno)171 get_try_hard_regno (int regno)
172 {
173 int hard_regno;
174 enum reg_class rclass;
175
176 if ((hard_regno = regno) >= FIRST_PSEUDO_REGISTER)
177 hard_regno = lra_get_regno_hard_regno (regno);
178 if (hard_regno >= 0)
179 return hard_regno;
180 rclass = lra_get_allocno_class (regno);
181 if (rclass == NO_REGS)
182 return -1;
183 return ira_class_hard_regs[rclass][0];
184 }
185
186 /* Return the hard regno of X after removing its subreg. If X is not
187 a register or a subreg of a register, return -1. If X is a pseudo,
188 use its assignment. If FINAL_P return the final hard regno which will
189 be after elimination. */
190 static int
get_hard_regno(rtx x,bool final_p)191 get_hard_regno (rtx x, bool final_p)
192 {
193 rtx reg;
194 int hard_regno;
195
196 reg = x;
197 if (SUBREG_P (x))
198 reg = SUBREG_REG (x);
199 if (! REG_P (reg))
200 return -1;
201 if (! HARD_REGISTER_NUM_P (hard_regno = REGNO (reg)))
202 hard_regno = lra_get_regno_hard_regno (hard_regno);
203 if (hard_regno < 0)
204 return -1;
205 if (final_p)
206 hard_regno = lra_get_elimination_hard_regno (hard_regno);
207 if (SUBREG_P (x))
208 hard_regno += subreg_regno_offset (hard_regno, GET_MODE (reg),
209 SUBREG_BYTE (x), GET_MODE (x));
210 return hard_regno;
211 }
212
213 /* If REGNO is a hard register or has been allocated a hard register,
214 return the class of that register. If REGNO is a reload pseudo
215 created by the current constraints pass, return its allocno class.
216 Return NO_REGS otherwise. */
217 static enum reg_class
get_reg_class(int regno)218 get_reg_class (int regno)
219 {
220 int hard_regno;
221
222 if (! HARD_REGISTER_NUM_P (hard_regno = regno))
223 hard_regno = lra_get_regno_hard_regno (regno);
224 if (hard_regno >= 0)
225 {
226 hard_regno = lra_get_elimination_hard_regno (hard_regno);
227 return REGNO_REG_CLASS (hard_regno);
228 }
229 if (regno >= new_regno_start)
230 return lra_get_allocno_class (regno);
231 return NO_REGS;
232 }
233
234 /* Return true if REG satisfies (or will satisfy) reg class constraint
235 CL. Use elimination first if REG is a hard register. If REG is a
236 reload pseudo created by this constraints pass, assume that it will
237 be allocated a hard register from its allocno class, but allow that
238 class to be narrowed to CL if it is currently a superset of CL.
239
240 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
241 REGNO (reg), or NO_REGS if no change in its class was needed. */
242 static bool
in_class_p(rtx reg,enum reg_class cl,enum reg_class * new_class)243 in_class_p (rtx reg, enum reg_class cl, enum reg_class *new_class)
244 {
245 enum reg_class rclass, common_class;
246 machine_mode reg_mode;
247 int class_size, hard_regno, nregs, i, j;
248 int regno = REGNO (reg);
249
250 if (new_class != NULL)
251 *new_class = NO_REGS;
252 if (regno < FIRST_PSEUDO_REGISTER)
253 {
254 rtx final_reg = reg;
255 rtx *final_loc = &final_reg;
256
257 lra_eliminate_reg_if_possible (final_loc);
258 return TEST_HARD_REG_BIT (reg_class_contents[cl], REGNO (*final_loc));
259 }
260 reg_mode = GET_MODE (reg);
261 rclass = get_reg_class (regno);
262 if (regno < new_regno_start
263 /* Do not allow the constraints for reload instructions to
264 influence the classes of new pseudos. These reloads are
265 typically moves that have many alternatives, and restricting
266 reload pseudos for one alternative may lead to situations
267 where other reload pseudos are no longer allocatable. */
268 || (INSN_UID (curr_insn) >= new_insn_uid_start
269 && curr_insn_set != NULL
270 && ((OBJECT_P (SET_SRC (curr_insn_set))
271 && ! CONSTANT_P (SET_SRC (curr_insn_set)))
272 || (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG
273 && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set)))
274 && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set)))))))
275 /* When we don't know what class will be used finally for reload
276 pseudos, we use ALL_REGS. */
277 return ((regno >= new_regno_start && rclass == ALL_REGS)
278 || (rclass != NO_REGS && ira_class_subset_p[rclass][cl]
279 && ! hard_reg_set_subset_p (reg_class_contents[cl],
280 lra_no_alloc_regs)));
281 else
282 {
283 common_class = ira_reg_class_subset[rclass][cl];
284 if (new_class != NULL)
285 *new_class = common_class;
286 if (hard_reg_set_subset_p (reg_class_contents[common_class],
287 lra_no_alloc_regs))
288 return false;
289 /* Check that there are enough allocatable regs. */
290 class_size = ira_class_hard_regs_num[common_class];
291 for (i = 0; i < class_size; i++)
292 {
293 hard_regno = ira_class_hard_regs[common_class][i];
294 nregs = hard_regno_nregs (hard_regno, reg_mode);
295 if (nregs == 1)
296 return true;
297 for (j = 0; j < nregs; j++)
298 if (TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno + j)
299 || ! TEST_HARD_REG_BIT (reg_class_contents[common_class],
300 hard_regno + j))
301 break;
302 if (j >= nregs)
303 return true;
304 }
305 return false;
306 }
307 }
308
309 /* Return true if REGNO satisfies a memory constraint. */
310 static bool
in_mem_p(int regno)311 in_mem_p (int regno)
312 {
313 return get_reg_class (regno) == NO_REGS;
314 }
315
316 /* Return 1 if ADDR is a valid memory address for mode MODE in address
317 space AS, and check that each pseudo has the proper kind of hard
318 reg. */
319 static int
valid_address_p(machine_mode mode ATTRIBUTE_UNUSED,rtx addr,addr_space_t as)320 valid_address_p (machine_mode mode ATTRIBUTE_UNUSED,
321 rtx addr, addr_space_t as)
322 {
323 #ifdef GO_IF_LEGITIMATE_ADDRESS
324 lra_assert (ADDR_SPACE_GENERIC_P (as));
325 GO_IF_LEGITIMATE_ADDRESS (mode, addr, win);
326 return 0;
327
328 win:
329 return 1;
330 #else
331 return targetm.addr_space.legitimate_address_p (mode, addr, 0, as);
332 #endif
333 }
334
335 namespace {
336 /* Temporarily eliminates registers in an address (for the lifetime of
337 the object). */
338 class address_eliminator {
339 public:
340 address_eliminator (struct address_info *ad);
341 ~address_eliminator ();
342
343 private:
344 struct address_info *m_ad;
345 rtx *m_base_loc;
346 rtx m_base_reg;
347 rtx *m_index_loc;
348 rtx m_index_reg;
349 };
350 }
351
address_eliminator(struct address_info * ad)352 address_eliminator::address_eliminator (struct address_info *ad)
353 : m_ad (ad),
354 m_base_loc (strip_subreg (ad->base_term)),
355 m_base_reg (NULL_RTX),
356 m_index_loc (strip_subreg (ad->index_term)),
357 m_index_reg (NULL_RTX)
358 {
359 if (m_base_loc != NULL)
360 {
361 m_base_reg = *m_base_loc;
362 lra_eliminate_reg_if_possible (m_base_loc);
363 if (m_ad->base_term2 != NULL)
364 *m_ad->base_term2 = *m_ad->base_term;
365 }
366 if (m_index_loc != NULL)
367 {
368 m_index_reg = *m_index_loc;
369 lra_eliminate_reg_if_possible (m_index_loc);
370 }
371 }
372
~address_eliminator()373 address_eliminator::~address_eliminator ()
374 {
375 if (m_base_loc && *m_base_loc != m_base_reg)
376 {
377 *m_base_loc = m_base_reg;
378 if (m_ad->base_term2 != NULL)
379 *m_ad->base_term2 = *m_ad->base_term;
380 }
381 if (m_index_loc && *m_index_loc != m_index_reg)
382 *m_index_loc = m_index_reg;
383 }
384
385 /* Return true if the eliminated form of AD is a legitimate target address. */
386 static bool
valid_address_p(struct address_info * ad)387 valid_address_p (struct address_info *ad)
388 {
389 address_eliminator eliminator (ad);
390 return valid_address_p (ad->mode, *ad->outer, ad->as);
391 }
392
393 /* Return true if the eliminated form of memory reference OP satisfies
394 extra (special) memory constraint CONSTRAINT. */
395 static bool
satisfies_memory_constraint_p(rtx op,enum constraint_num constraint)396 satisfies_memory_constraint_p (rtx op, enum constraint_num constraint)
397 {
398 struct address_info ad;
399
400 decompose_mem_address (&ad, op);
401 address_eliminator eliminator (&ad);
402 return constraint_satisfied_p (op, constraint);
403 }
404
405 /* Return true if the eliminated form of address AD satisfies extra
406 address constraint CONSTRAINT. */
407 static bool
satisfies_address_constraint_p(struct address_info * ad,enum constraint_num constraint)408 satisfies_address_constraint_p (struct address_info *ad,
409 enum constraint_num constraint)
410 {
411 address_eliminator eliminator (ad);
412 return constraint_satisfied_p (*ad->outer, constraint);
413 }
414
415 /* Return true if the eliminated form of address OP satisfies extra
416 address constraint CONSTRAINT. */
417 static bool
satisfies_address_constraint_p(rtx op,enum constraint_num constraint)418 satisfies_address_constraint_p (rtx op, enum constraint_num constraint)
419 {
420 struct address_info ad;
421
422 decompose_lea_address (&ad, &op);
423 return satisfies_address_constraint_p (&ad, constraint);
424 }
425
426 /* Initiate equivalences for LRA. As we keep original equivalences
427 before any elimination, we need to make copies otherwise any change
428 in insns might change the equivalences. */
429 void
lra_init_equiv(void)430 lra_init_equiv (void)
431 {
432 ira_expand_reg_equiv ();
433 for (int i = FIRST_PSEUDO_REGISTER; i < max_reg_num (); i++)
434 {
435 rtx res;
436
437 if ((res = ira_reg_equiv[i].memory) != NULL_RTX)
438 ira_reg_equiv[i].memory = copy_rtx (res);
439 if ((res = ira_reg_equiv[i].invariant) != NULL_RTX)
440 ira_reg_equiv[i].invariant = copy_rtx (res);
441 }
442 }
443
444 static rtx loc_equivalence_callback (rtx, const_rtx, void *);
445
446 /* Update equivalence for REGNO. We need to this as the equivalence
447 might contain other pseudos which are changed by their
448 equivalences. */
449 static void
update_equiv(int regno)450 update_equiv (int regno)
451 {
452 rtx x;
453
454 if ((x = ira_reg_equiv[regno].memory) != NULL_RTX)
455 ira_reg_equiv[regno].memory
456 = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback,
457 NULL_RTX);
458 if ((x = ira_reg_equiv[regno].invariant) != NULL_RTX)
459 ira_reg_equiv[regno].invariant
460 = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback,
461 NULL_RTX);
462 }
463
464 /* If we have decided to substitute X with another value, return that
465 value, otherwise return X. */
466 static rtx
get_equiv(rtx x)467 get_equiv (rtx x)
468 {
469 int regno;
470 rtx res;
471
472 if (! REG_P (x) || (regno = REGNO (x)) < FIRST_PSEUDO_REGISTER
473 || ! ira_reg_equiv[regno].defined_p
474 || ! ira_reg_equiv[regno].profitable_p
475 || lra_get_regno_hard_regno (regno) >= 0)
476 return x;
477 if ((res = ira_reg_equiv[regno].memory) != NULL_RTX)
478 {
479 if (targetm.cannot_substitute_mem_equiv_p (res))
480 return x;
481 return res;
482 }
483 if ((res = ira_reg_equiv[regno].constant) != NULL_RTX)
484 return res;
485 if ((res = ira_reg_equiv[regno].invariant) != NULL_RTX)
486 return res;
487 gcc_unreachable ();
488 }
489
490 /* If we have decided to substitute X with the equivalent value,
491 return that value after elimination for INSN, otherwise return
492 X. */
493 static rtx
get_equiv_with_elimination(rtx x,rtx_insn * insn)494 get_equiv_with_elimination (rtx x, rtx_insn *insn)
495 {
496 rtx res = get_equiv (x);
497
498 if (x == res || CONSTANT_P (res))
499 return res;
500 return lra_eliminate_regs_1 (insn, res, GET_MODE (res),
501 false, false, 0, true);
502 }
503
504 /* Set up curr_operand_mode. */
505 static void
init_curr_operand_mode(void)506 init_curr_operand_mode (void)
507 {
508 int nop = curr_static_id->n_operands;
509 for (int i = 0; i < nop; i++)
510 {
511 machine_mode mode = GET_MODE (*curr_id->operand_loc[i]);
512 if (mode == VOIDmode)
513 {
514 /* The .md mode for address operands is the mode of the
515 addressed value rather than the mode of the address itself. */
516 if (curr_id->icode >= 0 && curr_static_id->operand[i].is_address)
517 mode = Pmode;
518 else
519 mode = curr_static_id->operand[i].mode;
520 }
521 curr_operand_mode[i] = mode;
522 }
523 }
524
525
526
527 /* The page contains code to reuse input reloads. */
528
529 /* Structure describes input reload of the current insns. */
530 struct input_reload
531 {
532 /* True for input reload of matched operands. */
533 bool match_p;
534 /* Reloaded value. */
535 rtx input;
536 /* Reload pseudo used. */
537 rtx reg;
538 };
539
540 /* The number of elements in the following array. */
541 static int curr_insn_input_reloads_num;
542 /* Array containing info about input reloads. It is used to find the
543 same input reload and reuse the reload pseudo in this case. */
544 static struct input_reload curr_insn_input_reloads[LRA_MAX_INSN_RELOADS];
545
546 /* Initiate data concerning reuse of input reloads for the current
547 insn. */
548 static void
init_curr_insn_input_reloads(void)549 init_curr_insn_input_reloads (void)
550 {
551 curr_insn_input_reloads_num = 0;
552 }
553
554 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
555 created input reload pseudo (only if TYPE is not OP_OUT). Don't
556 reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be
557 wrapped up in SUBREG. The result pseudo is returned through
558 RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we
559 reused the already created input reload pseudo. Use TITLE to
560 describe new registers for debug purposes. */
561 static bool
get_reload_reg(enum op_type type,machine_mode mode,rtx original,enum reg_class rclass,bool in_subreg_p,const char * title,rtx * result_reg)562 get_reload_reg (enum op_type type, machine_mode mode, rtx original,
563 enum reg_class rclass, bool in_subreg_p,
564 const char *title, rtx *result_reg)
565 {
566 int i, regno;
567 enum reg_class new_class;
568 bool unique_p = false;
569
570 if (type == OP_OUT)
571 {
572 *result_reg
573 = lra_create_new_reg_with_unique_value (mode, original, rclass, title);
574 return true;
575 }
576 /* Prevent reuse value of expression with side effects,
577 e.g. volatile memory. */
578 if (! side_effects_p (original))
579 for (i = 0; i < curr_insn_input_reloads_num; i++)
580 {
581 if (! curr_insn_input_reloads[i].match_p
582 && rtx_equal_p (curr_insn_input_reloads[i].input, original)
583 && in_class_p (curr_insn_input_reloads[i].reg, rclass, &new_class))
584 {
585 rtx reg = curr_insn_input_reloads[i].reg;
586 regno = REGNO (reg);
587 /* If input is equal to original and both are VOIDmode,
588 GET_MODE (reg) might be still different from mode.
589 Ensure we don't return *result_reg with wrong mode. */
590 if (GET_MODE (reg) != mode)
591 {
592 if (in_subreg_p)
593 continue;
594 if (maybe_lt (GET_MODE_SIZE (GET_MODE (reg)),
595 GET_MODE_SIZE (mode)))
596 continue;
597 reg = lowpart_subreg (mode, reg, GET_MODE (reg));
598 if (reg == NULL_RTX || GET_CODE (reg) != SUBREG)
599 continue;
600 }
601 *result_reg = reg;
602 if (lra_dump_file != NULL)
603 {
604 fprintf (lra_dump_file, " Reuse r%d for reload ", regno);
605 dump_value_slim (lra_dump_file, original, 1);
606 }
607 if (new_class != lra_get_allocno_class (regno))
608 lra_change_class (regno, new_class, ", change to", false);
609 if (lra_dump_file != NULL)
610 fprintf (lra_dump_file, "\n");
611 return false;
612 }
613 /* If we have an input reload with a different mode, make sure it
614 will get a different hard reg. */
615 else if (REG_P (original)
616 && REG_P (curr_insn_input_reloads[i].input)
617 && REGNO (original) == REGNO (curr_insn_input_reloads[i].input)
618 && (GET_MODE (original)
619 != GET_MODE (curr_insn_input_reloads[i].input)))
620 unique_p = true;
621 }
622 *result_reg = (unique_p
623 ? lra_create_new_reg_with_unique_value
624 : lra_create_new_reg) (mode, original, rclass, title);
625 lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS);
626 curr_insn_input_reloads[curr_insn_input_reloads_num].input = original;
627 curr_insn_input_reloads[curr_insn_input_reloads_num].match_p = false;
628 curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = *result_reg;
629 return true;
630 }
631
632
633
634 /* The page contains code to extract memory address parts. */
635
636 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
637 static inline bool
ok_for_index_p_nonstrict(rtx reg)638 ok_for_index_p_nonstrict (rtx reg)
639 {
640 unsigned regno = REGNO (reg);
641
642 return regno >= FIRST_PSEUDO_REGISTER || REGNO_OK_FOR_INDEX_P (regno);
643 }
644
645 /* A version of regno_ok_for_base_p for use here, when all pseudos
646 should count as OK. Arguments as for regno_ok_for_base_p. */
647 static inline bool
ok_for_base_p_nonstrict(rtx reg,machine_mode mode,addr_space_t as,enum rtx_code outer_code,enum rtx_code index_code)648 ok_for_base_p_nonstrict (rtx reg, machine_mode mode, addr_space_t as,
649 enum rtx_code outer_code, enum rtx_code index_code)
650 {
651 unsigned regno = REGNO (reg);
652
653 if (regno >= FIRST_PSEUDO_REGISTER)
654 return true;
655 return ok_for_base_p_1 (regno, mode, as, outer_code, index_code);
656 }
657
658
659
660 /* The page contains major code to choose the current insn alternative
661 and generate reloads for it. */
662
663 /* Return the offset from REGNO of the least significant register
664 in (reg:MODE REGNO).
665
666 This function is used to tell whether two registers satisfy
667 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
668
669 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
670 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
671 int
lra_constraint_offset(int regno,machine_mode mode)672 lra_constraint_offset (int regno, machine_mode mode)
673 {
674 lra_assert (regno < FIRST_PSEUDO_REGISTER);
675
676 scalar_int_mode int_mode;
677 if (WORDS_BIG_ENDIAN
678 && is_a <scalar_int_mode> (mode, &int_mode)
679 && GET_MODE_SIZE (int_mode) > UNITS_PER_WORD)
680 return hard_regno_nregs (regno, mode) - 1;
681 return 0;
682 }
683
684 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
685 if they are the same hard reg, and has special hacks for
686 auto-increment and auto-decrement. This is specifically intended for
687 process_alt_operands to use in determining whether two operands
688 match. X is the operand whose number is the lower of the two.
689
690 It is supposed that X is the output operand and Y is the input
691 operand. Y_HARD_REGNO is the final hard regno of register Y or
692 register in subreg Y as we know it now. Otherwise, it is a
693 negative value. */
694 static bool
operands_match_p(rtx x,rtx y,int y_hard_regno)695 operands_match_p (rtx x, rtx y, int y_hard_regno)
696 {
697 int i;
698 RTX_CODE code = GET_CODE (x);
699 const char *fmt;
700
701 if (x == y)
702 return true;
703 if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x))))
704 && (REG_P (y) || (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y)))))
705 {
706 int j;
707
708 i = get_hard_regno (x, false);
709 if (i < 0)
710 goto slow;
711
712 if ((j = y_hard_regno) < 0)
713 goto slow;
714
715 i += lra_constraint_offset (i, GET_MODE (x));
716 j += lra_constraint_offset (j, GET_MODE (y));
717
718 return i == j;
719 }
720
721 /* If two operands must match, because they are really a single
722 operand of an assembler insn, then two post-increments are invalid
723 because the assembler insn would increment only once. On the
724 other hand, a post-increment matches ordinary indexing if the
725 post-increment is the output operand. */
726 if (code == POST_DEC || code == POST_INC || code == POST_MODIFY)
727 return operands_match_p (XEXP (x, 0), y, y_hard_regno);
728
729 /* Two pre-increments are invalid because the assembler insn would
730 increment only once. On the other hand, a pre-increment matches
731 ordinary indexing if the pre-increment is the input operand. */
732 if (GET_CODE (y) == PRE_DEC || GET_CODE (y) == PRE_INC
733 || GET_CODE (y) == PRE_MODIFY)
734 return operands_match_p (x, XEXP (y, 0), -1);
735
736 slow:
737
738 if (code == REG && REG_P (y))
739 return REGNO (x) == REGNO (y);
740
741 if (code == REG && GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y))
742 && x == SUBREG_REG (y))
743 return true;
744 if (GET_CODE (y) == REG && code == SUBREG && REG_P (SUBREG_REG (x))
745 && SUBREG_REG (x) == y)
746 return true;
747
748 /* Now we have disposed of all the cases in which different rtx
749 codes can match. */
750 if (code != GET_CODE (y))
751 return false;
752
753 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
754 if (GET_MODE (x) != GET_MODE (y))
755 return false;
756
757 switch (code)
758 {
759 CASE_CONST_UNIQUE:
760 return false;
761
762 case LABEL_REF:
763 return label_ref_label (x) == label_ref_label (y);
764 case SYMBOL_REF:
765 return XSTR (x, 0) == XSTR (y, 0);
766
767 default:
768 break;
769 }
770
771 /* Compare the elements. If any pair of corresponding elements fail
772 to match, return false for the whole things. */
773
774 fmt = GET_RTX_FORMAT (code);
775 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
776 {
777 int val, j;
778 switch (fmt[i])
779 {
780 case 'w':
781 if (XWINT (x, i) != XWINT (y, i))
782 return false;
783 break;
784
785 case 'i':
786 if (XINT (x, i) != XINT (y, i))
787 return false;
788 break;
789
790 case 'p':
791 if (maybe_ne (SUBREG_BYTE (x), SUBREG_BYTE (y)))
792 return false;
793 break;
794
795 case 'e':
796 val = operands_match_p (XEXP (x, i), XEXP (y, i), -1);
797 if (val == 0)
798 return false;
799 break;
800
801 case '0':
802 break;
803
804 case 'E':
805 if (XVECLEN (x, i) != XVECLEN (y, i))
806 return false;
807 for (j = XVECLEN (x, i) - 1; j >= 0; --j)
808 {
809 val = operands_match_p (XVECEXP (x, i, j), XVECEXP (y, i, j), -1);
810 if (val == 0)
811 return false;
812 }
813 break;
814
815 /* It is believed that rtx's at this level will never
816 contain anything but integers and other rtx's, except for
817 within LABEL_REFs and SYMBOL_REFs. */
818 default:
819 gcc_unreachable ();
820 }
821 }
822 return true;
823 }
824
825 /* True if X is a constant that can be forced into the constant pool.
826 MODE is the mode of the operand, or VOIDmode if not known. */
827 #define CONST_POOL_OK_P(MODE, X) \
828 ((MODE) != VOIDmode \
829 && CONSTANT_P (X) \
830 && GET_CODE (X) != HIGH \
831 && GET_MODE_SIZE (MODE).is_constant () \
832 && !targetm.cannot_force_const_mem (MODE, X))
833
834 /* True if C is a non-empty register class that has too few registers
835 to be safely used as a reload target class. */
836 #define SMALL_REGISTER_CLASS_P(C) \
837 (ira_class_hard_regs_num [(C)] == 1 \
838 || (ira_class_hard_regs_num [(C)] >= 1 \
839 && targetm.class_likely_spilled_p (C)))
840
841 /* If REG is a reload pseudo, try to make its class satisfying CL. */
842 static void
narrow_reload_pseudo_class(rtx reg,enum reg_class cl)843 narrow_reload_pseudo_class (rtx reg, enum reg_class cl)
844 {
845 enum reg_class rclass;
846
847 /* Do not make more accurate class from reloads generated. They are
848 mostly moves with a lot of constraints. Making more accurate
849 class may results in very narrow class and impossibility of find
850 registers for several reloads of one insn. */
851 if (INSN_UID (curr_insn) >= new_insn_uid_start)
852 return;
853 if (GET_CODE (reg) == SUBREG)
854 reg = SUBREG_REG (reg);
855 if (! REG_P (reg) || (int) REGNO (reg) < new_regno_start)
856 return;
857 if (in_class_p (reg, cl, &rclass) && rclass != cl)
858 lra_change_class (REGNO (reg), rclass, " Change to", true);
859 }
860
861 /* Searches X for any reference to a reg with the same value as REGNO,
862 returning the rtx of the reference found if any. Otherwise,
863 returns NULL_RTX. */
864 static rtx
regno_val_use_in(unsigned int regno,rtx x)865 regno_val_use_in (unsigned int regno, rtx x)
866 {
867 const char *fmt;
868 int i, j;
869 rtx tem;
870
871 if (REG_P (x) && lra_reg_info[REGNO (x)].val == lra_reg_info[regno].val)
872 return x;
873
874 fmt = GET_RTX_FORMAT (GET_CODE (x));
875 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
876 {
877 if (fmt[i] == 'e')
878 {
879 if ((tem = regno_val_use_in (regno, XEXP (x, i))))
880 return tem;
881 }
882 else if (fmt[i] == 'E')
883 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
884 if ((tem = regno_val_use_in (regno , XVECEXP (x, i, j))))
885 return tem;
886 }
887
888 return NULL_RTX;
889 }
890
891 /* Return true if all current insn non-output operands except INS (it
892 has a negaitve end marker) do not use pseudos with the same value
893 as REGNO. */
894 static bool
check_conflict_input_operands(int regno,signed char * ins)895 check_conflict_input_operands (int regno, signed char *ins)
896 {
897 int in;
898 int n_operands = curr_static_id->n_operands;
899
900 for (int nop = 0; nop < n_operands; nop++)
901 if (! curr_static_id->operand[nop].is_operator
902 && curr_static_id->operand[nop].type != OP_OUT)
903 {
904 for (int i = 0; (in = ins[i]) >= 0; i++)
905 if (in == nop)
906 break;
907 if (in < 0
908 && regno_val_use_in (regno, *curr_id->operand_loc[nop]) != NULL_RTX)
909 return false;
910 }
911 return true;
912 }
913
914 /* Generate reloads for matching OUT and INS (array of input operand
915 numbers with end marker -1) with reg class GOAL_CLASS, considering
916 output operands OUTS (similar array to INS) needing to be in different
917 registers. Add input and output reloads correspondingly to the lists
918 *BEFORE and *AFTER. OUT might be negative. In this case we generate
919 input reloads for matched input operands INS. EARLY_CLOBBER_P is a flag
920 that the output operand is early clobbered for chosen alternative. */
921 static void
match_reload(signed char out,signed char * ins,signed char * outs,enum reg_class goal_class,rtx_insn ** before,rtx_insn ** after,bool early_clobber_p)922 match_reload (signed char out, signed char *ins, signed char *outs,
923 enum reg_class goal_class, rtx_insn **before,
924 rtx_insn **after, bool early_clobber_p)
925 {
926 bool out_conflict;
927 int i, in;
928 rtx new_in_reg, new_out_reg, reg;
929 machine_mode inmode, outmode;
930 rtx in_rtx = *curr_id->operand_loc[ins[0]];
931 rtx out_rtx = out < 0 ? in_rtx : *curr_id->operand_loc[out];
932
933 inmode = curr_operand_mode[ins[0]];
934 outmode = out < 0 ? inmode : curr_operand_mode[out];
935 push_to_sequence (*before);
936 if (inmode != outmode)
937 {
938 /* process_alt_operands has already checked that the mode sizes
939 are ordered. */
940 if (partial_subreg_p (outmode, inmode))
941 {
942 reg = new_in_reg
943 = lra_create_new_reg_with_unique_value (inmode, in_rtx,
944 goal_class, "");
945 new_out_reg = gen_lowpart_SUBREG (outmode, reg);
946 LRA_SUBREG_P (new_out_reg) = 1;
947 /* If the input reg is dying here, we can use the same hard
948 register for REG and IN_RTX. We do it only for original
949 pseudos as reload pseudos can die although original
950 pseudos still live where reload pseudos dies. */
951 if (REG_P (in_rtx) && (int) REGNO (in_rtx) < lra_new_regno_start
952 && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx))
953 && (!early_clobber_p
954 || check_conflict_input_operands(REGNO (in_rtx), ins)))
955 lra_assign_reg_val (REGNO (in_rtx), REGNO (reg));
956 }
957 else
958 {
959 reg = new_out_reg
960 = lra_create_new_reg_with_unique_value (outmode, out_rtx,
961 goal_class, "");
962 new_in_reg = gen_lowpart_SUBREG (inmode, reg);
963 /* NEW_IN_REG is non-paradoxical subreg. We don't want
964 NEW_OUT_REG living above. We add clobber clause for
965 this. This is just a temporary clobber. We can remove
966 it at the end of LRA work. */
967 rtx_insn *clobber = emit_clobber (new_out_reg);
968 LRA_TEMP_CLOBBER_P (PATTERN (clobber)) = 1;
969 LRA_SUBREG_P (new_in_reg) = 1;
970 if (GET_CODE (in_rtx) == SUBREG)
971 {
972 rtx subreg_reg = SUBREG_REG (in_rtx);
973
974 /* If SUBREG_REG is dying here and sub-registers IN_RTX
975 and NEW_IN_REG are similar, we can use the same hard
976 register for REG and SUBREG_REG. */
977 if (REG_P (subreg_reg)
978 && (int) REGNO (subreg_reg) < lra_new_regno_start
979 && GET_MODE (subreg_reg) == outmode
980 && known_eq (SUBREG_BYTE (in_rtx), SUBREG_BYTE (new_in_reg))
981 && find_regno_note (curr_insn, REG_DEAD, REGNO (subreg_reg))
982 && (! early_clobber_p
983 || check_conflict_input_operands (REGNO (subreg_reg),
984 ins)))
985 lra_assign_reg_val (REGNO (subreg_reg), REGNO (reg));
986 }
987 }
988 }
989 else
990 {
991 /* Pseudos have values -- see comments for lra_reg_info.
992 Different pseudos with the same value do not conflict even if
993 they live in the same place. When we create a pseudo we
994 assign value of original pseudo (if any) from which we
995 created the new pseudo. If we create the pseudo from the
996 input pseudo, the new pseudo will have no conflict with the
997 input pseudo which is wrong when the input pseudo lives after
998 the insn and as the new pseudo value is changed by the insn
999 output. Therefore we create the new pseudo from the output
1000 except the case when we have single matched dying input
1001 pseudo.
1002
1003 We cannot reuse the current output register because we might
1004 have a situation like "a <- a op b", where the constraints
1005 force the second input operand ("b") to match the output
1006 operand ("a"). "b" must then be copied into a new register
1007 so that it doesn't clobber the current value of "a".
1008
1009 We can not use the same value if the output pseudo is
1010 early clobbered or the input pseudo is mentioned in the
1011 output, e.g. as an address part in memory, because
1012 output reload will actually extend the pseudo liveness.
1013 We don't care about eliminable hard regs here as we are
1014 interesting only in pseudos. */
1015
1016 /* Matching input's register value is the same as one of the other
1017 output operand. Output operands in a parallel insn must be in
1018 different registers. */
1019 out_conflict = false;
1020 if (REG_P (in_rtx))
1021 {
1022 for (i = 0; outs[i] >= 0; i++)
1023 {
1024 rtx other_out_rtx = *curr_id->operand_loc[outs[i]];
1025 if (REG_P (other_out_rtx)
1026 && (regno_val_use_in (REGNO (in_rtx), other_out_rtx)
1027 != NULL_RTX))
1028 {
1029 out_conflict = true;
1030 break;
1031 }
1032 }
1033 }
1034
1035 new_in_reg = new_out_reg
1036 = (! early_clobber_p && ins[1] < 0 && REG_P (in_rtx)
1037 && (int) REGNO (in_rtx) < lra_new_regno_start
1038 && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx))
1039 && (! early_clobber_p
1040 || check_conflict_input_operands (REGNO (in_rtx), ins))
1041 && (out < 0
1042 || regno_val_use_in (REGNO (in_rtx), out_rtx) == NULL_RTX)
1043 && !out_conflict
1044 ? lra_create_new_reg (inmode, in_rtx, goal_class, "")
1045 : lra_create_new_reg_with_unique_value (outmode, out_rtx,
1046 goal_class, ""));
1047 }
1048 /* In operand can be got from transformations before processing insn
1049 constraints. One example of such transformations is subreg
1050 reloading (see function simplify_operand_subreg). The new
1051 pseudos created by the transformations might have inaccurate
1052 class (ALL_REGS) and we should make their classes more
1053 accurate. */
1054 narrow_reload_pseudo_class (in_rtx, goal_class);
1055 lra_emit_move (copy_rtx (new_in_reg), in_rtx);
1056 *before = get_insns ();
1057 end_sequence ();
1058 /* Add the new pseudo to consider values of subsequent input reload
1059 pseudos. */
1060 lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS);
1061 curr_insn_input_reloads[curr_insn_input_reloads_num].input = in_rtx;
1062 curr_insn_input_reloads[curr_insn_input_reloads_num].match_p = true;
1063 curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = new_in_reg;
1064 for (i = 0; (in = ins[i]) >= 0; i++)
1065 {
1066 lra_assert
1067 (GET_MODE (*curr_id->operand_loc[in]) == VOIDmode
1068 || GET_MODE (new_in_reg) == GET_MODE (*curr_id->operand_loc[in]));
1069 *curr_id->operand_loc[in] = new_in_reg;
1070 }
1071 lra_update_dups (curr_id, ins);
1072 if (out < 0)
1073 return;
1074 /* See a comment for the input operand above. */
1075 narrow_reload_pseudo_class (out_rtx, goal_class);
1076 if (find_reg_note (curr_insn, REG_UNUSED, out_rtx) == NULL_RTX)
1077 {
1078 start_sequence ();
1079 lra_emit_move (out_rtx, copy_rtx (new_out_reg));
1080 emit_insn (*after);
1081 *after = get_insns ();
1082 end_sequence ();
1083 }
1084 *curr_id->operand_loc[out] = new_out_reg;
1085 lra_update_dup (curr_id, out);
1086 }
1087
1088 /* Return register class which is union of all reg classes in insn
1089 constraint alternative string starting with P. */
1090 static enum reg_class
reg_class_from_constraints(const char * p)1091 reg_class_from_constraints (const char *p)
1092 {
1093 int c, len;
1094 enum reg_class op_class = NO_REGS;
1095
1096 do
1097 switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c)
1098 {
1099 case '#':
1100 case ',':
1101 return op_class;
1102
1103 case 'g':
1104 op_class = reg_class_subunion[op_class][GENERAL_REGS];
1105 break;
1106
1107 default:
1108 enum constraint_num cn = lookup_constraint (p);
1109 enum reg_class cl = reg_class_for_constraint (cn);
1110 if (cl == NO_REGS)
1111 {
1112 if (insn_extra_address_constraint (cn))
1113 op_class
1114 = (reg_class_subunion
1115 [op_class][base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
1116 ADDRESS, SCRATCH)]);
1117 break;
1118 }
1119
1120 op_class = reg_class_subunion[op_class][cl];
1121 break;
1122 }
1123 while ((p += len), c);
1124 return op_class;
1125 }
1126
1127 /* If OP is a register, return the class of the register as per
1128 get_reg_class, otherwise return NO_REGS. */
1129 static inline enum reg_class
get_op_class(rtx op)1130 get_op_class (rtx op)
1131 {
1132 return REG_P (op) ? get_reg_class (REGNO (op)) : NO_REGS;
1133 }
1134
1135 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
1136 otherwise. If modes of MEM_PSEUDO and VAL are different, use
1137 SUBREG for VAL to make them equal. */
1138 static rtx_insn *
emit_spill_move(bool to_p,rtx mem_pseudo,rtx val)1139 emit_spill_move (bool to_p, rtx mem_pseudo, rtx val)
1140 {
1141 if (GET_MODE (mem_pseudo) != GET_MODE (val))
1142 {
1143 /* Usually size of mem_pseudo is greater than val size but in
1144 rare cases it can be less as it can be defined by target
1145 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
1146 if (! MEM_P (val))
1147 {
1148 val = gen_lowpart_SUBREG (GET_MODE (mem_pseudo),
1149 GET_CODE (val) == SUBREG
1150 ? SUBREG_REG (val) : val);
1151 LRA_SUBREG_P (val) = 1;
1152 }
1153 else
1154 {
1155 mem_pseudo = gen_lowpart_SUBREG (GET_MODE (val), mem_pseudo);
1156 LRA_SUBREG_P (mem_pseudo) = 1;
1157 }
1158 }
1159 return to_p ? gen_move_insn (mem_pseudo, val)
1160 : gen_move_insn (val, mem_pseudo);
1161 }
1162
1163 /* Process a special case insn (register move), return true if we
1164 don't need to process it anymore. INSN should be a single set
1165 insn. Set up that RTL was changed through CHANGE_P and that hook
1166 TARGET_SECONDARY_MEMORY_NEEDED says to use secondary memory through
1167 SEC_MEM_P. */
1168 static bool
check_and_process_move(bool * change_p,bool * sec_mem_p ATTRIBUTE_UNUSED)1169 check_and_process_move (bool *change_p, bool *sec_mem_p ATTRIBUTE_UNUSED)
1170 {
1171 int sregno, dregno;
1172 rtx dest, src, dreg, sreg, new_reg, scratch_reg;
1173 rtx_insn *before;
1174 enum reg_class dclass, sclass, secondary_class;
1175 secondary_reload_info sri;
1176
1177 lra_assert (curr_insn_set != NULL_RTX);
1178 dreg = dest = SET_DEST (curr_insn_set);
1179 sreg = src = SET_SRC (curr_insn_set);
1180 if (GET_CODE (dest) == SUBREG)
1181 dreg = SUBREG_REG (dest);
1182 if (GET_CODE (src) == SUBREG)
1183 sreg = SUBREG_REG (src);
1184 if (! (REG_P (dreg) || MEM_P (dreg)) || ! (REG_P (sreg) || MEM_P (sreg)))
1185 return false;
1186 sclass = dclass = NO_REGS;
1187 if (REG_P (dreg))
1188 dclass = get_reg_class (REGNO (dreg));
1189 gcc_assert (dclass < LIM_REG_CLASSES);
1190 if (dclass == ALL_REGS)
1191 /* ALL_REGS is used for new pseudos created by transformations
1192 like reload of SUBREG_REG (see function
1193 simplify_operand_subreg). We don't know their class yet. We
1194 should figure out the class from processing the insn
1195 constraints not in this fast path function. Even if ALL_REGS
1196 were a right class for the pseudo, secondary_... hooks usually
1197 are not define for ALL_REGS. */
1198 return false;
1199 if (REG_P (sreg))
1200 sclass = get_reg_class (REGNO (sreg));
1201 gcc_assert (sclass < LIM_REG_CLASSES);
1202 if (sclass == ALL_REGS)
1203 /* See comments above. */
1204 return false;
1205 if (sclass == NO_REGS && dclass == NO_REGS)
1206 return false;
1207 if (targetm.secondary_memory_needed (GET_MODE (src), sclass, dclass)
1208 && ((sclass != NO_REGS && dclass != NO_REGS)
1209 || (GET_MODE (src)
1210 != targetm.secondary_memory_needed_mode (GET_MODE (src)))))
1211 {
1212 *sec_mem_p = true;
1213 return false;
1214 }
1215 if (! REG_P (dreg) || ! REG_P (sreg))
1216 return false;
1217 sri.prev_sri = NULL;
1218 sri.icode = CODE_FOR_nothing;
1219 sri.extra_cost = 0;
1220 secondary_class = NO_REGS;
1221 /* Set up hard register for a reload pseudo for hook
1222 secondary_reload because some targets just ignore unassigned
1223 pseudos in the hook. */
1224 if (dclass != NO_REGS && lra_get_regno_hard_regno (REGNO (dreg)) < 0)
1225 {
1226 dregno = REGNO (dreg);
1227 reg_renumber[dregno] = ira_class_hard_regs[dclass][0];
1228 }
1229 else
1230 dregno = -1;
1231 if (sclass != NO_REGS && lra_get_regno_hard_regno (REGNO (sreg)) < 0)
1232 {
1233 sregno = REGNO (sreg);
1234 reg_renumber[sregno] = ira_class_hard_regs[sclass][0];
1235 }
1236 else
1237 sregno = -1;
1238 if (sclass != NO_REGS)
1239 secondary_class
1240 = (enum reg_class) targetm.secondary_reload (false, dest,
1241 (reg_class_t) sclass,
1242 GET_MODE (src), &sri);
1243 if (sclass == NO_REGS
1244 || ((secondary_class != NO_REGS || sri.icode != CODE_FOR_nothing)
1245 && dclass != NO_REGS))
1246 {
1247 enum reg_class old_sclass = secondary_class;
1248 secondary_reload_info old_sri = sri;
1249
1250 sri.prev_sri = NULL;
1251 sri.icode = CODE_FOR_nothing;
1252 sri.extra_cost = 0;
1253 secondary_class
1254 = (enum reg_class) targetm.secondary_reload (true, src,
1255 (reg_class_t) dclass,
1256 GET_MODE (src), &sri);
1257 /* Check the target hook consistency. */
1258 lra_assert
1259 ((secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing)
1260 || (old_sclass == NO_REGS && old_sri.icode == CODE_FOR_nothing)
1261 || (secondary_class == old_sclass && sri.icode == old_sri.icode));
1262 }
1263 if (sregno >= 0)
1264 reg_renumber [sregno] = -1;
1265 if (dregno >= 0)
1266 reg_renumber [dregno] = -1;
1267 if (secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing)
1268 return false;
1269 *change_p = true;
1270 new_reg = NULL_RTX;
1271 if (secondary_class != NO_REGS)
1272 new_reg = lra_create_new_reg_with_unique_value (GET_MODE (src), NULL_RTX,
1273 secondary_class,
1274 "secondary");
1275 start_sequence ();
1276 if (sri.icode == CODE_FOR_nothing)
1277 lra_emit_move (new_reg, src);
1278 else
1279 {
1280 enum reg_class scratch_class;
1281
1282 scratch_class = (reg_class_from_constraints
1283 (insn_data[sri.icode].operand[2].constraint));
1284 scratch_reg = (lra_create_new_reg_with_unique_value
1285 (insn_data[sri.icode].operand[2].mode, NULL_RTX,
1286 scratch_class, "scratch"));
1287 emit_insn (GEN_FCN (sri.icode) (new_reg != NULL_RTX ? new_reg : dest,
1288 src, scratch_reg));
1289 }
1290 before = get_insns ();
1291 end_sequence ();
1292 lra_process_new_insns (curr_insn, before, NULL, "Inserting the move");
1293 if (new_reg != NULL_RTX)
1294 SET_SRC (curr_insn_set) = new_reg;
1295 else
1296 {
1297 if (lra_dump_file != NULL)
1298 {
1299 fprintf (lra_dump_file, "Deleting move %u\n", INSN_UID (curr_insn));
1300 dump_insn_slim (lra_dump_file, curr_insn);
1301 }
1302 lra_set_insn_deleted (curr_insn);
1303 return true;
1304 }
1305 return false;
1306 }
1307
1308 /* The following data describe the result of process_alt_operands.
1309 The data are used in curr_insn_transform to generate reloads. */
1310
1311 /* The chosen reg classes which should be used for the corresponding
1312 operands. */
1313 static enum reg_class goal_alt[MAX_RECOG_OPERANDS];
1314 /* True if the operand should be the same as another operand and that
1315 other operand does not need a reload. */
1316 static bool goal_alt_match_win[MAX_RECOG_OPERANDS];
1317 /* True if the operand does not need a reload. */
1318 static bool goal_alt_win[MAX_RECOG_OPERANDS];
1319 /* True if the operand can be offsetable memory. */
1320 static bool goal_alt_offmemok[MAX_RECOG_OPERANDS];
1321 /* The number of an operand to which given operand can be matched to. */
1322 static int goal_alt_matches[MAX_RECOG_OPERANDS];
1323 /* The number of elements in the following array. */
1324 static int goal_alt_dont_inherit_ops_num;
1325 /* Numbers of operands whose reload pseudos should not be inherited. */
1326 static int goal_alt_dont_inherit_ops[MAX_RECOG_OPERANDS];
1327 /* True if the insn commutative operands should be swapped. */
1328 static bool goal_alt_swapped;
1329 /* The chosen insn alternative. */
1330 static int goal_alt_number;
1331
1332 /* True if the corresponding operand is the result of an equivalence
1333 substitution. */
1334 static bool equiv_substition_p[MAX_RECOG_OPERANDS];
1335
1336 /* The following five variables are used to choose the best insn
1337 alternative. They reflect final characteristics of the best
1338 alternative. */
1339
1340 /* Number of necessary reloads and overall cost reflecting the
1341 previous value and other unpleasantness of the best alternative. */
1342 static int best_losers, best_overall;
1343 /* Overall number hard registers used for reloads. For example, on
1344 some targets we need 2 general registers to reload DFmode and only
1345 one floating point register. */
1346 static int best_reload_nregs;
1347 /* Overall number reflecting distances of previous reloading the same
1348 value. The distances are counted from the current BB start. It is
1349 used to improve inheritance chances. */
1350 static int best_reload_sum;
1351
1352 /* True if the current insn should have no correspondingly input or
1353 output reloads. */
1354 static bool no_input_reloads_p, no_output_reloads_p;
1355
1356 /* True if we swapped the commutative operands in the current
1357 insn. */
1358 static int curr_swapped;
1359
1360 /* if CHECK_ONLY_P is false, arrange for address element *LOC to be a
1361 register of class CL. Add any input reloads to list BEFORE. AFTER
1362 is nonnull if *LOC is an automodified value; handle that case by
1363 adding the required output reloads to list AFTER. Return true if
1364 the RTL was changed.
1365
1366 if CHECK_ONLY_P is true, check that the *LOC is a correct address
1367 register. Return false if the address register is correct. */
1368 static bool
process_addr_reg(rtx * loc,bool check_only_p,rtx_insn ** before,rtx_insn ** after,enum reg_class cl)1369 process_addr_reg (rtx *loc, bool check_only_p, rtx_insn **before, rtx_insn **after,
1370 enum reg_class cl)
1371 {
1372 int regno;
1373 enum reg_class rclass, new_class;
1374 rtx reg;
1375 rtx new_reg;
1376 machine_mode mode;
1377 bool subreg_p, before_p = false;
1378
1379 subreg_p = GET_CODE (*loc) == SUBREG;
1380 if (subreg_p)
1381 {
1382 reg = SUBREG_REG (*loc);
1383 mode = GET_MODE (reg);
1384
1385 /* For mode with size bigger than ptr_mode, there unlikely to be "mov"
1386 between two registers with different classes, but there normally will
1387 be "mov" which transfers element of vector register into the general
1388 register, and this normally will be a subreg which should be reloaded
1389 as a whole. This is particularly likely to be triggered when
1390 -fno-split-wide-types specified. */
1391 if (!REG_P (reg)
1392 || in_class_p (reg, cl, &new_class)
1393 || known_le (GET_MODE_SIZE (mode), GET_MODE_SIZE (ptr_mode)))
1394 loc = &SUBREG_REG (*loc);
1395 }
1396
1397 reg = *loc;
1398 mode = GET_MODE (reg);
1399 if (! REG_P (reg))
1400 {
1401 if (check_only_p)
1402 return true;
1403 /* Always reload memory in an address even if the target supports
1404 such addresses. */
1405 new_reg = lra_create_new_reg_with_unique_value (mode, reg, cl, "address");
1406 before_p = true;
1407 }
1408 else
1409 {
1410 regno = REGNO (reg);
1411 rclass = get_reg_class (regno);
1412 if (! check_only_p
1413 && (*loc = get_equiv_with_elimination (reg, curr_insn)) != reg)
1414 {
1415 if (lra_dump_file != NULL)
1416 {
1417 fprintf (lra_dump_file,
1418 "Changing pseudo %d in address of insn %u on equiv ",
1419 REGNO (reg), INSN_UID (curr_insn));
1420 dump_value_slim (lra_dump_file, *loc, 1);
1421 fprintf (lra_dump_file, "\n");
1422 }
1423 *loc = copy_rtx (*loc);
1424 }
1425 if (*loc != reg || ! in_class_p (reg, cl, &new_class))
1426 {
1427 if (check_only_p)
1428 return true;
1429 reg = *loc;
1430 if (get_reload_reg (after == NULL ? OP_IN : OP_INOUT,
1431 mode, reg, cl, subreg_p, "address", &new_reg))
1432 before_p = true;
1433 }
1434 else if (new_class != NO_REGS && rclass != new_class)
1435 {
1436 if (check_only_p)
1437 return true;
1438 lra_change_class (regno, new_class, " Change to", true);
1439 return false;
1440 }
1441 else
1442 return false;
1443 }
1444 if (before_p)
1445 {
1446 push_to_sequence (*before);
1447 lra_emit_move (new_reg, reg);
1448 *before = get_insns ();
1449 end_sequence ();
1450 }
1451 *loc = new_reg;
1452 if (after != NULL)
1453 {
1454 start_sequence ();
1455 lra_emit_move (before_p ? copy_rtx (reg) : reg, new_reg);
1456 emit_insn (*after);
1457 *after = get_insns ();
1458 end_sequence ();
1459 }
1460 return true;
1461 }
1462
1463 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1464 the insn to be inserted before curr insn. AFTER returns the
1465 the insn to be inserted after curr insn. ORIGREG and NEWREG
1466 are the original reg and new reg for reload. */
1467 static void
insert_move_for_subreg(rtx_insn ** before,rtx_insn ** after,rtx origreg,rtx newreg)1468 insert_move_for_subreg (rtx_insn **before, rtx_insn **after, rtx origreg,
1469 rtx newreg)
1470 {
1471 if (before)
1472 {
1473 push_to_sequence (*before);
1474 lra_emit_move (newreg, origreg);
1475 *before = get_insns ();
1476 end_sequence ();
1477 }
1478 if (after)
1479 {
1480 start_sequence ();
1481 lra_emit_move (origreg, newreg);
1482 emit_insn (*after);
1483 *after = get_insns ();
1484 end_sequence ();
1485 }
1486 }
1487
1488 static int valid_address_p (machine_mode mode, rtx addr, addr_space_t as);
1489 static bool process_address (int, bool, rtx_insn **, rtx_insn **);
1490
1491 /* Make reloads for subreg in operand NOP with internal subreg mode
1492 REG_MODE, add new reloads for further processing. Return true if
1493 any change was done. */
1494 static bool
simplify_operand_subreg(int nop,machine_mode reg_mode)1495 simplify_operand_subreg (int nop, machine_mode reg_mode)
1496 {
1497 int hard_regno;
1498 rtx_insn *before, *after;
1499 machine_mode mode, innermode;
1500 rtx reg, new_reg;
1501 rtx operand = *curr_id->operand_loc[nop];
1502 enum reg_class regclass;
1503 enum op_type type;
1504
1505 before = after = NULL;
1506
1507 if (GET_CODE (operand) != SUBREG)
1508 return false;
1509
1510 mode = GET_MODE (operand);
1511 reg = SUBREG_REG (operand);
1512 innermode = GET_MODE (reg);
1513 type = curr_static_id->operand[nop].type;
1514 if (MEM_P (reg))
1515 {
1516 const bool addr_was_valid
1517 = valid_address_p (innermode, XEXP (reg, 0), MEM_ADDR_SPACE (reg));
1518 alter_subreg (curr_id->operand_loc[nop], false);
1519 rtx subst = *curr_id->operand_loc[nop];
1520 lra_assert (MEM_P (subst));
1521
1522 if (!addr_was_valid
1523 || valid_address_p (GET_MODE (subst), XEXP (subst, 0),
1524 MEM_ADDR_SPACE (subst))
1525 || ((get_constraint_type (lookup_constraint
1526 (curr_static_id->operand[nop].constraint))
1527 != CT_SPECIAL_MEMORY)
1528 /* We still can reload address and if the address is
1529 valid, we can remove subreg without reloading its
1530 inner memory. */
1531 && valid_address_p (GET_MODE (subst),
1532 regno_reg_rtx
1533 [ira_class_hard_regs
1534 [base_reg_class (GET_MODE (subst),
1535 MEM_ADDR_SPACE (subst),
1536 ADDRESS, SCRATCH)][0]],
1537 MEM_ADDR_SPACE (subst))))
1538 {
1539 /* If we change the address for a paradoxical subreg of memory, the
1540 new address might violate the necessary alignment or the access
1541 might be slow; take this into consideration. We need not worry
1542 about accesses beyond allocated memory for paradoxical memory
1543 subregs as we don't substitute such equiv memory (see processing
1544 equivalences in function lra_constraints) and because for spilled
1545 pseudos we allocate stack memory enough for the biggest
1546 corresponding paradoxical subreg.
1547
1548 However, do not blindly simplify a (subreg (mem ...)) for
1549 WORD_REGISTER_OPERATIONS targets as this may lead to loading junk
1550 data into a register when the inner is narrower than outer or
1551 missing important data from memory when the inner is wider than
1552 outer. This rule only applies to modes that are no wider than
1553 a word. */
1554 if (!(maybe_ne (GET_MODE_PRECISION (mode),
1555 GET_MODE_PRECISION (innermode))
1556 && known_le (GET_MODE_SIZE (mode), UNITS_PER_WORD)
1557 && known_le (GET_MODE_SIZE (innermode), UNITS_PER_WORD)
1558 && WORD_REGISTER_OPERATIONS)
1559 && (!(MEM_ALIGN (subst) < GET_MODE_ALIGNMENT (mode)
1560 && targetm.slow_unaligned_access (mode, MEM_ALIGN (subst)))
1561 || (MEM_ALIGN (reg) < GET_MODE_ALIGNMENT (innermode)
1562 && targetm.slow_unaligned_access (innermode,
1563 MEM_ALIGN (reg)))))
1564 return true;
1565
1566 *curr_id->operand_loc[nop] = operand;
1567
1568 /* But if the address was not valid, we cannot reload the MEM without
1569 reloading the address first. */
1570 if (!addr_was_valid)
1571 process_address (nop, false, &before, &after);
1572
1573 /* INNERMODE is fast, MODE slow. Reload the mem in INNERMODE. */
1574 enum reg_class rclass
1575 = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);
1576 if (get_reload_reg (curr_static_id->operand[nop].type, innermode,
1577 reg, rclass, TRUE, "slow mem", &new_reg))
1578 {
1579 bool insert_before, insert_after;
1580 bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg));
1581
1582 insert_before = (type != OP_OUT
1583 || partial_subreg_p (mode, innermode));
1584 insert_after = type != OP_IN;
1585 insert_move_for_subreg (insert_before ? &before : NULL,
1586 insert_after ? &after : NULL,
1587 reg, new_reg);
1588 }
1589 SUBREG_REG (operand) = new_reg;
1590
1591 /* Convert to MODE. */
1592 reg = operand;
1593 rclass
1594 = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);
1595 if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg,
1596 rclass, TRUE, "slow mem", &new_reg))
1597 {
1598 bool insert_before, insert_after;
1599 bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg));
1600
1601 insert_before = type != OP_OUT;
1602 insert_after = type != OP_IN;
1603 insert_move_for_subreg (insert_before ? &before : NULL,
1604 insert_after ? &after : NULL,
1605 reg, new_reg);
1606 }
1607 *curr_id->operand_loc[nop] = new_reg;
1608 lra_process_new_insns (curr_insn, before, after,
1609 "Inserting slow mem reload");
1610 return true;
1611 }
1612
1613 /* If the address was valid and became invalid, prefer to reload
1614 the memory. Typical case is when the index scale should
1615 correspond the memory. */
1616 *curr_id->operand_loc[nop] = operand;
1617 /* Do not return false here as the MEM_P (reg) will be processed
1618 later in this function. */
1619 }
1620 else if (REG_P (reg) && REGNO (reg) < FIRST_PSEUDO_REGISTER)
1621 {
1622 alter_subreg (curr_id->operand_loc[nop], false);
1623 return true;
1624 }
1625 else if (CONSTANT_P (reg))
1626 {
1627 /* Try to simplify subreg of constant. It is usually result of
1628 equivalence substitution. */
1629 if (innermode == VOIDmode
1630 && (innermode = original_subreg_reg_mode[nop]) == VOIDmode)
1631 innermode = curr_static_id->operand[nop].mode;
1632 if ((new_reg = simplify_subreg (mode, reg, innermode,
1633 SUBREG_BYTE (operand))) != NULL_RTX)
1634 {
1635 *curr_id->operand_loc[nop] = new_reg;
1636 return true;
1637 }
1638 }
1639 /* Put constant into memory when we have mixed modes. It generates
1640 a better code in most cases as it does not need a secondary
1641 reload memory. It also prevents LRA looping when LRA is using
1642 secondary reload memory again and again. */
1643 if (CONSTANT_P (reg) && CONST_POOL_OK_P (reg_mode, reg)
1644 && SCALAR_INT_MODE_P (reg_mode) != SCALAR_INT_MODE_P (mode))
1645 {
1646 SUBREG_REG (operand) = force_const_mem (reg_mode, reg);
1647 alter_subreg (curr_id->operand_loc[nop], false);
1648 return true;
1649 }
1650 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1651 if there may be a problem accessing OPERAND in the outer
1652 mode. */
1653 if ((REG_P (reg)
1654 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
1655 && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0
1656 /* Don't reload paradoxical subregs because we could be looping
1657 having repeatedly final regno out of hard regs range. */
1658 && (hard_regno_nregs (hard_regno, innermode)
1659 >= hard_regno_nregs (hard_regno, mode))
1660 && simplify_subreg_regno (hard_regno, innermode,
1661 SUBREG_BYTE (operand), mode) < 0
1662 /* Don't reload subreg for matching reload. It is actually
1663 valid subreg in LRA. */
1664 && ! LRA_SUBREG_P (operand))
1665 || CONSTANT_P (reg) || GET_CODE (reg) == PLUS || MEM_P (reg))
1666 {
1667 enum reg_class rclass;
1668
1669 if (REG_P (reg))
1670 /* There is a big probability that we will get the same class
1671 for the new pseudo and we will get the same insn which
1672 means infinite looping. So spill the new pseudo. */
1673 rclass = NO_REGS;
1674 else
1675 /* The class will be defined later in curr_insn_transform. */
1676 rclass
1677 = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);
1678
1679 if (get_reload_reg (curr_static_id->operand[nop].type, reg_mode, reg,
1680 rclass, TRUE, "subreg reg", &new_reg))
1681 {
1682 bool insert_before, insert_after;
1683 bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg));
1684
1685 insert_before = (type != OP_OUT
1686 || read_modify_subreg_p (operand));
1687 insert_after = (type != OP_IN);
1688 insert_move_for_subreg (insert_before ? &before : NULL,
1689 insert_after ? &after : NULL,
1690 reg, new_reg);
1691 }
1692 SUBREG_REG (operand) = new_reg;
1693 lra_process_new_insns (curr_insn, before, after,
1694 "Inserting subreg reload");
1695 return true;
1696 }
1697 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1698 IRA allocates hardreg to the inner pseudo reg according to its mode
1699 instead of the outermode, so the size of the hardreg may not be enough
1700 to contain the outermode operand, in that case we may need to insert
1701 reload for the reg. For the following two types of paradoxical subreg,
1702 we need to insert reload:
1703 1. If the op_type is OP_IN, and the hardreg could not be paired with
1704 other hardreg to contain the outermode operand
1705 (checked by in_hard_reg_set_p), we need to insert the reload.
1706 2. If the op_type is OP_OUT or OP_INOUT.
1707
1708 Here is a paradoxical subreg example showing how the reload is generated:
1709
1710 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1711 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1712
1713 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1714 here, if reg107 is assigned to hardreg R15, because R15 is the last
1715 hardreg, compiler cannot find another hardreg to pair with R15 to
1716 contain TImode data. So we insert a TImode reload reg180 for it.
1717 After reload is inserted:
1718
1719 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1720 (reg:DI 107 [ __comp ])) -1
1721 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1722 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1723
1724 Two reload hard registers will be allocated to reg180 to save TImode data
1725 in LRA_assign. */
1726 else if (REG_P (reg)
1727 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
1728 && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0
1729 && (hard_regno_nregs (hard_regno, innermode)
1730 < hard_regno_nregs (hard_regno, mode))
1731 && (regclass = lra_get_allocno_class (REGNO (reg)))
1732 && (type != OP_IN
1733 || !in_hard_reg_set_p (reg_class_contents[regclass],
1734 mode, hard_regno)))
1735 {
1736 /* The class will be defined later in curr_insn_transform. */
1737 enum reg_class rclass
1738 = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);
1739
1740 if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg,
1741 rclass, TRUE, "paradoxical subreg", &new_reg))
1742 {
1743 rtx subreg;
1744 bool insert_before, insert_after;
1745
1746 PUT_MODE (new_reg, mode);
1747 subreg = gen_lowpart_SUBREG (innermode, new_reg);
1748 bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg));
1749
1750 insert_before = (type != OP_OUT);
1751 insert_after = (type != OP_IN);
1752 insert_move_for_subreg (insert_before ? &before : NULL,
1753 insert_after ? &after : NULL,
1754 reg, subreg);
1755 }
1756 SUBREG_REG (operand) = new_reg;
1757 lra_process_new_insns (curr_insn, before, after,
1758 "Inserting paradoxical subreg reload");
1759 return true;
1760 }
1761 return false;
1762 }
1763
1764 /* Return TRUE if X refers for a hard register from SET. */
1765 static bool
uses_hard_regs_p(rtx x,HARD_REG_SET set)1766 uses_hard_regs_p (rtx x, HARD_REG_SET set)
1767 {
1768 int i, j, x_hard_regno;
1769 machine_mode mode;
1770 const char *fmt;
1771 enum rtx_code code;
1772
1773 if (x == NULL_RTX)
1774 return false;
1775 code = GET_CODE (x);
1776 mode = GET_MODE (x);
1777
1778 if (code == SUBREG)
1779 {
1780 /* For all SUBREGs we want to check whether the full multi-register
1781 overlaps the set. For normal SUBREGs this means 'get_hard_regno' of
1782 the inner register, for paradoxical SUBREGs this means the
1783 'get_hard_regno' of the full SUBREG and for complete SUBREGs either is
1784 fine. Use the wider mode for all cases. */
1785 rtx subreg = SUBREG_REG (x);
1786 mode = wider_subreg_mode (x);
1787 if (mode == GET_MODE (subreg))
1788 {
1789 x = subreg;
1790 code = GET_CODE (x);
1791 }
1792 }
1793
1794 if (REG_P (x) || SUBREG_P (x))
1795 {
1796 x_hard_regno = get_hard_regno (x, true);
1797 return (x_hard_regno >= 0
1798 && overlaps_hard_reg_set_p (set, mode, x_hard_regno));
1799 }
1800 if (MEM_P (x))
1801 {
1802 struct address_info ad;
1803
1804 decompose_mem_address (&ad, x);
1805 if (ad.base_term != NULL && uses_hard_regs_p (*ad.base_term, set))
1806 return true;
1807 if (ad.index_term != NULL && uses_hard_regs_p (*ad.index_term, set))
1808 return true;
1809 }
1810 fmt = GET_RTX_FORMAT (code);
1811 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1812 {
1813 if (fmt[i] == 'e')
1814 {
1815 if (uses_hard_regs_p (XEXP (x, i), set))
1816 return true;
1817 }
1818 else if (fmt[i] == 'E')
1819 {
1820 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1821 if (uses_hard_regs_p (XVECEXP (x, i, j), set))
1822 return true;
1823 }
1824 }
1825 return false;
1826 }
1827
1828 /* Return true if OP is a spilled pseudo. */
1829 static inline bool
spilled_pseudo_p(rtx op)1830 spilled_pseudo_p (rtx op)
1831 {
1832 return (REG_P (op)
1833 && REGNO (op) >= FIRST_PSEUDO_REGISTER && in_mem_p (REGNO (op)));
1834 }
1835
1836 /* Return true if X is a general constant. */
1837 static inline bool
general_constant_p(rtx x)1838 general_constant_p (rtx x)
1839 {
1840 return CONSTANT_P (x) && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (x));
1841 }
1842
1843 static bool
reg_in_class_p(rtx reg,enum reg_class cl)1844 reg_in_class_p (rtx reg, enum reg_class cl)
1845 {
1846 if (cl == NO_REGS)
1847 return get_reg_class (REGNO (reg)) == NO_REGS;
1848 return in_class_p (reg, cl, NULL);
1849 }
1850
1851 /* Return true if SET of RCLASS contains no hard regs which can be
1852 used in MODE. */
1853 static bool
prohibited_class_reg_set_mode_p(enum reg_class rclass,HARD_REG_SET & set,machine_mode mode)1854 prohibited_class_reg_set_mode_p (enum reg_class rclass,
1855 HARD_REG_SET &set,
1856 machine_mode mode)
1857 {
1858 HARD_REG_SET temp;
1859
1860 lra_assert (hard_reg_set_subset_p (reg_class_contents[rclass], set));
1861 COPY_HARD_REG_SET (temp, set);
1862 AND_COMPL_HARD_REG_SET (temp, lra_no_alloc_regs);
1863 return (hard_reg_set_subset_p
1864 (temp, ira_prohibited_class_mode_regs[rclass][mode]));
1865 }
1866
1867
1868 /* Used to check validity info about small class input operands. It
1869 should be incremented at start of processing an insn
1870 alternative. */
1871 static unsigned int curr_small_class_check = 0;
1872
1873 /* Update number of used inputs of class OP_CLASS for operand NOP.
1874 Return true if we have more such class operands than the number of
1875 available regs. */
1876 static bool
update_and_check_small_class_inputs(int nop,enum reg_class op_class)1877 update_and_check_small_class_inputs (int nop, enum reg_class op_class)
1878 {
1879 static unsigned int small_class_check[LIM_REG_CLASSES];
1880 static int small_class_input_nums[LIM_REG_CLASSES];
1881
1882 if (SMALL_REGISTER_CLASS_P (op_class)
1883 /* We are interesting in classes became small because of fixing
1884 some hard regs, e.g. by an user through GCC options. */
1885 && hard_reg_set_intersect_p (reg_class_contents[op_class],
1886 ira_no_alloc_regs)
1887 && (curr_static_id->operand[nop].type != OP_OUT
1888 || curr_static_id->operand[nop].early_clobber))
1889 {
1890 if (small_class_check[op_class] == curr_small_class_check)
1891 small_class_input_nums[op_class]++;
1892 else
1893 {
1894 small_class_check[op_class] = curr_small_class_check;
1895 small_class_input_nums[op_class] = 1;
1896 }
1897 if (small_class_input_nums[op_class] > ira_class_hard_regs_num[op_class])
1898 return true;
1899 }
1900 return false;
1901 }
1902
1903 /* Major function to choose the current insn alternative and what
1904 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1905 negative we should consider only this alternative. Return false if
1906 we can not choose the alternative or find how to reload the
1907 operands. */
1908 static bool
process_alt_operands(int only_alternative)1909 process_alt_operands (int only_alternative)
1910 {
1911 bool ok_p = false;
1912 int nop, overall, nalt;
1913 int n_alternatives = curr_static_id->n_alternatives;
1914 int n_operands = curr_static_id->n_operands;
1915 /* LOSERS counts the operands that don't fit this alternative and
1916 would require loading. */
1917 int losers;
1918 int addr_losers;
1919 /* REJECT is a count of how undesirable this alternative says it is
1920 if any reloading is required. If the alternative matches exactly
1921 then REJECT is ignored, but otherwise it gets this much counted
1922 against it in addition to the reloading needed. */
1923 int reject;
1924 /* This is defined by '!' or '?' alternative constraint and added to
1925 reject. But in some cases it can be ignored. */
1926 int static_reject;
1927 int op_reject;
1928 /* The number of elements in the following array. */
1929 int early_clobbered_regs_num;
1930 /* Numbers of operands which are early clobber registers. */
1931 int early_clobbered_nops[MAX_RECOG_OPERANDS];
1932 enum reg_class curr_alt[MAX_RECOG_OPERANDS];
1933 HARD_REG_SET curr_alt_set[MAX_RECOG_OPERANDS];
1934 bool curr_alt_match_win[MAX_RECOG_OPERANDS];
1935 bool curr_alt_win[MAX_RECOG_OPERANDS];
1936 bool curr_alt_offmemok[MAX_RECOG_OPERANDS];
1937 int curr_alt_matches[MAX_RECOG_OPERANDS];
1938 /* The number of elements in the following array. */
1939 int curr_alt_dont_inherit_ops_num;
1940 /* Numbers of operands whose reload pseudos should not be inherited. */
1941 int curr_alt_dont_inherit_ops[MAX_RECOG_OPERANDS];
1942 rtx op;
1943 /* The register when the operand is a subreg of register, otherwise the
1944 operand itself. */
1945 rtx no_subreg_reg_operand[MAX_RECOG_OPERANDS];
1946 /* The register if the operand is a register or subreg of register,
1947 otherwise NULL. */
1948 rtx operand_reg[MAX_RECOG_OPERANDS];
1949 int hard_regno[MAX_RECOG_OPERANDS];
1950 machine_mode biggest_mode[MAX_RECOG_OPERANDS];
1951 int reload_nregs, reload_sum;
1952 bool costly_p;
1953 enum reg_class cl;
1954
1955 /* Calculate some data common for all alternatives to speed up the
1956 function. */
1957 for (nop = 0; nop < n_operands; nop++)
1958 {
1959 rtx reg;
1960
1961 op = no_subreg_reg_operand[nop] = *curr_id->operand_loc[nop];
1962 /* The real hard regno of the operand after the allocation. */
1963 hard_regno[nop] = get_hard_regno (op, true);
1964
1965 operand_reg[nop] = reg = op;
1966 biggest_mode[nop] = GET_MODE (op);
1967 if (GET_CODE (op) == SUBREG)
1968 {
1969 biggest_mode[nop] = wider_subreg_mode (op);
1970 operand_reg[nop] = reg = SUBREG_REG (op);
1971 }
1972 if (! REG_P (reg))
1973 operand_reg[nop] = NULL_RTX;
1974 else if (REGNO (reg) >= FIRST_PSEUDO_REGISTER
1975 || ((int) REGNO (reg)
1976 == lra_get_elimination_hard_regno (REGNO (reg))))
1977 no_subreg_reg_operand[nop] = reg;
1978 else
1979 operand_reg[nop] = no_subreg_reg_operand[nop]
1980 /* Just use natural mode for elimination result. It should
1981 be enough for extra constraints hooks. */
1982 = regno_reg_rtx[hard_regno[nop]];
1983 }
1984
1985 /* The constraints are made of several alternatives. Each operand's
1986 constraint looks like foo,bar,... with commas separating the
1987 alternatives. The first alternatives for all operands go
1988 together, the second alternatives go together, etc.
1989
1990 First loop over alternatives. */
1991 alternative_mask preferred = curr_id->preferred_alternatives;
1992 if (only_alternative >= 0)
1993 preferred &= ALTERNATIVE_BIT (only_alternative);
1994
1995 for (nalt = 0; nalt < n_alternatives; nalt++)
1996 {
1997 /* Loop over operands for one constraint alternative. */
1998 if (!TEST_BIT (preferred, nalt))
1999 continue;
2000
2001 curr_small_class_check++;
2002 overall = losers = addr_losers = 0;
2003 static_reject = reject = reload_nregs = reload_sum = 0;
2004 for (nop = 0; nop < n_operands; nop++)
2005 {
2006 int inc = (curr_static_id
2007 ->operand_alternative[nalt * n_operands + nop].reject);
2008 if (lra_dump_file != NULL && inc != 0)
2009 fprintf (lra_dump_file,
2010 " Staticly defined alt reject+=%d\n", inc);
2011 static_reject += inc;
2012 }
2013 reject += static_reject;
2014 early_clobbered_regs_num = 0;
2015
2016 for (nop = 0; nop < n_operands; nop++)
2017 {
2018 const char *p;
2019 char *end;
2020 int len, c, m, i, opalt_num, this_alternative_matches;
2021 bool win, did_match, offmemok, early_clobber_p;
2022 /* false => this operand can be reloaded somehow for this
2023 alternative. */
2024 bool badop;
2025 /* true => this operand can be reloaded if the alternative
2026 allows regs. */
2027 bool winreg;
2028 /* True if a constant forced into memory would be OK for
2029 this operand. */
2030 bool constmemok;
2031 enum reg_class this_alternative, this_costly_alternative;
2032 HARD_REG_SET this_alternative_set, this_costly_alternative_set;
2033 bool this_alternative_match_win, this_alternative_win;
2034 bool this_alternative_offmemok;
2035 bool scratch_p;
2036 machine_mode mode;
2037 enum constraint_num cn;
2038
2039 opalt_num = nalt * n_operands + nop;
2040 if (curr_static_id->operand_alternative[opalt_num].anything_ok)
2041 {
2042 /* Fast track for no constraints at all. */
2043 curr_alt[nop] = NO_REGS;
2044 CLEAR_HARD_REG_SET (curr_alt_set[nop]);
2045 curr_alt_win[nop] = true;
2046 curr_alt_match_win[nop] = false;
2047 curr_alt_offmemok[nop] = false;
2048 curr_alt_matches[nop] = -1;
2049 continue;
2050 }
2051
2052 op = no_subreg_reg_operand[nop];
2053 mode = curr_operand_mode[nop];
2054
2055 win = did_match = winreg = offmemok = constmemok = false;
2056 badop = true;
2057
2058 early_clobber_p = false;
2059 p = curr_static_id->operand_alternative[opalt_num].constraint;
2060
2061 this_costly_alternative = this_alternative = NO_REGS;
2062 /* We update set of possible hard regs besides its class
2063 because reg class might be inaccurate. For example,
2064 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
2065 is translated in HI_REGS because classes are merged by
2066 pairs and there is no accurate intermediate class. */
2067 CLEAR_HARD_REG_SET (this_alternative_set);
2068 CLEAR_HARD_REG_SET (this_costly_alternative_set);
2069 this_alternative_win = false;
2070 this_alternative_match_win = false;
2071 this_alternative_offmemok = false;
2072 this_alternative_matches = -1;
2073
2074 /* An empty constraint should be excluded by the fast
2075 track. */
2076 lra_assert (*p != 0 && *p != ',');
2077
2078 op_reject = 0;
2079 /* Scan this alternative's specs for this operand; set WIN
2080 if the operand fits any letter in this alternative.
2081 Otherwise, clear BADOP if this operand could fit some
2082 letter after reloads, or set WINREG if this operand could
2083 fit after reloads provided the constraint allows some
2084 registers. */
2085 costly_p = false;
2086 do
2087 {
2088 switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c)
2089 {
2090 case '\0':
2091 len = 0;
2092 break;
2093 case ',':
2094 c = '\0';
2095 break;
2096
2097 case '&':
2098 early_clobber_p = true;
2099 break;
2100
2101 case '$':
2102 op_reject += LRA_MAX_REJECT;
2103 break;
2104 case '^':
2105 op_reject += LRA_LOSER_COST_FACTOR;
2106 break;
2107
2108 case '#':
2109 /* Ignore rest of this alternative. */
2110 c = '\0';
2111 break;
2112
2113 case '0': case '1': case '2': case '3': case '4':
2114 case '5': case '6': case '7': case '8': case '9':
2115 {
2116 int m_hregno;
2117 bool match_p;
2118
2119 m = strtoul (p, &end, 10);
2120 p = end;
2121 len = 0;
2122 lra_assert (nop > m);
2123
2124 /* Reject matches if we don't know which operand is
2125 bigger. This situation would arguably be a bug in
2126 an .md pattern, but could also occur in a user asm. */
2127 if (!ordered_p (GET_MODE_SIZE (biggest_mode[m]),
2128 GET_MODE_SIZE (biggest_mode[nop])))
2129 break;
2130
2131 /* Don't match wrong asm insn operands for proper
2132 diagnostic later. */
2133 if (INSN_CODE (curr_insn) < 0
2134 && (curr_operand_mode[m] == BLKmode
2135 || curr_operand_mode[nop] == BLKmode)
2136 && curr_operand_mode[m] != curr_operand_mode[nop])
2137 break;
2138
2139 m_hregno = get_hard_regno (*curr_id->operand_loc[m], false);
2140 /* We are supposed to match a previous operand.
2141 If we do, we win if that one did. If we do
2142 not, count both of the operands as losers.
2143 (This is too conservative, since most of the
2144 time only a single reload insn will be needed
2145 to make the two operands win. As a result,
2146 this alternative may be rejected when it is
2147 actually desirable.) */
2148 match_p = false;
2149 if (operands_match_p (*curr_id->operand_loc[nop],
2150 *curr_id->operand_loc[m], m_hregno))
2151 {
2152 /* We should reject matching of an early
2153 clobber operand if the matching operand is
2154 not dying in the insn. */
2155 if (! curr_static_id->operand[m].early_clobber
2156 || operand_reg[nop] == NULL_RTX
2157 || (find_regno_note (curr_insn, REG_DEAD,
2158 REGNO (op))
2159 || REGNO (op) == REGNO (operand_reg[m])))
2160 match_p = true;
2161 }
2162 if (match_p)
2163 {
2164 /* If we are matching a non-offsettable
2165 address where an offsettable address was
2166 expected, then we must reject this
2167 combination, because we can't reload
2168 it. */
2169 if (curr_alt_offmemok[m]
2170 && MEM_P (*curr_id->operand_loc[m])
2171 && curr_alt[m] == NO_REGS && ! curr_alt_win[m])
2172 continue;
2173 }
2174 else
2175 {
2176 /* Operands don't match. Both operands must
2177 allow a reload register, otherwise we
2178 cannot make them match. */
2179 if (curr_alt[m] == NO_REGS)
2180 break;
2181 /* Retroactively mark the operand we had to
2182 match as a loser, if it wasn't already and
2183 it wasn't matched to a register constraint
2184 (e.g it might be matched by memory). */
2185 if (curr_alt_win[m]
2186 && (operand_reg[m] == NULL_RTX
2187 || hard_regno[m] < 0))
2188 {
2189 losers++;
2190 reload_nregs
2191 += (ira_reg_class_max_nregs[curr_alt[m]]
2192 [GET_MODE (*curr_id->operand_loc[m])]);
2193 }
2194
2195 /* Prefer matching earlyclobber alternative as
2196 it results in less hard regs required for
2197 the insn than a non-matching earlyclobber
2198 alternative. */
2199 if (curr_static_id->operand[m].early_clobber)
2200 {
2201 if (lra_dump_file != NULL)
2202 fprintf
2203 (lra_dump_file,
2204 " %d Matching earlyclobber alt:"
2205 " reject--\n",
2206 nop);
2207 reject--;
2208 }
2209 /* Otherwise we prefer no matching
2210 alternatives because it gives more freedom
2211 in RA. */
2212 else if (operand_reg[nop] == NULL_RTX
2213 || (find_regno_note (curr_insn, REG_DEAD,
2214 REGNO (operand_reg[nop]))
2215 == NULL_RTX))
2216 {
2217 if (lra_dump_file != NULL)
2218 fprintf
2219 (lra_dump_file,
2220 " %d Matching alt: reject+=2\n",
2221 nop);
2222 reject += 2;
2223 }
2224 }
2225 /* If we have to reload this operand and some
2226 previous operand also had to match the same
2227 thing as this operand, we don't know how to do
2228 that. */
2229 if (!match_p || !curr_alt_win[m])
2230 {
2231 for (i = 0; i < nop; i++)
2232 if (curr_alt_matches[i] == m)
2233 break;
2234 if (i < nop)
2235 break;
2236 }
2237 else
2238 did_match = true;
2239
2240 this_alternative_matches = m;
2241 /* This can be fixed with reloads if the operand
2242 we are supposed to match can be fixed with
2243 reloads. */
2244 badop = false;
2245 this_alternative = curr_alt[m];
2246 COPY_HARD_REG_SET (this_alternative_set, curr_alt_set[m]);
2247 winreg = this_alternative != NO_REGS;
2248 break;
2249 }
2250
2251 case 'g':
2252 if (MEM_P (op)
2253 || general_constant_p (op)
2254 || spilled_pseudo_p (op))
2255 win = true;
2256 cl = GENERAL_REGS;
2257 goto reg;
2258
2259 default:
2260 cn = lookup_constraint (p);
2261 switch (get_constraint_type (cn))
2262 {
2263 case CT_REGISTER:
2264 cl = reg_class_for_constraint (cn);
2265 if (cl != NO_REGS)
2266 goto reg;
2267 break;
2268
2269 case CT_CONST_INT:
2270 if (CONST_INT_P (op)
2271 && insn_const_int_ok_for_constraint (INTVAL (op), cn))
2272 win = true;
2273 break;
2274
2275 case CT_MEMORY:
2276 if (MEM_P (op)
2277 && satisfies_memory_constraint_p (op, cn))
2278 win = true;
2279 else if (spilled_pseudo_p (op))
2280 win = true;
2281
2282 /* If we didn't already win, we can reload constants
2283 via force_const_mem or put the pseudo value into
2284 memory, or make other memory by reloading the
2285 address like for 'o'. */
2286 if (CONST_POOL_OK_P (mode, op)
2287 || MEM_P (op) || REG_P (op)
2288 /* We can restore the equiv insn by a
2289 reload. */
2290 || equiv_substition_p[nop])
2291 badop = false;
2292 constmemok = true;
2293 offmemok = true;
2294 break;
2295
2296 case CT_ADDRESS:
2297 /* An asm operand with an address constraint
2298 that doesn't satisfy address_operand has
2299 is_address cleared, so that we don't try to
2300 make a non-address fit. */
2301 if (!curr_static_id->operand[nop].is_address)
2302 break;
2303 /* If we didn't already win, we can reload the address
2304 into a base register. */
2305 if (satisfies_address_constraint_p (op, cn))
2306 win = true;
2307 cl = base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
2308 ADDRESS, SCRATCH);
2309 badop = false;
2310 goto reg;
2311
2312 case CT_FIXED_FORM:
2313 if (constraint_satisfied_p (op, cn))
2314 win = true;
2315 break;
2316
2317 case CT_SPECIAL_MEMORY:
2318 if (MEM_P (op)
2319 && satisfies_memory_constraint_p (op, cn))
2320 win = true;
2321 else if (spilled_pseudo_p (op))
2322 win = true;
2323 break;
2324 }
2325 break;
2326
2327 reg:
2328 if (mode == BLKmode)
2329 break;
2330 this_alternative = reg_class_subunion[this_alternative][cl];
2331 IOR_HARD_REG_SET (this_alternative_set,
2332 reg_class_contents[cl]);
2333 if (costly_p)
2334 {
2335 this_costly_alternative
2336 = reg_class_subunion[this_costly_alternative][cl];
2337 IOR_HARD_REG_SET (this_costly_alternative_set,
2338 reg_class_contents[cl]);
2339 }
2340 winreg = true;
2341 if (REG_P (op))
2342 {
2343 if (hard_regno[nop] >= 0
2344 && in_hard_reg_set_p (this_alternative_set,
2345 mode, hard_regno[nop]))
2346 win = true;
2347 else if (hard_regno[nop] < 0
2348 && in_class_p (op, this_alternative, NULL))
2349 win = true;
2350 }
2351 break;
2352 }
2353 if (c != ' ' && c != '\t')
2354 costly_p = c == '*';
2355 }
2356 while ((p += len), c);
2357
2358 scratch_p = (operand_reg[nop] != NULL_RTX
2359 && lra_former_scratch_p (REGNO (operand_reg[nop])));
2360 /* Record which operands fit this alternative. */
2361 if (win)
2362 {
2363 this_alternative_win = true;
2364 if (operand_reg[nop] != NULL_RTX)
2365 {
2366 if (hard_regno[nop] >= 0)
2367 {
2368 if (in_hard_reg_set_p (this_costly_alternative_set,
2369 mode, hard_regno[nop]))
2370 {
2371 if (lra_dump_file != NULL)
2372 fprintf (lra_dump_file,
2373 " %d Costly set: reject++\n",
2374 nop);
2375 reject++;
2376 }
2377 }
2378 else
2379 {
2380 /* Prefer won reg to spilled pseudo under other
2381 equal conditions for possibe inheritance. */
2382 if (! scratch_p)
2383 {
2384 if (lra_dump_file != NULL)
2385 fprintf
2386 (lra_dump_file,
2387 " %d Non pseudo reload: reject++\n",
2388 nop);
2389 reject++;
2390 }
2391 if (in_class_p (operand_reg[nop],
2392 this_costly_alternative, NULL))
2393 {
2394 if (lra_dump_file != NULL)
2395 fprintf
2396 (lra_dump_file,
2397 " %d Non pseudo costly reload:"
2398 " reject++\n",
2399 nop);
2400 reject++;
2401 }
2402 }
2403 /* We simulate the behavior of old reload here.
2404 Although scratches need hard registers and it
2405 might result in spilling other pseudos, no reload
2406 insns are generated for the scratches. So it
2407 might cost something but probably less than old
2408 reload pass believes. */
2409 if (scratch_p)
2410 {
2411 if (lra_dump_file != NULL)
2412 fprintf (lra_dump_file,
2413 " %d Scratch win: reject+=2\n",
2414 nop);
2415 reject += 2;
2416 }
2417 }
2418 }
2419 else if (did_match)
2420 this_alternative_match_win = true;
2421 else
2422 {
2423 int const_to_mem = 0;
2424 bool no_regs_p;
2425
2426 reject += op_reject;
2427 /* Never do output reload of stack pointer. It makes
2428 impossible to do elimination when SP is changed in
2429 RTL. */
2430 if (op == stack_pointer_rtx && ! frame_pointer_needed
2431 && curr_static_id->operand[nop].type != OP_IN)
2432 goto fail;
2433
2434 /* If this alternative asks for a specific reg class, see if there
2435 is at least one allocatable register in that class. */
2436 no_regs_p
2437 = (this_alternative == NO_REGS
2438 || (hard_reg_set_subset_p
2439 (reg_class_contents[this_alternative],
2440 lra_no_alloc_regs)));
2441
2442 /* For asms, verify that the class for this alternative is possible
2443 for the mode that is specified. */
2444 if (!no_regs_p && INSN_CODE (curr_insn) < 0)
2445 {
2446 int i;
2447 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2448 if (targetm.hard_regno_mode_ok (i, mode)
2449 && in_hard_reg_set_p (reg_class_contents[this_alternative],
2450 mode, i))
2451 break;
2452 if (i == FIRST_PSEUDO_REGISTER)
2453 winreg = false;
2454 }
2455
2456 /* If this operand accepts a register, and if the
2457 register class has at least one allocatable register,
2458 then this operand can be reloaded. */
2459 if (winreg && !no_regs_p)
2460 badop = false;
2461
2462 if (badop)
2463 {
2464 if (lra_dump_file != NULL)
2465 fprintf (lra_dump_file,
2466 " alt=%d: Bad operand -- refuse\n",
2467 nalt);
2468 goto fail;
2469 }
2470
2471 if (this_alternative != NO_REGS)
2472 {
2473 HARD_REG_SET available_regs;
2474
2475 COPY_HARD_REG_SET (available_regs,
2476 reg_class_contents[this_alternative]);
2477 AND_COMPL_HARD_REG_SET
2478 (available_regs,
2479 ira_prohibited_class_mode_regs[this_alternative][mode]);
2480 AND_COMPL_HARD_REG_SET (available_regs, lra_no_alloc_regs);
2481 if (hard_reg_set_empty_p (available_regs))
2482 {
2483 /* There are no hard regs holding a value of given
2484 mode. */
2485 if (offmemok)
2486 {
2487 this_alternative = NO_REGS;
2488 if (lra_dump_file != NULL)
2489 fprintf (lra_dump_file,
2490 " %d Using memory because of"
2491 " a bad mode: reject+=2\n",
2492 nop);
2493 reject += 2;
2494 }
2495 else
2496 {
2497 if (lra_dump_file != NULL)
2498 fprintf (lra_dump_file,
2499 " alt=%d: Wrong mode -- refuse\n",
2500 nalt);
2501 goto fail;
2502 }
2503 }
2504 }
2505
2506 /* If not assigned pseudo has a class which a subset of
2507 required reg class, it is a less costly alternative
2508 as the pseudo still can get a hard reg of necessary
2509 class. */
2510 if (! no_regs_p && REG_P (op) && hard_regno[nop] < 0
2511 && (cl = get_reg_class (REGNO (op))) != NO_REGS
2512 && ira_class_subset_p[this_alternative][cl])
2513 {
2514 if (lra_dump_file != NULL)
2515 fprintf
2516 (lra_dump_file,
2517 " %d Super set class reg: reject-=3\n", nop);
2518 reject -= 3;
2519 }
2520
2521 this_alternative_offmemok = offmemok;
2522 if (this_costly_alternative != NO_REGS)
2523 {
2524 if (lra_dump_file != NULL)
2525 fprintf (lra_dump_file,
2526 " %d Costly loser: reject++\n", nop);
2527 reject++;
2528 }
2529 /* If the operand is dying, has a matching constraint,
2530 and satisfies constraints of the matched operand
2531 which failed to satisfy the own constraints, most probably
2532 the reload for this operand will be gone. */
2533 if (this_alternative_matches >= 0
2534 && !curr_alt_win[this_alternative_matches]
2535 && REG_P (op)
2536 && find_regno_note (curr_insn, REG_DEAD, REGNO (op))
2537 && (hard_regno[nop] >= 0
2538 ? in_hard_reg_set_p (this_alternative_set,
2539 mode, hard_regno[nop])
2540 : in_class_p (op, this_alternative, NULL)))
2541 {
2542 if (lra_dump_file != NULL)
2543 fprintf
2544 (lra_dump_file,
2545 " %d Dying matched operand reload: reject++\n",
2546 nop);
2547 reject++;
2548 }
2549 else
2550 {
2551 /* Strict_low_part requires to reload the register
2552 not the sub-register. In this case we should
2553 check that a final reload hard reg can hold the
2554 value mode. */
2555 if (curr_static_id->operand[nop].strict_low
2556 && REG_P (op)
2557 && hard_regno[nop] < 0
2558 && GET_CODE (*curr_id->operand_loc[nop]) == SUBREG
2559 && ira_class_hard_regs_num[this_alternative] > 0
2560 && (!targetm.hard_regno_mode_ok
2561 (ira_class_hard_regs[this_alternative][0],
2562 GET_MODE (*curr_id->operand_loc[nop]))))
2563 {
2564 if (lra_dump_file != NULL)
2565 fprintf
2566 (lra_dump_file,
2567 " alt=%d: Strict low subreg reload -- refuse\n",
2568 nalt);
2569 goto fail;
2570 }
2571 losers++;
2572 }
2573 if (operand_reg[nop] != NULL_RTX
2574 /* Output operands and matched input operands are
2575 not inherited. The following conditions do not
2576 exactly describe the previous statement but they
2577 are pretty close. */
2578 && curr_static_id->operand[nop].type != OP_OUT
2579 && (this_alternative_matches < 0
2580 || curr_static_id->operand[nop].type != OP_IN))
2581 {
2582 int last_reload = (lra_reg_info[ORIGINAL_REGNO
2583 (operand_reg[nop])]
2584 .last_reload);
2585
2586 /* The value of reload_sum has sense only if we
2587 process insns in their order. It happens only on
2588 the first constraints sub-pass when we do most of
2589 reload work. */
2590 if (lra_constraint_iter == 1 && last_reload > bb_reload_num)
2591 reload_sum += last_reload - bb_reload_num;
2592 }
2593 /* If this is a constant that is reloaded into the
2594 desired class by copying it to memory first, count
2595 that as another reload. This is consistent with
2596 other code and is required to avoid choosing another
2597 alternative when the constant is moved into memory.
2598 Note that the test here is precisely the same as in
2599 the code below that calls force_const_mem. */
2600 if (CONST_POOL_OK_P (mode, op)
2601 && ((targetm.preferred_reload_class
2602 (op, this_alternative) == NO_REGS)
2603 || no_input_reloads_p))
2604 {
2605 const_to_mem = 1;
2606 if (! no_regs_p)
2607 losers++;
2608 }
2609
2610 /* Alternative loses if it requires a type of reload not
2611 permitted for this insn. We can always reload
2612 objects with a REG_UNUSED note. */
2613 if ((curr_static_id->operand[nop].type != OP_IN
2614 && no_output_reloads_p
2615 && ! find_reg_note (curr_insn, REG_UNUSED, op))
2616 || (curr_static_id->operand[nop].type != OP_OUT
2617 && no_input_reloads_p && ! const_to_mem)
2618 || (this_alternative_matches >= 0
2619 && (no_input_reloads_p
2620 || (no_output_reloads_p
2621 && (curr_static_id->operand
2622 [this_alternative_matches].type != OP_IN)
2623 && ! find_reg_note (curr_insn, REG_UNUSED,
2624 no_subreg_reg_operand
2625 [this_alternative_matches])))))
2626 {
2627 if (lra_dump_file != NULL)
2628 fprintf
2629 (lra_dump_file,
2630 " alt=%d: No input/otput reload -- refuse\n",
2631 nalt);
2632 goto fail;
2633 }
2634
2635 /* Alternative loses if it required class pseudo can not
2636 hold value of required mode. Such insns can be
2637 described by insn definitions with mode iterators. */
2638 if (GET_MODE (*curr_id->operand_loc[nop]) != VOIDmode
2639 && ! hard_reg_set_empty_p (this_alternative_set)
2640 /* It is common practice for constraints to use a
2641 class which does not have actually enough regs to
2642 hold the value (e.g. x86 AREG for mode requiring
2643 more one general reg). Therefore we have 2
2644 conditions to check that the reload pseudo can
2645 not hold the mode value. */
2646 && (!targetm.hard_regno_mode_ok
2647 (ira_class_hard_regs[this_alternative][0],
2648 GET_MODE (*curr_id->operand_loc[nop])))
2649 /* The above condition is not enough as the first
2650 reg in ira_class_hard_regs can be not aligned for
2651 multi-words mode values. */
2652 && (prohibited_class_reg_set_mode_p
2653 (this_alternative, this_alternative_set,
2654 GET_MODE (*curr_id->operand_loc[nop]))))
2655 {
2656 if (lra_dump_file != NULL)
2657 fprintf (lra_dump_file,
2658 " alt=%d: reload pseudo for op %d "
2659 " can not hold the mode value -- refuse\n",
2660 nalt, nop);
2661 goto fail;
2662 }
2663
2664 /* Check strong discouragement of reload of non-constant
2665 into class THIS_ALTERNATIVE. */
2666 if (! CONSTANT_P (op) && ! no_regs_p
2667 && (targetm.preferred_reload_class
2668 (op, this_alternative) == NO_REGS
2669 || (curr_static_id->operand[nop].type == OP_OUT
2670 && (targetm.preferred_output_reload_class
2671 (op, this_alternative) == NO_REGS))))
2672 {
2673 if (lra_dump_file != NULL)
2674 fprintf (lra_dump_file,
2675 " %d Non-prefered reload: reject+=%d\n",
2676 nop, LRA_MAX_REJECT);
2677 reject += LRA_MAX_REJECT;
2678 }
2679
2680 if (! (MEM_P (op) && offmemok)
2681 && ! (const_to_mem && constmemok))
2682 {
2683 /* We prefer to reload pseudos over reloading other
2684 things, since such reloads may be able to be
2685 eliminated later. So bump REJECT in other cases.
2686 Don't do this in the case where we are forcing a
2687 constant into memory and it will then win since
2688 we don't want to have a different alternative
2689 match then. */
2690 if (! (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER))
2691 {
2692 if (lra_dump_file != NULL)
2693 fprintf
2694 (lra_dump_file,
2695 " %d Non-pseudo reload: reject+=2\n",
2696 nop);
2697 reject += 2;
2698 }
2699
2700 if (! no_regs_p)
2701 reload_nregs
2702 += ira_reg_class_max_nregs[this_alternative][mode];
2703
2704 if (SMALL_REGISTER_CLASS_P (this_alternative))
2705 {
2706 if (lra_dump_file != NULL)
2707 fprintf
2708 (lra_dump_file,
2709 " %d Small class reload: reject+=%d\n",
2710 nop, LRA_LOSER_COST_FACTOR / 2);
2711 reject += LRA_LOSER_COST_FACTOR / 2;
2712 }
2713 }
2714
2715 /* We are trying to spill pseudo into memory. It is
2716 usually more costly than moving to a hard register
2717 although it might takes the same number of
2718 reloads.
2719
2720 Non-pseudo spill may happen also. Suppose a target allows both
2721 register and memory in the operand constraint alternatives,
2722 then it's typical that an eliminable register has a substition
2723 of "base + offset" which can either be reloaded by a simple
2724 "new_reg <= base + offset" which will match the register
2725 constraint, or a similar reg addition followed by further spill
2726 to and reload from memory which will match the memory
2727 constraint, but this memory spill will be much more costly
2728 usually.
2729
2730 Code below increases the reject for both pseudo and non-pseudo
2731 spill. */
2732 if (no_regs_p
2733 && !(MEM_P (op) && offmemok)
2734 && !(REG_P (op) && hard_regno[nop] < 0))
2735 {
2736 if (lra_dump_file != NULL)
2737 fprintf
2738 (lra_dump_file,
2739 " %d Spill %spseudo into memory: reject+=3\n",
2740 nop, REG_P (op) ? "" : "Non-");
2741 reject += 3;
2742 if (VECTOR_MODE_P (mode))
2743 {
2744 /* Spilling vectors into memory is usually more
2745 costly as they contain big values. */
2746 if (lra_dump_file != NULL)
2747 fprintf
2748 (lra_dump_file,
2749 " %d Spill vector pseudo: reject+=2\n",
2750 nop);
2751 reject += 2;
2752 }
2753 }
2754
2755 /* When we use an operand requiring memory in given
2756 alternative, the insn should write *and* read the
2757 value to/from memory it is costly in comparison with
2758 an insn alternative which does not use memory
2759 (e.g. register or immediate operand). We exclude
2760 memory operand for such case as we can satisfy the
2761 memory constraints by reloading address. */
2762 if (no_regs_p && offmemok && !MEM_P (op))
2763 {
2764 if (lra_dump_file != NULL)
2765 fprintf
2766 (lra_dump_file,
2767 " Using memory insn operand %d: reject+=3\n",
2768 nop);
2769 reject += 3;
2770 }
2771
2772 /* If reload requires moving value through secondary
2773 memory, it will need one more insn at least. */
2774 if (this_alternative != NO_REGS
2775 && REG_P (op) && (cl = get_reg_class (REGNO (op))) != NO_REGS
2776 && ((curr_static_id->operand[nop].type != OP_OUT
2777 && targetm.secondary_memory_needed (GET_MODE (op), cl,
2778 this_alternative))
2779 || (curr_static_id->operand[nop].type != OP_IN
2780 && (targetm.secondary_memory_needed
2781 (GET_MODE (op), this_alternative, cl)))))
2782 losers++;
2783
2784 /* Input reloads can be inherited more often than output
2785 reloads can be removed, so penalize output
2786 reloads. */
2787 if (!REG_P (op) || curr_static_id->operand[nop].type != OP_IN)
2788 {
2789 if (lra_dump_file != NULL)
2790 fprintf
2791 (lra_dump_file,
2792 " %d Non input pseudo reload: reject++\n",
2793 nop);
2794 reject++;
2795 }
2796
2797 if (MEM_P (op) && offmemok)
2798 addr_losers++;
2799 else if (curr_static_id->operand[nop].type == OP_INOUT)
2800 {
2801 if (lra_dump_file != NULL)
2802 fprintf
2803 (lra_dump_file,
2804 " %d Input/Output reload: reject+=%d\n",
2805 nop, LRA_LOSER_COST_FACTOR);
2806 reject += LRA_LOSER_COST_FACTOR;
2807 }
2808 }
2809
2810 if (early_clobber_p && ! scratch_p)
2811 {
2812 if (lra_dump_file != NULL)
2813 fprintf (lra_dump_file,
2814 " %d Early clobber: reject++\n", nop);
2815 reject++;
2816 }
2817 /* ??? We check early clobbers after processing all operands
2818 (see loop below) and there we update the costs more.
2819 Should we update the cost (may be approximately) here
2820 because of early clobber register reloads or it is a rare
2821 or non-important thing to be worth to do it. */
2822 overall = (losers * LRA_LOSER_COST_FACTOR + reject
2823 - (addr_losers == losers ? static_reject : 0));
2824 if ((best_losers == 0 || losers != 0) && best_overall < overall)
2825 {
2826 if (lra_dump_file != NULL)
2827 fprintf (lra_dump_file,
2828 " alt=%d,overall=%d,losers=%d -- refuse\n",
2829 nalt, overall, losers);
2830 goto fail;
2831 }
2832
2833 if (update_and_check_small_class_inputs (nop, this_alternative))
2834 {
2835 if (lra_dump_file != NULL)
2836 fprintf (lra_dump_file,
2837 " alt=%d, not enough small class regs -- refuse\n",
2838 nalt);
2839 goto fail;
2840 }
2841 curr_alt[nop] = this_alternative;
2842 COPY_HARD_REG_SET (curr_alt_set[nop], this_alternative_set);
2843 curr_alt_win[nop] = this_alternative_win;
2844 curr_alt_match_win[nop] = this_alternative_match_win;
2845 curr_alt_offmemok[nop] = this_alternative_offmemok;
2846 curr_alt_matches[nop] = this_alternative_matches;
2847
2848 if (this_alternative_matches >= 0
2849 && !did_match && !this_alternative_win)
2850 curr_alt_win[this_alternative_matches] = false;
2851
2852 if (early_clobber_p && operand_reg[nop] != NULL_RTX)
2853 early_clobbered_nops[early_clobbered_regs_num++] = nop;
2854 }
2855
2856 if (curr_insn_set != NULL_RTX && n_operands == 2
2857 /* Prevent processing non-move insns. */
2858 && (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG
2859 || SET_SRC (curr_insn_set) == no_subreg_reg_operand[1])
2860 && ((! curr_alt_win[0] && ! curr_alt_win[1]
2861 && REG_P (no_subreg_reg_operand[0])
2862 && REG_P (no_subreg_reg_operand[1])
2863 && (reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1])
2864 || reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0])))
2865 || (! curr_alt_win[0] && curr_alt_win[1]
2866 && REG_P (no_subreg_reg_operand[1])
2867 /* Check that we reload memory not the memory
2868 address. */
2869 && ! (curr_alt_offmemok[0]
2870 && MEM_P (no_subreg_reg_operand[0]))
2871 && reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0]))
2872 || (curr_alt_win[0] && ! curr_alt_win[1]
2873 && REG_P (no_subreg_reg_operand[0])
2874 /* Check that we reload memory not the memory
2875 address. */
2876 && ! (curr_alt_offmemok[1]
2877 && MEM_P (no_subreg_reg_operand[1]))
2878 && reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1])
2879 && (! CONST_POOL_OK_P (curr_operand_mode[1],
2880 no_subreg_reg_operand[1])
2881 || (targetm.preferred_reload_class
2882 (no_subreg_reg_operand[1],
2883 (enum reg_class) curr_alt[1]) != NO_REGS))
2884 /* If it is a result of recent elimination in move
2885 insn we can transform it into an add still by
2886 using this alternative. */
2887 && GET_CODE (no_subreg_reg_operand[1]) != PLUS
2888 /* Likewise if the source has been replaced with an
2889 equivalent value. This only happens once -- the reload
2890 will use the equivalent value instead of the register it
2891 replaces -- so there should be no danger of cycling. */
2892 && !equiv_substition_p[1])))
2893 {
2894 /* We have a move insn and a new reload insn will be similar
2895 to the current insn. We should avoid such situation as
2896 it results in LRA cycling. */
2897 if (lra_dump_file != NULL)
2898 fprintf (lra_dump_file,
2899 " Cycle danger: overall += LRA_MAX_REJECT\n");
2900 overall += LRA_MAX_REJECT;
2901 }
2902 ok_p = true;
2903 curr_alt_dont_inherit_ops_num = 0;
2904 for (nop = 0; nop < early_clobbered_regs_num; nop++)
2905 {
2906 int i, j, clobbered_hard_regno, first_conflict_j, last_conflict_j;
2907 HARD_REG_SET temp_set;
2908
2909 i = early_clobbered_nops[nop];
2910 if ((! curr_alt_win[i] && ! curr_alt_match_win[i])
2911 || hard_regno[i] < 0)
2912 continue;
2913 lra_assert (operand_reg[i] != NULL_RTX);
2914 clobbered_hard_regno = hard_regno[i];
2915 CLEAR_HARD_REG_SET (temp_set);
2916 add_to_hard_reg_set (&temp_set, biggest_mode[i], clobbered_hard_regno);
2917 first_conflict_j = last_conflict_j = -1;
2918 for (j = 0; j < n_operands; j++)
2919 if (j == i
2920 /* We don't want process insides of match_operator and
2921 match_parallel because otherwise we would process
2922 their operands once again generating a wrong
2923 code. */
2924 || curr_static_id->operand[j].is_operator)
2925 continue;
2926 else if ((curr_alt_matches[j] == i && curr_alt_match_win[j])
2927 || (curr_alt_matches[i] == j && curr_alt_match_win[i]))
2928 continue;
2929 /* If we don't reload j-th operand, check conflicts. */
2930 else if ((curr_alt_win[j] || curr_alt_match_win[j])
2931 && uses_hard_regs_p (*curr_id->operand_loc[j], temp_set))
2932 {
2933 if (first_conflict_j < 0)
2934 first_conflict_j = j;
2935 last_conflict_j = j;
2936 }
2937 if (last_conflict_j < 0)
2938 continue;
2939 /* If earlyclobber operand conflicts with another
2940 non-matching operand which is actually the same register
2941 as the earlyclobber operand, it is better to reload the
2942 another operand as an operand matching the earlyclobber
2943 operand can be also the same. */
2944 if (first_conflict_j == last_conflict_j
2945 && operand_reg[last_conflict_j] != NULL_RTX
2946 && ! curr_alt_match_win[last_conflict_j]
2947 && REGNO (operand_reg[i]) == REGNO (operand_reg[last_conflict_j]))
2948 {
2949 curr_alt_win[last_conflict_j] = false;
2950 curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++]
2951 = last_conflict_j;
2952 losers++;
2953 /* Early clobber was already reflected in REJECT. */
2954 lra_assert (reject > 0);
2955 if (lra_dump_file != NULL)
2956 fprintf
2957 (lra_dump_file,
2958 " %d Conflict early clobber reload: reject--\n",
2959 i);
2960 reject--;
2961 overall += LRA_LOSER_COST_FACTOR - 1;
2962 }
2963 else
2964 {
2965 /* We need to reload early clobbered register and the
2966 matched registers. */
2967 for (j = 0; j < n_operands; j++)
2968 if (curr_alt_matches[j] == i)
2969 {
2970 curr_alt_match_win[j] = false;
2971 losers++;
2972 overall += LRA_LOSER_COST_FACTOR;
2973 }
2974 if (! curr_alt_match_win[i])
2975 curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++] = i;
2976 else
2977 {
2978 /* Remember pseudos used for match reloads are never
2979 inherited. */
2980 lra_assert (curr_alt_matches[i] >= 0);
2981 curr_alt_win[curr_alt_matches[i]] = false;
2982 }
2983 curr_alt_win[i] = curr_alt_match_win[i] = false;
2984 losers++;
2985 /* Early clobber was already reflected in REJECT. */
2986 lra_assert (reject > 0);
2987 if (lra_dump_file != NULL)
2988 fprintf
2989 (lra_dump_file,
2990 " %d Matched conflict early clobber reloads: "
2991 "reject--\n",
2992 i);
2993 reject--;
2994 overall += LRA_LOSER_COST_FACTOR - 1;
2995 }
2996 }
2997 if (lra_dump_file != NULL)
2998 fprintf (lra_dump_file, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
2999 nalt, overall, losers, reload_nregs);
3000
3001 /* If this alternative can be made to work by reloading, and it
3002 needs less reloading than the others checked so far, record
3003 it as the chosen goal for reloading. */
3004 if ((best_losers != 0 && losers == 0)
3005 || (((best_losers == 0 && losers == 0)
3006 || (best_losers != 0 && losers != 0))
3007 && (best_overall > overall
3008 || (best_overall == overall
3009 /* If the cost of the reloads is the same,
3010 prefer alternative which requires minimal
3011 number of reload regs. */
3012 && (reload_nregs < best_reload_nregs
3013 || (reload_nregs == best_reload_nregs
3014 && (best_reload_sum < reload_sum
3015 || (best_reload_sum == reload_sum
3016 && nalt < goal_alt_number))))))))
3017 {
3018 for (nop = 0; nop < n_operands; nop++)
3019 {
3020 goal_alt_win[nop] = curr_alt_win[nop];
3021 goal_alt_match_win[nop] = curr_alt_match_win[nop];
3022 goal_alt_matches[nop] = curr_alt_matches[nop];
3023 goal_alt[nop] = curr_alt[nop];
3024 goal_alt_offmemok[nop] = curr_alt_offmemok[nop];
3025 }
3026 goal_alt_dont_inherit_ops_num = curr_alt_dont_inherit_ops_num;
3027 for (nop = 0; nop < curr_alt_dont_inherit_ops_num; nop++)
3028 goal_alt_dont_inherit_ops[nop] = curr_alt_dont_inherit_ops[nop];
3029 goal_alt_swapped = curr_swapped;
3030 best_overall = overall;
3031 best_losers = losers;
3032 best_reload_nregs = reload_nregs;
3033 best_reload_sum = reload_sum;
3034 goal_alt_number = nalt;
3035 }
3036 if (losers == 0)
3037 /* Everything is satisfied. Do not process alternatives
3038 anymore. */
3039 break;
3040 fail:
3041 ;
3042 }
3043 return ok_p;
3044 }
3045
3046 /* Make reload base reg from address AD. */
3047 static rtx
base_to_reg(struct address_info * ad)3048 base_to_reg (struct address_info *ad)
3049 {
3050 enum reg_class cl;
3051 int code = -1;
3052 rtx new_inner = NULL_RTX;
3053 rtx new_reg = NULL_RTX;
3054 rtx_insn *insn;
3055 rtx_insn *last_insn = get_last_insn();
3056
3057 lra_assert (ad->disp == ad->disp_term);
3058 cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code,
3059 get_index_code (ad));
3060 new_reg = lra_create_new_reg (GET_MODE (*ad->base), NULL_RTX,
3061 cl, "base");
3062 new_inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), new_reg,
3063 ad->disp_term == NULL
3064 ? const0_rtx
3065 : *ad->disp_term);
3066 if (!valid_address_p (ad->mode, new_inner, ad->as))
3067 return NULL_RTX;
3068 insn = emit_insn (gen_rtx_SET (new_reg, *ad->base));
3069 code = recog_memoized (insn);
3070 if (code < 0)
3071 {
3072 delete_insns_since (last_insn);
3073 return NULL_RTX;
3074 }
3075
3076 return new_inner;
3077 }
3078
3079 /* Make reload base reg + DISP from address AD. Return the new pseudo. */
3080 static rtx
base_plus_disp_to_reg(struct address_info * ad,rtx disp)3081 base_plus_disp_to_reg (struct address_info *ad, rtx disp)
3082 {
3083 enum reg_class cl;
3084 rtx new_reg;
3085
3086 lra_assert (ad->base == ad->base_term);
3087 cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code,
3088 get_index_code (ad));
3089 new_reg = lra_create_new_reg (GET_MODE (*ad->base_term), NULL_RTX,
3090 cl, "base + disp");
3091 lra_emit_add (new_reg, *ad->base_term, disp);
3092 return new_reg;
3093 }
3094
3095 /* Make reload of index part of address AD. Return the new
3096 pseudo. */
3097 static rtx
index_part_to_reg(struct address_info * ad)3098 index_part_to_reg (struct address_info *ad)
3099 {
3100 rtx new_reg;
3101
3102 new_reg = lra_create_new_reg (GET_MODE (*ad->index), NULL_RTX,
3103 INDEX_REG_CLASS, "index term");
3104 expand_mult (GET_MODE (*ad->index), *ad->index_term,
3105 GEN_INT (get_index_scale (ad)), new_reg, 1);
3106 return new_reg;
3107 }
3108
3109 /* Return true if we can add a displacement to address AD, even if that
3110 makes the address invalid. The fix-up code requires any new address
3111 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
3112 static bool
can_add_disp_p(struct address_info * ad)3113 can_add_disp_p (struct address_info *ad)
3114 {
3115 return (!ad->autoinc_p
3116 && ad->segment == NULL
3117 && ad->base == ad->base_term
3118 && ad->disp == ad->disp_term);
3119 }
3120
3121 /* Make equiv substitution in address AD. Return true if a substitution
3122 was made. */
3123 static bool
equiv_address_substitution(struct address_info * ad)3124 equiv_address_substitution (struct address_info *ad)
3125 {
3126 rtx base_reg, new_base_reg, index_reg, new_index_reg, *base_term, *index_term;
3127 poly_int64 disp;
3128 HOST_WIDE_INT scale;
3129 bool change_p;
3130
3131 base_term = strip_subreg (ad->base_term);
3132 if (base_term == NULL)
3133 base_reg = new_base_reg = NULL_RTX;
3134 else
3135 {
3136 base_reg = *base_term;
3137 new_base_reg = get_equiv_with_elimination (base_reg, curr_insn);
3138 }
3139 index_term = strip_subreg (ad->index_term);
3140 if (index_term == NULL)
3141 index_reg = new_index_reg = NULL_RTX;
3142 else
3143 {
3144 index_reg = *index_term;
3145 new_index_reg = get_equiv_with_elimination (index_reg, curr_insn);
3146 }
3147 if (base_reg == new_base_reg && index_reg == new_index_reg)
3148 return false;
3149 disp = 0;
3150 change_p = false;
3151 if (lra_dump_file != NULL)
3152 {
3153 fprintf (lra_dump_file, "Changing address in insn %d ",
3154 INSN_UID (curr_insn));
3155 dump_value_slim (lra_dump_file, *ad->outer, 1);
3156 }
3157 if (base_reg != new_base_reg)
3158 {
3159 poly_int64 offset;
3160 if (REG_P (new_base_reg))
3161 {
3162 *base_term = new_base_reg;
3163 change_p = true;
3164 }
3165 else if (GET_CODE (new_base_reg) == PLUS
3166 && REG_P (XEXP (new_base_reg, 0))
3167 && poly_int_rtx_p (XEXP (new_base_reg, 1), &offset)
3168 && can_add_disp_p (ad))
3169 {
3170 disp += offset;
3171 *base_term = XEXP (new_base_reg, 0);
3172 change_p = true;
3173 }
3174 if (ad->base_term2 != NULL)
3175 *ad->base_term2 = *ad->base_term;
3176 }
3177 if (index_reg != new_index_reg)
3178 {
3179 poly_int64 offset;
3180 if (REG_P (new_index_reg))
3181 {
3182 *index_term = new_index_reg;
3183 change_p = true;
3184 }
3185 else if (GET_CODE (new_index_reg) == PLUS
3186 && REG_P (XEXP (new_index_reg, 0))
3187 && poly_int_rtx_p (XEXP (new_index_reg, 1), &offset)
3188 && can_add_disp_p (ad)
3189 && (scale = get_index_scale (ad)))
3190 {
3191 disp += offset * scale;
3192 *index_term = XEXP (new_index_reg, 0);
3193 change_p = true;
3194 }
3195 }
3196 if (maybe_ne (disp, 0))
3197 {
3198 if (ad->disp != NULL)
3199 *ad->disp = plus_constant (GET_MODE (*ad->inner), *ad->disp, disp);
3200 else
3201 {
3202 *ad->inner = plus_constant (GET_MODE (*ad->inner), *ad->inner, disp);
3203 update_address (ad);
3204 }
3205 change_p = true;
3206 }
3207 if (lra_dump_file != NULL)
3208 {
3209 if (! change_p)
3210 fprintf (lra_dump_file, " -- no change\n");
3211 else
3212 {
3213 fprintf (lra_dump_file, " on equiv ");
3214 dump_value_slim (lra_dump_file, *ad->outer, 1);
3215 fprintf (lra_dump_file, "\n");
3216 }
3217 }
3218 return change_p;
3219 }
3220
3221 /* Major function to make reloads for an address in operand NOP or
3222 check its correctness (If CHECK_ONLY_P is true). The supported
3223 cases are:
3224
3225 1) an address that existed before LRA started, at which point it
3226 must have been valid. These addresses are subject to elimination
3227 and may have become invalid due to the elimination offset being out
3228 of range.
3229
3230 2) an address created by forcing a constant to memory
3231 (force_const_to_mem). The initial form of these addresses might
3232 not be valid, and it is this function's job to make them valid.
3233
3234 3) a frame address formed from a register and a (possibly zero)
3235 constant offset. As above, these addresses might not be valid and
3236 this function must make them so.
3237
3238 Add reloads to the lists *BEFORE and *AFTER. We might need to add
3239 reloads to *AFTER because of inc/dec, {pre, post} modify in the
3240 address. Return true for any RTL change.
3241
3242 The function is a helper function which does not produce all
3243 transformations (when CHECK_ONLY_P is false) which can be
3244 necessary. It does just basic steps. To do all necessary
3245 transformations use function process_address. */
3246 static bool
process_address_1(int nop,bool check_only_p,rtx_insn ** before,rtx_insn ** after)3247 process_address_1 (int nop, bool check_only_p,
3248 rtx_insn **before, rtx_insn **after)
3249 {
3250 struct address_info ad;
3251 rtx new_reg;
3252 HOST_WIDE_INT scale;
3253 rtx op = *curr_id->operand_loc[nop];
3254 const char *constraint = curr_static_id->operand[nop].constraint;
3255 enum constraint_num cn = lookup_constraint (constraint);
3256 bool change_p = false;
3257
3258 if (MEM_P (op)
3259 && GET_MODE (op) == BLKmode
3260 && GET_CODE (XEXP (op, 0)) == SCRATCH)
3261 return false;
3262
3263 if (insn_extra_address_constraint (cn)
3264 /* When we find an asm operand with an address constraint that
3265 doesn't satisfy address_operand to begin with, we clear
3266 is_address, so that we don't try to make a non-address fit.
3267 If the asm statement got this far, it's because other
3268 constraints are available, and we'll use them, disregarding
3269 the unsatisfiable address ones. */
3270 && curr_static_id->operand[nop].is_address)
3271 decompose_lea_address (&ad, curr_id->operand_loc[nop]);
3272 /* Do not attempt to decompose arbitrary addresses generated by combine
3273 for asm operands with loose constraints, e.g 'X'. */
3274 else if (MEM_P (op)
3275 && !(INSN_CODE (curr_insn) < 0
3276 && get_constraint_type (cn) == CT_FIXED_FORM
3277 && constraint_satisfied_p (op, cn)))
3278 decompose_mem_address (&ad, op);
3279 else if (GET_CODE (op) == SUBREG
3280 && MEM_P (SUBREG_REG (op)))
3281 decompose_mem_address (&ad, SUBREG_REG (op));
3282 else
3283 return false;
3284 /* If INDEX_REG_CLASS is assigned to base_term already and isn't to
3285 index_term, swap them so to avoid assigning INDEX_REG_CLASS to both
3286 when INDEX_REG_CLASS is a single register class. */
3287 if (ad.base_term != NULL
3288 && ad.index_term != NULL
3289 && ira_class_hard_regs_num[INDEX_REG_CLASS] == 1
3290 && REG_P (*ad.base_term)
3291 && REG_P (*ad.index_term)
3292 && in_class_p (*ad.base_term, INDEX_REG_CLASS, NULL)
3293 && ! in_class_p (*ad.index_term, INDEX_REG_CLASS, NULL))
3294 {
3295 std::swap (ad.base, ad.index);
3296 std::swap (ad.base_term, ad.index_term);
3297 }
3298 if (! check_only_p)
3299 change_p = equiv_address_substitution (&ad);
3300 if (ad.base_term != NULL
3301 && (process_addr_reg
3302 (ad.base_term, check_only_p, before,
3303 (ad.autoinc_p
3304 && !(REG_P (*ad.base_term)
3305 && find_regno_note (curr_insn, REG_DEAD,
3306 REGNO (*ad.base_term)) != NULL_RTX)
3307 ? after : NULL),
3308 base_reg_class (ad.mode, ad.as, ad.base_outer_code,
3309 get_index_code (&ad)))))
3310 {
3311 change_p = true;
3312 if (ad.base_term2 != NULL)
3313 *ad.base_term2 = *ad.base_term;
3314 }
3315 if (ad.index_term != NULL
3316 && process_addr_reg (ad.index_term, check_only_p,
3317 before, NULL, INDEX_REG_CLASS))
3318 change_p = true;
3319
3320 /* Target hooks sometimes don't treat extra-constraint addresses as
3321 legitimate address_operands, so handle them specially. */
3322 if (insn_extra_address_constraint (cn)
3323 && satisfies_address_constraint_p (&ad, cn))
3324 return change_p;
3325
3326 if (check_only_p)
3327 return change_p;
3328
3329 /* There are three cases where the shape of *AD.INNER may now be invalid:
3330
3331 1) the original address was valid, but either elimination or
3332 equiv_address_substitution was applied and that made
3333 the address invalid.
3334
3335 2) the address is an invalid symbolic address created by
3336 force_const_to_mem.
3337
3338 3) the address is a frame address with an invalid offset.
3339
3340 4) the address is a frame address with an invalid base.
3341
3342 All these cases involve a non-autoinc address, so there is no
3343 point revalidating other types. */
3344 if (ad.autoinc_p || valid_address_p (&ad))
3345 return change_p;
3346
3347 /* Any index existed before LRA started, so we can assume that the
3348 presence and shape of the index is valid. */
3349 push_to_sequence (*before);
3350 lra_assert (ad.disp == ad.disp_term);
3351 if (ad.base == NULL)
3352 {
3353 if (ad.index == NULL)
3354 {
3355 rtx_insn *insn;
3356 rtx_insn *last = get_last_insn ();
3357 int code = -1;
3358 enum reg_class cl = base_reg_class (ad.mode, ad.as,
3359 SCRATCH, SCRATCH);
3360 rtx addr = *ad.inner;
3361
3362 new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "addr");
3363 if (HAVE_lo_sum)
3364 {
3365 /* addr => lo_sum (new_base, addr), case (2) above. */
3366 insn = emit_insn (gen_rtx_SET
3367 (new_reg,
3368 gen_rtx_HIGH (Pmode, copy_rtx (addr))));
3369 code = recog_memoized (insn);
3370 if (code >= 0)
3371 {
3372 *ad.inner = gen_rtx_LO_SUM (Pmode, new_reg, addr);
3373 if (! valid_address_p (ad.mode, *ad.outer, ad.as))
3374 {
3375 /* Try to put lo_sum into register. */
3376 insn = emit_insn (gen_rtx_SET
3377 (new_reg,
3378 gen_rtx_LO_SUM (Pmode, new_reg, addr)));
3379 code = recog_memoized (insn);
3380 if (code >= 0)
3381 {
3382 *ad.inner = new_reg;
3383 if (! valid_address_p (ad.mode, *ad.outer, ad.as))
3384 {
3385 *ad.inner = addr;
3386 code = -1;
3387 }
3388 }
3389
3390 }
3391 }
3392 if (code < 0)
3393 delete_insns_since (last);
3394 }
3395
3396 if (code < 0)
3397 {
3398 /* addr => new_base, case (2) above. */
3399 lra_emit_move (new_reg, addr);
3400
3401 for (insn = last == NULL_RTX ? get_insns () : NEXT_INSN (last);
3402 insn != NULL_RTX;
3403 insn = NEXT_INSN (insn))
3404 if (recog_memoized (insn) < 0)
3405 break;
3406 if (insn != NULL_RTX)
3407 {
3408 /* Do nothing if we cannot generate right insns.
3409 This is analogous to reload pass behavior. */
3410 delete_insns_since (last);
3411 end_sequence ();
3412 return false;
3413 }
3414 *ad.inner = new_reg;
3415 }
3416 }
3417 else
3418 {
3419 /* index * scale + disp => new base + index * scale,
3420 case (1) above. */
3421 enum reg_class cl = base_reg_class (ad.mode, ad.as, PLUS,
3422 GET_CODE (*ad.index));
3423
3424 lra_assert (INDEX_REG_CLASS != NO_REGS);
3425 new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "disp");
3426 lra_emit_move (new_reg, *ad.disp);
3427 *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg),
3428 new_reg, *ad.index);
3429 }
3430 }
3431 else if (ad.index == NULL)
3432 {
3433 int regno;
3434 enum reg_class cl;
3435 rtx set;
3436 rtx_insn *insns, *last_insn;
3437 /* Try to reload base into register only if the base is invalid
3438 for the address but with valid offset, case (4) above. */
3439 start_sequence ();
3440 new_reg = base_to_reg (&ad);
3441
3442 /* base + disp => new base, cases (1) and (3) above. */
3443 /* Another option would be to reload the displacement into an
3444 index register. However, postreload has code to optimize
3445 address reloads that have the same base and different
3446 displacements, so reloading into an index register would
3447 not necessarily be a win. */
3448 if (new_reg == NULL_RTX)
3449 {
3450 /* See if the target can split the displacement into a
3451 legitimate new displacement from a local anchor. */
3452 gcc_assert (ad.disp == ad.disp_term);
3453 poly_int64 orig_offset;
3454 rtx offset1, offset2;
3455 if (poly_int_rtx_p (*ad.disp, &orig_offset)
3456 && targetm.legitimize_address_displacement (&offset1, &offset2,
3457 orig_offset,
3458 ad.mode))
3459 {
3460 new_reg = base_plus_disp_to_reg (&ad, offset1);
3461 new_reg = gen_rtx_PLUS (GET_MODE (new_reg), new_reg, offset2);
3462 }
3463 else
3464 new_reg = base_plus_disp_to_reg (&ad, *ad.disp);
3465 }
3466 insns = get_insns ();
3467 last_insn = get_last_insn ();
3468 /* If we generated at least two insns, try last insn source as
3469 an address. If we succeed, we generate one less insn. */
3470 if (REG_P (new_reg)
3471 && last_insn != insns
3472 && (set = single_set (last_insn)) != NULL_RTX
3473 && GET_CODE (SET_SRC (set)) == PLUS
3474 && REG_P (XEXP (SET_SRC (set), 0))
3475 && CONSTANT_P (XEXP (SET_SRC (set), 1)))
3476 {
3477 *ad.inner = SET_SRC (set);
3478 if (valid_address_p (ad.mode, *ad.outer, ad.as))
3479 {
3480 *ad.base_term = XEXP (SET_SRC (set), 0);
3481 *ad.disp_term = XEXP (SET_SRC (set), 1);
3482 cl = base_reg_class (ad.mode, ad.as, ad.base_outer_code,
3483 get_index_code (&ad));
3484 regno = REGNO (*ad.base_term);
3485 if (regno >= FIRST_PSEUDO_REGISTER
3486 && cl != lra_get_allocno_class (regno))
3487 lra_change_class (regno, cl, " Change to", true);
3488 new_reg = SET_SRC (set);
3489 delete_insns_since (PREV_INSN (last_insn));
3490 }
3491 }
3492 end_sequence ();
3493 emit_insn (insns);
3494 *ad.inner = new_reg;
3495 }
3496 else if (ad.disp_term != NULL)
3497 {
3498 /* base + scale * index + disp => new base + scale * index,
3499 case (1) above. */
3500 gcc_assert (ad.disp == ad.disp_term);
3501 new_reg = base_plus_disp_to_reg (&ad, *ad.disp);
3502 *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg),
3503 new_reg, *ad.index);
3504 }
3505 else if ((scale = get_index_scale (&ad)) == 1)
3506 {
3507 /* The last transformation to one reg will be made in
3508 curr_insn_transform function. */
3509 end_sequence ();
3510 return false;
3511 }
3512 else if (scale != 0)
3513 {
3514 /* base + scale * index => base + new_reg,
3515 case (1) above.
3516 Index part of address may become invalid. For example, we
3517 changed pseudo on the equivalent memory and a subreg of the
3518 pseudo onto the memory of different mode for which the scale is
3519 prohibitted. */
3520 new_reg = index_part_to_reg (&ad);
3521 *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg),
3522 *ad.base_term, new_reg);
3523 }
3524 else
3525 {
3526 enum reg_class cl = base_reg_class (ad.mode, ad.as,
3527 SCRATCH, SCRATCH);
3528 rtx addr = *ad.inner;
3529
3530 new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "addr");
3531 /* addr => new_base. */
3532 lra_emit_move (new_reg, addr);
3533 *ad.inner = new_reg;
3534 }
3535 *before = get_insns ();
3536 end_sequence ();
3537 return true;
3538 }
3539
3540 /* If CHECK_ONLY_P is false, do address reloads until it is necessary.
3541 Use process_address_1 as a helper function. Return true for any
3542 RTL changes.
3543
3544 If CHECK_ONLY_P is true, just check address correctness. Return
3545 false if the address correct. */
3546 static bool
process_address(int nop,bool check_only_p,rtx_insn ** before,rtx_insn ** after)3547 process_address (int nop, bool check_only_p,
3548 rtx_insn **before, rtx_insn **after)
3549 {
3550 bool res = false;
3551
3552 while (process_address_1 (nop, check_only_p, before, after))
3553 {
3554 if (check_only_p)
3555 return true;
3556 res = true;
3557 }
3558 return res;
3559 }
3560
3561 /* Emit insns to reload VALUE into a new register. VALUE is an
3562 auto-increment or auto-decrement RTX whose operand is a register or
3563 memory location; so reloading involves incrementing that location.
3564 IN is either identical to VALUE, or some cheaper place to reload
3565 value being incremented/decremented from.
3566
3567 INC_AMOUNT is the number to increment or decrement by (always
3568 positive and ignored for POST_MODIFY/PRE_MODIFY).
3569
3570 Return pseudo containing the result. */
3571 static rtx
emit_inc(enum reg_class new_rclass,rtx in,rtx value,poly_int64 inc_amount)3572 emit_inc (enum reg_class new_rclass, rtx in, rtx value, poly_int64 inc_amount)
3573 {
3574 /* REG or MEM to be copied and incremented. */
3575 rtx incloc = XEXP (value, 0);
3576 /* Nonzero if increment after copying. */
3577 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
3578 || GET_CODE (value) == POST_MODIFY);
3579 rtx_insn *last;
3580 rtx inc;
3581 rtx_insn *add_insn;
3582 int code;
3583 rtx real_in = in == value ? incloc : in;
3584 rtx result;
3585 bool plus_p = true;
3586
3587 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
3588 {
3589 lra_assert (GET_CODE (XEXP (value, 1)) == PLUS
3590 || GET_CODE (XEXP (value, 1)) == MINUS);
3591 lra_assert (rtx_equal_p (XEXP (XEXP (value, 1), 0), XEXP (value, 0)));
3592 plus_p = GET_CODE (XEXP (value, 1)) == PLUS;
3593 inc = XEXP (XEXP (value, 1), 1);
3594 }
3595 else
3596 {
3597 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
3598 inc_amount = -inc_amount;
3599
3600 inc = gen_int_mode (inc_amount, GET_MODE (value));
3601 }
3602
3603 if (! post && REG_P (incloc))
3604 result = incloc;
3605 else
3606 result = lra_create_new_reg (GET_MODE (value), value, new_rclass,
3607 "INC/DEC result");
3608
3609 if (real_in != result)
3610 {
3611 /* First copy the location to the result register. */
3612 lra_assert (REG_P (result));
3613 emit_insn (gen_move_insn (result, real_in));
3614 }
3615
3616 /* We suppose that there are insns to add/sub with the constant
3617 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
3618 old reload worked with this assumption. If the assumption
3619 becomes wrong, we should use approach in function
3620 base_plus_disp_to_reg. */
3621 if (in == value)
3622 {
3623 /* See if we can directly increment INCLOC. */
3624 last = get_last_insn ();
3625 add_insn = emit_insn (plus_p
3626 ? gen_add2_insn (incloc, inc)
3627 : gen_sub2_insn (incloc, inc));
3628
3629 code = recog_memoized (add_insn);
3630 if (code >= 0)
3631 {
3632 if (! post && result != incloc)
3633 emit_insn (gen_move_insn (result, incloc));
3634 return result;
3635 }
3636 delete_insns_since (last);
3637 }
3638
3639 /* If couldn't do the increment directly, must increment in RESULT.
3640 The way we do this depends on whether this is pre- or
3641 post-increment. For pre-increment, copy INCLOC to the reload
3642 register, increment it there, then save back. */
3643 if (! post)
3644 {
3645 if (real_in != result)
3646 emit_insn (gen_move_insn (result, real_in));
3647 if (plus_p)
3648 emit_insn (gen_add2_insn (result, inc));
3649 else
3650 emit_insn (gen_sub2_insn (result, inc));
3651 if (result != incloc)
3652 emit_insn (gen_move_insn (incloc, result));
3653 }
3654 else
3655 {
3656 /* Post-increment.
3657
3658 Because this might be a jump insn or a compare, and because
3659 RESULT may not be available after the insn in an input
3660 reload, we must do the incrementing before the insn being
3661 reloaded for.
3662
3663 We have already copied IN to RESULT. Increment the copy in
3664 RESULT, save that back, then decrement RESULT so it has
3665 the original value. */
3666 if (plus_p)
3667 emit_insn (gen_add2_insn (result, inc));
3668 else
3669 emit_insn (gen_sub2_insn (result, inc));
3670 emit_insn (gen_move_insn (incloc, result));
3671 /* Restore non-modified value for the result. We prefer this
3672 way because it does not require an additional hard
3673 register. */
3674 if (plus_p)
3675 {
3676 poly_int64 offset;
3677 if (poly_int_rtx_p (inc, &offset))
3678 emit_insn (gen_add2_insn (result,
3679 gen_int_mode (-offset,
3680 GET_MODE (result))));
3681 else
3682 emit_insn (gen_sub2_insn (result, inc));
3683 }
3684 else
3685 emit_insn (gen_add2_insn (result, inc));
3686 }
3687 return result;
3688 }
3689
3690 /* Return true if the current move insn does not need processing as we
3691 already know that it satisfies its constraints. */
3692 static bool
simple_move_p(void)3693 simple_move_p (void)
3694 {
3695 rtx dest, src;
3696 enum reg_class dclass, sclass;
3697
3698 lra_assert (curr_insn_set != NULL_RTX);
3699 dest = SET_DEST (curr_insn_set);
3700 src = SET_SRC (curr_insn_set);
3701
3702 /* If the instruction has multiple sets we need to process it even if it
3703 is single_set. This can happen if one or more of the SETs are dead.
3704 See PR73650. */
3705 if (multiple_sets (curr_insn))
3706 return false;
3707
3708 return ((dclass = get_op_class (dest)) != NO_REGS
3709 && (sclass = get_op_class (src)) != NO_REGS
3710 /* The backend guarantees that register moves of cost 2
3711 never need reloads. */
3712 && targetm.register_move_cost (GET_MODE (src), sclass, dclass) == 2);
3713 }
3714
3715 /* Swap operands NOP and NOP + 1. */
3716 static inline void
swap_operands(int nop)3717 swap_operands (int nop)
3718 {
3719 std::swap (curr_operand_mode[nop], curr_operand_mode[nop + 1]);
3720 std::swap (original_subreg_reg_mode[nop], original_subreg_reg_mode[nop + 1]);
3721 std::swap (*curr_id->operand_loc[nop], *curr_id->operand_loc[nop + 1]);
3722 std::swap (equiv_substition_p[nop], equiv_substition_p[nop + 1]);
3723 /* Swap the duplicates too. */
3724 lra_update_dup (curr_id, nop);
3725 lra_update_dup (curr_id, nop + 1);
3726 }
3727
3728 /* Main entry point of the constraint code: search the body of the
3729 current insn to choose the best alternative. It is mimicking insn
3730 alternative cost calculation model of former reload pass. That is
3731 because machine descriptions were written to use this model. This
3732 model can be changed in future. Make commutative operand exchange
3733 if it is chosen.
3734
3735 if CHECK_ONLY_P is false, do RTL changes to satisfy the
3736 constraints. Return true if any change happened during function
3737 call.
3738
3739 If CHECK_ONLY_P is true then don't do any transformation. Just
3740 check that the insn satisfies all constraints. If the insn does
3741 not satisfy any constraint, return true. */
3742 static bool
curr_insn_transform(bool check_only_p)3743 curr_insn_transform (bool check_only_p)
3744 {
3745 int i, j, k;
3746 int n_operands;
3747 int n_alternatives;
3748 int n_outputs;
3749 int commutative;
3750 signed char goal_alt_matched[MAX_RECOG_OPERANDS][MAX_RECOG_OPERANDS];
3751 signed char match_inputs[MAX_RECOG_OPERANDS + 1];
3752 signed char outputs[MAX_RECOG_OPERANDS + 1];
3753 rtx_insn *before, *after;
3754 bool alt_p = false;
3755 /* Flag that the insn has been changed through a transformation. */
3756 bool change_p;
3757 bool sec_mem_p;
3758 bool use_sec_mem_p;
3759 int max_regno_before;
3760 int reused_alternative_num;
3761
3762 curr_insn_set = single_set (curr_insn);
3763 if (curr_insn_set != NULL_RTX && simple_move_p ())
3764 {
3765 /* We assume that the corresponding insn alternative has no
3766 earlier clobbers. If it is not the case, don't define move
3767 cost equal to 2 for the corresponding register classes. */
3768 lra_set_used_insn_alternative (curr_insn, LRA_NON_CLOBBERED_ALT);
3769 return false;
3770 }
3771
3772 no_input_reloads_p = no_output_reloads_p = false;
3773 goal_alt_number = -1;
3774 change_p = sec_mem_p = false;
3775 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
3776 reloads; neither are insns that SET cc0. Insns that use CC0 are
3777 not allowed to have any input reloads. */
3778 if (JUMP_P (curr_insn) || CALL_P (curr_insn))
3779 no_output_reloads_p = true;
3780
3781 if (HAVE_cc0 && reg_referenced_p (cc0_rtx, PATTERN (curr_insn)))
3782 no_input_reloads_p = true;
3783 if (HAVE_cc0 && reg_set_p (cc0_rtx, PATTERN (curr_insn)))
3784 no_output_reloads_p = true;
3785
3786 n_operands = curr_static_id->n_operands;
3787 n_alternatives = curr_static_id->n_alternatives;
3788
3789 /* Just return "no reloads" if insn has no operands with
3790 constraints. */
3791 if (n_operands == 0 || n_alternatives == 0)
3792 return false;
3793
3794 max_regno_before = max_reg_num ();
3795
3796 for (i = 0; i < n_operands; i++)
3797 {
3798 goal_alt_matched[i][0] = -1;
3799 goal_alt_matches[i] = -1;
3800 }
3801
3802 commutative = curr_static_id->commutative;
3803
3804 /* Now see what we need for pseudos that didn't get hard regs or got
3805 the wrong kind of hard reg. For this, we must consider all the
3806 operands together against the register constraints. */
3807
3808 best_losers = best_overall = INT_MAX;
3809 best_reload_sum = 0;
3810
3811 curr_swapped = false;
3812 goal_alt_swapped = false;
3813
3814 if (! check_only_p)
3815 /* Make equivalence substitution and memory subreg elimination
3816 before address processing because an address legitimacy can
3817 depend on memory mode. */
3818 for (i = 0; i < n_operands; i++)
3819 {
3820 rtx op, subst, old;
3821 bool op_change_p = false;
3822
3823 if (curr_static_id->operand[i].is_operator)
3824 continue;
3825
3826 old = op = *curr_id->operand_loc[i];
3827 if (GET_CODE (old) == SUBREG)
3828 old = SUBREG_REG (old);
3829 subst = get_equiv_with_elimination (old, curr_insn);
3830 original_subreg_reg_mode[i] = VOIDmode;
3831 equiv_substition_p[i] = false;
3832 if (subst != old)
3833 {
3834 equiv_substition_p[i] = true;
3835 subst = copy_rtx (subst);
3836 lra_assert (REG_P (old));
3837 if (GET_CODE (op) != SUBREG)
3838 *curr_id->operand_loc[i] = subst;
3839 else
3840 {
3841 SUBREG_REG (op) = subst;
3842 if (GET_MODE (subst) == VOIDmode)
3843 original_subreg_reg_mode[i] = GET_MODE (old);
3844 }
3845 if (lra_dump_file != NULL)
3846 {
3847 fprintf (lra_dump_file,
3848 "Changing pseudo %d in operand %i of insn %u on equiv ",
3849 REGNO (old), i, INSN_UID (curr_insn));
3850 dump_value_slim (lra_dump_file, subst, 1);
3851 fprintf (lra_dump_file, "\n");
3852 }
3853 op_change_p = change_p = true;
3854 }
3855 if (simplify_operand_subreg (i, GET_MODE (old)) || op_change_p)
3856 {
3857 change_p = true;
3858 lra_update_dup (curr_id, i);
3859 }
3860 }
3861
3862 /* Reload address registers and displacements. We do it before
3863 finding an alternative because of memory constraints. */
3864 before = after = NULL;
3865 for (i = 0; i < n_operands; i++)
3866 if (! curr_static_id->operand[i].is_operator
3867 && process_address (i, check_only_p, &before, &after))
3868 {
3869 if (check_only_p)
3870 return true;
3871 change_p = true;
3872 lra_update_dup (curr_id, i);
3873 }
3874
3875 if (change_p)
3876 /* If we've changed the instruction then any alternative that
3877 we chose previously may no longer be valid. */
3878 lra_set_used_insn_alternative (curr_insn, LRA_UNKNOWN_ALT);
3879
3880 if (! check_only_p && curr_insn_set != NULL_RTX
3881 && check_and_process_move (&change_p, &sec_mem_p))
3882 return change_p;
3883
3884 try_swapped:
3885
3886 reused_alternative_num = check_only_p ? LRA_UNKNOWN_ALT : curr_id->used_insn_alternative;
3887 if (lra_dump_file != NULL && reused_alternative_num >= 0)
3888 fprintf (lra_dump_file, "Reusing alternative %d for insn #%u\n",
3889 reused_alternative_num, INSN_UID (curr_insn));
3890
3891 if (process_alt_operands (reused_alternative_num))
3892 alt_p = true;
3893
3894 if (check_only_p)
3895 return ! alt_p || best_losers != 0;
3896
3897 /* If insn is commutative (it's safe to exchange a certain pair of
3898 operands) then we need to try each alternative twice, the second
3899 time matching those two operands as if we had exchanged them. To
3900 do this, really exchange them in operands.
3901
3902 If we have just tried the alternatives the second time, return
3903 operands to normal and drop through. */
3904
3905 if (reused_alternative_num < 0 && commutative >= 0)
3906 {
3907 curr_swapped = !curr_swapped;
3908 if (curr_swapped)
3909 {
3910 swap_operands (commutative);
3911 goto try_swapped;
3912 }
3913 else
3914 swap_operands (commutative);
3915 }
3916
3917 if (! alt_p && ! sec_mem_p)
3918 {
3919 /* No alternative works with reloads?? */
3920 if (INSN_CODE (curr_insn) >= 0)
3921 fatal_insn ("unable to generate reloads for:", curr_insn);
3922 error_for_asm (curr_insn,
3923 "inconsistent operand constraints in an %<asm%>");
3924 /* Avoid further trouble with this insn. Don't generate use
3925 pattern here as we could use the insn SP offset. */
3926 lra_set_insn_deleted (curr_insn);
3927 return true;
3928 }
3929
3930 /* If the best alternative is with operands 1 and 2 swapped, swap
3931 them. Update the operand numbers of any reloads already
3932 pushed. */
3933
3934 if (goal_alt_swapped)
3935 {
3936 if (lra_dump_file != NULL)
3937 fprintf (lra_dump_file, " Commutative operand exchange in insn %u\n",
3938 INSN_UID (curr_insn));
3939
3940 /* Swap the duplicates too. */
3941 swap_operands (commutative);
3942 change_p = true;
3943 }
3944
3945 /* Some targets' TARGET_SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
3946 too conservatively. So we use the secondary memory only if there
3947 is no any alternative without reloads. */
3948 use_sec_mem_p = false;
3949 if (! alt_p)
3950 use_sec_mem_p = true;
3951 else if (sec_mem_p)
3952 {
3953 for (i = 0; i < n_operands; i++)
3954 if (! goal_alt_win[i] && ! goal_alt_match_win[i])
3955 break;
3956 use_sec_mem_p = i < n_operands;
3957 }
3958
3959 if (use_sec_mem_p)
3960 {
3961 int in = -1, out = -1;
3962 rtx new_reg, src, dest, rld;
3963 machine_mode sec_mode, rld_mode;
3964
3965 lra_assert (curr_insn_set != NULL_RTX && sec_mem_p);
3966 dest = SET_DEST (curr_insn_set);
3967 src = SET_SRC (curr_insn_set);
3968 for (i = 0; i < n_operands; i++)
3969 if (*curr_id->operand_loc[i] == dest)
3970 out = i;
3971 else if (*curr_id->operand_loc[i] == src)
3972 in = i;
3973 for (i = 0; i < curr_static_id->n_dups; i++)
3974 if (out < 0 && *curr_id->dup_loc[i] == dest)
3975 out = curr_static_id->dup_num[i];
3976 else if (in < 0 && *curr_id->dup_loc[i] == src)
3977 in = curr_static_id->dup_num[i];
3978 lra_assert (out >= 0 && in >= 0
3979 && curr_static_id->operand[out].type == OP_OUT
3980 && curr_static_id->operand[in].type == OP_IN);
3981 rld = partial_subreg_p (GET_MODE (src), GET_MODE (dest)) ? src : dest;
3982 rld_mode = GET_MODE (rld);
3983 sec_mode = targetm.secondary_memory_needed_mode (rld_mode);
3984 new_reg = lra_create_new_reg (sec_mode, NULL_RTX,
3985 NO_REGS, "secondary");
3986 /* If the mode is changed, it should be wider. */
3987 lra_assert (!partial_subreg_p (sec_mode, rld_mode));
3988 if (sec_mode != rld_mode)
3989 {
3990 /* If the target says specifically to use another mode for
3991 secondary memory moves we can not reuse the original
3992 insn. */
3993 after = emit_spill_move (false, new_reg, dest);
3994 lra_process_new_insns (curr_insn, NULL, after,
3995 "Inserting the sec. move");
3996 /* We may have non null BEFORE here (e.g. after address
3997 processing. */
3998 push_to_sequence (before);
3999 before = emit_spill_move (true, new_reg, src);
4000 emit_insn (before);
4001 before = get_insns ();
4002 end_sequence ();
4003 lra_process_new_insns (curr_insn, before, NULL, "Changing on");
4004 lra_set_insn_deleted (curr_insn);
4005 }
4006 else if (dest == rld)
4007 {
4008 *curr_id->operand_loc[out] = new_reg;
4009 lra_update_dup (curr_id, out);
4010 after = emit_spill_move (false, new_reg, dest);
4011 lra_process_new_insns (curr_insn, NULL, after,
4012 "Inserting the sec. move");
4013 }
4014 else
4015 {
4016 *curr_id->operand_loc[in] = new_reg;
4017 lra_update_dup (curr_id, in);
4018 /* See comments above. */
4019 push_to_sequence (before);
4020 before = emit_spill_move (true, new_reg, src);
4021 emit_insn (before);
4022 before = get_insns ();
4023 end_sequence ();
4024 lra_process_new_insns (curr_insn, before, NULL,
4025 "Inserting the sec. move");
4026 }
4027 lra_update_insn_regno_info (curr_insn);
4028 return true;
4029 }
4030
4031 lra_assert (goal_alt_number >= 0);
4032 lra_set_used_insn_alternative (curr_insn, goal_alt_number);
4033
4034 if (lra_dump_file != NULL)
4035 {
4036 const char *p;
4037
4038 fprintf (lra_dump_file, " Choosing alt %d in insn %u:",
4039 goal_alt_number, INSN_UID (curr_insn));
4040 for (i = 0; i < n_operands; i++)
4041 {
4042 p = (curr_static_id->operand_alternative
4043 [goal_alt_number * n_operands + i].constraint);
4044 if (*p == '\0')
4045 continue;
4046 fprintf (lra_dump_file, " (%d) ", i);
4047 for (; *p != '\0' && *p != ',' && *p != '#'; p++)
4048 fputc (*p, lra_dump_file);
4049 }
4050 if (INSN_CODE (curr_insn) >= 0
4051 && (p = get_insn_name (INSN_CODE (curr_insn))) != NULL)
4052 fprintf (lra_dump_file, " {%s}", p);
4053 if (maybe_ne (curr_id->sp_offset, 0))
4054 {
4055 fprintf (lra_dump_file, " (sp_off=");
4056 print_dec (curr_id->sp_offset, lra_dump_file);
4057 fprintf (lra_dump_file, ")");
4058 }
4059 fprintf (lra_dump_file, "\n");
4060 }
4061
4062 /* Right now, for any pair of operands I and J that are required to
4063 match, with J < I, goal_alt_matches[I] is J. Add I to
4064 goal_alt_matched[J]. */
4065
4066 for (i = 0; i < n_operands; i++)
4067 if ((j = goal_alt_matches[i]) >= 0)
4068 {
4069 for (k = 0; goal_alt_matched[j][k] >= 0; k++)
4070 ;
4071 /* We allow matching one output operand and several input
4072 operands. */
4073 lra_assert (k == 0
4074 || (curr_static_id->operand[j].type == OP_OUT
4075 && curr_static_id->operand[i].type == OP_IN
4076 && (curr_static_id->operand
4077 [goal_alt_matched[j][0]].type == OP_IN)));
4078 goal_alt_matched[j][k] = i;
4079 goal_alt_matched[j][k + 1] = -1;
4080 }
4081
4082 for (i = 0; i < n_operands; i++)
4083 goal_alt_win[i] |= goal_alt_match_win[i];
4084
4085 /* Any constants that aren't allowed and can't be reloaded into
4086 registers are here changed into memory references. */
4087 for (i = 0; i < n_operands; i++)
4088 if (goal_alt_win[i])
4089 {
4090 int regno;
4091 enum reg_class new_class;
4092 rtx reg = *curr_id->operand_loc[i];
4093
4094 if (GET_CODE (reg) == SUBREG)
4095 reg = SUBREG_REG (reg);
4096
4097 if (REG_P (reg) && (regno = REGNO (reg)) >= FIRST_PSEUDO_REGISTER)
4098 {
4099 bool ok_p = in_class_p (reg, goal_alt[i], &new_class);
4100
4101 if (new_class != NO_REGS && get_reg_class (regno) != new_class)
4102 {
4103 lra_assert (ok_p);
4104 lra_change_class (regno, new_class, " Change to", true);
4105 }
4106 }
4107 }
4108 else
4109 {
4110 const char *constraint;
4111 char c;
4112 rtx op = *curr_id->operand_loc[i];
4113 rtx subreg = NULL_RTX;
4114 machine_mode mode = curr_operand_mode[i];
4115
4116 if (GET_CODE (op) == SUBREG)
4117 {
4118 subreg = op;
4119 op = SUBREG_REG (op);
4120 mode = GET_MODE (op);
4121 }
4122
4123 if (CONST_POOL_OK_P (mode, op)
4124 && ((targetm.preferred_reload_class
4125 (op, (enum reg_class) goal_alt[i]) == NO_REGS)
4126 || no_input_reloads_p))
4127 {
4128 rtx tem = force_const_mem (mode, op);
4129
4130 change_p = true;
4131 if (subreg != NULL_RTX)
4132 tem = gen_rtx_SUBREG (mode, tem, SUBREG_BYTE (subreg));
4133
4134 *curr_id->operand_loc[i] = tem;
4135 lra_update_dup (curr_id, i);
4136 process_address (i, false, &before, &after);
4137
4138 /* If the alternative accepts constant pool refs directly
4139 there will be no reload needed at all. */
4140 if (subreg != NULL_RTX)
4141 continue;
4142 /* Skip alternatives before the one requested. */
4143 constraint = (curr_static_id->operand_alternative
4144 [goal_alt_number * n_operands + i].constraint);
4145 for (;
4146 (c = *constraint) && c != ',' && c != '#';
4147 constraint += CONSTRAINT_LEN (c, constraint))
4148 {
4149 enum constraint_num cn = lookup_constraint (constraint);
4150 if ((insn_extra_memory_constraint (cn)
4151 || insn_extra_special_memory_constraint (cn))
4152 && satisfies_memory_constraint_p (tem, cn))
4153 break;
4154 }
4155 if (c == '\0' || c == ',' || c == '#')
4156 continue;
4157
4158 goal_alt_win[i] = true;
4159 }
4160 }
4161
4162 n_outputs = 0;
4163 outputs[0] = -1;
4164 for (i = 0; i < n_operands; i++)
4165 {
4166 int regno;
4167 bool optional_p = false;
4168 rtx old, new_reg;
4169 rtx op = *curr_id->operand_loc[i];
4170
4171 if (goal_alt_win[i])
4172 {
4173 if (goal_alt[i] == NO_REGS
4174 && REG_P (op)
4175 /* When we assign NO_REGS it means that we will not
4176 assign a hard register to the scratch pseudo by
4177 assigment pass and the scratch pseudo will be
4178 spilled. Spilled scratch pseudos are transformed
4179 back to scratches at the LRA end. */
4180 && lra_former_scratch_operand_p (curr_insn, i)
4181 && lra_former_scratch_p (REGNO (op)))
4182 {
4183 int regno = REGNO (op);
4184 lra_change_class (regno, NO_REGS, " Change to", true);
4185 if (lra_get_regno_hard_regno (regno) >= 0)
4186 /* We don't have to mark all insn affected by the
4187 spilled pseudo as there is only one such insn, the
4188 current one. */
4189 reg_renumber[regno] = -1;
4190 lra_assert (bitmap_single_bit_set_p
4191 (&lra_reg_info[REGNO (op)].insn_bitmap));
4192 }
4193 /* We can do an optional reload. If the pseudo got a hard
4194 reg, we might improve the code through inheritance. If
4195 it does not get a hard register we coalesce memory/memory
4196 moves later. Ignore move insns to avoid cycling. */
4197 if (! lra_simple_p
4198 && lra_undo_inheritance_iter < LRA_MAX_INHERITANCE_PASSES
4199 && goal_alt[i] != NO_REGS && REG_P (op)
4200 && (regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER
4201 && regno < new_regno_start
4202 && ! lra_former_scratch_p (regno)
4203 && reg_renumber[regno] < 0
4204 /* Check that the optional reload pseudo will be able to
4205 hold given mode value. */
4206 && ! (prohibited_class_reg_set_mode_p
4207 (goal_alt[i], reg_class_contents[goal_alt[i]],
4208 PSEUDO_REGNO_MODE (regno)))
4209 && (curr_insn_set == NULL_RTX
4210 || !((REG_P (SET_SRC (curr_insn_set))
4211 || MEM_P (SET_SRC (curr_insn_set))
4212 || GET_CODE (SET_SRC (curr_insn_set)) == SUBREG)
4213 && (REG_P (SET_DEST (curr_insn_set))
4214 || MEM_P (SET_DEST (curr_insn_set))
4215 || GET_CODE (SET_DEST (curr_insn_set)) == SUBREG))))
4216 optional_p = true;
4217 else
4218 continue;
4219 }
4220
4221 /* Operands that match previous ones have already been handled. */
4222 if (goal_alt_matches[i] >= 0)
4223 continue;
4224
4225 /* We should not have an operand with a non-offsettable address
4226 appearing where an offsettable address will do. It also may
4227 be a case when the address should be special in other words
4228 not a general one (e.g. it needs no index reg). */
4229 if (goal_alt_matched[i][0] == -1 && goal_alt_offmemok[i] && MEM_P (op))
4230 {
4231 enum reg_class rclass;
4232 rtx *loc = &XEXP (op, 0);
4233 enum rtx_code code = GET_CODE (*loc);
4234
4235 push_to_sequence (before);
4236 rclass = base_reg_class (GET_MODE (op), MEM_ADDR_SPACE (op),
4237 MEM, SCRATCH);
4238 if (GET_RTX_CLASS (code) == RTX_AUTOINC)
4239 new_reg = emit_inc (rclass, *loc, *loc,
4240 /* This value does not matter for MODIFY. */
4241 GET_MODE_SIZE (GET_MODE (op)));
4242 else if (get_reload_reg (OP_IN, Pmode, *loc, rclass, FALSE,
4243 "offsetable address", &new_reg))
4244 {
4245 rtx addr = *loc;
4246 enum rtx_code code = GET_CODE (addr);
4247
4248 if (code == AND && CONST_INT_P (XEXP (addr, 1)))
4249 /* (and ... (const_int -X)) is used to align to X bytes. */
4250 addr = XEXP (*loc, 0);
4251 lra_emit_move (new_reg, addr);
4252 if (addr != *loc)
4253 emit_move_insn (new_reg, gen_rtx_AND (GET_MODE (new_reg), new_reg, XEXP (*loc, 1)));
4254 }
4255 before = get_insns ();
4256 end_sequence ();
4257 *loc = new_reg;
4258 lra_update_dup (curr_id, i);
4259 }
4260 else if (goal_alt_matched[i][0] == -1)
4261 {
4262 machine_mode mode;
4263 rtx reg, *loc;
4264 int hard_regno;
4265 enum op_type type = curr_static_id->operand[i].type;
4266
4267 loc = curr_id->operand_loc[i];
4268 mode = curr_operand_mode[i];
4269 if (GET_CODE (*loc) == SUBREG)
4270 {
4271 reg = SUBREG_REG (*loc);
4272 poly_int64 byte = SUBREG_BYTE (*loc);
4273 if (REG_P (reg)
4274 /* Strict_low_part requires reloading the register and not
4275 just the subreg. Likewise for a strict subreg no wider
4276 than a word for WORD_REGISTER_OPERATIONS targets. */
4277 && (curr_static_id->operand[i].strict_low
4278 || (!paradoxical_subreg_p (mode, GET_MODE (reg))
4279 && (hard_regno
4280 = get_try_hard_regno (REGNO (reg))) >= 0
4281 && (simplify_subreg_regno
4282 (hard_regno,
4283 GET_MODE (reg), byte, mode) < 0)
4284 && (goal_alt[i] == NO_REGS
4285 || (simplify_subreg_regno
4286 (ira_class_hard_regs[goal_alt[i]][0],
4287 GET_MODE (reg), byte, mode) >= 0)))
4288 || (partial_subreg_p (mode, GET_MODE (reg))
4289 && known_le (GET_MODE_SIZE (GET_MODE (reg)),
4290 UNITS_PER_WORD)
4291 && WORD_REGISTER_OPERATIONS)))
4292 {
4293 /* An OP_INOUT is required when reloading a subreg of a
4294 mode wider than a word to ensure that data beyond the
4295 word being reloaded is preserved. Also automatically
4296 ensure that strict_low_part reloads are made into
4297 OP_INOUT which should already be true from the backend
4298 constraints. */
4299 if (type == OP_OUT
4300 && (curr_static_id->operand[i].strict_low
4301 || read_modify_subreg_p (*loc)))
4302 type = OP_INOUT;
4303 loc = &SUBREG_REG (*loc);
4304 mode = GET_MODE (*loc);
4305 }
4306 }
4307 old = *loc;
4308 if (get_reload_reg (type, mode, old, goal_alt[i],
4309 loc != curr_id->operand_loc[i], "", &new_reg)
4310 && type != OP_OUT)
4311 {
4312 push_to_sequence (before);
4313 lra_emit_move (new_reg, old);
4314 before = get_insns ();
4315 end_sequence ();
4316 }
4317 *loc = new_reg;
4318 if (type != OP_IN
4319 && find_reg_note (curr_insn, REG_UNUSED, old) == NULL_RTX)
4320 {
4321 start_sequence ();
4322 lra_emit_move (type == OP_INOUT ? copy_rtx (old) : old, new_reg);
4323 emit_insn (after);
4324 after = get_insns ();
4325 end_sequence ();
4326 *loc = new_reg;
4327 }
4328 for (j = 0; j < goal_alt_dont_inherit_ops_num; j++)
4329 if (goal_alt_dont_inherit_ops[j] == i)
4330 {
4331 lra_set_regno_unique_value (REGNO (new_reg));
4332 break;
4333 }
4334 lra_update_dup (curr_id, i);
4335 }
4336 else if (curr_static_id->operand[i].type == OP_IN
4337 && (curr_static_id->operand[goal_alt_matched[i][0]].type
4338 == OP_OUT
4339 || (curr_static_id->operand[goal_alt_matched[i][0]].type
4340 == OP_INOUT
4341 && (operands_match_p
4342 (*curr_id->operand_loc[i],
4343 *curr_id->operand_loc[goal_alt_matched[i][0]],
4344 -1)))))
4345 {
4346 /* generate reloads for input and matched outputs. */
4347 match_inputs[0] = i;
4348 match_inputs[1] = -1;
4349 match_reload (goal_alt_matched[i][0], match_inputs, outputs,
4350 goal_alt[i], &before, &after,
4351 curr_static_id->operand_alternative
4352 [goal_alt_number * n_operands + goal_alt_matched[i][0]]
4353 .earlyclobber);
4354 }
4355 else if ((curr_static_id->operand[i].type == OP_OUT
4356 || (curr_static_id->operand[i].type == OP_INOUT
4357 && (operands_match_p
4358 (*curr_id->operand_loc[i],
4359 *curr_id->operand_loc[goal_alt_matched[i][0]],
4360 -1))))
4361 && (curr_static_id->operand[goal_alt_matched[i][0]].type
4362 == OP_IN))
4363 /* Generate reloads for output and matched inputs. */
4364 match_reload (i, goal_alt_matched[i], outputs, goal_alt[i], &before,
4365 &after, curr_static_id->operand_alternative
4366 [goal_alt_number * n_operands + i].earlyclobber);
4367 else if (curr_static_id->operand[i].type == OP_IN
4368 && (curr_static_id->operand[goal_alt_matched[i][0]].type
4369 == OP_IN))
4370 {
4371 /* Generate reloads for matched inputs. */
4372 match_inputs[0] = i;
4373 for (j = 0; (k = goal_alt_matched[i][j]) >= 0; j++)
4374 match_inputs[j + 1] = k;
4375 match_inputs[j + 1] = -1;
4376 match_reload (-1, match_inputs, outputs, goal_alt[i], &before,
4377 &after, false);
4378 }
4379 else
4380 /* We must generate code in any case when function
4381 process_alt_operands decides that it is possible. */
4382 gcc_unreachable ();
4383
4384 /* Memorise processed outputs so that output remaining to be processed
4385 can avoid using the same register value (see match_reload). */
4386 if (curr_static_id->operand[i].type == OP_OUT)
4387 {
4388 outputs[n_outputs++] = i;
4389 outputs[n_outputs] = -1;
4390 }
4391
4392 if (optional_p)
4393 {
4394 rtx reg = op;
4395
4396 lra_assert (REG_P (reg));
4397 regno = REGNO (reg);
4398 op = *curr_id->operand_loc[i]; /* Substitution. */
4399 if (GET_CODE (op) == SUBREG)
4400 op = SUBREG_REG (op);
4401 gcc_assert (REG_P (op) && (int) REGNO (op) >= new_regno_start);
4402 bitmap_set_bit (&lra_optional_reload_pseudos, REGNO (op));
4403 lra_reg_info[REGNO (op)].restore_rtx = reg;
4404 if (lra_dump_file != NULL)
4405 fprintf (lra_dump_file,
4406 " Making reload reg %d for reg %d optional\n",
4407 REGNO (op), regno);
4408 }
4409 }
4410 if (before != NULL_RTX || after != NULL_RTX
4411 || max_regno_before != max_reg_num ())
4412 change_p = true;
4413 if (change_p)
4414 {
4415 lra_update_operator_dups (curr_id);
4416 /* Something changes -- process the insn. */
4417 lra_update_insn_regno_info (curr_insn);
4418 }
4419 lra_process_new_insns (curr_insn, before, after, "Inserting insn reload");
4420 return change_p;
4421 }
4422
4423 /* Return true if INSN satisfies all constraints. In other words, no
4424 reload insns are needed. */
4425 bool
lra_constrain_insn(rtx_insn * insn)4426 lra_constrain_insn (rtx_insn *insn)
4427 {
4428 int saved_new_regno_start = new_regno_start;
4429 int saved_new_insn_uid_start = new_insn_uid_start;
4430 bool change_p;
4431
4432 curr_insn = insn;
4433 curr_id = lra_get_insn_recog_data (curr_insn);
4434 curr_static_id = curr_id->insn_static_data;
4435 new_insn_uid_start = get_max_uid ();
4436 new_regno_start = max_reg_num ();
4437 change_p = curr_insn_transform (true);
4438 new_regno_start = saved_new_regno_start;
4439 new_insn_uid_start = saved_new_insn_uid_start;
4440 return ! change_p;
4441 }
4442
4443 /* Return true if X is in LIST. */
4444 static bool
in_list_p(rtx x,rtx list)4445 in_list_p (rtx x, rtx list)
4446 {
4447 for (; list != NULL_RTX; list = XEXP (list, 1))
4448 if (XEXP (list, 0) == x)
4449 return true;
4450 return false;
4451 }
4452
4453 /* Return true if X contains an allocatable hard register (if
4454 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
4455 static bool
contains_reg_p(rtx x,bool hard_reg_p,bool spilled_p)4456 contains_reg_p (rtx x, bool hard_reg_p, bool spilled_p)
4457 {
4458 int i, j;
4459 const char *fmt;
4460 enum rtx_code code;
4461
4462 code = GET_CODE (x);
4463 if (REG_P (x))
4464 {
4465 int regno = REGNO (x);
4466 HARD_REG_SET alloc_regs;
4467
4468 if (hard_reg_p)
4469 {
4470 if (regno >= FIRST_PSEUDO_REGISTER)
4471 regno = lra_get_regno_hard_regno (regno);
4472 if (regno < 0)
4473 return false;
4474 COMPL_HARD_REG_SET (alloc_regs, lra_no_alloc_regs);
4475 return overlaps_hard_reg_set_p (alloc_regs, GET_MODE (x), regno);
4476 }
4477 else
4478 {
4479 if (regno < FIRST_PSEUDO_REGISTER)
4480 return false;
4481 if (! spilled_p)
4482 return true;
4483 return lra_get_regno_hard_regno (regno) < 0;
4484 }
4485 }
4486 fmt = GET_RTX_FORMAT (code);
4487 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4488 {
4489 if (fmt[i] == 'e')
4490 {
4491 if (contains_reg_p (XEXP (x, i), hard_reg_p, spilled_p))
4492 return true;
4493 }
4494 else if (fmt[i] == 'E')
4495 {
4496 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4497 if (contains_reg_p (XVECEXP (x, i, j), hard_reg_p, spilled_p))
4498 return true;
4499 }
4500 }
4501 return false;
4502 }
4503
4504 /* Process all regs in location *LOC and change them on equivalent
4505 substitution. Return true if any change was done. */
4506 static bool
loc_equivalence_change_p(rtx * loc)4507 loc_equivalence_change_p (rtx *loc)
4508 {
4509 rtx subst, reg, x = *loc;
4510 bool result = false;
4511 enum rtx_code code = GET_CODE (x);
4512 const char *fmt;
4513 int i, j;
4514
4515 if (code == SUBREG)
4516 {
4517 reg = SUBREG_REG (x);
4518 if ((subst = get_equiv_with_elimination (reg, curr_insn)) != reg
4519 && GET_MODE (subst) == VOIDmode)
4520 {
4521 /* We cannot reload debug location. Simplify subreg here
4522 while we know the inner mode. */
4523 *loc = simplify_gen_subreg (GET_MODE (x), subst,
4524 GET_MODE (reg), SUBREG_BYTE (x));
4525 return true;
4526 }
4527 }
4528 if (code == REG && (subst = get_equiv_with_elimination (x, curr_insn)) != x)
4529 {
4530 *loc = subst;
4531 return true;
4532 }
4533
4534 /* Scan all the operand sub-expressions. */
4535 fmt = GET_RTX_FORMAT (code);
4536 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4537 {
4538 if (fmt[i] == 'e')
4539 result = loc_equivalence_change_p (&XEXP (x, i)) || result;
4540 else if (fmt[i] == 'E')
4541 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4542 result
4543 = loc_equivalence_change_p (&XVECEXP (x, i, j)) || result;
4544 }
4545 return result;
4546 }
4547
4548 /* Similar to loc_equivalence_change_p, but for use as
4549 simplify_replace_fn_rtx callback. DATA is insn for which the
4550 elimination is done. If it null we don't do the elimination. */
4551 static rtx
loc_equivalence_callback(rtx loc,const_rtx,void * data)4552 loc_equivalence_callback (rtx loc, const_rtx, void *data)
4553 {
4554 if (!REG_P (loc))
4555 return NULL_RTX;
4556
4557 rtx subst = (data == NULL
4558 ? get_equiv (loc) : get_equiv_with_elimination (loc, (rtx_insn *) data));
4559 if (subst != loc)
4560 return subst;
4561
4562 return NULL_RTX;
4563 }
4564
4565 /* Maximum number of generated reload insns per an insn. It is for
4566 preventing this pass cycling in a bug case. */
4567 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
4568
4569 /* The current iteration number of this LRA pass. */
4570 int lra_constraint_iter;
4571
4572 /* True if we substituted equiv which needs checking register
4573 allocation correctness because the equivalent value contains
4574 allocatable hard registers or when we restore multi-register
4575 pseudo. */
4576 bool lra_risky_transformations_p;
4577
4578 /* Return true if REGNO is referenced in more than one block. */
4579 static bool
multi_block_pseudo_p(int regno)4580 multi_block_pseudo_p (int regno)
4581 {
4582 basic_block bb = NULL;
4583 unsigned int uid;
4584 bitmap_iterator bi;
4585
4586 if (regno < FIRST_PSEUDO_REGISTER)
4587 return false;
4588
4589 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi)
4590 if (bb == NULL)
4591 bb = BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn);
4592 else if (BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn) != bb)
4593 return true;
4594 return false;
4595 }
4596
4597 /* Return true if LIST contains a deleted insn. */
4598 static bool
contains_deleted_insn_p(rtx_insn_list * list)4599 contains_deleted_insn_p (rtx_insn_list *list)
4600 {
4601 for (; list != NULL_RTX; list = list->next ())
4602 if (NOTE_P (list->insn ())
4603 && NOTE_KIND (list->insn ()) == NOTE_INSN_DELETED)
4604 return true;
4605 return false;
4606 }
4607
4608 /* Return true if X contains a pseudo dying in INSN. */
4609 static bool
dead_pseudo_p(rtx x,rtx_insn * insn)4610 dead_pseudo_p (rtx x, rtx_insn *insn)
4611 {
4612 int i, j;
4613 const char *fmt;
4614 enum rtx_code code;
4615
4616 if (REG_P (x))
4617 return (insn != NULL_RTX
4618 && find_regno_note (insn, REG_DEAD, REGNO (x)) != NULL_RTX);
4619 code = GET_CODE (x);
4620 fmt = GET_RTX_FORMAT (code);
4621 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4622 {
4623 if (fmt[i] == 'e')
4624 {
4625 if (dead_pseudo_p (XEXP (x, i), insn))
4626 return true;
4627 }
4628 else if (fmt[i] == 'E')
4629 {
4630 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4631 if (dead_pseudo_p (XVECEXP (x, i, j), insn))
4632 return true;
4633 }
4634 }
4635 return false;
4636 }
4637
4638 /* Return true if INSN contains a dying pseudo in INSN right hand
4639 side. */
4640 static bool
insn_rhs_dead_pseudo_p(rtx_insn * insn)4641 insn_rhs_dead_pseudo_p (rtx_insn *insn)
4642 {
4643 rtx set = single_set (insn);
4644
4645 gcc_assert (set != NULL);
4646 return dead_pseudo_p (SET_SRC (set), insn);
4647 }
4648
4649 /* Return true if any init insn of REGNO contains a dying pseudo in
4650 insn right hand side. */
4651 static bool
init_insn_rhs_dead_pseudo_p(int regno)4652 init_insn_rhs_dead_pseudo_p (int regno)
4653 {
4654 rtx_insn_list *insns = ira_reg_equiv[regno].init_insns;
4655
4656 if (insns == NULL)
4657 return false;
4658 for (; insns != NULL_RTX; insns = insns->next ())
4659 if (insn_rhs_dead_pseudo_p (insns->insn ()))
4660 return true;
4661 return false;
4662 }
4663
4664 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
4665 reverse only if we have one init insn with given REGNO as a
4666 source. */
4667 static bool
reverse_equiv_p(int regno)4668 reverse_equiv_p (int regno)
4669 {
4670 rtx_insn_list *insns = ira_reg_equiv[regno].init_insns;
4671 rtx set;
4672
4673 if (insns == NULL)
4674 return false;
4675 if (! INSN_P (insns->insn ())
4676 || insns->next () != NULL)
4677 return false;
4678 if ((set = single_set (insns->insn ())) == NULL_RTX)
4679 return false;
4680 return REG_P (SET_SRC (set)) && (int) REGNO (SET_SRC (set)) == regno;
4681 }
4682
4683 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
4684 call this function only for non-reverse equivalence. */
4685 static bool
contains_reloaded_insn_p(int regno)4686 contains_reloaded_insn_p (int regno)
4687 {
4688 rtx set;
4689 rtx_insn_list *list = ira_reg_equiv[regno].init_insns;
4690
4691 for (; list != NULL; list = list->next ())
4692 if ((set = single_set (list->insn ())) == NULL_RTX
4693 || ! REG_P (SET_DEST (set))
4694 || (int) REGNO (SET_DEST (set)) != regno)
4695 return true;
4696 return false;
4697 }
4698
4699 /* Entry function of LRA constraint pass. Return true if the
4700 constraint pass did change the code. */
4701 bool
lra_constraints(bool first_p)4702 lra_constraints (bool first_p)
4703 {
4704 bool changed_p;
4705 int i, hard_regno, new_insns_num;
4706 unsigned int min_len, new_min_len, uid;
4707 rtx set, x, reg, dest_reg;
4708 basic_block last_bb;
4709 bitmap_iterator bi;
4710
4711 lra_constraint_iter++;
4712 if (lra_dump_file != NULL)
4713 fprintf (lra_dump_file, "\n********** Local #%d: **********\n\n",
4714 lra_constraint_iter);
4715 changed_p = false;
4716 if (pic_offset_table_rtx
4717 && REGNO (pic_offset_table_rtx) >= FIRST_PSEUDO_REGISTER)
4718 lra_risky_transformations_p = true;
4719 else
4720 /* On the first iteration we should check IRA assignment
4721 correctness. In rare cases, the assignments can be wrong as
4722 early clobbers operands are ignored in IRA. */
4723 lra_risky_transformations_p = first_p;
4724 new_insn_uid_start = get_max_uid ();
4725 new_regno_start = first_p ? lra_constraint_new_regno_start : max_reg_num ();
4726 /* Mark used hard regs for target stack size calulations. */
4727 for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++)
4728 if (lra_reg_info[i].nrefs != 0
4729 && (hard_regno = lra_get_regno_hard_regno (i)) >= 0)
4730 {
4731 int j, nregs;
4732
4733 nregs = hard_regno_nregs (hard_regno, lra_reg_info[i].biggest_mode);
4734 for (j = 0; j < nregs; j++)
4735 df_set_regs_ever_live (hard_regno + j, true);
4736 }
4737 /* Do elimination before the equivalence processing as we can spill
4738 some pseudos during elimination. */
4739 lra_eliminate (false, first_p);
4740 auto_bitmap equiv_insn_bitmap (®_obstack);
4741 for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++)
4742 if (lra_reg_info[i].nrefs != 0)
4743 {
4744 ira_reg_equiv[i].profitable_p = true;
4745 reg = regno_reg_rtx[i];
4746 if (lra_get_regno_hard_regno (i) < 0 && (x = get_equiv (reg)) != reg)
4747 {
4748 bool pseudo_p = contains_reg_p (x, false, false);
4749
4750 /* After RTL transformation, we can not guarantee that
4751 pseudo in the substitution was not reloaded which might
4752 make equivalence invalid. For example, in reverse
4753 equiv of p0
4754
4755 p0 <- ...
4756 ...
4757 equiv_mem <- p0
4758
4759 the memory address register was reloaded before the 2nd
4760 insn. */
4761 if ((! first_p && pseudo_p)
4762 /* We don't use DF for compilation speed sake. So it
4763 is problematic to update live info when we use an
4764 equivalence containing pseudos in more than one
4765 BB. */
4766 || (pseudo_p && multi_block_pseudo_p (i))
4767 /* If an init insn was deleted for some reason, cancel
4768 the equiv. We could update the equiv insns after
4769 transformations including an equiv insn deletion
4770 but it is not worthy as such cases are extremely
4771 rare. */
4772 || contains_deleted_insn_p (ira_reg_equiv[i].init_insns)
4773 /* If it is not a reverse equivalence, we check that a
4774 pseudo in rhs of the init insn is not dying in the
4775 insn. Otherwise, the live info at the beginning of
4776 the corresponding BB might be wrong after we
4777 removed the insn. When the equiv can be a
4778 constant, the right hand side of the init insn can
4779 be a pseudo. */
4780 || (! reverse_equiv_p (i)
4781 && (init_insn_rhs_dead_pseudo_p (i)
4782 /* If we reloaded the pseudo in an equivalence
4783 init insn, we can not remove the equiv init
4784 insns and the init insns might write into
4785 const memory in this case. */
4786 || contains_reloaded_insn_p (i)))
4787 /* Prevent access beyond equivalent memory for
4788 paradoxical subregs. */
4789 || (MEM_P (x)
4790 && maybe_gt (GET_MODE_SIZE (lra_reg_info[i].biggest_mode),
4791 GET_MODE_SIZE (GET_MODE (x))))
4792 || (pic_offset_table_rtx
4793 && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i), x)
4794 && (targetm.preferred_reload_class
4795 (x, lra_get_allocno_class (i)) == NO_REGS))
4796 || contains_symbol_ref_p (x))))
4797 ira_reg_equiv[i].defined_p = false;
4798 if (contains_reg_p (x, false, true))
4799 ira_reg_equiv[i].profitable_p = false;
4800 if (get_equiv (reg) != reg)
4801 bitmap_ior_into (equiv_insn_bitmap, &lra_reg_info[i].insn_bitmap);
4802 }
4803 }
4804 for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++)
4805 update_equiv (i);
4806 /* We should add all insns containing pseudos which should be
4807 substituted by their equivalences. */
4808 EXECUTE_IF_SET_IN_BITMAP (equiv_insn_bitmap, 0, uid, bi)
4809 lra_push_insn_by_uid (uid);
4810 min_len = lra_insn_stack_length ();
4811 new_insns_num = 0;
4812 last_bb = NULL;
4813 changed_p = false;
4814 while ((new_min_len = lra_insn_stack_length ()) != 0)
4815 {
4816 curr_insn = lra_pop_insn ();
4817 --new_min_len;
4818 curr_bb = BLOCK_FOR_INSN (curr_insn);
4819 if (curr_bb != last_bb)
4820 {
4821 last_bb = curr_bb;
4822 bb_reload_num = lra_curr_reload_num;
4823 }
4824 if (min_len > new_min_len)
4825 {
4826 min_len = new_min_len;
4827 new_insns_num = 0;
4828 }
4829 if (new_insns_num > MAX_RELOAD_INSNS_NUMBER)
4830 internal_error
4831 ("Max. number of generated reload insns per insn is achieved (%d)\n",
4832 MAX_RELOAD_INSNS_NUMBER);
4833 new_insns_num++;
4834 if (DEBUG_INSN_P (curr_insn))
4835 {
4836 /* We need to check equivalence in debug insn and change
4837 pseudo to the equivalent value if necessary. */
4838 curr_id = lra_get_insn_recog_data (curr_insn);
4839 if (bitmap_bit_p (equiv_insn_bitmap, INSN_UID (curr_insn)))
4840 {
4841 rtx old = *curr_id->operand_loc[0];
4842 *curr_id->operand_loc[0]
4843 = simplify_replace_fn_rtx (old, NULL_RTX,
4844 loc_equivalence_callback, curr_insn);
4845 if (old != *curr_id->operand_loc[0])
4846 {
4847 lra_update_insn_regno_info (curr_insn);
4848 changed_p = true;
4849 }
4850 }
4851 }
4852 else if (INSN_P (curr_insn))
4853 {
4854 if ((set = single_set (curr_insn)) != NULL_RTX)
4855 {
4856 dest_reg = SET_DEST (set);
4857 /* The equivalence pseudo could be set up as SUBREG in a
4858 case when it is a call restore insn in a mode
4859 different from the pseudo mode. */
4860 if (GET_CODE (dest_reg) == SUBREG)
4861 dest_reg = SUBREG_REG (dest_reg);
4862 if ((REG_P (dest_reg)
4863 && (x = get_equiv (dest_reg)) != dest_reg
4864 /* Remove insns which set up a pseudo whose value
4865 can not be changed. Such insns might be not in
4866 init_insns because we don't update equiv data
4867 during insn transformations.
4868
4869 As an example, let suppose that a pseudo got
4870 hard register and on the 1st pass was not
4871 changed to equivalent constant. We generate an
4872 additional insn setting up the pseudo because of
4873 secondary memory movement. Then the pseudo is
4874 spilled and we use the equiv constant. In this
4875 case we should remove the additional insn and
4876 this insn is not init_insns list. */
4877 && (! MEM_P (x) || MEM_READONLY_P (x)
4878 /* Check that this is actually an insn setting
4879 up the equivalence. */
4880 || in_list_p (curr_insn,
4881 ira_reg_equiv
4882 [REGNO (dest_reg)].init_insns)))
4883 || (((x = get_equiv (SET_SRC (set))) != SET_SRC (set))
4884 && in_list_p (curr_insn,
4885 ira_reg_equiv
4886 [REGNO (SET_SRC (set))].init_insns)))
4887 {
4888 /* This is equiv init insn of pseudo which did not get a
4889 hard register -- remove the insn. */
4890 if (lra_dump_file != NULL)
4891 {
4892 fprintf (lra_dump_file,
4893 " Removing equiv init insn %i (freq=%d)\n",
4894 INSN_UID (curr_insn),
4895 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn)));
4896 dump_insn_slim (lra_dump_file, curr_insn);
4897 }
4898 if (contains_reg_p (x, true, false))
4899 lra_risky_transformations_p = true;
4900 lra_set_insn_deleted (curr_insn);
4901 continue;
4902 }
4903 }
4904 curr_id = lra_get_insn_recog_data (curr_insn);
4905 curr_static_id = curr_id->insn_static_data;
4906 init_curr_insn_input_reloads ();
4907 init_curr_operand_mode ();
4908 if (curr_insn_transform (false))
4909 changed_p = true;
4910 /* Check non-transformed insns too for equiv change as USE
4911 or CLOBBER don't need reloads but can contain pseudos
4912 being changed on their equivalences. */
4913 else if (bitmap_bit_p (equiv_insn_bitmap, INSN_UID (curr_insn))
4914 && loc_equivalence_change_p (&PATTERN (curr_insn)))
4915 {
4916 lra_update_insn_regno_info (curr_insn);
4917 changed_p = true;
4918 }
4919 }
4920 }
4921
4922 /* If we used a new hard regno, changed_p should be true because the
4923 hard reg is assigned to a new pseudo. */
4924 if (flag_checking && !changed_p)
4925 {
4926 for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++)
4927 if (lra_reg_info[i].nrefs != 0
4928 && (hard_regno = lra_get_regno_hard_regno (i)) >= 0)
4929 {
4930 int j, nregs = hard_regno_nregs (hard_regno,
4931 PSEUDO_REGNO_MODE (i));
4932
4933 for (j = 0; j < nregs; j++)
4934 lra_assert (df_regs_ever_live_p (hard_regno + j));
4935 }
4936 }
4937 return changed_p;
4938 }
4939
4940 static void initiate_invariants (void);
4941 static void finish_invariants (void);
4942
4943 /* Initiate the LRA constraint pass. It is done once per
4944 function. */
4945 void
lra_constraints_init(void)4946 lra_constraints_init (void)
4947 {
4948 initiate_invariants ();
4949 }
4950
4951 /* Finalize the LRA constraint pass. It is done once per
4952 function. */
4953 void
lra_constraints_finish(void)4954 lra_constraints_finish (void)
4955 {
4956 finish_invariants ();
4957 }
4958
4959
4960
4961 /* Structure describes invariants for ineheritance. */
4962 struct lra_invariant
4963 {
4964 /* The order number of the invariant. */
4965 int num;
4966 /* The invariant RTX. */
4967 rtx invariant_rtx;
4968 /* The origin insn of the invariant. */
4969 rtx_insn *insn;
4970 };
4971
4972 typedef lra_invariant invariant_t;
4973 typedef invariant_t *invariant_ptr_t;
4974 typedef const invariant_t *const_invariant_ptr_t;
4975
4976 /* Pointer to the inheritance invariants. */
4977 static vec<invariant_ptr_t> invariants;
4978
4979 /* Allocation pool for the invariants. */
4980 static object_allocator<lra_invariant> *invariants_pool;
4981
4982 /* Hash table for the invariants. */
4983 static htab_t invariant_table;
4984
4985 /* Hash function for INVARIANT. */
4986 static hashval_t
invariant_hash(const void * invariant)4987 invariant_hash (const void *invariant)
4988 {
4989 rtx inv = ((const_invariant_ptr_t) invariant)->invariant_rtx;
4990 return lra_rtx_hash (inv);
4991 }
4992
4993 /* Equal function for invariants INVARIANT1 and INVARIANT2. */
4994 static int
invariant_eq_p(const void * invariant1,const void * invariant2)4995 invariant_eq_p (const void *invariant1, const void *invariant2)
4996 {
4997 rtx inv1 = ((const_invariant_ptr_t) invariant1)->invariant_rtx;
4998 rtx inv2 = ((const_invariant_ptr_t) invariant2)->invariant_rtx;
4999
5000 return rtx_equal_p (inv1, inv2);
5001 }
5002
5003 /* Insert INVARIANT_RTX into the table if it is not there yet. Return
5004 invariant which is in the table. */
5005 static invariant_ptr_t
insert_invariant(rtx invariant_rtx)5006 insert_invariant (rtx invariant_rtx)
5007 {
5008 void **entry_ptr;
5009 invariant_t invariant;
5010 invariant_ptr_t invariant_ptr;
5011
5012 invariant.invariant_rtx = invariant_rtx;
5013 entry_ptr = htab_find_slot (invariant_table, &invariant, INSERT);
5014 if (*entry_ptr == NULL)
5015 {
5016 invariant_ptr = invariants_pool->allocate ();
5017 invariant_ptr->invariant_rtx = invariant_rtx;
5018 invariant_ptr->insn = NULL;
5019 invariants.safe_push (invariant_ptr);
5020 *entry_ptr = (void *) invariant_ptr;
5021 }
5022 return (invariant_ptr_t) *entry_ptr;
5023 }
5024
5025 /* Initiate the invariant table. */
5026 static void
initiate_invariants(void)5027 initiate_invariants (void)
5028 {
5029 invariants.create (100);
5030 invariants_pool
5031 = new object_allocator<lra_invariant> ("Inheritance invariants");
5032 invariant_table = htab_create (100, invariant_hash, invariant_eq_p, NULL);
5033 }
5034
5035 /* Finish the invariant table. */
5036 static void
finish_invariants(void)5037 finish_invariants (void)
5038 {
5039 htab_delete (invariant_table);
5040 delete invariants_pool;
5041 invariants.release ();
5042 }
5043
5044 /* Make the invariant table empty. */
5045 static void
clear_invariants(void)5046 clear_invariants (void)
5047 {
5048 htab_empty (invariant_table);
5049 invariants_pool->release ();
5050 invariants.truncate (0);
5051 }
5052
5053
5054
5055 /* This page contains code to do inheritance/split
5056 transformations. */
5057
5058 /* Number of reloads passed so far in current EBB. */
5059 static int reloads_num;
5060
5061 /* Number of calls passed so far in current EBB. */
5062 static int calls_num;
5063
5064 /* Current reload pseudo check for validity of elements in
5065 USAGE_INSNS. */
5066 static int curr_usage_insns_check;
5067
5068 /* Info about last usage of registers in EBB to do inheritance/split
5069 transformation. Inheritance transformation is done from a spilled
5070 pseudo and split transformations from a hard register or a pseudo
5071 assigned to a hard register. */
5072 struct usage_insns
5073 {
5074 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
5075 value INSNS is valid. The insns is chain of optional debug insns
5076 and a finishing non-debug insn using the corresponding reg. The
5077 value is also used to mark the registers which are set up in the
5078 current insn. The negated insn uid is used for this. */
5079 int check;
5080 /* Value of global reloads_num at the last insn in INSNS. */
5081 int reloads_num;
5082 /* Value of global reloads_nums at the last insn in INSNS. */
5083 int calls_num;
5084 /* It can be true only for splitting. And it means that the restore
5085 insn should be put after insn given by the following member. */
5086 bool after_p;
5087 /* Next insns in the current EBB which use the original reg and the
5088 original reg value is not changed between the current insn and
5089 the next insns. In order words, e.g. for inheritance, if we need
5090 to use the original reg value again in the next insns we can try
5091 to use the value in a hard register from a reload insn of the
5092 current insn. */
5093 rtx insns;
5094 };
5095
5096 /* Map: regno -> corresponding pseudo usage insns. */
5097 static struct usage_insns *usage_insns;
5098
5099 static void
setup_next_usage_insn(int regno,rtx insn,int reloads_num,bool after_p)5100 setup_next_usage_insn (int regno, rtx insn, int reloads_num, bool after_p)
5101 {
5102 usage_insns[regno].check = curr_usage_insns_check;
5103 usage_insns[regno].insns = insn;
5104 usage_insns[regno].reloads_num = reloads_num;
5105 usage_insns[regno].calls_num = calls_num;
5106 usage_insns[regno].after_p = after_p;
5107 }
5108
5109 /* The function is used to form list REGNO usages which consists of
5110 optional debug insns finished by a non-debug insn using REGNO.
5111 RELOADS_NUM is current number of reload insns processed so far. */
5112 static void
add_next_usage_insn(int regno,rtx_insn * insn,int reloads_num)5113 add_next_usage_insn (int regno, rtx_insn *insn, int reloads_num)
5114 {
5115 rtx next_usage_insns;
5116
5117 if (usage_insns[regno].check == curr_usage_insns_check
5118 && (next_usage_insns = usage_insns[regno].insns) != NULL_RTX
5119 && DEBUG_INSN_P (insn))
5120 {
5121 /* Check that we did not add the debug insn yet. */
5122 if (next_usage_insns != insn
5123 && (GET_CODE (next_usage_insns) != INSN_LIST
5124 || XEXP (next_usage_insns, 0) != insn))
5125 usage_insns[regno].insns = gen_rtx_INSN_LIST (VOIDmode, insn,
5126 next_usage_insns);
5127 }
5128 else if (NONDEBUG_INSN_P (insn))
5129 setup_next_usage_insn (regno, insn, reloads_num, false);
5130 else
5131 usage_insns[regno].check = 0;
5132 }
5133
5134 /* Return first non-debug insn in list USAGE_INSNS. */
5135 static rtx_insn *
skip_usage_debug_insns(rtx usage_insns)5136 skip_usage_debug_insns (rtx usage_insns)
5137 {
5138 rtx insn;
5139
5140 /* Skip debug insns. */
5141 for (insn = usage_insns;
5142 insn != NULL_RTX && GET_CODE (insn) == INSN_LIST;
5143 insn = XEXP (insn, 1))
5144 ;
5145 return safe_as_a <rtx_insn *> (insn);
5146 }
5147
5148 /* Return true if we need secondary memory moves for insn in
5149 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
5150 into the insn. */
5151 static bool
check_secondary_memory_needed_p(enum reg_class inher_cl ATTRIBUTE_UNUSED,rtx usage_insns ATTRIBUTE_UNUSED)5152 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED,
5153 rtx usage_insns ATTRIBUTE_UNUSED)
5154 {
5155 rtx_insn *insn;
5156 rtx set, dest;
5157 enum reg_class cl;
5158
5159 if (inher_cl == ALL_REGS
5160 || (insn = skip_usage_debug_insns (usage_insns)) == NULL_RTX)
5161 return false;
5162 lra_assert (INSN_P (insn));
5163 if ((set = single_set (insn)) == NULL_RTX || ! REG_P (SET_DEST (set)))
5164 return false;
5165 dest = SET_DEST (set);
5166 if (! REG_P (dest))
5167 return false;
5168 lra_assert (inher_cl != NO_REGS);
5169 cl = get_reg_class (REGNO (dest));
5170 return (cl != NO_REGS && cl != ALL_REGS
5171 && targetm.secondary_memory_needed (GET_MODE (dest), inher_cl, cl));
5172 }
5173
5174 /* Registers involved in inheritance/split in the current EBB
5175 (inheritance/split pseudos and original registers). */
5176 static bitmap_head check_only_regs;
5177
5178 /* Reload pseudos can not be involded in invariant inheritance in the
5179 current EBB. */
5180 static bitmap_head invalid_invariant_regs;
5181
5182 /* Do inheritance transformations for insn INSN, which defines (if
5183 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
5184 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
5185 form as the "insns" field of usage_insns. Return true if we
5186 succeed in such transformation.
5187
5188 The transformations look like:
5189
5190 p <- ... i <- ...
5191 ... p <- i (new insn)
5192 ... =>
5193 <- ... p ... <- ... i ...
5194 or
5195 ... i <- p (new insn)
5196 <- ... p ... <- ... i ...
5197 ... =>
5198 <- ... p ... <- ... i ...
5199 where p is a spilled original pseudo and i is a new inheritance pseudo.
5200
5201
5202 The inheritance pseudo has the smallest class of two classes CL and
5203 class of ORIGINAL REGNO. */
5204 static bool
inherit_reload_reg(bool def_p,int original_regno,enum reg_class cl,rtx_insn * insn,rtx next_usage_insns)5205 inherit_reload_reg (bool def_p, int original_regno,
5206 enum reg_class cl, rtx_insn *insn, rtx next_usage_insns)
5207 {
5208 if (optimize_function_for_size_p (cfun))
5209 return false;
5210
5211 enum reg_class rclass = lra_get_allocno_class (original_regno);
5212 rtx original_reg = regno_reg_rtx[original_regno];
5213 rtx new_reg, usage_insn;
5214 rtx_insn *new_insns;
5215
5216 lra_assert (! usage_insns[original_regno].after_p);
5217 if (lra_dump_file != NULL)
5218 fprintf (lra_dump_file,
5219 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
5220 if (! ira_reg_classes_intersect_p[cl][rclass])
5221 {
5222 if (lra_dump_file != NULL)
5223 {
5224 fprintf (lra_dump_file,
5225 " Rejecting inheritance for %d "
5226 "because of disjoint classes %s and %s\n",
5227 original_regno, reg_class_names[cl],
5228 reg_class_names[rclass]);
5229 fprintf (lra_dump_file,
5230 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5231 }
5232 return false;
5233 }
5234 if ((ira_class_subset_p[cl][rclass] && cl != rclass)
5235 /* We don't use a subset of two classes because it can be
5236 NO_REGS. This transformation is still profitable in most
5237 cases even if the classes are not intersected as register
5238 move is probably cheaper than a memory load. */
5239 || ira_class_hard_regs_num[cl] < ira_class_hard_regs_num[rclass])
5240 {
5241 if (lra_dump_file != NULL)
5242 fprintf (lra_dump_file, " Use smallest class of %s and %s\n",
5243 reg_class_names[cl], reg_class_names[rclass]);
5244
5245 rclass = cl;
5246 }
5247 if (check_secondary_memory_needed_p (rclass, next_usage_insns))
5248 {
5249 /* Reject inheritance resulting in secondary memory moves.
5250 Otherwise, there is a danger in LRA cycling. Also such
5251 transformation will be unprofitable. */
5252 if (lra_dump_file != NULL)
5253 {
5254 rtx_insn *insn = skip_usage_debug_insns (next_usage_insns);
5255 rtx set = single_set (insn);
5256
5257 lra_assert (set != NULL_RTX);
5258
5259 rtx dest = SET_DEST (set);
5260
5261 lra_assert (REG_P (dest));
5262 fprintf (lra_dump_file,
5263 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
5264 "as secondary mem is needed\n",
5265 REGNO (dest), reg_class_names[get_reg_class (REGNO (dest))],
5266 original_regno, reg_class_names[rclass]);
5267 fprintf (lra_dump_file,
5268 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5269 }
5270 return false;
5271 }
5272 new_reg = lra_create_new_reg (GET_MODE (original_reg), original_reg,
5273 rclass, "inheritance");
5274 start_sequence ();
5275 if (def_p)
5276 lra_emit_move (original_reg, new_reg);
5277 else
5278 lra_emit_move (new_reg, original_reg);
5279 new_insns = get_insns ();
5280 end_sequence ();
5281 if (NEXT_INSN (new_insns) != NULL_RTX)
5282 {
5283 if (lra_dump_file != NULL)
5284 {
5285 fprintf (lra_dump_file,
5286 " Rejecting inheritance %d->%d "
5287 "as it results in 2 or more insns:\n",
5288 original_regno, REGNO (new_reg));
5289 dump_rtl_slim (lra_dump_file, new_insns, NULL, -1, 0);
5290 fprintf (lra_dump_file,
5291 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5292 }
5293 return false;
5294 }
5295 lra_substitute_pseudo_within_insn (insn, original_regno, new_reg, false);
5296 lra_update_insn_regno_info (insn);
5297 if (! def_p)
5298 /* We now have a new usage insn for original regno. */
5299 setup_next_usage_insn (original_regno, new_insns, reloads_num, false);
5300 if (lra_dump_file != NULL)
5301 fprintf (lra_dump_file, " Original reg change %d->%d (bb%d):\n",
5302 original_regno, REGNO (new_reg), BLOCK_FOR_INSN (insn)->index);
5303 lra_reg_info[REGNO (new_reg)].restore_rtx = regno_reg_rtx[original_regno];
5304 bitmap_set_bit (&check_only_regs, REGNO (new_reg));
5305 bitmap_set_bit (&check_only_regs, original_regno);
5306 bitmap_set_bit (&lra_inheritance_pseudos, REGNO (new_reg));
5307 if (def_p)
5308 lra_process_new_insns (insn, NULL, new_insns,
5309 "Add original<-inheritance");
5310 else
5311 lra_process_new_insns (insn, new_insns, NULL,
5312 "Add inheritance<-original");
5313 while (next_usage_insns != NULL_RTX)
5314 {
5315 if (GET_CODE (next_usage_insns) != INSN_LIST)
5316 {
5317 usage_insn = next_usage_insns;
5318 lra_assert (NONDEBUG_INSN_P (usage_insn));
5319 next_usage_insns = NULL;
5320 }
5321 else
5322 {
5323 usage_insn = XEXP (next_usage_insns, 0);
5324 lra_assert (DEBUG_INSN_P (usage_insn));
5325 next_usage_insns = XEXP (next_usage_insns, 1);
5326 }
5327 lra_substitute_pseudo (&usage_insn, original_regno, new_reg, false,
5328 DEBUG_INSN_P (usage_insn));
5329 lra_update_insn_regno_info (as_a <rtx_insn *> (usage_insn));
5330 if (lra_dump_file != NULL)
5331 {
5332 basic_block bb = BLOCK_FOR_INSN (usage_insn);
5333 fprintf (lra_dump_file,
5334 " Inheritance reuse change %d->%d (bb%d):\n",
5335 original_regno, REGNO (new_reg),
5336 bb ? bb->index : -1);
5337 dump_insn_slim (lra_dump_file, as_a <rtx_insn *> (usage_insn));
5338 }
5339 }
5340 if (lra_dump_file != NULL)
5341 fprintf (lra_dump_file,
5342 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5343 return true;
5344 }
5345
5346 /* Return true if we need a caller save/restore for pseudo REGNO which
5347 was assigned to a hard register. */
5348 static inline bool
need_for_call_save_p(int regno)5349 need_for_call_save_p (int regno)
5350 {
5351 lra_assert (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] >= 0);
5352 return (usage_insns[regno].calls_num < calls_num
5353 && (overlaps_hard_reg_set_p
5354 ((flag_ipa_ra &&
5355 ! hard_reg_set_empty_p (lra_reg_info[regno].actual_call_used_reg_set))
5356 ? lra_reg_info[regno].actual_call_used_reg_set
5357 : call_used_reg_set,
5358 PSEUDO_REGNO_MODE (regno), reg_renumber[regno])
5359 || (targetm.hard_regno_call_part_clobbered
5360 (reg_renumber[regno], PSEUDO_REGNO_MODE (regno)))));
5361 }
5362
5363 /* Global registers occurring in the current EBB. */
5364 static bitmap_head ebb_global_regs;
5365
5366 /* Return true if we need a split for hard register REGNO or pseudo
5367 REGNO which was assigned to a hard register.
5368 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
5369 used for reloads since the EBB end. It is an approximation of the
5370 used hard registers in the split range. The exact value would
5371 require expensive calculations. If we were aggressive with
5372 splitting because of the approximation, the split pseudo will save
5373 the same hard register assignment and will be removed in the undo
5374 pass. We still need the approximation because too aggressive
5375 splitting would result in too inaccurate cost calculation in the
5376 assignment pass because of too many generated moves which will be
5377 probably removed in the undo pass. */
5378 static inline bool
need_for_split_p(HARD_REG_SET potential_reload_hard_regs,int regno)5379 need_for_split_p (HARD_REG_SET potential_reload_hard_regs, int regno)
5380 {
5381 int hard_regno = regno < FIRST_PSEUDO_REGISTER ? regno : reg_renumber[regno];
5382
5383 lra_assert (hard_regno >= 0);
5384 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs, hard_regno)
5385 /* Don't split eliminable hard registers, otherwise we can
5386 split hard registers like hard frame pointer, which
5387 lives on BB start/end according to DF-infrastructure,
5388 when there is a pseudo assigned to the register and
5389 living in the same BB. */
5390 && (regno >= FIRST_PSEUDO_REGISTER
5391 || ! TEST_HARD_REG_BIT (eliminable_regset, hard_regno))
5392 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno)
5393 /* Don't split call clobbered hard regs living through
5394 calls, otherwise we might have a check problem in the
5395 assign sub-pass as in the most cases (exception is a
5396 situation when lra_risky_transformations_p value is
5397 true) the assign pass assumes that all pseudos living
5398 through calls are assigned to call saved hard regs. */
5399 && (regno >= FIRST_PSEUDO_REGISTER
5400 || ! TEST_HARD_REG_BIT (call_used_reg_set, regno)
5401 || usage_insns[regno].calls_num == calls_num)
5402 /* We need at least 2 reloads to make pseudo splitting
5403 profitable. We should provide hard regno splitting in
5404 any case to solve 1st insn scheduling problem when
5405 moving hard register definition up might result in
5406 impossibility to find hard register for reload pseudo of
5407 small register class. */
5408 && (usage_insns[regno].reloads_num
5409 + (regno < FIRST_PSEUDO_REGISTER ? 0 : 3) < reloads_num)
5410 && (regno < FIRST_PSEUDO_REGISTER
5411 /* For short living pseudos, spilling + inheritance can
5412 be considered a substitution for splitting.
5413 Therefore we do not splitting for local pseudos. It
5414 decreases also aggressiveness of splitting. The
5415 minimal number of references is chosen taking into
5416 account that for 2 references splitting has no sense
5417 as we can just spill the pseudo. */
5418 || (regno >= FIRST_PSEUDO_REGISTER
5419 && lra_reg_info[regno].nrefs > 3
5420 && bitmap_bit_p (&ebb_global_regs, regno))))
5421 || (regno >= FIRST_PSEUDO_REGISTER && need_for_call_save_p (regno)));
5422 }
5423
5424 /* Return class for the split pseudo created from original pseudo with
5425 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
5426 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
5427 results in no secondary memory movements. */
5428 static enum reg_class
choose_split_class(enum reg_class allocno_class,int hard_regno ATTRIBUTE_UNUSED,machine_mode mode ATTRIBUTE_UNUSED)5429 choose_split_class (enum reg_class allocno_class,
5430 int hard_regno ATTRIBUTE_UNUSED,
5431 machine_mode mode ATTRIBUTE_UNUSED)
5432 {
5433 int i;
5434 enum reg_class cl, best_cl = NO_REGS;
5435 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
5436 = REGNO_REG_CLASS (hard_regno);
5437
5438 if (! targetm.secondary_memory_needed (mode, allocno_class, allocno_class)
5439 && TEST_HARD_REG_BIT (reg_class_contents[allocno_class], hard_regno))
5440 return allocno_class;
5441 for (i = 0;
5442 (cl = reg_class_subclasses[allocno_class][i]) != LIM_REG_CLASSES;
5443 i++)
5444 if (! targetm.secondary_memory_needed (mode, cl, hard_reg_class)
5445 && ! targetm.secondary_memory_needed (mode, hard_reg_class, cl)
5446 && TEST_HARD_REG_BIT (reg_class_contents[cl], hard_regno)
5447 && (best_cl == NO_REGS
5448 || ira_class_hard_regs_num[best_cl] < ira_class_hard_regs_num[cl]))
5449 best_cl = cl;
5450 return best_cl;
5451 }
5452
5453 /* Copy any equivalence information from ORIGINAL_REGNO to NEW_REGNO.
5454 It only makes sense to call this function if NEW_REGNO is always
5455 equal to ORIGINAL_REGNO. */
5456
5457 static void
lra_copy_reg_equiv(unsigned int new_regno,unsigned int original_regno)5458 lra_copy_reg_equiv (unsigned int new_regno, unsigned int original_regno)
5459 {
5460 if (!ira_reg_equiv[original_regno].defined_p)
5461 return;
5462
5463 ira_expand_reg_equiv ();
5464 ira_reg_equiv[new_regno].defined_p = true;
5465 if (ira_reg_equiv[original_regno].memory)
5466 ira_reg_equiv[new_regno].memory
5467 = copy_rtx (ira_reg_equiv[original_regno].memory);
5468 if (ira_reg_equiv[original_regno].constant)
5469 ira_reg_equiv[new_regno].constant
5470 = copy_rtx (ira_reg_equiv[original_regno].constant);
5471 if (ira_reg_equiv[original_regno].invariant)
5472 ira_reg_equiv[new_regno].invariant
5473 = copy_rtx (ira_reg_equiv[original_regno].invariant);
5474 }
5475
5476 /* Do split transformations for insn INSN, which defines or uses
5477 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
5478 the EBB next uses ORIGINAL_REGNO; it has the same form as the
5479 "insns" field of usage_insns. If TO is not NULL, we don't use
5480 usage_insns, we put restore insns after TO insn.
5481
5482 The transformations look like:
5483
5484 p <- ... p <- ...
5485 ... s <- p (new insn -- save)
5486 ... =>
5487 ... p <- s (new insn -- restore)
5488 <- ... p ... <- ... p ...
5489 or
5490 <- ... p ... <- ... p ...
5491 ... s <- p (new insn -- save)
5492 ... =>
5493 ... p <- s (new insn -- restore)
5494 <- ... p ... <- ... p ...
5495
5496 where p is an original pseudo got a hard register or a hard
5497 register and s is a new split pseudo. The save is put before INSN
5498 if BEFORE_P is true. Return true if we succeed in such
5499 transformation. */
5500 static bool
split_reg(bool before_p,int original_regno,rtx_insn * insn,rtx next_usage_insns,rtx_insn * to)5501 split_reg (bool before_p, int original_regno, rtx_insn *insn,
5502 rtx next_usage_insns, rtx_insn *to)
5503 {
5504 enum reg_class rclass;
5505 rtx original_reg;
5506 int hard_regno, nregs;
5507 rtx new_reg, usage_insn;
5508 rtx_insn *restore, *save;
5509 bool after_p;
5510 bool call_save_p;
5511 machine_mode mode;
5512
5513 if (original_regno < FIRST_PSEUDO_REGISTER)
5514 {
5515 rclass = ira_allocno_class_translate[REGNO_REG_CLASS (original_regno)];
5516 hard_regno = original_regno;
5517 call_save_p = false;
5518 nregs = 1;
5519 mode = lra_reg_info[hard_regno].biggest_mode;
5520 machine_mode reg_rtx_mode = GET_MODE (regno_reg_rtx[hard_regno]);
5521 /* A reg can have a biggest_mode of VOIDmode if it was only ever seen
5522 as part of a multi-word register. In that case, or if the biggest
5523 mode was larger than a register, just use the reg_rtx. Otherwise,
5524 limit the size to that of the biggest access in the function. */
5525 if (mode == VOIDmode
5526 || paradoxical_subreg_p (mode, reg_rtx_mode))
5527 {
5528 original_reg = regno_reg_rtx[hard_regno];
5529 mode = reg_rtx_mode;
5530 }
5531 else
5532 original_reg = gen_rtx_REG (mode, hard_regno);
5533 }
5534 else
5535 {
5536 mode = PSEUDO_REGNO_MODE (original_regno);
5537 hard_regno = reg_renumber[original_regno];
5538 nregs = hard_regno_nregs (hard_regno, mode);
5539 rclass = lra_get_allocno_class (original_regno);
5540 original_reg = regno_reg_rtx[original_regno];
5541 call_save_p = need_for_call_save_p (original_regno);
5542 }
5543 lra_assert (hard_regno >= 0);
5544 if (lra_dump_file != NULL)
5545 fprintf (lra_dump_file,
5546 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
5547
5548 if (call_save_p)
5549 {
5550 mode = HARD_REGNO_CALLER_SAVE_MODE (hard_regno,
5551 hard_regno_nregs (hard_regno, mode),
5552 mode);
5553 new_reg = lra_create_new_reg (mode, NULL_RTX, NO_REGS, "save");
5554 }
5555 else
5556 {
5557 rclass = choose_split_class (rclass, hard_regno, mode);
5558 if (rclass == NO_REGS)
5559 {
5560 if (lra_dump_file != NULL)
5561 {
5562 fprintf (lra_dump_file,
5563 " Rejecting split of %d(%s): "
5564 "no good reg class for %d(%s)\n",
5565 original_regno,
5566 reg_class_names[lra_get_allocno_class (original_regno)],
5567 hard_regno,
5568 reg_class_names[REGNO_REG_CLASS (hard_regno)]);
5569 fprintf
5570 (lra_dump_file,
5571 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5572 }
5573 return false;
5574 }
5575 /* Split_if_necessary can split hard registers used as part of a
5576 multi-register mode but splits each register individually. The
5577 mode used for each independent register may not be supported
5578 so reject the split. Splitting the wider mode should theoretically
5579 be possible but is not implemented. */
5580 if (!targetm.hard_regno_mode_ok (hard_regno, mode))
5581 {
5582 if (lra_dump_file != NULL)
5583 {
5584 fprintf (lra_dump_file,
5585 " Rejecting split of %d(%s): unsuitable mode %s\n",
5586 original_regno,
5587 reg_class_names[lra_get_allocno_class (original_regno)],
5588 GET_MODE_NAME (mode));
5589 fprintf
5590 (lra_dump_file,
5591 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5592 }
5593 return false;
5594 }
5595 new_reg = lra_create_new_reg (mode, original_reg, rclass, "split");
5596 reg_renumber[REGNO (new_reg)] = hard_regno;
5597 }
5598 int new_regno = REGNO (new_reg);
5599 save = emit_spill_move (true, new_reg, original_reg);
5600 if (NEXT_INSN (save) != NULL_RTX && !call_save_p)
5601 {
5602 if (lra_dump_file != NULL)
5603 {
5604 fprintf
5605 (lra_dump_file,
5606 " Rejecting split %d->%d resulting in > 2 save insns:\n",
5607 original_regno, new_regno);
5608 dump_rtl_slim (lra_dump_file, save, NULL, -1, 0);
5609 fprintf (lra_dump_file,
5610 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5611 }
5612 return false;
5613 }
5614 restore = emit_spill_move (false, new_reg, original_reg);
5615 if (NEXT_INSN (restore) != NULL_RTX && !call_save_p)
5616 {
5617 if (lra_dump_file != NULL)
5618 {
5619 fprintf (lra_dump_file,
5620 " Rejecting split %d->%d "
5621 "resulting in > 2 restore insns:\n",
5622 original_regno, new_regno);
5623 dump_rtl_slim (lra_dump_file, restore, NULL, -1, 0);
5624 fprintf (lra_dump_file,
5625 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5626 }
5627 return false;
5628 }
5629 /* Transfer equivalence information to the spill register, so that
5630 if we fail to allocate the spill register, we have the option of
5631 rematerializing the original value instead of spilling to the stack. */
5632 if (!HARD_REGISTER_NUM_P (original_regno)
5633 && mode == PSEUDO_REGNO_MODE (original_regno))
5634 lra_copy_reg_equiv (new_regno, original_regno);
5635 lra_reg_info[new_regno].restore_rtx = regno_reg_rtx[original_regno];
5636 bitmap_set_bit (&check_only_regs, new_regno);
5637 bitmap_set_bit (&check_only_regs, original_regno);
5638 bitmap_set_bit (&lra_split_regs, new_regno);
5639 if (to != NULL)
5640 {
5641 usage_insn = to;
5642 after_p = TRUE;
5643 }
5644 else
5645 {
5646 after_p = usage_insns[original_regno].after_p;
5647 for (;;)
5648 {
5649 if (GET_CODE (next_usage_insns) != INSN_LIST)
5650 {
5651 usage_insn = next_usage_insns;
5652 break;
5653 }
5654 usage_insn = XEXP (next_usage_insns, 0);
5655 lra_assert (DEBUG_INSN_P (usage_insn));
5656 next_usage_insns = XEXP (next_usage_insns, 1);
5657 lra_substitute_pseudo (&usage_insn, original_regno, new_reg, false,
5658 true);
5659 lra_update_insn_regno_info (as_a <rtx_insn *> (usage_insn));
5660 if (lra_dump_file != NULL)
5661 {
5662 fprintf (lra_dump_file, " Split reuse change %d->%d:\n",
5663 original_regno, new_regno);
5664 dump_insn_slim (lra_dump_file, as_a <rtx_insn *> (usage_insn));
5665 }
5666 }
5667 }
5668 lra_assert (NOTE_P (usage_insn) || NONDEBUG_INSN_P (usage_insn));
5669 lra_assert (usage_insn != insn || (after_p && before_p));
5670 lra_process_new_insns (as_a <rtx_insn *> (usage_insn),
5671 after_p ? NULL : restore,
5672 after_p ? restore : NULL,
5673 call_save_p
5674 ? "Add reg<-save" : "Add reg<-split");
5675 lra_process_new_insns (insn, before_p ? save : NULL,
5676 before_p ? NULL : save,
5677 call_save_p
5678 ? "Add save<-reg" : "Add split<-reg");
5679 if (nregs > 1)
5680 /* If we are trying to split multi-register. We should check
5681 conflicts on the next assignment sub-pass. IRA can allocate on
5682 sub-register levels, LRA do this on pseudos level right now and
5683 this discrepancy may create allocation conflicts after
5684 splitting. */
5685 lra_risky_transformations_p = true;
5686 if (lra_dump_file != NULL)
5687 fprintf (lra_dump_file,
5688 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5689 return true;
5690 }
5691
5692 /* Split a hard reg for reload pseudo REGNO having RCLASS and living
5693 in the range [FROM, TO]. Return true if did a split. Otherwise,
5694 return false. */
5695 bool
spill_hard_reg_in_range(int regno,enum reg_class rclass,rtx_insn * from,rtx_insn * to)5696 spill_hard_reg_in_range (int regno, enum reg_class rclass, rtx_insn *from, rtx_insn *to)
5697 {
5698 int i, hard_regno;
5699 int rclass_size;
5700 rtx_insn *insn;
5701 unsigned int uid;
5702 bitmap_iterator bi;
5703 HARD_REG_SET ignore;
5704
5705 lra_assert (from != NULL && to != NULL);
5706 CLEAR_HARD_REG_SET (ignore);
5707 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi)
5708 {
5709 lra_insn_recog_data_t id = lra_insn_recog_data[uid];
5710 struct lra_static_insn_data *static_id = id->insn_static_data;
5711 struct lra_insn_reg *reg;
5712
5713 for (reg = id->regs; reg != NULL; reg = reg->next)
5714 if (reg->regno <= FIRST_PSEUDO_REGISTER)
5715 SET_HARD_REG_BIT (ignore, reg->regno);
5716 for (reg = static_id->hard_regs; reg != NULL; reg = reg->next)
5717 SET_HARD_REG_BIT (ignore, reg->regno);
5718 }
5719 rclass_size = ira_class_hard_regs_num[rclass];
5720 for (i = 0; i < rclass_size; i++)
5721 {
5722 hard_regno = ira_class_hard_regs[rclass][i];
5723 if (! TEST_HARD_REG_BIT (lra_reg_info[regno].conflict_hard_regs, hard_regno)
5724 || TEST_HARD_REG_BIT (ignore, hard_regno))
5725 continue;
5726 for (insn = from; insn != NEXT_INSN (to); insn = NEXT_INSN (insn))
5727 if (bitmap_bit_p (&lra_reg_info[hard_regno].insn_bitmap,
5728 INSN_UID (insn)))
5729 break;
5730 if (insn != NEXT_INSN (to))
5731 continue;
5732 if (split_reg (TRUE, hard_regno, from, NULL, to))
5733 return true;
5734 }
5735 return false;
5736 }
5737
5738 /* Recognize that we need a split transformation for insn INSN, which
5739 defines or uses REGNO in its insn biggest MODE (we use it only if
5740 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
5741 hard registers which might be used for reloads since the EBB end.
5742 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
5743 uid before starting INSN processing. Return true if we succeed in
5744 such transformation. */
5745 static bool
split_if_necessary(int regno,machine_mode mode,HARD_REG_SET potential_reload_hard_regs,bool before_p,rtx_insn * insn,int max_uid)5746 split_if_necessary (int regno, machine_mode mode,
5747 HARD_REG_SET potential_reload_hard_regs,
5748 bool before_p, rtx_insn *insn, int max_uid)
5749 {
5750 bool res = false;
5751 int i, nregs = 1;
5752 rtx next_usage_insns;
5753
5754 if (regno < FIRST_PSEUDO_REGISTER)
5755 nregs = hard_regno_nregs (regno, mode);
5756 for (i = 0; i < nregs; i++)
5757 if (usage_insns[regno + i].check == curr_usage_insns_check
5758 && (next_usage_insns = usage_insns[regno + i].insns) != NULL_RTX
5759 /* To avoid processing the register twice or more. */
5760 && ((GET_CODE (next_usage_insns) != INSN_LIST
5761 && INSN_UID (next_usage_insns) < max_uid)
5762 || (GET_CODE (next_usage_insns) == INSN_LIST
5763 && (INSN_UID (XEXP (next_usage_insns, 0)) < max_uid)))
5764 && need_for_split_p (potential_reload_hard_regs, regno + i)
5765 && split_reg (before_p, regno + i, insn, next_usage_insns, NULL))
5766 res = true;
5767 return res;
5768 }
5769
5770 /* Return TRUE if rtx X is considered as an invariant for
5771 inheritance. */
5772 static bool
invariant_p(const_rtx x)5773 invariant_p (const_rtx x)
5774 {
5775 machine_mode mode;
5776 const char *fmt;
5777 enum rtx_code code;
5778 int i, j;
5779
5780 if (side_effects_p (x))
5781 return false;
5782
5783 code = GET_CODE (x);
5784 mode = GET_MODE (x);
5785 if (code == SUBREG)
5786 {
5787 x = SUBREG_REG (x);
5788 code = GET_CODE (x);
5789 mode = wider_subreg_mode (mode, GET_MODE (x));
5790 }
5791
5792 if (MEM_P (x))
5793 return false;
5794
5795 if (REG_P (x))
5796 {
5797 int i, nregs, regno = REGNO (x);
5798
5799 if (regno >= FIRST_PSEUDO_REGISTER || regno == STACK_POINTER_REGNUM
5800 || TEST_HARD_REG_BIT (eliminable_regset, regno)
5801 || GET_MODE_CLASS (GET_MODE (x)) == MODE_CC)
5802 return false;
5803 nregs = hard_regno_nregs (regno, mode);
5804 for (i = 0; i < nregs; i++)
5805 if (! fixed_regs[regno + i]
5806 /* A hard register may be clobbered in the current insn
5807 but we can ignore this case because if the hard
5808 register is used it should be set somewhere after the
5809 clobber. */
5810 || bitmap_bit_p (&invalid_invariant_regs, regno + i))
5811 return false;
5812 }
5813 fmt = GET_RTX_FORMAT (code);
5814 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5815 {
5816 if (fmt[i] == 'e')
5817 {
5818 if (! invariant_p (XEXP (x, i)))
5819 return false;
5820 }
5821 else if (fmt[i] == 'E')
5822 {
5823 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5824 if (! invariant_p (XVECEXP (x, i, j)))
5825 return false;
5826 }
5827 }
5828 return true;
5829 }
5830
5831 /* We have 'dest_reg <- invariant'. Let us try to make an invariant
5832 inheritance transformation (using dest_reg instead invariant in a
5833 subsequent insn). */
5834 static bool
process_invariant_for_inheritance(rtx dst_reg,rtx invariant_rtx)5835 process_invariant_for_inheritance (rtx dst_reg, rtx invariant_rtx)
5836 {
5837 invariant_ptr_t invariant_ptr;
5838 rtx_insn *insn, *new_insns;
5839 rtx insn_set, insn_reg, new_reg;
5840 int insn_regno;
5841 bool succ_p = false;
5842 int dst_regno = REGNO (dst_reg);
5843 machine_mode dst_mode = GET_MODE (dst_reg);
5844 enum reg_class cl = lra_get_allocno_class (dst_regno), insn_reg_cl;
5845
5846 invariant_ptr = insert_invariant (invariant_rtx);
5847 if ((insn = invariant_ptr->insn) != NULL_RTX)
5848 {
5849 /* We have a subsequent insn using the invariant. */
5850 insn_set = single_set (insn);
5851 lra_assert (insn_set != NULL);
5852 insn_reg = SET_DEST (insn_set);
5853 lra_assert (REG_P (insn_reg));
5854 insn_regno = REGNO (insn_reg);
5855 insn_reg_cl = lra_get_allocno_class (insn_regno);
5856
5857 if (dst_mode == GET_MODE (insn_reg)
5858 /* We should consider only result move reg insns which are
5859 cheap. */
5860 && targetm.register_move_cost (dst_mode, cl, insn_reg_cl) == 2
5861 && targetm.register_move_cost (dst_mode, cl, cl) == 2)
5862 {
5863 if (lra_dump_file != NULL)
5864 fprintf (lra_dump_file,
5865 " [[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[\n");
5866 new_reg = lra_create_new_reg (dst_mode, dst_reg,
5867 cl, "invariant inheritance");
5868 bitmap_set_bit (&lra_inheritance_pseudos, REGNO (new_reg));
5869 bitmap_set_bit (&check_only_regs, REGNO (new_reg));
5870 lra_reg_info[REGNO (new_reg)].restore_rtx = PATTERN (insn);
5871 start_sequence ();
5872 lra_emit_move (new_reg, dst_reg);
5873 new_insns = get_insns ();
5874 end_sequence ();
5875 lra_process_new_insns (curr_insn, NULL, new_insns,
5876 "Add invariant inheritance<-original");
5877 start_sequence ();
5878 lra_emit_move (SET_DEST (insn_set), new_reg);
5879 new_insns = get_insns ();
5880 end_sequence ();
5881 lra_process_new_insns (insn, NULL, new_insns,
5882 "Changing reload<-inheritance");
5883 lra_set_insn_deleted (insn);
5884 succ_p = true;
5885 if (lra_dump_file != NULL)
5886 {
5887 fprintf (lra_dump_file,
5888 " Invariant inheritance reuse change %d (bb%d):\n",
5889 REGNO (new_reg), BLOCK_FOR_INSN (insn)->index);
5890 dump_insn_slim (lra_dump_file, insn);
5891 fprintf (lra_dump_file,
5892 " ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]\n");
5893 }
5894 }
5895 }
5896 invariant_ptr->insn = curr_insn;
5897 return succ_p;
5898 }
5899
5900 /* Check only registers living at the current program point in the
5901 current EBB. */
5902 static bitmap_head live_regs;
5903
5904 /* Update live info in EBB given by its HEAD and TAIL insns after
5905 inheritance/split transformation. The function removes dead moves
5906 too. */
5907 static void
update_ebb_live_info(rtx_insn * head,rtx_insn * tail)5908 update_ebb_live_info (rtx_insn *head, rtx_insn *tail)
5909 {
5910 unsigned int j;
5911 int i, regno;
5912 bool live_p;
5913 rtx_insn *prev_insn;
5914 rtx set;
5915 bool remove_p;
5916 basic_block last_bb, prev_bb, curr_bb;
5917 bitmap_iterator bi;
5918 struct lra_insn_reg *reg;
5919 edge e;
5920 edge_iterator ei;
5921
5922 last_bb = BLOCK_FOR_INSN (tail);
5923 prev_bb = NULL;
5924 for (curr_insn = tail;
5925 curr_insn != PREV_INSN (head);
5926 curr_insn = prev_insn)
5927 {
5928 prev_insn = PREV_INSN (curr_insn);
5929 /* We need to process empty blocks too. They contain
5930 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
5931 if (NOTE_P (curr_insn) && NOTE_KIND (curr_insn) != NOTE_INSN_BASIC_BLOCK)
5932 continue;
5933 curr_bb = BLOCK_FOR_INSN (curr_insn);
5934 if (curr_bb != prev_bb)
5935 {
5936 if (prev_bb != NULL)
5937 {
5938 /* Update df_get_live_in (prev_bb): */
5939 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi)
5940 if (bitmap_bit_p (&live_regs, j))
5941 bitmap_set_bit (df_get_live_in (prev_bb), j);
5942 else
5943 bitmap_clear_bit (df_get_live_in (prev_bb), j);
5944 }
5945 if (curr_bb != last_bb)
5946 {
5947 /* Update df_get_live_out (curr_bb): */
5948 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi)
5949 {
5950 live_p = bitmap_bit_p (&live_regs, j);
5951 if (! live_p)
5952 FOR_EACH_EDGE (e, ei, curr_bb->succs)
5953 if (bitmap_bit_p (df_get_live_in (e->dest), j))
5954 {
5955 live_p = true;
5956 break;
5957 }
5958 if (live_p)
5959 bitmap_set_bit (df_get_live_out (curr_bb), j);
5960 else
5961 bitmap_clear_bit (df_get_live_out (curr_bb), j);
5962 }
5963 }
5964 prev_bb = curr_bb;
5965 bitmap_and (&live_regs, &check_only_regs, df_get_live_out (curr_bb));
5966 }
5967 if (! NONDEBUG_INSN_P (curr_insn))
5968 continue;
5969 curr_id = lra_get_insn_recog_data (curr_insn);
5970 curr_static_id = curr_id->insn_static_data;
5971 remove_p = false;
5972 if ((set = single_set (curr_insn)) != NULL_RTX
5973 && REG_P (SET_DEST (set))
5974 && (regno = REGNO (SET_DEST (set))) >= FIRST_PSEUDO_REGISTER
5975 && SET_DEST (set) != pic_offset_table_rtx
5976 && bitmap_bit_p (&check_only_regs, regno)
5977 && ! bitmap_bit_p (&live_regs, regno))
5978 remove_p = true;
5979 /* See which defined values die here. */
5980 for (reg = curr_id->regs; reg != NULL; reg = reg->next)
5981 if (reg->type == OP_OUT && ! reg->subreg_p)
5982 bitmap_clear_bit (&live_regs, reg->regno);
5983 for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next)
5984 if (reg->type == OP_OUT && ! reg->subreg_p)
5985 bitmap_clear_bit (&live_regs, reg->regno);
5986 if (curr_id->arg_hard_regs != NULL)
5987 /* Make clobbered argument hard registers die. */
5988 for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++)
5989 if (regno >= FIRST_PSEUDO_REGISTER)
5990 bitmap_clear_bit (&live_regs, regno - FIRST_PSEUDO_REGISTER);
5991 /* Mark each used value as live. */
5992 for (reg = curr_id->regs; reg != NULL; reg = reg->next)
5993 if (reg->type != OP_OUT
5994 && bitmap_bit_p (&check_only_regs, reg->regno))
5995 bitmap_set_bit (&live_regs, reg->regno);
5996 for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next)
5997 if (reg->type != OP_OUT
5998 && bitmap_bit_p (&check_only_regs, reg->regno))
5999 bitmap_set_bit (&live_regs, reg->regno);
6000 if (curr_id->arg_hard_regs != NULL)
6001 /* Make used argument hard registers live. */
6002 for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++)
6003 if (regno < FIRST_PSEUDO_REGISTER
6004 && bitmap_bit_p (&check_only_regs, regno))
6005 bitmap_set_bit (&live_regs, regno);
6006 /* It is quite important to remove dead move insns because it
6007 means removing dead store. We don't need to process them for
6008 constraints. */
6009 if (remove_p)
6010 {
6011 if (lra_dump_file != NULL)
6012 {
6013 fprintf (lra_dump_file, " Removing dead insn:\n ");
6014 dump_insn_slim (lra_dump_file, curr_insn);
6015 }
6016 lra_set_insn_deleted (curr_insn);
6017 }
6018 }
6019 }
6020
6021 /* The structure describes info to do an inheritance for the current
6022 insn. We need to collect such info first before doing the
6023 transformations because the transformations change the insn
6024 internal representation. */
6025 struct to_inherit
6026 {
6027 /* Original regno. */
6028 int regno;
6029 /* Subsequent insns which can inherit original reg value. */
6030 rtx insns;
6031 };
6032
6033 /* Array containing all info for doing inheritance from the current
6034 insn. */
6035 static struct to_inherit to_inherit[LRA_MAX_INSN_RELOADS];
6036
6037 /* Number elements in the previous array. */
6038 static int to_inherit_num;
6039
6040 /* Add inheritance info REGNO and INSNS. Their meaning is described in
6041 structure to_inherit. */
6042 static void
add_to_inherit(int regno,rtx insns)6043 add_to_inherit (int regno, rtx insns)
6044 {
6045 int i;
6046
6047 for (i = 0; i < to_inherit_num; i++)
6048 if (to_inherit[i].regno == regno)
6049 return;
6050 lra_assert (to_inherit_num < LRA_MAX_INSN_RELOADS);
6051 to_inherit[to_inherit_num].regno = regno;
6052 to_inherit[to_inherit_num++].insns = insns;
6053 }
6054
6055 /* Return the last non-debug insn in basic block BB, or the block begin
6056 note if none. */
6057 static rtx_insn *
get_last_insertion_point(basic_block bb)6058 get_last_insertion_point (basic_block bb)
6059 {
6060 rtx_insn *insn;
6061
6062 FOR_BB_INSNS_REVERSE (bb, insn)
6063 if (NONDEBUG_INSN_P (insn) || NOTE_INSN_BASIC_BLOCK_P (insn))
6064 return insn;
6065 gcc_unreachable ();
6066 }
6067
6068 /* Set up RES by registers living on edges FROM except the edge (FROM,
6069 TO) or by registers set up in a jump insn in BB FROM. */
6070 static void
get_live_on_other_edges(basic_block from,basic_block to,bitmap res)6071 get_live_on_other_edges (basic_block from, basic_block to, bitmap res)
6072 {
6073 rtx_insn *last;
6074 struct lra_insn_reg *reg;
6075 edge e;
6076 edge_iterator ei;
6077
6078 lra_assert (to != NULL);
6079 bitmap_clear (res);
6080 FOR_EACH_EDGE (e, ei, from->succs)
6081 if (e->dest != to)
6082 bitmap_ior_into (res, df_get_live_in (e->dest));
6083 last = get_last_insertion_point (from);
6084 if (! JUMP_P (last))
6085 return;
6086 curr_id = lra_get_insn_recog_data (last);
6087 for (reg = curr_id->regs; reg != NULL; reg = reg->next)
6088 if (reg->type != OP_IN)
6089 bitmap_set_bit (res, reg->regno);
6090 }
6091
6092 /* Used as a temporary results of some bitmap calculations. */
6093 static bitmap_head temp_bitmap;
6094
6095 /* We split for reloads of small class of hard regs. The following
6096 defines how many hard regs the class should have to be qualified as
6097 small. The code is mostly oriented to x86/x86-64 architecture
6098 where some insns need to use only specific register or pair of
6099 registers and these register can live in RTL explicitly, e.g. for
6100 parameter passing. */
6101 static const int max_small_class_regs_num = 2;
6102
6103 /* Do inheritance/split transformations in EBB starting with HEAD and
6104 finishing on TAIL. We process EBB insns in the reverse order.
6105 Return true if we did any inheritance/split transformation in the
6106 EBB.
6107
6108 We should avoid excessive splitting which results in worse code
6109 because of inaccurate cost calculations for spilling new split
6110 pseudos in such case. To achieve this we do splitting only if
6111 register pressure is high in given basic block and there are reload
6112 pseudos requiring hard registers. We could do more register
6113 pressure calculations at any given program point to avoid necessary
6114 splitting even more but it is to expensive and the current approach
6115 works well enough. */
6116 static bool
inherit_in_ebb(rtx_insn * head,rtx_insn * tail)6117 inherit_in_ebb (rtx_insn *head, rtx_insn *tail)
6118 {
6119 int i, src_regno, dst_regno, nregs;
6120 bool change_p, succ_p, update_reloads_num_p;
6121 rtx_insn *prev_insn, *last_insn;
6122 rtx next_usage_insns, curr_set;
6123 enum reg_class cl;
6124 struct lra_insn_reg *reg;
6125 basic_block last_processed_bb, curr_bb = NULL;
6126 HARD_REG_SET potential_reload_hard_regs, live_hard_regs;
6127 bitmap to_process;
6128 unsigned int j;
6129 bitmap_iterator bi;
6130 bool head_p, after_p;
6131
6132 change_p = false;
6133 curr_usage_insns_check++;
6134 clear_invariants ();
6135 reloads_num = calls_num = 0;
6136 bitmap_clear (&check_only_regs);
6137 bitmap_clear (&invalid_invariant_regs);
6138 last_processed_bb = NULL;
6139 CLEAR_HARD_REG_SET (potential_reload_hard_regs);
6140 COPY_HARD_REG_SET (live_hard_regs, eliminable_regset);
6141 IOR_HARD_REG_SET (live_hard_regs, lra_no_alloc_regs);
6142 /* We don't process new insns generated in the loop. */
6143 for (curr_insn = tail; curr_insn != PREV_INSN (head); curr_insn = prev_insn)
6144 {
6145 prev_insn = PREV_INSN (curr_insn);
6146 if (BLOCK_FOR_INSN (curr_insn) != NULL)
6147 curr_bb = BLOCK_FOR_INSN (curr_insn);
6148 if (last_processed_bb != curr_bb)
6149 {
6150 /* We are at the end of BB. Add qualified living
6151 pseudos for potential splitting. */
6152 to_process = df_get_live_out (curr_bb);
6153 if (last_processed_bb != NULL)
6154 {
6155 /* We are somewhere in the middle of EBB. */
6156 get_live_on_other_edges (curr_bb, last_processed_bb,
6157 &temp_bitmap);
6158 to_process = &temp_bitmap;
6159 }
6160 last_processed_bb = curr_bb;
6161 last_insn = get_last_insertion_point (curr_bb);
6162 after_p = (! JUMP_P (last_insn)
6163 && (! CALL_P (last_insn)
6164 || (find_reg_note (last_insn,
6165 REG_NORETURN, NULL_RTX) == NULL_RTX
6166 && ! SIBLING_CALL_P (last_insn))));
6167 CLEAR_HARD_REG_SET (potential_reload_hard_regs);
6168 EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi)
6169 {
6170 if ((int) j >= lra_constraint_new_regno_start)
6171 break;
6172 if (j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0)
6173 {
6174 if (j < FIRST_PSEUDO_REGISTER)
6175 SET_HARD_REG_BIT (live_hard_regs, j);
6176 else
6177 add_to_hard_reg_set (&live_hard_regs,
6178 PSEUDO_REGNO_MODE (j),
6179 reg_renumber[j]);
6180 setup_next_usage_insn (j, last_insn, reloads_num, after_p);
6181 }
6182 }
6183 }
6184 src_regno = dst_regno = -1;
6185 curr_set = single_set (curr_insn);
6186 if (curr_set != NULL_RTX && REG_P (SET_DEST (curr_set)))
6187 dst_regno = REGNO (SET_DEST (curr_set));
6188 if (curr_set != NULL_RTX && REG_P (SET_SRC (curr_set)))
6189 src_regno = REGNO (SET_SRC (curr_set));
6190 update_reloads_num_p = true;
6191 if (src_regno < lra_constraint_new_regno_start
6192 && src_regno >= FIRST_PSEUDO_REGISTER
6193 && reg_renumber[src_regno] < 0
6194 && dst_regno >= lra_constraint_new_regno_start
6195 && (cl = lra_get_allocno_class (dst_regno)) != NO_REGS)
6196 {
6197 /* 'reload_pseudo <- original_pseudo'. */
6198 if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num)
6199 reloads_num++;
6200 update_reloads_num_p = false;
6201 succ_p = false;
6202 if (usage_insns[src_regno].check == curr_usage_insns_check
6203 && (next_usage_insns = usage_insns[src_regno].insns) != NULL_RTX)
6204 succ_p = inherit_reload_reg (false, src_regno, cl,
6205 curr_insn, next_usage_insns);
6206 if (succ_p)
6207 change_p = true;
6208 else
6209 setup_next_usage_insn (src_regno, curr_insn, reloads_num, false);
6210 if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs))
6211 IOR_HARD_REG_SET (potential_reload_hard_regs,
6212 reg_class_contents[cl]);
6213 }
6214 else if (src_regno < 0
6215 && dst_regno >= lra_constraint_new_regno_start
6216 && invariant_p (SET_SRC (curr_set))
6217 && (cl = lra_get_allocno_class (dst_regno)) != NO_REGS
6218 && ! bitmap_bit_p (&invalid_invariant_regs, dst_regno)
6219 && ! bitmap_bit_p (&invalid_invariant_regs,
6220 ORIGINAL_REGNO(regno_reg_rtx[dst_regno])))
6221 {
6222 /* 'reload_pseudo <- invariant'. */
6223 if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num)
6224 reloads_num++;
6225 update_reloads_num_p = false;
6226 if (process_invariant_for_inheritance (SET_DEST (curr_set), SET_SRC (curr_set)))
6227 change_p = true;
6228 if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs))
6229 IOR_HARD_REG_SET (potential_reload_hard_regs,
6230 reg_class_contents[cl]);
6231 }
6232 else if (src_regno >= lra_constraint_new_regno_start
6233 && dst_regno < lra_constraint_new_regno_start
6234 && dst_regno >= FIRST_PSEUDO_REGISTER
6235 && reg_renumber[dst_regno] < 0
6236 && (cl = lra_get_allocno_class (src_regno)) != NO_REGS
6237 && usage_insns[dst_regno].check == curr_usage_insns_check
6238 && (next_usage_insns
6239 = usage_insns[dst_regno].insns) != NULL_RTX)
6240 {
6241 if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num)
6242 reloads_num++;
6243 update_reloads_num_p = false;
6244 /* 'original_pseudo <- reload_pseudo'. */
6245 if (! JUMP_P (curr_insn)
6246 && inherit_reload_reg (true, dst_regno, cl,
6247 curr_insn, next_usage_insns))
6248 change_p = true;
6249 /* Invalidate. */
6250 usage_insns[dst_regno].check = 0;
6251 if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs))
6252 IOR_HARD_REG_SET (potential_reload_hard_regs,
6253 reg_class_contents[cl]);
6254 }
6255 else if (INSN_P (curr_insn))
6256 {
6257 int iter;
6258 int max_uid = get_max_uid ();
6259
6260 curr_id = lra_get_insn_recog_data (curr_insn);
6261 curr_static_id = curr_id->insn_static_data;
6262 to_inherit_num = 0;
6263 /* Process insn definitions. */
6264 for (iter = 0; iter < 2; iter++)
6265 for (reg = iter == 0 ? curr_id->regs : curr_static_id->hard_regs;
6266 reg != NULL;
6267 reg = reg->next)
6268 if (reg->type != OP_IN
6269 && (dst_regno = reg->regno) < lra_constraint_new_regno_start)
6270 {
6271 if (dst_regno >= FIRST_PSEUDO_REGISTER && reg->type == OP_OUT
6272 && reg_renumber[dst_regno] < 0 && ! reg->subreg_p
6273 && usage_insns[dst_regno].check == curr_usage_insns_check
6274 && (next_usage_insns
6275 = usage_insns[dst_regno].insns) != NULL_RTX)
6276 {
6277 struct lra_insn_reg *r;
6278
6279 for (r = curr_id->regs; r != NULL; r = r->next)
6280 if (r->type != OP_OUT && r->regno == dst_regno)
6281 break;
6282 /* Don't do inheritance if the pseudo is also
6283 used in the insn. */
6284 if (r == NULL)
6285 /* We can not do inheritance right now
6286 because the current insn reg info (chain
6287 regs) can change after that. */
6288 add_to_inherit (dst_regno, next_usage_insns);
6289 }
6290 /* We can not process one reg twice here because of
6291 usage_insns invalidation. */
6292 if ((dst_regno < FIRST_PSEUDO_REGISTER
6293 || reg_renumber[dst_regno] >= 0)
6294 && ! reg->subreg_p && reg->type != OP_IN)
6295 {
6296 HARD_REG_SET s;
6297
6298 if (split_if_necessary (dst_regno, reg->biggest_mode,
6299 potential_reload_hard_regs,
6300 false, curr_insn, max_uid))
6301 change_p = true;
6302 CLEAR_HARD_REG_SET (s);
6303 if (dst_regno < FIRST_PSEUDO_REGISTER)
6304 add_to_hard_reg_set (&s, reg->biggest_mode, dst_regno);
6305 else
6306 add_to_hard_reg_set (&s, PSEUDO_REGNO_MODE (dst_regno),
6307 reg_renumber[dst_regno]);
6308 AND_COMPL_HARD_REG_SET (live_hard_regs, s);
6309 AND_COMPL_HARD_REG_SET (potential_reload_hard_regs, s);
6310 }
6311 /* We should invalidate potential inheritance or
6312 splitting for the current insn usages to the next
6313 usage insns (see code below) as the output pseudo
6314 prevents this. */
6315 if ((dst_regno >= FIRST_PSEUDO_REGISTER
6316 && reg_renumber[dst_regno] < 0)
6317 || (reg->type == OP_OUT && ! reg->subreg_p
6318 && (dst_regno < FIRST_PSEUDO_REGISTER
6319 || reg_renumber[dst_regno] >= 0)))
6320 {
6321 /* Invalidate and mark definitions. */
6322 if (dst_regno >= FIRST_PSEUDO_REGISTER)
6323 usage_insns[dst_regno].check = -(int) INSN_UID (curr_insn);
6324 else
6325 {
6326 nregs = hard_regno_nregs (dst_regno,
6327 reg->biggest_mode);
6328 for (i = 0; i < nregs; i++)
6329 usage_insns[dst_regno + i].check
6330 = -(int) INSN_UID (curr_insn);
6331 }
6332 }
6333 }
6334 /* Process clobbered call regs. */
6335 if (curr_id->arg_hard_regs != NULL)
6336 for (i = 0; (dst_regno = curr_id->arg_hard_regs[i]) >= 0; i++)
6337 if (dst_regno >= FIRST_PSEUDO_REGISTER)
6338 usage_insns[dst_regno - FIRST_PSEUDO_REGISTER].check
6339 = -(int) INSN_UID (curr_insn);
6340 if (! JUMP_P (curr_insn))
6341 for (i = 0; i < to_inherit_num; i++)
6342 if (inherit_reload_reg (true, to_inherit[i].regno,
6343 ALL_REGS, curr_insn,
6344 to_inherit[i].insns))
6345 change_p = true;
6346 if (CALL_P (curr_insn))
6347 {
6348 rtx cheap, pat, dest;
6349 rtx_insn *restore;
6350 int regno, hard_regno;
6351
6352 calls_num++;
6353 if ((cheap = find_reg_note (curr_insn,
6354 REG_RETURNED, NULL_RTX)) != NULL_RTX
6355 && ((cheap = XEXP (cheap, 0)), true)
6356 && (regno = REGNO (cheap)) >= FIRST_PSEUDO_REGISTER
6357 && (hard_regno = reg_renumber[regno]) >= 0
6358 && usage_insns[regno].check == curr_usage_insns_check
6359 /* If there are pending saves/restores, the
6360 optimization is not worth. */
6361 && usage_insns[regno].calls_num == calls_num - 1
6362 && TEST_HARD_REG_BIT (call_used_reg_set, hard_regno))
6363 {
6364 /* Restore the pseudo from the call result as
6365 REG_RETURNED note says that the pseudo value is
6366 in the call result and the pseudo is an argument
6367 of the call. */
6368 pat = PATTERN (curr_insn);
6369 if (GET_CODE (pat) == PARALLEL)
6370 pat = XVECEXP (pat, 0, 0);
6371 dest = SET_DEST (pat);
6372 /* For multiple return values dest is PARALLEL.
6373 Currently we handle only single return value case. */
6374 if (REG_P (dest))
6375 {
6376 start_sequence ();
6377 emit_move_insn (cheap, copy_rtx (dest));
6378 restore = get_insns ();
6379 end_sequence ();
6380 lra_process_new_insns (curr_insn, NULL, restore,
6381 "Inserting call parameter restore");
6382 /* We don't need to save/restore of the pseudo from
6383 this call. */
6384 usage_insns[regno].calls_num = calls_num;
6385 bitmap_set_bit (&check_only_regs, regno);
6386 }
6387 }
6388 }
6389 to_inherit_num = 0;
6390 /* Process insn usages. */
6391 for (iter = 0; iter < 2; iter++)
6392 for (reg = iter == 0 ? curr_id->regs : curr_static_id->hard_regs;
6393 reg != NULL;
6394 reg = reg->next)
6395 if ((reg->type != OP_OUT
6396 || (reg->type == OP_OUT && reg->subreg_p))
6397 && (src_regno = reg->regno) < lra_constraint_new_regno_start)
6398 {
6399 if (src_regno >= FIRST_PSEUDO_REGISTER
6400 && reg_renumber[src_regno] < 0 && reg->type == OP_IN)
6401 {
6402 if (usage_insns[src_regno].check == curr_usage_insns_check
6403 && (next_usage_insns
6404 = usage_insns[src_regno].insns) != NULL_RTX
6405 && NONDEBUG_INSN_P (curr_insn))
6406 add_to_inherit (src_regno, next_usage_insns);
6407 else if (usage_insns[src_regno].check
6408 != -(int) INSN_UID (curr_insn))
6409 /* Add usages but only if the reg is not set up
6410 in the same insn. */
6411 add_next_usage_insn (src_regno, curr_insn, reloads_num);
6412 }
6413 else if (src_regno < FIRST_PSEUDO_REGISTER
6414 || reg_renumber[src_regno] >= 0)
6415 {
6416 bool before_p;
6417 rtx_insn *use_insn = curr_insn;
6418
6419 before_p = (JUMP_P (curr_insn)
6420 || (CALL_P (curr_insn) && reg->type == OP_IN));
6421 if (NONDEBUG_INSN_P (curr_insn)
6422 && (! JUMP_P (curr_insn) || reg->type == OP_IN)
6423 && split_if_necessary (src_regno, reg->biggest_mode,
6424 potential_reload_hard_regs,
6425 before_p, curr_insn, max_uid))
6426 {
6427 if (reg->subreg_p)
6428 lra_risky_transformations_p = true;
6429 change_p = true;
6430 /* Invalidate. */
6431 usage_insns[src_regno].check = 0;
6432 if (before_p)
6433 use_insn = PREV_INSN (curr_insn);
6434 }
6435 if (NONDEBUG_INSN_P (curr_insn))
6436 {
6437 if (src_regno < FIRST_PSEUDO_REGISTER)
6438 add_to_hard_reg_set (&live_hard_regs,
6439 reg->biggest_mode, src_regno);
6440 else
6441 add_to_hard_reg_set (&live_hard_regs,
6442 PSEUDO_REGNO_MODE (src_regno),
6443 reg_renumber[src_regno]);
6444 }
6445 if (src_regno >= FIRST_PSEUDO_REGISTER)
6446 add_next_usage_insn (src_regno, use_insn, reloads_num);
6447 else
6448 {
6449 for (i = 0; i < hard_regno_nregs (src_regno, reg->biggest_mode); i++)
6450 add_next_usage_insn (src_regno + i, use_insn, reloads_num);
6451 }
6452 }
6453 }
6454 /* Process used call regs. */
6455 if (curr_id->arg_hard_regs != NULL)
6456 for (i = 0; (src_regno = curr_id->arg_hard_regs[i]) >= 0; i++)
6457 if (src_regno < FIRST_PSEUDO_REGISTER)
6458 {
6459 SET_HARD_REG_BIT (live_hard_regs, src_regno);
6460 add_next_usage_insn (src_regno, curr_insn, reloads_num);
6461 }
6462 for (i = 0; i < to_inherit_num; i++)
6463 {
6464 src_regno = to_inherit[i].regno;
6465 if (inherit_reload_reg (false, src_regno, ALL_REGS,
6466 curr_insn, to_inherit[i].insns))
6467 change_p = true;
6468 else
6469 setup_next_usage_insn (src_regno, curr_insn, reloads_num, false);
6470 }
6471 }
6472 if (update_reloads_num_p
6473 && NONDEBUG_INSN_P (curr_insn) && curr_set != NULL_RTX)
6474 {
6475 int regno = -1;
6476 if ((REG_P (SET_DEST (curr_set))
6477 && (regno = REGNO (SET_DEST (curr_set))) >= lra_constraint_new_regno_start
6478 && reg_renumber[regno] < 0
6479 && (cl = lra_get_allocno_class (regno)) != NO_REGS)
6480 || (REG_P (SET_SRC (curr_set))
6481 && (regno = REGNO (SET_SRC (curr_set))) >= lra_constraint_new_regno_start
6482 && reg_renumber[regno] < 0
6483 && (cl = lra_get_allocno_class (regno)) != NO_REGS))
6484 {
6485 if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num)
6486 reloads_num++;
6487 if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs))
6488 IOR_HARD_REG_SET (potential_reload_hard_regs,
6489 reg_class_contents[cl]);
6490 }
6491 }
6492 if (NONDEBUG_INSN_P (curr_insn))
6493 {
6494 int regno;
6495
6496 /* Invalidate invariants with changed regs. */
6497 curr_id = lra_get_insn_recog_data (curr_insn);
6498 for (reg = curr_id->regs; reg != NULL; reg = reg->next)
6499 if (reg->type != OP_IN)
6500 {
6501 bitmap_set_bit (&invalid_invariant_regs, reg->regno);
6502 bitmap_set_bit (&invalid_invariant_regs,
6503 ORIGINAL_REGNO (regno_reg_rtx[reg->regno]));
6504 }
6505 curr_static_id = curr_id->insn_static_data;
6506 for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next)
6507 if (reg->type != OP_IN)
6508 bitmap_set_bit (&invalid_invariant_regs, reg->regno);
6509 if (curr_id->arg_hard_regs != NULL)
6510 for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++)
6511 if (regno >= FIRST_PSEUDO_REGISTER)
6512 bitmap_set_bit (&invalid_invariant_regs,
6513 regno - FIRST_PSEUDO_REGISTER);
6514 }
6515 /* We reached the start of the current basic block. */
6516 if (prev_insn == NULL_RTX || prev_insn == PREV_INSN (head)
6517 || BLOCK_FOR_INSN (prev_insn) != curr_bb)
6518 {
6519 /* We reached the beginning of the current block -- do
6520 rest of spliting in the current BB. */
6521 to_process = df_get_live_in (curr_bb);
6522 if (BLOCK_FOR_INSN (head) != curr_bb)
6523 {
6524 /* We are somewhere in the middle of EBB. */
6525 get_live_on_other_edges (EDGE_PRED (curr_bb, 0)->src,
6526 curr_bb, &temp_bitmap);
6527 to_process = &temp_bitmap;
6528 }
6529 head_p = true;
6530 EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi)
6531 {
6532 if ((int) j >= lra_constraint_new_regno_start)
6533 break;
6534 if (((int) j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0)
6535 && usage_insns[j].check == curr_usage_insns_check
6536 && (next_usage_insns = usage_insns[j].insns) != NULL_RTX)
6537 {
6538 if (need_for_split_p (potential_reload_hard_regs, j))
6539 {
6540 if (lra_dump_file != NULL && head_p)
6541 {
6542 fprintf (lra_dump_file,
6543 " ----------------------------------\n");
6544 head_p = false;
6545 }
6546 if (split_reg (false, j, bb_note (curr_bb),
6547 next_usage_insns, NULL))
6548 change_p = true;
6549 }
6550 usage_insns[j].check = 0;
6551 }
6552 }
6553 }
6554 }
6555 return change_p;
6556 }
6557
6558 /* This value affects EBB forming. If probability of edge from EBB to
6559 a BB is not greater than the following value, we don't add the BB
6560 to EBB. */
6561 #define EBB_PROBABILITY_CUTOFF \
6562 ((REG_BR_PROB_BASE * LRA_INHERITANCE_EBB_PROBABILITY_CUTOFF) / 100)
6563
6564 /* Current number of inheritance/split iteration. */
6565 int lra_inheritance_iter;
6566
6567 /* Entry function for inheritance/split pass. */
6568 void
lra_inheritance(void)6569 lra_inheritance (void)
6570 {
6571 int i;
6572 basic_block bb, start_bb;
6573 edge e;
6574
6575 lra_inheritance_iter++;
6576 if (lra_inheritance_iter > LRA_MAX_INHERITANCE_PASSES)
6577 return;
6578 timevar_push (TV_LRA_INHERITANCE);
6579 if (lra_dump_file != NULL)
6580 fprintf (lra_dump_file, "\n********** Inheritance #%d: **********\n\n",
6581 lra_inheritance_iter);
6582 curr_usage_insns_check = 0;
6583 usage_insns = XNEWVEC (struct usage_insns, lra_constraint_new_regno_start);
6584 for (i = 0; i < lra_constraint_new_regno_start; i++)
6585 usage_insns[i].check = 0;
6586 bitmap_initialize (&check_only_regs, ®_obstack);
6587 bitmap_initialize (&invalid_invariant_regs, ®_obstack);
6588 bitmap_initialize (&live_regs, ®_obstack);
6589 bitmap_initialize (&temp_bitmap, ®_obstack);
6590 bitmap_initialize (&ebb_global_regs, ®_obstack);
6591 FOR_EACH_BB_FN (bb, cfun)
6592 {
6593 start_bb = bb;
6594 if (lra_dump_file != NULL)
6595 fprintf (lra_dump_file, "EBB");
6596 /* Form a EBB starting with BB. */
6597 bitmap_clear (&ebb_global_regs);
6598 bitmap_ior_into (&ebb_global_regs, df_get_live_in (bb));
6599 for (;;)
6600 {
6601 if (lra_dump_file != NULL)
6602 fprintf (lra_dump_file, " %d", bb->index);
6603 if (bb->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
6604 || LABEL_P (BB_HEAD (bb->next_bb)))
6605 break;
6606 e = find_fallthru_edge (bb->succs);
6607 if (! e)
6608 break;
6609 if (e->probability.initialized_p ()
6610 && e->probability.to_reg_br_prob_base () < EBB_PROBABILITY_CUTOFF)
6611 break;
6612 bb = bb->next_bb;
6613 }
6614 bitmap_ior_into (&ebb_global_regs, df_get_live_out (bb));
6615 if (lra_dump_file != NULL)
6616 fprintf (lra_dump_file, "\n");
6617 if (inherit_in_ebb (BB_HEAD (start_bb), BB_END (bb)))
6618 /* Remember that the EBB head and tail can change in
6619 inherit_in_ebb. */
6620 update_ebb_live_info (BB_HEAD (start_bb), BB_END (bb));
6621 }
6622 bitmap_clear (&ebb_global_regs);
6623 bitmap_clear (&temp_bitmap);
6624 bitmap_clear (&live_regs);
6625 bitmap_clear (&invalid_invariant_regs);
6626 bitmap_clear (&check_only_regs);
6627 free (usage_insns);
6628
6629 timevar_pop (TV_LRA_INHERITANCE);
6630 }
6631
6632
6633
6634 /* This page contains code to undo failed inheritance/split
6635 transformations. */
6636
6637 /* Current number of iteration undoing inheritance/split. */
6638 int lra_undo_inheritance_iter;
6639
6640 /* Fix BB live info LIVE after removing pseudos created on pass doing
6641 inheritance/split which are REMOVED_PSEUDOS. */
6642 static void
fix_bb_live_info(bitmap live,bitmap removed_pseudos)6643 fix_bb_live_info (bitmap live, bitmap removed_pseudos)
6644 {
6645 unsigned int regno;
6646 bitmap_iterator bi;
6647
6648 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos, 0, regno, bi)
6649 if (bitmap_clear_bit (live, regno)
6650 && REG_P (lra_reg_info[regno].restore_rtx))
6651 bitmap_set_bit (live, REGNO (lra_reg_info[regno].restore_rtx));
6652 }
6653
6654 /* Return regno of the (subreg of) REG. Otherwise, return a negative
6655 number. */
6656 static int
get_regno(rtx reg)6657 get_regno (rtx reg)
6658 {
6659 if (GET_CODE (reg) == SUBREG)
6660 reg = SUBREG_REG (reg);
6661 if (REG_P (reg))
6662 return REGNO (reg);
6663 return -1;
6664 }
6665
6666 /* Delete a move INSN with destination reg DREGNO and a previous
6667 clobber insn with the same regno. The inheritance/split code can
6668 generate moves with preceding clobber and when we delete such moves
6669 we should delete the clobber insn too to keep the correct life
6670 info. */
6671 static void
delete_move_and_clobber(rtx_insn * insn,int dregno)6672 delete_move_and_clobber (rtx_insn *insn, int dregno)
6673 {
6674 rtx_insn *prev_insn = PREV_INSN (insn);
6675
6676 lra_set_insn_deleted (insn);
6677 lra_assert (dregno >= 0);
6678 if (prev_insn != NULL && NONDEBUG_INSN_P (prev_insn)
6679 && GET_CODE (PATTERN (prev_insn)) == CLOBBER
6680 && dregno == get_regno (XEXP (PATTERN (prev_insn), 0)))
6681 lra_set_insn_deleted (prev_insn);
6682 }
6683
6684 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
6685 return true if we did any change. The undo transformations for
6686 inheritance looks like
6687 i <- i2
6688 p <- i => p <- i2
6689 or removing
6690 p <- i, i <- p, and i <- i3
6691 where p is original pseudo from which inheritance pseudo i was
6692 created, i and i3 are removed inheritance pseudos, i2 is another
6693 not removed inheritance pseudo. All split pseudos or other
6694 occurrences of removed inheritance pseudos are changed on the
6695 corresponding original pseudos.
6696
6697 The function also schedules insns changed and created during
6698 inheritance/split pass for processing by the subsequent constraint
6699 pass. */
6700 static bool
remove_inheritance_pseudos(bitmap remove_pseudos)6701 remove_inheritance_pseudos (bitmap remove_pseudos)
6702 {
6703 basic_block bb;
6704 int regno, sregno, prev_sregno, dregno;
6705 rtx restore_rtx;
6706 rtx set, prev_set;
6707 rtx_insn *prev_insn;
6708 bool change_p, done_p;
6709
6710 change_p = ! bitmap_empty_p (remove_pseudos);
6711 /* We can not finish the function right away if CHANGE_P is true
6712 because we need to marks insns affected by previous
6713 inheritance/split pass for processing by the subsequent
6714 constraint pass. */
6715 FOR_EACH_BB_FN (bb, cfun)
6716 {
6717 fix_bb_live_info (df_get_live_in (bb), remove_pseudos);
6718 fix_bb_live_info (df_get_live_out (bb), remove_pseudos);
6719 FOR_BB_INSNS_REVERSE (bb, curr_insn)
6720 {
6721 if (! INSN_P (curr_insn))
6722 continue;
6723 done_p = false;
6724 sregno = dregno = -1;
6725 if (change_p && NONDEBUG_INSN_P (curr_insn)
6726 && (set = single_set (curr_insn)) != NULL_RTX)
6727 {
6728 dregno = get_regno (SET_DEST (set));
6729 sregno = get_regno (SET_SRC (set));
6730 }
6731
6732 if (sregno >= 0 && dregno >= 0)
6733 {
6734 if (bitmap_bit_p (remove_pseudos, dregno)
6735 && ! REG_P (lra_reg_info[dregno].restore_rtx))
6736 {
6737 /* invariant inheritance pseudo <- original pseudo */
6738 if (lra_dump_file != NULL)
6739 {
6740 fprintf (lra_dump_file, " Removing invariant inheritance:\n");
6741 dump_insn_slim (lra_dump_file, curr_insn);
6742 fprintf (lra_dump_file, "\n");
6743 }
6744 delete_move_and_clobber (curr_insn, dregno);
6745 done_p = true;
6746 }
6747 else if (bitmap_bit_p (remove_pseudos, sregno)
6748 && ! REG_P (lra_reg_info[sregno].restore_rtx))
6749 {
6750 /* reload pseudo <- invariant inheritance pseudo */
6751 start_sequence ();
6752 /* We can not just change the source. It might be
6753 an insn different from the move. */
6754 emit_insn (lra_reg_info[sregno].restore_rtx);
6755 rtx_insn *new_insns = get_insns ();
6756 end_sequence ();
6757 lra_assert (single_set (new_insns) != NULL
6758 && SET_DEST (set) == SET_DEST (single_set (new_insns)));
6759 lra_process_new_insns (curr_insn, NULL, new_insns,
6760 "Changing reload<-invariant inheritance");
6761 delete_move_and_clobber (curr_insn, dregno);
6762 done_p = true;
6763 }
6764 else if ((bitmap_bit_p (remove_pseudos, sregno)
6765 && (get_regno (lra_reg_info[sregno].restore_rtx) == dregno
6766 || (bitmap_bit_p (remove_pseudos, dregno)
6767 && get_regno (lra_reg_info[sregno].restore_rtx) >= 0
6768 && (get_regno (lra_reg_info[sregno].restore_rtx)
6769 == get_regno (lra_reg_info[dregno].restore_rtx)))))
6770 || (bitmap_bit_p (remove_pseudos, dregno)
6771 && get_regno (lra_reg_info[dregno].restore_rtx) == sregno))
6772 /* One of the following cases:
6773 original <- removed inheritance pseudo
6774 removed inherit pseudo <- another removed inherit pseudo
6775 removed inherit pseudo <- original pseudo
6776 Or
6777 removed_split_pseudo <- original_reg
6778 original_reg <- removed_split_pseudo */
6779 {
6780 if (lra_dump_file != NULL)
6781 {
6782 fprintf (lra_dump_file, " Removing %s:\n",
6783 bitmap_bit_p (&lra_split_regs, sregno)
6784 || bitmap_bit_p (&lra_split_regs, dregno)
6785 ? "split" : "inheritance");
6786 dump_insn_slim (lra_dump_file, curr_insn);
6787 }
6788 delete_move_and_clobber (curr_insn, dregno);
6789 done_p = true;
6790 }
6791 else if (bitmap_bit_p (remove_pseudos, sregno)
6792 && bitmap_bit_p (&lra_inheritance_pseudos, sregno))
6793 {
6794 /* Search the following pattern:
6795 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
6796 original_pseudo <- inherit_or_split_pseudo1
6797 where the 2nd insn is the current insn and
6798 inherit_or_split_pseudo2 is not removed. If it is found,
6799 change the current insn onto:
6800 original_pseudo <- inherit_or_split_pseudo2. */
6801 for (prev_insn = PREV_INSN (curr_insn);
6802 prev_insn != NULL_RTX && ! NONDEBUG_INSN_P (prev_insn);
6803 prev_insn = PREV_INSN (prev_insn))
6804 ;
6805 if (prev_insn != NULL_RTX && BLOCK_FOR_INSN (prev_insn) == bb
6806 && (prev_set = single_set (prev_insn)) != NULL_RTX
6807 /* There should be no subregs in insn we are
6808 searching because only the original reg might
6809 be in subreg when we changed the mode of
6810 load/store for splitting. */
6811 && REG_P (SET_DEST (prev_set))
6812 && REG_P (SET_SRC (prev_set))
6813 && (int) REGNO (SET_DEST (prev_set)) == sregno
6814 && ((prev_sregno = REGNO (SET_SRC (prev_set)))
6815 >= FIRST_PSEUDO_REGISTER)
6816 && (lra_reg_info[prev_sregno].restore_rtx == NULL_RTX
6817 ||
6818 /* As we consider chain of inheritance or
6819 splitting described in above comment we should
6820 check that sregno and prev_sregno were
6821 inheritance/split pseudos created from the
6822 same original regno. */
6823 (get_regno (lra_reg_info[sregno].restore_rtx) >= 0
6824 && (get_regno (lra_reg_info[sregno].restore_rtx)
6825 == get_regno (lra_reg_info[prev_sregno].restore_rtx))))
6826 && ! bitmap_bit_p (remove_pseudos, prev_sregno))
6827 {
6828 lra_assert (GET_MODE (SET_SRC (prev_set))
6829 == GET_MODE (regno_reg_rtx[sregno]));
6830 /* Although we have a single set, the insn can
6831 contain more one sregno register occurrence
6832 as a source. Change all occurrences. */
6833 lra_substitute_pseudo_within_insn (curr_insn, sregno,
6834 SET_SRC (prev_set),
6835 false);
6836 /* As we are finishing with processing the insn
6837 here, check the destination too as it might
6838 inheritance pseudo for another pseudo. */
6839 if (bitmap_bit_p (remove_pseudos, dregno)
6840 && bitmap_bit_p (&lra_inheritance_pseudos, dregno)
6841 && (restore_rtx
6842 = lra_reg_info[dregno].restore_rtx) != NULL_RTX)
6843 {
6844 if (GET_CODE (SET_DEST (set)) == SUBREG)
6845 SUBREG_REG (SET_DEST (set)) = restore_rtx;
6846 else
6847 SET_DEST (set) = restore_rtx;
6848 }
6849 lra_push_insn_and_update_insn_regno_info (curr_insn);
6850 lra_set_used_insn_alternative_by_uid
6851 (INSN_UID (curr_insn), LRA_UNKNOWN_ALT);
6852 done_p = true;
6853 if (lra_dump_file != NULL)
6854 {
6855 fprintf (lra_dump_file, " Change reload insn:\n");
6856 dump_insn_slim (lra_dump_file, curr_insn);
6857 }
6858 }
6859 }
6860 }
6861 if (! done_p)
6862 {
6863 struct lra_insn_reg *reg;
6864 bool restored_regs_p = false;
6865 bool kept_regs_p = false;
6866
6867 curr_id = lra_get_insn_recog_data (curr_insn);
6868 for (reg = curr_id->regs; reg != NULL; reg = reg->next)
6869 {
6870 regno = reg->regno;
6871 restore_rtx = lra_reg_info[regno].restore_rtx;
6872 if (restore_rtx != NULL_RTX)
6873 {
6874 if (change_p && bitmap_bit_p (remove_pseudos, regno))
6875 {
6876 lra_substitute_pseudo_within_insn
6877 (curr_insn, regno, restore_rtx, false);
6878 restored_regs_p = true;
6879 }
6880 else
6881 kept_regs_p = true;
6882 }
6883 }
6884 if (NONDEBUG_INSN_P (curr_insn) && kept_regs_p)
6885 {
6886 /* The instruction has changed since the previous
6887 constraints pass. */
6888 lra_push_insn_and_update_insn_regno_info (curr_insn);
6889 lra_set_used_insn_alternative_by_uid
6890 (INSN_UID (curr_insn), LRA_UNKNOWN_ALT);
6891 }
6892 else if (restored_regs_p)
6893 /* The instruction has been restored to the form that
6894 it had during the previous constraints pass. */
6895 lra_update_insn_regno_info (curr_insn);
6896 if (restored_regs_p && lra_dump_file != NULL)
6897 {
6898 fprintf (lra_dump_file, " Insn after restoring regs:\n");
6899 dump_insn_slim (lra_dump_file, curr_insn);
6900 }
6901 }
6902 }
6903 }
6904 return change_p;
6905 }
6906
6907 /* If optional reload pseudos failed to get a hard register or was not
6908 inherited, it is better to remove optional reloads. We do this
6909 transformation after undoing inheritance to figure out necessity to
6910 remove optional reloads easier. Return true if we do any
6911 change. */
6912 static bool
undo_optional_reloads(void)6913 undo_optional_reloads (void)
6914 {
6915 bool change_p, keep_p;
6916 unsigned int regno, uid;
6917 bitmap_iterator bi, bi2;
6918 rtx_insn *insn;
6919 rtx set, src, dest;
6920 auto_bitmap removed_optional_reload_pseudos (®_obstack);
6921
6922 bitmap_copy (removed_optional_reload_pseudos, &lra_optional_reload_pseudos);
6923 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos, 0, regno, bi)
6924 {
6925 keep_p = false;
6926 /* Keep optional reloads from previous subpasses. */
6927 if (lra_reg_info[regno].restore_rtx == NULL_RTX
6928 /* If the original pseudo changed its allocation, just
6929 removing the optional pseudo is dangerous as the original
6930 pseudo will have longer live range. */
6931 || reg_renumber[REGNO (lra_reg_info[regno].restore_rtx)] >= 0)
6932 keep_p = true;
6933 else if (reg_renumber[regno] >= 0)
6934 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi2)
6935 {
6936 insn = lra_insn_recog_data[uid]->insn;
6937 if ((set = single_set (insn)) == NULL_RTX)
6938 continue;
6939 src = SET_SRC (set);
6940 dest = SET_DEST (set);
6941 if (! REG_P (src) || ! REG_P (dest))
6942 continue;
6943 if (REGNO (dest) == regno
6944 /* Ignore insn for optional reloads itself. */
6945 && REGNO (lra_reg_info[regno].restore_rtx) != REGNO (src)
6946 /* Check only inheritance on last inheritance pass. */
6947 && (int) REGNO (src) >= new_regno_start
6948 /* Check that the optional reload was inherited. */
6949 && bitmap_bit_p (&lra_inheritance_pseudos, REGNO (src)))
6950 {
6951 keep_p = true;
6952 break;
6953 }
6954 }
6955 if (keep_p)
6956 {
6957 bitmap_clear_bit (removed_optional_reload_pseudos, regno);
6958 if (lra_dump_file != NULL)
6959 fprintf (lra_dump_file, "Keep optional reload reg %d\n", regno);
6960 }
6961 }
6962 change_p = ! bitmap_empty_p (removed_optional_reload_pseudos);
6963 auto_bitmap insn_bitmap (®_obstack);
6964 EXECUTE_IF_SET_IN_BITMAP (removed_optional_reload_pseudos, 0, regno, bi)
6965 {
6966 if (lra_dump_file != NULL)
6967 fprintf (lra_dump_file, "Remove optional reload reg %d\n", regno);
6968 bitmap_copy (insn_bitmap, &lra_reg_info[regno].insn_bitmap);
6969 EXECUTE_IF_SET_IN_BITMAP (insn_bitmap, 0, uid, bi2)
6970 {
6971 insn = lra_insn_recog_data[uid]->insn;
6972 if ((set = single_set (insn)) != NULL_RTX)
6973 {
6974 src = SET_SRC (set);
6975 dest = SET_DEST (set);
6976 if (REG_P (src) && REG_P (dest)
6977 && ((REGNO (src) == regno
6978 && (REGNO (lra_reg_info[regno].restore_rtx)
6979 == REGNO (dest)))
6980 || (REGNO (dest) == regno
6981 && (REGNO (lra_reg_info[regno].restore_rtx)
6982 == REGNO (src)))))
6983 {
6984 if (lra_dump_file != NULL)
6985 {
6986 fprintf (lra_dump_file, " Deleting move %u\n",
6987 INSN_UID (insn));
6988 dump_insn_slim (lra_dump_file, insn);
6989 }
6990 delete_move_and_clobber (insn, REGNO (dest));
6991 continue;
6992 }
6993 /* We should not worry about generation memory-memory
6994 moves here as if the corresponding inheritance did
6995 not work (inheritance pseudo did not get a hard reg),
6996 we remove the inheritance pseudo and the optional
6997 reload. */
6998 }
6999 lra_substitute_pseudo_within_insn
7000 (insn, regno, lra_reg_info[regno].restore_rtx, false);
7001 lra_update_insn_regno_info (insn);
7002 if (lra_dump_file != NULL)
7003 {
7004 fprintf (lra_dump_file,
7005 " Restoring original insn:\n");
7006 dump_insn_slim (lra_dump_file, insn);
7007 }
7008 }
7009 }
7010 /* Clear restore_regnos. */
7011 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos, 0, regno, bi)
7012 lra_reg_info[regno].restore_rtx = NULL_RTX;
7013 return change_p;
7014 }
7015
7016 /* Entry function for undoing inheritance/split transformation. Return true
7017 if we did any RTL change in this pass. */
7018 bool
lra_undo_inheritance(void)7019 lra_undo_inheritance (void)
7020 {
7021 unsigned int regno;
7022 int hard_regno;
7023 int n_all_inherit, n_inherit, n_all_split, n_split;
7024 rtx restore_rtx;
7025 bitmap_iterator bi;
7026 bool change_p;
7027
7028 lra_undo_inheritance_iter++;
7029 if (lra_undo_inheritance_iter > LRA_MAX_INHERITANCE_PASSES)
7030 return false;
7031 if (lra_dump_file != NULL)
7032 fprintf (lra_dump_file,
7033 "\n********** Undoing inheritance #%d: **********\n\n",
7034 lra_undo_inheritance_iter);
7035 auto_bitmap remove_pseudos (®_obstack);
7036 n_inherit = n_all_inherit = 0;
7037 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi)
7038 if (lra_reg_info[regno].restore_rtx != NULL_RTX)
7039 {
7040 n_all_inherit++;
7041 if (reg_renumber[regno] < 0
7042 /* If the original pseudo changed its allocation, just
7043 removing inheritance is dangerous as for changing
7044 allocation we used shorter live-ranges. */
7045 && (! REG_P (lra_reg_info[regno].restore_rtx)
7046 || reg_renumber[REGNO (lra_reg_info[regno].restore_rtx)] < 0))
7047 bitmap_set_bit (remove_pseudos, regno);
7048 else
7049 n_inherit++;
7050 }
7051 if (lra_dump_file != NULL && n_all_inherit != 0)
7052 fprintf (lra_dump_file, "Inherit %d out of %d (%.2f%%)\n",
7053 n_inherit, n_all_inherit,
7054 (double) n_inherit / n_all_inherit * 100);
7055 n_split = n_all_split = 0;
7056 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi)
7057 if ((restore_rtx = lra_reg_info[regno].restore_rtx) != NULL_RTX)
7058 {
7059 int restore_regno = REGNO (restore_rtx);
7060
7061 n_all_split++;
7062 hard_regno = (restore_regno >= FIRST_PSEUDO_REGISTER
7063 ? reg_renumber[restore_regno] : restore_regno);
7064 if (hard_regno < 0 || reg_renumber[regno] == hard_regno)
7065 bitmap_set_bit (remove_pseudos, regno);
7066 else
7067 {
7068 n_split++;
7069 if (lra_dump_file != NULL)
7070 fprintf (lra_dump_file, " Keep split r%d (orig=r%d)\n",
7071 regno, restore_regno);
7072 }
7073 }
7074 if (lra_dump_file != NULL && n_all_split != 0)
7075 fprintf (lra_dump_file, "Split %d out of %d (%.2f%%)\n",
7076 n_split, n_all_split,
7077 (double) n_split / n_all_split * 100);
7078 change_p = remove_inheritance_pseudos (remove_pseudos);
7079 /* Clear restore_regnos. */
7080 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi)
7081 lra_reg_info[regno].restore_rtx = NULL_RTX;
7082 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi)
7083 lra_reg_info[regno].restore_rtx = NULL_RTX;
7084 change_p = undo_optional_reloads () || change_p;
7085 return change_p;
7086 }
7087