1 /* Output routines for GCC for Renesas / SuperH SH.
2 Copyright (C) 1993-2018 Free Software Foundation, Inc.
3 Contributed by Steve Chamberlain (sac@cygnus.com).
4 Improved by Jim Wilson (wilson@cygnus.com).
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
21
22 #include <sstream>
23
24 #define IN_TARGET_CODE 1
25
26 #include "config.h"
27 #define INCLUDE_VECTOR
28 #include "system.h"
29 #include "coretypes.h"
30 #include "backend.h"
31 #include "target.h"
32 #include "rtl.h"
33 #include "tree.h"
34 #include "gimple.h"
35 #include "cfghooks.h"
36 #include "df.h"
37 #include "memmodel.h"
38 #include "tm_p.h"
39 #include "stringpool.h"
40 #include "attribs.h"
41 #include "optabs.h"
42 #include "emit-rtl.h"
43 #include "recog.h"
44 #include "diagnostic-core.h"
45 #include "alias.h"
46 #include "fold-const.h"
47 #include "stor-layout.h"
48 #include "calls.h"
49 #include "varasm.h"
50 #include "flags.h"
51 #include "explow.h"
52 #include "expr.h"
53 #include "reload.h"
54 #include "output.h"
55 #include "insn-attr.h"
56 #include "dwarf2.h"
57 #include "langhooks.h"
58 #include "cfgrtl.h"
59 #include "intl.h"
60 #include "sched-int.h"
61 #include "gimplify.h"
62 #include "tm-constrs.h"
63 #include "opts.h"
64 #include "tree-pass.h"
65 #include "context.h"
66 #include "builtins.h"
67 #include "rtl-iter.h"
68 #include "regs.h"
69
70 /* This file should be included last. */
71 #include "target-def.h"
72
73 int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;
74
75 #define CONST_OK_FOR_ADD(size) CONST_OK_FOR_I08 (size)
76 #define GEN_MOV (*(gen_movsi))
77 #define GEN_ADD3 (*(gen_addsi3))
78 #define GEN_SUB3 (*(gen_subsi3))
79
80 /* Used to simplify the logic below. Find the attributes wherever
81 they may be. */
82 #define SH_ATTRIBUTES(decl) \
83 (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
84 : DECL_ATTRIBUTES (decl) \
85 ? (DECL_ATTRIBUTES (decl)) \
86 : TYPE_ATTRIBUTES (TREE_TYPE (decl))
87
88 /* Set to true by expand_prologue() when the function is an
89 interrupt handler. */
90 bool current_function_interrupt;
91
92 tree sh_deferred_function_attributes;
93 tree *sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
94
95 /* Global variables for machine-dependent things. */
96
97 /* Which cpu are we scheduling for. */
98 enum processor_type sh_cpu;
99
100 /* Definitions used in ready queue reordering for first scheduling pass. */
101
102 /* Reg weights arrays for modes SFmode and SImode, indexed by insn LUID. */
103 static short *regmode_weight[2];
104
105 /* Total SFmode and SImode weights of scheduled insns. */
106 static int curr_regmode_pressure[2];
107
108 /* Number of r0 life regions. */
109 static int r0_life_regions;
110
111 /* If true, skip cycles for Q -> R movement. */
112 static int skip_cycles = 0;
113
114 /* Cached value of can_issue_more. This is cached in sh_variable_issue hook
115 and returned from sh_reorder2. */
116 static short cached_can_issue_more;
117
118 /* Unique number for UNSPEC_BBR pattern. */
119 static unsigned int unspec_bbr_uid = 1;
120
121 /* Provides the class number of the smallest class containing
122 reg number. */
123 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER] =
124 {
125 R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
126 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
127 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
128 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
129 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
130 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
131 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
132 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
133 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
134 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
135 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
136 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
137 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
138 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
139 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
140 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
141 FP0_REGS,FP_REGS, FP_REGS, FP_REGS,
142 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
143 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
144 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
145 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
146 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
147 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
148 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
149 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
150 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
151 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
152 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
153 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
154 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
155 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
156 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
157 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
158 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
159 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
160 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
161 NO_REGS, GENERAL_REGS, PR_REGS, T_REGS,
162 MAC_REGS, MAC_REGS, FPUL_REGS, FPSCR_REGS,
163 GENERAL_REGS, GENERAL_REGS,
164 };
165
166 char sh_register_names[FIRST_PSEUDO_REGISTER] \
167 [MAX_REGISTER_NAME_LENGTH + 1] = SH_REGISTER_NAMES_INITIALIZER;
168
169 char sh_additional_register_names[ADDREGNAMES_SIZE] \
170 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1]
171 = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER;
172
173 int assembler_dialect;
174
175 static void split_branches (rtx_insn *);
176 static int branch_dest (rtx);
177 static void print_slot (rtx_sequence *);
178 static rtx_code_label *add_constant (rtx, machine_mode, rtx);
179 static void dump_table (rtx_insn *, rtx_insn *);
180 static bool broken_move (rtx_insn *);
181 static bool mova_p (rtx_insn *);
182 static rtx_insn *find_barrier (int, rtx_insn *, rtx_insn *);
183 static bool noncall_uses_reg (rtx, rtx_insn *, rtx *);
184 static rtx_insn *gen_block_redirect (rtx_insn *, int, int);
185 static void sh_reorg (void);
186 static void sh_option_override (void);
187 static void sh_override_options_after_change (void);
188 static void output_stack_adjust (int, rtx, int, HARD_REG_SET *, bool);
189 static rtx_insn* emit_frame_insn (rtx);
190 static rtx push (int);
191 static void pop (int);
192 static void push_regs (HARD_REG_SET* mask, bool interrupt_handler);
193 static int calc_live_regs (HARD_REG_SET *);
194 static HOST_WIDE_INT rounded_frame_size (int);
195 static bool sh_frame_pointer_required (void);
196 static void sh_emit_mode_set (int, int, int, HARD_REG_SET);
197 static int sh_mode_needed (int, rtx_insn *);
198 static int sh_mode_after (int, int, rtx_insn *);
199 static int sh_mode_entry (int);
200 static int sh_mode_exit (int);
201 static int sh_mode_priority (int entity, int n);
202
203 static rtx mark_constant_pool_use (rtx);
204 static tree sh_handle_interrupt_handler_attribute (tree *, tree, tree,
205 int, bool *);
206 static tree sh_handle_resbank_handler_attribute (tree *, tree,
207 tree, int, bool *);
208 static tree sh2a_handle_function_vector_handler_attribute (tree *, tree,
209 tree, int, bool *);
210 static tree sh_handle_sp_switch_attribute (tree *, tree, tree, int, bool *);
211 static tree sh_handle_trap_exit_attribute (tree *, tree, tree, int, bool *);
212 static tree sh_handle_renesas_attribute (tree *, tree, tree, int, bool *);
213 static void sh_print_operand (FILE *, rtx, int);
214 static void sh_print_operand_address (FILE *, machine_mode, rtx);
215 static bool sh_print_operand_punct_valid_p (unsigned char code);
216 static bool sh_asm_output_addr_const_extra (FILE *file, rtx x);
217 static void sh_output_function_epilogue (FILE *);
218 static void sh_insert_attributes (tree, tree *);
219 static const char *sh_check_pch_target_flags (int);
220 static int sh_register_move_cost (machine_mode, reg_class_t, reg_class_t);
221 static int sh_adjust_cost (rtx_insn *, int, rtx_insn *, int, unsigned int);
222 static int sh_issue_rate (void);
223 static int sh_dfa_new_cycle (FILE *, int, rtx_insn *, int, int, int *sort_p);
224 static short find_set_regmode_weight (rtx, machine_mode);
225 static short find_insn_regmode_weight (rtx, machine_mode);
226 static void find_regmode_weight (basic_block, machine_mode);
227 static int find_r0_life_regions (basic_block);
228 static void sh_md_init_global (FILE *, int, int);
229 static void sh_md_finish_global (FILE *, int);
230 static int rank_for_reorder (const void *, const void *);
231 static void swap_reorder (rtx_insn **, int);
232 static void ready_reorder (rtx_insn **, int);
233 static bool high_pressure (machine_mode);
234 static int sh_reorder (FILE *, int, rtx_insn **, int *, int);
235 static int sh_reorder2 (FILE *, int, rtx_insn **, int *, int);
236 static void sh_md_init (FILE *, int, int);
237 static int sh_variable_issue (FILE *, int, rtx_insn *, int);
238
239 static bool sh_function_ok_for_sibcall (tree, tree);
240
241 static bool sh_can_follow_jump (const rtx_insn *, const rtx_insn *);
242 static bool sh_ms_bitfield_layout_p (const_tree);
243
244 static void sh_init_builtins (void);
245 static tree sh_builtin_decl (unsigned, bool);
246 static rtx sh_expand_builtin (tree, rtx, rtx, machine_mode, int);
247 static void sh_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
248 HOST_WIDE_INT, tree);
249 static void sh_file_start (void);
250 static bool sh_assemble_integer (rtx, unsigned int, int);
251 static bool flow_dependent_p (rtx, rtx);
252 static void flow_dependent_p_1 (rtx, const_rtx, void *);
253 static int shiftcosts (rtx);
254 static int and_xor_ior_costs (rtx, int);
255 static int addsubcosts (rtx);
256 static int multcosts (rtx);
257 static bool unspec_caller_rtx_p (rtx);
258 static bool sh_cannot_copy_insn_p (rtx_insn *);
259 static bool sh_cannot_force_const_mem_p (machine_mode, rtx);
260 static bool sh_rtx_costs (rtx, machine_mode, int, int, int *, bool);
261 static int sh_address_cost (rtx, machine_mode, addr_space_t, bool);
262 static int sh_pr_n_sets (void);
263 static rtx sh_allocate_initial_value (rtx);
264 static reg_class_t sh_preferred_reload_class (rtx, reg_class_t);
265 static reg_class_t sh_secondary_reload (bool, rtx, reg_class_t,
266 machine_mode,
267 struct secondary_reload_info *);
268 static bool sh_legitimate_address_p (machine_mode, rtx, bool);
269 static rtx sh_legitimize_address (rtx, rtx, machine_mode);
270 static rtx sh_delegitimize_address (rtx);
271 static bool sh_cannot_substitute_mem_equiv_p (rtx);
272 static bool sh_legitimize_address_displacement (rtx *, rtx *,
273 poly_int64, machine_mode);
274 static int scavenge_reg (HARD_REG_SET *s);
275
276 static rtx sh_struct_value_rtx (tree, int);
277 static rtx sh_function_value (const_tree, const_tree, bool);
278 static bool sh_function_value_regno_p (const unsigned int);
279 static rtx sh_libcall_value (machine_mode, const_rtx);
280 static bool sh_return_in_memory (const_tree, const_tree);
281 static rtx sh_builtin_saveregs (void);
282 static void sh_setup_incoming_varargs (cumulative_args_t, machine_mode,
283 tree, int *, int);
284 static bool sh_strict_argument_naming (cumulative_args_t);
285 static bool sh_pretend_outgoing_varargs_named (cumulative_args_t);
286 static void sh_atomic_assign_expand_fenv (tree *, tree *, tree *);
287 static tree sh_build_builtin_va_list (void);
288 static void sh_va_start (tree, rtx);
289 static tree sh_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *);
290 static bool sh_promote_prototypes (const_tree);
291 static machine_mode sh_promote_function_mode (const_tree type,
292 machine_mode,
293 int *punsignedp,
294 const_tree funtype,
295 int for_return);
296 static bool sh_pass_by_reference (cumulative_args_t, machine_mode,
297 const_tree, bool);
298 static bool sh_callee_copies (cumulative_args_t, machine_mode,
299 const_tree, bool);
300 static int sh_arg_partial_bytes (cumulative_args_t, machine_mode,
301 tree, bool);
302 static void sh_function_arg_advance (cumulative_args_t, machine_mode,
303 const_tree, bool);
304 static rtx sh_function_arg (cumulative_args_t, machine_mode,
305 const_tree, bool);
306 static int sh_dwarf_calling_convention (const_tree);
307 static void sh_encode_section_info (tree, rtx, int);
308 static bool sh2a_function_vector_p (tree);
309 static void sh_trampoline_init (rtx, tree, rtx);
310 static rtx sh_trampoline_adjust_address (rtx);
311 static void sh_conditional_register_usage (void);
312 static bool sh_legitimate_constant_p (machine_mode, rtx);
313 static int mov_insn_size (machine_mode, bool);
314 static int mov_insn_alignment_mask (machine_mode, bool);
315 static bool sh_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT,
316 unsigned int,
317 enum by_pieces_operation,
318 bool);
319 static bool sequence_insn_p (rtx_insn *);
320 static void sh_canonicalize_comparison (int *, rtx *, rtx *, bool);
321 static void sh_canonicalize_comparison (enum rtx_code&, rtx&, rtx&,
322 machine_mode, bool);
323 static bool sh_legitimate_combined_insn (rtx_insn* insn);
324
325 static bool sh_fixed_condition_code_regs (unsigned int* p1, unsigned int* p2);
326
327 static void sh_init_sync_libfuncs (void) ATTRIBUTE_UNUSED;
328 static unsigned int sh_hard_regno_nregs (unsigned int, machine_mode);
329 static bool sh_hard_regno_mode_ok (unsigned int, machine_mode);
330 static bool sh_modes_tieable_p (machine_mode, machine_mode);
331 static bool sh_can_change_mode_class (machine_mode, machine_mode, reg_class_t);
332
333 static const struct attribute_spec sh_attribute_table[] =
334 {
335 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
336 affects_type_identity, handler, exclude } */
337 { "interrupt_handler", 0, 0, true, false, false, false,
338 sh_handle_interrupt_handler_attribute, NULL },
339 { "sp_switch", 1, 1, true, false, false, false,
340 sh_handle_sp_switch_attribute, NULL },
341 { "trap_exit", 1, 1, true, false, false, false,
342 sh_handle_trap_exit_attribute, NULL },
343 { "renesas", 0, 0, false, true, false, false,
344 sh_handle_renesas_attribute, NULL },
345 { "trapa_handler", 0, 0, true, false, false, false,
346 sh_handle_interrupt_handler_attribute, NULL },
347 { "nosave_low_regs", 0, 0, true, false, false, false,
348 sh_handle_interrupt_handler_attribute, NULL },
349 { "resbank", 0, 0, true, false, false, false,
350 sh_handle_resbank_handler_attribute, NULL },
351 { "function_vector", 1, 1, true, false, false, false,
352 sh2a_handle_function_vector_handler_attribute, NULL },
353 { NULL, 0, 0, false, false, false, false, NULL, NULL }
354 };
355
356 /* Initialize the GCC target structure. */
357 #undef TARGET_ATTRIBUTE_TABLE
358 #define TARGET_ATTRIBUTE_TABLE sh_attribute_table
359
360 /* The next two are used for debug info when compiling with -gdwarf. */
361 #undef TARGET_ASM_UNALIGNED_HI_OP
362 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"
363 #undef TARGET_ASM_UNALIGNED_SI_OP
364 #define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"
365
366 #undef TARGET_OPTION_OVERRIDE
367 #define TARGET_OPTION_OVERRIDE sh_option_override
368
369 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
370 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE \
371 sh_override_options_after_change
372
373 #undef TARGET_PRINT_OPERAND
374 #define TARGET_PRINT_OPERAND sh_print_operand
375 #undef TARGET_PRINT_OPERAND_ADDRESS
376 #define TARGET_PRINT_OPERAND_ADDRESS sh_print_operand_address
377 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
378 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P sh_print_operand_punct_valid_p
379 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
380 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA sh_asm_output_addr_const_extra
381
382 #undef TARGET_ASM_FUNCTION_EPILOGUE
383 #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
384
385 #undef TARGET_ASM_OUTPUT_MI_THUNK
386 #define TARGET_ASM_OUTPUT_MI_THUNK sh_output_mi_thunk
387
388 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
389 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
390 hook_bool_const_tree_hwi_hwi_const_tree_true
391
392 #undef TARGET_ASM_FILE_START
393 #define TARGET_ASM_FILE_START sh_file_start
394 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
395 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
396
397 #undef TARGET_ASM_INTEGER
398 #define TARGET_ASM_INTEGER sh_assemble_integer
399
400 #undef TARGET_REGISTER_MOVE_COST
401 #define TARGET_REGISTER_MOVE_COST sh_register_move_cost
402
403 #undef TARGET_INSERT_ATTRIBUTES
404 #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
405
406 #undef TARGET_SCHED_ADJUST_COST
407 #define TARGET_SCHED_ADJUST_COST sh_adjust_cost
408
409 #undef TARGET_SCHED_ISSUE_RATE
410 #define TARGET_SCHED_ISSUE_RATE sh_issue_rate
411
412 /* The next 5 hooks have been implemented for reenabling sched1. With the
413 help of these macros we are limiting the movement of insns in sched1 to
414 reduce the register pressure. The overall idea is to keep count of SImode
415 and SFmode regs required by already scheduled insns. When these counts
416 cross some threshold values; give priority to insns that free registers.
417 The insn that frees registers is most likely to be the insn with lowest
418 LUID (original insn order); but such an insn might be there in the stalled
419 queue (Q) instead of the ready queue (R). To solve this, we skip cycles
420 up to a max of 8 cycles so that such insns may move from Q -> R.
421
422 The description of the hooks are as below:
423
424 TARGET_SCHED_INIT_GLOBAL: Added a new target hook in the generic
425 scheduler; it is called inside the sched_init function just after
426 find_insn_reg_weights function call. It is used to calculate the SImode
427 and SFmode weights of insns of basic blocks; much similar to what
428 find_insn_reg_weights does.
429 TARGET_SCHED_FINISH_GLOBAL: Corresponding cleanup hook.
430
431 TARGET_SCHED_DFA_NEW_CYCLE: Skip cycles if high register pressure is
432 indicated by TARGET_SCHED_REORDER2; doing this may move insns from
433 (Q)->(R).
434
435 TARGET_SCHED_REORDER: If the register pressure for SImode or SFmode is
436 high; reorder the ready queue so that the insn with lowest LUID will be
437 issued next.
438
439 TARGET_SCHED_REORDER2: If the register pressure is high, indicate to
440 TARGET_SCHED_DFA_NEW_CYCLE to skip cycles.
441
442 TARGET_SCHED_VARIABLE_ISSUE: Cache the value of can_issue_more so that it
443 can be returned from TARGET_SCHED_REORDER2.
444
445 TARGET_SCHED_INIT: Reset the register pressure counting variables. */
446
447 #undef TARGET_SCHED_DFA_NEW_CYCLE
448 #define TARGET_SCHED_DFA_NEW_CYCLE sh_dfa_new_cycle
449
450 #undef TARGET_SCHED_INIT_GLOBAL
451 #define TARGET_SCHED_INIT_GLOBAL sh_md_init_global
452
453 #undef TARGET_SCHED_FINISH_GLOBAL
454 #define TARGET_SCHED_FINISH_GLOBAL sh_md_finish_global
455
456 #undef TARGET_SCHED_VARIABLE_ISSUE
457 #define TARGET_SCHED_VARIABLE_ISSUE sh_variable_issue
458
459 #undef TARGET_SCHED_REORDER
460 #define TARGET_SCHED_REORDER sh_reorder
461
462 #undef TARGET_SCHED_REORDER2
463 #define TARGET_SCHED_REORDER2 sh_reorder2
464
465 #undef TARGET_SCHED_INIT
466 #define TARGET_SCHED_INIT sh_md_init
467
468 #undef TARGET_DELEGITIMIZE_ADDRESS
469 #define TARGET_DELEGITIMIZE_ADDRESS sh_delegitimize_address
470
471 #undef TARGET_LEGITIMIZE_ADDRESS
472 #define TARGET_LEGITIMIZE_ADDRESS sh_legitimize_address
473
474 #undef TARGET_CAN_FOLLOW_JUMP
475 #define TARGET_CAN_FOLLOW_JUMP sh_can_follow_jump
476
477 #undef TARGET_MS_BITFIELD_LAYOUT_P
478 #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
479
480 #undef TARGET_INIT_BUILTINS
481 #define TARGET_INIT_BUILTINS sh_init_builtins
482 #undef TARGET_BUILTIN_DECL
483 #define TARGET_BUILTIN_DECL sh_builtin_decl
484 #undef TARGET_EXPAND_BUILTIN
485 #define TARGET_EXPAND_BUILTIN sh_expand_builtin
486
487 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
488 #define TARGET_FUNCTION_OK_FOR_SIBCALL sh_function_ok_for_sibcall
489
490 #undef TARGET_CANNOT_COPY_INSN_P
491 #define TARGET_CANNOT_COPY_INSN_P sh_cannot_copy_insn_p
492 #undef TARGET_RTX_COSTS
493 #define TARGET_RTX_COSTS sh_rtx_costs
494 #undef TARGET_ADDRESS_COST
495 #define TARGET_ADDRESS_COST sh_address_cost
496 #undef TARGET_ALLOCATE_INITIAL_VALUE
497 #define TARGET_ALLOCATE_INITIAL_VALUE sh_allocate_initial_value
498
499 #undef TARGET_MACHINE_DEPENDENT_REORG
500 #define TARGET_MACHINE_DEPENDENT_REORG sh_reorg
501
502 #undef TARGET_DWARF_REGISTER_SPAN
503 #define TARGET_DWARF_REGISTER_SPAN sh_dwarf_register_span
504
505 #ifdef HAVE_AS_TLS
506 #undef TARGET_HAVE_TLS
507 #define TARGET_HAVE_TLS true
508 #endif
509
510 #undef TARGET_PROMOTE_PROTOTYPES
511 #define TARGET_PROMOTE_PROTOTYPES sh_promote_prototypes
512 #undef TARGET_PROMOTE_FUNCTION_MODE
513 #define TARGET_PROMOTE_FUNCTION_MODE sh_promote_function_mode
514
515 #undef TARGET_FUNCTION_VALUE
516 #define TARGET_FUNCTION_VALUE sh_function_value
517 #undef TARGET_FUNCTION_VALUE_REGNO_P
518 #define TARGET_FUNCTION_VALUE_REGNO_P sh_function_value_regno_p
519 #undef TARGET_LIBCALL_VALUE
520 #define TARGET_LIBCALL_VALUE sh_libcall_value
521 #undef TARGET_STRUCT_VALUE_RTX
522 #define TARGET_STRUCT_VALUE_RTX sh_struct_value_rtx
523 #undef TARGET_RETURN_IN_MEMORY
524 #define TARGET_RETURN_IN_MEMORY sh_return_in_memory
525
526 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
527 #define TARGET_EXPAND_BUILTIN_SAVEREGS sh_builtin_saveregs
528 #undef TARGET_SETUP_INCOMING_VARARGS
529 #define TARGET_SETUP_INCOMING_VARARGS sh_setup_incoming_varargs
530 #undef TARGET_STRICT_ARGUMENT_NAMING
531 #define TARGET_STRICT_ARGUMENT_NAMING sh_strict_argument_naming
532 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
533 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED sh_pretend_outgoing_varargs_named
534 #undef TARGET_MUST_PASS_IN_STACK
535 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
536 #undef TARGET_PASS_BY_REFERENCE
537 #define TARGET_PASS_BY_REFERENCE sh_pass_by_reference
538 #undef TARGET_CALLEE_COPIES
539 #define TARGET_CALLEE_COPIES sh_callee_copies
540 #undef TARGET_ARG_PARTIAL_BYTES
541 #define TARGET_ARG_PARTIAL_BYTES sh_arg_partial_bytes
542 #undef TARGET_FUNCTION_ARG
543 #define TARGET_FUNCTION_ARG sh_function_arg
544 #undef TARGET_FUNCTION_ARG_ADVANCE
545 #define TARGET_FUNCTION_ARG_ADVANCE sh_function_arg_advance
546
547 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
548 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV sh_atomic_assign_expand_fenv
549
550 #undef TARGET_BUILD_BUILTIN_VA_LIST
551 #define TARGET_BUILD_BUILTIN_VA_LIST sh_build_builtin_va_list
552 #undef TARGET_EXPAND_BUILTIN_VA_START
553 #define TARGET_EXPAND_BUILTIN_VA_START sh_va_start
554 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
555 #define TARGET_GIMPLIFY_VA_ARG_EXPR sh_gimplify_va_arg_expr
556
557 #undef TARGET_VECTOR_MODE_SUPPORTED_P
558 #define TARGET_VECTOR_MODE_SUPPORTED_P sh_vector_mode_supported_p
559
560 #undef TARGET_CHECK_PCH_TARGET_FLAGS
561 #define TARGET_CHECK_PCH_TARGET_FLAGS sh_check_pch_target_flags
562
563 #undef TARGET_DWARF_CALLING_CONVENTION
564 #define TARGET_DWARF_CALLING_CONVENTION sh_dwarf_calling_convention
565
566 #undef TARGET_FRAME_POINTER_REQUIRED
567 #define TARGET_FRAME_POINTER_REQUIRED sh_frame_pointer_required
568
569 #undef TARGET_MODE_EMIT
570 #define TARGET_MODE_EMIT sh_emit_mode_set
571
572 #undef TARGET_MODE_NEEDED
573 #define TARGET_MODE_NEEDED sh_mode_needed
574
575 #undef TARGET_MODE_AFTER
576 #define TARGET_MODE_AFTER sh_mode_after
577
578 #undef TARGET_MODE_ENTRY
579 #define TARGET_MODE_ENTRY sh_mode_entry
580
581 #undef TARGET_MODE_EXIT
582 #define TARGET_MODE_EXIT sh_mode_exit
583
584 #undef TARGET_MODE_PRIORITY
585 #define TARGET_MODE_PRIORITY sh_mode_priority
586
587 /* Return regmode weight for insn. */
588 #define INSN_REGMODE_WEIGHT(INSN, MODE)\
589 regmode_weight[((MODE) == SImode) ? 0 : 1][INSN_UID (INSN)]
590
591 /* Return current register pressure for regmode. */
592 #define CURR_REGMODE_PRESSURE(MODE)\
593 curr_regmode_pressure[((MODE) == SImode) ? 0 : 1]
594
595 #undef TARGET_ENCODE_SECTION_INFO
596 #define TARGET_ENCODE_SECTION_INFO sh_encode_section_info
597
598 #undef TARGET_LRA_P
599 #define TARGET_LRA_P sh_lra_p
600
601 #undef TARGET_SECONDARY_RELOAD
602 #define TARGET_SECONDARY_RELOAD sh_secondary_reload
603
604 #undef TARGET_PREFERRED_RELOAD_CLASS
605 #define TARGET_PREFERRED_RELOAD_CLASS sh_preferred_reload_class
606
607 #undef TARGET_CONDITIONAL_REGISTER_USAGE
608 #define TARGET_CONDITIONAL_REGISTER_USAGE sh_conditional_register_usage
609
610 #undef TARGET_LEGITIMATE_ADDRESS_P
611 #define TARGET_LEGITIMATE_ADDRESS_P sh_legitimate_address_p
612
613 #undef TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV_P
614 #define TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV_P sh_cannot_substitute_mem_equiv_p
615
616 #undef TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT
617 #define TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT \
618 sh_legitimize_address_displacement
619
620 #undef TARGET_TRAMPOLINE_INIT
621 #define TARGET_TRAMPOLINE_INIT sh_trampoline_init
622 #undef TARGET_TRAMPOLINE_ADJUST_ADDRESS
623 #define TARGET_TRAMPOLINE_ADJUST_ADDRESS sh_trampoline_adjust_address
624
625 #undef TARGET_LEGITIMATE_CONSTANT_P
626 #define TARGET_LEGITIMATE_CONSTANT_P sh_legitimate_constant_p
627
628 #undef TARGET_CANONICALIZE_COMPARISON
629 #define TARGET_CANONICALIZE_COMPARISON sh_canonicalize_comparison
630
631 #undef TARGET_LEGITIMATE_COMBINED_INSN
632 #define TARGET_LEGITIMATE_COMBINED_INSN sh_legitimate_combined_insn
633
634 #undef TARGET_FIXED_CONDITION_CODE_REGS
635 #define TARGET_FIXED_CONDITION_CODE_REGS sh_fixed_condition_code_regs
636
637 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
638 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
639 sh_use_by_pieces_infrastructure_p
640
641 /* Machine-specific symbol_ref flags. */
642 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
643
644 /* The tas.b instruction sets the 7th bit in the byte, i.e. 0x80. This value
645 is used by optabs.c atomic op expansion code as well as in sync.md. */
646 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
647 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 0x80
648
649 #undef TARGET_CANNOT_FORCE_CONST_MEM
650 #define TARGET_CANNOT_FORCE_CONST_MEM sh_cannot_force_const_mem_p
651
652 #undef TARGET_HARD_REGNO_NREGS
653 #define TARGET_HARD_REGNO_NREGS sh_hard_regno_nregs
654 #undef TARGET_HARD_REGNO_MODE_OK
655 #define TARGET_HARD_REGNO_MODE_OK sh_hard_regno_mode_ok
656
657 #undef TARGET_MODES_TIEABLE_P
658 #define TARGET_MODES_TIEABLE_P sh_modes_tieable_p
659
660 #undef TARGET_CAN_CHANGE_MODE_CLASS
661 #define TARGET_CAN_CHANGE_MODE_CLASS sh_can_change_mode_class
662
663 #undef TARGET_CONSTANT_ALIGNMENT
664 #define TARGET_CONSTANT_ALIGNMENT constant_alignment_word_strings
665
666 struct gcc_target targetm = TARGET_INITIALIZER;
667
668
669 /* Information on the currently selected atomic model.
670 This is initialized in sh_option_override. */
671 static sh_atomic_model selected_atomic_model_;
672
673 const sh_atomic_model&
selected_atomic_model(void)674 selected_atomic_model (void)
675 {
676 return selected_atomic_model_;
677 }
678
679 static sh_atomic_model
parse_validate_atomic_model_option(const char * str)680 parse_validate_atomic_model_option (const char* str)
681 {
682 const char* model_names[sh_atomic_model::num_models];
683 model_names[sh_atomic_model::none] = "none";
684 model_names[sh_atomic_model::soft_gusa] = "soft-gusa";
685 model_names[sh_atomic_model::hard_llcs] = "hard-llcs";
686 model_names[sh_atomic_model::soft_tcb] = "soft-tcb";
687 model_names[sh_atomic_model::soft_imask] = "soft-imask";
688
689 const char* model_cdef_names[sh_atomic_model::num_models];
690 model_cdef_names[sh_atomic_model::none] = "NONE";
691 model_cdef_names[sh_atomic_model::soft_gusa] = "SOFT_GUSA";
692 model_cdef_names[sh_atomic_model::hard_llcs] = "HARD_LLCS";
693 model_cdef_names[sh_atomic_model::soft_tcb] = "SOFT_TCB";
694 model_cdef_names[sh_atomic_model::soft_imask] = "SOFT_IMASK";
695
696 sh_atomic_model ret;
697 ret.type = sh_atomic_model::none;
698 ret.name = model_names[sh_atomic_model::none];
699 ret.cdef_name = model_cdef_names[sh_atomic_model::none];
700 ret.strict = false;
701 ret.tcb_gbr_offset = -1;
702
703 /* Handle empty string as 'none'. */
704 if (str == NULL || *str == '\0')
705 return ret;
706
707 #define err_ret(...) do { error (__VA_ARGS__); return ret; } while (0)
708
709 std::vector<std::string> tokens;
710 for (std::stringstream ss (str); ss.good (); )
711 {
712 tokens.push_back (std::string ());
713 std::getline (ss, tokens.back (), ',');
714 }
715
716 if (tokens.empty ())
717 err_ret ("invalid atomic model option");
718
719 /* The first token must be the atomic model name. */
720 {
721 for (size_t i = 0; i < sh_atomic_model::num_models; ++i)
722 if (tokens.front () == model_names[i])
723 {
724 ret.type = (sh_atomic_model::enum_type)i;
725 ret.name = model_names[i];
726 ret.cdef_name = model_cdef_names[i];
727 goto got_mode_name;
728 }
729
730 err_ret ("invalid atomic model name \"%s\"", tokens.front ().c_str ());
731 got_mode_name:;
732 }
733
734 /* Go through the remaining tokens. */
735 for (size_t i = 1; i < tokens.size (); ++i)
736 {
737 if (tokens[i] == "strict")
738 ret.strict = true;
739 else if (tokens[i].find ("gbr-offset=") == 0)
740 {
741 std::string offset_str = tokens[i].substr (strlen ("gbr-offset="));
742 ret.tcb_gbr_offset = integral_argument (offset_str.c_str ());
743 if (offset_str.empty () || ret.tcb_gbr_offset == -1)
744 err_ret ("could not parse gbr-offset value \"%s\" in atomic model "
745 "option", offset_str.c_str ());
746 }
747 else
748 err_ret ("unknown parameter \"%s\" in atomic model option",
749 tokens[i].c_str ());
750 }
751
752 /* Check that the selection makes sense. */
753 if (ret.type == sh_atomic_model::soft_gusa && !TARGET_SH3)
754 err_ret ("atomic model %s is only available on SH3 and SH4 targets",
755 ret.name);
756
757 if (ret.type == sh_atomic_model::hard_llcs && !TARGET_SH4A)
758 err_ret ("atomic model %s is only available on SH4A targets", ret.name);
759
760 if (ret.type == sh_atomic_model::soft_tcb && ret.tcb_gbr_offset == -1)
761 err_ret ("atomic model %s requires gbr-offset parameter", ret.name);
762
763 if (ret.type == sh_atomic_model::soft_tcb
764 && (ret.tcb_gbr_offset < 0 || ret.tcb_gbr_offset > 1020
765 || (ret.tcb_gbr_offset & 3) != 0))
766 err_ret ("invalid gbr-offset value \"%d\" for atomic model %s; it must be "
767 "a multiple of 4 in the range 0-1020", ret.tcb_gbr_offset,
768 ret.name);
769
770 if (ret.type == sh_atomic_model::soft_imask && TARGET_USERMODE)
771 err_ret ("cannot use atomic model %s in user mode", ret.name);
772
773 return ret;
774
775 #undef err_ret
776 }
777
778 /* Register SH specific RTL passes. */
779 extern opt_pass* make_pass_sh_treg_combine (gcc::context* ctx, bool split_insns,
780 const char* name);
781 extern opt_pass* make_pass_sh_optimize_sett_clrt (gcc::context* ctx,
782 const char* name);
783 static void
register_sh_passes(void)784 register_sh_passes (void)
785 {
786 /* Running the sh_treg_combine pass after ce1 generates better code when
787 comparisons are combined and reg-reg moves are introduced, because
788 reg-reg moves will be eliminated afterwards. However, there are quite
789 some cases where combine will be unable to fold comparison related insns,
790 thus for now don't do it.
791 register_pass (make_pass_sh_treg_combine (g, false, "sh_treg_combine1"),
792 PASS_POS_INSERT_AFTER, "ce1", 1);
793 */
794
795 /* Run sh_treg_combine pass after combine but before register allocation. */
796 register_pass (make_pass_sh_treg_combine (g, true, "sh_treg_combine2"),
797 PASS_POS_INSERT_AFTER, "split1", 1);
798
799 /* Run sh_treg_combine pass after register allocation and basic block
800 reordering as this sometimes creates new opportunities. */
801 register_pass (make_pass_sh_treg_combine (g, true, "sh_treg_combine3"),
802 PASS_POS_INSERT_AFTER, "split4", 1);
803
804 /* Optimize sett and clrt insns, by e.g. removing them if the T bit value
805 is known after a conditional branch.
806 This must be done after basic blocks and branch conditions have
807 stabilized and won't be changed by further passes. */
808 register_pass (make_pass_sh_optimize_sett_clrt (g, "sh_optimize_sett_clrt"),
809 PASS_POS_INSERT_BEFORE, "sched2", 1);
810 }
811
812 /* Implement TARGET_OPTION_OVERRIDE macro. Validate and override
813 various options, and do some machine dependent initialization. */
814 static void
sh_option_override(void)815 sh_option_override (void)
816 {
817 int regno;
818
819 SUBTARGET_OVERRIDE_OPTIONS;
820
821 sh_cpu = PROCESSOR_SH1;
822 assembler_dialect = 0;
823 if (TARGET_SH2)
824 sh_cpu = PROCESSOR_SH2;
825 if (TARGET_SH2E)
826 sh_cpu = PROCESSOR_SH2E;
827 if (TARGET_SH2A)
828 sh_cpu = PROCESSOR_SH2A;
829 if (TARGET_SH3)
830 sh_cpu = PROCESSOR_SH3;
831 if (TARGET_SH3E)
832 sh_cpu = PROCESSOR_SH3E;
833 if (TARGET_SH4)
834 {
835 assembler_dialect = 1;
836 sh_cpu = PROCESSOR_SH4;
837 }
838 if (TARGET_SH4A)
839 {
840 assembler_dialect = 1;
841 sh_cpu = PROCESSOR_SH4A;
842 }
843
844 /* User/priviledged mode is supported only on SH3* and SH4*.
845 Disable it for everything else. */
846 if (!TARGET_SH3 && TARGET_USERMODE)
847 TARGET_USERMODE = false;
848
849 if (! strcmp (sh_div_str, "call-div1"))
850 sh_div_strategy = SH_DIV_CALL_DIV1;
851 else if (! strcmp (sh_div_str, "call-fp") && TARGET_FPU_ANY)
852 sh_div_strategy = SH_DIV_CALL_FP;
853 else if (! strcmp (sh_div_str, "call-table") && TARGET_DYNSHIFT)
854 sh_div_strategy = SH_DIV_CALL_TABLE;
855 else
856 {
857 /* Pick one that makes most sense for the target in general.
858 It is not much good to use different functions depending on -Os,
859 since then we'll end up with two different functions when some of
860 the code is compiled for size, and some for speed. */
861
862 /* SH4 tends to emphasize speed. */
863 if (TARGET_HARD_SH4)
864 sh_div_strategy = SH_DIV_CALL_TABLE;
865 /* These have their own way of doing things. */
866 else if (TARGET_SH2A)
867 sh_div_strategy = SH_DIV_INTRINSIC;
868 /* SH1 .. SH3 cores often go into small-footprint systems, so
869 default to the smallest implementation available. */
870 else
871 sh_div_strategy = SH_DIV_CALL_DIV1;
872 }
873
874 if (sh_divsi3_libfunc[0])
875 ; /* User supplied - leave it alone. */
876 else if (TARGET_DIVIDE_CALL_FP)
877 sh_divsi3_libfunc = "__sdivsi3_i4";
878 else if (TARGET_DIVIDE_CALL_TABLE)
879 sh_divsi3_libfunc = "__sdivsi3_i4i";
880 else
881 sh_divsi3_libfunc = "__sdivsi3";
882
883 if (sh_branch_cost == -1)
884 {
885 /* The SH1 does not have delay slots, hence we get a pipeline stall
886 at every branch. The SH4 is superscalar, so the single delay slot
887 is not sufficient to keep both pipelines filled.
888 In any case, set the default branch cost to '2', as it results in
889 slightly overall smaller code and also enables some if conversions
890 that are required for matching special T bit related insns. */
891 sh_branch_cost = 2;
892 }
893
894 /* Set -mzdcbranch for SH4 / SH4A if not otherwise specified by the user. */
895 if (! global_options_set.x_TARGET_ZDCBRANCH && TARGET_HARD_SH4)
896 TARGET_ZDCBRANCH = 1;
897
898 /* FDPIC code is a special form of PIC, and the vast majority of code
899 generation constraints that apply to PIC also apply to FDPIC, so we
900 set flag_pic to avoid the need to check TARGET_FDPIC everywhere
901 flag_pic is checked. */
902 if (TARGET_FDPIC && !flag_pic)
903 flag_pic = 2;
904
905 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
906 if (! VALID_REGISTER_P (regno))
907 sh_register_names[regno][0] = '\0';
908
909 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++)
910 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno)))
911 sh_additional_register_names[regno][0] = '\0';
912
913 if (flag_pic && ! TARGET_PREFERGOT)
914 flag_no_function_cse = 1;
915
916 if (targetm.small_register_classes_for_mode_p (VOIDmode))
917 {
918 /* Never run scheduling before reload, since that can
919 break global alloc, and generates slower code anyway due
920 to the pressure on R0. */
921 /* Enable sched1 for SH4 if the user explicitly requests.
922 When sched1 is enabled, the ready queue will be reordered by
923 the target hooks if pressure is high. We can not do this for
924 PIC, SH3 and lower as they give spill failures for R0. */
925 if (!TARGET_HARD_SH4 || flag_pic)
926 flag_schedule_insns = 0;
927 /* ??? Current exception handling places basic block boundaries
928 after call_insns. It causes the high pressure on R0 and gives
929 spill failures for R0 in reload. See PR 22553 and the thread
930 on gcc-patches
931 <http://gcc.gnu.org/ml/gcc-patches/2005-10/msg00816.html>. */
932 else if (flag_exceptions)
933 {
934 if (flag_schedule_insns && global_options_set.x_flag_schedule_insns)
935 warning (0, "ignoring -fschedule-insns because of exception "
936 "handling bug");
937 flag_schedule_insns = 0;
938 }
939 else if (flag_schedule_insns
940 && !global_options_set.x_flag_schedule_insns)
941 flag_schedule_insns = 0;
942 }
943
944 /* Unwind info is not correct around the CFG unless either a frame
945 pointer is present or M_A_O_A is set. Fixing this requires rewriting
946 unwind info generation to be aware of the CFG and propagating states
947 around edges. */
948 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
949 || flag_exceptions || flag_non_call_exceptions)
950 && flag_omit_frame_pointer && !TARGET_ACCUMULATE_OUTGOING_ARGS)
951 {
952 warning (0, "unwind tables currently require either a frame pointer "
953 "or -maccumulate-outgoing-args for correctness");
954 TARGET_ACCUMULATE_OUTGOING_ARGS = 1;
955 }
956
957 if (flag_unsafe_math_optimizations)
958 {
959 /* Enable fsca insn for SH4A if not otherwise specified by the user. */
960 if (global_options_set.x_TARGET_FSCA == 0 && TARGET_SH4A_FP)
961 TARGET_FSCA = 1;
962
963 /* Enable fsrra insn for SH4A if not otherwise specified by the user. */
964 if (global_options_set.x_TARGET_FSRRA == 0 && TARGET_SH4A_FP)
965 TARGET_FSRRA = 1;
966 }
967
968 /* Allow fsrra insn only if -funsafe-math-optimizations and
969 -ffinite-math-only is enabled. */
970 TARGET_FSRRA = TARGET_FSRRA
971 && flag_unsafe_math_optimizations
972 && flag_finite_math_only;
973
974 /* If the -mieee option was not explicitly set by the user, turn it on
975 unless -ffinite-math-only was specified. See also PR 33135. */
976 if (! global_options_set.x_TARGET_IEEE)
977 TARGET_IEEE = ! flag_finite_math_only;
978
979 if (sh_fixed_range_str)
980 sh_fix_range (sh_fixed_range_str);
981
982 /* This target defaults to strict volatile bitfields. */
983 if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2))
984 flag_strict_volatile_bitfields = 1;
985
986 sh_override_options_after_change ();
987
988 /* Parse atomic model option and make sure it is valid for the current
989 target CPU. */
990 selected_atomic_model_
991 = parse_validate_atomic_model_option (sh_atomic_model_str);
992
993 register_sh_passes ();
994 }
995
996 /* Implement targetm.override_options_after_change. */
997
998 static void
sh_override_options_after_change(void)999 sh_override_options_after_change (void)
1000 {
1001 /* Adjust loop, jump and function alignment values (in bytes), if those
1002 were not specified by the user using -falign-loops, -falign-jumps
1003 and -falign-functions options.
1004 32 bit alignment is better for speed, because instructions can be
1005 fetched as a pair from a longword boundary. For size use 16 bit
1006 alignment to get more compact code.
1007 Aligning all jumps increases the code size, even if it might
1008 result in slightly faster code. Thus, it is set to the smallest
1009 alignment possible if not specified by the user. */
1010 if (align_loops == 0)
1011 align_loops = optimize_size ? 2 : 4;
1012
1013 if (align_jumps == 0)
1014 align_jumps = 2;
1015 else if (align_jumps < 2)
1016 align_jumps = 2;
1017
1018 if (align_functions == 0)
1019 align_functions = optimize_size ? 2 : 4;
1020
1021 /* The linker relaxation code breaks when a function contains
1022 alignments that are larger than that at the start of a
1023 compilation unit. */
1024 if (TARGET_RELAX)
1025 {
1026 int min_align = align_loops > align_jumps ? align_loops : align_jumps;
1027
1028 /* Also take possible .long constants / mova tables into account. */
1029 if (min_align < 4)
1030 min_align = 4;
1031 if (align_functions < min_align)
1032 align_functions = min_align;
1033 }
1034 }
1035
1036 /* Print the operand address in x to the stream. */
1037 static void
sh_print_operand_address(FILE * stream,machine_mode,rtx x)1038 sh_print_operand_address (FILE *stream, machine_mode /*mode*/, rtx x)
1039 {
1040 switch (GET_CODE (x))
1041 {
1042 case REG:
1043 case SUBREG:
1044 fprintf (stream, "@%s", reg_names[true_regnum (x)]);
1045 break;
1046
1047 case PLUS:
1048 {
1049 rtx base = XEXP (x, 0);
1050 rtx index = XEXP (x, 1);
1051
1052 switch (GET_CODE (index))
1053 {
1054 case CONST_INT:
1055 fprintf (stream, "@(%d,%s)", (int) INTVAL (index),
1056 reg_names[true_regnum (base)]);
1057 break;
1058
1059 case REG:
1060 case SUBREG:
1061 {
1062 int base_num = true_regnum (base);
1063 int index_num = true_regnum (index);
1064
1065 /* If base or index is R0, make sure that it comes first.
1066 Usually one of them will be R0, but the order might be wrong.
1067 If neither base nor index are R0 it's an error and we just
1068 pass it on to the assembler. This avoids silent wrong code
1069 bugs. */
1070 if (base_num == 0 && index_num != 0)
1071 std::swap (base_num, index_num);
1072
1073 fprintf (stream, "@(%s,%s)", reg_names[index_num],
1074 reg_names[base_num]);
1075 break;
1076 }
1077
1078 default:
1079 gcc_unreachable ();
1080 }
1081 }
1082 break;
1083
1084 case PRE_DEC:
1085 fprintf (stream, "@-%s", reg_names[true_regnum (XEXP (x, 0))]);
1086 break;
1087
1088 case POST_INC:
1089 fprintf (stream, "@%s+", reg_names[true_regnum (XEXP (x, 0))]);
1090 break;
1091
1092 default:
1093 x = mark_constant_pool_use (x);
1094 output_addr_const (stream, x);
1095 break;
1096 }
1097 }
1098
1099 /* Print operand x (an rtx) in assembler syntax to file stream
1100 according to modifier code.
1101
1102 '.' print a .s if insn needs delay slot
1103 ',' print LOCAL_LABEL_PREFIX
1104 '@' print trap, rte or rts depending upon pragma interruptness
1105 '#' output a nop if there is nothing to put in the delay slot
1106 ''' print likelihood suffix (/u for unlikely).
1107 '>' print branch target if -fverbose-asm
1108 'O' print a constant without the #
1109 'R' print the LSW of a dp value - changes if in little endian
1110 'S' print the MSW of a dp value - changes if in little endian
1111 'T' print the next word of a dp value - same as 'R' in big endian mode.
1112 'M' print .b / .w / .l / .s / .d suffix if operand is a MEM.
1113 'N' print 'r63' if the operand is (const_int 0).
1114 'd' print a V2SF reg as dN instead of fpN.
1115 'm' print a pair `base,offset' or `base,index', for LD and ST.
1116 'U' Likewise for {LD,ST}{HI,LO}.
1117 'V' print the position of a single bit set.
1118 'W' print the position of a single bit cleared.
1119 't' print a memory address which is a register.
1120 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
1121 'o' output an operator. */
1122 static void
sh_print_operand(FILE * stream,rtx x,int code)1123 sh_print_operand (FILE *stream, rtx x, int code)
1124 {
1125 int regno;
1126 machine_mode mode;
1127
1128 switch (code)
1129 {
1130 tree trapa_attr;
1131
1132 case '.':
1133 if (final_sequence
1134 && ! INSN_ANNULLED_BRANCH_P (final_sequence->insn (0))
1135 && get_attr_length (final_sequence->insn (1)))
1136 fprintf (stream, ASSEMBLER_DIALECT ? "/s" : ".s");
1137 break;
1138 case ',':
1139 fprintf (stream, "%s", LOCAL_LABEL_PREFIX);
1140 break;
1141 case '@':
1142 trapa_attr = lookup_attribute ("trap_exit",
1143 DECL_ATTRIBUTES (current_function_decl));
1144 if (trapa_attr)
1145 fprintf (stream, "trapa #%ld",
1146 (long) TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (trapa_attr))));
1147 else if (sh_cfun_interrupt_handler_p ())
1148 {
1149 if (sh_cfun_resbank_handler_p ())
1150 fprintf (stream, "resbank\n");
1151 fprintf (stream, "rte");
1152 }
1153 else
1154 fprintf (stream, "rts");
1155 break;
1156 case '#':
1157 /* Output a nop if there's nothing in the delay slot. */
1158 if (dbr_sequence_length () == 0)
1159 fprintf (stream, "\n\tnop");
1160 break;
1161 case '\'':
1162 {
1163 rtx note = find_reg_note (current_output_insn, REG_BR_PROB, 0);
1164
1165 if (note
1166 && profile_probability::from_reg_br_prob_note (XINT (note, 0))
1167 < profile_probability::even ())
1168 fputs ("/u", stream);
1169 break;
1170 }
1171 case '>':
1172 if (flag_verbose_asm && JUMP_LABEL (current_output_insn))
1173 {
1174 fputs ("\t! target: ", stream);
1175 output_addr_const (stream, JUMP_LABEL (current_output_insn));
1176 }
1177 break;
1178 case 'O':
1179 x = mark_constant_pool_use (x);
1180 output_addr_const (stream, x);
1181 break;
1182 /* N.B.: %R / %S / %T adjust memory addresses by four.
1183 While they can be used to access 64 bit parts of a larger value
1184 held in general purpose registers, that won't work with memory -
1185 neither for fp registers, since the frxx names are used. */
1186 case 'R':
1187 if (REG_P (x) || GET_CODE (x) == SUBREG)
1188 {
1189 regno = true_regnum (x);
1190 regno += FP_REGISTER_P (regno) ? 1 : SH_REG_LSW_OFFSET;
1191 fputs (reg_names[regno], (stream));
1192 }
1193 else if (MEM_P (x))
1194 {
1195 x = adjust_address (x, SImode, 4 * SH_REG_LSW_OFFSET);
1196 sh_print_operand_address (stream, GET_MODE (x), XEXP (x, 0));
1197 }
1198 else
1199 {
1200 rtx sub = NULL_RTX;
1201
1202 mode = GET_MODE (x);
1203 if (mode == VOIDmode)
1204 mode = DImode;
1205 if (GET_MODE_SIZE (mode) >= 8)
1206 sub = simplify_subreg (SImode, x, mode, 4 * SH_REG_LSW_OFFSET);
1207 if (sub)
1208 sh_print_operand (stream, sub, 0);
1209 else
1210 output_operand_lossage ("invalid operand to %%R");
1211 }
1212 break;
1213 case 'S':
1214 if (REG_P (x) || GET_CODE (x) == SUBREG)
1215 {
1216 regno = true_regnum (x);
1217 regno += FP_REGISTER_P (regno) ? 0 : SH_REG_MSW_OFFSET;
1218 fputs (reg_names[regno], (stream));
1219 }
1220 else if (MEM_P (x))
1221 {
1222 x = adjust_address (x, SImode, 4 * SH_REG_MSW_OFFSET);
1223 sh_print_operand_address (stream, GET_MODE (x), XEXP (x, 0));
1224 }
1225 else
1226 {
1227 rtx sub = NULL_RTX;
1228
1229 mode = GET_MODE (x);
1230 if (mode == VOIDmode)
1231 mode = DImode;
1232 if (GET_MODE_SIZE (mode) >= 8)
1233 sub = simplify_subreg (SImode, x, mode, 4 * SH_REG_MSW_OFFSET);
1234 if (sub)
1235 sh_print_operand (stream, sub, 0);
1236 else
1237 output_operand_lossage ("invalid operand to %%S");
1238 }
1239 break;
1240 case 'T':
1241 /* Next word of a double. */
1242 switch (GET_CODE (x))
1243 {
1244 case REG:
1245 fputs (reg_names[REGNO (x) + 1], (stream));
1246 break;
1247 case MEM:
1248 {
1249 machine_mode mode = GET_MODE (x);
1250 if (GET_CODE (XEXP (x, 0)) != PRE_DEC
1251 && GET_CODE (XEXP (x, 0)) != POST_INC)
1252 x = adjust_address (x, SImode, 4);
1253 sh_print_operand_address (stream, mode, XEXP (x, 0));
1254 }
1255 break;
1256 default:
1257 break;
1258 }
1259 break;
1260
1261 case 't':
1262 gcc_assert (MEM_P (x));
1263 x = XEXP (x, 0);
1264 switch (GET_CODE (x))
1265 {
1266 case REG:
1267 case SUBREG:
1268 sh_print_operand (stream, x, 0);
1269 break;
1270 default:
1271 break;
1272 }
1273 break;
1274
1275 case 'o':
1276 switch (GET_CODE (x))
1277 {
1278 case PLUS: fputs ("add", stream); break;
1279 case MINUS: fputs ("sub", stream); break;
1280 case MULT: fputs ("mul", stream); break;
1281 case DIV: fputs ("div", stream); break;
1282 case EQ: fputs ("eq", stream); break;
1283 case NE: fputs ("ne", stream); break;
1284 case GT: case LT: fputs ("gt", stream); break;
1285 case GE: case LE: fputs ("ge", stream); break;
1286 case GTU: case LTU: fputs ("gtu", stream); break;
1287 case GEU: case LEU: fputs ("geu", stream); break;
1288 default:
1289 break;
1290 }
1291 break;
1292 case 'M':
1293 if (MEM_P (x))
1294 {
1295 switch (GET_MODE (x))
1296 {
1297 case E_QImode: fputs (".b", stream); break;
1298 case E_HImode: fputs (".w", stream); break;
1299 case E_SImode: fputs (".l", stream); break;
1300 case E_SFmode: fputs (".s", stream); break;
1301 case E_DFmode: fputs (".d", stream); break;
1302 default: gcc_unreachable ();
1303 }
1304 }
1305 break;
1306
1307 case 'm':
1308 gcc_assert (MEM_P (x));
1309 x = XEXP (x, 0);
1310 /* Fall through. */
1311 case 'U':
1312 switch (GET_CODE (x))
1313 {
1314 case REG:
1315 case SUBREG:
1316 sh_print_operand (stream, x, 0);
1317 fputs (", 0", stream);
1318 break;
1319
1320 case PLUS:
1321 sh_print_operand (stream, XEXP (x, 0), 0);
1322 fputs (", ", stream);
1323 sh_print_operand (stream, XEXP (x, 1), 0);
1324 break;
1325
1326 default:
1327 gcc_unreachable ();
1328 }
1329 break;
1330
1331 case 'V':
1332 {
1333 int num = exact_log2 (INTVAL (x));
1334 gcc_assert (num >= 0);
1335 fprintf (stream, "#%d", num);
1336 }
1337 break;
1338
1339 case 'W':
1340 {
1341 int num = exact_log2 (~INTVAL (x));
1342 gcc_assert (num >= 0);
1343 fprintf (stream, "#%d", num);
1344 }
1345 break;
1346
1347 case 'd':
1348 gcc_assert (REG_P (x) && GET_MODE (x) == V2SFmode);
1349
1350 fprintf ((stream), "d%s", reg_names[REGNO (x)] + 1);
1351 break;
1352
1353 case 'N':
1354 if (x == CONST0_RTX (GET_MODE (x)))
1355 {
1356 fprintf ((stream), "r63");
1357 break;
1358 }
1359 goto default_output;
1360 case 'u':
1361 if (CONST_INT_P (x))
1362 {
1363 fprintf ((stream), "%u", (unsigned) INTVAL (x) & (0x10000 - 1));
1364 break;
1365 }
1366 /* Fall through. */
1367
1368 default_output:
1369 default:
1370 regno = 0;
1371 mode = GET_MODE (x);
1372
1373 switch (GET_CODE (x))
1374 {
1375 case TRUNCATE:
1376 {
1377 rtx inner = XEXP (x, 0);
1378 int offset = 0;
1379 machine_mode inner_mode;
1380
1381 /* We might see SUBREGs with vector mode registers inside. */
1382 if (GET_CODE (inner) == SUBREG
1383 && (GET_MODE_SIZE (GET_MODE (inner))
1384 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
1385 && subreg_lowpart_p (inner))
1386 inner = SUBREG_REG (inner);
1387 if (CONST_INT_P (inner))
1388 {
1389 x = GEN_INT (trunc_int_for_mode (INTVAL (inner), GET_MODE (x)));
1390 goto default_output;
1391 }
1392 inner_mode = GET_MODE (inner);
1393 if (GET_CODE (inner) == SUBREG
1394 && (GET_MODE_SIZE (GET_MODE (inner))
1395 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
1396 && REG_P (SUBREG_REG (inner)))
1397 {
1398 offset = subreg_regno_offset (REGNO (SUBREG_REG (inner)),
1399 GET_MODE (SUBREG_REG (inner)),
1400 SUBREG_BYTE (inner),
1401 GET_MODE (inner));
1402 inner = SUBREG_REG (inner);
1403 }
1404 if (!REG_P (inner) || GET_MODE_SIZE (inner_mode) > 8)
1405 abort ();
1406 /* Floating point register pairs are always big endian;
1407 general purpose registers are 64 bit wide. */
1408 regno = REGNO (inner);
1409 regno = (hard_regno_nregs (regno, inner_mode)
1410 - hard_regno_nregs (regno, mode))
1411 + offset;
1412 x = inner;
1413 goto reg;
1414 }
1415 case SIGN_EXTEND:
1416 x = XEXP (x, 0);
1417 goto reg;
1418 case SUBREG:
1419 gcc_assert (SUBREG_BYTE (x) == 0
1420 && REG_P (SUBREG_REG (x)));
1421
1422 x = SUBREG_REG (x);
1423 /* Fall through. */
1424
1425 reg:
1426 case REG:
1427 regno += REGNO (x);
1428 if (FP_REGISTER_P (regno)
1429 && mode == V16SFmode)
1430 fprintf ((stream), "mtrx%s", reg_names[regno] + 2);
1431 else if (FP_REGISTER_P (REGNO (x))
1432 && mode == V4SFmode)
1433 fprintf ((stream), "fv%s", reg_names[regno] + 2);
1434 else if (REG_P (x)
1435 && mode == V2SFmode)
1436 fprintf ((stream), "fp%s", reg_names[regno] + 2);
1437 else if (FP_REGISTER_P (REGNO (x))
1438 && GET_MODE_SIZE (mode) > 4)
1439 fprintf ((stream), "d%s", reg_names[regno] + 1);
1440 else
1441 fputs (reg_names[regno], (stream));
1442 break;
1443
1444 case MEM:
1445 output_address (GET_MODE (x), XEXP (x, 0));
1446 break;
1447
1448 default:
1449 fputc ('#', stream);
1450 output_addr_const (stream, x);
1451 break;
1452 }
1453 break;
1454 }
1455 }
1456
1457 static bool
sh_print_operand_punct_valid_p(unsigned char code)1458 sh_print_operand_punct_valid_p (unsigned char code)
1459 {
1460 return (code == '.' || code == '#' || code == '@' || code == ','
1461 || code == '$' || code == '\'' || code == '>');
1462 }
1463
1464 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
1465 static bool
sh_asm_output_addr_const_extra(FILE * file,rtx x)1466 sh_asm_output_addr_const_extra (FILE *file, rtx x)
1467 {
1468 if (GET_CODE (x) == UNSPEC)
1469 {
1470 switch (XINT (x, 1))
1471 {
1472 case UNSPEC_PIC:
1473 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */
1474 output_addr_const (file, XVECEXP (x, 0, 0));
1475 break;
1476 case UNSPEC_GOT:
1477 output_addr_const (file, XVECEXP (x, 0, 0));
1478 fputs ("@GOT", file);
1479 break;
1480 case UNSPEC_GOTOFF:
1481 output_addr_const (file, XVECEXP (x, 0, 0));
1482 fputs ("@GOTOFF", file);
1483 break;
1484 case UNSPEC_PLT:
1485 output_addr_const (file, XVECEXP (x, 0, 0));
1486 fputs ("@PLT", file);
1487 break;
1488 case UNSPEC_GOTPLT:
1489 output_addr_const (file, XVECEXP (x, 0, 0));
1490 fputs ("@GOTPLT", file);
1491 break;
1492 case UNSPEC_PCREL:
1493 output_addr_const (file, XVECEXP (x, 0, 0));
1494 fputs ("@PCREL", file);
1495 break;
1496 case UNSPEC_DTPOFF:
1497 output_addr_const (file, XVECEXP (x, 0, 0));
1498 fputs ("@DTPOFF", file);
1499 break;
1500 case UNSPEC_GOTTPOFF:
1501 output_addr_const (file, XVECEXP (x, 0, 0));
1502 fputs ("@GOTTPOFF", file);
1503 break;
1504 case UNSPEC_TPOFF:
1505 output_addr_const (file, XVECEXP (x, 0, 0));
1506 fputs ("@TPOFF", file);
1507 break;
1508 case UNSPEC_CALLER:
1509 {
1510 char name[32];
1511 /* LPCS stands for Label for PIC Call Site. */
1512 targetm.asm_out.generate_internal_label (name, "LPCS",
1513 INTVAL (XVECEXP (x, 0, 0)));
1514 assemble_name (file, name);
1515 }
1516 break;
1517 case UNSPEC_SYMOFF:
1518 output_addr_const (file, XVECEXP (x, 0, 0));
1519 fputc ('-', file);
1520 if (GET_CODE (XVECEXP (x, 0, 1)) == CONST)
1521 {
1522 fputc ('(', file);
1523 output_addr_const (file, XVECEXP (x, 0, 1));
1524 fputc (')', file);
1525 }
1526 else
1527 output_addr_const (file, XVECEXP (x, 0, 1));
1528 break;
1529 case UNSPEC_PCREL_SYMOFF:
1530 output_addr_const (file, XVECEXP (x, 0, 0));
1531 fputs ("-(", file);
1532 output_addr_const (file, XVECEXP (x, 0, 1));
1533 fputs ("-.)", file);
1534 break;
1535 case UNSPEC_GOTFUNCDESC:
1536 output_addr_const (file, XVECEXP (x, 0, 0));
1537 fputs ("@GOTFUNCDESC", file);
1538 break;
1539 case UNSPEC_GOTOFFFUNCDESC:
1540 output_addr_const (file, XVECEXP (x, 0, 0));
1541 fputs ("@GOTOFFFUNCDESC", file);
1542 break;
1543 default:
1544 return false;
1545 }
1546 return true;
1547 }
1548 else
1549 return false;
1550 }
1551
1552 /* Encode symbol attributes of a SYMBOL_REF into its
1553 SYMBOL_REF_FLAGS. */
1554 static void
sh_encode_section_info(tree decl,rtx rtl,int first)1555 sh_encode_section_info (tree decl, rtx rtl, int first)
1556 {
1557 default_encode_section_info (decl, rtl, first);
1558
1559 if (TREE_CODE (decl) == FUNCTION_DECL
1560 && sh2a_function_vector_p (decl) && TARGET_SH2A)
1561 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FUNCVEC_FUNCTION;
1562 }
1563
1564 /* Prepare operands for a move define_expand; specifically, one of the
1565 operands must be in a register. */
1566 void
prepare_move_operands(rtx operands[],machine_mode mode)1567 prepare_move_operands (rtx operands[], machine_mode mode)
1568 {
1569 if ((mode == SImode || mode == DImode)
1570 && flag_pic
1571 && ! ((mode == Pmode || mode == ptr_mode)
1572 && tls_symbolic_operand (operands[1], Pmode) != TLS_MODEL_NONE))
1573 {
1574 rtx temp;
1575 if (SYMBOLIC_CONST_P (operands[1]))
1576 {
1577 if (MEM_P (operands[0]))
1578 operands[1] = force_reg (Pmode, operands[1]);
1579 else
1580 {
1581 temp = (!can_create_pseudo_p ()
1582 ? operands[0]
1583 : gen_reg_rtx (Pmode));
1584 operands[1] = legitimize_pic_address (operands[1], mode, temp);
1585 }
1586 }
1587 else if (GET_CODE (operands[1]) == CONST
1588 && GET_CODE (XEXP (operands[1], 0)) == PLUS
1589 && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0)))
1590 {
1591 temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
1592 temp = legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
1593 mode, temp);
1594 operands[1] = expand_binop (mode, add_optab, temp,
1595 XEXP (XEXP (operands[1], 0), 1),
1596 (!can_create_pseudo_p ()
1597 ? temp
1598 : gen_reg_rtx (Pmode)),
1599 0, OPTAB_LIB_WIDEN);
1600 }
1601 }
1602
1603 if (! reload_in_progress && ! reload_completed)
1604 {
1605 /* Copy the source to a register if both operands aren't registers. */
1606 if (! register_operand (operands[0], mode)
1607 && ! register_operand (operands[1], mode))
1608 operands[1] = copy_to_mode_reg (mode, operands[1]);
1609
1610 if (MEM_P (operands[0]) && ! memory_operand (operands[0], mode))
1611 {
1612 /* This is like change_address_1 (operands[0], mode, 0, 1) ,
1613 except that we can't use that function because it is static. */
1614 rtx new_rtx = change_address (operands[0], mode, 0);
1615 MEM_COPY_ATTRIBUTES (new_rtx, operands[0]);
1616 operands[0] = new_rtx;
1617 }
1618
1619 /* This case can happen while generating code to move the result
1620 of a library call to the target. Reject `st r0,@(rX,rY)' because
1621 reload will fail to find a spill register for rX, since r0 is already
1622 being used for the source. */
1623 else if (refers_to_regno_p (R0_REG, operands[1])
1624 && MEM_P (operands[0])
1625 && GET_CODE (XEXP (operands[0], 0)) == PLUS
1626 && REG_P (XEXP (XEXP (operands[0], 0), 1)))
1627 operands[1] = copy_to_mode_reg (mode, operands[1]);
1628
1629 /* When the displacement addressing is used, RA will assign r0 to
1630 the pseudo register operand for the QI/HImode load/store.
1631 This tends to make a long live range for R0 and might cause
1632 anomalous register spills in some case with LRA. See PR
1633 target/55212.
1634 We split possible load/store to two move insns via r0 so as to
1635 shorten R0 live range. It will make some codes worse but will
1636 win on average for LRA.
1637 Also when base+index addressing is used and the index term is
1638 a subreg, LRA assumes that more hard registers can be available
1639 in some situation. It isn't the case for SH in the problematic
1640 case. We can pre-allocate R0 for that index term to avoid
1641 the issue. See PR target/66591. */
1642 else if (sh_lra_p ()
1643 && ! TARGET_SH2A
1644 && ((REG_P (operands[0]) && MEM_P (operands[1]))
1645 || (REG_P (operands[1]) && MEM_P (operands[0]))))
1646 {
1647 bool load_p = REG_P (operands[0]);
1648 rtx reg = operands[load_p ? 0 : 1];
1649 rtx adr = XEXP (operands[load_p ? 1 : 0], 0);
1650
1651 if ((mode == QImode || mode == HImode)
1652 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
1653 && GET_CODE (adr) == PLUS
1654 && REG_P (XEXP (adr, 0))
1655 && (REGNO (XEXP (adr, 0)) >= FIRST_PSEUDO_REGISTER)
1656 && CONST_INT_P (XEXP (adr, 1))
1657 && INTVAL (XEXP (adr, 1)) != 0
1658 && sh_legitimate_index_p (mode, XEXP (adr, 1), false, true))
1659 {
1660 rtx r0_rtx = gen_rtx_REG (mode, R0_REG);
1661 emit_move_insn (r0_rtx, operands[1]);
1662 operands[1] = r0_rtx;
1663 }
1664 if (REGNO (reg) >= FIRST_PSEUDO_REGISTER
1665 && GET_CODE (adr) == PLUS
1666 && REG_P (XEXP (adr, 0))
1667 && (REGNO (XEXP (adr, 0)) >= FIRST_PSEUDO_REGISTER)
1668 && SUBREG_P (XEXP (adr, 1))
1669 && REG_P (SUBREG_REG (XEXP (adr, 1))))
1670 {
1671 rtx r0_rtx = gen_rtx_REG (GET_MODE (XEXP (adr, 1)), R0_REG);
1672 emit_move_insn (r0_rtx, XEXP (adr, 1));
1673 XEXP (adr, 1) = r0_rtx;
1674 }
1675 }
1676 }
1677
1678 if (mode == Pmode || mode == ptr_mode)
1679 {
1680 rtx op0 = operands[0];
1681 rtx op1 = operands[1];
1682 rtx opc;
1683 if (GET_CODE (op1) == CONST
1684 && GET_CODE (XEXP (op1, 0)) == PLUS
1685 && (tls_symbolic_operand (XEXP (XEXP (op1, 0), 0), Pmode)
1686 != TLS_MODEL_NONE))
1687 {
1688 opc = XEXP (XEXP (op1, 0), 1);
1689 op1 = XEXP (XEXP (op1, 0), 0);
1690 }
1691 else
1692 opc = NULL_RTX;
1693
1694 enum tls_model tls_kind;
1695
1696 if (! reload_in_progress && ! reload_completed
1697 && (tls_kind = tls_symbolic_operand (op1, Pmode)) != TLS_MODEL_NONE)
1698 {
1699 rtx tga_op1, tga_ret, tmp, tmp2;
1700
1701 if (! flag_pic
1702 && (tls_kind == TLS_MODEL_GLOBAL_DYNAMIC
1703 || tls_kind == TLS_MODEL_LOCAL_DYNAMIC
1704 || tls_kind == TLS_MODEL_INITIAL_EXEC))
1705 {
1706 static int got_labelno;
1707 /* Don't schedule insns for getting GOT address when
1708 the first scheduling is enabled, to avoid spill
1709 failures for R0. */
1710 if (flag_schedule_insns)
1711 emit_insn (gen_blockage ());
1712 emit_insn (gen_GOTaddr2picreg (GEN_INT (++got_labelno)));
1713 emit_use (gen_rtx_REG (SImode, PIC_REG));
1714 if (flag_schedule_insns)
1715 emit_insn (gen_blockage ());
1716 }
1717
1718 switch (tls_kind)
1719 {
1720 case TLS_MODEL_GLOBAL_DYNAMIC:
1721 tga_ret = gen_rtx_REG (Pmode, R0_REG);
1722 if (TARGET_FDPIC)
1723 emit_move_insn (gen_rtx_REG (Pmode, PIC_REG),
1724 sh_get_fdpic_reg_initial_val ());
1725 emit_call_insn (gen_tls_global_dynamic (tga_ret, op1));
1726 tmp = gen_reg_rtx (Pmode);
1727 emit_move_insn (tmp, tga_ret);
1728 op1 = tmp;
1729 break;
1730
1731 case TLS_MODEL_LOCAL_DYNAMIC:
1732 tga_ret = gen_rtx_REG (Pmode, R0_REG);
1733 if (TARGET_FDPIC)
1734 emit_move_insn (gen_rtx_REG (Pmode, PIC_REG),
1735 sh_get_fdpic_reg_initial_val ());
1736 emit_call_insn (gen_tls_local_dynamic (tga_ret, op1));
1737
1738 tmp = gen_reg_rtx (Pmode);
1739 emit_move_insn (tmp, tga_ret);
1740
1741 if (register_operand (op0, Pmode))
1742 tmp2 = op0;
1743 else
1744 tmp2 = gen_reg_rtx (Pmode);
1745
1746 emit_insn (gen_symDTPOFF2reg (tmp2, op1, tmp));
1747 op1 = tmp2;
1748 break;
1749
1750 case TLS_MODEL_INITIAL_EXEC:
1751 tga_op1 = !can_create_pseudo_p () ? op0 : gen_reg_rtx (Pmode);
1752 tmp = gen_sym2GOTTPOFF (op1);
1753 if (TARGET_FDPIC)
1754 emit_move_insn (gen_rtx_REG (Pmode, PIC_REG),
1755 sh_get_fdpic_reg_initial_val ());
1756 emit_insn (gen_tls_initial_exec (tga_op1, tmp));
1757 op1 = tga_op1;
1758 break;
1759
1760 case TLS_MODEL_LOCAL_EXEC:
1761 tmp2 = gen_reg_rtx (Pmode);
1762 emit_insn (gen_store_gbr (tmp2));
1763 tmp = gen_reg_rtx (Pmode);
1764 emit_insn (gen_symTPOFF2reg (tmp, op1));
1765
1766 if (register_operand (op0, Pmode))
1767 op1 = op0;
1768 else
1769 op1 = gen_reg_rtx (Pmode);
1770
1771 emit_insn (gen_addsi3 (op1, tmp, tmp2));
1772 break;
1773
1774 default:
1775 gcc_unreachable ();
1776 }
1777 if (opc)
1778 emit_insn (gen_addsi3 (op1, op1, force_reg (SImode, opc)));
1779 operands[1] = op1;
1780 }
1781 }
1782
1783 if (SH_OFFSETS_MUST_BE_WITHIN_SECTIONS_P)
1784 {
1785 rtx base, offset;
1786 split_const (operands[1], &base, &offset);
1787
1788 if (GET_CODE (base) == SYMBOL_REF
1789 && !offset_within_block_p (base, INTVAL (offset)))
1790 {
1791 rtx tmp = can_create_pseudo_p () ? gen_reg_rtx (mode) : operands[0];
1792 emit_move_insn (tmp, base);
1793 if (!arith_operand (offset, mode))
1794 offset = force_reg (mode, offset);
1795 emit_insn (gen_add3_insn (operands[0], tmp, offset));
1796 }
1797 }
1798 }
1799
1800 /* Implement the canonicalize_comparison target hook for the combine
1801 pass. For the target hook this function is invoked via
1802 sh_canonicalize_comparison. This function is also re-used to
1803 canonicalize comparisons in cbranch pattern expanders. */
1804 static void
sh_canonicalize_comparison(enum rtx_code & cmp,rtx & op0,rtx & op1,machine_mode mode,bool op0_preserve_value)1805 sh_canonicalize_comparison (enum rtx_code& cmp, rtx& op0, rtx& op1,
1806 machine_mode mode,
1807 bool op0_preserve_value)
1808 {
1809 /* When invoked from within the combine pass the mode is not specified,
1810 so try to get it from one of the operands. */
1811 if (mode == VOIDmode)
1812 mode = GET_MODE (op0);
1813 if (mode == VOIDmode)
1814 mode = GET_MODE (op1);
1815
1816 // We need to have a mode to do something useful here.
1817 if (mode == VOIDmode)
1818 return;
1819
1820 // Currently, we don't deal with floats here.
1821 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
1822 return;
1823
1824 // Make sure that the constant operand is the second operand.
1825 if (CONST_INT_P (op0) && !CONST_INT_P (op1))
1826 {
1827 if (op0_preserve_value)
1828 return;
1829
1830 std::swap (op0, op1);
1831 cmp = swap_condition (cmp);
1832 }
1833
1834 if (CONST_INT_P (op1))
1835 {
1836 /* Try to adjust the constant operand in such a way that available
1837 comparison insns can be utilized better and the constant can be
1838 loaded with a 'mov #imm,Rm' insn. This avoids a load from the
1839 constant pool. */
1840 const HOST_WIDE_INT val = INTVAL (op1);
1841
1842 /* x > -1 --> x >= 0
1843 x > 0xFFFFFF7F --> x >= 0xFFFFFF80
1844 x <= -1 --> x < 0
1845 x <= 0xFFFFFF7F --> x < 0xFFFFFF80 */
1846 if ((val == -1 || val == -0x81) && (cmp == GT || cmp == LE))
1847 {
1848 cmp = cmp == GT ? GE : LT;
1849 op1 = gen_int_mode (val + 1, mode);
1850 }
1851
1852 /* x >= 1 --> x > 0
1853 x >= 0x80 --> x > 0x7F
1854 x < 1 --> x <= 0
1855 x < 0x80 --> x <= 0x7F */
1856 else if ((val == 1 || val == 0x80) && (cmp == GE || cmp == LT))
1857 {
1858 cmp = cmp == GE ? GT : LE;
1859 op1 = gen_int_mode (val - 1, mode);
1860 }
1861
1862 /* unsigned x >= 1 --> x != 0
1863 unsigned x < 1 --> x == 0 */
1864 else if (val == 1 && (cmp == GEU || cmp == LTU))
1865 {
1866 cmp = cmp == GEU ? NE : EQ;
1867 op1 = CONST0_RTX (mode);
1868 }
1869
1870 /* unsigned x >= 0x80 --> unsigned x > 0x7F
1871 unsigned x < 0x80 --> unsigned x < 0x7F */
1872 else if (val == 0x80 && (cmp == GEU || cmp == LTU))
1873 {
1874 cmp = cmp == GEU ? GTU : LEU;
1875 op1 = gen_int_mode (val - 1, mode);
1876 }
1877
1878 /* unsigned x > 0 --> x != 0
1879 unsigned x <= 0 --> x == 0 */
1880 else if (val == 0 && (cmp == GTU || cmp == LEU))
1881 cmp = cmp == GTU ? NE : EQ;
1882
1883 /* unsigned x > 0x7FFFFFFF --> signed x < 0
1884 unsigned x <= 0x7FFFFFFF --> signed x >= 0 */
1885 else if (mode == SImode && (cmp == GTU || cmp == LEU)
1886 && val == 0x7FFFFFFF)
1887 {
1888 cmp = cmp == GTU ? LT : GE;
1889 op1 = const0_rtx;
1890 }
1891
1892 /* unsigned x >= 0x80000000 --> signed x < 0
1893 unsigned x < 0x80000000 --> signed x >= 0 */
1894 else if (mode == SImode && (cmp == GEU || cmp == LTU)
1895 && (unsigned HOST_WIDE_INT)val
1896 == ((unsigned HOST_WIDE_INT)0x7FFFFFFF + 1))
1897 {
1898 cmp = cmp == GEU ? LT : GE;
1899 op1 = const0_rtx;
1900 }
1901 }
1902 }
1903
1904 /* This function implements the canonicalize_comparison target hook.
1905 This wrapper around the internally used sh_canonicalize_comparison
1906 function is needed to do the enum rtx_code <-> int conversion.
1907 Target hooks cannot use enum rtx_code in its definition. */
1908 static void
sh_canonicalize_comparison(int * code,rtx * op0,rtx * op1,bool op0_preserve_value)1909 sh_canonicalize_comparison (int *code, rtx *op0, rtx *op1,
1910 bool op0_preserve_value)
1911 {
1912 enum rtx_code tmp_code = (enum rtx_code)*code;
1913 sh_canonicalize_comparison (tmp_code, *op0, *op1,
1914 VOIDmode, op0_preserve_value);
1915 *code = (int)tmp_code;
1916 }
1917
1918 /* This function implements the legitimate_combined_insn target hook,
1919 which the combine pass uses to early reject combined insns, before
1920 it tries to recog the insn and determine its cost. */
1921 static bool
sh_legitimate_combined_insn(rtx_insn * insn)1922 sh_legitimate_combined_insn (rtx_insn* insn)
1923 {
1924 /* Reject combinations of memory loads and zero extensions, as these
1925 interfere with other combine patterns such as zero extracts and bit
1926 tests. The SH2A movu.{b|w} insns are formed later in the
1927 'sh_optimize_extu_exts' pass after combine/split1. */
1928 rtx p = PATTERN (insn);
1929 if (GET_CODE (p) == SET
1930 && REG_P (XEXP (p, 0)) && GET_MODE (XEXP (p, 0)) == SImode
1931 && GET_CODE (XEXP (p, 1)) == ZERO_EXTEND
1932 && MEM_P (XEXP (XEXP (p, 1), 0)))
1933 return false;
1934
1935 return true;
1936 }
1937
1938 bool
sh_fixed_condition_code_regs(unsigned int * p1,unsigned int * p2)1939 sh_fixed_condition_code_regs (unsigned int* p1, unsigned int* p2)
1940 {
1941 *p1 = T_REG;
1942 *p2 = INVALID_REGNUM;
1943 return true;
1944 }
1945
1946 /* Try to calculate the branch distance of a conditional branch in bytes.
1947
1948 FIXME: Because of PR 59189 we can't use the CFG here. Instead just
1949 walk from this insn into the next (fall-through) basic block and see if
1950 we hit the label. */
1951 unsigned int
sh_cbranch_distance(rtx_insn * _cbranch_insn,unsigned int max_dist)1952 sh_cbranch_distance (rtx_insn* _cbranch_insn, unsigned int max_dist)
1953 {
1954 rtx_jump_insn* cbranch_insn = safe_as_a<rtx_jump_insn*> (_cbranch_insn);
1955
1956 if (dump_file)
1957 {
1958 fprintf (dump_file, "sh_cbranch_distance insn = \n");
1959 print_rtl_single (dump_file, cbranch_insn);
1960 }
1961
1962 unsigned int dist = 0;
1963
1964 for (rtx_insn* i = next_nonnote_insn (cbranch_insn);
1965 i != NULL && dist < max_dist; i = next_nonnote_insn (i))
1966 {
1967 const unsigned int i_len = get_attr_length (i);
1968 dist += i_len;
1969
1970 if (dump_file)
1971 fprintf (dump_file, " insn %d length = %u dist = %u\n",
1972 INSN_UID (i), i_len, dist);
1973
1974 if (rtx_code_label* l = dyn_cast<rtx_code_label*> (i))
1975 {
1976 if (l == cbranch_insn->jump_target ())
1977 {
1978 if (dump_file)
1979 fprintf (dump_file, " cbranch dist = %u\n", dist);
1980 return dist;
1981 }
1982 break;
1983 }
1984 }
1985
1986 if (dump_file)
1987 fprintf (dump_file, " cbranch dist = unknown\n");
1988
1989 return unknown_cbranch_distance;
1990 }
1991
1992 enum rtx_code
prepare_cbranch_operands(rtx * operands,machine_mode mode,enum rtx_code comparison)1993 prepare_cbranch_operands (rtx *operands, machine_mode mode,
1994 enum rtx_code comparison)
1995 {
1996 gcc_assert (can_create_pseudo_p ());
1997
1998 if (comparison == LAST_AND_UNUSED_RTX_CODE)
1999 comparison = GET_CODE (operands[0]);
2000
2001 sh_canonicalize_comparison (comparison, operands[1], operands[2],
2002 mode, false);
2003
2004 rtx op1 = operands[1];
2005 operands[1] = force_reg (mode, op1);
2006
2007 /* When we are handling DImode comparisons, we want to keep constants so
2008 that we can optimize the component comparisons; however, memory loads
2009 are better issued as a whole so that they can be scheduled well.
2010 SImode equality comparisons allow I08 constants, but only when they
2011 compare r0. Hence, if operands[1] has to be loaded from somewhere else
2012 into a register, that register might as well be r0, and we allow the
2013 constant. If it is already in a register, this is likely to be
2014 allocated to a different hard register, thus we load the constant into
2015 a register unless it is zero. */
2016 if (!REG_P (operands[2])
2017 && (!CONST_INT_P (operands[2])
2018 || (mode == SImode && operands[2] != CONST0_RTX (SImode)
2019 && ((comparison != EQ && comparison != NE)
2020 || (REG_P (op1) && REGNO (op1) != R0_REG)
2021 || !satisfies_constraint_I08 (operands[2])))))
2022 operands[2] = force_reg (mode, operands[2]);
2023
2024 return comparison;
2025 }
2026
2027 static void
expand_cbranchsi4(rtx * operands,enum rtx_code comparison,profile_probability probability)2028 expand_cbranchsi4 (rtx *operands, enum rtx_code comparison,
2029 profile_probability probability)
2030 {
2031 rtx (*branch_expander) (rtx) = gen_branch_true;
2032 comparison = prepare_cbranch_operands (operands, SImode, comparison);
2033 switch (comparison)
2034 {
2035 case NE: case LT: case LE: case LTU: case LEU:
2036 comparison = reverse_condition (comparison);
2037 branch_expander = gen_branch_false;
2038 default: ;
2039 }
2040 emit_insn (gen_rtx_SET (get_t_reg_rtx (),
2041 gen_rtx_fmt_ee (comparison, SImode,
2042 operands[1], operands[2])));
2043 rtx_insn *jump = emit_jump_insn (branch_expander (operands[3]));
2044 if (probability.initialized_p ())
2045 add_reg_br_prob_note (jump, probability);
2046 }
2047
2048 void
expand_cbranchsi4(rtx * operands,enum rtx_code comparison)2049 expand_cbranchsi4 (rtx *operands, enum rtx_code comparison)
2050 {
2051 expand_cbranchsi4 (operands, comparison,
2052 profile_probability::uninitialized ());
2053 }
2054
2055 /* ??? How should we distribute probabilities when more than one branch
2056 is generated. So far we only have some ad-hoc observations:
2057 - If the operands are random, they are likely to differ in both parts.
2058 - If comparing items in a hash chain, the operands are random or equal;
2059 operation should be EQ or NE.
2060 - If items are searched in an ordered tree from the root, we can expect
2061 the highpart to be unequal about half of the time; operation should be
2062 an inequality comparison, operands non-constant, and overall probability
2063 about 50%. Likewise for quicksort.
2064 - Range checks will be often made against constants. Even if we assume for
2065 simplicity an even distribution of the non-constant operand over a
2066 sub-range here, the same probability could be generated with differently
2067 wide sub-ranges - as long as the ratio of the part of the subrange that
2068 is before the threshold to the part that comes after the threshold stays
2069 the same. Thus, we can't really tell anything here;
2070 assuming random distribution is at least simple.
2071 */
2072 bool
expand_cbranchdi4(rtx * operands,enum rtx_code comparison)2073 expand_cbranchdi4 (rtx *operands, enum rtx_code comparison)
2074 {
2075 enum rtx_code msw_taken, msw_skip, lsw_taken;
2076 rtx_code_label *skip_label = NULL;
2077 rtx op1h, op1l, op2h, op2l;
2078 int num_branches;
2079 profile_probability prob, rev_prob;
2080 profile_probability msw_taken_prob = profile_probability::uninitialized (),
2081 msw_skip_prob = profile_probability::uninitialized (),
2082 lsw_taken_prob = profile_probability::uninitialized ();
2083
2084 comparison = prepare_cbranch_operands (operands, DImode, comparison);
2085 op1h = gen_highpart_mode (SImode, DImode, operands[1]);
2086 op2h = gen_highpart_mode (SImode, DImode, operands[2]);
2087 op1l = gen_lowpart (SImode, operands[1]);
2088 op2l = gen_lowpart (SImode, operands[2]);
2089 msw_taken = msw_skip = lsw_taken = LAST_AND_UNUSED_RTX_CODE;
2090 prob = split_branch_probability;
2091 rev_prob = prob.invert ();
2092 switch (comparison)
2093 {
2094 case EQ:
2095 msw_skip = NE;
2096 lsw_taken = EQ;
2097 if (prob.initialized_p ())
2098 {
2099 /* FIXME: This is not optimal. We do not really know the probablity
2100 that values differ by MCW only, but we should probably distribute
2101 probabilities more evenly. */
2102 msw_skip_prob = rev_prob;
2103 lsw_taken_prob = prob > profile_probability::never ()
2104 ? profile_probability::guessed_always ()
2105 : profile_probability::guessed_never ();
2106 }
2107 break;
2108 case NE:
2109 msw_taken = NE;
2110 msw_taken_prob = prob;
2111 lsw_taken = NE;
2112 lsw_taken_prob = profile_probability::guessed_never ();
2113 break;
2114 case GTU: case GT:
2115 msw_taken = comparison;
2116 if (CONST_INT_P (op2l) && INTVAL (op2l) == -1)
2117 break;
2118 if (comparison != GTU || op2h != CONST0_RTX (SImode))
2119 msw_skip = swap_condition (msw_taken);
2120 lsw_taken = GTU;
2121 break;
2122 case GEU: case GE:
2123 if (op2l == CONST0_RTX (SImode))
2124 msw_taken = comparison;
2125 else
2126 {
2127 msw_taken = comparison == GE ? GT : GTU;
2128 msw_skip = swap_condition (msw_taken);
2129 lsw_taken = GEU;
2130 }
2131 break;
2132 case LTU: case LT:
2133 msw_taken = comparison;
2134 if (op2l == CONST0_RTX (SImode))
2135 break;
2136 msw_skip = swap_condition (msw_taken);
2137 lsw_taken = LTU;
2138 break;
2139 case LEU: case LE:
2140 if (CONST_INT_P (op2l) && INTVAL (op2l) == -1)
2141 msw_taken = comparison;
2142 else
2143 {
2144 lsw_taken = LEU;
2145 if (comparison == LE)
2146 msw_taken = LT;
2147 else if (op2h != CONST0_RTX (SImode))
2148 msw_taken = LTU;
2149 else
2150 {
2151 msw_skip = swap_condition (LTU);
2152 break;
2153 }
2154 msw_skip = swap_condition (msw_taken);
2155 }
2156 break;
2157 default: return false;
2158 }
2159 num_branches = ((msw_taken != LAST_AND_UNUSED_RTX_CODE)
2160 + (msw_skip != LAST_AND_UNUSED_RTX_CODE)
2161 + (lsw_taken != LAST_AND_UNUSED_RTX_CODE));
2162 if (comparison != EQ && comparison != NE && num_branches > 1)
2163 {
2164 if (!CONSTANT_P (operands[2])
2165 && prob.initialized_p ()
2166 && prob.to_reg_br_prob_base () >= (int) (REG_BR_PROB_BASE * 3 / 8U)
2167 && prob.to_reg_br_prob_base () <= (int) (REG_BR_PROB_BASE * 5 / 8U))
2168 {
2169 msw_taken_prob = prob.apply_scale (1, 2);
2170 msw_skip_prob = rev_prob.apply_scale (REG_BR_PROB_BASE,
2171 rev_prob.to_reg_br_prob_base ()
2172 + REG_BR_PROB_BASE);
2173 lsw_taken_prob = prob;
2174 }
2175 else
2176 {
2177 msw_taken_prob = prob;
2178 msw_skip_prob = profile_probability::guessed_always ();
2179 /* ??? If we have a constant op2h, should we use that when
2180 calculating lsw_taken_prob? */
2181 lsw_taken_prob = prob;
2182 }
2183 }
2184 operands[1] = op1h;
2185 operands[2] = op2h;
2186
2187 if (msw_taken != LAST_AND_UNUSED_RTX_CODE)
2188 expand_cbranchsi4 (operands, msw_taken, msw_taken_prob);
2189 if (msw_skip != LAST_AND_UNUSED_RTX_CODE)
2190 {
2191 rtx taken_label = operands[3];
2192
2193 /* Operands were possibly modified, but msw_skip doesn't expect this.
2194 Always use the original ones. */
2195 if (msw_taken != LAST_AND_UNUSED_RTX_CODE)
2196 {
2197 operands[1] = op1h;
2198 operands[2] = op2h;
2199 }
2200
2201 operands[3] = skip_label = gen_label_rtx ();
2202 expand_cbranchsi4 (operands, msw_skip, msw_skip_prob);
2203 operands[3] = taken_label;
2204 }
2205 operands[1] = op1l;
2206 operands[2] = op2l;
2207 if (lsw_taken != LAST_AND_UNUSED_RTX_CODE)
2208 expand_cbranchsi4 (operands, lsw_taken, lsw_taken_prob);
2209 if (msw_skip != LAST_AND_UNUSED_RTX_CODE)
2210 emit_label (skip_label);
2211 return true;
2212 }
2213
2214 /* Given an operand, return 1 if the evaluated operand plugged into an
2215 if_then_else will result in a branch_true, 0 if branch_false, or
2216 -1 if neither nor applies. The truth table goes like this:
2217
2218 op | cmpval | code | result
2219 ---------+--------+---------+--------------------
2220 T (0) | 0 | EQ (1) | 0 = 0 ^ (0 == 1)
2221 T (0) | 1 | EQ (1) | 1 = 0 ^ (1 == 1)
2222 T (0) | 0 | NE (0) | 1 = 0 ^ (0 == 0)
2223 T (0) | 1 | NE (0) | 0 = 0 ^ (1 == 0)
2224 !T (1) | 0 | EQ (1) | 1 = 1 ^ (0 == 1)
2225 !T (1) | 1 | EQ (1) | 0 = 1 ^ (1 == 1)
2226 !T (1) | 0 | NE (0) | 0 = 1 ^ (0 == 0)
2227 !T (1) | 1 | NE (0) | 1 = 1 ^ (1 == 0) */
2228 int
sh_eval_treg_value(rtx op)2229 sh_eval_treg_value (rtx op)
2230 {
2231 if (t_reg_operand (op, GET_MODE (op)))
2232 return 1;
2233 if (negt_reg_operand (op, GET_MODE (op)))
2234 return 0;
2235
2236 rtx_code code = GET_CODE (op);
2237 if ((code != EQ && code != NE) || !CONST_INT_P (XEXP (op, 1)))
2238 return -1;
2239
2240 int cmpop = code == EQ ? 1 : 0;
2241 int cmpval = INTVAL (XEXP (op, 1));
2242 if (cmpval != 0 && cmpval != 1)
2243 return -1;
2244
2245 int t;
2246 if (t_reg_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0))))
2247 t = 0;
2248 else if (negt_reg_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0))))
2249 t = 1;
2250 else
2251 return -1;
2252
2253 return t ^ (cmpval == cmpop);
2254 }
2255
2256 /* Emit INSN, possibly in a PARALLEL with an USE/CLOBBER of FPSCR bits in case
2257 of floating-point comparisons. */
2258 static void
sh_emit_set_t_insn(rtx insn,machine_mode mode)2259 sh_emit_set_t_insn (rtx insn, machine_mode mode)
2260 {
2261 if (TARGET_FPU_ANY && GET_MODE_CLASS (mode) == MODE_FLOAT
2262 && GET_CODE (insn) != PARALLEL)
2263 {
2264 insn = gen_rtx_PARALLEL (VOIDmode,
2265 gen_rtvec (3, insn,
2266 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, FPSCR_STAT_REG)),
2267 gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, FPSCR_MODES_REG))));
2268 }
2269 emit_insn (insn);
2270 }
2271
2272 /* Prepare the operands for an scc instruction; make sure that the
2273 compare has been done and the result is in T_REG. */
2274 void
sh_emit_scc_to_t(enum rtx_code code,rtx op0,rtx op1)2275 sh_emit_scc_to_t (enum rtx_code code, rtx op0, rtx op1)
2276 {
2277 rtx t_reg = get_t_reg_rtx ();
2278 enum rtx_code oldcode = code;
2279
2280 /* First need a compare insn. */
2281 switch (code)
2282 {
2283 case NE:
2284 /* It isn't possible to handle this case. */
2285 gcc_unreachable ();
2286 case LT:
2287 code = GT;
2288 break;
2289 case LE:
2290 code = GE;
2291 break;
2292 case LTU:
2293 code = GTU;
2294 break;
2295 case LEU:
2296 code = GEU;
2297 break;
2298 default:
2299 break;
2300 }
2301 if (code != oldcode)
2302 std::swap (op0, op1);
2303
2304 machine_mode mode = GET_MODE (op0);
2305 if (mode == VOIDmode)
2306 mode = GET_MODE (op1);
2307
2308 op0 = force_reg (mode, op0);
2309 if ((code != EQ && code != NE
2310 && (op1 != const0_rtx
2311 || code == GTU || code == GEU || code == LTU || code == LEU))
2312 || (mode == DImode && op1 != const0_rtx)
2313 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
2314 op1 = force_reg (mode, op1);
2315
2316 sh_emit_set_t_insn (gen_rtx_SET (t_reg,
2317 gen_rtx_fmt_ee (code, SImode, op0, op1)),
2318 mode);
2319 }
2320
2321 /* Called from the md file, set up the operands of a compare instruction. */
2322 void
sh_emit_compare_and_branch(rtx * operands,machine_mode mode)2323 sh_emit_compare_and_branch (rtx *operands, machine_mode mode)
2324 {
2325 enum rtx_code code = GET_CODE (operands[0]);
2326 enum rtx_code branch_code;
2327 rtx op0 = operands[1];
2328 rtx op1 = operands[2];
2329 rtx insn;
2330 bool need_ccmpeq = false;
2331
2332 if (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT)
2333 {
2334 op0 = force_reg (mode, op0);
2335 op1 = force_reg (mode, op1);
2336 }
2337 else
2338 {
2339 if (code != EQ || mode == DImode)
2340 {
2341 /* Force args into regs, since we can't use constants here. */
2342 op0 = force_reg (mode, op0);
2343 if (op1 != const0_rtx || code == GTU || code == GEU)
2344 op1 = force_reg (mode, op1);
2345 }
2346 }
2347
2348 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2349 {
2350 if (code == LT
2351 || (code == LE && TARGET_IEEE && TARGET_SH2E)
2352 || (code == GE && !(TARGET_IEEE && TARGET_SH2E)))
2353 {
2354 std::swap (op0, op1);
2355 code = swap_condition (code);
2356 }
2357
2358 /* GE becomes fcmp/gt+fcmp/eq, for SH2E and TARGET_IEEE only. */
2359 if (code == GE)
2360 {
2361 gcc_assert (TARGET_IEEE && TARGET_SH2E);
2362 need_ccmpeq = true;
2363 code = GT;
2364 }
2365
2366 /* Now we can have EQ, NE, GT, LE. NE and LE are then transformed
2367 to EQ/GT respectively. */
2368 gcc_assert (code == EQ || code == GT || code == NE || code == LE);
2369 }
2370
2371 switch (code)
2372 {
2373 case EQ:
2374 case GT:
2375 case GE:
2376 case GTU:
2377 case GEU:
2378 branch_code = code;
2379 break;
2380 case NE:
2381 case LT:
2382 case LE:
2383 case LTU:
2384 case LEU:
2385 branch_code = reverse_condition (code);
2386 break;
2387 default:
2388 gcc_unreachable ();
2389 }
2390
2391 insn = gen_rtx_SET (get_t_reg_rtx (),
2392 gen_rtx_fmt_ee (branch_code, SImode, op0, op1));
2393
2394 sh_emit_set_t_insn (insn, mode);
2395 if (need_ccmpeq)
2396 sh_emit_set_t_insn (gen_ieee_ccmpeqsf_t (op0, op1), mode);
2397
2398 if (branch_code == code)
2399 emit_jump_insn (gen_branch_true (operands[3]));
2400 else
2401 emit_jump_insn (gen_branch_false (operands[3]));
2402 }
2403
2404 void
sh_emit_compare_and_set(rtx * operands,machine_mode mode)2405 sh_emit_compare_and_set (rtx *operands, machine_mode mode)
2406 {
2407 enum rtx_code code = GET_CODE (operands[1]);
2408 rtx op0 = operands[2];
2409 rtx op1 = operands[3];
2410 rtx_code_label *lab = NULL;
2411 bool invert = false;
2412
2413 op0 = force_reg (mode, op0);
2414 if ((code != EQ && code != NE
2415 && (op1 != const0_rtx
2416 || code == GTU || code == GEU || code == LTU || code == LEU))
2417 || (mode == DImode && op1 != const0_rtx)
2418 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
2419 op1 = force_reg (mode, op1);
2420
2421 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2422 {
2423 if (code == LT || code == LE)
2424 {
2425 std::swap (op0, op1);
2426 code = swap_condition (code);
2427 }
2428 if (code == GE)
2429 {
2430 if (TARGET_IEEE)
2431 {
2432 lab = gen_label_rtx ();
2433 sh_emit_scc_to_t (EQ, op0, op1);
2434 emit_jump_insn (gen_branch_true (lab));
2435 code = GT;
2436 }
2437 else
2438 {
2439 code = LT;
2440 invert = true;
2441 }
2442 }
2443 }
2444
2445 if (code == NE)
2446 {
2447 code = EQ;
2448 invert = true;
2449 }
2450
2451 sh_emit_scc_to_t (code, op0, op1);
2452 if (lab)
2453 emit_label (lab);
2454 if (invert)
2455 emit_insn (gen_movnegt (operands[0], get_t_reg_rtx ()));
2456 else
2457 emit_move_insn (operands[0], get_t_reg_rtx ());
2458 }
2459
2460 /* Functions to output assembly code. */
2461
2462 /* Return a sequence of instructions to perform DI or DF move.
2463
2464 Since the SH cannot move a DI or DF in one instruction, we have
2465 to take care when we see overlapping source and dest registers. */
2466 const char *
output_movedouble(rtx insn ATTRIBUTE_UNUSED,rtx operands[],machine_mode mode)2467 output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
2468 machine_mode mode)
2469 {
2470 rtx dst = operands[0];
2471 rtx src = operands[1];
2472
2473 if (MEM_P (dst)
2474 && GET_CODE (XEXP (dst, 0)) == PRE_DEC)
2475 return "mov.l %T1,%0" "\n"
2476 " mov.l %1,%0";
2477
2478 if (register_operand (dst, mode)
2479 && register_operand (src, mode))
2480 {
2481 if (REGNO (src) == MACH_REG)
2482 return "sts mach,%S0" "\n"
2483 " sts macl,%R0";
2484
2485 /* When mov.d r1,r2 do r2->r3 then r1->r2;
2486 when mov.d r1,r0 do r1->r0 then r2->r1. */
2487 if (REGNO (src) + 1 == REGNO (dst))
2488 return "mov %T1,%T0" "\n"
2489 " mov %1,%0";
2490 else
2491 return "mov %1,%0" "\n"
2492 " mov %T1,%T0";
2493 }
2494 else if (CONST_INT_P (src))
2495 {
2496 if (INTVAL (src) < 0)
2497 output_asm_insn ("mov #-1,%S0", operands);
2498 else
2499 output_asm_insn ("mov #0,%S0", operands);
2500
2501 return "mov %1,%R0";
2502 }
2503 else if (MEM_P (src))
2504 {
2505 int ptrreg = -1;
2506 int dreg = REGNO (dst);
2507 rtx inside = XEXP (src, 0);
2508
2509 switch (GET_CODE (inside))
2510 {
2511 case REG:
2512 ptrreg = REGNO (inside);
2513 break;
2514
2515 case SUBREG:
2516 ptrreg = subreg_regno (inside);
2517 break;
2518
2519 case PLUS:
2520 ptrreg = REGNO (XEXP (inside, 0));
2521 /* ??? A r0+REG address shouldn't be possible here, because it isn't
2522 an offsettable address. Unfortunately, offsettable addresses use
2523 QImode to check the offset, and a QImode offsettable address
2524 requires r0 for the other operand, which is not currently
2525 supported, so we can't use the 'o' constraint.
2526 Thus we must check for and handle r0+REG addresses here.
2527 We punt for now, since this is likely very rare. */
2528 gcc_assert (!REG_P (XEXP (inside, 1)));
2529 break;
2530
2531 case LABEL_REF:
2532 return "mov.l %1,%0" "\n"
2533 " mov.l %1+4,%T0";
2534 case POST_INC:
2535 return "mov.l %1,%0" "\n"
2536 " mov.l %1,%T0";
2537 default:
2538 gcc_unreachable ();
2539 }
2540
2541 /* Work out the safe way to copy. Copy into the second half first. */
2542 if (dreg == ptrreg)
2543 return "mov.l %T1,%T0" "\n"
2544 " mov.l %1,%0";
2545 }
2546
2547 return "mov.l %1,%0" "\n"
2548 " mov.l %T1,%T0";
2549 }
2550
2551 /* Print an instruction which would have gone into a delay slot after
2552 another instruction, but couldn't because the other instruction expanded
2553 into a sequence where putting the slot insn at the end wouldn't work. */
2554 static void
print_slot(rtx_sequence * seq)2555 print_slot (rtx_sequence *seq)
2556 {
2557 final_scan_insn (seq->insn (1), asm_out_file, optimize, 1, NULL);
2558
2559 seq->insn (1)->set_deleted ();
2560 }
2561
2562 const char *
output_far_jump(rtx_insn * insn,rtx op)2563 output_far_jump (rtx_insn *insn, rtx op)
2564 {
2565 struct { rtx lab, reg, op; } this_jmp;
2566 rtx_code_label *braf_base_lab = NULL;
2567 const char *jump;
2568 int far;
2569 int offset = branch_dest (insn) - INSN_ADDRESSES (INSN_UID (insn));
2570 rtx_insn *prev;
2571
2572 this_jmp.lab = gen_label_rtx ();
2573
2574 if (TARGET_SH2
2575 && offset >= -32764
2576 && offset - get_attr_length (insn) <= 32766
2577 && ! CROSSING_JUMP_P (insn))
2578 {
2579 far = 0;
2580 jump = "mov.w %O0,%1" "\n"
2581 " braf %1";
2582 }
2583 else
2584 {
2585 far = 1;
2586 if (flag_pic)
2587 {
2588 if (TARGET_SH2)
2589 jump = "mov.l %O0,%1" "\n"
2590 " braf %1";
2591 else
2592 jump = "mov.l r0,@-r15" "\n"
2593 " mova %O0,r0" "\n"
2594 " mov.l @r0,%1" "\n"
2595 " add r0,%1" "\n"
2596 " mov.l @r15+,r0" "\n"
2597 " jmp @%1";
2598 }
2599 else
2600 jump = "mov.l %O0,%1" "\n"
2601 " jmp @%1";
2602 }
2603 /* If we have a scratch register available, use it. */
2604 if (NONJUMP_INSN_P ((prev = prev_nonnote_insn (insn)))
2605 && INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
2606 {
2607 this_jmp.reg = SET_DEST (XVECEXP (PATTERN (prev), 0, 0));
2608 if (REGNO (this_jmp.reg) == R0_REG && flag_pic && ! TARGET_SH2)
2609 jump = "mov.l r1,@-r15" "\n"
2610 " mova %O0,r0" "\n"
2611 " mov.l @r0,r1" "\n"
2612 " add r1,r0" "\n"
2613 " mov.l @r15+,r1" "\n"
2614 " jmp @%1";
2615 output_asm_insn (jump, &this_jmp.lab);
2616 if (dbr_sequence_length ())
2617 print_slot (final_sequence);
2618 else
2619 output_asm_insn ("nop", 0);
2620 }
2621 else
2622 {
2623 /* Output the delay slot insn first if any. */
2624 if (dbr_sequence_length ())
2625 print_slot (final_sequence);
2626
2627 this_jmp.reg = gen_rtx_REG (SImode, 13);
2628 output_asm_insn ("mov.l r13,@-r15", 0);
2629 output_asm_insn (jump, &this_jmp.lab);
2630 output_asm_insn ("mov.l @r15+,r13", 0);
2631 }
2632 if (far && flag_pic && TARGET_SH2)
2633 {
2634 braf_base_lab = gen_label_rtx ();
2635 (*targetm.asm_out.internal_label) (asm_out_file, "L",
2636 CODE_LABEL_NUMBER (braf_base_lab));
2637 }
2638 if (far)
2639 output_asm_insn (".align 2", 0);
2640 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (this_jmp.lab));
2641 this_jmp.op = op;
2642 if (far && flag_pic)
2643 {
2644 if (TARGET_SH2)
2645 this_jmp.lab = braf_base_lab;
2646 output_asm_insn (".long %O2-%O0", &this_jmp.lab);
2647 }
2648 else
2649 output_asm_insn (far ? ".long %O2" : ".word %O2-%O0", &this_jmp.lab);
2650 return "";
2651 }
2652
2653 /* Local label counter, used for constants in the pool and inside
2654 pattern branches. */
2655 static int lf = 100;
2656
2657 /* Output code for ordinary branches. */
2658 const char *
output_branch(int logic,rtx_insn * insn,rtx * operands)2659 output_branch (int logic, rtx_insn *insn, rtx *operands)
2660 {
2661 switch (get_attr_length (insn))
2662 {
2663 case 6:
2664 /* This can happen if filling the delay slot has caused a forward
2665 branch to exceed its range (we could reverse it, but only
2666 when we know we won't overextend other branches; this should
2667 best be handled by relaxation).
2668 It can also happen when other condbranches hoist delay slot insn
2669 from their destination, thus leading to code size increase.
2670 But the branch will still be in the range -4092..+4098 bytes. */
2671 if (! TARGET_RELAX)
2672 {
2673 int label = lf++;
2674 /* The call to print_slot will clobber the operands. */
2675 rtx op0 = operands[0];
2676
2677 /* If the instruction in the delay slot is annulled (true), then
2678 there is no delay slot where we can put it now. The only safe
2679 place for it is after the label. final will do that by default. */
2680
2681 if (final_sequence
2682 && ! INSN_ANNULLED_BRANCH_P (final_sequence->insn (0))
2683 && get_attr_length (final_sequence->insn (1)))
2684 {
2685 asm_fprintf (asm_out_file, "\tb%s%ss\t%LLF%d\n", logic ? "f" : "t",
2686 ASSEMBLER_DIALECT ? "/" : ".", label);
2687 print_slot (final_sequence);
2688 }
2689 else
2690 asm_fprintf (asm_out_file, "\tb%s\t%LLF%d\n", logic ? "f" : "t", label);
2691
2692 output_asm_insn ("bra\t%l0", &op0);
2693 fprintf (asm_out_file, "\tnop\n");
2694 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
2695
2696 return "";
2697 }
2698 /* FALLTHRU */
2699 /* When relaxing, handle this like a short branch. The linker
2700 will fix it up if it still doesn't fit after relaxation. */
2701 case 2:
2702 return logic ? "bt%.\t%l0" : "bf%.\t%l0";
2703
2704 /* These are for SH2e, in which we have to account for the
2705 extra nop because of the hardware bug in annulled branches. */
2706 case 8:
2707 if (! TARGET_RELAX)
2708 {
2709 int label = lf++;
2710
2711 gcc_assert (!final_sequence
2712 || !(INSN_ANNULLED_BRANCH_P
2713 (XVECEXP (final_sequence, 0, 0))));
2714 asm_fprintf (asm_out_file, "b%s%ss\t%LLF%d\n",
2715 logic ? "f" : "t",
2716 ASSEMBLER_DIALECT ? "/" : ".", label);
2717 fprintf (asm_out_file, "\tnop\n");
2718 output_asm_insn ("bra\t%l0", operands);
2719 fprintf (asm_out_file, "\tnop\n");
2720 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
2721
2722 return "";
2723 }
2724 /* FALLTHRU */
2725 case 4:
2726 {
2727 char buffer[10];
2728
2729 sprintf (buffer, "b%s%ss\t%%l0",
2730 logic ? "t" : "f",
2731 ASSEMBLER_DIALECT ? "/" : ".");
2732 output_asm_insn (buffer, &operands[0]);
2733 return "nop";
2734 }
2735
2736 default:
2737 /* There should be no longer branches now - that would
2738 indicate that something has destroyed the branches set
2739 up in machine_dependent_reorg. */
2740 gcc_unreachable ();
2741 }
2742 }
2743
2744 /* Output a code sequence for INSN using TEMPL with OPERANDS; but before,
2745 fill in operands 9 as a label to the successor insn.
2746 We try to use jump threading where possible.
2747 IF CODE matches the comparison in the IF_THEN_ELSE of a following jump,
2748 we assume the jump is taken. I.e. EQ means follow jmp and bf, NE means
2749 follow jmp and bt, if the address is in range. */
2750 const char *
output_branchy_insn(enum rtx_code code,const char * templ,rtx_insn * insn,rtx * operands)2751 output_branchy_insn (enum rtx_code code, const char *templ,
2752 rtx_insn *insn, rtx *operands)
2753 {
2754 rtx_insn *next_insn = NEXT_INSN (insn);
2755
2756 if (next_insn && JUMP_P (next_insn) && condjump_p (next_insn))
2757 {
2758 rtx src = SET_SRC (PATTERN (next_insn));
2759 if (GET_CODE (src) == IF_THEN_ELSE && GET_CODE (XEXP (src, 0)) != code)
2760 {
2761 /* Following branch not taken */
2762 rtx_code_label *lab = gen_label_rtx ();
2763 emit_label_after (lab, next_insn);
2764 INSN_ADDRESSES_NEW (lab,
2765 INSN_ADDRESSES (INSN_UID (next_insn))
2766 + get_attr_length (next_insn));
2767 operands[9] = lab;
2768 return templ;
2769 }
2770 else
2771 {
2772 int offset = (branch_dest (next_insn)
2773 - INSN_ADDRESSES (INSN_UID (next_insn)) + 4);
2774 if (offset >= -252 && offset <= 258)
2775 {
2776 if (GET_CODE (src) == IF_THEN_ELSE)
2777 /* branch_true */
2778 src = XEXP (src, 1);
2779 operands[9] = src;
2780 return templ;
2781 }
2782 }
2783 }
2784 rtx_code_label *lab = gen_label_rtx ();
2785 emit_label_after (lab, insn);
2786 INSN_ADDRESSES_NEW (lab,
2787 INSN_ADDRESSES (INSN_UID (insn))
2788 + get_attr_length (insn));
2789 operands[9] = lab;
2790 return templ;
2791 }
2792
2793 const char *
output_ieee_ccmpeq(rtx_insn * insn,rtx * operands)2794 output_ieee_ccmpeq (rtx_insn *insn, rtx *operands)
2795 {
2796 return output_branchy_insn (NE, "bt %l9" "\n"
2797 " fcmp/eq %1,%0",
2798 insn, operands);
2799 }
2800
2801 /* Output the start of the assembler file. */
2802 static void
sh_file_start(void)2803 sh_file_start (void)
2804 {
2805 default_file_start ();
2806
2807 if (TARGET_ELF)
2808 /* We need to show the text section with the proper
2809 attributes as in TEXT_SECTION_ASM_OP, before dwarf2out
2810 emits it without attributes in TEXT_SECTION_ASM_OP, else GAS
2811 will complain. We can teach GAS specifically about the
2812 default attributes for our choice of text section, but
2813 then we would have to change GAS again if/when we change
2814 the text section name. */
2815 fprintf (asm_out_file, "%s\n", TEXT_SECTION_ASM_OP);
2816 else
2817 /* Switch to the data section so that the coffsem symbol
2818 isn't in the text section. */
2819 switch_to_section (data_section);
2820
2821 if (TARGET_LITTLE_ENDIAN)
2822 fputs ("\t.little\n", asm_out_file);
2823 }
2824
2825 /* Implementation of TARGET_ASM_INTEGER for SH. Pointers to functions
2826 need to be output as pointers to function descriptors for
2827 FDPIC. */
2828
2829 static bool
sh_assemble_integer(rtx value,unsigned int size,int aligned_p)2830 sh_assemble_integer (rtx value, unsigned int size, int aligned_p)
2831 {
2832 if (TARGET_FDPIC && size == UNITS_PER_WORD
2833 && GET_CODE (value) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (value))
2834 {
2835 fputs ("\t.long\t", asm_out_file);
2836 output_addr_const (asm_out_file, value);
2837 fputs ("@FUNCDESC\n", asm_out_file);
2838 return true;
2839 }
2840 return default_assemble_integer (value, size, aligned_p);
2841 }
2842
2843 /* Check if PAT includes UNSPEC_CALLER unspec pattern. */
2844 static bool
unspec_caller_rtx_p(rtx pat)2845 unspec_caller_rtx_p (rtx pat)
2846 {
2847 rtx base, offset;
2848 split_const (pat, &base, &offset);
2849
2850 if (GET_CODE (base) == UNSPEC)
2851 {
2852 if (XINT (base, 1) == UNSPEC_CALLER)
2853 return true;
2854 for (int i = 0; i < XVECLEN (base, 0); i++)
2855 if (unspec_caller_rtx_p (XVECEXP (base, 0, i)))
2856 return true;
2857 }
2858 return false;
2859 }
2860
2861 /* Indicate that INSN cannot be duplicated. This is true for insn
2862 that generates a unique label. */
2863 static bool
sh_cannot_copy_insn_p(rtx_insn * insn)2864 sh_cannot_copy_insn_p (rtx_insn *insn)
2865 {
2866 if (!reload_completed || !flag_pic)
2867 return false;
2868
2869 if (!NONJUMP_INSN_P (insn))
2870 return false;
2871 if (asm_noperands (insn) >= 0)
2872 return false;
2873
2874 rtx pat = PATTERN (insn);
2875
2876 if (GET_CODE (pat) == CLOBBER || GET_CODE (pat) == USE)
2877 return false;
2878
2879 if (TARGET_FDPIC && GET_CODE (pat) == PARALLEL)
2880 {
2881 rtx t = XVECEXP (pat, 0, XVECLEN (pat, 0) - 1);
2882 if (GET_CODE (t) == USE && unspec_caller_rtx_p (XEXP (t, 0)))
2883 return true;
2884 }
2885
2886 if (GET_CODE (pat) != SET)
2887 return false;
2888 pat = SET_SRC (pat);
2889
2890 if (unspec_caller_rtx_p (pat))
2891 return true;
2892
2893 return false;
2894 }
2895
2896 /* Number of instructions used to make an arithmetic right shift by N. */
2897 static const char ashiftrt_insns[] =
2898 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
2899
2900 /* Description of a logical left or right shift, when expanded to a sequence
2901 of 1/2/8/16 shifts.
2902 Notice that one bit right shifts clobber the T bit. One bit left shifts
2903 are done with an 'add Rn,Rm' insn and thus do not clobber the T bit. */
2904 enum
2905 {
2906 ASHL_CLOBBERS_T = 1 << 0,
2907 LSHR_CLOBBERS_T = 1 << 1
2908 };
2909
2910 struct ashl_lshr_sequence
2911 {
2912 char insn_count;
2913 signed char amount[6];
2914 char clobbers_t;
2915 };
2916
2917 static const struct ashl_lshr_sequence ashl_lshr_seq[32] =
2918 {
2919 { 0, { 0 }, 0 }, // 0
2920 { 1, { 1 }, LSHR_CLOBBERS_T },
2921 { 1, { 2 }, 0 },
2922 { 2, { 2, 1 }, LSHR_CLOBBERS_T },
2923 { 2, { 2, 2 }, 0 }, // 4
2924 { 3, { 2, 1, 2 }, LSHR_CLOBBERS_T },
2925 { 3, { 2, 2, 2 }, 0 },
2926 { 4, { 2, 2, 1, 2 }, LSHR_CLOBBERS_T },
2927 { 1, { 8 }, 0 }, // 8
2928 { 2, { 8, 1 }, LSHR_CLOBBERS_T },
2929 { 2, { 8, 2 }, 0 },
2930 { 3, { 8, 1, 2 }, LSHR_CLOBBERS_T },
2931 { 3, { 8, 2, 2 }, 0 }, // 12
2932 { 4, { 8, 2, 1, 2 }, LSHR_CLOBBERS_T },
2933 { 3, { 8, -2, 8 }, 0 },
2934 { 3, { 8, -1, 8 }, ASHL_CLOBBERS_T },
2935 { 1, { 16 }, 0 }, // 16
2936 { 2, { 16, 1 }, LSHR_CLOBBERS_T },
2937 { 2, { 16, 2 }, 0 },
2938 { 3, { 16, 1, 2 }, LSHR_CLOBBERS_T },
2939 { 3, { 16, 2, 2 }, 0 }, // 20
2940 { 4, { 16, 2, 1, 2 }, LSHR_CLOBBERS_T },
2941 { 3, { 16, -2, 8 }, 0 },
2942 { 3, { 16, -1, 8 }, ASHL_CLOBBERS_T },
2943 { 2, { 16, 8 }, 0 }, // 24
2944 { 3, { 16, 1, 8 }, LSHR_CLOBBERS_T },
2945 { 3, { 16, 8, 2 }, 0 },
2946 { 4, { 16, 8, 1, 2 }, LSHR_CLOBBERS_T },
2947 { 4, { 16, 8, 2, 2 }, 0 }, // 28
2948 { 4, { 16, -1, -2, 16 }, ASHL_CLOBBERS_T },
2949 { 3, { 16, -2, 16 }, 0 },
2950
2951 /* For a right shift by 31 a 2 insn shll-movt sequence can be used.
2952 For a left shift by 31 a 2 insn and-rotl sequences can be used.
2953 However, the shift-and combiner code needs this entry here to be in
2954 terms of real shift insns. */
2955 { 3, { 16, -1, 16 }, ASHL_CLOBBERS_T }
2956 };
2957
2958 /* Individual shift amounts for shift amounts < 16, up to three highmost
2959 bits might be clobbered. This is typically used when combined with some
2960 kind of sign or zero extension. */
2961 static const struct ashl_lshr_sequence ext_ashl_lshr_seq[32] =
2962 {
2963 { 0, { 0 }, 0 }, // 0
2964 { 1, { 1 }, LSHR_CLOBBERS_T },
2965 { 1, { 2 }, 0 },
2966 { 2, { 2, 1 }, LSHR_CLOBBERS_T },
2967 { 2, { 2, 2 }, 0 }, // 4
2968 { 3, { 2, 1, 2 }, LSHR_CLOBBERS_T },
2969 { 2, { 8, -2 }, 0 },
2970 { 2, { 8, -1 }, ASHL_CLOBBERS_T },
2971 { 1, { 8 }, 0 }, // 8
2972 { 2, { 8, 1 }, LSHR_CLOBBERS_T },
2973 { 2, { 8, 2 }, 0 },
2974 { 3, { 8, 1, 2 }, LSHR_CLOBBERS_T },
2975 { 3, { 8, 2, 2 }, 0 }, // 12
2976 { 3, { 16, -2, -1 }, ASHL_CLOBBERS_T },
2977 { 2, { 16, -2 }, 0 },
2978 { 2, { 16, -1 }, ASHL_CLOBBERS_T },
2979 { 1, { 16 }, 0 }, // 16
2980 { 2, { 16, 1 }, LSHR_CLOBBERS_T },
2981 { 2, { 16, 2 }, 0 },
2982 { 3, { 16, 1, 2 }, LSHR_CLOBBERS_T },
2983 { 3, { 16, 2, 2 }, 0 }, // 20
2984 { 4, { 16, 2, 1, 2 }, LSHR_CLOBBERS_T },
2985 { 3, { 16, -2, 8 }, 0 },
2986 { 3, { 16, -1, 8 }, ASHL_CLOBBERS_T },
2987 { 2, { 16, 8 }, 0 }, // 24
2988 { 3, { 16, 1, 8 }, LSHR_CLOBBERS_T },
2989 { 3, { 16, 8, 2 }, 0 },
2990 { 4, { 16, 8, 1, 2 }, LSHR_CLOBBERS_T },
2991 { 4, { 16, 8, 2, 2 }, 0 }, // 28
2992 { 4, { 16, -1, -2, 16 }, ASHL_CLOBBERS_T },
2993 { 3, { 16, -2, 16 }, 0 },
2994 { 3, { 16, -1, 16 }, ASHL_CLOBBERS_T }
2995 };
2996
2997 /* Return true if a shift left consisting of 1/2/8/16 shift instructions
2998 will clobber the T bit. */
2999 bool
sh_ashlsi_clobbers_t_reg_p(rtx shift_amount)3000 sh_ashlsi_clobbers_t_reg_p (rtx shift_amount)
3001 {
3002 gcc_assert (CONST_INT_P (shift_amount));
3003
3004 const int shift_amount_i = INTVAL (shift_amount) & 31;
3005
3006 /* Special case for shift count of 31: use and-rotl sequence. */
3007 if (shift_amount_i == 31)
3008 return true;
3009
3010 return (ashl_lshr_seq[shift_amount_i].clobbers_t
3011 & ASHL_CLOBBERS_T) != 0;
3012 }
3013
3014 /* Return true if a logical right shift consisting of 1/2/8/16 shift
3015 instructions will clobber the T bit. */
3016 bool
sh_lshrsi_clobbers_t_reg_p(rtx shift_amount)3017 sh_lshrsi_clobbers_t_reg_p (rtx shift_amount)
3018 {
3019 gcc_assert (CONST_INT_P (shift_amount));
3020
3021 /* For right shifts the constant might be negative. */
3022 const int shift_amount_i = std::abs (INTVAL (shift_amount)) & 31;
3023
3024 /* Special case for shift count of 31: use shll-movt sequence. */
3025 if (shift_amount_i == 31)
3026 return true;
3027
3028 return (ashl_lshr_seq[shift_amount_i].clobbers_t
3029 & LSHR_CLOBBERS_T) != 0;
3030 }
3031
3032 /* Return true if it is potentially beneficial to use a dynamic shift
3033 instruction (shad / shar) instead of a combination of 1/2/8/16
3034 shift instructions for the specified shift count.
3035 If dynamic shifts are not available, always return false. */
3036 bool
sh_dynamicalize_shift_p(rtx count)3037 sh_dynamicalize_shift_p (rtx count)
3038 {
3039 gcc_assert (CONST_INT_P (count));
3040
3041 /* For right shifts the constant might be negative. */
3042 const int shift_amount_i = std::abs (INTVAL (count)) & 31;
3043 int insn_count;
3044
3045 /* For left and right shifts, there are shorter 2 insn sequences for
3046 shift amounts of 31. */
3047 if (shift_amount_i == 31)
3048 insn_count = 2;
3049 else
3050 insn_count = ashl_lshr_seq[shift_amount_i].insn_count;
3051
3052 return TARGET_DYNSHIFT && (insn_count > 1 + SH_DYNAMIC_SHIFT_COST);
3053 }
3054
3055 /* Assuming we have a value that has been sign-extended by at least one bit,
3056 can we use the ext_shift_amounts with the last shift turned to an
3057 arithmetic shift to shift it by N without data loss, and quicker than by
3058 other means? */
3059 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
3060
3061 /* Return the cost of a shift. */
3062 static inline int
shiftcosts(rtx x)3063 shiftcosts (rtx x)
3064 {
3065 if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
3066 {
3067 if (GET_MODE (x) == DImode
3068 && CONST_INT_P (XEXP (x, 1))
3069 && INTVAL (XEXP (x, 1)) == 1)
3070 return 2;
3071
3072 /* Everything else is invalid, because there is no pattern for it. */
3073 return -1;
3074 }
3075 /* If shift by a non constant, then this will be expensive. */
3076 if (!CONST_INT_P (XEXP (x, 1)))
3077 return SH_DYNAMIC_SHIFT_COST;
3078
3079 /* Otherwise, return the true cost in instructions. Cope with out of range
3080 shift counts more or less arbitrarily. */
3081 int value = INTVAL (XEXP (x, 1)) & 31;
3082
3083 if (GET_CODE (x) == ASHIFTRT)
3084 {
3085 int cost = ashiftrt_insns[value];
3086 /* If dynamic shifts are available and profitable in this case, then we
3087 put the constant in a reg and use shad. */
3088 if (cost > 1 + SH_DYNAMIC_SHIFT_COST)
3089 cost = 1 + SH_DYNAMIC_SHIFT_COST;
3090 return cost;
3091 }
3092 else
3093 return ashl_lshr_seq[value].insn_count;
3094 }
3095
3096 /* Return the cost of an AND/XOR/IOR operation. */
3097 static inline int
and_xor_ior_costs(rtx x,int code)3098 and_xor_ior_costs (rtx x, int code)
3099 {
3100 /* On SH1-4 we have only max. SImode operations.
3101 Double the cost for modes > SImode. */
3102 const int cost_scale = GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD ? 2 : 1;
3103
3104 /* A logical operation with two registers is a single cycle
3105 instruction. */
3106 if (!CONST_INT_P (XEXP (x, 1)))
3107 return 1 * cost_scale;
3108
3109 int i = INTVAL (XEXP (x, 1));
3110
3111 /* These constants are single cycle extu.[bw] instructions. */
3112 if ((i == 0xff || i == 0xffff) && code == AND)
3113 return 1 * cost_scale;
3114 /* Constants that can be used in an instruction as an immediate are
3115 a single cycle, but this requires r0, so make it a little more
3116 expensive. */
3117 if (CONST_OK_FOR_K08 (i))
3118 return 2 * cost_scale;
3119 /* Constants that can be loaded with a mov immediate need one more cycle.
3120 This case is probably unnecessary. */
3121 if (CONST_OK_FOR_I08 (i))
3122 return 2 * cost_scale;
3123 /* Any other constant requires an additional 2 cycle pc-relative load.
3124 This case is probably unnecessary. */
3125 return 3 * cost_scale;
3126 }
3127
3128 /* Return the cost of an addition or a subtraction. */
3129 static inline int
addsubcosts(rtx x)3130 addsubcosts (rtx x)
3131 {
3132 if (GET_MODE (x) == SImode)
3133 {
3134 /* The addc or subc patterns will eventually become one or two
3135 instructions. Below are some costs for some of the patterns
3136 which combine would reject because the costs of the individual
3137 insns in the patterns are lower.
3138
3139 FIXME: It would be much easier if we had something like insn cost
3140 attributes and the cost calculation machinery used those attributes
3141 in the first place. This would eliminate redundant recog-like C
3142 code to calculate costs of complex patterns. */
3143 rtx op0 = XEXP (x, 0);
3144 rtx op1 = XEXP (x, 1);
3145
3146 if (GET_CODE (x) == PLUS)
3147 {
3148 if (GET_CODE (op0) == AND
3149 && XEXP (op0, 1) == const1_rtx
3150 && (GET_CODE (op1) == PLUS
3151 || (GET_CODE (op1) == MULT && XEXP (op1, 1) == const2_rtx)))
3152 return 1;
3153
3154 if (GET_CODE (op0) == MULT && XEXP (op0, 1) == const2_rtx
3155 && GET_CODE (op1) == LSHIFTRT
3156 && CONST_INT_P (XEXP (op1, 1)) && INTVAL (XEXP (op1, 1)) == 31)
3157 return 1;
3158 }
3159 /* Let's assume that adding the result of an insns that stores into
3160 the T bit is cheap. */
3161 if (treg_set_expr (op1, SImode))
3162 return 1;
3163 if (treg_set_expr (op0, SImode))
3164 return 1;
3165 }
3166
3167 /* On SH1-4 we have only max. SImode operations.
3168 Double the cost for modes > SImode. */
3169 const int cost_scale = GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD ? 2 : 1;
3170
3171 /* Adding a register is a single cycle insn. */
3172 if (REG_P (XEXP (x, 1))
3173 || GET_CODE (XEXP (x, 1)) == SUBREG)
3174 return 1 * cost_scale;
3175
3176 /* Likewise for small constants. */
3177 if (CONST_INT_P (XEXP (x, 1))
3178 && CONST_OK_FOR_ADD (INTVAL (XEXP (x, 1))))
3179 return 1 * cost_scale;
3180
3181 /* Any other constant requires a 2 cycle pc-relative load plus an
3182 addition. */
3183 return 3 * cost_scale;
3184 }
3185
3186 /* Return the cost of a multiply. */
3187 static inline int
multcosts(rtx x ATTRIBUTE_UNUSED)3188 multcosts (rtx x ATTRIBUTE_UNUSED)
3189 {
3190 if (sh_multcost >= 0)
3191 return sh_multcost;
3192
3193 if (TARGET_SH2)
3194 {
3195 /* We have a mul insn, so we can never take more than the mul and the
3196 read of the mac reg, but count more because of the latency and extra
3197 reg usage. */
3198 if (optimize_size)
3199 return 2;
3200 return 3;
3201 }
3202
3203 /* If we're aiming at small code, then just count the number of
3204 insns in a multiply call sequence. */
3205 if (optimize_size)
3206 return 5;
3207
3208 /* Otherwise count all the insns in the routine we'd be calling too. */
3209 return 20;
3210 }
3211
3212 /* Compute a (partial) cost for rtx X. Return true if the complete
3213 cost has been computed, and false if subexpressions should be
3214 scanned. In either case, *TOTAL contains the cost result. */
3215 static bool
sh_rtx_costs(rtx x,machine_mode mode ATTRIBUTE_UNUSED,int outer_code,int opno ATTRIBUTE_UNUSED,int * total,bool speed ATTRIBUTE_UNUSED)3216 sh_rtx_costs (rtx x, machine_mode mode ATTRIBUTE_UNUSED, int outer_code,
3217 int opno ATTRIBUTE_UNUSED,
3218 int *total, bool speed ATTRIBUTE_UNUSED)
3219 {
3220 int code = GET_CODE (x);
3221
3222 switch (code)
3223 {
3224 /* The lower-subreg pass decides whether to split multi-word regs
3225 into individual regs by looking at the cost for a SET of certain
3226 modes with the following patterns:
3227 (set (reg) (reg))
3228 (set (reg) (const_int 0))
3229 On machines that support vector-move operations a multi-word move
3230 is the same cost as individual reg move. On SH there is no
3231 vector-move, so we have to provide the correct cost in the number
3232 of move insns to load/store the reg of the mode in question. */
3233 case SET:
3234 if (sh_movt_set_dest (x) != NULL || sh_movrt_set_dest (x) != NULL)
3235 {
3236 *total = COSTS_N_INSNS (1);
3237 return true;
3238 }
3239
3240 if (register_operand (SET_DEST (x), VOIDmode)
3241 && (register_operand (SET_SRC (x), VOIDmode)
3242 || satisfies_constraint_Z (SET_SRC (x))))
3243 {
3244 const machine_mode mode = GET_MODE (SET_DEST (x));
3245 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode)
3246 / mov_insn_size (mode, TARGET_SH2A));
3247 return true;
3248 }
3249 return false;
3250
3251 /* The cost of a mem access is mainly the cost of the address mode. */
3252 case MEM:
3253 *total = sh_address_cost (XEXP (x, 0), GET_MODE (x), MEM_ADDR_SPACE (x),
3254 true);
3255 return true;
3256
3257 case IF_THEN_ELSE:
3258 /* This case is required for the if_then_else negc pattern. */
3259 if (treg_set_expr (XEXP (x, 0), SImode))
3260 {
3261 *total = COSTS_N_INSNS (1);
3262 return true;
3263 }
3264 else
3265 return false;
3266
3267 /* Zero extracts of single bits are usually combine patterns for the
3268 tst insns. */
3269 case ZERO_EXTRACT:
3270 if (GET_CODE (XEXP (x, 0)) == XOR
3271 && arith_reg_operand (XEXP (XEXP (x, 0), 0), VOIDmode)
3272 && XEXP (x, 1) == const1_rtx
3273 && CONST_INT_P (XEXP (x, 2))
3274 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
3275 /* Check that the xor constaint overlaps with the extracted bit. */
3276 && (INTVAL (XEXP (XEXP (x, 0), 1)) & (1LL << INTVAL (XEXP (x, 2)))))
3277 {
3278 *total = 1; //COSTS_N_INSNS (1);
3279 return true;
3280 }
3281
3282 /* div0s variant. */
3283 if (GET_CODE (XEXP (x, 0)) == XOR
3284 && GET_CODE (XEXP (XEXP (x, 0), 0)) == XOR
3285 && CONST_INT_P (XEXP (XEXP (x, 0), 1)))
3286 {
3287 *total = 1;
3288 return true;
3289 }
3290 return false;
3291
3292 /* The cost of a sign or zero extend depends on whether the source is a
3293 reg or a mem. In case of a mem take the address into account. */
3294 case SIGN_EXTEND:
3295 if (arith_reg_operand (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
3296 {
3297 *total = COSTS_N_INSNS (1);
3298 return true;
3299 }
3300 if (MEM_P (XEXP (x, 0)))
3301 {
3302 *total = sh_address_cost (XEXP (XEXP (x, 0), 0),
3303 GET_MODE (XEXP (x, 0)),
3304 MEM_ADDR_SPACE (XEXP (x, 0)), true);
3305 return true;
3306 }
3307 return false;
3308
3309 case ZERO_EXTEND:
3310 if (arith_reg_operand (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
3311 {
3312 *total = COSTS_N_INSNS (1);
3313 return true;
3314 }
3315 else if (TARGET_SH2A && MEM_P (XEXP (x, 0))
3316 && (GET_MODE (XEXP (x, 0)) == QImode
3317 || GET_MODE (XEXP (x, 0)) == HImode))
3318 {
3319 /* Handle SH2A's movu.b and movu.w insn. */
3320 *total = sh_address_cost (XEXP (XEXP (x, 0), 0),
3321 GET_MODE (XEXP (x, 0)),
3322 MEM_ADDR_SPACE (XEXP (x, 0)), true);
3323 return true;
3324 }
3325 return false;
3326
3327 /* mems for SFmode and DFmode can be inside a parallel due to
3328 the way the fpscr is handled. */
3329 case PARALLEL:
3330 for (int i = 0; i < XVECLEN (x, 0); i++)
3331 {
3332 rtx xx = XVECEXP (x, 0, i);
3333 if (GET_CODE (xx) == SET && MEM_P (XEXP (xx, 0)))
3334 {
3335 *total = sh_address_cost (XEXP (XEXP (xx, 0), 0),
3336 GET_MODE (XEXP (xx, 0)),
3337 MEM_ADDR_SPACE (XEXP (xx, 0)), true);
3338 return true;
3339 }
3340 if (GET_CODE (xx) == SET && MEM_P (XEXP (xx, 1)))
3341 {
3342 *total = sh_address_cost (XEXP (XEXP (xx, 1), 0),
3343 GET_MODE (XEXP (xx, 1)),
3344 MEM_ADDR_SPACE (XEXP (xx, 1)), true);
3345 return true;
3346 }
3347 }
3348
3349 if (sh_1el_vec (x, VOIDmode))
3350 *total = outer_code != SET;
3351 else if (sh_rep_vec (x, VOIDmode))
3352 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
3353 + (outer_code != SET));
3354 else
3355 *total = COSTS_N_INSNS (3) + (outer_code != SET);
3356 return true;
3357
3358 case CONST_INT:
3359 if (CONST_OK_FOR_I08 (INTVAL (x)))
3360 *total = 0;
3361 else if ((outer_code == AND || outer_code == IOR || outer_code == XOR)
3362 && CONST_OK_FOR_K08 (INTVAL (x)))
3363 *total = 1;
3364 /* prepare_cmp_insn will force costly constants int registers before
3365 the cbranch[sd]i4 patterns can see them, so preserve potentially
3366 interesting ones not covered by I08 above. */
3367 else if (outer_code == COMPARE
3368 && ((unsigned HOST_WIDE_INT) INTVAL (x)
3369 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
3370 || INTVAL (x) == 0x7fffffff
3371 || INTVAL (x) == 0x80 || INTVAL (x) == -0x81))
3372 *total = 1;
3373 else
3374 *total = 8;
3375 return true;
3376
3377 case EQ:
3378 /* An and with a constant compared against zero is
3379 most likely going to be a TST #imm, R0 instruction. */
3380 if (XEXP (x, 1) == const0_rtx
3381 && ((GET_CODE (XEXP (x, 0)) == AND
3382 || (SUBREG_P (XEXP (x, 0))
3383 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == AND))
3384 || GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT))
3385 {
3386 *total = 1;
3387 return true;
3388 }
3389
3390 else if (XEXP (x, 1) == const0_rtx
3391 && GET_CODE (XEXP (x, 0)) == AND
3392 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
3393 && GET_CODE (XEXP (XEXP (x, 0), 0)) == ASHIFT
3394 && arith_reg_operand (XEXP (XEXP (XEXP (x, 0), 0), 0), SImode)
3395 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1)))
3396 {
3397 *total = 1;
3398 return true;
3399 }
3400 else
3401 return false;
3402
3403 case SMIN:
3404 case SMAX:
3405 /* This is most likely a clips.b or clips.w insn that is being made up
3406 by combine. */
3407 if (TARGET_SH2A
3408 && (GET_CODE (XEXP (x, 0)) == SMAX || GET_CODE (XEXP (x, 0)) == SMIN)
3409 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
3410 && REG_P (XEXP (XEXP (x, 0), 0))
3411 && CONST_INT_P (XEXP (x, 1)))
3412 {
3413 *total = COSTS_N_INSNS (1);
3414 return true;
3415 }
3416 else
3417 return false;
3418
3419 case CONST:
3420 case LABEL_REF:
3421 case SYMBOL_REF:
3422 *total = 5;
3423 return true;
3424
3425 case CONST_DOUBLE:
3426 /* prepare_cmp_insn will force costly constants int registers before
3427 the cbranchdi4 pattern can see them, so preserve potentially
3428 interesting ones. */
3429 if (outer_code == COMPARE && GET_MODE (x) == DImode)
3430 *total = 1;
3431 else
3432 *total = 10;
3433 return true;
3434
3435 case CONST_VECTOR:
3436 /* FIXME: This looks broken. Only the last statement has any effect.
3437 Probably this could be folded with the PARALLEL case? */
3438 if (x == CONST0_RTX (GET_MODE (x)))
3439 *total = 0;
3440 else if (sh_1el_vec (x, VOIDmode))
3441 *total = outer_code != SET;
3442 if (sh_rep_vec (x, VOIDmode))
3443 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
3444 + (outer_code != SET));
3445 *total = COSTS_N_INSNS (3) + (outer_code != SET);
3446 return true;
3447
3448 case PLUS:
3449 case MINUS:
3450 *total = COSTS_N_INSNS (addsubcosts (x));
3451 return true;
3452
3453 case AND:
3454 /* Check for (and (not (reg)) (const_int 1)) which is a tst insn. */
3455 if (GET_CODE (XEXP (x, 0)) == NOT && XEXP (x, 1) == const1_rtx)
3456 {
3457 *total = COSTS_N_INSNS (1);
3458 return true;
3459 }
3460 /* Fall through. */
3461
3462 case XOR:
3463 case IOR:
3464 *total = COSTS_N_INSNS (and_xor_ior_costs (x, code));
3465 return true;
3466
3467 case MULT:
3468 *total = COSTS_N_INSNS (multcosts (x));
3469 return true;
3470
3471 case LT:
3472 case GE:
3473 /* div0s sign comparison. */
3474 if (GET_CODE (XEXP (x, 0)) == XOR
3475 && REG_P ((XEXP (XEXP (x, 0), 0)))
3476 && REG_P ((XEXP (XEXP (x, 0), 1)))
3477 && satisfies_constraint_Z (XEXP (x, 1)))
3478 {
3479 *total = COSTS_N_INSNS (1);
3480 return true;
3481 }
3482 else
3483 return false;
3484
3485 case LSHIFTRT:
3486 /* div0s sign comparison. */
3487 if (GET_CODE (XEXP (x, 0)) == XOR
3488 && REG_P ((XEXP (XEXP (x, 0), 0)))
3489 && REG_P ((XEXP (XEXP (x, 0), 1)))
3490 && CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) == 31)
3491 {
3492 *total = COSTS_N_INSNS (1);
3493 return true;
3494 }
3495 /* FALLTHRU */
3496 case ASHIFT:
3497 case ASHIFTRT:
3498 {
3499 int cost = shiftcosts (x);
3500 if (cost < 0)
3501 return false;
3502 *total = COSTS_N_INSNS (cost);
3503 return true;
3504 }
3505
3506 case DIV:
3507 case UDIV:
3508 case MOD:
3509 case UMOD:
3510 *total = COSTS_N_INSNS (20);
3511 return true;
3512
3513 case FLOAT:
3514 case FIX:
3515 *total = 100;
3516 return true;
3517
3518 default:
3519 return false;
3520 }
3521 }
3522
3523 /* Determine the size of the fundamental move insn that will be used
3524 for the specified mode. */
3525 static inline int
mov_insn_size(machine_mode mode,bool consider_sh2a)3526 mov_insn_size (machine_mode mode, bool consider_sh2a)
3527 {
3528 const int mode_sz = GET_MODE_SIZE (mode);
3529
3530 if ((consider_sh2a && TARGET_SH2A_DOUBLE && mode == DFmode)
3531 || (TARGET_FMOVD && mode == DFmode))
3532 return mode_sz;
3533 else
3534 {
3535 /* The max. available mode for actual move insns is SImode.
3536 Larger accesses will be split into multiple loads/stores. */
3537 const int max_mov_sz = GET_MODE_SIZE (SImode);
3538 return mode_sz >= max_mov_sz ? max_mov_sz : mode_sz;
3539 }
3540 }
3541
3542 /* Determine the maximum possible displacement for a move insn for the
3543 specified mode. */
3544 int
sh_max_mov_insn_displacement(machine_mode mode,bool consider_sh2a)3545 sh_max_mov_insn_displacement (machine_mode mode, bool consider_sh2a)
3546 {
3547 /* The 4 byte displacement move insns are the same as the 2 byte
3548 versions but take a 12 bit displacement. All we need to do is to
3549 scale the max. displacement value accordingly. */
3550 const int disp_scale = consider_sh2a ? (4095 / 15) : 1;
3551
3552 /* SH2A supports FPU move insns with 12 bit displacements.
3553 Other variants to do not support any kind of displacements for
3554 FPU move insns. */
3555 if (! consider_sh2a && TARGET_FPU_ANY && GET_MODE_CLASS (mode) == MODE_FLOAT)
3556 return 0;
3557 else
3558 {
3559 const int mov_insn_sz = mov_insn_size (mode, consider_sh2a);
3560 const int mode_sz = GET_MODE_SIZE (mode);
3561 int r = 15 * mov_insn_sz * disp_scale;
3562
3563 /* If the mov insn will be split into multiple loads/stores, the
3564 maximum possible displacement is a bit smaller. */
3565 if (mode_sz > mov_insn_sz)
3566 r -= mode_sz - mov_insn_sz;
3567 return r;
3568 }
3569 }
3570
3571 /* Determine the alignment mask for a move insn of the
3572 specified mode. */
3573 static inline int
mov_insn_alignment_mask(machine_mode mode,bool consider_sh2a)3574 mov_insn_alignment_mask (machine_mode mode, bool consider_sh2a)
3575 {
3576 const int mov_insn_sz = mov_insn_size (mode, consider_sh2a);
3577 return mov_insn_sz > 0 ? (mov_insn_sz - 1) : 0;
3578 }
3579
3580 /* Return the displacement value of a displacement address. */
3581 HOST_WIDE_INT
sh_disp_addr_displacement(rtx x)3582 sh_disp_addr_displacement (rtx x)
3583 {
3584 gcc_assert (satisfies_constraint_Sdd (x));
3585 return INTVAL (XEXP (XEXP (x, 0), 1));
3586 }
3587
3588 /* Compute the cost of an address. */
3589 static int
sh_address_cost(rtx x,machine_mode mode,addr_space_t as ATTRIBUTE_UNUSED,bool speed ATTRIBUTE_UNUSED)3590 sh_address_cost (rtx x, machine_mode mode,
3591 addr_space_t as ATTRIBUTE_UNUSED, bool speed ATTRIBUTE_UNUSED)
3592 {
3593 /* 'GBR + 0'. Account one more because of R0 restriction. */
3594 if (REG_P (x) && REGNO (x) == GBR_REG)
3595 return 2;
3596
3597 /* Simple reg, post-inc, pre-dec addressing. */
3598 if (REG_P (x) || GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_DEC)
3599 return 1;
3600
3601 /* 'reg + disp' addressing. */
3602 if (GET_CODE (x) == PLUS
3603 && REG_P (XEXP (x, 0)) && CONST_INT_P (XEXP (x, 1)))
3604 {
3605 /* 'GBR + disp'. Account one more because of R0 restriction. */
3606 if (REGNO (XEXP (x, 0)) == GBR_REG
3607 && gbr_displacement (XEXP (x, 1), mode))
3608 return 2;
3609
3610 const HOST_WIDE_INT offset = INTVAL (XEXP (x, 1));
3611
3612 if (offset == 0)
3613 return 1;
3614
3615 /* The displacement would fit into a 2 byte move insn.
3616 HImode and QImode loads/stores with displacement put pressure on
3617 R0 which will most likely require another reg copy. Thus account
3618 a higher cost for that. */
3619 if (offset > 0 && offset <= sh_max_mov_insn_displacement (mode, false))
3620 return (mode == HImode || mode == QImode) ? 2 : 1;
3621
3622 /* The displacement would fit into a 4 byte move insn (SH2A). */
3623 if (TARGET_SH2A
3624 && offset > 0 && offset <= sh_max_mov_insn_displacement (mode, true))
3625 return 2;
3626
3627 /* The displacement is probably out of range and will require extra
3628 calculations. */
3629 return 3;
3630 }
3631
3632 /* 'reg + reg' addressing. Account a slightly higher cost because of
3633 increased pressure on R0. */
3634 if (GET_CODE (x) == PLUS && ! CONSTANT_P (XEXP (x, 1)))
3635 return 3;
3636
3637 /* Not sure what it is - probably expensive. */
3638 return 10;
3639 }
3640
3641 /* Code to expand a shift. */
3642 static void
gen_ashift(int type,int n,rtx reg)3643 gen_ashift (int type, int n, rtx reg)
3644 {
3645 rtx n_rtx;
3646
3647 /* Negative values here come from the shift_amounts array. */
3648 if (n < 0)
3649 {
3650 if (type == ASHIFT)
3651 type = LSHIFTRT;
3652 else
3653 type = ASHIFT;
3654 n = -n;
3655 }
3656
3657 n_rtx = GEN_INT (n);
3658 gcc_assert (satisfies_constraint_P27 (n_rtx));
3659
3660 switch (type)
3661 {
3662 case ASHIFTRT:
3663 emit_insn (gen_ashrsi3_k (reg, reg, n_rtx));
3664 break;
3665 case LSHIFTRT:
3666 if (n == 1)
3667 emit_insn (gen_shlr (reg, reg));
3668 else
3669 emit_insn (gen_lshrsi3_k (reg, reg, n_rtx));
3670 break;
3671 case ASHIFT:
3672 emit_insn (gen_ashlsi3_k (reg, reg, n_rtx));
3673 break;
3674 default:
3675 gcc_unreachable ();
3676 }
3677 }
3678
3679 /* Code to expand a HImode shift. */
3680 static void
gen_ashift_hi(int type,int n,rtx reg)3681 gen_ashift_hi (int type, int n, rtx reg)
3682 {
3683 /* Negative values here come from the shift_amounts array. */
3684 if (n < 0)
3685 {
3686 if (type == ASHIFT)
3687 type = LSHIFTRT;
3688 else
3689 type = ASHIFT;
3690 n = -n;
3691 }
3692
3693 switch (type)
3694 {
3695 case ASHIFTRT:
3696 case LSHIFTRT:
3697 /* We don't have HImode right shift operations because using the
3698 ordinary 32 bit shift instructions for that doesn't generate proper
3699 zero/sign extension.
3700 gen_ashift_hi is only called in contexts where we know that the
3701 sign extension works out correctly. */
3702 {
3703 int offset = 0;
3704 if (GET_CODE (reg) == SUBREG)
3705 {
3706 offset = SUBREG_BYTE (reg);
3707 reg = SUBREG_REG (reg);
3708 }
3709 gen_ashift (type, n, gen_rtx_SUBREG (SImode, reg, offset));
3710 break;
3711 }
3712 case ASHIFT:
3713 emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n)));
3714 break;
3715 }
3716 }
3717
3718 /* Output RTL to split a constant shift into its component SH constant
3719 shift instructions. */
3720 void
gen_shifty_op(int code,rtx * operands)3721 gen_shifty_op (int code, rtx *operands)
3722 {
3723 int value = INTVAL (operands[2]);
3724 int max, i;
3725
3726 /* Truncate the shift count in case it is out of bounds. */
3727 value = value & 31;
3728
3729 if (value == 31)
3730 {
3731 if (code == LSHIFTRT)
3732 {
3733 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
3734 emit_insn (gen_movt (operands[0], get_t_reg_rtx ()));
3735 return;
3736 }
3737 else if (code == ASHIFT)
3738 {
3739 /* There is a two instruction sequence for 31 bit left shifts,
3740 but it requires r0. */
3741 if (REG_P (operands[0]) && REGNO (operands[0]) == 0)
3742 {
3743 emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
3744 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
3745 return;
3746 }
3747 }
3748 }
3749 else if (value == 0)
3750 {
3751 /* This can happen even when optimizing, if there were subregs before
3752 reload. Don't output a nop here, as this is never optimized away;
3753 use a no-op move instead. */
3754 emit_insn (gen_rtx_SET (operands[0], operands[0]));
3755 return;
3756 }
3757
3758 max = ashl_lshr_seq[value].insn_count;
3759 for (i = 0; i < max; i++)
3760 gen_ashift (code, ashl_lshr_seq[value].amount[i], operands[0]);
3761 }
3762
3763 /* Same as gen_shifty_op, but optimized for values where the topmost bits
3764 don't matter. */
3765 void
gen_shifty_hi_op(int code,rtx * operands)3766 gen_shifty_hi_op (int code, rtx *operands)
3767 {
3768 int value = INTVAL (operands[2]);
3769 int max, i;
3770 void (*gen_fun) (int, int, rtx);
3771
3772 /* This operation is used by and_shl for SImode values with a few
3773 high bits known to be cleared. */
3774 value &= 31;
3775 if (value == 0)
3776 {
3777 emit_insn (gen_nop ());
3778 return;
3779 }
3780
3781 gen_fun = GET_MODE (operands[0]) == HImode ? gen_ashift_hi : gen_ashift;
3782 if (code == ASHIFT)
3783 {
3784 max = ext_ashl_lshr_seq[value].insn_count;
3785 for (i = 0; i < max; i++)
3786 gen_fun (code, ext_ashl_lshr_seq[value].amount[i], operands[0]);
3787 }
3788 else
3789 /* When shifting right, emit the shifts in reverse order, so that
3790 solitary negative values come first. */
3791 for (i = ext_ashl_lshr_seq[value].insn_count - 1; i >= 0; i--)
3792 gen_fun (code, ext_ashl_lshr_seq[value].amount[i], operands[0]);
3793 }
3794
3795 /* Output RTL for an arithmetic right shift.
3796 ??? Rewrite to use super-optimizer sequences. */
3797 bool
expand_ashiftrt(rtx * operands)3798 expand_ashiftrt (rtx *operands)
3799 {
3800 rtx wrk;
3801 char func[18];
3802 int value;
3803
3804 if (TARGET_DYNSHIFT)
3805 {
3806 if (!CONST_INT_P (operands[2]))
3807 {
3808 rtx count = copy_to_mode_reg (SImode, operands[2]);
3809 emit_insn (gen_negsi2 (count, count));
3810 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
3811 return true;
3812 }
3813 else if (ashiftrt_insns[INTVAL (operands[2]) & 31]
3814 > 1 + SH_DYNAMIC_SHIFT_COST)
3815 {
3816 rtx count
3817 = force_reg (SImode, GEN_INT (- (INTVAL (operands[2]) & 31)));
3818 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
3819 return true;
3820 }
3821 }
3822 if (!CONST_INT_P (operands[2]))
3823 return false;
3824
3825 value = INTVAL (operands[2]) & 31;
3826
3827 if (value == 31)
3828 {
3829 /* If we are called from abs expansion, arrange things so that we
3830 we can use a single MT instruction that doesn't clobber the source,
3831 if LICM can hoist out the load of the constant zero. */
3832 if (currently_expanding_to_rtl)
3833 {
3834 emit_insn (gen_cmpgtsi_t (force_reg (SImode, CONST0_RTX (SImode)),
3835 operands[1]));
3836 emit_insn (gen_mov_neg_si_t (operands[0], get_t_reg_rtx ()));
3837 return true;
3838 }
3839 emit_insn (gen_ashrsi2_31 (operands[0], operands[1]));
3840 return true;
3841 }
3842 else if (value >= 16 && value <= 19)
3843 {
3844 wrk = gen_reg_rtx (SImode);
3845 emit_insn (gen_ashrsi2_16 (wrk, operands[1]));
3846 value -= 16;
3847 while (value--)
3848 gen_ashift (ASHIFTRT, 1, wrk);
3849 emit_move_insn (operands[0], wrk);
3850 return true;
3851 }
3852 /* Expand a short sequence inline, longer call a magic routine. */
3853 else if (value <= 5)
3854 {
3855 wrk = gen_reg_rtx (SImode);
3856 emit_move_insn (wrk, operands[1]);
3857 while (value--)
3858 gen_ashift (ASHIFTRT, 1, wrk);
3859 emit_move_insn (operands[0], wrk);
3860 return true;
3861 }
3862
3863 wrk = gen_reg_rtx (Pmode);
3864
3865 /* Load the value into an arg reg and call a helper. */
3866 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
3867 sprintf (func, "__ashiftrt_r4_%d", value);
3868 rtx lab = function_symbol (wrk, func, SFUNC_STATIC).lab;
3869 emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk, lab));
3870 emit_move_insn (operands[0], gen_rtx_REG (SImode, 4));
3871 return true;
3872 }
3873
3874 /* Try to find a good way to implement the combiner pattern
3875 [(set (match_operand:SI 0 "register_operand" "r")
3876 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3877 (match_operand:SI 2 "const_int_operand" "n"))
3878 (match_operand:SI 3 "const_int_operand" "n"))) .
3879 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
3880 return 0 for simple right / left or left/right shift combination.
3881 return 1 for a combination of shifts with zero_extend.
3882 return 2 for a combination of shifts with an AND that needs r0.
3883 return 3 for a combination of shifts with an AND that needs an extra
3884 scratch register, when the three highmost bits of the AND mask are clear.
3885 return 4 for a combination of shifts with an AND that needs an extra
3886 scratch register, when any of the three highmost bits of the AND mask
3887 is set.
3888 If ATTRP is set, store an initial right shift width in ATTRP[0],
3889 and the instruction length in ATTRP[1] . These values are not valid
3890 when returning 0.
3891 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
3892 shift_amounts for the last shift value that is to be used before the
3893 sign extend. */
3894 int
shl_and_kind(rtx left_rtx,rtx mask_rtx,int * attrp)3895 shl_and_kind (rtx left_rtx, rtx mask_rtx, int *attrp)
3896 {
3897 unsigned HOST_WIDE_INT mask, lsb, mask2, lsb2;
3898 int left = INTVAL (left_rtx), right;
3899 int best = 0;
3900 int cost, best_cost = 10000;
3901 int best_right = 0, best_len = 0;
3902 int i;
3903 int can_ext;
3904
3905 if (left < 0 || left > 31)
3906 return 0;
3907 if (CONST_INT_P (mask_rtx))
3908 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left;
3909 else
3910 mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left;
3911 /* Can this be expressed as a right shift / left shift pair? */
3912 lsb = ((mask ^ (mask - 1)) >> 1) + 1;
3913 right = exact_log2 (lsb);
3914 mask2 = ~(mask + lsb - 1);
3915 lsb2 = ((mask2 ^ (mask2 - 1)) >> 1) + 1;
3916 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
3917 if (! mask2)
3918 best_cost = ashl_lshr_seq[right].insn_count
3919 + ashl_lshr_seq[right + left].insn_count;
3920 /* mask has no trailing zeroes <==> ! right */
3921 else if (! right && mask2 == ~(lsb2 - 1))
3922 {
3923 int late_right = exact_log2 (lsb2);
3924 best_cost = ashl_lshr_seq[left + late_right].insn_count
3925 + ashl_lshr_seq[late_right].insn_count;
3926 }
3927 /* Try to use zero extend. */
3928 if (mask2 == ~(lsb2 - 1))
3929 {
3930 int width, first;
3931
3932 for (width = 8; width <= 16; width += 8)
3933 {
3934 /* Can we zero-extend right away? */
3935 if (lsb2 == (unsigned HOST_WIDE_INT) 1 << width)
3936 {
3937 cost = 1 + ext_ashl_lshr_seq[right].insn_count
3938 + ext_ashl_lshr_seq[left + right].insn_count;
3939 if (cost < best_cost)
3940 {
3941 best = 1;
3942 best_cost = cost;
3943 best_right = right;
3944 best_len = cost;
3945 if (attrp)
3946 attrp[2] = -1;
3947 }
3948 continue;
3949 }
3950 /* ??? Could try to put zero extend into initial right shift,
3951 or even shift a bit left before the right shift. */
3952 /* Determine value of first part of left shift, to get to the
3953 zero extend cut-off point. */
3954 first = width - exact_log2 (lsb2) + right;
3955 if (first >= 0 && right + left - first >= 0)
3956 {
3957 cost = ext_ashl_lshr_seq[right].insn_count
3958 + ext_ashl_lshr_seq[first].insn_count + 1
3959 + ext_ashl_lshr_seq[right + left - first].insn_count;
3960
3961 if (cost < best_cost)
3962 {
3963 best = 1;
3964 best_cost = cost;
3965 best_right = right;
3966 best_len = cost;
3967 if (attrp)
3968 attrp[2] = first;
3969 }
3970 }
3971 }
3972 }
3973 /* Try to use r0 AND pattern */
3974 for (i = 0; i <= 2; i++)
3975 {
3976 if (i > right)
3977 break;
3978 if (! CONST_OK_FOR_K08 (mask >> i))
3979 continue;
3980 cost = (i != 0) + 2 + ext_ashl_lshr_seq[left + i].insn_count;
3981 if (cost < best_cost)
3982 {
3983 best = 2;
3984 best_cost = cost;
3985 best_right = i;
3986 best_len = cost - 1;
3987 }
3988 }
3989 /* Try to use a scratch register to hold the AND operand. */
3990 can_ext = ((mask << left) & ((unsigned HOST_WIDE_INT) 3 << 30)) == 0;
3991 for (i = 0; i <= 2; i++)
3992 {
3993 if (i > right)
3994 break;
3995 cost = (i != 0) + (CONST_OK_FOR_I08 (mask >> i) ? 2 : 3)
3996 + (can_ext
3997 ? ext_ashl_lshr_seq
3998 : ashl_lshr_seq)[left + i].insn_count;
3999 if (cost < best_cost)
4000 {
4001 best = 4 - can_ext;
4002 best_cost = cost;
4003 best_right = i;
4004 best_len = cost - 1 - ! CONST_OK_FOR_I08 (mask >> i);
4005 }
4006 }
4007
4008 if (attrp)
4009 {
4010 attrp[0] = best_right;
4011 attrp[1] = best_len;
4012 }
4013 return best;
4014 }
4015
4016 /* This is used in length attributes of the unnamed instructions
4017 corresponding to shl_and_kind return values of 1 and 2. */
4018 int
shl_and_length(rtx insn)4019 shl_and_length (rtx insn)
4020 {
4021 rtx set_src, left_rtx, mask_rtx;
4022 int attributes[3];
4023
4024 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
4025 left_rtx = XEXP (XEXP (set_src, 0), 1);
4026 mask_rtx = XEXP (set_src, 1);
4027 shl_and_kind (left_rtx, mask_rtx, attributes);
4028 return attributes[1];
4029 }
4030
4031 /* This is used in length attribute of the and_shl_scratch instruction. */
4032 int
shl_and_scr_length(rtx insn)4033 shl_and_scr_length (rtx insn)
4034 {
4035 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
4036 int len = ashl_lshr_seq[INTVAL (XEXP (set_src, 1)) & 31].insn_count;
4037 rtx op = XEXP (set_src, 0);
4038 len += ashl_lshr_seq[INTVAL (XEXP (op, 1)) & 31].insn_count + 1;
4039 op = XEXP (XEXP (op, 0), 0);
4040 return len + ashl_lshr_seq[INTVAL (XEXP (op, 1)) & 31].insn_count;
4041 }
4042
4043 /* Generate rtl for instructions for which shl_and_kind advised a particular
4044 method of generating them, i.e. returned zero. */
4045 bool
gen_shl_and(rtx dest,rtx left_rtx,rtx mask_rtx,rtx source)4046 gen_shl_and (rtx dest, rtx left_rtx, rtx mask_rtx, rtx source)
4047 {
4048 int attributes[3];
4049 unsigned HOST_WIDE_INT mask;
4050 int kind = shl_and_kind (left_rtx, mask_rtx, attributes);
4051 int right, total_shift;
4052 void (*shift_gen_fun) (int, rtx *) = gen_shifty_hi_op;
4053
4054 right = attributes[0];
4055 total_shift = INTVAL (left_rtx) + right;
4056 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> total_shift;
4057 switch (kind)
4058 {
4059 default:
4060 return true;
4061 case 1:
4062 {
4063 int first = attributes[2];
4064 rtx operands[3];
4065
4066 if (first < 0)
4067 {
4068 emit_insn ((mask << right) <= 0xff
4069 ? gen_zero_extendqisi2 (dest,
4070 gen_lowpart (QImode, source))
4071 : gen_zero_extendhisi2 (dest,
4072 gen_lowpart (HImode, source)));
4073 source = dest;
4074 }
4075 if (source != dest)
4076 emit_insn (gen_movsi (dest, source));
4077 operands[0] = dest;
4078 if (right)
4079 {
4080 operands[2] = GEN_INT (right);
4081 gen_shifty_hi_op (LSHIFTRT, operands);
4082 }
4083 if (first > 0)
4084 {
4085 operands[2] = GEN_INT (first);
4086 gen_shifty_hi_op (ASHIFT, operands);
4087 total_shift -= first;
4088 mask <<= first;
4089 }
4090 if (first >= 0)
4091 emit_insn (mask <= 0xff
4092 ? gen_zero_extendqisi2 (dest, gen_lowpart (QImode, dest))
4093 : gen_zero_extendhisi2 (dest, gen_lowpart (HImode, dest)));
4094 if (total_shift > 0)
4095 {
4096 operands[2] = GEN_INT (total_shift);
4097 gen_shifty_hi_op (ASHIFT, operands);
4098 }
4099 break;
4100 }
4101 case 4:
4102 shift_gen_fun = gen_shifty_op;
4103 /* FALLTHRU */
4104 case 3:
4105 /* If the topmost bit that matters is set, set the topmost bits
4106 that don't matter. This way, we might be able to get a shorter
4107 signed constant. */
4108 if (mask & ((HOST_WIDE_INT) 1 << (31 - total_shift)))
4109 mask |= (HOST_WIDE_INT) ((HOST_WIDE_INT_M1U) << (31 - total_shift));
4110 /* FALLTHRU */
4111 case 2:
4112 /* Don't expand fine-grained when combining, because that will
4113 make the pattern fail. */
4114 if (currently_expanding_to_rtl
4115 || reload_in_progress || reload_completed)
4116 {
4117 rtx operands[3];
4118
4119 /* Cases 3 and 4 should be handled by this split
4120 only while combining */
4121 gcc_assert (kind <= 2);
4122 if (right)
4123 {
4124 emit_insn (gen_lshrsi3 (dest, source, GEN_INT (right)));
4125 source = dest;
4126 }
4127 emit_insn (gen_andsi3 (dest, source, GEN_INT (mask)));
4128 if (total_shift)
4129 {
4130 operands[0] = dest;
4131 operands[1] = dest;
4132 operands[2] = GEN_INT (total_shift);
4133 shift_gen_fun (ASHIFT, operands);
4134 }
4135 break;
4136 }
4137 else
4138 {
4139 int neg = 0;
4140 if (kind != 4 && total_shift < 16)
4141 {
4142 neg = -ext_ashl_lshr_seq[total_shift].amount[1];
4143 if (neg > 0)
4144 neg -= ext_ashl_lshr_seq[total_shift].amount[2];
4145 else
4146 neg = 0;
4147 }
4148 emit_insn (gen_and_shl_scratch (dest, source,
4149 GEN_INT (right),
4150 GEN_INT (mask),
4151 GEN_INT (total_shift + neg),
4152 GEN_INT (neg)));
4153 emit_insn (gen_movsi (dest, dest));
4154 break;
4155 }
4156 }
4157 return false;
4158 }
4159
4160 /* Try to find a good way to implement the combiner pattern
4161 [(set (match_operand:SI 0 "register_operand" "=r")
4162 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
4163 (match_operand:SI 2 "const_int_operand" "n")
4164 (match_operand:SI 3 "const_int_operand" "n")
4165 (const_int 0)))
4166 (clobber (reg:SI T_REG))]
4167 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
4168 return 0 for simple left / right shift combination.
4169 return 1 for left shift / 8 bit sign extend / left shift.
4170 return 2 for left shift / 16 bit sign extend / left shift.
4171 return 3 for left shift / 8 bit sign extend / shift / sign extend.
4172 return 4 for left shift / 16 bit sign extend / shift / sign extend.
4173 return 5 for left shift / 16 bit sign extend / right shift
4174 return 6 for < 8 bit sign extend / left shift.
4175 return 7 for < 8 bit sign extend / left shift / single right shift.
4176 If COSTP is nonzero, assign the calculated cost to *COSTP. */
4177 int
shl_sext_kind(rtx left_rtx,rtx size_rtx,int * costp)4178 shl_sext_kind (rtx left_rtx, rtx size_rtx, int *costp)
4179 {
4180 int left, size, insize, ext;
4181 int cost = 0, best_cost;
4182 int kind;
4183
4184 left = INTVAL (left_rtx);
4185 size = INTVAL (size_rtx);
4186 insize = size - left;
4187 gcc_assert (insize > 0);
4188 /* Default to left / right shift. */
4189 kind = 0;
4190 best_cost = ashl_lshr_seq[32 - insize].insn_count
4191 + ashl_lshr_seq[32 - size].insn_count;
4192 if (size <= 16)
4193 {
4194 /* 16 bit shift / sign extend / 16 bit shift */
4195 cost = ashl_lshr_seq[16 - insize].insn_count + 1
4196 + ashl_lshr_seq[16 - size].insn_count;
4197 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
4198 below, by alternative 3 or something even better. */
4199 if (cost < best_cost)
4200 {
4201 kind = 5;
4202 best_cost = cost;
4203 }
4204 }
4205 /* Try a plain sign extend between two shifts. */
4206 for (ext = 16; ext >= insize; ext -= 8)
4207 {
4208 if (ext <= size)
4209 {
4210 cost = ext_ashl_lshr_seq[ext - insize].insn_count + 1
4211 + ashl_lshr_seq[size - ext].insn_count;
4212 if (cost < best_cost)
4213 {
4214 kind = ext / (unsigned) 8;
4215 best_cost = cost;
4216 }
4217 }
4218 /* Check if we can do a sloppy shift with a final signed shift
4219 restoring the sign. */
4220 if (EXT_SHIFT_SIGNED (size - ext))
4221 cost = ext_ashl_lshr_seq[ext - insize].insn_count
4222 + ext_ashl_lshr_seq[size - ext].insn_count + 1;
4223 /* If not, maybe it's still cheaper to do the second shift sloppy,
4224 and do a final sign extend? */
4225 else if (size <= 16)
4226 cost = ext_ashl_lshr_seq[ext - insize].insn_count + 1
4227 + ext_ashl_lshr_seq[size > ext ? size - ext : ext - size].insn_count
4228 + 1;
4229 else
4230 continue;
4231 if (cost < best_cost)
4232 {
4233 kind = ext / (unsigned) 8 + 2;
4234 best_cost = cost;
4235 }
4236 }
4237 /* Check if we can sign extend in r0 */
4238 if (insize < 8)
4239 {
4240 cost = 3 + ashl_lshr_seq[left].insn_count;
4241 if (cost < best_cost)
4242 {
4243 kind = 6;
4244 best_cost = cost;
4245 }
4246 /* Try the same with a final signed shift. */
4247 if (left < 31)
4248 {
4249 cost = 3 + ext_ashl_lshr_seq[left + 1].insn_count + 1;
4250 if (cost < best_cost)
4251 {
4252 kind = 7;
4253 best_cost = cost;
4254 }
4255 }
4256 }
4257 if (TARGET_DYNSHIFT)
4258 {
4259 /* Try to use a dynamic shift. */
4260 cost = ashl_lshr_seq[32 - insize].insn_count + 1 + SH_DYNAMIC_SHIFT_COST;
4261 if (cost < best_cost)
4262 {
4263 kind = 0;
4264 best_cost = cost;
4265 }
4266 }
4267 if (costp)
4268 *costp = cost;
4269 return kind;
4270 }
4271
4272 /* Function to be used in the length attribute of the instructions
4273 implementing this pattern. */
4274 int
shl_sext_length(rtx insn)4275 shl_sext_length (rtx insn)
4276 {
4277 rtx set_src, left_rtx, size_rtx;
4278 int cost;
4279
4280 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
4281 left_rtx = XEXP (XEXP (set_src, 0), 1);
4282 size_rtx = XEXP (set_src, 1);
4283 shl_sext_kind (left_rtx, size_rtx, &cost);
4284 return cost;
4285 }
4286
4287 /* Generate rtl for this pattern */
4288 bool
gen_shl_sext(rtx dest,rtx left_rtx,rtx size_rtx,rtx source)4289 gen_shl_sext (rtx dest, rtx left_rtx, rtx size_rtx, rtx source)
4290 {
4291 int kind;
4292 int left, size, insize, cost;
4293 rtx operands[3];
4294
4295 kind = shl_sext_kind (left_rtx, size_rtx, &cost);
4296 left = INTVAL (left_rtx);
4297 size = INTVAL (size_rtx);
4298 insize = size - left;
4299 switch (kind)
4300 {
4301 case 1:
4302 case 2:
4303 case 3:
4304 case 4:
4305 {
4306 int ext = kind & 1 ? 8 : 16;
4307 int shift2 = size - ext;
4308
4309 /* Don't expand fine-grained when combining, because that will
4310 make the pattern fail. */
4311 if (! currently_expanding_to_rtl
4312 && ! reload_in_progress && ! reload_completed)
4313 {
4314 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
4315 emit_insn (gen_movsi (dest, source));
4316 break;
4317 }
4318 if (dest != source)
4319 emit_insn (gen_movsi (dest, source));
4320 operands[0] = dest;
4321 if (ext - insize)
4322 {
4323 operands[2] = GEN_INT (ext - insize);
4324 gen_shifty_hi_op (ASHIFT, operands);
4325 }
4326 emit_insn (kind & 1
4327 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
4328 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
4329 if (kind <= 2)
4330 {
4331 if (shift2)
4332 {
4333 operands[2] = GEN_INT (shift2);
4334 gen_shifty_op (ASHIFT, operands);
4335 }
4336 }
4337 else
4338 {
4339 if (shift2 > 0)
4340 {
4341 if (EXT_SHIFT_SIGNED (shift2))
4342 {
4343 operands[2] = GEN_INT (shift2 + 1);
4344 gen_shifty_op (ASHIFT, operands);
4345 operands[2] = const1_rtx;
4346 gen_shifty_op (ASHIFTRT, operands);
4347 break;
4348 }
4349 operands[2] = GEN_INT (shift2);
4350 gen_shifty_hi_op (ASHIFT, operands);
4351 }
4352 else if (shift2)
4353 {
4354 operands[2] = GEN_INT (-shift2);
4355 gen_shifty_hi_op (LSHIFTRT, operands);
4356 }
4357 emit_insn (size <= 8
4358 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
4359 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
4360 }
4361 break;
4362 }
4363 case 5:
4364 {
4365 int i = 16 - size;
4366 if (! currently_expanding_to_rtl
4367 && ! reload_in_progress && ! reload_completed)
4368 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
4369 else
4370 {
4371 operands[0] = dest;
4372 operands[2] = GEN_INT (16 - insize);
4373 gen_shifty_hi_op (ASHIFT, operands);
4374 emit_insn (gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
4375 }
4376 /* Don't use gen_ashrsi3 because it generates new pseudos. */
4377 while (--i >= 0)
4378 gen_ashift (ASHIFTRT, 1, dest);
4379 break;
4380 }
4381 case 6:
4382 case 7:
4383 /* Don't expand fine-grained when combining, because that will
4384 make the pattern fail. */
4385 if (! currently_expanding_to_rtl
4386 && ! reload_in_progress && ! reload_completed)
4387 {
4388 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
4389 emit_insn (gen_movsi (dest, source));
4390 break;
4391 }
4392 emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1)));
4393 emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1))));
4394 emit_insn (gen_addsi3 (dest, dest, GEN_INT (HOST_WIDE_INT_M1U << (insize - 1))));
4395 operands[0] = dest;
4396 operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
4397 gen_shifty_op (ASHIFT, operands);
4398 if (kind == 7)
4399 emit_insn (gen_ashrsi3_k (dest, dest, const1_rtx));
4400 break;
4401 default:
4402 return true;
4403 }
4404 return false;
4405 }
4406
4407 typedef struct label_ref_list_d
4408 {
4409 rtx_code_label *label;
4410 struct label_ref_list_d *next;
4411 } *label_ref_list_t;
4412
4413 static object_allocator<label_ref_list_d> label_ref_list_d_pool
4414 ("label references list");
4415
4416 /* The SH cannot load a large constant into a register, constants have to
4417 come from a pc relative load. The reference of a pc relative load
4418 instruction must be less than 1k in front of the instruction. This
4419 means that we often have to dump a constant inside a function, and
4420 generate code to branch around it.
4421
4422 It is important to minimize this, since the branches will slow things
4423 down and make things bigger.
4424
4425 Worst case code looks like:
4426
4427 mov.l L1,rn
4428 bra L2
4429 nop
4430 align
4431 L1: .long value
4432 L2:
4433 ..
4434
4435 mov.l L3,rn
4436 bra L4
4437 nop
4438 align
4439 L3: .long value
4440 L4:
4441 ..
4442
4443 We fix this by performing a scan before scheduling, which notices which
4444 instructions need to have their operands fetched from the constant table
4445 and builds the table.
4446
4447 The algorithm is:
4448
4449 scan, find an instruction which needs a pcrel move. Look forward, find the
4450 last barrier which is within MAX_COUNT bytes of the requirement.
4451 If there isn't one, make one. Process all the instructions between
4452 the find and the barrier.
4453
4454 In the above example, we can tell that L3 is within 1k of L1, so
4455 the first move can be shrunk from the 3 insn+constant sequence into
4456 just 1 insn, and the constant moved to L3 to make:
4457
4458 mov.l L1,rn
4459 ..
4460 mov.l L3,rn
4461 bra L4
4462 nop
4463 align
4464 L3:.long value
4465 L4:.long value
4466
4467 Then the second move becomes the target for the shortening process. */
4468
4469 typedef struct
4470 {
4471 rtx value; /* Value in table. */
4472 rtx_code_label *label; /* Label of value. */
4473 label_ref_list_t wend; /* End of window. */
4474 machine_mode mode; /* Mode of value. */
4475
4476 /* True if this constant is accessed as part of a post-increment
4477 sequence. Note that HImode constants are never accessed in this way. */
4478 bool part_of_sequence_p;
4479 } pool_node;
4480
4481 /* The maximum number of constants that can fit into one pool, since
4482 constants in the range 0..510 are at least 2 bytes long, and in the
4483 range from there to 1018 at least 4 bytes. */
4484
4485 #define MAX_POOL_SIZE 372
4486 static pool_node pool_vector[MAX_POOL_SIZE];
4487 static int pool_size;
4488 static rtx_code_label *pool_window_label;
4489 static int pool_window_last;
4490
4491 static int max_labelno_before_reorg;
4492
4493 /* ??? If we need a constant in HImode which is the truncated value of a
4494 constant we need in SImode, we could combine the two entries thus saving
4495 two bytes. Is this common enough to be worth the effort of implementing
4496 it? */
4497
4498 /* ??? This stuff should be done at the same time that we shorten branches.
4499 As it is now, we must assume that all branches are the maximum size, and
4500 this causes us to almost always output constant pools sooner than
4501 necessary. */
4502
4503 /* Add a constant to the pool and return its label. */
4504 static rtx_code_label *
add_constant(rtx x,machine_mode mode,rtx last_value)4505 add_constant (rtx x, machine_mode mode, rtx last_value)
4506 {
4507 rtx_code_label *lab, *new_rtx;
4508 label_ref_list_t ref, newref;
4509
4510 /* First see if we've already got it. */
4511 for (int i = 0; i < pool_size; i++)
4512 {
4513 if (x->code == pool_vector[i].value->code
4514 && mode == pool_vector[i].mode)
4515 {
4516 if (x->code == CODE_LABEL)
4517 {
4518 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
4519 continue;
4520 }
4521 if (rtx_equal_p (x, pool_vector[i].value))
4522 {
4523 lab = new_rtx = 0;
4524 if (! last_value
4525 || ! i
4526 || ! rtx_equal_p (last_value, pool_vector[i-1].value))
4527 {
4528 new_rtx = gen_label_rtx ();
4529 LABEL_REFS (new_rtx) = pool_vector[i].label;
4530 pool_vector[i].label = lab = new_rtx;
4531 }
4532 if (lab && pool_window_label)
4533 {
4534 newref = label_ref_list_d_pool.allocate ();
4535 newref->label = pool_window_label;
4536 ref = pool_vector[pool_window_last].wend;
4537 newref->next = ref;
4538 pool_vector[pool_window_last].wend = newref;
4539 }
4540 if (new_rtx)
4541 pool_window_label = new_rtx;
4542 pool_window_last = i;
4543 return lab;
4544 }
4545 }
4546 }
4547
4548 /* Need a new one. */
4549 pool_vector[pool_size].value = x;
4550 if (last_value && rtx_equal_p (last_value, pool_vector[pool_size - 1].value))
4551 {
4552 lab = 0;
4553 pool_vector[pool_size - 1].part_of_sequence_p = true;
4554 }
4555 else
4556 lab = gen_label_rtx ();
4557 pool_vector[pool_size].mode = mode;
4558 pool_vector[pool_size].label = lab;
4559 pool_vector[pool_size].wend = NULL;
4560 pool_vector[pool_size].part_of_sequence_p = (lab == 0);
4561 if (lab && pool_window_label)
4562 {
4563 newref = label_ref_list_d_pool.allocate ();
4564 newref->label = pool_window_label;
4565 ref = pool_vector[pool_window_last].wend;
4566 newref->next = ref;
4567 pool_vector[pool_window_last].wend = newref;
4568 }
4569 if (lab)
4570 pool_window_label = lab;
4571 pool_window_last = pool_size;
4572 pool_size++;
4573 return lab;
4574 }
4575
4576 /* Output the literal table. START, if nonzero, is the first instruction
4577 this table is needed for, and also indicates that there is at least one
4578 casesi_worker_2 instruction; We have to emit the operand3 labels from
4579 these insns at a 4-byte aligned position. BARRIER is the barrier
4580 after which we are to place the table. */
4581 static void
dump_table(rtx_insn * start,rtx_insn * barrier)4582 dump_table (rtx_insn *start, rtx_insn *barrier)
4583 {
4584 rtx_insn *scan = barrier;
4585 bool need_align = true;
4586 rtx lab;
4587 label_ref_list_t ref;
4588 bool have_df = false;
4589
4590 /* Do two passes, first time dump out the HI sized constants. */
4591
4592 for (int i = 0; i < pool_size; i++)
4593 {
4594 pool_node *p = &pool_vector[i];
4595
4596 if (p->mode == HImode)
4597 {
4598 if (need_align)
4599 {
4600 scan = emit_insn_after (gen_align_2 (), scan);
4601 need_align = false;
4602 }
4603 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4604 scan = emit_label_after (lab, scan);
4605 scan = emit_insn_after (gen_consttable_2 (p->value, const0_rtx),
4606 scan);
4607 for (ref = p->wend; ref; ref = ref->next)
4608 {
4609 lab = ref->label;
4610 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
4611 }
4612 }
4613 else if (p->mode == DFmode)
4614 have_df = true;
4615 }
4616
4617 need_align = true;
4618
4619 if (start)
4620 {
4621 scan = emit_insn_after (gen_align_4 (), scan);
4622 need_align = false;
4623 for (; start != barrier; start = NEXT_INSN (start))
4624 if (NONJUMP_INSN_P (start)
4625 && recog_memoized (start) == CODE_FOR_casesi_worker_2)
4626 {
4627 rtx src = SET_SRC (XVECEXP (PATTERN (start), 0, 0));
4628 rtx lab = XEXP (XVECEXP (src, 0, 3), 0);
4629
4630 scan = emit_label_after (lab, scan);
4631 }
4632 }
4633 if (TARGET_FMOVD && TARGET_ALIGN_DOUBLE && have_df)
4634 {
4635 rtx_insn *align_insn = NULL;
4636
4637 scan = emit_label_after (gen_label_rtx (), scan);
4638 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
4639 need_align = false;
4640
4641 for (int i = 0; i < pool_size; i++)
4642 {
4643 pool_node *p = &pool_vector[i];
4644
4645 switch (p->mode)
4646 {
4647 case E_HImode:
4648 break;
4649 case E_SImode:
4650 case E_SFmode:
4651 if (align_insn && !p->part_of_sequence_p)
4652 {
4653 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4654 emit_label_before (lab, align_insn);
4655 emit_insn_before (gen_consttable_4 (p->value, const0_rtx),
4656 align_insn);
4657 for (ref = p->wend; ref; ref = ref->next)
4658 {
4659 lab = ref->label;
4660 emit_insn_before (gen_consttable_window_end (lab),
4661 align_insn);
4662 }
4663 delete_insn (align_insn);
4664 align_insn = NULL;
4665 continue;
4666 }
4667 else
4668 {
4669 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4670 scan = emit_label_after (lab, scan);
4671 scan = emit_insn_after (gen_consttable_4 (p->value,
4672 const0_rtx), scan);
4673 need_align = ! need_align;
4674 }
4675 break;
4676 case E_DFmode:
4677 if (need_align)
4678 {
4679 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
4680 align_insn = scan;
4681 need_align = false;
4682 }
4683 /* FALLTHRU */
4684 case E_DImode:
4685 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4686 scan = emit_label_after (lab, scan);
4687 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
4688 scan);
4689 break;
4690 default:
4691 gcc_unreachable ();
4692 }
4693
4694 if (p->mode != HImode)
4695 {
4696 for (ref = p->wend; ref; ref = ref->next)
4697 {
4698 lab = ref->label;
4699 scan = emit_insn_after (gen_consttable_window_end (lab),
4700 scan);
4701 }
4702 }
4703 }
4704
4705 pool_size = 0;
4706 }
4707
4708 for (int i = 0; i < pool_size; i++)
4709 {
4710 pool_node *p = &pool_vector[i];
4711
4712 switch (p->mode)
4713 {
4714 case E_HImode:
4715 break;
4716 case E_SImode:
4717 case E_SFmode:
4718 if (need_align)
4719 {
4720 need_align = false;
4721 scan = emit_label_after (gen_label_rtx (), scan);
4722 scan = emit_insn_after (gen_align_4 (), scan);
4723 }
4724 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4725 scan = emit_label_after (lab, scan);
4726 scan = emit_insn_after (gen_consttable_4 (p->value, const0_rtx),
4727 scan);
4728 break;
4729 case E_DFmode:
4730 case E_DImode:
4731 if (need_align)
4732 {
4733 need_align = false;
4734 scan = emit_label_after (gen_label_rtx (), scan);
4735 scan = emit_insn_after (gen_align_4 (), scan);
4736 }
4737 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4738 scan = emit_label_after (lab, scan);
4739 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
4740 scan);
4741 break;
4742 default:
4743 gcc_unreachable ();
4744 }
4745
4746 if (p->mode != HImode)
4747 {
4748 for (ref = p->wend; ref; ref = ref->next)
4749 {
4750 lab = ref->label;
4751 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
4752 }
4753 }
4754 }
4755
4756 scan = emit_insn_after (gen_consttable_end (), scan);
4757 scan = emit_barrier_after (scan);
4758 pool_size = 0;
4759 pool_window_label = NULL;
4760 pool_window_last = 0;
4761 }
4762
4763 #define MOVA_LABELREF(mova) XVECEXP (SET_SRC (PATTERN (mova)), 0, 0)
4764
4765 /* Nonzero if the insn is a move instruction which needs to be fixed. */
4766
4767 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
4768 CONST_DOUBLE input value is CONST_OK_FOR_I08. For a SFmode move, we don't
4769 need to fix it if the input value is CONST_OK_FOR_I08. */
4770 static bool
broken_move(rtx_insn * insn)4771 broken_move (rtx_insn *insn)
4772 {
4773 if (NONJUMP_INSN_P (insn))
4774 {
4775 rtx pat = PATTERN (insn);
4776 if (GET_CODE (pat) == PARALLEL)
4777 pat = XVECEXP (pat, 0, 0);
4778 if (GET_CODE (pat) == SET
4779 /* We can load any 8-bit value if we don't care what the high
4780 order bits end up as. */
4781 && GET_MODE (SET_DEST (pat)) != QImode
4782 && (CONSTANT_P (SET_SRC (pat))
4783 || (GET_CODE (SET_SRC (pat)) == UNSPEC_VOLATILE
4784 && XINT (SET_SRC (pat), 1) == UNSPECV_SP_SWITCH_B)
4785 /* Match mova_const. */
4786 || (GET_CODE (SET_SRC (pat)) == UNSPEC
4787 && XINT (SET_SRC (pat), 1) == UNSPEC_MOVA
4788 && GET_CODE (XVECEXP (SET_SRC (pat), 0, 0)) == CONST))
4789 && ! (TARGET_SH2E
4790 && GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
4791 && (fp_zero_operand (SET_SRC (pat))
4792 || fp_one_operand (SET_SRC (pat)))
4793 /* In general we don't know the current setting of fpscr, so
4794 disable fldi.
4795 There is an exception if this was a register-register move
4796 before reload - and hence it was ascertained that we have
4797 single precision setting - and in a post-reload optimization
4798 we changed this to do a constant load. In that case
4799 we don't have an r0 clobber, hence we must use fldi. */
4800 && (TARGET_FMOVD
4801 || (GET_CODE (XEXP (XVECEXP (PATTERN (insn), 0, 2), 0))
4802 == SCRATCH))
4803 && REG_P (SET_DEST (pat))
4804 && FP_REGISTER_P (REGNO (SET_DEST (pat))))
4805 && ! (TARGET_SH2A
4806 && GET_MODE (SET_DEST (pat)) == SImode
4807 && (satisfies_constraint_I20 (SET_SRC (pat))
4808 || satisfies_constraint_I28 (SET_SRC (pat))))
4809 && ! satisfies_constraint_I08 (SET_SRC (pat)))
4810 return true;
4811 }
4812
4813 return false;
4814 }
4815
4816 /* Return true if the specified insn is a mova insn. */
4817 static bool
mova_p(rtx_insn * insn)4818 mova_p (rtx_insn *insn)
4819 {
4820 return (NONJUMP_INSN_P (insn)
4821 && GET_CODE (PATTERN (insn)) == SET
4822 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
4823 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_MOVA
4824 /* Don't match mova_const. */
4825 && GET_CODE (MOVA_LABELREF (insn)) == LABEL_REF);
4826 }
4827
4828 /* Fix up a mova from a switch that went out of range. */
4829 static void
fixup_mova(rtx_insn * mova)4830 fixup_mova (rtx_insn *mova)
4831 {
4832 PUT_MODE (XEXP (MOVA_LABELREF (mova), 0), QImode);
4833 if (! flag_pic)
4834 {
4835 SET_SRC (PATTERN (mova)) = MOVA_LABELREF (mova);
4836 INSN_CODE (mova) = -1;
4837 }
4838 else
4839 {
4840 rtx_insn *worker = mova;
4841 rtx_code_label *lab = gen_label_rtx ();
4842 rtx wpat, wpat0, wpat1, wsrc, target, base, diff;
4843
4844 do
4845 {
4846 worker = NEXT_INSN (worker);
4847 gcc_assert (worker
4848 && !LABEL_P (worker)
4849 && !JUMP_P (worker));
4850 } while (NOTE_P (worker)
4851 || recog_memoized (worker) != CODE_FOR_casesi_worker_1);
4852 wpat = PATTERN (worker);
4853 wpat0 = XVECEXP (wpat, 0, 0);
4854 wpat1 = XVECEXP (wpat, 0, 1);
4855 wsrc = SET_SRC (wpat0);
4856 PATTERN (worker) = (gen_casesi_worker_2
4857 (SET_DEST (wpat0), XVECEXP (wsrc, 0, 1),
4858 XEXP (XVECEXP (wsrc, 0, 2), 0), lab,
4859 XEXP (wpat1, 0)));
4860 INSN_CODE (worker) = -1;
4861 target = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
4862 base = gen_rtx_LABEL_REF (Pmode, lab);
4863 diff = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, target, base), UNSPEC_SYMOFF);
4864 SET_SRC (PATTERN (mova)) = gen_rtx_CONST (Pmode, diff);
4865 INSN_CODE (mova) = -1;
4866 }
4867 }
4868
4869 /* NEW_MOVA is a mova we've just encountered while scanning forward. Update
4870 *num_mova, and check if the new mova is not nested within the first one.
4871 return 0 if *first_mova was replaced, 1 if new_mova was replaced,
4872 2 if new_mova has been assigned to *first_mova, -1 otherwise.. */
4873 static int
untangle_mova(int * num_mova,rtx_insn ** first_mova,rtx_insn * new_mova)4874 untangle_mova (int *num_mova, rtx_insn **first_mova, rtx_insn *new_mova)
4875 {
4876 int n_addr = 0; /* Initialization to shut up spurious warning. */
4877 int f_target, n_target = 0; /* Likewise. */
4878
4879 if (optimize)
4880 {
4881 /* If NEW_MOVA has no address yet, it will be handled later. */
4882 if (INSN_ADDRESSES_SIZE() <= (unsigned) INSN_UID (new_mova))
4883 return -1;
4884
4885 n_addr = INSN_ADDRESSES (INSN_UID (new_mova));
4886 n_target = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (new_mova), 0)));
4887 if (n_addr > n_target || n_addr + 1022 < n_target)
4888 {
4889 /* Change the mova into a load.
4890 broken_move will then return true for it. */
4891 fixup_mova (new_mova);
4892 return 1;
4893 }
4894 }
4895 if (!(*num_mova)++)
4896 {
4897 *first_mova = new_mova;
4898 return 2;
4899 }
4900 if (!optimize
4901 || ((f_target
4902 = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (*first_mova), 0))))
4903 >= n_target))
4904 return -1;
4905
4906 (*num_mova)--;
4907 if (f_target - INSN_ADDRESSES (INSN_UID (*first_mova))
4908 > n_target - n_addr)
4909 {
4910 fixup_mova (*first_mova);
4911 return 0;
4912 }
4913 else
4914 {
4915 fixup_mova (new_mova);
4916 return 1;
4917 }
4918 }
4919
4920 /* Find the last barrier from insn FROM which is close enough to hold the
4921 constant pool. If we can't find one, then create one near the end of
4922 the range. */
4923 static rtx_insn *
find_barrier(int num_mova,rtx_insn * mova,rtx_insn * from)4924 find_barrier (int num_mova, rtx_insn *mova, rtx_insn *from)
4925 {
4926 int count_si = 0;
4927 int count_hi = 0;
4928 int found_hi = 0;
4929 int found_si = 0;
4930 int hi_align = 2;
4931 int si_align = 2;
4932 int leading_mova = num_mova;
4933 rtx_insn *barrier_before_mova = NULL;
4934 rtx_insn *found_barrier = NULL;
4935 rtx_insn *good_barrier = NULL;
4936 int si_limit;
4937 int hi_limit;
4938 rtx_insn *orig = from;
4939 rtx_insn *last_got = NULL;
4940 rtx_insn *last_symoff = NULL;
4941
4942 /* For HImode: range is 510, add 4 because pc counts from address of
4943 second instruction after this one, subtract 2 for the jump instruction
4944 that we may need to emit before the table, subtract 2 for the instruction
4945 that fills the jump delay slot (in very rare cases, reorg will take an
4946 instruction from after the constant pool or will leave the delay slot
4947 empty). This gives 510.
4948 For SImode: range is 1020, add 4 because pc counts from address of
4949 second instruction after this one, subtract 2 in case pc is 2 byte
4950 aligned, subtract 2 for the jump instruction that we may need to emit
4951 before the table, subtract 2 for the instruction that fills the jump
4952 delay slot. This gives 1018. */
4953
4954 /* The branch will always be shortened now that the reference address for
4955 forward branches is the successor address, thus we need no longer make
4956 adjustments to the [sh]i_limit for -O0. */
4957
4958 si_limit = 1018;
4959 hi_limit = 510;
4960
4961 while (from && count_si < si_limit && count_hi < hi_limit)
4962 {
4963 int inc = get_attr_length (from);
4964 int new_align = 1;
4965
4966 /* If this is a label that existed at the time of the compute_alignments
4967 call, determine the alignment. N.B. When find_barrier recurses for
4968 an out-of-reach mova, we might see labels at the start of previously
4969 inserted constant tables. */
4970 if (LABEL_P (from)
4971 && CODE_LABEL_NUMBER (from) <= max_labelno_before_reorg)
4972 {
4973 if (optimize)
4974 new_align = 1 << label_to_alignment (from);
4975 else if (BARRIER_P (prev_nonnote_insn (from)))
4976 new_align = 1 << barrier_align (from);
4977 else
4978 new_align = 1;
4979 inc = 0;
4980 }
4981 /* In case we are scanning a constant table because of recursion, check
4982 for explicit alignments. If the table is long, we might be forced
4983 to emit the new table in front of it; the length of the alignment
4984 might be the last straw. */
4985 else if (NONJUMP_INSN_P (from)
4986 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
4987 && XINT (PATTERN (from), 1) == UNSPECV_ALIGN)
4988 new_align = INTVAL (XVECEXP (PATTERN (from), 0, 0));
4989 /* When we find the end of a constant table, paste the new constant
4990 at the end. That is better than putting it in front because
4991 this way, we don't need extra alignment for adding a 4-byte-aligned
4992 mov(a) label to a 2/4 or 8/4 byte aligned table. */
4993 else if (NONJUMP_INSN_P (from)
4994 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
4995 && XINT (PATTERN (from), 1) == UNSPECV_CONST_END)
4996 return from;
4997
4998 if (BARRIER_P (from))
4999 {
5000 rtx_insn *next;
5001
5002 found_barrier = from;
5003
5004 /* If we are at the end of the function, or in front of an alignment
5005 instruction, we need not insert an extra alignment. We prefer
5006 this kind of barrier. */
5007 if (barrier_align (from) > 2)
5008 good_barrier = from;
5009
5010 /* If we are at the end of a hot/cold block, dump the constants
5011 here. */
5012 next = NEXT_INSN (from);
5013 if (next
5014 && NOTE_P (next)
5015 && NOTE_KIND (next) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
5016 break;
5017 }
5018
5019 if (broken_move (from))
5020 {
5021 rtx pat, src, dst;
5022 machine_mode mode;
5023
5024 pat = PATTERN (from);
5025 if (GET_CODE (pat) == PARALLEL)
5026 pat = XVECEXP (pat, 0, 0);
5027 src = SET_SRC (pat);
5028 dst = SET_DEST (pat);
5029 mode = GET_MODE (dst);
5030
5031 /* GOT pcrelat setting comes in pair of
5032 mova .L8,r0
5033 mov.l .L8,r12
5034 instructions. (plus add r0,r12).
5035 Remember if we see one without the other. */
5036 if (GET_CODE (src) == UNSPEC && PIC_ADDR_P (XVECEXP (src, 0, 0)))
5037 last_got = last_got ? NULL : from;
5038 else if (PIC_ADDR_P (src))
5039 last_got = last_got ? NULL : from;
5040
5041 /* We must explicitly check the mode, because sometimes the
5042 front end will generate code to load unsigned constants into
5043 HImode targets without properly sign extending them. */
5044 if (mode == HImode
5045 || (mode == SImode && satisfies_constraint_I16 (src)
5046 && REGNO (dst) != FPUL_REG))
5047 {
5048 found_hi += 2;
5049 /* We put the short constants before the long constants, so
5050 we must count the length of short constants in the range
5051 for the long constants. */
5052 /* ??? This isn't optimal, but is easy to do. */
5053 si_limit -= 2;
5054 }
5055 else
5056 {
5057 /* We dump DF/DI constants before SF/SI ones, because
5058 the limit is the same, but the alignment requirements
5059 are higher. We may waste up to 4 additional bytes
5060 for alignment, and the DF/DI constant may have
5061 another SF/SI constant placed before it. */
5062 while (si_align > 2 && found_si + si_align - 2 > count_si)
5063 si_align >>= 1;
5064 if (found_si > count_si)
5065 count_si = found_si;
5066 found_si += GET_MODE_SIZE (mode);
5067 if (num_mova)
5068 si_limit -= GET_MODE_SIZE (mode);
5069 }
5070 }
5071
5072 if (mova_p (from))
5073 {
5074 switch (untangle_mova (&num_mova, &mova, from))
5075 {
5076 case 1:
5077 if (flag_pic)
5078 {
5079 rtx src = SET_SRC (PATTERN (from));
5080 if (GET_CODE (src) == CONST
5081 && GET_CODE (XEXP (src, 0)) == UNSPEC
5082 && XINT (XEXP (src, 0), 1) == UNSPEC_SYMOFF)
5083 last_symoff = from;
5084 }
5085 break;
5086 case 0: return find_barrier (0, 0, mova);
5087 case 2:
5088 {
5089 leading_mova = 0;
5090 barrier_before_mova
5091 = good_barrier ? good_barrier : found_barrier;
5092 }
5093 default: break;
5094 }
5095 if (found_si > count_si)
5096 count_si = found_si;
5097 }
5098 else if (JUMP_TABLE_DATA_P (from)
5099 && GET_CODE (PATTERN (from)) == ADDR_DIFF_VEC)
5100 {
5101 if ((num_mova > 1 && GET_MODE (prev_nonnote_insn (from)) == VOIDmode)
5102 || (num_mova
5103 && (prev_nonnote_insn (from)
5104 == XEXP (MOVA_LABELREF (mova), 0))))
5105 num_mova--;
5106 if (barrier_align (next_real_insn (from)) == align_jumps_log)
5107 {
5108 /* We have just passed the barrier in front of the
5109 ADDR_DIFF_VEC, which is stored in found_barrier. Since
5110 the ADDR_DIFF_VEC is accessed as data, just like our pool
5111 constants, this is a good opportunity to accommodate what
5112 we have gathered so far.
5113 If we waited any longer, we could end up at a barrier in
5114 front of code, which gives worse cache usage for separated
5115 instruction / data caches. */
5116 good_barrier = found_barrier;
5117 break;
5118 }
5119 else
5120 {
5121 rtx body = PATTERN (from);
5122 inc = XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body));
5123 }
5124 }
5125 /* For the SH1, we generate alignments even after jumps-around-jumps. */
5126 else if (JUMP_P (from)
5127 && ! TARGET_SH2
5128 && ! optimize_size)
5129 new_align = 4;
5130
5131 /* There is a possibility that a bf is transformed into a bf/s by the
5132 delay slot scheduler. */
5133 if (JUMP_P (from)
5134 && get_attr_type (from) == TYPE_CBRANCH
5135 && ! sequence_insn_p (from))
5136 inc += 2;
5137
5138 if (found_si)
5139 {
5140 count_si += inc;
5141 if (new_align > si_align)
5142 {
5143 si_limit -= (count_si - 1) & (new_align - si_align);
5144 si_align = new_align;
5145 }
5146 count_si = (count_si + new_align - 1) & -new_align;
5147 }
5148 if (found_hi)
5149 {
5150 count_hi += inc;
5151 if (new_align > hi_align)
5152 {
5153 hi_limit -= (count_hi - 1) & (new_align - hi_align);
5154 hi_align = new_align;
5155 }
5156 count_hi = (count_hi + new_align - 1) & -new_align;
5157 }
5158 from = NEXT_INSN (from);
5159 }
5160
5161 if (num_mova)
5162 {
5163 if (leading_mova)
5164 {
5165 /* Try as we might, the leading mova is out of range. Change
5166 it into a load (which will become a pcload) and retry. */
5167 fixup_mova (mova);
5168 return find_barrier (0, 0, mova);
5169 }
5170 else
5171 {
5172 /* Insert the constant pool table before the mova instruction,
5173 to prevent the mova label reference from going out of range. */
5174 from = mova;
5175 good_barrier = found_barrier = barrier_before_mova;
5176 }
5177 }
5178
5179 if (found_barrier)
5180 {
5181 if (good_barrier && next_real_insn (found_barrier))
5182 found_barrier = good_barrier;
5183 }
5184 else
5185 {
5186 /* We didn't find a barrier in time to dump our stuff,
5187 so we'll make one. */
5188 rtx_code_label *label = gen_label_rtx ();
5189
5190 /* Don't emit a constant table in the middle of insns for
5191 casesi_worker_2. This is a bit overkill but is enough
5192 because casesi_worker_2 wouldn't appear so frequently. */
5193 if (last_symoff)
5194 from = last_symoff;
5195
5196 /* If we exceeded the range, then we must back up over the last
5197 instruction we looked at. Otherwise, we just need to undo the
5198 NEXT_INSN at the end of the loop. */
5199 if (PREV_INSN (from) != orig
5200 && (count_hi > hi_limit || count_si > si_limit))
5201 from = PREV_INSN (PREV_INSN (from));
5202 else
5203 from = PREV_INSN (from);
5204
5205 /* Don't emit a constant table int the middle of global pointer setting,
5206 since that that would move the addressing base GOT into another table.
5207 We need the first mov instruction before the _GLOBAL_OFFSET_TABLE_
5208 in the pool anyway, so just move up the whole constant pool.
5209
5210 However, avoid doing so when the last single GOT mov is the starting
5211 insn itself. Going past above the start insn would create a negative
5212 offset, causing errors. */
5213 if (last_got && last_got != orig)
5214 from = PREV_INSN (last_got);
5215
5216 /* Don't insert the constant pool table at the position which
5217 may be the landing pad. */
5218 if (flag_exceptions
5219 && CALL_P (from)
5220 && find_reg_note (from, REG_EH_REGION, NULL_RTX))
5221 from = PREV_INSN (from);
5222
5223 /* Walk back to be just before any jump or label.
5224 Putting it before a label reduces the number of times the branch
5225 around the constant pool table will be hit. Putting it before
5226 a jump makes it more likely that the bra delay slot will be
5227 filled. */
5228 while (NOTE_P (from) || JUMP_P (from) || LABEL_P (from))
5229 from = PREV_INSN (from);
5230
5231 if (CALL_P (from))
5232 {
5233 bool sibcall_p = SIBLING_CALL_P (from);
5234
5235 /* If FROM was a sibling call, then we know that control
5236 will not return. In fact, we were guaranteed to hit
5237 a barrier before another real insn.
5238
5239 The jump around the constant pool is unnecessary. It
5240 costs space, but more importantly it confuses dwarf2cfi
5241 generation. */
5242 if (sibcall_p)
5243 return emit_barrier_after (from);
5244 }
5245
5246 from = emit_jump_insn_after (gen_jump (label), from);
5247 JUMP_LABEL (from) = label;
5248 LABEL_NUSES (label) = 1;
5249 found_barrier = emit_barrier_after (from);
5250 emit_label_after (label, found_barrier);
5251 }
5252
5253 return found_barrier;
5254 }
5255
5256 /* If the instruction INSN is implemented by a special function, and we can
5257 positively find the register that is used to call the sfunc, and this
5258 register is not used anywhere else in this instruction - except as the
5259 destination of a set, return this register; else, return 0. */
5260 rtx
sfunc_uses_reg(rtx_insn * insn)5261 sfunc_uses_reg (rtx_insn *insn)
5262 {
5263 int i;
5264 rtx pattern, part, reg_part, reg;
5265
5266 if (!NONJUMP_INSN_P (insn))
5267 return NULL_RTX;
5268 pattern = PATTERN (insn);
5269 if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC)
5270 return NULL_RTX;
5271
5272 for (reg_part = NULL_RTX, i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
5273 {
5274 part = XVECEXP (pattern, 0, i);
5275 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == SImode)
5276 reg_part = part;
5277 }
5278 if (! reg_part)
5279 return NULL_RTX;
5280 reg = XEXP (reg_part, 0);
5281 for (int i = XVECLEN (pattern, 0) - 1; i >= 0; i--)
5282 {
5283 part = XVECEXP (pattern, 0, i);
5284 if (part == reg_part || GET_CODE (part) == CLOBBER)
5285 continue;
5286 if (reg_mentioned_p (reg, ((GET_CODE (part) == SET
5287 && REG_P (SET_DEST (part)))
5288 ? SET_SRC (part) : part)))
5289 return NULL_RTX;
5290 }
5291 return reg;
5292 }
5293
5294 /* See if the only way in which INSN uses REG is by calling it, or by
5295 setting it while calling it. Set *SET to a SET rtx if the register
5296 is set by INSN. */
5297 static bool
noncall_uses_reg(rtx reg,rtx_insn * insn,rtx * set)5298 noncall_uses_reg (rtx reg, rtx_insn *insn, rtx *set)
5299 {
5300 *set = NULL_RTX;
5301
5302 rtx reg2 = sfunc_uses_reg (insn);
5303 if (reg2 && REGNO (reg2) == REGNO (reg))
5304 {
5305 rtx pattern = single_set (insn);
5306 if (pattern
5307 && REG_P (SET_DEST (pattern))
5308 && REGNO (reg) == REGNO (SET_DEST (pattern)))
5309 *set = pattern;
5310 return false;
5311 }
5312 if (!CALL_P (insn))
5313 {
5314 /* We don't use rtx_equal_p because we don't care if the mode is
5315 different. */
5316 rtx pattern = single_set (insn);
5317 if (pattern
5318 && REG_P (SET_DEST (pattern))
5319 && REGNO (reg) == REGNO (SET_DEST (pattern)))
5320 {
5321 rtx par, part;
5322 int i;
5323
5324 *set = pattern;
5325 par = PATTERN (insn);
5326 if (GET_CODE (par) == PARALLEL)
5327 for (i = XVECLEN (par, 0) - 1; i >= 0; i--)
5328 {
5329 part = XVECEXP (par, 0, i);
5330 if (GET_CODE (part) != SET && reg_mentioned_p (reg, part))
5331 return true;
5332 }
5333 return reg_mentioned_p (reg, SET_SRC (pattern));
5334 }
5335
5336 return true;
5337 }
5338
5339 rtx pattern = PATTERN (insn);
5340
5341 if (GET_CODE (pattern) == PARALLEL)
5342 {
5343 for (int i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
5344 if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i)))
5345 return true;
5346 pattern = XVECEXP (pattern, 0, 0);
5347 }
5348
5349 if (GET_CODE (pattern) == SET)
5350 {
5351 if (reg_mentioned_p (reg, SET_DEST (pattern)))
5352 {
5353 /* We don't use rtx_equal_p, because we don't care if the
5354 mode is different. */
5355 if (!REG_P (SET_DEST (pattern))
5356 || REGNO (reg) != REGNO (SET_DEST (pattern)))
5357 return true;
5358
5359 *set = pattern;
5360 }
5361
5362 pattern = SET_SRC (pattern);
5363 }
5364
5365 if (GET_CODE (pattern) != CALL
5366 || !MEM_P (XEXP (pattern, 0))
5367 || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0)))
5368 return true;
5369
5370 return false;
5371 }
5372
5373 /* Given a X, a pattern of an insn or a part of it, return a mask of used
5374 general registers. Bits 0..15 mean that the respective registers
5375 are used as inputs in the instruction. Bits 16..31 mean that the
5376 registers 0..15, respectively, are used as outputs, or are clobbered.
5377 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
5378 int
regs_used(rtx x,int is_dest)5379 regs_used (rtx x, int is_dest)
5380 {
5381 enum rtx_code code;
5382 const char *fmt;
5383 int used = 0;
5384
5385 if (! x)
5386 return used;
5387 code = GET_CODE (x);
5388 switch (code)
5389 {
5390 case REG:
5391 if (REGNO (x) < 16)
5392 return (((1 << hard_regno_nregs (0, GET_MODE (x))) - 1)
5393 << (REGNO (x) + is_dest));
5394 return 0;
5395 case SUBREG:
5396 {
5397 rtx y = SUBREG_REG (x);
5398
5399 if (!REG_P (y))
5400 break;
5401 if (REGNO (y) < 16)
5402 return (((1 << hard_regno_nregs (0, GET_MODE (x))) - 1)
5403 << (REGNO (y) +
5404 subreg_regno_offset (REGNO (y),
5405 GET_MODE (y),
5406 SUBREG_BYTE (x),
5407 GET_MODE (x)) + is_dest));
5408 return 0;
5409 }
5410 case SET:
5411 return regs_used (SET_SRC (x), 0) | regs_used (SET_DEST (x), 16);
5412 case RETURN:
5413 /* If there was a return value, it must have been indicated with USE. */
5414 return 0x00ffff00;
5415 case CLOBBER:
5416 is_dest = 1;
5417 break;
5418 case MEM:
5419 is_dest = 0;
5420 break;
5421 case CALL:
5422 used |= 0x00ff00f0;
5423 break;
5424 default:
5425 break;
5426 }
5427
5428 fmt = GET_RTX_FORMAT (code);
5429
5430 for (int i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5431 {
5432 if (fmt[i] == 'E')
5433 {
5434 for (int j = XVECLEN (x, i) - 1; j >= 0; j--)
5435 used |= regs_used (XVECEXP (x, i, j), is_dest);
5436 }
5437 else if (fmt[i] == 'e')
5438 used |= regs_used (XEXP (x, i), is_dest);
5439 }
5440 return used;
5441 }
5442
5443 /* Create an instruction that prevents redirection of a conditional branch
5444 to the destination of the JUMP with address ADDR.
5445 If the branch needs to be implemented as an indirect jump, try to find
5446 a scratch register for it.
5447 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
5448 If any preceding insn that doesn't fit into a delay slot is good enough,
5449 pass 1. Pass 2 if a definite blocking insn is needed.
5450 -1 is used internally to avoid deep recursion.
5451 If a blocking instruction is made or recognized, return it. */
5452 static rtx_insn *
gen_block_redirect(rtx_insn * jump,int addr,int need_block)5453 gen_block_redirect (rtx_insn *jump, int addr, int need_block)
5454 {
5455 int dead = 0;
5456 rtx_insn *prev = prev_nonnote_insn (jump);
5457
5458 /* First, check if we already have an instruction that satisfies our need. */
5459 if (prev && NONJUMP_INSN_P (prev) && ! prev->deleted ())
5460 {
5461 if (INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
5462 return prev;
5463 if (GET_CODE (PATTERN (prev)) == USE
5464 || GET_CODE (PATTERN (prev)) == CLOBBER
5465 || get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
5466 prev = jump;
5467 else if ((need_block &= ~1) < 0)
5468 return prev;
5469 else if (recog_memoized (prev) == CODE_FOR_block_branch_redirect)
5470 need_block = 0;
5471 }
5472 if (GET_CODE (PATTERN (jump)) == RETURN)
5473 {
5474 if (! need_block)
5475 return prev;
5476 /* Reorg even does nasty things with return insns that cause branches
5477 to go out of range - see find_end_label and callers. */
5478 return emit_insn_before (gen_block_branch_redirect (const0_rtx) , jump);
5479 }
5480 /* We can't use JUMP_LABEL here because it might be undefined
5481 when not optimizing. */
5482 rtx dest = XEXP (SET_SRC (PATTERN (jump)), 0);
5483 /* If the branch is out of range, try to find a scratch register for it. */
5484 if (optimize
5485 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
5486 > 4092 + 4098))
5487 {
5488 rtx_insn *scan;
5489 /* Don't look for the stack pointer as a scratch register,
5490 it would cause trouble if an interrupt occurred. */
5491 unsigned attempt = 0x7fff, used;
5492 int jump_left = flag_expensive_optimizations + 1;
5493
5494 /* It is likely that the most recent eligible instruction is wanted for
5495 the delay slot. Therefore, find out which registers it uses, and
5496 try to avoid using them. */
5497
5498 for (scan = jump; (scan = PREV_INSN (scan)); )
5499 {
5500 if (scan->deleted ())
5501 continue;
5502 rtx_code code = GET_CODE (scan);
5503 if (code == CODE_LABEL || code == JUMP_INSN)
5504 break;
5505 if (code == INSN
5506 && GET_CODE (PATTERN (scan)) != USE
5507 && GET_CODE (PATTERN (scan)) != CLOBBER
5508 && get_attr_in_delay_slot (scan) == IN_DELAY_SLOT_YES)
5509 {
5510 attempt &= ~regs_used (PATTERN (scan), 0);
5511 break;
5512 }
5513 }
5514 for (used = dead = 0, scan = JUMP_LABEL_AS_INSN (jump);
5515 (scan = NEXT_INSN (scan)); )
5516 {
5517 if (scan->deleted ())
5518 continue;
5519 rtx_code code = GET_CODE (scan);
5520 if (INSN_P (scan))
5521 {
5522 used |= regs_used (PATTERN (scan), 0);
5523 if (code == CALL_INSN)
5524 used |= regs_used (CALL_INSN_FUNCTION_USAGE (scan), 0);
5525 dead |= (used >> 16) & ~used;
5526 if (dead & attempt)
5527 {
5528 dead &= attempt;
5529 break;
5530 }
5531 if (code == JUMP_INSN)
5532 {
5533 if (jump_left-- && simplejump_p (scan))
5534 scan = JUMP_LABEL_AS_INSN (scan);
5535 else
5536 break;
5537 }
5538 }
5539 }
5540 /* Mask out the stack pointer again, in case it was
5541 the only 'free' register we have found. */
5542 dead &= 0x7fff;
5543 }
5544 /* If the immediate destination is still in range, check for possible
5545 threading with a jump beyond the delay slot insn.
5546 Don't check if we are called recursively; the jump has been or will be
5547 checked in a different invocation then. */
5548
5549 else if (optimize && need_block >= 0)
5550 {
5551 rtx_insn *next = next_active_insn (as_a<rtx_insn *> (dest));
5552 next = next_active_insn (next);
5553 if (next && JUMP_P (next)
5554 && GET_CODE (PATTERN (next)) == SET
5555 && recog_memoized (next) == CODE_FOR_jump_compact)
5556 {
5557 dest = JUMP_LABEL (next);
5558 if (dest
5559 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
5560 > 4092 + 4098))
5561 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), -1);
5562 }
5563 }
5564
5565 if (dead)
5566 {
5567 rtx reg = gen_rtx_REG (SImode, exact_log2 (dead & -dead));
5568
5569 /* It would be nice if we could convert the jump into an indirect
5570 jump / far branch right now, and thus exposing all constituent
5571 instructions to further optimization. However, reorg uses
5572 simplejump_p to determine if there is an unconditional jump where
5573 it should try to schedule instructions from the target of the
5574 branch; simplejump_p fails for indirect jumps even if they have
5575 a JUMP_LABEL. */
5576 rtx_insn *insn = emit_insn_before (gen_indirect_jump_scratch
5577 (reg, GEN_INT (unspec_bbr_uid++)),
5578 jump);
5579 /* ??? We would like this to have the scope of the jump, but that
5580 scope will change when a delay slot insn of an inner scope is added.
5581 Hence, after delay slot scheduling, we'll have to expect
5582 NOTE_INSN_BLOCK_END notes between the indirect_jump_scratch and
5583 the jump. */
5584
5585 INSN_LOCATION (insn) = INSN_LOCATION (jump);
5586 INSN_CODE (insn) = CODE_FOR_indirect_jump_scratch;
5587 return insn;
5588 }
5589 else if (need_block)
5590 /* We can't use JUMP_LABEL here because it might be undefined
5591 when not optimizing. */
5592 return emit_insn_before (gen_block_branch_redirect
5593 (GEN_INT (unspec_bbr_uid++)),
5594 jump);
5595 return prev;
5596 }
5597
5598 #define CONDJUMP_MIN -252
5599 #define CONDJUMP_MAX 262
5600 struct far_branch
5601 {
5602 /* A label (to be placed) in front of the jump
5603 that jumps to our ultimate destination. */
5604 rtx_insn *near_label;
5605 /* Where we are going to insert it if we cannot move the jump any farther,
5606 or the jump itself if we have picked up an existing jump. */
5607 rtx_insn *insert_place;
5608 /* The ultimate destination. */
5609 rtx_insn *far_label;
5610 struct far_branch *prev;
5611 /* If the branch has already been created, its address;
5612 else the address of its first prospective user. */
5613 int address;
5614 };
5615
5616 enum mdep_reorg_phase_e mdep_reorg_phase;
5617
5618 static void
gen_far_branch(struct far_branch * bp)5619 gen_far_branch (struct far_branch *bp)
5620 {
5621 rtx_insn *insn = bp->insert_place;
5622 rtx_jump_insn *jump;
5623 rtx_code_label *label = gen_label_rtx ();
5624
5625 emit_label_after (label, insn);
5626 if (bp->far_label)
5627 {
5628 jump = emit_jump_insn_after (gen_jump (bp->far_label), insn);
5629 LABEL_NUSES (bp->far_label)++;
5630 }
5631 else
5632 jump = emit_jump_insn_after (gen_return (), insn);
5633
5634 /* Emit a barrier so that reorg knows that any following instructions
5635 are not reachable via a fall-through path.
5636 But don't do this when not optimizing, since we wouldn't suppress the
5637 alignment for the barrier then, and could end up with out-of-range
5638 pc-relative loads. */
5639 if (optimize)
5640 emit_barrier_after (jump);
5641 emit_label_after (bp->near_label, insn);
5642
5643 if (bp->far_label)
5644 JUMP_LABEL (jump) = bp->far_label;
5645 else
5646 {
5647 rtx pat = PATTERN (jump);
5648 gcc_assert (ANY_RETURN_P (pat));
5649 JUMP_LABEL (jump) = pat;
5650 }
5651
5652 bool ok = invert_jump (as_a <rtx_jump_insn *> (insn), label, 1);
5653 gcc_assert (ok);
5654
5655 /* If we are branching around a jump (rather than a return), prevent
5656 reorg from using an insn from the jump target as the delay slot insn -
5657 when reorg did this, it pessimized code (we rather hide the delay slot)
5658 and it could cause branches to go out of range. */
5659 if (bp->far_label)
5660 (emit_insn_after
5661 (gen_stuff_delay_slot
5662 (GEN_INT (unspec_bbr_uid++),
5663 GEN_INT (recog_memoized (insn) == CODE_FOR_branch_false)),
5664 insn));
5665 /* Prevent reorg from undoing our splits. */
5666 gen_block_redirect (jump, bp->address += 2, 2);
5667 }
5668
5669 /* Fix up ADDR_DIFF_VECs. */
5670 void
fixup_addr_diff_vecs(rtx_insn * first)5671 fixup_addr_diff_vecs (rtx_insn *first)
5672 {
5673 rtx_insn *insn;
5674
5675 for (insn = first; insn; insn = NEXT_INSN (insn))
5676 {
5677 rtx vec_lab, pat, prevpat, x, braf_label;
5678 rtx_insn *prev;
5679
5680 if (! JUMP_TABLE_DATA_P (insn)
5681 || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
5682 continue;
5683 pat = PATTERN (insn);
5684 vec_lab = XEXP (XEXP (pat, 0), 0);
5685
5686 /* Search the matching casesi_jump_2. */
5687 for (prev = as_a <rtx_insn *> (vec_lab); ; prev = PREV_INSN (prev))
5688 {
5689 if (!JUMP_P (prev))
5690 continue;
5691 prevpat = PATTERN (prev);
5692 if (GET_CODE (prevpat) != PARALLEL || XVECLEN (prevpat, 0) != 2)
5693 continue;
5694 x = XVECEXP (prevpat, 0, 1);
5695 if (GET_CODE (x) != USE)
5696 continue;
5697 x = XEXP (x, 0);
5698 if (GET_CODE (x) == LABEL_REF && XEXP (x, 0) == vec_lab)
5699 break;
5700 }
5701 /* FIXME: This is a bug in the optimizer, but it seems harmless
5702 to just avoid panicing. */
5703 if (!prev)
5704 continue;
5705
5706 /* Emit the reference label of the braf where it belongs, right after
5707 the casesi_jump_2 (i.e. braf). */
5708 braf_label = XEXP (XEXP (SET_SRC (XVECEXP (prevpat, 0, 0)), 1), 0);
5709 emit_label_after (braf_label, prev);
5710
5711 /* Fix up the ADDR_DIF_VEC to be relative
5712 to the reference address of the braf. */
5713 XEXP (XEXP (pat, 0), 0) = braf_label;
5714 }
5715 }
5716
5717 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
5718 a barrier. Return the base 2 logarithm of the desired alignment. */
5719 int
barrier_align(rtx_insn * barrier_or_label)5720 barrier_align (rtx_insn *barrier_or_label)
5721 {
5722 if (! barrier_or_label)
5723 return 0;
5724
5725 if (LABEL_P (barrier_or_label)
5726 && NEXT_INSN (barrier_or_label)
5727 && JUMP_TABLE_DATA_P (NEXT_INSN (barrier_or_label)))
5728 return 2;
5729
5730 if (BARRIER_P (barrier_or_label)
5731 && PREV_INSN (barrier_or_label)
5732 && JUMP_TABLE_DATA_P (PREV_INSN (barrier_or_label)))
5733 {
5734 rtx pat = PATTERN (PREV_INSN (barrier_or_label));
5735 /* If this is a very small table, we want to keep the alignment after
5736 the table to the minimum for proper code alignment. */
5737 return ((optimize_size
5738 || ((unsigned) XVECLEN (pat, 1) * GET_MODE_SIZE (GET_MODE (pat))
5739 <= (unsigned) 1 << (CACHE_LOG - 2)))
5740 ? 1 : align_jumps_log);
5741 }
5742
5743 rtx_insn *next = next_active_insn (barrier_or_label);
5744
5745 if (! next)
5746 return 0;
5747
5748 rtx pat = PATTERN (next);
5749
5750 if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_ALIGN)
5751 /* This is a barrier in front of a constant table. */
5752 return 0;
5753
5754 if (optimize_size)
5755 return 0;
5756
5757 if (! TARGET_SH2 || ! optimize)
5758 return align_jumps_log;
5759
5760 /* When fixing up pcloads, a constant table might be inserted just before
5761 the basic block that ends with the barrier. Thus, we can't trust the
5762 instruction lengths before that. */
5763 if (mdep_reorg_phase > SH_FIXUP_PCLOAD)
5764 {
5765 /* Check if there is an immediately preceding branch to the insn beyond
5766 the barrier. We must weight the cost of discarding useful information
5767 from the current cache line when executing this branch and there is
5768 an alignment, against that of fetching unneeded insn in front of the
5769 branch target when there is no alignment. */
5770
5771 /* There are two delay_slot cases to consider. One is the simple case
5772 where the preceding branch is to the insn beyond the barrier (simple
5773 delay slot filling), and the other is where the preceding branch has
5774 a delay slot that is a duplicate of the insn after the barrier
5775 (fill_eager_delay_slots) and the branch is to the insn after the insn
5776 after the barrier. */
5777
5778 int slot, credit;
5779 bool jump_to_next = false;
5780
5781 /* Skip to the insn before the JUMP_INSN before the barrier under
5782 investigation. */
5783 rtx_insn *prev = prev_real_insn (prev_active_insn (barrier_or_label));
5784
5785 for (slot = 2, credit = (1 << (CACHE_LOG - 2)) + 2;
5786 credit >= 0 && prev && NONJUMP_INSN_P (prev);
5787 prev = prev_real_insn (prev))
5788 {
5789 jump_to_next = false;
5790 if (GET_CODE (PATTERN (prev)) == USE
5791 || GET_CODE (PATTERN (prev)) == CLOBBER)
5792 continue;
5793 if (rtx_sequence *prev_seq = dyn_cast <rtx_sequence *> (PATTERN (prev)))
5794 {
5795 prev = prev_seq->insn (1);
5796 if (INSN_UID (prev) == INSN_UID (next))
5797 {
5798 /* Delay slot was filled with insn at jump target. */
5799 jump_to_next = true;
5800 continue;
5801 }
5802 }
5803
5804 if (slot &&
5805 get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
5806 slot = 0;
5807 credit -= get_attr_length (prev);
5808 }
5809 if (prev && jump_to_label_p (prev))
5810 {
5811 rtx_insn *x;
5812 if (jump_to_next
5813 || next_real_insn (JUMP_LABEL (prev)) == next
5814 /* If relax_delay_slots() decides NEXT was redundant
5815 with some previous instruction, it will have
5816 redirected PREV's jump to the following insn. */
5817 || JUMP_LABEL (prev) == next_nonnote_insn (next)
5818 /* There is no upper bound on redundant instructions
5819 that might have been skipped, but we must not put an
5820 alignment where none had been before. */
5821 || (x = (NEXT_INSN (NEXT_INSN (PREV_INSN (prev)))),
5822 (INSN_P (x)
5823 && (INSN_CODE (x) == CODE_FOR_block_branch_redirect
5824 || INSN_CODE (x) == CODE_FOR_indirect_jump_scratch
5825 || INSN_CODE (x) == CODE_FOR_stuff_delay_slot))))
5826 {
5827 rtx pat = PATTERN (prev);
5828 if (GET_CODE (pat) == PARALLEL)
5829 pat = XVECEXP (pat, 0, 0);
5830 if (credit - slot >= (GET_CODE (SET_SRC (pat)) == PC ? 2 : 0))
5831 return 0;
5832 }
5833 }
5834 }
5835
5836 return align_jumps_log;
5837 }
5838
5839 /* If we are inside a phony loop, almost any kind of label can turn up as the
5840 first one in the loop. Aligning a braf label causes incorrect switch
5841 destination addresses; we can detect braf labels because they are
5842 followed by a BARRIER.
5843 Applying loop alignment to small constant or switch tables is a waste
5844 of space, so we suppress this too. */
5845 int
sh_loop_align(rtx_insn * label)5846 sh_loop_align (rtx_insn *label)
5847 {
5848 rtx_insn *next = label;
5849
5850 if (! optimize || optimize_size)
5851 return 0;
5852
5853 do
5854 next = next_nonnote_insn (next);
5855 while (next && LABEL_P (next));
5856
5857 if (! next
5858 || ! INSN_P (next)
5859 || recog_memoized (next) == CODE_FOR_consttable_2)
5860 return 0;
5861
5862 return align_loops_log;
5863 }
5864
5865 /* Do a final pass over the function, just before delayed branch
5866 scheduling. */
5867 static void
sh_reorg(void)5868 sh_reorg (void)
5869 {
5870 rtx_insn *first, *insn, *mova = NULL;
5871 int num_mova;
5872 rtx r0_rtx = gen_rtx_REG (Pmode, 0);
5873 rtx r0_inc_rtx = gen_rtx_POST_INC (Pmode, r0_rtx);
5874
5875 first = get_insns ();
5876 max_labelno_before_reorg = max_label_num ();
5877
5878 /* We must split call insns before introducing `mova's. If we're
5879 optimizing, they'll have already been split. Otherwise, make
5880 sure we don't split them too late. */
5881 if (! optimize)
5882 split_all_insns_noflow ();
5883
5884 /* If relaxing, generate pseudo-ops to associate function calls with
5885 the symbols they call. It does no harm to not generate these
5886 pseudo-ops. However, when we can generate them, it enables the
5887 linker to potentially relax the jsr to a bsr, and eliminate the
5888 register load and, possibly, the constant pool entry. */
5889
5890 mdep_reorg_phase = SH_INSERT_USES_LABELS;
5891 if (TARGET_RELAX)
5892 {
5893 /* Remove all REG_LABEL_OPERAND notes. We want to use them for our
5894 own purposes. This works because none of the remaining passes
5895 need to look at them.
5896
5897 ??? But it may break in the future. We should use a machine
5898 dependent REG_NOTE, or some other approach entirely. */
5899 for (insn = first; insn; insn = NEXT_INSN (insn))
5900 {
5901 if (INSN_P (insn))
5902 {
5903 rtx note;
5904
5905 while ((note = find_reg_note (insn, REG_LABEL_OPERAND,
5906 NULL_RTX)) != 0)
5907 remove_note (insn, note);
5908 }
5909 }
5910
5911 for (insn = first; insn; insn = NEXT_INSN (insn))
5912 {
5913 rtx pattern, reg, set, dies;
5914 rtx_code_label *label;
5915 rtx_insn *link, *scan;
5916 int rescan = 0, foundinsn = 0;
5917
5918 if (CALL_P (insn))
5919 {
5920 pattern = PATTERN (insn);
5921
5922 if (GET_CODE (pattern) == PARALLEL)
5923 pattern = XVECEXP (pattern, 0, 0);
5924 if (GET_CODE (pattern) == SET)
5925 pattern = SET_SRC (pattern);
5926
5927 if (GET_CODE (pattern) != CALL
5928 || !MEM_P (XEXP (pattern, 0)))
5929 continue;
5930
5931 reg = XEXP (XEXP (pattern, 0), 0);
5932 }
5933 else
5934 {
5935 reg = sfunc_uses_reg (insn);
5936 if (! reg)
5937 continue;
5938 }
5939
5940 if (!REG_P (reg))
5941 continue;
5942
5943 /* Try scanning backward to find where the register is set. */
5944 link = NULL;
5945 for (scan = PREV_INSN (insn);
5946 scan && !LABEL_P (scan);
5947 scan = PREV_INSN (scan))
5948 {
5949 if (! INSN_P (scan))
5950 continue;
5951
5952 if (! reg_mentioned_p (reg, scan))
5953 continue;
5954
5955 if (noncall_uses_reg (reg, scan, &set))
5956 break;
5957
5958 if (set)
5959 {
5960 link = scan;
5961 break;
5962 }
5963 }
5964
5965 if (! link)
5966 continue;
5967
5968 /* The register is set at LINK. */
5969
5970 /* We can only optimize the function call if the register is
5971 being set to a symbol. In theory, we could sometimes
5972 optimize calls to a constant location, but the assembler
5973 and linker do not support that at present. */
5974 if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
5975 && GET_CODE (SET_SRC (set)) != LABEL_REF)
5976 continue;
5977
5978 /* Scan forward from LINK to the place where REG dies, and
5979 make sure that the only insns which use REG are
5980 themselves function calls. */
5981
5982 /* ??? This doesn't work for call targets that were allocated
5983 by reload, since there may not be a REG_DEAD note for the
5984 register. */
5985
5986 dies = NULL_RTX;
5987 for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan))
5988 {
5989 rtx scanset;
5990
5991 /* Don't try to trace forward past a CODE_LABEL if we haven't
5992 seen INSN yet. Ordinarily, we will only find the setting insn
5993 if it is in the same basic block. However,
5994 cross-jumping can insert code labels in between the load and
5995 the call, and can result in situations where a single call
5996 insn may have two targets depending on where we came from. */
5997
5998 if (LABEL_P (scan) && ! foundinsn)
5999 break;
6000
6001 if (! INSN_P (scan))
6002 continue;
6003
6004 /* Don't try to trace forward past a JUMP. To optimize
6005 safely, we would have to check that all the
6006 instructions at the jump destination did not use REG. */
6007
6008 if (JUMP_P (scan))
6009 break;
6010
6011 if (! reg_mentioned_p (reg, scan))
6012 continue;
6013
6014 if (noncall_uses_reg (reg, scan, &scanset))
6015 break;
6016
6017 if (scan == insn)
6018 foundinsn = 1;
6019
6020 if (scan != insn
6021 && (CALL_P (scan) || sfunc_uses_reg (scan)))
6022 {
6023 /* There is a function call to this register other
6024 than the one we are checking. If we optimize
6025 this call, we need to rescan again below. */
6026 rescan = 1;
6027 }
6028
6029 /* ??? We shouldn't have to worry about SCANSET here.
6030 We should just be able to check for a REG_DEAD note
6031 on a function call. However, the REG_DEAD notes are
6032 apparently not dependable around libcalls; c-torture
6033 execute/920501-2 is a test case. If SCANSET is set,
6034 then this insn sets the register, so it must have
6035 died earlier. Unfortunately, this will only handle
6036 the cases in which the register is, in fact, set in a
6037 later insn. */
6038
6039 /* ??? We shouldn't have to use FOUNDINSN here.
6040 This dates back to when we used LOG_LINKS to find
6041 the most recent insn which sets the register. */
6042
6043 if (foundinsn
6044 && (scanset
6045 || find_reg_note (scan, REG_DEAD, reg)))
6046 {
6047 dies = scan;
6048 break;
6049 }
6050 }
6051
6052 if (! dies)
6053 {
6054 /* Either there was a branch, or some insn used REG
6055 other than as a function call address. */
6056 continue;
6057 }
6058
6059 /* Create a code label, and put it in a REG_LABEL_OPERAND note
6060 on the insn which sets the register, and on each call insn
6061 which uses the register. In final_prescan_insn we look for
6062 the REG_LABEL_OPERAND notes, and output the appropriate label
6063 or pseudo-op. */
6064
6065 label = gen_label_rtx ();
6066 add_reg_note (link, REG_LABEL_OPERAND, label);
6067 add_reg_note (insn, REG_LABEL_OPERAND, label);
6068 if (rescan)
6069 {
6070 scan = link;
6071 do
6072 {
6073 rtx reg2;
6074
6075 scan = NEXT_INSN (scan);
6076 if (scan != insn
6077 && ((CALL_P (scan)
6078 && reg_mentioned_p (reg, scan))
6079 || ((reg2 = sfunc_uses_reg (scan))
6080 && REGNO (reg2) == REGNO (reg))))
6081 add_reg_note (scan, REG_LABEL_OPERAND, label);
6082 }
6083 while (scan != dies);
6084 }
6085 }
6086 }
6087
6088 if (TARGET_SH2)
6089 fixup_addr_diff_vecs (first);
6090
6091 if (optimize)
6092 {
6093 mdep_reorg_phase = SH_SHORTEN_BRANCHES0;
6094 shorten_branches (first);
6095 }
6096
6097 /* Scan the function looking for move instructions which have to be
6098 changed to pc-relative loads and insert the literal tables. */
6099 mdep_reorg_phase = SH_FIXUP_PCLOAD;
6100 for (insn = first, num_mova = 0; insn; insn = NEXT_INSN (insn))
6101 {
6102 if (mova_p (insn))
6103 {
6104 /* ??? basic block reordering can move a switch table dispatch
6105 below the switch table. Check if that has happened.
6106 We only have the addresses available when optimizing; but then,
6107 this check shouldn't be needed when not optimizing. */
6108 if (!untangle_mova (&num_mova, &mova, insn))
6109 {
6110 insn = mova;
6111 num_mova = 0;
6112 }
6113 }
6114 else if (JUMP_TABLE_DATA_P (insn)
6115 && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
6116 && num_mova
6117 /* ??? loop invariant motion can also move a mova out of a
6118 loop. Since loop does this code motion anyway, maybe we
6119 should wrap UNSPEC_MOVA into a CONST, so that reload can
6120 move it back. */
6121 && ((num_mova > 1
6122 && GET_MODE (prev_nonnote_insn (insn)) == VOIDmode)
6123 || (prev_nonnote_insn (insn)
6124 == XEXP (MOVA_LABELREF (mova), 0))))
6125 {
6126 rtx_insn *scan;
6127 int total;
6128
6129 num_mova--;
6130
6131 /* Some code might have been inserted between the mova and
6132 its ADDR_DIFF_VEC. Check if the mova is still in range. */
6133 for (scan = mova, total = 0; scan != insn; scan = NEXT_INSN (scan))
6134 total += get_attr_length (scan);
6135
6136 /* range of mova is 1020, add 4 because pc counts from address of
6137 second instruction after this one, subtract 2 in case pc is 2
6138 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
6139 cancels out with alignment effects of the mova itself. */
6140 if (total > 1022)
6141 {
6142 /* Change the mova into a load, and restart scanning
6143 there. broken_move will then return true for mova. */
6144 fixup_mova (mova);
6145 insn = mova;
6146 }
6147 }
6148 if (broken_move (insn)
6149 || (NONJUMP_INSN_P (insn)
6150 && recog_memoized (insn) == CODE_FOR_casesi_worker_2))
6151 {
6152 rtx_insn *scan;
6153 /* Scan ahead looking for a barrier to stick the constant table
6154 behind. */
6155 rtx_insn *barrier = find_barrier (num_mova, mova, insn);
6156 rtx_insn *last_float_move = NULL;
6157 rtx last_float = 0, *last_float_addr = NULL;
6158 int need_aligned_label = 0;
6159
6160 if (num_mova && ! mova_p (mova))
6161 {
6162 /* find_barrier had to change the first mova into a
6163 pcload; thus, we have to start with this new pcload. */
6164 insn = mova;
6165 num_mova = 0;
6166 }
6167 /* Now find all the moves between the points and modify them. */
6168 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
6169 {
6170 if (LABEL_P (scan))
6171 last_float = 0;
6172 if (NONJUMP_INSN_P (scan)
6173 && recog_memoized (scan) == CODE_FOR_casesi_worker_2)
6174 need_aligned_label = 1;
6175 if (broken_move (scan))
6176 {
6177 rtx *patp = &PATTERN (scan), pat = *patp;
6178 rtx src, dst;
6179 rtx lab;
6180 rtx newsrc;
6181 machine_mode mode;
6182
6183 if (GET_CODE (pat) == PARALLEL)
6184 patp = &XVECEXP (pat, 0, 0), pat = *patp;
6185 src = SET_SRC (pat);
6186 dst = SET_DEST (pat);
6187 mode = GET_MODE (dst);
6188
6189 if (mode == SImode && satisfies_constraint_I16 (src)
6190 && REGNO (dst) != FPUL_REG)
6191 {
6192 int offset = 0;
6193
6194 mode = HImode;
6195 while (GET_CODE (dst) == SUBREG)
6196 {
6197 offset += subreg_regno_offset (REGNO (SUBREG_REG (dst)),
6198 GET_MODE (SUBREG_REG (dst)),
6199 SUBREG_BYTE (dst),
6200 GET_MODE (dst));
6201 dst = SUBREG_REG (dst);
6202 }
6203 dst = gen_rtx_REG (HImode, REGNO (dst) + offset);
6204 }
6205 if (REG_P (dst) && FP_ANY_REGISTER_P (REGNO (dst)))
6206 {
6207 /* This must be an insn that clobbers r0. */
6208 rtx *clobberp = &XVECEXP (PATTERN (scan), 0,
6209 XVECLEN (PATTERN (scan), 0)
6210 - 1);
6211 rtx clobber = *clobberp;
6212
6213 gcc_assert (GET_CODE (clobber) == CLOBBER
6214 && rtx_equal_p (XEXP (clobber, 0), r0_rtx));
6215
6216 if (last_float
6217 && reg_set_between_p (r0_rtx, last_float_move, scan))
6218 last_float = 0;
6219 lab = add_constant (src, mode, last_float);
6220 if (lab)
6221 emit_insn_before (gen_mova (lab), scan);
6222 else
6223 {
6224 /* There will be a REG_UNUSED note for r0 on
6225 LAST_FLOAT_MOVE; we have to change it to REG_INC,
6226 lest reorg:mark_target_live_regs will not
6227 consider r0 to be used, and we end up with delay
6228 slot insn in front of SCAN that clobbers r0. */
6229 rtx note
6230 = find_regno_note (last_float_move, REG_UNUSED, 0);
6231
6232 /* If we are not optimizing, then there may not be
6233 a note. */
6234 if (note)
6235 PUT_REG_NOTE_KIND (note, REG_INC);
6236
6237 *last_float_addr = r0_inc_rtx;
6238 }
6239 last_float_move = scan;
6240 last_float = src;
6241 newsrc = gen_const_mem (mode,
6242 (((TARGET_SH4 && ! TARGET_FMOVD)
6243 || REGNO (dst) == FPUL_REG)
6244 ? r0_inc_rtx
6245 : r0_rtx));
6246 last_float_addr = &XEXP (newsrc, 0);
6247
6248 /* Remove the clobber of r0. */
6249 *clobberp = gen_rtx_CLOBBER (GET_MODE (clobber),
6250 gen_rtx_SCRATCH (Pmode));
6251 }
6252 /* This is a mova needing a label. Create it. */
6253 else if (GET_CODE (src) == UNSPEC
6254 && XINT (src, 1) == UNSPEC_MOVA
6255 && GET_CODE (XVECEXP (src, 0, 0)) == CONST)
6256 {
6257 lab = add_constant (XVECEXP (src, 0, 0), mode, 0);
6258 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
6259 newsrc = gen_rtx_UNSPEC (SImode,
6260 gen_rtvec (1, newsrc),
6261 UNSPEC_MOVA);
6262 }
6263 else if (GET_CODE (src) == UNSPEC_VOLATILE
6264 && XINT (src, 1) == UNSPECV_SP_SWITCH_B)
6265 {
6266 newsrc = XVECEXP (src, 0, 0);
6267 XVECEXP (src, 0, 0) = gen_const_mem (mode, newsrc);
6268 INSN_CODE (scan) = -1;
6269 continue;
6270 }
6271 else
6272 {
6273 lab = add_constant (src, mode, 0);
6274 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
6275 newsrc = gen_const_mem (mode, newsrc);
6276 }
6277 *patp = gen_rtx_SET (dst, newsrc);
6278 INSN_CODE (scan) = -1;
6279 }
6280 }
6281 dump_table (need_aligned_label ? insn : 0, barrier);
6282 insn = barrier;
6283 }
6284 }
6285 label_ref_list_d_pool.release ();
6286 for (insn = first; insn; insn = NEXT_INSN (insn))
6287 PUT_MODE (insn, VOIDmode);
6288
6289 mdep_reorg_phase = SH_SHORTEN_BRANCHES1;
6290 INSN_ADDRESSES_FREE ();
6291 split_branches (first);
6292
6293 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
6294 also has an effect on the register that holds the address of the sfunc.
6295 Insert an extra dummy insn in front of each sfunc that pretends to
6296 use this register. */
6297 if (flag_delayed_branch)
6298 {
6299 for (insn = first; insn; insn = NEXT_INSN (insn))
6300 {
6301 rtx reg = sfunc_uses_reg (insn);
6302
6303 if (! reg)
6304 continue;
6305 emit_insn_before (gen_use_sfunc_addr (reg), insn);
6306 }
6307 }
6308 mdep_reorg_phase = SH_AFTER_MDEP_REORG;
6309 }
6310
6311 /* Return the UID of the insn that follows the specified label. */
6312 int
get_dest_uid(rtx label,int max_uid)6313 get_dest_uid (rtx label, int max_uid)
6314 {
6315 rtx_insn *dest = next_real_insn (label);
6316
6317 if (! dest)
6318 /* This can happen for an undefined label. */
6319 return 0;
6320 int dest_uid = INSN_UID (dest);
6321 /* If this is a newly created branch redirection blocking instruction,
6322 we cannot index the branch_uid or insn_addresses arrays with its
6323 uid. But then, we won't need to, because the actual destination is
6324 the following branch. */
6325 while (dest_uid >= max_uid)
6326 {
6327 dest = NEXT_INSN (dest);
6328 dest_uid = INSN_UID (dest);
6329 }
6330 if (JUMP_P (dest) && GET_CODE (PATTERN (dest)) == RETURN)
6331 return 0;
6332 return dest_uid;
6333 }
6334
6335 /* Split condbranches that are out of range. Also add clobbers for
6336 scratch registers that are needed in far jumps.
6337 We do this before delay slot scheduling, so that it can take our
6338 newly created instructions into account. It also allows us to
6339 find branches with common targets more easily. */
6340 static void
split_branches(rtx_insn * first)6341 split_branches (rtx_insn *first)
6342 {
6343 rtx_insn *insn;
6344 struct far_branch **uid_branch, *far_branch_list = 0;
6345 int max_uid = get_max_uid ();
6346 int ok;
6347
6348 /* Find out which branches are out of range. */
6349 shorten_branches (first);
6350
6351 uid_branch = (struct far_branch **) alloca (max_uid * sizeof *uid_branch);
6352 memset ((char *) uid_branch, 0, max_uid * sizeof *uid_branch);
6353
6354 for (insn = first; insn; insn = NEXT_INSN (insn))
6355 if (! INSN_P (insn))
6356 continue;
6357 else if (insn->deleted ())
6358 {
6359 /* Shorten_branches would split this instruction again,
6360 so transform it into a note. */
6361 SET_INSN_DELETED (insn);
6362 }
6363 else if (JUMP_P (insn))
6364 {
6365 enum attr_type type = get_attr_type (insn);
6366 if (type == TYPE_CBRANCH)
6367 {
6368 rtx_insn *next, *beyond;
6369
6370 if (get_attr_length (insn) > 4)
6371 {
6372 rtx src = SET_SRC (PATTERN (insn));
6373 rtx olabel = XEXP (XEXP (src, 1), 0);
6374 int addr = INSN_ADDRESSES (INSN_UID (insn));
6375 rtx_insn *label = 0;
6376 int dest_uid = get_dest_uid (olabel, max_uid);
6377 struct far_branch *bp = uid_branch[dest_uid];
6378
6379 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
6380 the label if the LABEL_NUSES count drops to zero. There is
6381 always a jump_optimize pass that sets these values, but it
6382 proceeds to delete unreferenced code, and then if not
6383 optimizing, to un-delete the deleted instructions, thus
6384 leaving labels with too low uses counts. */
6385 if (! optimize)
6386 {
6387 JUMP_LABEL (insn) = olabel;
6388 LABEL_NUSES (olabel)++;
6389 }
6390 if (! bp)
6391 {
6392 bp = (struct far_branch *) alloca (sizeof *bp);
6393 uid_branch[dest_uid] = bp;
6394 bp->prev = far_branch_list;
6395 far_branch_list = bp;
6396 bp->far_label = as_a <rtx_insn *> (
6397 XEXP (XEXP (SET_SRC (PATTERN (insn)), 1),
6398 0));
6399 LABEL_NUSES (bp->far_label)++;
6400 }
6401 else
6402 {
6403 label = bp->near_label;
6404 if (! label && bp->address - addr >= CONDJUMP_MIN)
6405 {
6406 rtx_insn *block = bp->insert_place;
6407
6408 if (GET_CODE (PATTERN (block)) == RETURN)
6409 block = PREV_INSN (block);
6410 else
6411 block = gen_block_redirect (block,
6412 bp->address, 2);
6413 label = emit_label_after (gen_label_rtx (),
6414 PREV_INSN (block));
6415 bp->near_label = label;
6416 }
6417 else if (label && ! NEXT_INSN (label))
6418 {
6419 if (addr + 2 - bp->address <= CONDJUMP_MAX)
6420 bp->insert_place = insn;
6421 else
6422 gen_far_branch (bp);
6423 }
6424 }
6425 if (! label
6426 || (NEXT_INSN (label) && bp->address - addr < CONDJUMP_MIN))
6427 {
6428 bp->near_label = label = gen_label_rtx ();
6429 bp->insert_place = insn;
6430 bp->address = addr;
6431 }
6432 ok = redirect_jump (as_a <rtx_jump_insn *> (insn), label, 0);
6433 gcc_assert (ok);
6434 }
6435 else
6436 {
6437 /* get_attr_length (insn) == 2 */
6438 /* Check if we have a pattern where reorg wants to redirect
6439 the branch to a label from an unconditional branch that
6440 is too far away. */
6441 /* We can't use JUMP_LABEL here because it might be undefined
6442 when not optimizing. */
6443 /* A syntax error might cause beyond to be NULL_RTX. */
6444 rtx temp = XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), 0);
6445 beyond = next_active_insn (as_a<rtx_insn *> (temp));
6446
6447 if (beyond
6448 && (JUMP_P (beyond)
6449 || ((beyond = next_active_insn (beyond))
6450 && JUMP_P (beyond)))
6451 && GET_CODE (PATTERN (beyond)) == SET
6452 && recog_memoized (beyond) == CODE_FOR_jump_compact
6453 && ((INSN_ADDRESSES
6454 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond)), 0)))
6455 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
6456 > 252 + 258 + 2))
6457 gen_block_redirect (beyond,
6458 INSN_ADDRESSES (INSN_UID (beyond)), 1);
6459 }
6460
6461 next = next_active_insn (insn);
6462
6463 if (next
6464 && (JUMP_P (next)
6465 || ((next = next_active_insn (next))
6466 && JUMP_P (next)))
6467 && GET_CODE (PATTERN (next)) == SET
6468 && recog_memoized (next) == CODE_FOR_jump_compact
6469 && ((INSN_ADDRESSES
6470 (INSN_UID (XEXP (SET_SRC (PATTERN (next)), 0)))
6471 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
6472 > 252 + 258 + 2))
6473 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), 1);
6474 }
6475 else if (type == TYPE_JUMP || type == TYPE_RETURN)
6476 {
6477 int addr = INSN_ADDRESSES (INSN_UID (insn));
6478 rtx_insn *far_label = 0;
6479 int dest_uid = 0;
6480 struct far_branch *bp;
6481
6482 if (type == TYPE_JUMP)
6483 {
6484 if (CROSSING_JUMP_P (insn))
6485 {
6486 emit_insn_before (gen_block_branch_redirect (const0_rtx),
6487 insn);
6488 continue;
6489 }
6490
6491 far_label = as_a <rtx_insn *> (
6492 XEXP (SET_SRC (PATTERN (insn)), 0));
6493 dest_uid = get_dest_uid (far_label, max_uid);
6494 if (! dest_uid)
6495 {
6496 /* Parse errors can lead to labels outside
6497 the insn stream. */
6498 if (! NEXT_INSN (far_label))
6499 continue;
6500
6501 if (! optimize)
6502 {
6503 JUMP_LABEL (insn) = far_label;
6504 LABEL_NUSES (far_label)++;
6505 }
6506 redirect_jump (as_a <rtx_jump_insn *> (insn), ret_rtx, 1);
6507 far_label = 0;
6508 }
6509 }
6510 bp = uid_branch[dest_uid];
6511 if (! bp)
6512 {
6513 bp = (struct far_branch *) alloca (sizeof *bp);
6514 uid_branch[dest_uid] = bp;
6515 bp->prev = far_branch_list;
6516 far_branch_list = bp;
6517 bp->near_label = 0;
6518 bp->far_label = far_label;
6519 if (far_label)
6520 LABEL_NUSES (far_label)++;
6521 }
6522 else if (bp->near_label && ! NEXT_INSN (bp->near_label))
6523 if (addr - bp->address <= CONDJUMP_MAX)
6524 emit_label_after (bp->near_label, PREV_INSN (insn));
6525 else
6526 {
6527 gen_far_branch (bp);
6528 bp->near_label = 0;
6529 }
6530 else
6531 bp->near_label = 0;
6532 bp->address = addr;
6533 bp->insert_place = insn;
6534 if (! far_label)
6535 emit_insn_before (gen_block_branch_redirect (const0_rtx), insn);
6536 else
6537 gen_block_redirect (insn, addr, bp->near_label ? 2 : 0);
6538 }
6539 }
6540 /* Generate all pending far branches,
6541 and free our references to the far labels. */
6542 while (far_branch_list)
6543 {
6544 if (far_branch_list->near_label
6545 && ! NEXT_INSN (far_branch_list->near_label))
6546 gen_far_branch (far_branch_list);
6547 if (optimize
6548 && far_branch_list->far_label
6549 && ! --LABEL_NUSES (far_branch_list->far_label))
6550 delete_insn (far_branch_list->far_label);
6551 far_branch_list = far_branch_list->prev;
6552 }
6553
6554 /* Instruction length information is no longer valid due to the new
6555 instructions that have been generated. */
6556 init_insn_lengths ();
6557 }
6558
6559 /* Dump out instruction addresses, which is useful for debugging the
6560 constant pool table stuff.
6561
6562 If relaxing, output the label and pseudo-ops used to link together
6563 calls and the instruction which set the registers.
6564
6565 ??? The addresses printed by this routine for insns are nonsense for
6566 insns which are inside of a sequence where none of the inner insns have
6567 variable length. This is because the second pass of shorten_branches
6568 does not bother to update them. */
6569 void
final_prescan_insn(rtx_insn * insn,rtx * opvec ATTRIBUTE_UNUSED,int noperands ATTRIBUTE_UNUSED)6570 final_prescan_insn (rtx_insn *insn, rtx *opvec ATTRIBUTE_UNUSED,
6571 int noperands ATTRIBUTE_UNUSED)
6572 {
6573 if (TARGET_DUMPISIZE)
6574 fprintf (asm_out_file, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn)));
6575
6576 if (TARGET_RELAX)
6577 {
6578 if (rtx note = find_reg_note (insn, REG_LABEL_OPERAND, NULL_RTX))
6579 {
6580 rtx pattern = PATTERN (insn);
6581 if (GET_CODE (pattern) == PARALLEL)
6582 pattern = XVECEXP (pattern, 0, 0);
6583 switch (GET_CODE (pattern))
6584 {
6585 case SET:
6586 if (GET_CODE (SET_SRC (pattern)) != CALL
6587 && get_attr_type (insn) != TYPE_SFUNC)
6588 {
6589 targetm.asm_out.internal_label
6590 (asm_out_file, "L", CODE_LABEL_NUMBER (XEXP (note, 0)));
6591 break;
6592 }
6593 /* FALLTHROUGH */
6594 case CALL:
6595 asm_fprintf (asm_out_file, "\t.uses %LL%d\n",
6596 CODE_LABEL_NUMBER (XEXP (note, 0)));
6597 break;
6598
6599 default:
6600 gcc_unreachable ();
6601 }
6602 }
6603 }
6604 }
6605
6606 /* Dump out any constants accumulated in the final pass. These will
6607 only be labels. */
6608 const char *
output_jump_label_table(void)6609 output_jump_label_table (void)
6610 {
6611 if (pool_size)
6612 {
6613 fprintf (asm_out_file, "\t.align 2\n");
6614 for (int i = 0; i < pool_size; i++)
6615 {
6616 pool_node *p = &pool_vector[i];
6617
6618 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6619 CODE_LABEL_NUMBER (p->label));
6620 output_asm_insn (".long %O0", &p->value);
6621 }
6622 pool_size = 0;
6623 }
6624
6625 return "";
6626 }
6627
6628 /* A full frame looks like:
6629
6630 arg-5
6631 arg-4
6632 [ if current_function_anonymous_args
6633 arg-3
6634 arg-2
6635 arg-1
6636 arg-0 ]
6637 saved-fp
6638 saved-r10
6639 saved-r11
6640 saved-r12
6641 saved-pr
6642 local-n
6643 ..
6644 local-1
6645 local-0 <- fp points here.
6646
6647 Number of bytes pushed for anonymous args, used to pass information
6648 between expand_prologue and expand_epilogue.
6649
6650 Adjust the stack by SIZE bytes. REG holds the rtl of the register to be
6651 adjusted. If epilogue_p is zero, this is for a prologue; otherwise, it's
6652 for an epilogue and a negative value means that it's for a sibcall
6653 epilogue. If LIVE_REGS_MASK is nonzero, it points to a HARD_REG_SET of
6654 all the registers that are about to be restored, and hence dead. */
6655 static void
output_stack_adjust(int size,rtx reg,int epilogue_p,HARD_REG_SET * live_regs_mask,bool frame_p)6656 output_stack_adjust (int size, rtx reg, int epilogue_p,
6657 HARD_REG_SET *live_regs_mask, bool frame_p)
6658 {
6659 rtx_insn *(*emit_fn) (rtx) = frame_p ? &emit_frame_insn : &emit_insn;
6660 if (size)
6661 {
6662 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
6663
6664 /* This test is bogus, as output_stack_adjust is used to re-align the
6665 stack. */
6666 #if 0
6667 gcc_assert (!(size % align));
6668 #endif
6669
6670 if (CONST_OK_FOR_ADD (size))
6671 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size)));
6672 /* Try to do it with two partial adjustments; however, we must make
6673 sure that the stack is properly aligned at all times, in case
6674 an interrupt occurs between the two partial adjustments. */
6675 else if (CONST_OK_FOR_ADD (size / 2 & -align)
6676 && CONST_OK_FOR_ADD (size - (size / 2 & -align)))
6677 {
6678 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size / 2 & -align)));
6679 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size - (size / 2 & -align))));
6680 }
6681 else
6682 {
6683 rtx const_reg;
6684 rtx insn;
6685 int temp = epilogue_p ? 7 : 1;
6686 int i;
6687
6688 /* If TEMP is invalid, we could temporarily save a general
6689 register to MACL. However, there is currently no need
6690 to handle this case, so just die when we see it. */
6691 if (epilogue_p < 0
6692 || current_function_interrupt
6693 || ! call_really_used_regs[temp] || fixed_regs[temp])
6694 temp = -1;
6695 if (temp < 0 && ! current_function_interrupt && epilogue_p >= 0)
6696 {
6697 HARD_REG_SET temps;
6698 COPY_HARD_REG_SET (temps, call_used_reg_set);
6699 AND_COMPL_HARD_REG_SET (temps, call_fixed_reg_set);
6700 if (epilogue_p > 0)
6701 {
6702 int nreg = 0;
6703 if (crtl->return_rtx)
6704 {
6705 machine_mode mode;
6706 mode = GET_MODE (crtl->return_rtx);
6707 if (BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG)
6708 nreg = hard_regno_nregs (FIRST_RET_REG, mode);
6709 }
6710 for (i = 0; i < nreg; i++)
6711 CLEAR_HARD_REG_BIT (temps, FIRST_RET_REG + i);
6712 if (crtl->calls_eh_return)
6713 {
6714 CLEAR_HARD_REG_BIT (temps, EH_RETURN_STACKADJ_REGNO);
6715 for (i = 0; i <= 3; i++)
6716 CLEAR_HARD_REG_BIT (temps, EH_RETURN_DATA_REGNO (i));
6717 }
6718 }
6719 if (epilogue_p <= 0)
6720 {
6721 for (i = FIRST_PARM_REG;
6722 i < FIRST_PARM_REG + NPARM_REGS (SImode); i++)
6723 CLEAR_HARD_REG_BIT (temps, i);
6724 if (cfun->static_chain_decl != NULL)
6725 CLEAR_HARD_REG_BIT (temps, STATIC_CHAIN_REGNUM);
6726 }
6727 temp = scavenge_reg (&temps);
6728 }
6729 if (temp < 0 && live_regs_mask)
6730 {
6731 HARD_REG_SET temps;
6732
6733 COPY_HARD_REG_SET (temps, *live_regs_mask);
6734 CLEAR_HARD_REG_BIT (temps, REGNO (reg));
6735 temp = scavenge_reg (&temps);
6736 }
6737 if (temp < 0)
6738 {
6739 rtx adj_reg, tmp_reg, mem;
6740
6741 /* If we reached here, the most likely case is the (sibcall)
6742 epilogue. Put a special push/pop sequence for such case as
6743 the last resort. This looks lengthy but would not be problem
6744 because it seems to be very rare. */
6745 gcc_assert (epilogue_p);
6746
6747 /* ??? There is still the slight possibility that r4 or
6748 r5 have been reserved as fixed registers or assigned
6749 as global registers, and they change during an
6750 interrupt. There are possible ways to handle this:
6751
6752 - If we are adjusting the frame pointer (r14), we can do
6753 with a single temp register and an ordinary push / pop
6754 on the stack.
6755 - Grab any call-used or call-saved registers (i.e. not
6756 fixed or globals) for the temps we need. We might
6757 also grab r14 if we are adjusting the stack pointer.
6758 If we can't find enough available registers, issue
6759 a diagnostic and die - the user must have reserved
6760 way too many registers.
6761 But since all this is rather unlikely to happen and
6762 would require extra testing, we just die if r4 / r5
6763 are not available. */
6764 gcc_assert (!fixed_regs[4] && !fixed_regs[5]
6765 && !global_regs[4] && !global_regs[5]);
6766
6767 adj_reg = gen_rtx_REG (GET_MODE (reg), 4);
6768 tmp_reg = gen_rtx_REG (GET_MODE (reg), 5);
6769 emit_move_insn (gen_tmp_stack_mem (Pmode, reg), adj_reg);
6770 emit_insn (GEN_MOV (adj_reg, GEN_INT (size)));
6771 emit_insn (GEN_ADD3 (adj_reg, adj_reg, reg));
6772 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
6773 emit_move_insn (mem, tmp_reg);
6774 emit_move_insn (tmp_reg, gen_tmp_stack_mem (Pmode, reg));
6775 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
6776 emit_move_insn (mem, tmp_reg);
6777 emit_move_insn (reg, adj_reg);
6778 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
6779 emit_move_insn (adj_reg, mem);
6780 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
6781 emit_move_insn (tmp_reg, mem);
6782 /* Tell flow the insns that pop r4/r5 aren't dead. */
6783 emit_use (tmp_reg);
6784 emit_use (adj_reg);
6785 return;
6786 }
6787 const_reg = gen_rtx_REG (GET_MODE (reg), temp);
6788
6789 /* If SIZE is negative, subtract the positive value.
6790 This sometimes allows a constant pool entry to be shared
6791 between prologue and epilogue code. */
6792 if (size < 0)
6793 {
6794 emit_insn (GEN_MOV (const_reg, GEN_INT (-size)));
6795 insn = emit_fn (GEN_SUB3 (reg, reg, const_reg));
6796 }
6797 else
6798 {
6799 emit_insn (GEN_MOV (const_reg, GEN_INT (size)));
6800 insn = emit_fn (GEN_ADD3 (reg, reg, const_reg));
6801 }
6802 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
6803 gen_rtx_SET (reg, gen_rtx_PLUS (SImode, reg,
6804 GEN_INT (size))));
6805 }
6806 }
6807 }
6808
6809 /* Emit the specified insn and mark it as frame related. */
6810 static rtx_insn *
emit_frame_insn(rtx x)6811 emit_frame_insn (rtx x)
6812 {
6813 rtx_insn *insn = emit_insn (x);
6814 RTX_FRAME_RELATED_P (insn) = 1;
6815 return insn;
6816 }
6817
6818 /* Output RTL to push register RN onto the stack. */
6819 static rtx
push(int rn)6820 push (int rn)
6821 {
6822 rtx x;
6823 if (rn == FPUL_REG)
6824 x = gen_push_fpul ();
6825 else if (rn == FPSCR_REG)
6826 x = gen_push_fpscr ();
6827 else if (TARGET_FPU_DOUBLE && TARGET_FMOVD
6828 && ! TARGET_FPU_SINGLE && FP_OR_XD_REGISTER_P (rn))
6829 {
6830 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
6831 return NULL_RTX;
6832 x = gen_push_4 (gen_rtx_REG (DFmode, rn));
6833 }
6834 else if (TARGET_SH2E && FP_REGISTER_P (rn))
6835 x = gen_push_e (gen_rtx_REG (SFmode, rn));
6836 else
6837 x = gen_push (gen_rtx_REG (SImode, rn));
6838
6839 x = emit_frame_insn (x);
6840 add_reg_note (x, REG_INC, gen_rtx_REG (SImode, STACK_POINTER_REGNUM));
6841 return x;
6842 }
6843
6844 /* Output RTL to pop register RN from the stack. */
6845 static void
pop(int rn)6846 pop (int rn)
6847 {
6848 rtx x, sp_reg, reg;
6849 if (rn == FPUL_REG)
6850 x = gen_pop_fpul ();
6851 else if (rn == FPSCR_REG)
6852 x = gen_pop_fpscr ();
6853 else if (TARGET_FPU_DOUBLE && TARGET_FMOVD
6854 && ! TARGET_FPU_SINGLE && FP_OR_XD_REGISTER_P (rn))
6855 {
6856 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
6857 return;
6858 x = gen_pop_4 (gen_rtx_REG (DFmode, rn));
6859 }
6860 else if (TARGET_SH2E && FP_REGISTER_P (rn))
6861 x = gen_pop_e (gen_rtx_REG (SFmode, rn));
6862 else
6863 x = gen_pop (gen_rtx_REG (SImode, rn));
6864
6865 x = emit_insn (x);
6866
6867 sp_reg = gen_rtx_REG (SImode, STACK_POINTER_REGNUM);
6868 reg = copy_rtx (GET_CODE (PATTERN (x)) == PARALLEL
6869 ? SET_DEST (XVECEXP (PATTERN (x), 0, 0))
6870 : SET_DEST (PATTERN (x)));
6871 add_reg_note (x, REG_CFA_RESTORE, reg);
6872 add_reg_note (x, REG_CFA_ADJUST_CFA,
6873 gen_rtx_SET (sp_reg,
6874 plus_constant (SImode, sp_reg,
6875 GET_MODE_SIZE (GET_MODE (reg)))));
6876 add_reg_note (x, REG_INC, gen_rtx_REG (SImode, STACK_POINTER_REGNUM));
6877 RTX_FRAME_RELATED_P (x) = 1;
6878 }
6879
6880 /* Generate code to push the regs specified in the mask. */
6881 static void
push_regs(HARD_REG_SET * mask,bool interrupt_handler)6882 push_regs (HARD_REG_SET *mask, bool interrupt_handler)
6883 {
6884 bool skip_fpscr = false;
6885
6886 /* Push PR last; this gives better latencies after the prologue, and
6887 candidates for the return delay slot when there are no general
6888 registers pushed. */
6889 for (int i = interrupt_handler ? LAST_BANKED_REG + 1 : 0;
6890 i < FIRST_PSEUDO_REGISTER; i++)
6891 {
6892 /* If this is an interrupt handler, and the SZ bit varies,
6893 and we have to push any floating point register, we need
6894 to switch to the correct precision first. */
6895 if (i == FIRST_FP_REG && interrupt_handler && TARGET_FMOVD
6896 && hard_reg_set_intersect_p (*mask, reg_class_contents[DF_REGS]))
6897 {
6898 HARD_REG_SET unsaved;
6899
6900 push (FPSCR_REG);
6901 COMPL_HARD_REG_SET (unsaved, *mask);
6902 fpscr_set_from_mem (NORMAL_MODE (FP_MODE), unsaved);
6903 skip_fpscr = true;
6904 }
6905 if (i != PR_REG
6906 && (i != FPSCR_REG || ! skip_fpscr)
6907 && TEST_HARD_REG_BIT (*mask, i))
6908 {
6909 /* If the ISR has RESBANK attribute assigned, don't push any of
6910 the following registers - R0-R14, MACH, MACL and GBR. */
6911 if (! (sh_cfun_resbank_handler_p ()
6912 && ((i >= FIRST_GENERAL_REG && i < LAST_GENERAL_REG)
6913 || i == MACH_REG
6914 || i == MACL_REG
6915 || i == GBR_REG)))
6916 push (i);
6917 }
6918 }
6919
6920 /* Push banked registers last to improve delay slot opportunities. */
6921 if (interrupt_handler)
6922 {
6923 bool use_movml = false;
6924
6925 if (TARGET_SH2A)
6926 {
6927 unsigned int count = 0;
6928
6929 for (int i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
6930 if (TEST_HARD_REG_BIT (*mask, i))
6931 count++;
6932 else
6933 break;
6934
6935 /* Use movml when all banked registers are pushed. */
6936 if (count == LAST_BANKED_REG - FIRST_BANKED_REG + 1)
6937 use_movml = true;
6938 }
6939
6940 if (sh_cfun_resbank_handler_p ())
6941 ; /* Do nothing. */
6942 else if (use_movml)
6943 {
6944 rtx x, mem, reg, set;
6945 rtx sp_reg = gen_rtx_REG (SImode, STACK_POINTER_REGNUM);
6946
6947 /* We must avoid scheduling multiple store insn with another
6948 insns. */
6949 emit_insn (gen_blockage ());
6950 x = gen_movml_push_banked (sp_reg);
6951 x = emit_frame_insn (x);
6952 for (int i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
6953 {
6954 mem = gen_rtx_MEM (SImode, plus_constant (Pmode, sp_reg, i * 4));
6955 reg = gen_rtx_REG (SImode, i);
6956 add_reg_note (x, REG_CFA_OFFSET, gen_rtx_SET (mem, reg));
6957 }
6958
6959 set = gen_rtx_SET (sp_reg, plus_constant (Pmode, sp_reg, - 32));
6960 add_reg_note (x, REG_CFA_ADJUST_CFA, set);
6961 emit_insn (gen_blockage ());
6962 }
6963 else
6964 for (int i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
6965 if (TEST_HARD_REG_BIT (*mask, i))
6966 push (i);
6967 }
6968
6969 /* Don't push PR register for an ISR with RESBANK attribute assigned. */
6970 if (TEST_HARD_REG_BIT (*mask, PR_REG) && !sh_cfun_resbank_handler_p ())
6971 push (PR_REG);
6972 }
6973
6974 /* Work out the registers which need to be saved, both as a mask and a
6975 count of saved words. Return the count.
6976
6977 If doing a pragma interrupt function, then push all regs used by the
6978 function, and if we call another function (we can tell by looking at PR),
6979 make sure that all the regs it clobbers are safe too. */
6980 static int
calc_live_regs(HARD_REG_SET * live_regs_mask)6981 calc_live_regs (HARD_REG_SET *live_regs_mask)
6982 {
6983 unsigned int reg;
6984 tree attrs;
6985 bool interrupt_or_trapa_handler, trapa_handler, interrupt_handler;
6986 bool nosave_low_regs;
6987
6988 attrs = DECL_ATTRIBUTES (current_function_decl);
6989 interrupt_or_trapa_handler = sh_cfun_interrupt_handler_p ();
6990 trapa_handler = lookup_attribute ("trapa_handler", attrs) != NULL_TREE;
6991 interrupt_handler = interrupt_or_trapa_handler && ! trapa_handler;
6992 nosave_low_regs = lookup_attribute ("nosave_low_regs", attrs) != NULL_TREE;
6993
6994 CLEAR_HARD_REG_SET (*live_regs_mask);
6995 if (TARGET_FPU_DOUBLE && TARGET_FMOVD && interrupt_handler
6996 && df_regs_ever_live_p (FPSCR_REG))
6997 target_flags &= ~MASK_FPU_SINGLE;
6998 /* If we can save a lot of saves by switching to double mode, do that. */
6999 else if (TARGET_FPU_DOUBLE && TARGET_FMOVD && TARGET_FPU_SINGLE)
7000 for (int count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2)
7001 if (df_regs_ever_live_p (reg) && df_regs_ever_live_p (reg+1)
7002 && (! call_really_used_regs[reg]
7003 || interrupt_handler)
7004 && ++count > 2)
7005 {
7006 target_flags &= ~MASK_FPU_SINGLE;
7007 break;
7008 }
7009
7010
7011 rtx pr_initial = has_hard_reg_initial_val (Pmode, PR_REG);
7012 bool pr_live = (pr_initial
7013 ? (!REG_P (pr_initial)
7014 || REGNO (pr_initial) != (PR_REG))
7015 : df_regs_ever_live_p (PR_REG));
7016 /* For Shcompact, if not optimizing, we end up with a memory reference
7017 using the return address pointer for __builtin_return_address even
7018 though there is no actual need to put the PR register on the stack. */
7019 pr_live |= df_regs_ever_live_p (RETURN_ADDRESS_POINTER_REGNUM);
7020
7021 /* Force PR to be live if the prologue has to call the SHmedia
7022 argument decoder or register saver. */
7023 bool has_call = pr_live;
7024
7025 int count;
7026 for (count = 0, reg = FIRST_PSEUDO_REGISTER; reg-- != 0; )
7027 {
7028 if (reg == PR_REG
7029 ? pr_live
7030 : interrupt_handler
7031 ? (/* Need to save all the regs ever live. */
7032 (df_regs_ever_live_p (reg)
7033 || (call_really_used_regs[reg]
7034 && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG
7035 || reg == PIC_OFFSET_TABLE_REGNUM)
7036 && has_call))
7037 && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
7038 && reg != RETURN_ADDRESS_POINTER_REGNUM
7039 && reg != T_REG && reg != GBR_REG
7040 && reg != FPSCR_MODES_REG && reg != FPSCR_STAT_REG
7041 /* Push fpscr only on targets which have FPU */
7042 && (reg != FPSCR_REG || TARGET_FPU_ANY))
7043 : (/* Only push those regs which are used and need to be saved. */
7044 (false)
7045 || (df_regs_ever_live_p (reg)
7046 && ((!call_really_used_regs[reg]
7047 && !(reg != PIC_OFFSET_TABLE_REGNUM
7048 && fixed_regs[reg] && call_used_regs[reg]))
7049 || (trapa_handler && reg == FPSCR_REG && TARGET_FPU_ANY)))
7050 || (crtl->calls_eh_return
7051 && (reg == EH_RETURN_DATA_REGNO (0)
7052 || reg == EH_RETURN_DATA_REGNO (1)
7053 || reg == EH_RETURN_DATA_REGNO (2)
7054 || reg == EH_RETURN_DATA_REGNO (3)))
7055 || ((reg == MACL_REG || reg == MACH_REG)
7056 && df_regs_ever_live_p (reg)
7057 && sh_cfun_attr_renesas_p ())
7058 ))
7059 {
7060 SET_HARD_REG_BIT (*live_regs_mask, reg);
7061 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
7062
7063 if (TARGET_FPU_DOUBLE && TARGET_FMOVD
7064 && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg)) == MODE_FLOAT)
7065 {
7066 if (FP_REGISTER_P (reg))
7067 {
7068 if (! TARGET_FPU_SINGLE && ! df_regs_ever_live_p (reg ^ 1))
7069 {
7070 SET_HARD_REG_BIT (*live_regs_mask, (reg ^ 1));
7071 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg ^ 1));
7072 }
7073 }
7074 else if (XD_REGISTER_P (reg))
7075 {
7076 /* Must switch to double mode to access these registers. */
7077 target_flags &= ~MASK_FPU_SINGLE;
7078 }
7079 }
7080 }
7081 if (nosave_low_regs && reg == R8_REG)
7082 break;
7083 }
7084
7085 return count;
7086 }
7087
7088 /* Code to generate prologue and epilogue sequences */
7089
7090 /* PUSHED is the number of bytes that are being pushed on the
7091 stack for register saves. Return the frame size, padded
7092 appropriately so that the stack stays properly aligned. */
7093 static HOST_WIDE_INT
rounded_frame_size(int pushed)7094 rounded_frame_size (int pushed)
7095 {
7096 HOST_WIDE_INT size = get_frame_size ();
7097 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
7098
7099 if (ACCUMULATE_OUTGOING_ARGS)
7100 size += crtl->outgoing_args_size;
7101
7102 return ((size + pushed + align - 1) & -align) - pushed;
7103 }
7104
7105 /* Expand code for the function prologue. */
7106 void
sh_expand_prologue(void)7107 sh_expand_prologue (void)
7108 {
7109 int save_flags = target_flags;
7110 tree sp_switch_attr
7111 = lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl));
7112
7113 current_function_interrupt = sh_cfun_interrupt_handler_p ();
7114
7115 /* We have pretend args if we had an object sent partially in registers
7116 and partially on the stack, e.g. a large structure. */
7117 int pretend_args = crtl->args.pretend_args_size;
7118 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl)
7119 && (NPARM_REGS(SImode)
7120 > crtl->args.info.arg_count[(int) SH_ARG_INT]))
7121 pretend_args = 0;
7122
7123 output_stack_adjust (-pretend_args, stack_pointer_rtx, 0, NULL, true);
7124 int stack_usage = pretend_args;
7125
7126 /* Emit the code for SETUP_VARARGS. */
7127 if (cfun->stdarg)
7128 {
7129 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
7130 {
7131 /* Push arg regs as if they'd been provided by caller in stack. */
7132 for (int i = 0; i < NPARM_REGS(SImode); i++)
7133 {
7134 int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1;
7135
7136 if (i >= (NPARM_REGS(SImode)
7137 - crtl->args.info.arg_count[(int) SH_ARG_INT]
7138 ))
7139 break;
7140 push (rn);
7141 stack_usage += GET_MODE_SIZE (SImode);
7142 }
7143 }
7144 }
7145
7146 /* If we're supposed to switch stacks at function entry, do so now. */
7147 if (sp_switch_attr)
7148 {
7149 rtx lab, newsrc;
7150 /* The argument specifies a variable holding the address of the
7151 stack the interrupt function should switch to/from at entry/exit. */
7152 tree arg = TREE_VALUE ( TREE_VALUE (sp_switch_attr));
7153 const char* s = ggc_strdup (TREE_STRING_POINTER (arg));
7154 rtx sp_switch = gen_rtx_SYMBOL_REF (Pmode, s);
7155
7156 lab = add_constant (sp_switch, SImode, 0);
7157 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
7158
7159 emit_insn (gen_sp_switch_1 (newsrc));
7160 }
7161
7162 HARD_REG_SET live_regs_mask;
7163 int d = calc_live_regs (&live_regs_mask);
7164 /* ??? Maybe we could save some switching if we can move a mode switch
7165 that already happens to be at the function start into the prologue. */
7166 if (target_flags != save_flags && ! current_function_interrupt)
7167 emit_insn (gen_toggle_sz ());
7168
7169 push_regs (&live_regs_mask, current_function_interrupt);
7170 stack_usage += d;
7171
7172 if (flag_pic && !TARGET_FDPIC
7173 && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
7174 emit_insn (gen_GOTaddr2picreg (const0_rtx));
7175
7176 if (target_flags != save_flags && ! current_function_interrupt)
7177 emit_insn (gen_toggle_sz ());
7178
7179 target_flags = save_flags;
7180
7181 output_stack_adjust (-rounded_frame_size (d),
7182 stack_pointer_rtx, 0, NULL, true);
7183 stack_usage += rounded_frame_size (d);
7184
7185 if (frame_pointer_needed)
7186 emit_frame_insn (GEN_MOV (hard_frame_pointer_rtx, stack_pointer_rtx));
7187
7188 /* If we are profiling, make sure no instructions are scheduled before
7189 the call to mcount. Similarly if some call instructions are swapped
7190 before frame related insns, it'll confuse the unwinder because
7191 currently SH has no unwind info for function epilogues. */
7192 if (crtl->profile || flag_exceptions || flag_unwind_tables)
7193 emit_insn (gen_blockage ());
7194
7195 if (flag_stack_usage_info)
7196 current_function_static_stack_size = stack_usage;
7197 }
7198
7199 /* Expand code for the function epilogue. */
7200 void
sh_expand_epilogue(bool sibcall_p)7201 sh_expand_epilogue (bool sibcall_p)
7202 {
7203 int save_flags = target_flags;
7204 bool fpscr_deferred = false;
7205 int e = sibcall_p ? -1 : 1;
7206
7207 HARD_REG_SET live_regs_mask;
7208 int d = calc_live_regs (&live_regs_mask);
7209
7210 int save_size = d;
7211 int frame_size = rounded_frame_size (d);
7212
7213 if (frame_pointer_needed)
7214 {
7215 /* We must avoid scheduling the epilogue with previous basic blocks.
7216 See PR/18032 and PR/40313. */
7217 emit_insn (gen_blockage ());
7218 output_stack_adjust (frame_size, hard_frame_pointer_rtx, e,
7219 &live_regs_mask, true);
7220
7221 /* We must avoid moving the stack pointer adjustment past code
7222 which reads from the local frame, else an interrupt could
7223 occur after the SP adjustment and clobber data in the local
7224 frame. */
7225 emit_insn (gen_blockage ());
7226 emit_frame_insn (GEN_MOV (stack_pointer_rtx, hard_frame_pointer_rtx));
7227 }
7228 else if (frame_size)
7229 {
7230 /* We must avoid moving the stack pointer adjustment past code
7231 which reads from the local frame, else an interrupt could
7232 occur after the SP adjustment and clobber data in the local
7233 frame. */
7234 emit_insn (gen_blockage ());
7235 output_stack_adjust (frame_size, stack_pointer_rtx, e,
7236 &live_regs_mask, true);
7237 }
7238
7239 /* Pop all the registers. */
7240
7241 if (target_flags != save_flags && ! current_function_interrupt)
7242 emit_insn (gen_toggle_sz ());
7243
7244 {
7245 int last_reg;
7246
7247 save_size = 0;
7248 /* For an ISR with RESBANK attribute assigned, don't pop PR
7249 register. */
7250 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG)
7251 && !sh_cfun_resbank_handler_p ())
7252 {
7253 if (!frame_pointer_needed)
7254 emit_insn (gen_blockage ());
7255 pop (PR_REG);
7256 }
7257
7258 /* Banked registers are popped first to avoid being scheduled in the
7259 delay slot. RTE switches banks before the ds instruction. */
7260 if (current_function_interrupt)
7261 {
7262 bool use_movml = false;
7263
7264 if (TARGET_SH2A)
7265 {
7266 unsigned int count = 0;
7267
7268 for (int i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
7269 if (TEST_HARD_REG_BIT (live_regs_mask, i))
7270 count++;
7271 else
7272 break;
7273
7274 /* Use movml when all banked register are poped. */
7275 if (count == LAST_BANKED_REG - FIRST_BANKED_REG + 1)
7276 use_movml = true;
7277 }
7278
7279 if (sh_cfun_resbank_handler_p ())
7280 ; /* Do nothing. */
7281 else if (use_movml)
7282 {
7283 rtx sp_reg = gen_rtx_REG (SImode, STACK_POINTER_REGNUM);
7284
7285 /* We must avoid scheduling multiple load insn with another
7286 insns. */
7287 emit_insn (gen_blockage ());
7288 emit_insn (gen_movml_pop_banked (sp_reg));
7289 emit_insn (gen_blockage ());
7290 }
7291 else
7292 for (int i = LAST_BANKED_REG; i >= FIRST_BANKED_REG; i--)
7293 if (TEST_HARD_REG_BIT (live_regs_mask, i))
7294 pop (i);
7295
7296 last_reg = FIRST_PSEUDO_REGISTER - LAST_BANKED_REG - 1;
7297 }
7298 else
7299 last_reg = FIRST_PSEUDO_REGISTER;
7300
7301 for (int i = 0; i < last_reg; i++)
7302 {
7303 int j = (FIRST_PSEUDO_REGISTER - 1) - i;
7304
7305 if (j == FPSCR_REG && current_function_interrupt && TARGET_FMOVD
7306 && hard_reg_set_intersect_p (live_regs_mask,
7307 reg_class_contents[DF_REGS]))
7308 fpscr_deferred = true;
7309 /* For an ISR with RESBANK attribute assigned, don't pop
7310 following registers, R0-R14, MACH, MACL and GBR. */
7311 else if (j != PR_REG && TEST_HARD_REG_BIT (live_regs_mask, j)
7312 && ! (sh_cfun_resbank_handler_p ()
7313 && ((j >= FIRST_GENERAL_REG
7314 && j < LAST_GENERAL_REG)
7315 || j == MACH_REG
7316 || j == MACL_REG
7317 || j == GBR_REG)))
7318 pop (j);
7319
7320 if (j == FIRST_FP_REG && fpscr_deferred)
7321 pop (FPSCR_REG);
7322 }
7323 }
7324 if (target_flags != save_flags && ! current_function_interrupt)
7325 emit_insn (gen_toggle_sz ());
7326 target_flags = save_flags;
7327
7328 output_stack_adjust (crtl->args.pretend_args_size + save_size,
7329 stack_pointer_rtx, e, NULL, true);
7330
7331 if (crtl->calls_eh_return)
7332 emit_insn (GEN_ADD3 (stack_pointer_rtx, stack_pointer_rtx,
7333 EH_RETURN_STACKADJ_RTX));
7334
7335 /* Switch back to the normal stack if necessary. */
7336 if (lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl)))
7337 emit_insn (gen_sp_switch_2 ());
7338
7339 /* Tell flow the insn that pops PR isn't dead. */
7340 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG))
7341 emit_use (gen_rtx_REG (SImode, PR_REG));
7342 }
7343
7344 /* Emit code to change the current function's return address to RA.
7345 TEMP is available as a scratch register, if needed. */
7346 void
sh_set_return_address(rtx ra,rtx tmp)7347 sh_set_return_address (rtx ra, rtx tmp)
7348 {
7349 HARD_REG_SET live_regs_mask;
7350 int d = calc_live_regs (&live_regs_mask);
7351
7352 /* If pr_reg isn't life, we can set it directly. */
7353 if (! TEST_HARD_REG_BIT (live_regs_mask, PR_REG))
7354 {
7355 rtx rr = gen_rtx_REG (SImode, PR_REG);
7356 emit_insn (GEN_MOV (rr, ra));
7357 /* Tell flow the register for return isn't dead. */
7358 emit_use (rr);
7359 return;
7360 }
7361
7362 int pr_offset = rounded_frame_size (d);
7363
7364 emit_insn (GEN_MOV (tmp, GEN_INT (pr_offset)));
7365
7366 if (frame_pointer_needed)
7367 emit_insn (GEN_ADD3 (tmp, tmp, hard_frame_pointer_rtx));
7368 else
7369 emit_insn (GEN_ADD3 (tmp, tmp, stack_pointer_rtx));
7370
7371 tmp = gen_frame_mem (Pmode, tmp);
7372 emit_insn (GEN_MOV (tmp, ra));
7373 /* Tell this store isn't dead. */
7374 emit_use (tmp);
7375 }
7376
7377 /* Clear variables at function end. */
7378 static void
sh_output_function_epilogue(FILE *)7379 sh_output_function_epilogue (FILE *)
7380 {
7381 }
7382
7383 static rtx
sh_builtin_saveregs(void)7384 sh_builtin_saveregs (void)
7385 {
7386 /* First unnamed integer register. */
7387 int first_intreg = crtl->args.info.arg_count[(int) SH_ARG_INT];
7388 /* Number of integer registers we need to save. */
7389 int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg);
7390 /* First unnamed SFmode float reg */
7391 int first_floatreg = crtl->args.info.arg_count[(int) SH_ARG_FLOAT];
7392 /* Number of SFmode float regs to save. */
7393 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
7394 rtx regbuf, fpregs;
7395 int bufsize, regno;
7396 alias_set_type alias_set;
7397
7398 if (!TARGET_FPU_ANY)
7399 {
7400 error ("__builtin_saveregs not supported by this subtarget");
7401 return const0_rtx;
7402 }
7403
7404 /* Allocate block of memory for the regs. */
7405 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
7406 Or can assign_stack_local accept a 0 SIZE argument? */
7407 bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD);
7408
7409 if (n_floatregs & 1)
7410 {
7411 rtx addr;
7412
7413 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
7414 addr = copy_to_mode_reg (Pmode, XEXP (regbuf, 0));
7415 emit_insn (gen_iorsi3 (addr, addr, GEN_INT (UNITS_PER_WORD)));
7416 regbuf = change_address (regbuf, BLKmode, addr);
7417 }
7418 else if (STACK_BOUNDARY < 64 && TARGET_FPU_DOUBLE && n_floatregs)
7419 {
7420 rtx addr, mask;
7421
7422 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
7423 addr = copy_to_mode_reg (Pmode, plus_constant (Pmode,
7424 XEXP (regbuf, 0), 4));
7425 mask = copy_to_mode_reg (Pmode, GEN_INT (-8));
7426 emit_insn (gen_andsi3 (addr, addr, mask));
7427 regbuf = change_address (regbuf, BLKmode, addr);
7428 }
7429 else
7430 regbuf = assign_stack_local (BLKmode, bufsize, TARGET_FPU_DOUBLE ? 64 : 0);
7431 alias_set = get_varargs_alias_set ();
7432 set_mem_alias_set (regbuf, alias_set);
7433
7434 /* Save int args.
7435 This is optimized to only save the regs that are necessary. Explicitly
7436 named args need not be saved. */
7437 if (n_intregs > 0)
7438 move_block_from_reg (BASE_ARG_REG (SImode) + first_intreg,
7439 adjust_address (regbuf, BLKmode,
7440 n_floatregs * UNITS_PER_WORD),
7441 n_intregs);
7442
7443 /* Save float args.
7444 This is optimized to only save the regs that are necessary. Explicitly
7445 named args need not be saved.
7446 We explicitly build a pointer to the buffer because it halves the insn
7447 count when not optimizing (otherwise the pointer is built for each reg
7448 saved).
7449 We emit the moves in reverse order so that we can use predecrement. */
7450
7451 fpregs = copy_to_mode_reg (Pmode,
7452 plus_constant (Pmode, XEXP (regbuf, 0),
7453 n_floatregs * UNITS_PER_WORD));
7454 if (TARGET_FPU_DOUBLE)
7455 {
7456 rtx mem;
7457 for (regno = NPARM_REGS (DFmode) - 2; regno >= first_floatreg; regno -= 2)
7458 {
7459 emit_insn (gen_addsi3 (fpregs, fpregs,
7460 GEN_INT (-2 * UNITS_PER_WORD)));
7461 mem = change_address (regbuf, DFmode, fpregs);
7462 emit_move_insn (mem,
7463 gen_rtx_REG (DFmode, BASE_ARG_REG (DFmode) + regno));
7464 }
7465 regno = first_floatreg;
7466 if (regno & 1)
7467 {
7468 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
7469 mem = change_address (regbuf, SFmode, fpregs);
7470 emit_move_insn (mem,
7471 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode)
7472 + regno - SH_REG_MSW_OFFSET));
7473 }
7474 }
7475 else
7476 for (regno = NPARM_REGS (SFmode) - 1; regno >= first_floatreg; regno--)
7477 {
7478 rtx mem;
7479
7480 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
7481 mem = change_address (regbuf, SFmode, fpregs);
7482 emit_move_insn (mem,
7483 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno));
7484 }
7485
7486 /* Return the address of the regbuf. */
7487 return XEXP (regbuf, 0);
7488 }
7489
7490 /* Define the `__builtin_va_list' type for the ABI. */
7491 static tree
sh_build_builtin_va_list(void)7492 sh_build_builtin_va_list (void)
7493 {
7494 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7495 tree record, type_decl;
7496
7497 if ((! TARGET_SH2E && ! TARGET_SH4)
7498 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
7499 return ptr_type_node;
7500
7501 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
7502 type_decl = build_decl (BUILTINS_LOCATION,
7503 TYPE_DECL, get_identifier ("__va_list_tag"), record);
7504
7505 f_next_o = build_decl (BUILTINS_LOCATION,
7506 FIELD_DECL, get_identifier ("__va_next_o"),
7507 ptr_type_node);
7508 f_next_o_limit = build_decl (BUILTINS_LOCATION,
7509 FIELD_DECL,
7510 get_identifier ("__va_next_o_limit"),
7511 ptr_type_node);
7512 f_next_fp = build_decl (BUILTINS_LOCATION,
7513 FIELD_DECL, get_identifier ("__va_next_fp"),
7514 ptr_type_node);
7515 f_next_fp_limit = build_decl (BUILTINS_LOCATION,
7516 FIELD_DECL,
7517 get_identifier ("__va_next_fp_limit"),
7518 ptr_type_node);
7519 f_next_stack = build_decl (BUILTINS_LOCATION,
7520 FIELD_DECL, get_identifier ("__va_next_stack"),
7521 ptr_type_node);
7522
7523 DECL_FIELD_CONTEXT (f_next_o) = record;
7524 DECL_FIELD_CONTEXT (f_next_o_limit) = record;
7525 DECL_FIELD_CONTEXT (f_next_fp) = record;
7526 DECL_FIELD_CONTEXT (f_next_fp_limit) = record;
7527 DECL_FIELD_CONTEXT (f_next_stack) = record;
7528
7529 TYPE_STUB_DECL (record) = type_decl;
7530 TYPE_NAME (record) = type_decl;
7531 TYPE_FIELDS (record) = f_next_o;
7532 DECL_CHAIN (f_next_o) = f_next_o_limit;
7533 DECL_CHAIN (f_next_o_limit) = f_next_fp;
7534 DECL_CHAIN (f_next_fp) = f_next_fp_limit;
7535 DECL_CHAIN (f_next_fp_limit) = f_next_stack;
7536
7537 layout_type (record);
7538
7539 return record;
7540 }
7541
7542 /* Implement `va_start' for varargs and stdarg. */
7543 static void
sh_va_start(tree valist,rtx nextarg)7544 sh_va_start (tree valist, rtx nextarg)
7545 {
7546 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7547 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7548 tree t, u;
7549 int nfp, nint;
7550
7551 if ((! TARGET_SH2E && ! TARGET_SH4)
7552 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
7553 {
7554 std_expand_builtin_va_start (valist, nextarg);
7555 return;
7556 }
7557
7558 f_next_o = TYPE_FIELDS (va_list_type_node);
7559 f_next_o_limit = DECL_CHAIN (f_next_o);
7560 f_next_fp = DECL_CHAIN (f_next_o_limit);
7561 f_next_fp_limit = DECL_CHAIN (f_next_fp);
7562 f_next_stack = DECL_CHAIN (f_next_fp_limit);
7563
7564 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
7565 NULL_TREE);
7566 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7567 valist, f_next_o_limit, NULL_TREE);
7568 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp), valist, f_next_fp,
7569 NULL_TREE);
7570 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7571 valist, f_next_fp_limit, NULL_TREE);
7572 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7573 valist, f_next_stack, NULL_TREE);
7574
7575 /* Call __builtin_saveregs. */
7576 u = make_tree (sizetype, expand_builtin_saveregs ());
7577 u = fold_convert (ptr_type_node, u);
7578 t = build2 (MODIFY_EXPR, ptr_type_node, next_fp, u);
7579 TREE_SIDE_EFFECTS (t) = 1;
7580 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7581
7582 nfp = crtl->args.info.arg_count[SH_ARG_FLOAT];
7583 if (nfp < 8)
7584 nfp = 8 - nfp;
7585 else
7586 nfp = 0;
7587 u = fold_build_pointer_plus_hwi (u, UNITS_PER_WORD * nfp);
7588 t = build2 (MODIFY_EXPR, ptr_type_node, next_fp_limit, u);
7589 TREE_SIDE_EFFECTS (t) = 1;
7590 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7591
7592 t = build2 (MODIFY_EXPR, ptr_type_node, next_o, u);
7593 TREE_SIDE_EFFECTS (t) = 1;
7594 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7595
7596 nint = crtl->args.info.arg_count[SH_ARG_INT];
7597 if (nint < 4)
7598 nint = 4 - nint;
7599 else
7600 nint = 0;
7601 u = fold_build_pointer_plus_hwi (u, UNITS_PER_WORD * nint);
7602 t = build2 (MODIFY_EXPR, ptr_type_node, next_o_limit, u);
7603 TREE_SIDE_EFFECTS (t) = 1;
7604 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7605
7606 u = make_tree (ptr_type_node, nextarg);
7607 t = build2 (MODIFY_EXPR, ptr_type_node, next_stack, u);
7608 TREE_SIDE_EFFECTS (t) = 1;
7609 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7610 }
7611
7612 /* TYPE is a RECORD_TYPE. If there is only a single nonzero-sized
7613 member, return it. */
7614 static tree
find_sole_member(tree type)7615 find_sole_member (tree type)
7616 {
7617 tree field, member = NULL_TREE;
7618
7619 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
7620 {
7621 if (TREE_CODE (field) != FIELD_DECL)
7622 continue;
7623 if (!DECL_SIZE (field))
7624 return NULL_TREE;
7625 if (integer_zerop (DECL_SIZE (field)))
7626 continue;
7627 if (member)
7628 return NULL_TREE;
7629 member = field;
7630 }
7631 return member;
7632 }
7633
7634 /* Implement `va_arg'. */
7635 static tree
sh_gimplify_va_arg_expr(tree valist,tree type,gimple_seq * pre_p,gimple_seq * post_p ATTRIBUTE_UNUSED)7636 sh_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
7637 gimple_seq *post_p ATTRIBUTE_UNUSED)
7638 {
7639 tree tmp;
7640 tree addr, lab_over = NULL, result = NULL;
7641 tree eff_type;
7642
7643 const bool pass_by_ref =
7644 !VOID_TYPE_P (type)
7645 && targetm.calls.must_pass_in_stack (TYPE_MODE (type), type);
7646
7647 if (pass_by_ref)
7648 type = build_pointer_type (type);
7649
7650 HOST_WIDE_INT size = int_size_in_bytes (type);
7651 HOST_WIDE_INT rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
7652 tree pptr_type_node = build_pointer_type (ptr_type_node);
7653
7654 if ((TARGET_SH2E || TARGET_SH4)
7655 && ! (TARGET_HITACHI || sh_cfun_attr_renesas_p ()))
7656 {
7657 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7658 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7659 tree lab_false;
7660 tree member;
7661
7662 f_next_o = TYPE_FIELDS (va_list_type_node);
7663 f_next_o_limit = DECL_CHAIN (f_next_o);
7664 f_next_fp = DECL_CHAIN (f_next_o_limit);
7665 f_next_fp_limit = DECL_CHAIN (f_next_fp);
7666 f_next_stack = DECL_CHAIN (f_next_fp_limit);
7667
7668 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
7669 NULL_TREE);
7670 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7671 valist, f_next_o_limit, NULL_TREE);
7672 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp),
7673 valist, f_next_fp, NULL_TREE);
7674 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7675 valist, f_next_fp_limit, NULL_TREE);
7676 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7677 valist, f_next_stack, NULL_TREE);
7678
7679 /* Structures with a single member with a distinct mode are passed
7680 like their member. This is relevant if the latter has a REAL_TYPE
7681 or COMPLEX_TYPE type. */
7682 eff_type = type;
7683 while (TREE_CODE (eff_type) == RECORD_TYPE
7684 && (member = find_sole_member (eff_type))
7685 && (TREE_CODE (TREE_TYPE (member)) == REAL_TYPE
7686 || TREE_CODE (TREE_TYPE (member)) == COMPLEX_TYPE
7687 || TREE_CODE (TREE_TYPE (member)) == RECORD_TYPE))
7688 {
7689 tree field_type = TREE_TYPE (member);
7690
7691 if (TYPE_MODE (eff_type) == TYPE_MODE (field_type))
7692 eff_type = field_type;
7693 else
7694 {
7695 gcc_assert ((TYPE_ALIGN (eff_type)
7696 < GET_MODE_ALIGNMENT (TYPE_MODE (field_type)))
7697 || (TYPE_ALIGN (eff_type)
7698 > GET_MODE_BITSIZE (TYPE_MODE (field_type))));
7699 break;
7700 }
7701 }
7702
7703 bool pass_as_float;
7704 if (TARGET_FPU_DOUBLE)
7705 {
7706 pass_as_float = ((TREE_CODE (eff_type) == REAL_TYPE && size <= 8)
7707 || (TREE_CODE (eff_type) == COMPLEX_TYPE
7708 && TREE_CODE (TREE_TYPE (eff_type)) == REAL_TYPE
7709 && size <= 16));
7710 }
7711 else
7712 {
7713 pass_as_float = (TREE_CODE (eff_type) == REAL_TYPE && size == 4);
7714 }
7715
7716 addr = create_tmp_var (pptr_type_node);
7717 lab_false = create_artificial_label (UNKNOWN_LOCATION);
7718 lab_over = create_artificial_label (UNKNOWN_LOCATION);
7719
7720 valist = build_simple_mem_ref (addr);
7721
7722 if (pass_as_float)
7723 {
7724 tree next_fp_tmp = create_tmp_var (TREE_TYPE (f_next_fp));
7725 tree cmp;
7726 bool is_double = size == 8 && TREE_CODE (eff_type) == REAL_TYPE;
7727
7728 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_fp));
7729 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7730
7731 gimplify_assign (unshare_expr (next_fp_tmp), valist, pre_p);
7732 tmp = next_fp_limit;
7733 if (size > 4 && !is_double)
7734 tmp = fold_build_pointer_plus_hwi (unshare_expr (tmp), 4 - size);
7735 tmp = build2 (GE_EXPR, boolean_type_node,
7736 unshare_expr (next_fp_tmp), unshare_expr (tmp));
7737 cmp = build3 (COND_EXPR, void_type_node, tmp,
7738 build1 (GOTO_EXPR, void_type_node,
7739 unshare_expr (lab_false)), NULL_TREE);
7740 if (!is_double)
7741 gimplify_and_add (cmp, pre_p);
7742
7743 if (TYPE_ALIGN (eff_type) > BITS_PER_WORD
7744 || (is_double || size == 16))
7745 {
7746 tmp = fold_convert (sizetype, next_fp_tmp);
7747 tmp = build2 (BIT_AND_EXPR, sizetype, tmp,
7748 size_int (UNITS_PER_WORD));
7749 tmp = fold_build_pointer_plus (unshare_expr (next_fp_tmp), tmp);
7750 gimplify_assign (unshare_expr (next_fp_tmp), tmp, pre_p);
7751 }
7752 if (is_double)
7753 gimplify_and_add (cmp, pre_p);
7754
7755 #ifdef FUNCTION_ARG_SCmode_WART
7756 if (TYPE_MODE (eff_type) == SCmode
7757 && TARGET_SH4 && TARGET_LITTLE_ENDIAN)
7758 {
7759 tree subtype = TREE_TYPE (eff_type);
7760 tree real, imag;
7761
7762 imag
7763 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
7764 imag = get_initialized_tmp_var (imag, pre_p, NULL);
7765
7766 real
7767 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
7768 real = get_initialized_tmp_var (real, pre_p, NULL);
7769
7770 result = build2 (COMPLEX_EXPR, eff_type, real, imag);
7771 if (type != eff_type)
7772 result = build1 (VIEW_CONVERT_EXPR, type, result);
7773 result = get_initialized_tmp_var (result, pre_p, NULL);
7774 }
7775 #endif /* FUNCTION_ARG_SCmode_WART */
7776
7777 tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over));
7778 gimplify_and_add (tmp, pre_p);
7779
7780 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false));
7781 gimplify_and_add (tmp, pre_p);
7782
7783 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack));
7784 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7785 gimplify_assign (unshare_expr (next_fp_tmp),
7786 unshare_expr (valist), pre_p);
7787
7788 gimplify_assign (unshare_expr (valist),
7789 unshare_expr (next_fp_tmp), post_p);
7790 valist = next_fp_tmp;
7791 }
7792 else
7793 {
7794 tmp = fold_build_pointer_plus_hwi (unshare_expr (next_o), rsize);
7795 tmp = build2 (GT_EXPR, boolean_type_node, tmp,
7796 unshare_expr (next_o_limit));
7797 tmp = build3 (COND_EXPR, void_type_node, tmp,
7798 build1 (GOTO_EXPR, void_type_node,
7799 unshare_expr (lab_false)),
7800 NULL_TREE);
7801 gimplify_and_add (tmp, pre_p);
7802
7803 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_o));
7804 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7805
7806 tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over));
7807 gimplify_and_add (tmp, pre_p);
7808
7809 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false));
7810 gimplify_and_add (tmp, pre_p);
7811
7812 if (size > 4 && ! (TARGET_SH4 || TARGET_SH2A))
7813 gimplify_assign (unshare_expr (next_o),
7814 unshare_expr (next_o_limit), pre_p);
7815
7816 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack));
7817 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7818 }
7819
7820 if (!result)
7821 {
7822 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over));
7823 gimplify_and_add (tmp, pre_p);
7824 }
7825 }
7826
7827 /* ??? In va-sh.h, there had been code to make values larger than
7828 size 8 indirect. This does not match the FUNCTION_ARG macros. */
7829
7830 tmp = std_gimplify_va_arg_expr (valist, type, pre_p, NULL);
7831 if (result)
7832 {
7833 gimplify_assign (result, tmp, pre_p);
7834 result = build1 (NOP_EXPR, TREE_TYPE (result), result);
7835 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over));
7836 gimplify_and_add (tmp, pre_p);
7837 }
7838 else
7839 result = tmp;
7840
7841 if (pass_by_ref)
7842 result = build_va_arg_indirect_ref (result);
7843
7844 return result;
7845 }
7846
7847 /* 64 bit floating points memory transfers are paired single precision loads
7848 or store. So DWARF information needs fixing in little endian (unless
7849 PR=SZ=1 in FPSCR). */
7850 rtx
sh_dwarf_register_span(rtx reg)7851 sh_dwarf_register_span (rtx reg)
7852 {
7853 unsigned regno = REGNO (reg);
7854
7855 if (WORDS_BIG_ENDIAN || GET_MODE (reg) != DFmode)
7856 return NULL_RTX;
7857
7858 return
7859 gen_rtx_PARALLEL (VOIDmode,
7860 gen_rtvec (2,
7861 gen_rtx_REG (SFmode, regno + 1),
7862 gen_rtx_REG (SFmode, regno)));
7863 }
7864
7865 static machine_mode
sh_promote_function_mode(const_tree type,machine_mode mode,int * punsignedp,const_tree funtype,int for_return)7866 sh_promote_function_mode (const_tree type, machine_mode mode,
7867 int *punsignedp, const_tree funtype,
7868 int for_return)
7869 {
7870 if (sh_promote_prototypes (funtype))
7871 return promote_mode (type, mode, punsignedp);
7872 else
7873 return default_promote_function_mode (type, mode, punsignedp, funtype,
7874 for_return);
7875 }
7876
7877 static bool
sh_promote_prototypes(const_tree type)7878 sh_promote_prototypes (const_tree type)
7879 {
7880 if (TARGET_HITACHI)
7881 return false;
7882 if (! type)
7883 return true;
7884 return ! sh_attr_renesas_p (type);
7885 }
7886
7887 static bool
sh_pass_by_reference(cumulative_args_t cum_v,machine_mode mode,const_tree type,bool named ATTRIBUTE_UNUSED)7888 sh_pass_by_reference (cumulative_args_t cum_v, machine_mode mode,
7889 const_tree type, bool named ATTRIBUTE_UNUSED)
7890 {
7891 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
7892
7893 if (targetm.calls.must_pass_in_stack (mode, type))
7894 return true;
7895
7896 /* ??? std_gimplify_va_arg_expr passes NULL for cum. That function
7897 wants to know about pass-by-reference semantics for incoming
7898 arguments. */
7899 if (! cum)
7900 return false;
7901
7902 return false;
7903 }
7904
7905 static bool
sh_callee_copies(cumulative_args_t cum,machine_mode mode,const_tree type,bool named ATTRIBUTE_UNUSED)7906 sh_callee_copies (cumulative_args_t cum, machine_mode mode,
7907 const_tree type, bool named ATTRIBUTE_UNUSED)
7908 {
7909 /* ??? How can it possibly be correct to return true only on the
7910 caller side of the equation? Is there someplace else in the
7911 sh backend that's magically producing the copies? */
7912 return (get_cumulative_args (cum)->outgoing
7913 && ((mode == BLKmode ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode))
7914 % SH_MIN_ALIGN_FOR_CALLEE_COPY == 0));
7915 }
7916
7917 static sh_arg_class
get_sh_arg_class(machine_mode mode)7918 get_sh_arg_class (machine_mode mode)
7919 {
7920 if (TARGET_FPU_ANY && mode == SFmode)
7921 return SH_ARG_FLOAT;
7922
7923 if (TARGET_FPU_DOUBLE
7924 && (GET_MODE_CLASS (mode) == MODE_FLOAT
7925 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT))
7926 return SH_ARG_FLOAT;
7927
7928 return SH_ARG_INT;
7929 }
7930
7931 /* Round a register number up to a proper boundary for an arg of mode
7932 MODE.
7933 The SH doesn't care about double alignment, so we only
7934 round doubles to even regs when asked to explicitly. */
7935 static int
sh_round_reg(const CUMULATIVE_ARGS & cum,machine_mode mode)7936 sh_round_reg (const CUMULATIVE_ARGS& cum, machine_mode mode)
7937 {
7938 /* FIXME: This used to be a macro and has been copy pasted into this
7939 function as is. Make this more readable. */
7940 return
7941 (((TARGET_ALIGN_DOUBLE
7942 || (TARGET_FPU_DOUBLE
7943 && (mode == DFmode || mode == DCmode)
7944 && cum.arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (mode)))
7945 && GET_MODE_UNIT_SIZE (mode) > UNITS_PER_WORD)
7946 ? (cum.arg_count[(int) get_sh_arg_class (mode)]
7947 + (cum.arg_count[(int) get_sh_arg_class (mode)] & 1))
7948 : cum.arg_count[(int) get_sh_arg_class (mode)]);
7949 }
7950
7951 /* Return true if arg of the specified mode should be passed in a register
7952 or false otherwise. */
7953 static bool
sh_pass_in_reg_p(const CUMULATIVE_ARGS & cum,machine_mode mode,const_tree type)7954 sh_pass_in_reg_p (const CUMULATIVE_ARGS& cum, machine_mode mode,
7955 const_tree type)
7956 {
7957 /* FIXME: This used to be a macro and has been copy pasted into this
7958 function as is. Make this more readable. */
7959 return
7960 ((type == 0
7961 || (! TREE_ADDRESSABLE (type)
7962 && (! (TARGET_HITACHI || cum.renesas_abi)
7963 || ! (AGGREGATE_TYPE_P (type)
7964 || (!TARGET_FPU_ANY
7965 && (GET_MODE_CLASS (mode) == MODE_FLOAT
7966 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (SFmode)))))))
7967 && ! cum.force_mem
7968 && (TARGET_SH2E
7969 ? ((mode) == BLKmode
7970 ? ((cum.arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD
7971 + int_size_in_bytes (type))
7972 <= NPARM_REGS (SImode) * UNITS_PER_WORD)
7973 : ((sh_round_reg (cum, mode)
7974 + sh_hard_regno_nregs (BASE_ARG_REG (mode), mode))
7975 <= NPARM_REGS (mode)))
7976 : sh_round_reg (cum, mode) < NPARM_REGS (mode)));
7977 }
7978
7979 static int
sh_arg_partial_bytes(cumulative_args_t cum_v,machine_mode mode,tree type,bool named ATTRIBUTE_UNUSED)7980 sh_arg_partial_bytes (cumulative_args_t cum_v, machine_mode mode,
7981 tree type, bool named ATTRIBUTE_UNUSED)
7982 {
7983 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
7984 int words = 0;
7985
7986 if (sh_pass_in_reg_p (*cum, mode, type)
7987 && !TARGET_FPU_DOUBLE
7988 && (sh_round_reg (*cum, mode)
7989 + (mode != BLKmode
7990 ? CEIL (GET_MODE_SIZE (mode), UNITS_PER_WORD)
7991 : CEIL (int_size_in_bytes (type), UNITS_PER_WORD))
7992 > NPARM_REGS (mode)))
7993 words = NPARM_REGS (mode) - sh_round_reg (*cum, mode);
7994
7995 return words * UNITS_PER_WORD;
7996 }
7997
7998
7999 /* Define where to put the arguments to a function.
8000 Value is zero to push the argument on the stack,
8001 or a hard register in which to store the argument.
8002
8003 MODE is the argument's machine mode.
8004 TYPE is the data type of the argument (as a tree).
8005 This is null for libcalls where that information may
8006 not be available.
8007 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8008 the preceding args and about the function being called.
8009 NAMED is nonzero if this argument is a named parameter
8010 (otherwise it is an extra parameter matching an ellipsis).
8011
8012 On SH the first args are normally in registers
8013 and the rest are pushed. Any arg that starts within the first
8014 NPARM_REGS words is at least partially passed in a register unless
8015 its data type forbids. */
8016 static rtx
sh_function_arg(cumulative_args_t ca_v,machine_mode mode,const_tree type,bool named)8017 sh_function_arg (cumulative_args_t ca_v, machine_mode mode,
8018 const_tree type, bool named)
8019 {
8020 CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v);
8021
8022 if (mode == VOIDmode)
8023 return ca->renesas_abi ? const1_rtx : const0_rtx;
8024
8025 if (sh_pass_in_reg_p (*ca, mode, type)
8026 && (named || ! (TARGET_HITACHI || ca->renesas_abi)))
8027 {
8028 int regno;
8029
8030 if (mode == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN
8031 && (! FUNCTION_ARG_SCmode_WART || (sh_round_reg (*ca, mode) & 1)))
8032 {
8033 rtx r1 = gen_rtx_EXPR_LIST (VOIDmode,
8034 gen_rtx_REG (SFmode,
8035 BASE_ARG_REG (mode)
8036 + (sh_round_reg (*ca, mode) ^ 1)),
8037 const0_rtx);
8038 rtx r2 = gen_rtx_EXPR_LIST (VOIDmode,
8039 gen_rtx_REG (SFmode,
8040 BASE_ARG_REG (mode)
8041 + ((sh_round_reg (*ca, mode) + 1) ^ 1)),
8042 GEN_INT (4));
8043 return gen_rtx_PARALLEL(SCmode, gen_rtvec(2, r1, r2));
8044 }
8045
8046 /* If the alignment of a DF value causes an SF register to be
8047 skipped, we will use that skipped register for the next SF
8048 value. */
8049 if ((TARGET_HITACHI || ca->renesas_abi)
8050 && ca->free_single_fp_reg
8051 && mode == SFmode)
8052 return gen_rtx_REG (mode, ca->free_single_fp_reg);
8053
8054 regno = (BASE_ARG_REG (mode) + sh_round_reg (*ca, mode))
8055 ^ (mode == SFmode && TARGET_SH4
8056 && TARGET_LITTLE_ENDIAN
8057 && ! TARGET_HITACHI && ! ca->renesas_abi);
8058 return gen_rtx_REG (mode, regno);
8059
8060 }
8061
8062 return NULL_RTX;
8063 }
8064
8065 /* Update the data in CUM to advance over an argument
8066 of mode MODE and data type TYPE.
8067 (TYPE is null for libcalls where that information may not be
8068 available.) */
8069 static void
sh_function_arg_advance(cumulative_args_t ca_v,machine_mode mode,const_tree type,bool named ATTRIBUTE_UNUSED)8070 sh_function_arg_advance (cumulative_args_t ca_v, machine_mode mode,
8071 const_tree type, bool named ATTRIBUTE_UNUSED)
8072 {
8073 CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v);
8074
8075 if (ca->force_mem)
8076 ca->force_mem = false;
8077
8078 if ((TARGET_HITACHI || ca->renesas_abi) && TARGET_FPU_DOUBLE)
8079 {
8080 /* Note that we've used the skipped register. */
8081 if (mode == SFmode && ca->free_single_fp_reg)
8082 {
8083 ca->free_single_fp_reg = 0;
8084 return;
8085 }
8086 /* When we have a DF after an SF, there's an SF register that get
8087 skipped in order to align the DF value. We note this skipped
8088 register, because the next SF value will use it, and not the
8089 SF that follows the DF. */
8090 if (mode == DFmode
8091 && sh_round_reg (*ca, DFmode) != sh_round_reg (*ca, SFmode))
8092 {
8093 ca->free_single_fp_reg = (sh_round_reg (*ca, SFmode)
8094 + BASE_ARG_REG (mode));
8095 }
8096 }
8097
8098 if (! ((TARGET_SH4 || TARGET_SH2A) || ca->renesas_abi)
8099 || sh_pass_in_reg_p (*ca, mode, type))
8100 (ca->arg_count[(int) get_sh_arg_class (mode)]
8101 = (sh_round_reg (*ca, mode)
8102 + (mode == BLKmode
8103 ? CEIL (int_size_in_bytes (type), UNITS_PER_WORD)
8104 : CEIL (GET_MODE_SIZE (mode), UNITS_PER_WORD))));
8105 }
8106
8107 /* The Renesas calling convention doesn't quite fit into this scheme since
8108 the address is passed like an invisible argument, but one that is always
8109 passed in memory. */
8110 static rtx
sh_struct_value_rtx(tree fndecl,int incoming ATTRIBUTE_UNUSED)8111 sh_struct_value_rtx (tree fndecl, int incoming ATTRIBUTE_UNUSED)
8112 {
8113 if (TARGET_HITACHI || sh_attr_renesas_p (fndecl))
8114 return NULL_RTX;
8115 return gen_rtx_REG (Pmode, 2);
8116 }
8117
8118 /* Worker function for TARGET_FUNCTION_VALUE.
8119
8120 For the SH, this is like LIBCALL_VALUE, except that we must change the
8121 mode like PROMOTE_MODE does.
8122 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
8123 tested here has to be kept in sync with the one in
8124 explow.c:promote_mode. */
8125 static rtx
sh_function_value(const_tree valtype,const_tree fn_decl_or_type,bool outgoing ATTRIBUTE_UNUSED)8126 sh_function_value (const_tree valtype,
8127 const_tree fn_decl_or_type,
8128 bool outgoing ATTRIBUTE_UNUSED)
8129 {
8130 if (fn_decl_or_type
8131 && !DECL_P (fn_decl_or_type))
8132 fn_decl_or_type = NULL;
8133
8134 return gen_rtx_REG (
8135 ((GET_MODE_CLASS (TYPE_MODE (valtype)) == MODE_INT
8136 && GET_MODE_SIZE (TYPE_MODE (valtype)) < 4
8137 && (TREE_CODE (valtype) == INTEGER_TYPE
8138 || TREE_CODE (valtype) == ENUMERAL_TYPE
8139 || TREE_CODE (valtype) == BOOLEAN_TYPE
8140 || TREE_CODE (valtype) == REAL_TYPE
8141 || TREE_CODE (valtype) == OFFSET_TYPE))
8142 && sh_promote_prototypes (fn_decl_or_type)
8143 ? SImode : TYPE_MODE (valtype)),
8144 BASE_RETURN_VALUE_REG (TYPE_MODE (valtype)));
8145 }
8146
8147 /* Worker function for TARGET_LIBCALL_VALUE. */
8148 static rtx
sh_libcall_value(machine_mode mode,const_rtx fun ATTRIBUTE_UNUSED)8149 sh_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
8150 {
8151 return gen_rtx_REG (mode, BASE_RETURN_VALUE_REG (mode));
8152 }
8153
8154 /* Return true if N is a possible register number of function value. */
8155 static bool
sh_function_value_regno_p(const unsigned int regno)8156 sh_function_value_regno_p (const unsigned int regno)
8157 {
8158 return regno == FIRST_RET_REG || (TARGET_SH2E && regno == FIRST_FP_RET_REG);
8159 }
8160
8161 /* Worker function for TARGET_RETURN_IN_MEMORY. */
8162 static bool
sh_return_in_memory(const_tree type,const_tree fndecl)8163 sh_return_in_memory (const_tree type, const_tree fndecl)
8164 {
8165 return TYPE_MODE (type) == BLKmode
8166 || ((TARGET_HITACHI || sh_attr_renesas_p (fndecl))
8167 && TREE_CODE (type) == RECORD_TYPE);
8168 }
8169
8170 /* We actually emit the code in sh_expand_prologue. We used to use
8171 a static variable to flag that we need to emit this code, but that
8172 doesn't when inlining, when functions are deferred and then emitted
8173 later. Fortunately, we already have two flags that are part of struct
8174 function that tell if a function uses varargs or stdarg. */
8175 static void
sh_setup_incoming_varargs(cumulative_args_t ca,machine_mode mode,tree type,int * pretend_arg_size,int second_time ATTRIBUTE_UNUSED)8176 sh_setup_incoming_varargs (cumulative_args_t ca,
8177 machine_mode mode,
8178 tree type,
8179 int *pretend_arg_size,
8180 int second_time ATTRIBUTE_UNUSED)
8181 {
8182 gcc_assert (cfun->stdarg);
8183 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
8184 {
8185 int named_parm_regs, anon_parm_regs;
8186
8187 named_parm_regs = (sh_round_reg (*get_cumulative_args (ca), mode)
8188 + (mode == BLKmode
8189 ? CEIL (int_size_in_bytes (type), UNITS_PER_WORD)
8190 : CEIL (GET_MODE_SIZE (mode), UNITS_PER_WORD)));
8191 anon_parm_regs = NPARM_REGS (SImode) - named_parm_regs;
8192 if (anon_parm_regs > 0)
8193 *pretend_arg_size = anon_parm_regs * 4;
8194 }
8195 }
8196
8197 static bool
sh_strict_argument_naming(cumulative_args_t ca ATTRIBUTE_UNUSED)8198 sh_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED)
8199 {
8200 return false;
8201 }
8202
8203 static bool
sh_pretend_outgoing_varargs_named(cumulative_args_t ca_v)8204 sh_pretend_outgoing_varargs_named (cumulative_args_t ca_v)
8205 {
8206 CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v);
8207
8208 return ! (TARGET_HITACHI || ca->renesas_abi);
8209 }
8210
8211
8212 /* Define the offset between two registers, one to be eliminated, and
8213 the other its replacement, at the start of a routine. */
8214 int
initial_elimination_offset(int from,int to)8215 initial_elimination_offset (int from, int to)
8216 {
8217 const int regs_saved_rounding = 0;
8218 int save_flags = target_flags;
8219 HARD_REG_SET live_regs_mask;
8220
8221 int regs_saved = calc_live_regs (&live_regs_mask);
8222
8223 int total_auto_space = rounded_frame_size (regs_saved) - regs_saved_rounding;
8224 target_flags = save_flags;
8225
8226 int total_saved_regs_space = regs_saved + regs_saved_rounding;
8227
8228 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
8229 return total_saved_regs_space + total_auto_space;
8230
8231 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8232 return total_saved_regs_space + total_auto_space;
8233
8234 /* Initial gap between fp and sp is 0. */
8235 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8236 return 0;
8237
8238 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8239 return rounded_frame_size (0);
8240
8241 if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
8242 return rounded_frame_size (0);
8243
8244 gcc_assert (from == RETURN_ADDRESS_POINTER_REGNUM
8245 && (to == HARD_FRAME_POINTER_REGNUM
8246 || to == STACK_POINTER_REGNUM));
8247 return total_auto_space;
8248 }
8249
8250 /* Parse the -mfixed-range= option string. */
8251 void
sh_fix_range(const char * const_str)8252 sh_fix_range (const char *const_str)
8253 {
8254 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
8255 REG2 are either register names or register numbers. The effect
8256 of this option is to mark the registers in the range from REG1 to
8257 REG2 as ``fixed'' so they won't be used by the compiler. */
8258
8259 char* str = strcpy ((char*)alloca (strlen (const_str) + 1), const_str);
8260
8261 while (1)
8262 {
8263 char* dash = strchr (str, '-');
8264 if (!dash)
8265 {
8266 warning (0, "value of -mfixed-range must have form REG1-REG2");
8267 return;
8268 }
8269 *dash = '\0';
8270 char* comma = strchr (dash + 1, ',');
8271 if (comma)
8272 *comma = '\0';
8273
8274 int first = decode_reg_name (str);
8275 if (first < 0)
8276 {
8277 warning (0, "unknown register name: %s", str);
8278 return;
8279 }
8280
8281 int last = decode_reg_name (dash + 1);
8282 if (last < 0)
8283 {
8284 warning (0, "unknown register name: %s", dash + 1);
8285 return;
8286 }
8287
8288 *dash = '-';
8289
8290 if (first > last)
8291 {
8292 warning (0, "%s-%s is an empty range", str, dash + 1);
8293 return;
8294 }
8295
8296 for (int i = first; i <= last; ++i)
8297 fixed_regs[i] = call_used_regs[i] = 1;
8298
8299 if (!comma)
8300 break;
8301
8302 *comma = ',';
8303 str = comma + 1;
8304 }
8305 }
8306
8307 /* Insert any deferred function attributes from earlier pragmas. */
8308 static void
sh_insert_attributes(tree node,tree * attributes)8309 sh_insert_attributes (tree node, tree *attributes)
8310 {
8311 if (TREE_CODE (node) != FUNCTION_DECL)
8312 return;
8313
8314 /* We are only interested in fields. */
8315 if (!DECL_P (node))
8316 return;
8317
8318 /* Append the attributes to the deferred attributes. */
8319 *sh_deferred_function_attributes_tail = *attributes;
8320 tree attrs = sh_deferred_function_attributes;
8321 if (!attrs)
8322 return;
8323
8324 /* Some attributes imply or require the interrupt attribute. */
8325 if (!lookup_attribute ("interrupt_handler", attrs)
8326 && !lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (node)))
8327 {
8328 /* If we have a trapa_handler, but no interrupt_handler attribute,
8329 insert an interrupt_handler attribute. */
8330 if (lookup_attribute ("trapa_handler", attrs) != NULL_TREE)
8331 /* We can't use sh_pr_interrupt here because that's not in the
8332 java frontend. */
8333 attrs
8334 = tree_cons (get_identifier("interrupt_handler"), NULL_TREE, attrs);
8335 /* However, for sp_switch, trap_exit, nosave_low_regs and resbank,
8336 if the interrupt attribute is missing, we ignore the attribute
8337 and warn. */
8338 else if (lookup_attribute ("sp_switch", attrs)
8339 || lookup_attribute ("trap_exit", attrs)
8340 || lookup_attribute ("nosave_low_regs", attrs)
8341 || lookup_attribute ("resbank", attrs))
8342 {
8343 tree *tail;
8344
8345 for (tail = attributes; attrs; attrs = TREE_CHAIN (attrs))
8346 {
8347 if (is_attribute_p ("sp_switch", TREE_PURPOSE (attrs))
8348 || is_attribute_p ("trap_exit", TREE_PURPOSE (attrs))
8349 || is_attribute_p ("nosave_low_regs", TREE_PURPOSE (attrs))
8350 || is_attribute_p ("resbank", TREE_PURPOSE (attrs)))
8351 warning (OPT_Wattributes,
8352 "%qE attribute only applies to interrupt functions",
8353 TREE_PURPOSE (attrs));
8354 else
8355 {
8356 *tail = tree_cons (TREE_PURPOSE (attrs), NULL_TREE,
8357 NULL_TREE);
8358 tail = &TREE_CHAIN (*tail);
8359 }
8360 }
8361 attrs = *attributes;
8362 }
8363 }
8364
8365 /* Install the processed list. */
8366 *attributes = attrs;
8367
8368 /* Clear deferred attributes. */
8369 sh_deferred_function_attributes = NULL_TREE;
8370 sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
8371
8372 return;
8373 }
8374
8375 /*------------------------------------------------------------------------------
8376 Target specific attributes
8377 Supported attributes are:
8378
8379 * interrupt_handler
8380 Specifies this function is an interrupt handler.
8381
8382 * trapa_handler
8383 Like interrupt_handler, but don't save all registers.
8384
8385 * sp_switch
8386 Specifies an alternate stack for an interrupt handler to run on.
8387
8388 * trap_exit
8389 Use a trapa to exit an interrupt function instead of rte.
8390
8391 * nosave_low_regs
8392 Don't save r0..r7 in an interrupt handler function.
8393 This is useful on SH3* and SH4*, which have a separate set of low
8394 regs for user and privileged modes.
8395 This is mainly to be used for non-reentrant interrupt handlers (i.e.
8396 those that run with interrupts disabled and thus can't be
8397 interrupted thenselves).
8398
8399 * renesas
8400 Use Renesas calling/layout conventions (functions and structures).
8401
8402 * resbank
8403 In case of an interrupt handler function, use a register bank to
8404 save registers R0-R14, MACH, MACL, GBR and PR.
8405 This is available only on SH2A targets.
8406
8407 * function_vector
8408 Declares a function to be called using the TBR relative addressing
8409 mode. Takes an argument that specifies the slot number in the table
8410 where this function can be looked up by the JSR/N @@(disp8,TBR) insn.
8411 */
8412
8413 /* Handle a 'resbank' attribute. */
8414 static tree
sh_handle_resbank_handler_attribute(tree * node,tree name,tree args ATTRIBUTE_UNUSED,int flags ATTRIBUTE_UNUSED,bool * no_add_attrs)8415 sh_handle_resbank_handler_attribute (tree * node, tree name,
8416 tree args ATTRIBUTE_UNUSED,
8417 int flags ATTRIBUTE_UNUSED,
8418 bool * no_add_attrs)
8419 {
8420 if (!TARGET_SH2A)
8421 {
8422 warning (OPT_Wattributes, "%qE attribute is supported only for SH2A",
8423 name);
8424 *no_add_attrs = true;
8425 }
8426 if (TREE_CODE (*node) != FUNCTION_DECL)
8427 {
8428 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8429 name);
8430 *no_add_attrs = true;
8431 }
8432
8433 return NULL_TREE;
8434 }
8435
8436 /* Handle an "interrupt_handler" attribute; arguments as in
8437 struct attribute_spec.handler. */
8438 static tree
sh_handle_interrupt_handler_attribute(tree * node,tree name,tree args ATTRIBUTE_UNUSED,int flags ATTRIBUTE_UNUSED,bool * no_add_attrs)8439 sh_handle_interrupt_handler_attribute (tree *node, tree name,
8440 tree args ATTRIBUTE_UNUSED,
8441 int flags ATTRIBUTE_UNUSED,
8442 bool *no_add_attrs)
8443 {
8444 if (TREE_CODE (*node) != FUNCTION_DECL)
8445 {
8446 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8447 name);
8448 *no_add_attrs = true;
8449 }
8450
8451 return NULL_TREE;
8452 }
8453
8454 /* Handle an 'function_vector' attribute; arguments as in
8455 struct attribute_spec.handler. */
8456 static tree
sh2a_handle_function_vector_handler_attribute(tree * node,tree name,tree args ATTRIBUTE_UNUSED,int flags ATTRIBUTE_UNUSED,bool * no_add_attrs)8457 sh2a_handle_function_vector_handler_attribute (tree * node, tree name,
8458 tree args ATTRIBUTE_UNUSED,
8459 int flags ATTRIBUTE_UNUSED,
8460 bool * no_add_attrs)
8461 {
8462 if (!TARGET_SH2A)
8463 {
8464 warning (OPT_Wattributes, "%qE attribute only applies to SH2A",
8465 name);
8466 *no_add_attrs = true;
8467 }
8468 else if (TREE_CODE (*node) != FUNCTION_DECL)
8469 {
8470 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8471 name);
8472 *no_add_attrs = true;
8473 }
8474 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
8475 {
8476 /* The argument must be a constant integer. */
8477 warning (OPT_Wattributes,
8478 "%qE attribute argument not an integer constant",
8479 name);
8480 *no_add_attrs = true;
8481 }
8482 else if (TREE_INT_CST_LOW (TREE_VALUE (args)) > 255)
8483 {
8484 /* The argument value must be between 0 to 255. */
8485 warning (OPT_Wattributes,
8486 "%qE attribute argument should be between 0 to 255",
8487 name);
8488 *no_add_attrs = true;
8489 }
8490 return NULL_TREE;
8491 }
8492
8493 /* Returns true if current function has been assigned the attribute
8494 'function_vector'. */
8495 bool
sh2a_is_function_vector_call(rtx x)8496 sh2a_is_function_vector_call (rtx x)
8497 {
8498 if (GET_CODE (x) == SYMBOL_REF
8499 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
8500 {
8501 tree tr = SYMBOL_REF_DECL (x);
8502
8503 if (sh2a_function_vector_p (tr))
8504 return true;
8505 }
8506
8507 return false;
8508 }
8509
8510 /* Returns the function vector number, if the attribute
8511 'function_vector' is assigned, otherwise returns zero. */
8512 int
sh2a_get_function_vector_number(rtx x)8513 sh2a_get_function_vector_number (rtx x)
8514 {
8515 if ((GET_CODE (x) == SYMBOL_REF)
8516 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
8517 {
8518 tree t = SYMBOL_REF_DECL (x);
8519
8520 if (TREE_CODE (t) != FUNCTION_DECL)
8521 return 0;
8522
8523 for (tree list = SH_ATTRIBUTES (t); list; list = TREE_CHAIN (list))
8524 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
8525 return TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list)));
8526
8527 return 0;
8528 }
8529 else
8530 return 0;
8531 }
8532
8533 /* Handle an "sp_switch" attribute; arguments as in
8534 struct attribute_spec.handler. */
8535 static tree
sh_handle_sp_switch_attribute(tree * node,tree name,tree args,int flags ATTRIBUTE_UNUSED,bool * no_add_attrs)8536 sh_handle_sp_switch_attribute (tree *node, tree name, tree args,
8537 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
8538 {
8539 if (TREE_CODE (*node) != FUNCTION_DECL)
8540 {
8541 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8542 name);
8543 *no_add_attrs = true;
8544 }
8545 else if (TREE_CODE (TREE_VALUE (args)) != STRING_CST)
8546 {
8547 /* The argument must be a constant string. */
8548 warning (OPT_Wattributes, "%qE attribute argument not a string constant",
8549 name);
8550 *no_add_attrs = true;
8551 }
8552
8553 return NULL_TREE;
8554 }
8555
8556 /* Handle an "trap_exit" attribute; arguments as in
8557 struct attribute_spec.handler. */
8558 static tree
sh_handle_trap_exit_attribute(tree * node,tree name,tree args,int flags ATTRIBUTE_UNUSED,bool * no_add_attrs)8559 sh_handle_trap_exit_attribute (tree *node, tree name, tree args,
8560 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
8561 {
8562 if (TREE_CODE (*node) != FUNCTION_DECL)
8563 {
8564 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8565 name);
8566 *no_add_attrs = true;
8567 }
8568 /* The argument specifies a trap number to be used in a trapa instruction
8569 at function exit (instead of an rte instruction). */
8570 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
8571 {
8572 /* The argument must be a constant integer. */
8573 warning (OPT_Wattributes, "%qE attribute argument not an "
8574 "integer constant", name);
8575 *no_add_attrs = true;
8576 }
8577
8578 return NULL_TREE;
8579 }
8580
8581 static tree
sh_handle_renesas_attribute(tree * node ATTRIBUTE_UNUSED,tree name ATTRIBUTE_UNUSED,tree args ATTRIBUTE_UNUSED,int flags ATTRIBUTE_UNUSED,bool * no_add_attrs ATTRIBUTE_UNUSED)8582 sh_handle_renesas_attribute (tree *node ATTRIBUTE_UNUSED,
8583 tree name ATTRIBUTE_UNUSED,
8584 tree args ATTRIBUTE_UNUSED,
8585 int flags ATTRIBUTE_UNUSED,
8586 bool *no_add_attrs ATTRIBUTE_UNUSED)
8587 {
8588 return NULL_TREE;
8589 }
8590
8591 /* True if __attribute__((renesas)) or -mrenesas. */
8592 bool
sh_attr_renesas_p(const_tree td)8593 sh_attr_renesas_p (const_tree td)
8594 {
8595 if (TARGET_HITACHI)
8596 return true;
8597 if (td == NULL_TREE)
8598 return false;
8599 if (DECL_P (td))
8600 td = TREE_TYPE (td);
8601 if (td == error_mark_node)
8602 return false;
8603 return lookup_attribute ("renesas", TYPE_ATTRIBUTES (td)) != NULL_TREE;
8604 }
8605
8606 /* True if __attribute__((renesas)) or -mrenesas, for the current
8607 function. */
8608 bool
sh_cfun_attr_renesas_p(void)8609 sh_cfun_attr_renesas_p (void)
8610 {
8611 return sh_attr_renesas_p (current_function_decl);
8612 }
8613
8614 /* Returns true if the current function has the "interrupt_handler"
8615 attribute set. */
8616 bool
sh_cfun_interrupt_handler_p(void)8617 sh_cfun_interrupt_handler_p (void)
8618 {
8619 return (lookup_attribute ("interrupt_handler",
8620 DECL_ATTRIBUTES (current_function_decl))
8621 != NULL_TREE);
8622 }
8623
8624 /* Returns true if FUNC has been assigned the attribute
8625 "function_vector". */
8626 bool
sh2a_function_vector_p(tree func)8627 sh2a_function_vector_p (tree func)
8628 {
8629 if (TREE_CODE (func) != FUNCTION_DECL)
8630 return false;
8631
8632 for (tree list = SH_ATTRIBUTES (func); list; list = TREE_CHAIN (list))
8633 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
8634 return true;
8635
8636 return false;
8637 }
8638
8639 /* Returns true if given tree has the "resbank" attribute set. */
8640 bool
sh_cfun_resbank_handler_p(void)8641 sh_cfun_resbank_handler_p (void)
8642 {
8643 return ((lookup_attribute ("resbank",
8644 DECL_ATTRIBUTES (current_function_decl))
8645 != NULL_TREE)
8646 && (lookup_attribute ("interrupt_handler",
8647 DECL_ATTRIBUTES (current_function_decl))
8648 != NULL_TREE) && TARGET_SH2A);
8649 }
8650
8651 /* Returns true if the current function has a "trap_exit" attribute set. */
8652 bool
sh_cfun_trap_exit_p(void)8653 sh_cfun_trap_exit_p (void)
8654 {
8655 return lookup_attribute ("trap_exit", DECL_ATTRIBUTES (current_function_decl))
8656 != NULL_TREE;
8657 }
8658
8659 /* Implement TARGET_CHECK_PCH_TARGET_FLAGS. */
8660 static const char *
sh_check_pch_target_flags(int old_flags)8661 sh_check_pch_target_flags (int old_flags)
8662 {
8663 if ((old_flags ^ target_flags) & (MASK_SH1 | MASK_SH2 | MASK_SH3
8664 | MASK_SH_E | MASK_HARD_SH4
8665 | MASK_FPU_SINGLE | MASK_SH4))
8666 return _("created and used with different architectures / ABIs");
8667 if ((old_flags ^ target_flags) & MASK_HITACHI)
8668 return _("created and used with different ABIs");
8669 if ((old_flags ^ target_flags) & MASK_LITTLE_ENDIAN)
8670 return _("created and used with different endianness");
8671 return NULL;
8672 }
8673
8674 /* Predicates used by the templates. */
8675
8676 /* Returns true if OP is MACL, MACH or PR. The input must be a REG rtx.
8677 Used only in general_movsrc_operand. */
8678 bool
system_reg_operand(rtx op,machine_mode mode ATTRIBUTE_UNUSED)8679 system_reg_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
8680 {
8681 switch (REGNO (op))
8682 {
8683 case PR_REG:
8684 case MACL_REG:
8685 case MACH_REG:
8686 return true;
8687 }
8688 return false;
8689 }
8690
8691 /* Returns true if OP is a floating point value with value 0.0. */
8692 bool
fp_zero_operand(rtx op)8693 fp_zero_operand (rtx op)
8694 {
8695 if (GET_MODE (op) != SFmode)
8696 return false;
8697
8698 const REAL_VALUE_TYPE* r = CONST_DOUBLE_REAL_VALUE (op);
8699 return real_equal (r, &dconst0) && ! REAL_VALUE_MINUS_ZERO (*r);
8700 }
8701
8702 /* Returns true if OP is a floating point value with value 1.0. */
8703 bool
fp_one_operand(rtx op)8704 fp_one_operand (rtx op)
8705 {
8706 if (GET_MODE (op) != SFmode)
8707 return false;
8708
8709 return real_equal (CONST_DOUBLE_REAL_VALUE (op), &dconst1);
8710 }
8711
8712 /* Return the TLS type for TLS symbols. */
8713 enum tls_model
tls_symbolic_operand(rtx op,machine_mode mode ATTRIBUTE_UNUSED)8714 tls_symbolic_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
8715 {
8716 if (GET_CODE (op) != SYMBOL_REF)
8717 return TLS_MODEL_NONE;
8718 return SYMBOL_REF_TLS_MODEL (op);
8719 }
8720
8721 /* Return the destination address of a branch. */
8722 static int
branch_dest(rtx branch)8723 branch_dest (rtx branch)
8724 {
8725 rtx dest = SET_SRC (PATTERN (branch));
8726
8727 if (GET_CODE (dest) == IF_THEN_ELSE)
8728 dest = XEXP (dest, 1);
8729
8730 return INSN_ADDRESSES (INSN_UID (XEXP (dest, 0)));
8731 }
8732
8733 /* Return nonzero if REG is not used after INSN.
8734 We assume REG is a reload reg, and therefore does
8735 not live past labels. It may live past calls or jumps though. */
8736 bool
reg_unused_after(rtx reg,rtx_insn * insn)8737 reg_unused_after (rtx reg, rtx_insn *insn)
8738 {
8739 /* If the reg is set by this instruction, then it is safe for our
8740 case. Disregard the case where this is a store to memory, since
8741 we are checking a register used in the store address. */
8742 rtx set = single_set (insn);
8743 if (set && !MEM_P (SET_DEST (set))
8744 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
8745 return true;
8746
8747 while ((insn = NEXT_INSN (insn)))
8748 {
8749 if (!INSN_P (insn))
8750 continue;
8751
8752 rtx_code code = GET_CODE (insn);
8753
8754 #if 0
8755 /* If this is a label that existed before reload, then the register
8756 is dead here. However, if this is a label added by reorg, then
8757 the register may still be live here. We can't tell the difference,
8758 so we just ignore labels completely. */
8759 if (code == CODE_LABEL)
8760 return 1;
8761 /* else */
8762 #endif
8763
8764 if (code == JUMP_INSN)
8765 return false;
8766
8767 /* If this is a sequence, we must handle them all at once.
8768 We could have for instance a call that sets the target register,
8769 and an insn in a delay slot that uses the register. In this case,
8770 we must return 0. */
8771 else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
8772 {
8773 rtx_sequence *seq = as_a <rtx_sequence *> (PATTERN (insn));
8774 bool retval = false;
8775
8776 for (int i = 0; i < seq->len (); i++)
8777 {
8778 rtx_insn *this_insn = seq->insn (i);
8779 rtx set = single_set (this_insn);
8780
8781 if (CALL_P (this_insn))
8782 code = CALL_INSN;
8783 else if (JUMP_P (this_insn))
8784 {
8785 if (INSN_ANNULLED_BRANCH_P (this_insn))
8786 return false;
8787 code = JUMP_INSN;
8788 }
8789
8790 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
8791 return false;
8792 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
8793 {
8794 if (!MEM_P (SET_DEST (set)))
8795 retval = true;
8796 else
8797 return false;
8798 }
8799 if (set == NULL_RTX
8800 && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
8801 return false;
8802 }
8803 if (retval)
8804 return true;
8805 else if (code == JUMP_INSN)
8806 return false;
8807 }
8808
8809 rtx set = single_set (insn);
8810 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
8811 return false;
8812 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
8813 return !MEM_P (SET_DEST (set));
8814 if (set == NULL && reg_overlap_mentioned_p (reg, PATTERN (insn)))
8815 return false;
8816
8817 if (code == CALL_INSN && call_really_used_regs[REGNO (reg)])
8818 return true;
8819 }
8820 return true;
8821 }
8822
8823
8824 static GTY(()) rtx t_reg_rtx;
8825 rtx
get_t_reg_rtx(void)8826 get_t_reg_rtx (void)
8827 {
8828 if (! t_reg_rtx)
8829 t_reg_rtx = gen_rtx_REG (SImode, T_REG);
8830 return t_reg_rtx;
8831 }
8832
8833 static GTY(()) tree fpscr_values;
8834
8835 static void
emit_fpu_switch(rtx scratch,int index)8836 emit_fpu_switch (rtx scratch, int index)
8837 {
8838 if (fpscr_values == NULL)
8839 {
8840 tree t = build_index_type (integer_one_node);
8841 t = build_array_type (integer_type_node, t);
8842 t = build_decl (BUILTINS_LOCATION,
8843 VAR_DECL, get_identifier ("__fpscr_values"), t);
8844 DECL_ARTIFICIAL (t) = 1;
8845 DECL_IGNORED_P (t) = 1;
8846 DECL_EXTERNAL (t) = 1;
8847 TREE_STATIC (t) = 1;
8848 TREE_PUBLIC (t) = 1;
8849 TREE_USED (t) = 1;
8850
8851 fpscr_values = t;
8852 }
8853
8854 rtx src = DECL_RTL (fpscr_values);
8855 if (!can_create_pseudo_p ())
8856 {
8857 emit_move_insn (scratch, XEXP (src, 0));
8858 if (index != 0)
8859 emit_insn (gen_addsi3 (scratch, scratch, GEN_INT (index * 4)));
8860 src = adjust_automodify_address (src, SImode, scratch, index * 4);
8861 }
8862 else
8863 src = adjust_address (src, SImode, index * 4);
8864
8865 emit_insn (gen_lds_fpscr (src));
8866 }
8867
8868 static rtx get_free_reg (HARD_REG_SET);
8869
8870 /* This function returns a register to use to load the address to load
8871 the fpscr from. Currently it always returns r1 or r7, but when we are
8872 able to use pseudo registers after combine, or have a better mechanism
8873 for choosing a register, it should be done here. */
8874 /* REGS_LIVE is the liveness information for the point for which we
8875 need this allocation. In some bare-bones exit blocks, r1 is live at the
8876 start. We can even have all of r0..r3 being live:
8877 __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
8878 INSN before which new insns are placed with will clobber the register
8879 we return. If a basic block consists only of setting the return value
8880 register to a pseudo and using that register, the return value is not
8881 live before or after this block, yet we we'll insert our insns right in
8882 the middle. */
8883 static rtx
get_free_reg(HARD_REG_SET regs_live)8884 get_free_reg (HARD_REG_SET regs_live)
8885 {
8886 if (! TEST_HARD_REG_BIT (regs_live, 1))
8887 return gen_rtx_REG (Pmode, 1);
8888
8889 /* Hard reg 1 is live; since this is a small register classes target,
8890 there shouldn't be anything but a jump before the function end. */
8891 gcc_assert (!TEST_HARD_REG_BIT (regs_live, 7));
8892 return gen_rtx_REG (Pmode, 7);
8893 }
8894
8895 /* This function will set the fpscr from memory.
8896 MODE is the mode we are setting it to. */
8897 void
fpscr_set_from_mem(int mode,HARD_REG_SET regs_live)8898 fpscr_set_from_mem (int mode, HARD_REG_SET regs_live)
8899 {
8900 enum attr_fp_mode fp_mode = (enum attr_fp_mode) mode;
8901 enum attr_fp_mode norm_mode = ACTUAL_NORMAL_MODE (FP_MODE);
8902
8903 rtx addr_reg = !can_create_pseudo_p () ? get_free_reg (regs_live) : NULL_RTX;
8904 emit_fpu_switch (addr_reg, fp_mode == norm_mode);
8905 }
8906
8907 /* Is the given character a logical line separator for the assembler? */
8908 #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
8909 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == ';')
8910 #endif
8911
8912 static bool
sequence_insn_p(rtx_insn * insn)8913 sequence_insn_p (rtx_insn *insn)
8914 {
8915 rtx_insn* prev = PREV_INSN (insn);
8916 if (prev == NULL)
8917 return false;
8918
8919 rtx_insn* next = NEXT_INSN (prev);
8920 if (next == NULL)
8921 return false;
8922
8923 return INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE;
8924 }
8925
8926 int
sh_insn_length_adjustment(rtx_insn * insn)8927 sh_insn_length_adjustment (rtx_insn *insn)
8928 {
8929 /* Instructions with unfilled delay slots take up an extra two bytes for
8930 the nop in the delay slot. */
8931 if (((NONJUMP_INSN_P (insn)
8932 && GET_CODE (PATTERN (insn)) != USE
8933 && GET_CODE (PATTERN (insn)) != CLOBBER)
8934 || CALL_P (insn) || JUMP_P (insn))
8935 && ! sequence_insn_p (insn)
8936 && get_attr_needs_delay_slot (insn) == NEEDS_DELAY_SLOT_YES)
8937 return 2;
8938
8939 /* Increase the insn length of a cbranch without a delay slot insn to
8940 force a delay slot which will be stuffed with a nop. */
8941 if (TARGET_CBRANCH_FORCE_DELAY_SLOT && TARGET_SH2
8942 && JUMP_P (insn) && get_attr_type (insn) == TYPE_CBRANCH
8943 && ! sequence_insn_p (insn))
8944 return 2;
8945
8946 /* sh-dsp parallel processing insn take four bytes instead of two. */
8947
8948 if (NONJUMP_INSN_P (insn))
8949 {
8950 int sum = 0;
8951 rtx body = PATTERN (insn);
8952 const char *templ;
8953 char c;
8954 bool maybe_label = true;
8955
8956 if (GET_CODE (body) == ASM_INPUT)
8957 templ = XSTR (body, 0);
8958 else if (asm_noperands (body) >= 0)
8959 templ
8960 = decode_asm_operands (body, NULL, NULL, NULL, NULL, NULL);
8961 else
8962 return 0;
8963 do
8964 {
8965 int ppi_adjust = 0;
8966
8967 do
8968 c = *templ++;
8969 while (c == ' ' || c == '\t');
8970 /* all sh-dsp parallel-processing insns start with p.
8971 The only non-ppi sh insn starting with p is pref.
8972 The only ppi starting with pr is prnd. */
8973 if ((c == 'p' || c == 'P') && strncasecmp ("re", templ, 2))
8974 ppi_adjust = 2;
8975 /* The repeat pseudo-insn expands two three insns, a total of
8976 six bytes in size. */
8977 else if ((c == 'r' || c == 'R')
8978 && ! strncasecmp ("epeat", templ, 5))
8979 ppi_adjust = 4;
8980 while (c && c != '\n'
8981 && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c, templ))
8982 {
8983 /* If this is a label, it is obviously not a ppi insn. */
8984 if (c == ':' && maybe_label)
8985 {
8986 ppi_adjust = 0;
8987 break;
8988 }
8989 else if (c == '\'' || c == '"')
8990 maybe_label = false;
8991 c = *templ++;
8992 }
8993 sum += ppi_adjust;
8994 maybe_label = c != ':';
8995 }
8996 while (c);
8997 return sum;
8998 }
8999 return 0;
9000 }
9001
9002 /* Return TRUE for a valid displacement for the REG+disp addressing
9003 with MODE. */
9004 bool
sh_legitimate_index_p(machine_mode mode,rtx op,bool consider_sh2a,bool allow_zero)9005 sh_legitimate_index_p (machine_mode mode, rtx op, bool consider_sh2a,
9006 bool allow_zero)
9007 {
9008 if (! CONST_INT_P (op))
9009 return false;
9010
9011 {
9012 const HOST_WIDE_INT offset = INTVAL (op);
9013 const int max_disp = sh_max_mov_insn_displacement (mode, consider_sh2a);
9014 const int align_mask = mov_insn_alignment_mask (mode, consider_sh2a);
9015
9016 /* If the mode does not support any displacement always return false.
9017 Even though an index of '0' is actually always valid, it will cause
9018 troubles when e.g. a DFmode move is split into two SFmode moves,
9019 where one SFmode move will have index '0' and the other move will
9020 have index '4'. */
9021 if (!allow_zero && max_disp < 1)
9022 return false;
9023
9024 return offset >= 0 && offset <= max_disp && (offset & align_mask) == 0;
9025 }
9026 }
9027
9028 /* Recognize an RTL expression that is a valid memory address for
9029 an instruction.
9030 The MODE argument is the machine mode for the MEM expression
9031 that wants to use this address.
9032 Allow REG
9033 REG+disp
9034 REG+r0
9035 REG++
9036 --REG
9037 GBR
9038 GBR+disp */
9039 static bool
sh_legitimate_address_p(machine_mode mode,rtx x,bool strict)9040 sh_legitimate_address_p (machine_mode mode, rtx x, bool strict)
9041 {
9042 if (REG_P (x) && REGNO (x) == GBR_REG)
9043 return true;
9044
9045 if (MAYBE_BASE_REGISTER_RTX_P (x, strict))
9046 return true;
9047 else if ((GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_DEC)
9048 && MAYBE_BASE_REGISTER_RTX_P (XEXP (x, 0), strict))
9049 return true;
9050 else if (GET_CODE (x) == PLUS)
9051 {
9052 rtx xop0 = XEXP (x, 0);
9053 rtx xop1 = XEXP (x, 1);
9054
9055 if (REG_P (xop0) && REGNO (xop0) == GBR_REG)
9056 return gbr_displacement (xop1, mode);
9057
9058 if (GET_MODE_SIZE (mode) <= 8
9059 && MAYBE_BASE_REGISTER_RTX_P (xop0, strict)
9060 && sh_legitimate_index_p (mode, xop1, TARGET_SH2A, false))
9061 return true;
9062
9063 if (GET_MODE_SIZE (mode) <= 4
9064 || (TARGET_FPU_DOUBLE && TARGET_FMOVD && mode == DFmode))
9065 {
9066 if (MAYBE_BASE_REGISTER_RTX_P (xop1, strict)
9067 && MAYBE_INDEX_REGISTER_RTX_P (xop0, strict))
9068 return true;
9069 if (MAYBE_INDEX_REGISTER_RTX_P (xop1, strict)
9070 && MAYBE_BASE_REGISTER_RTX_P (xop0, strict))
9071 return true;
9072 }
9073 }
9074
9075 return false;
9076 }
9077
9078 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
9079 isn't protected by a PIC unspec. */
9080 bool
nonpic_symbol_mentioned_p(rtx x)9081 nonpic_symbol_mentioned_p (rtx x)
9082 {
9083 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF
9084 || GET_CODE (x) == PC)
9085 return true;
9086
9087 /* We don't want to look into the possible MEM location of a
9088 CONST_DOUBLE, since we're not going to use it, in general. */
9089 if (GET_CODE (x) == CONST_DOUBLE)
9090 return false;
9091
9092 if (GET_CODE (x) == UNSPEC
9093 && (XINT (x, 1) == UNSPEC_PIC
9094 || XINT (x, 1) == UNSPEC_GOT
9095 || XINT (x, 1) == UNSPEC_GOTOFF
9096 || XINT (x, 1) == UNSPEC_GOTPLT
9097 || XINT (x, 1) == UNSPEC_GOTTPOFF
9098 || XINT (x, 1) == UNSPEC_DTPOFF
9099 || XINT (x, 1) == UNSPEC_TPOFF
9100 || XINT (x, 1) == UNSPEC_PLT
9101 || XINT (x, 1) == UNSPEC_PCREL
9102 || XINT (x, 1) == UNSPEC_SYMOFF
9103 || XINT (x, 1) == UNSPEC_PCREL_SYMOFF
9104 || XINT (x, 1) == UNSPEC_GOTFUNCDESC
9105 || XINT (x, 1) == UNSPEC_GOTOFFFUNCDESC))
9106 return false;
9107
9108 const char* fmt = GET_RTX_FORMAT (GET_CODE (x));
9109 for (int i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
9110 {
9111 if (fmt[i] == 'E')
9112 {
9113 for (int j = XVECLEN (x, i) - 1; j >= 0; j--)
9114 if (nonpic_symbol_mentioned_p (XVECEXP (x, i, j)))
9115 return true;
9116 }
9117 else if (fmt[i] == 'e' && nonpic_symbol_mentioned_p (XEXP (x, i)))
9118 return true;
9119 }
9120
9121 return false;
9122 }
9123
9124 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
9125 @GOTOFF in `reg'. */
9126 rtx
legitimize_pic_address(rtx orig,machine_mode mode ATTRIBUTE_UNUSED,rtx reg)9127 legitimize_pic_address (rtx orig, machine_mode mode ATTRIBUTE_UNUSED, rtx reg)
9128 {
9129 if (tls_symbolic_operand (orig, Pmode) != TLS_MODEL_NONE)
9130 return orig;
9131
9132 if (GET_CODE (orig) == LABEL_REF
9133 || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig)))
9134 {
9135 if (reg == NULL_RTX)
9136 reg = gen_reg_rtx (Pmode);
9137
9138 if (TARGET_FDPIC
9139 && GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (orig))
9140 {
9141 /* Weak functions may be NULL which doesn't work with
9142 GOTOFFFUNCDESC because the runtime offset is not known. */
9143 if (SYMBOL_REF_WEAK (orig))
9144 emit_insn (gen_symGOTFUNCDESC2reg (reg, orig));
9145 else
9146 emit_insn (gen_symGOTOFFFUNCDESC2reg (reg, orig));
9147 }
9148 else if (TARGET_FDPIC
9149 && (GET_CODE (orig) == LABEL_REF
9150 || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_DECL (orig)
9151 && (TREE_READONLY (SYMBOL_REF_DECL (orig))
9152 || SYMBOL_REF_EXTERNAL_P (orig)
9153 || DECL_SECTION_NAME(SYMBOL_REF_DECL (orig))))))
9154 /* In FDPIC, GOTOFF can only be used for writable data. */
9155 emit_insn (gen_symGOT2reg (reg, orig));
9156 else
9157 emit_insn (gen_symGOTOFF2reg (reg, orig));
9158 return reg;
9159 }
9160 else if (GET_CODE (orig) == SYMBOL_REF)
9161 {
9162 if (reg == NULL_RTX)
9163 reg = gen_reg_rtx (Pmode);
9164
9165 if (TARGET_FDPIC && SYMBOL_REF_FUNCTION_P (orig))
9166 emit_insn (gen_symGOTFUNCDESC2reg (reg, orig));
9167 else
9168 emit_insn (gen_symGOT2reg (reg, orig));
9169 return reg;
9170 }
9171 return orig;
9172 }
9173
9174 /* Given a (logical) mode size and an offset in bytes, try to find a the
9175 appropriate displacement value for a mov insn. On SH the displacements
9176 are limited to max. 60 bytes for SImode, max. 30 bytes in HImode and max.
9177 15 bytes in QImode. To compensate this we create a new base address by
9178 adding an adjustment value to it.
9179
9180 If the originally requested offset is greater than 127 we prefer using
9181 values 124..127 over 128..131 to increase opportunities to use the
9182 add #imm, Rn insn.
9183
9184 In some cases it is possible that a requested offset might seem unaligned
9185 or inappropriate for the mode size, like offset = 2 and mode size = 4.
9186 This is compensated by adjusting the base address so that the effective
9187 address of the displacement move insn will be aligned.
9188
9189 This is not the best possible way of rebasing the base address, as it
9190 does not look at other present displacement addressings around it.
9191 In some cases this can create more base address adjustments than would
9192 actually be necessary. */
9193 struct disp_adjust
9194 {
9195 rtx offset_adjust;
9196 rtx mov_disp;
9197 };
9198
9199 static struct disp_adjust
sh_find_mov_disp_adjust(machine_mode mode,HOST_WIDE_INT offset)9200 sh_find_mov_disp_adjust (machine_mode mode, HOST_WIDE_INT offset)
9201 {
9202 struct disp_adjust res = { NULL_RTX, NULL_RTX };
9203
9204 /* Do not try to use SH2A's large displacements here, because this would
9205 effectively disable the small displacement insns. */
9206 const int mode_sz = GET_MODE_SIZE (mode);
9207 const int mov_insn_sz = mov_insn_size (mode, false);
9208 const int max_disp = sh_max_mov_insn_displacement (mode, false);
9209 const int max_disp_next = max_disp + mov_insn_sz;
9210 HOST_WIDE_INT align_modifier = offset > 127 ? mov_insn_sz : 0;
9211 HOST_WIDE_INT offset_adjust;
9212
9213 /* In some cases this actually does happen and we must check for it. */
9214 if (mode_sz < 1 || mode_sz > 8 || max_disp < 1)
9215 return res;
9216
9217 /* Keeps the previous behavior for QImode displacement addressing.
9218 This just decides how the offset is re-based. Removing this special
9219 case will result in slightly bigger code on average, but it's not that
9220 bad actually. */
9221 if (mov_insn_sz == 1)
9222 align_modifier = 0;
9223
9224 offset_adjust = ((offset + align_modifier) & ~max_disp) - align_modifier;
9225
9226 if (mode_sz + offset - offset_adjust <= max_disp_next)
9227 {
9228 res.offset_adjust = GEN_INT (offset_adjust);
9229 res.mov_disp = GEN_INT (offset - offset_adjust);
9230 }
9231
9232 return res;
9233 }
9234
9235 /* Try to modify an illegitimate address and make it legitimate.
9236 If we find one, return the new, valid address.
9237 Otherwise, return the original address. */
9238 static rtx
sh_legitimize_address(rtx x,rtx oldx,machine_mode mode)9239 sh_legitimize_address (rtx x, rtx oldx, machine_mode mode)
9240 {
9241 if (flag_pic)
9242 x = legitimize_pic_address (oldx, mode, NULL_RTX);
9243
9244 if ((TARGET_FPU_DOUBLE && mode == DFmode)
9245 || (TARGET_SH2E && mode == SFmode))
9246 return x;
9247
9248 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1))
9249 && BASE_REGISTER_RTX_P (XEXP (x, 0)))
9250 {
9251 struct disp_adjust adj = sh_find_mov_disp_adjust (mode,
9252 INTVAL (XEXP (x, 1)));
9253
9254 if (adj.offset_adjust != NULL_RTX && adj.mov_disp != NULL_RTX)
9255 {
9256 rtx sum = expand_binop (Pmode, add_optab, XEXP (x, 0),
9257 adj.offset_adjust, NULL_RTX, 0,
9258 OPTAB_LIB_WIDEN);
9259 return gen_rtx_PLUS (Pmode, sum, adj.mov_disp);
9260 }
9261 }
9262 return x;
9263 }
9264
9265 /* Attempt to replace *p, which is an address that needs reloading, with
9266 a valid memory address for an operand of mode MODE.
9267 Like for sh_legitimize_address, for the SH we try to get a normal form
9268 of the address. That will allow inheritance of the address reloads. */
9269 bool
sh_legitimize_reload_address(rtx * p,machine_mode mode,int opnum,int itype)9270 sh_legitimize_reload_address (rtx *p, machine_mode mode, int opnum,
9271 int itype)
9272 {
9273 enum reload_type type = (enum reload_type) itype;
9274 const int mode_sz = GET_MODE_SIZE (mode);
9275
9276 if (sh_lra_p ())
9277 return false;
9278
9279 if (GET_CODE (*p) == PLUS && CONST_INT_P (XEXP (*p, 1))
9280 && MAYBE_BASE_REGISTER_RTX_P (XEXP (*p, 0), true))
9281 {
9282 const HOST_WIDE_INT offset = INTVAL (XEXP (*p, 1));
9283 struct disp_adjust adj = sh_find_mov_disp_adjust (mode, offset);
9284
9285 if (TARGET_SH2A && mode == DFmode && (offset & 0x7))
9286 {
9287 push_reload (*p, NULL_RTX, p, NULL,
9288 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type);
9289 return true;
9290 }
9291
9292 if (TARGET_SH2E && mode == SFmode)
9293 {
9294 *p = copy_rtx (*p);
9295 push_reload (*p, NULL_RTX, p, NULL,
9296 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type);
9297 return true;
9298 }
9299
9300 /* FIXME: Do not allow to legitimize QImode and HImode displacement
9301 moves because then reload has a problem figuring the constraint
9302 that the move insn target/source reg must be R0.
9303 Or maybe some handling is wrong in sh_secondary_reload for this
9304 to work properly? */
9305 if ((mode_sz == 4 || mode_sz == 8)
9306 && ! (TARGET_SH4 && mode == DFmode)
9307 && adj.offset_adjust != NULL_RTX && adj.mov_disp != NULL_RTX)
9308 {
9309 rtx sum = gen_rtx_PLUS (Pmode, XEXP (*p, 0), adj.offset_adjust);
9310 *p = gen_rtx_PLUS (Pmode, sum, adj.mov_disp);
9311 push_reload (sum, NULL_RTX, &XEXP (*p, 0), NULL,
9312 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type);
9313 return true;
9314 }
9315 }
9316
9317 /* We must re-recognize what we created before. */
9318 if (GET_CODE (*p) == PLUS
9319 && (mode_sz == 4 || mode_sz == 8)
9320 && GET_CODE (XEXP (*p, 0)) == PLUS
9321 && CONST_INT_P (XEXP (XEXP (*p, 0), 1))
9322 && MAYBE_BASE_REGISTER_RTX_P (XEXP (XEXP (*p, 0), 0), true)
9323 && CONST_INT_P (XEXP (*p, 1))
9324 && ! (TARGET_SH2E && mode == SFmode))
9325 {
9326 /* Because this address is so complex, we know it must have
9327 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus,
9328 it is already unshared, and needs no further unsharing. */
9329 push_reload (XEXP (*p, 0), NULL_RTX, &XEXP (*p, 0), NULL,
9330 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type);
9331 return true;
9332 }
9333
9334 return false;
9335 }
9336
9337 /* In the name of slightly smaller debug output, and to cater to
9338 general assembler lossage, recognize various UNSPEC sequences
9339 and turn them back into a direct symbol reference. */
9340 static rtx
sh_delegitimize_address(rtx orig_x)9341 sh_delegitimize_address (rtx orig_x)
9342 {
9343 orig_x = delegitimize_mem_from_attrs (orig_x);
9344
9345 rtx x = orig_x;
9346 if (MEM_P (x))
9347 x = XEXP (x, 0);
9348 if (GET_CODE (x) == CONST)
9349 {
9350 rtx y = XEXP (x, 0);
9351 if (GET_CODE (y) == UNSPEC)
9352 {
9353 if (XINT (y, 1) == UNSPEC_GOT
9354 || XINT (y, 1) == UNSPEC_GOTOFF
9355 || XINT (y, 1) == UNSPEC_SYMOFF)
9356 return XVECEXP (y, 0, 0);
9357 else if (XINT (y, 1) == UNSPEC_PCREL_SYMOFF)
9358 {
9359 if (GET_CODE (XVECEXP (y, 0, 0)) == CONST)
9360 {
9361 rtx symplt = XEXP (XVECEXP (y, 0, 0), 0);
9362
9363 if (GET_CODE (symplt) == UNSPEC
9364 && (XINT (symplt, 1) == UNSPEC_PLT
9365 || XINT (symplt, 1) == UNSPEC_PCREL))
9366 return XVECEXP (symplt, 0, 0);
9367 }
9368 }
9369 }
9370 }
9371
9372 return orig_x;
9373 }
9374
9375 /* Mark the use of a constant in the literal table. If the constant
9376 has multiple labels, make it unique. */
9377 static rtx
mark_constant_pool_use(rtx x)9378 mark_constant_pool_use (rtx x)
9379 {
9380 if (x == NULL_RTX)
9381 return x;
9382
9383 switch (GET_CODE (x))
9384 {
9385 case LABEL_REF:
9386 x = XEXP (x, 0);
9387 case CODE_LABEL:
9388 break;
9389 default:
9390 return x;
9391 }
9392
9393 /* Get the first label in the list of labels for the same constant
9394 and delete another labels in the list. */
9395 rtx_insn* lab = as_a <rtx_insn*> (x);
9396 for (rtx_insn* insn = PREV_INSN (lab); insn; insn = PREV_INSN (insn))
9397 {
9398 if (!LABEL_P (insn)
9399 || LABEL_REFS (insn) != NEXT_INSN (insn))
9400 break;
9401 lab = insn;
9402 }
9403
9404 for (rtx insn = LABEL_REFS (lab); insn; insn = LABEL_REFS (insn))
9405 as_a<rtx_insn *> (insn)->set_deleted ();
9406
9407 /* Mark constants in a window. */
9408 for (rtx_insn* insn = NEXT_INSN (as_a <rtx_insn *> (x)); insn;
9409 insn = NEXT_INSN (insn))
9410 {
9411 if (!NONJUMP_INSN_P (insn))
9412 continue;
9413
9414 rtx pattern = PATTERN (insn);
9415 if (GET_CODE (pattern) != UNSPEC_VOLATILE)
9416 continue;
9417
9418 switch (XINT (pattern, 1))
9419 {
9420 case UNSPECV_CONST2:
9421 case UNSPECV_CONST4:
9422 case UNSPECV_CONST8:
9423 XVECEXP (pattern, 0, 1) = const1_rtx;
9424 break;
9425 case UNSPECV_WINDOW_END:
9426 if (XVECEXP (pattern, 0, 0) == x)
9427 return lab;
9428 break;
9429 case UNSPECV_CONST_END:
9430 return lab;
9431 default:
9432 break;
9433 }
9434 }
9435
9436 return lab;
9437 }
9438
9439 /* Return true if it's possible to redirect BRANCH1 to the destination
9440 of an unconditional jump BRANCH2. We only want to do this if the
9441 resulting branch will have a short displacement. */
9442 static bool
sh_can_follow_jump(const rtx_insn * branch1,const rtx_insn * branch2)9443 sh_can_follow_jump (const rtx_insn *branch1, const rtx_insn *branch2)
9444 {
9445 /* Don't follow if BRANCH2 is possible to be a jump crossing between
9446 hot and cold partitions. */
9447 if (flag_reorder_blocks_and_partition
9448 && simplejump_p (branch2)
9449 && CROSSING_JUMP_P (branch2))
9450 return false;
9451
9452 if (flag_expensive_optimizations && simplejump_p (branch2))
9453 {
9454 rtx dest = XEXP (SET_SRC (single_set (branch2)), 0);
9455 rtx_insn *insn;
9456 int distance;
9457
9458 for (distance = 0, insn = NEXT_INSN (branch1);
9459 insn && distance < 256;
9460 insn = PREV_INSN (insn))
9461 {
9462 if (insn == dest)
9463 return true;
9464 else
9465 distance += get_attr_length (insn);
9466 }
9467 for (distance = 0, insn = NEXT_INSN (branch1);
9468 insn && distance < 256;
9469 insn = NEXT_INSN (insn))
9470 {
9471 if (insn == dest)
9472 return true;
9473 else
9474 distance += get_attr_length (insn);
9475 }
9476 }
9477 return false;
9478 }
9479
9480 /* Return nonzero if register old_reg can be renamed to register new_reg. */
9481 bool
sh_hard_regno_rename_ok(unsigned int old_reg ATTRIBUTE_UNUSED,unsigned int new_reg)9482 sh_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
9483 unsigned int new_reg)
9484 {
9485 /* Interrupt functions can only use registers that have already been
9486 saved by the prologue, even if they would normally be
9487 call-clobbered. */
9488 if (sh_cfun_interrupt_handler_p () && !df_regs_ever_live_p (new_reg))
9489 return false;
9490
9491 return true;
9492 }
9493
9494 /* Function to update the integer COST
9495 based on the relationship between INSN that is dependent on
9496 DEP_INSN through the dependence LINK. The default is to make no
9497 adjustment to COST. This can be used for example to specify to
9498 the scheduler that an output- or anti-dependence does not incur
9499 the same cost as a data-dependence. The return value should be
9500 the new value for COST. */
9501 static int
sh_adjust_cost(rtx_insn * insn,int dep_type,rtx_insn * dep_insn,int cost,unsigned int)9502 sh_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost,
9503 unsigned int)
9504 {
9505 rtx reg, use_pat;
9506
9507 if (dep_type == 0)
9508 {
9509 if (recog_memoized (insn) < 0
9510 || recog_memoized (dep_insn) < 0)
9511 return cost;
9512
9513 rtx dep_set = single_set (dep_insn);
9514
9515 /* The latency that we specify in the scheduling description refers
9516 to the actual output, not to an auto-increment register; for that,
9517 the latency is one. */
9518 if (dep_set && MEM_P (SET_SRC (dep_set)) && cost > 1)
9519 {
9520 rtx set = single_set (insn);
9521
9522 if (set
9523 && !reg_mentioned_p (SET_DEST (dep_set), SET_SRC (set))
9524 && (!MEM_P (SET_DEST (set))
9525 || !reg_mentioned_p (SET_DEST (dep_set),
9526 XEXP (SET_DEST (set), 0))))
9527 cost = 1;
9528 }
9529 /* The only input for a call that is timing-critical is the
9530 function's address. */
9531 if (CALL_P (insn))
9532 {
9533 rtx call = get_call_rtx_from (insn);
9534 if (call
9535 /* sibcalli_thunk uses a symbol_ref in an unspec. */
9536 && (GET_CODE (XEXP (XEXP (call, 0), 0)) == UNSPEC
9537 || ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn)))
9538 cost -= TARGET_SH4_300 ? 3 : 6;
9539 }
9540 /* Likewise, the most timing critical input for an sfuncs call
9541 is the function address. However, sfuncs typically start
9542 using their arguments pretty quickly.
9543 Assume a four cycle delay for SH4 before they are needed.
9544 Cached ST40-300 calls are quicker, so assume only a one
9545 cycle delay there.
9546 ??? Maybe we should encode the delays till input registers
9547 are needed by sfuncs into the sfunc call insn. */
9548 /* All sfunc calls are parallels with at least four components.
9549 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
9550 else if (GET_CODE (PATTERN (insn)) == PARALLEL
9551 && XVECLEN (PATTERN (insn), 0) >= 4
9552 && (reg = sfunc_uses_reg (insn)))
9553 {
9554 if (! reg_set_p (reg, dep_insn))
9555 cost -= TARGET_SH4_300 ? 1 : 4;
9556 }
9557 if (TARGET_HARD_SH4 && !TARGET_SH4_300)
9558 {
9559 attr_type dep_type = get_attr_type (dep_insn);
9560 attr_type type;
9561 if (dep_type == TYPE_FLOAD || dep_type == TYPE_PCFLOAD)
9562 cost--;
9563 else if ((dep_type == TYPE_LOAD_SI || dep_type == TYPE_PCLOAD_SI)
9564 && (type = get_attr_type (insn)) != TYPE_CALL
9565 && type != TYPE_SFUNC)
9566 cost--;
9567 /* When the preceding instruction loads the shift amount of
9568 the following SHAD/SHLD, the latency of the load is increased
9569 by 1 cycle. */
9570 if (get_attr_type (insn) == TYPE_DYN_SHIFT
9571 && get_attr_any_int_load (dep_insn) == ANY_INT_LOAD_YES
9572 && reg_overlap_mentioned_p (SET_DEST (dep_set),
9573 XEXP (SET_SRC (single_set (insn)),
9574 1)))
9575 cost++;
9576 /* When an LS group instruction with a latency of less than
9577 3 cycles is followed by a double-precision floating-point
9578 instruction, FIPR, or FTRV, the latency of the first
9579 instruction is increased to 3 cycles. */
9580 else if (cost < 3
9581 && get_attr_insn_class (dep_insn) == INSN_CLASS_LS_GROUP
9582 && get_attr_dfp_comp (insn) == DFP_COMP_YES)
9583 cost = 3;
9584 /* The lsw register of a double-precision computation is ready one
9585 cycle earlier. */
9586 else if (reload_completed
9587 && get_attr_dfp_comp (dep_insn) == DFP_COMP_YES
9588 && (use_pat = single_set (insn))
9589 && ! regno_use_in (REGNO (SET_DEST (single_set (dep_insn))),
9590 SET_SRC (use_pat)))
9591 cost -= 1;
9592
9593 if (get_attr_any_fp_comp (dep_insn) == ANY_FP_COMP_YES
9594 && get_attr_late_fp_use (insn) == LATE_FP_USE_YES)
9595 cost -= 1;
9596 }
9597 else if (TARGET_SH4_300)
9598 {
9599 /* Stores need their input register two cycles later. */
9600 attr_type type;
9601 if (dep_set && cost >= 1
9602 && ((type = get_attr_type (insn)) == TYPE_STORE
9603 || type == TYPE_PSTORE
9604 || type == TYPE_FSTORE || type == TYPE_MAC_MEM))
9605 {
9606 rtx set = single_set (insn);
9607
9608 if (!reg_mentioned_p (SET_SRC (set), XEXP (SET_DEST (set), 0))
9609 && rtx_equal_p (SET_SRC (set), SET_DEST (dep_set)))
9610 {
9611 cost -= 2;
9612 /* But don't reduce the cost below 1 if the address depends
9613 on a side effect of dep_insn. */
9614 if (cost < 1
9615 && modified_in_p (XEXP (SET_DEST (set), 0), dep_insn))
9616 cost = 1;
9617 }
9618 }
9619 }
9620 }
9621 /* An anti-dependence penalty of two applies if the first insn is a double
9622 precision fadd / fsub / fmul. */
9623 else if (!TARGET_SH4_300
9624 && dep_type == REG_DEP_ANTI
9625 && recog_memoized (dep_insn) >= 0
9626 && (get_attr_type (dep_insn) == TYPE_DFP_ARITH
9627 || get_attr_type (dep_insn) == TYPE_DFP_MUL)
9628 /* A lot of alleged anti-flow dependences are fake,
9629 so check this one is real. */
9630 && flow_dependent_p (dep_insn, insn))
9631 cost = 2;
9632
9633 return cost;
9634 }
9635
9636 /* Check if INSN is flow-dependent on DEP_INSN. Can also be used to check
9637 if DEP_INSN is anti-flow dependent on INSN. */
9638 static bool
flow_dependent_p(rtx insn,rtx dep_insn)9639 flow_dependent_p (rtx insn, rtx dep_insn)
9640 {
9641 rtx tmp = PATTERN (insn);
9642
9643 note_stores (PATTERN (dep_insn), flow_dependent_p_1, &tmp);
9644 return tmp == NULL_RTX;
9645 }
9646
9647 /* A helper function for flow_dependent_p called through note_stores. */
9648 static void
flow_dependent_p_1(rtx x,const_rtx pat ATTRIBUTE_UNUSED,void * data)9649 flow_dependent_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
9650 {
9651 rtx * pinsn = (rtx *) data;
9652
9653 if (*pinsn && reg_referenced_p (x, *pinsn))
9654 *pinsn = NULL_RTX;
9655 }
9656
9657 /* For use by sh_allocate_initial_value. Note that sh.md contains some
9658 'special function' patterns (type sfunc) that clobber pr, but that
9659 do not look like function calls to leaf_function_p. Hence we must
9660 do this extra check. */
9661 static int
sh_pr_n_sets(void)9662 sh_pr_n_sets (void)
9663 {
9664 return DF_REG_DEF_COUNT (PR_REG);
9665 }
9666
9667 /* Return where to allocate pseudo for a given hard register initial
9668 value. */
9669 static rtx
sh_allocate_initial_value(rtx hard_reg)9670 sh_allocate_initial_value (rtx hard_reg)
9671 {
9672 if (REGNO (hard_reg) == PR_REG)
9673 {
9674 if (crtl->is_leaf && ! sh_pr_n_sets ())
9675 return hard_reg;
9676 else
9677 return gen_frame_mem (Pmode, return_address_pointer_rtx);
9678 }
9679
9680 return NULL_RTX;
9681 }
9682
9683 /* This function returns "2" to indicate dual issue for the SH4
9684 processor. To be used by the DFA pipeline description. */
9685 static int
sh_issue_rate(void)9686 sh_issue_rate (void)
9687 {
9688 if (TARGET_SUPERSCALAR)
9689 return 2;
9690 else
9691 return 1;
9692 }
9693
9694 /* Functions for ready queue reordering for sched1. */
9695
9696 /* Get weight for mode for a set x. */
9697 static short
find_set_regmode_weight(rtx x,machine_mode mode)9698 find_set_regmode_weight (rtx x, machine_mode mode)
9699 {
9700 if (GET_CODE (x) == CLOBBER && register_operand (SET_DEST (x), mode))
9701 return 1;
9702 if (GET_CODE (x) == SET && register_operand (SET_DEST (x), mode))
9703 {
9704 if (REG_P (SET_DEST (x)))
9705 {
9706 if (!reg_mentioned_p (SET_DEST (x), SET_SRC (x)))
9707 return 1;
9708 else
9709 return 0;
9710 }
9711 return 1;
9712 }
9713 return 0;
9714 }
9715
9716 /* Get regmode weight for insn. */
9717 static short
find_insn_regmode_weight(rtx insn,machine_mode mode)9718 find_insn_regmode_weight (rtx insn, machine_mode mode)
9719 {
9720 /* Increment weight for each register born here. */
9721 rtx x = PATTERN (insn);
9722 short reg_weight = find_set_regmode_weight (x, mode);
9723 if (GET_CODE (x) == PARALLEL)
9724 {
9725 int j;
9726 for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
9727 {
9728 x = XVECEXP (PATTERN (insn), 0, j);
9729 reg_weight += find_set_regmode_weight (x, mode);
9730 }
9731 }
9732 /* Decrement weight for each register that dies here. */
9733 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
9734 {
9735 if (REG_NOTE_KIND (x) == REG_DEAD || REG_NOTE_KIND (x) == REG_UNUSED)
9736 {
9737 rtx note = XEXP (x, 0);
9738 if (REG_P (note) && GET_MODE (note) == mode)
9739 reg_weight--;
9740 }
9741 }
9742 return reg_weight;
9743 }
9744
9745 /* Calculate regmode weights for all insns of a basic block. */
9746 static void
find_regmode_weight(basic_block b,machine_mode mode)9747 find_regmode_weight (basic_block b, machine_mode mode)
9748 {
9749 rtx_insn *insn, *next_tail, *head, *tail;
9750
9751 get_ebb_head_tail (b, b, &head, &tail);
9752 next_tail = NEXT_INSN (tail);
9753
9754 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
9755 {
9756 /* Handle register life information. */
9757 if (!INSN_P (insn))
9758 continue;
9759
9760 if (mode == SFmode)
9761 INSN_REGMODE_WEIGHT (insn, mode) =
9762 find_insn_regmode_weight (insn, mode)
9763 + 2 * find_insn_regmode_weight (insn, DFmode);
9764 else if (mode == SImode)
9765 INSN_REGMODE_WEIGHT (insn, mode) =
9766 find_insn_regmode_weight (insn, mode)
9767 + 2 * find_insn_regmode_weight (insn, DImode);
9768 }
9769 }
9770
9771 /* Comparison function for ready queue sorting. */
9772 static int
rank_for_reorder(const void * x,const void * y)9773 rank_for_reorder (const void *x, const void *y)
9774 {
9775 rtx_insn *tmp = *(rtx_insn * const *) y;
9776 rtx_insn *tmp2 = *(rtx_insn * const *) x;
9777
9778 /* The insn in a schedule group should be issued the first. */
9779 if (SCHED_GROUP_P (tmp) != SCHED_GROUP_P (tmp2))
9780 return SCHED_GROUP_P (tmp2) ? 1 : -1;
9781
9782 /* If insns are equally good, sort by INSN_LUID (original insn order), This
9783 minimizes instruction movement, thus minimizing sched's effect on
9784 register pressure. */
9785 return INSN_LUID (tmp) - INSN_LUID (tmp2);
9786 }
9787
9788 /* Resort the array A in which only element at index N may be out of order. */
9789 static void
swap_reorder(rtx_insn ** a,int n)9790 swap_reorder (rtx_insn **a, int n)
9791 {
9792 rtx_insn *insn = a[n - 1];
9793 int i = n - 2;
9794
9795 while (i >= 0 && rank_for_reorder (a + i, &insn) >= 0)
9796 {
9797 a[i + 1] = a[i];
9798 i -= 1;
9799 }
9800 a[i + 1] = insn;
9801 }
9802
9803 /* Sort the ready list by ascending priority. */
9804 static void
ready_reorder(rtx_insn ** ready,int nready)9805 ready_reorder (rtx_insn **ready, int nready)
9806 {
9807 if (nready == 2)
9808 swap_reorder (ready, nready);
9809 else if (nready > 2)
9810 qsort (ready, nready, sizeof (rtx_insn *), rank_for_reorder);
9811 }
9812
9813 /* Count life regions of r0 for a block. */
9814 static int
find_r0_life_regions(basic_block b)9815 find_r0_life_regions (basic_block b)
9816 {
9817 bool live;
9818 int set;
9819 int death = 0;
9820
9821 if (REGNO_REG_SET_P (df_get_live_in (b), R0_REG))
9822 {
9823 set = 1;
9824 live = true;
9825 }
9826 else
9827 {
9828 set = 0;
9829 live = false;
9830 }
9831
9832 rtx_insn* insn = BB_HEAD (b);
9833 rtx_insn* end = BB_END (b);
9834 rtx r0_reg = gen_rtx_REG (SImode, R0_REG);
9835 while (1)
9836 {
9837 if (INSN_P (insn))
9838 {
9839 if (find_regno_note (insn, REG_DEAD, R0_REG))
9840 {
9841 death++;
9842 live = false;
9843 }
9844
9845 rtx pset;
9846 if (!live
9847 && (pset = single_set (insn))
9848 && reg_overlap_mentioned_p (r0_reg, SET_DEST (pset))
9849 && !find_regno_note (insn, REG_UNUSED, R0_REG))
9850 {
9851 set++;
9852 live = true;
9853 }
9854 }
9855 if (insn == end)
9856 break;
9857 insn = NEXT_INSN (insn);
9858 }
9859 return set - death;
9860 }
9861
9862 /* Calculate regmode weights for all insns of all basic block. */
9863 static void
sh_md_init_global(FILE * dump ATTRIBUTE_UNUSED,int verbose ATTRIBUTE_UNUSED,int old_max_uid)9864 sh_md_init_global (FILE *dump ATTRIBUTE_UNUSED,
9865 int verbose ATTRIBUTE_UNUSED,
9866 int old_max_uid)
9867 {
9868 basic_block b;
9869
9870 regmode_weight[0] = (short *) xcalloc (old_max_uid, sizeof (short));
9871 regmode_weight[1] = (short *) xcalloc (old_max_uid, sizeof (short));
9872 r0_life_regions = 0;
9873
9874 FOR_EACH_BB_REVERSE_FN (b, cfun)
9875 {
9876 find_regmode_weight (b, SImode);
9877 find_regmode_weight (b, SFmode);
9878 if (!reload_completed)
9879 r0_life_regions += find_r0_life_regions (b);
9880 }
9881
9882 CURR_REGMODE_PRESSURE (SImode) = 0;
9883 CURR_REGMODE_PRESSURE (SFmode) = 0;
9884 }
9885
9886 /* Cleanup. */
9887 static void
sh_md_finish_global(FILE * dump ATTRIBUTE_UNUSED,int verbose ATTRIBUTE_UNUSED)9888 sh_md_finish_global (FILE *dump ATTRIBUTE_UNUSED,
9889 int verbose ATTRIBUTE_UNUSED)
9890 {
9891 if (regmode_weight[0])
9892 {
9893 free (regmode_weight[0]);
9894 regmode_weight[0] = NULL;
9895 }
9896 if (regmode_weight[1])
9897 {
9898 free (regmode_weight[1]);
9899 regmode_weight[1] = NULL;
9900 }
9901 }
9902
9903 /* Cache the can_issue_more so that we can return it from reorder2. Also,
9904 keep count of register pressures on SImode and SFmode. */
9905 static int
sh_variable_issue(FILE * dump ATTRIBUTE_UNUSED,int sched_verbose ATTRIBUTE_UNUSED,rtx_insn * insn,int can_issue_more)9906 sh_variable_issue (FILE *dump ATTRIBUTE_UNUSED,
9907 int sched_verbose ATTRIBUTE_UNUSED,
9908 rtx_insn *insn,
9909 int can_issue_more)
9910 {
9911 if (GET_CODE (PATTERN (insn)) != USE
9912 && GET_CODE (PATTERN (insn)) != CLOBBER)
9913 cached_can_issue_more = can_issue_more - 1;
9914 else
9915 cached_can_issue_more = can_issue_more;
9916
9917 if (reload_completed)
9918 return cached_can_issue_more;
9919
9920 CURR_REGMODE_PRESSURE (SImode) += INSN_REGMODE_WEIGHT (insn, SImode);
9921 CURR_REGMODE_PRESSURE (SFmode) += INSN_REGMODE_WEIGHT (insn, SFmode);
9922
9923 return cached_can_issue_more;
9924 }
9925
9926 static void
sh_md_init(FILE * dump ATTRIBUTE_UNUSED,int verbose ATTRIBUTE_UNUSED,int veclen ATTRIBUTE_UNUSED)9927 sh_md_init (FILE *dump ATTRIBUTE_UNUSED,
9928 int verbose ATTRIBUTE_UNUSED,
9929 int veclen ATTRIBUTE_UNUSED)
9930 {
9931 CURR_REGMODE_PRESSURE (SImode) = 0;
9932 CURR_REGMODE_PRESSURE (SFmode) = 0;
9933 }
9934
9935 /* Some magic numbers. */
9936 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
9937 functions that already have high pressure on r0. */
9938 #define R0_MAX_LIFE_REGIONS 2
9939 /* Register Pressure thresholds for SImode and SFmode registers. */
9940 #define SIMODE_MAX_WEIGHT 5
9941 #define SFMODE_MAX_WEIGHT 10
9942
9943 /* Return true if the pressure is high for MODE. */
9944 static bool
high_pressure(machine_mode mode)9945 high_pressure (machine_mode mode)
9946 {
9947 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
9948 functions that already have high pressure on r0. */
9949 if (r0_life_regions >= R0_MAX_LIFE_REGIONS)
9950 return true;
9951
9952 if (mode == SFmode)
9953 return (CURR_REGMODE_PRESSURE (SFmode) > SFMODE_MAX_WEIGHT);
9954 else
9955 return (CURR_REGMODE_PRESSURE (SImode) > SIMODE_MAX_WEIGHT);
9956 }
9957
9958 /* Reorder ready queue if register pressure is high. */
9959 static int
sh_reorder(FILE * dump ATTRIBUTE_UNUSED,int sched_verbose ATTRIBUTE_UNUSED,rtx_insn ** ready,int * n_readyp,int clock_var ATTRIBUTE_UNUSED)9960 sh_reorder (FILE *dump ATTRIBUTE_UNUSED,
9961 int sched_verbose ATTRIBUTE_UNUSED,
9962 rtx_insn **ready,
9963 int *n_readyp,
9964 int clock_var ATTRIBUTE_UNUSED)
9965 {
9966 if (reload_completed)
9967 return sh_issue_rate ();
9968
9969 if (high_pressure (SFmode) || high_pressure (SImode))
9970 {
9971 ready_reorder (ready, *n_readyp);
9972 }
9973
9974 return sh_issue_rate ();
9975 }
9976
9977 /* Skip cycles if the current register pressure is high. */
9978 static int
sh_reorder2(FILE * dump ATTRIBUTE_UNUSED,int sched_verbose ATTRIBUTE_UNUSED,rtx_insn ** ready ATTRIBUTE_UNUSED,int * n_readyp ATTRIBUTE_UNUSED,int clock_var ATTRIBUTE_UNUSED)9979 sh_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
9980 int sched_verbose ATTRIBUTE_UNUSED,
9981 rtx_insn **ready ATTRIBUTE_UNUSED,
9982 int *n_readyp ATTRIBUTE_UNUSED,
9983 int clock_var ATTRIBUTE_UNUSED)
9984 {
9985 if (reload_completed)
9986 return cached_can_issue_more;
9987
9988 if (high_pressure(SFmode) || high_pressure (SImode))
9989 skip_cycles = 1;
9990
9991 return cached_can_issue_more;
9992 }
9993
9994 /* Skip cycles without sorting the ready queue. This will move insn from
9995 Q->R. If this is the last cycle we are skipping; allow sorting of ready
9996 queue by sh_reorder. */
9997
9998 /* Generally, skipping these many cycles are sufficient for all insns to move
9999 from Q -> R. */
10000 #define MAX_SKIPS 8
10001
10002 static int
sh_dfa_new_cycle(FILE * sched_dump ATTRIBUTE_UNUSED,int sched_verbose ATTRIBUTE_UNUSED,rtx_insn * insn ATTRIBUTE_UNUSED,int last_clock_var,int clock_var,int * sort_p)10003 sh_dfa_new_cycle (FILE *sched_dump ATTRIBUTE_UNUSED,
10004 int sched_verbose ATTRIBUTE_UNUSED,
10005 rtx_insn *insn ATTRIBUTE_UNUSED,
10006 int last_clock_var,
10007 int clock_var,
10008 int *sort_p)
10009 {
10010 if (reload_completed)
10011 return 0;
10012
10013 if (skip_cycles)
10014 {
10015 if ((clock_var - last_clock_var) < MAX_SKIPS)
10016 {
10017 *sort_p = 0;
10018 return 1;
10019 }
10020 /* If this is the last cycle we are skipping, allow reordering of R. */
10021 if ((clock_var - last_clock_var) == MAX_SKIPS)
10022 {
10023 *sort_p = 1;
10024 return 1;
10025 }
10026 }
10027
10028 skip_cycles = 0;
10029
10030 return 0;
10031 }
10032
10033 static bool
sh_ms_bitfield_layout_p(const_tree record_type ATTRIBUTE_UNUSED)10034 sh_ms_bitfield_layout_p (const_tree record_type ATTRIBUTE_UNUSED)
10035 {
10036 return TARGET_HITACHI || sh_attr_renesas_p (record_type);
10037 }
10038
10039 /*
10040 On the SH1..SH4, the trampoline looks like
10041 2 0002 D202 mov.l l2,r2
10042 1 0000 D301 mov.l l1,r3
10043 3 0004 422B jmp @r2
10044 4 0006 0009 nop
10045 5 0008 00000000 l1: .long area
10046 6 000c 00000000 l2: .long function
10047
10048 FDPIC needs a form that includes a function descriptor and
10049 code to load the GOT register:
10050 0 0000 00000000 .long l0
10051 1 0004 00000000 .long gotval
10052 2 0008 D302 l0: mov.l l1,r3
10053 3 000a D203 mov.l l2,r2
10054 4 000c 6122 mov.l @r2,r1
10055 5 000e 5C21 mov.l @(4,r2),r12
10056 6 0010 412B jmp @r1
10057 7 0012 0009 nop
10058 8 0014 00000000 l1: .long area
10059 9 0018 00000000 l2: .long function
10060
10061 SH5 (compact) uses r1 instead of r3 for the static chain. */
10062
10063 /* Emit insns to store a value at memory address + offset. */
10064 static void
sh_emit_storesi(rtx addr,HOST_WIDE_INT offset,rtx value)10065 sh_emit_storesi (rtx addr, HOST_WIDE_INT offset, rtx value)
10066 {
10067 gcc_assert ((offset & 3) == 0);
10068 emit_move_insn (offset == 0
10069 ? change_address (addr, SImode, NULL_RTX)
10070 : adjust_address (addr, SImode, offset), value);
10071 }
10072
10073 /* Emit insns to store w0 at addr + offset and w1 at addr + offset + 2. */
10074 static void
sh_emit_storehi(rtx addr,HOST_WIDE_INT offset,uint16_t w0,uint16_t w1)10075 sh_emit_storehi (rtx addr, HOST_WIDE_INT offset, uint16_t w0, uint16_t w1)
10076 {
10077 sh_emit_storesi (addr, offset, gen_int_mode (TARGET_LITTLE_ENDIAN
10078 ? (w0 | (w1 << 16))
10079 : (w1 | (w0 << 16)), SImode));
10080 }
10081
10082 /* Emit RTL insns to initialize the variable parts of a trampoline.
10083 FNADDR is an RTX for the address of the function's pure code.
10084 CXT is an RTX for the static chain value for the function. */
10085 static void
sh_trampoline_init(rtx tramp_mem,tree fndecl,rtx cxt)10086 sh_trampoline_init (rtx tramp_mem, tree fndecl, rtx cxt)
10087 {
10088 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
10089 rtx tramp = force_reg (Pmode, XEXP (tramp_mem, 0));
10090
10091 if (TARGET_FDPIC)
10092 {
10093 rtx a = force_reg (Pmode, plus_constant (Pmode, XEXP (tramp_mem, 0), 8));
10094
10095 sh_emit_storesi (tramp_mem, 0, a);
10096 sh_emit_storesi (tramp_mem, 4, sh_get_fdpic_reg_initial_val ());
10097
10098 sh_emit_storehi (tramp_mem, 8, 0xd302, 0xd203);
10099 sh_emit_storehi (tramp_mem, 12, 0x6122, 0x5c21);
10100 sh_emit_storehi (tramp_mem, 16, 0x412b, 0x0009);
10101
10102 sh_emit_storesi (tramp_mem, 20, cxt);
10103 sh_emit_storesi (tramp_mem, 24, fnaddr);
10104 }
10105 else
10106 {
10107 sh_emit_storehi (tramp_mem, 0, 0xd202, 0xd301);
10108 sh_emit_storehi (tramp_mem, 4, 0x422b, 0x0009);
10109
10110 sh_emit_storesi (tramp_mem, 8, cxt);
10111 sh_emit_storesi (tramp_mem, 12, fnaddr);
10112 }
10113 if (TARGET_HARD_SH4)
10114 {
10115 if (!TARGET_INLINE_IC_INVALIDATE
10116 || (!(TARGET_SH4A || TARGET_SH4_300) && TARGET_USERMODE))
10117 emit_library_call (function_symbol (NULL, "__ic_invalidate",
10118 FUNCTION_ORDINARY).sym,
10119 LCT_NORMAL, VOIDmode, tramp, SImode);
10120 else
10121 emit_insn (gen_ic_invalidate_line (tramp));
10122 }
10123 }
10124
10125 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
10126 static rtx
sh_trampoline_adjust_address(rtx tramp)10127 sh_trampoline_adjust_address (rtx tramp)
10128 {
10129 return tramp;
10130 }
10131
10132 /* If PIC, we cannot make sibling calls to global functions
10133 because the PLT requires r12 to be live. */
10134 static bool
sh_function_ok_for_sibcall(tree decl,tree exp ATTRIBUTE_UNUSED)10135 sh_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
10136 {
10137 return (1
10138 && ! sh_cfun_interrupt_handler_p ()
10139 && (! flag_pic || TARGET_FDPIC
10140 || (decl && ! (TREE_PUBLIC (decl) || DECL_WEAK (decl)))
10141 || (decl && DECL_VISIBILITY (decl) != VISIBILITY_DEFAULT)));
10142 }
10143
10144 /* Expand to appropriate sym*_label2reg for SYM and SIBCALL_P. */
10145 void
sh_expand_sym_label2reg(rtx reg,rtx sym,rtx lab,bool sibcall_p)10146 sh_expand_sym_label2reg (rtx reg, rtx sym, rtx lab, bool sibcall_p)
10147 {
10148 const_tree decl = SYMBOL_REF_DECL (sym);
10149 bool is_weak = (decl && DECL_P (decl) && DECL_WEAK (decl));
10150
10151 if (!is_weak && SYMBOL_REF_LOCAL_P (sym))
10152 emit_insn (gen_sym_label2reg (reg, sym, lab));
10153 else if (sibcall_p && SYMBOL_REF_LOCAL_P (sym))
10154 emit_insn (gen_symPCREL_label2reg (reg, sym, lab));
10155 else
10156 emit_insn (gen_symPLT_label2reg (reg, sym, lab));
10157 }
10158
10159 /* Machine specific built-in functions. */
10160
10161 struct builtin_description
10162 {
10163 bool (* const is_enabled) (void);
10164 const enum insn_code icode;
10165 const char *const name;
10166 int signature;
10167 tree fndecl;
10168 };
10169
10170 /* This function can be used if there are any built-ins that are not for
10171 SHmedia. It's commented out to avoid the defined-but-unused warning. */
10172 static bool
sh1_builtin_p(void)10173 sh1_builtin_p (void)
10174 {
10175 return TARGET_SH1;
10176 }
10177
10178 /* describe number and signedness of arguments; arg[0] == result
10179 (1: unsigned, 2: signed, 4: don't care, 8: pointer 0: no argument */
10180 /* 9: 64-bit pointer, 10: 32-bit pointer */
10181 static const char signature_args[][4] =
10182 {
10183 #define SH_BLTIN_V2SI2 0
10184 { 4, 4 },
10185 #define SH_BLTIN_V4HI2 1
10186 { 4, 4 },
10187 #define SH_BLTIN_V2SI3 2
10188 { 4, 4, 4 },
10189 #define SH_BLTIN_V4HI3 3
10190 { 4, 4, 4 },
10191 #define SH_BLTIN_V8QI3 4
10192 { 4, 4, 4 },
10193 #define SH_BLTIN_MAC_HISI 5
10194 { 1, 4, 4, 1 },
10195 #define SH_BLTIN_SH_HI 6
10196 { 4, 4, 1 },
10197 #define SH_BLTIN_SH_SI 7
10198 { 4, 4, 1 },
10199 #define SH_BLTIN_V4HI2V2SI 8
10200 { 4, 4, 4 },
10201 #define SH_BLTIN_V4HI2V8QI 9
10202 { 4, 4, 4 },
10203 #define SH_BLTIN_SISF 10
10204 { 4, 2 },
10205 #define SH_BLTIN_LDUA_L 11
10206 { 2, 10 },
10207 #define SH_BLTIN_LDUA_Q 12
10208 { 1, 10 },
10209 #define SH_BLTIN_STUA_L 13
10210 { 0, 10, 2 },
10211 #define SH_BLTIN_STUA_Q 14
10212 { 0, 10, 1 },
10213 #define SH_BLTIN_LDUA_L64 15
10214 { 2, 9 },
10215 #define SH_BLTIN_LDUA_Q64 16
10216 { 1, 9 },
10217 #define SH_BLTIN_STUA_L64 17
10218 { 0, 9, 2 },
10219 #define SH_BLTIN_STUA_Q64 18
10220 { 0, 9, 1 },
10221 #define SH_BLTIN_NUM_SHARED_SIGNATURES 19
10222 #define SH_BLTIN_2 19
10223 #define SH_BLTIN_SU 19
10224 { 1, 2 },
10225 #define SH_BLTIN_3 20
10226 #define SH_BLTIN_SUS 20
10227 { 2, 2, 1 },
10228 #define SH_BLTIN_PSSV 21
10229 { 0, 8, 2, 2 },
10230 #define SH_BLTIN_XXUU 22
10231 #define SH_BLTIN_UUUU 22
10232 { 1, 1, 1, 1 },
10233 #define SH_BLTIN_PV 23
10234 { 0, 8 },
10235 #define SH_BLTIN_VP 24
10236 { 8, 0 },
10237 #define SH_BLTIN_UV 25
10238 { 1, 0 },
10239 #define SH_BLTIN_VU 26
10240 { 0, 1 },
10241 };
10242 /* mcmv: operands considered unsigned. */
10243 /* mmulsum_wq, msad_ubq: result considered unsigned long long. */
10244 /* mperm: control value considered unsigned int. */
10245 /* mshalds, mshard, mshards, mshlld, mshlrd: shift count is unsigned int. */
10246 /* mshards_q: returns signed short. */
10247 /* nsb: takes long long arg, returns unsigned char. */
10248 static struct builtin_description bdesc[] =
10249 {
10250 { sh1_builtin_p,
10251 CODE_FOR_sts_fpscr, "__builtin_sh_get_fpscr", SH_BLTIN_UV, 0 },
10252 { sh1_builtin_p,
10253 CODE_FOR_set_fpscr, "__builtin_sh_set_fpscr", SH_BLTIN_VU, 0 },
10254 };
10255
10256 static tree sh_builtin_get_fpscr;
10257 static tree sh_builtin_set_fpscr;
10258
10259 static void
sh_init_builtins(void)10260 sh_init_builtins (void)
10261 {
10262 tree shared[SH_BLTIN_NUM_SHARED_SIGNATURES];
10263 memset (shared, 0, sizeof shared);
10264
10265 for (unsigned int di = 0; di < ARRAY_SIZE (bdesc); ++di)
10266 {
10267 builtin_description* d = &bdesc[di];
10268
10269 if (!d->is_enabled ())
10270 continue;
10271
10272 tree type, arg_type = NULL_TREE;
10273 int signature = d->signature;
10274
10275 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES && shared[signature])
10276 type = shared[signature];
10277 else
10278 {
10279 int has_result = signature_args[signature][0] != 0;
10280 tree args[3];
10281
10282 if (! TARGET_FPU_ANY
10283 && FLOAT_MODE_P (insn_data[d->icode].operand[0].mode))
10284 continue;
10285 for (unsigned int i = 0; i < ARRAY_SIZE (args); i++)
10286 args[i] = NULL_TREE;
10287 for (int i = 3; ; i--)
10288 {
10289 int arg = signature_args[signature][i];
10290 int opno = i - 1 + has_result;
10291
10292 if (arg & 8)
10293 arg_type = ptr_type_node;
10294 else if (arg)
10295 arg_type = (*lang_hooks.types.type_for_mode)
10296 (insn_data[d->icode].operand[opno].mode, (arg & 1));
10297 else if (i)
10298 continue;
10299 else
10300 arg_type = void_type_node;
10301 if (i == 0)
10302 break;
10303 args[i-1] = arg_type;
10304 }
10305 type = build_function_type_list (arg_type, args[0], args[1],
10306 args[2], NULL_TREE);
10307 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES)
10308 shared[signature] = type;
10309 }
10310 d->fndecl =
10311 add_builtin_function (d->name, type, d - bdesc, BUILT_IN_MD,
10312 NULL, NULL_TREE);
10313 /* Recode {sts,set}_fpscr decls for sh_atomic_assign_expand_fenv. */
10314 if (d->icode == CODE_FOR_sts_fpscr)
10315 sh_builtin_get_fpscr = d->fndecl;
10316 else if (d->icode == CODE_FOR_set_fpscr)
10317 sh_builtin_set_fpscr = d->fndecl;
10318 }
10319 }
10320
10321 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
10322
10323 static void
sh_atomic_assign_expand_fenv(tree * hold,tree * clear,tree * update)10324 sh_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
10325 {
10326 const unsigned SH_FE_INVALID = 64;
10327 const unsigned SH_FE_DIVBYZERO = 32;
10328 const unsigned SH_FE_OVERFLOW = 16;
10329 const unsigned SH_FE_UNDERFLOW = 8;
10330 const unsigned SH_FE_INEXACT = 4;
10331 const unsigned HOST_WIDE_INT SH_FE_ALL_EXCEPT = (SH_FE_INVALID
10332 | SH_FE_DIVBYZERO
10333 | SH_FE_OVERFLOW
10334 | SH_FE_UNDERFLOW
10335 | SH_FE_INEXACT);
10336 const unsigned HOST_WIDE_INT SH_FE_EXCEPT_SHIFT = 5;
10337 tree fenv_var, mask, ld_fenv, masked_fenv;
10338 tree new_fenv_var, reload_fenv, restore_fnenv;
10339 tree update_call, atomic_feraiseexcept, hold_fnclex;
10340
10341 if (! TARGET_FPU_ANY)
10342 return;
10343
10344 /* Generate the equivalent of :
10345 unsigned int fenv_var;
10346 fenv_var = __builtin_sh_get_fpscr ();
10347
10348 unsigned int masked_fenv;
10349 masked_fenv = fenv_var & mask;
10350
10351 __builtin_sh_set_fpscr (masked_fenv); */
10352
10353 fenv_var = create_tmp_var_raw (unsigned_type_node);
10354 mask = build_int_cst (unsigned_type_node,
10355 ~((SH_FE_ALL_EXCEPT << SH_FE_EXCEPT_SHIFT)
10356 | SH_FE_ALL_EXCEPT));
10357 ld_fenv = build2 (MODIFY_EXPR, unsigned_type_node,
10358 fenv_var, build_call_expr (sh_builtin_get_fpscr, 0));
10359 masked_fenv = build2 (BIT_AND_EXPR, unsigned_type_node, fenv_var, mask);
10360 hold_fnclex = build_call_expr (sh_builtin_set_fpscr, 1, masked_fenv);
10361 fenv_var = build4 (TARGET_EXPR, unsigned_type_node, fenv_var,
10362 build2 (COMPOUND_EXPR, void_type_node, masked_fenv,
10363 ld_fenv),
10364 NULL_TREE, NULL_TREE);
10365 *hold = build2 (COMPOUND_EXPR, void_type_node, fenv_var, hold_fnclex);
10366
10367 /* Store the value of masked_fenv to clear the exceptions:
10368 __builtin_sh_set_fpscr (masked_fenv); */
10369
10370 *clear = build_call_expr (sh_builtin_set_fpscr, 1, masked_fenv);
10371
10372 /* Generate the equivalent of :
10373 unsigned int new_fenv_var;
10374 new_fenv_var = __builtin_sh_get_fpscr ();
10375
10376 __builtin_sh_set_fpscr (fenv_var);
10377
10378 __atomic_feraiseexcept (new_fenv_var); */
10379
10380 new_fenv_var = create_tmp_var_raw (unsigned_type_node);
10381 reload_fenv = build2 (MODIFY_EXPR, unsigned_type_node, new_fenv_var,
10382 build_call_expr (sh_builtin_get_fpscr, 0));
10383 restore_fnenv = build_call_expr (sh_builtin_set_fpscr, 1, fenv_var);
10384 atomic_feraiseexcept = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT);
10385 update_call = build_call_expr (atomic_feraiseexcept, 1,
10386 fold_convert (integer_type_node,
10387 new_fenv_var));
10388 *update = build2 (COMPOUND_EXPR, void_type_node,
10389 build2 (COMPOUND_EXPR, void_type_node,
10390 reload_fenv, restore_fnenv), update_call);
10391 }
10392
10393 /* Implements target hook vector_mode_supported_p. */
10394 bool
sh_vector_mode_supported_p(machine_mode mode ATTRIBUTE_UNUSED)10395 sh_vector_mode_supported_p (machine_mode mode ATTRIBUTE_UNUSED)
10396 {
10397 return false;
10398 }
10399
10400 bool
sh_frame_pointer_required(void)10401 sh_frame_pointer_required (void)
10402 {
10403 /* If needed override this in other tm.h files to cope with various OS
10404 lossage requiring a frame pointer. */
10405 if (SUBTARGET_FRAME_POINTER_REQUIRED)
10406 return true;
10407
10408 if (crtl->profile)
10409 return true;
10410
10411 return false;
10412 }
10413
10414 /* Implements target hook dwarf_calling_convention. Return an enum
10415 of dwarf_calling_convention. */
10416 int
sh_dwarf_calling_convention(const_tree func)10417 sh_dwarf_calling_convention (const_tree func)
10418 {
10419 if (sh_attr_renesas_p (func))
10420 return DW_CC_GNU_renesas_sh;
10421
10422 return DW_CC_normal;
10423 }
10424
10425 /* Returns the sh builtin decl for CODE. */
10426 static tree
sh_builtin_decl(unsigned code,bool initialize_p ATTRIBUTE_UNUSED)10427 sh_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
10428 {
10429 if (code >= ARRAY_SIZE (bdesc))
10430 return error_mark_node;
10431
10432 if (!bdesc[code].is_enabled ())
10433 return error_mark_node;
10434
10435 return bdesc[code].fndecl;
10436 }
10437
10438 /* Expand an expression EXP that calls a built-in function,
10439 with result going to TARGET if that's convenient
10440 (and in mode MODE if that's convenient).
10441 SUBTARGET may be used as the target for computing one of EXP's operands.
10442 IGNORE is nonzero if the value is to be ignored. */
10443 static rtx
sh_expand_builtin(tree exp,rtx target,rtx subtarget ATTRIBUTE_UNUSED,machine_mode mode ATTRIBUTE_UNUSED,int ignore)10444 sh_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
10445 machine_mode mode ATTRIBUTE_UNUSED, int ignore)
10446 {
10447 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10448 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10449 const struct builtin_description *d = &bdesc[fcode];
10450 enum insn_code icode = d->icode;
10451 int signature = d->signature;
10452 int nop = 0;
10453 rtx op[4];
10454
10455 if (signature_args[signature][0])
10456 {
10457 if (ignore)
10458 return NULL_RTX;
10459
10460 machine_mode tmode = insn_data[icode].operand[0].mode;
10461 if (! target || GET_MODE (target) != tmode
10462 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10463 target = gen_reg_rtx (tmode);
10464 op[nop++] = target;
10465 }
10466 else
10467 target = NULL_RTX;
10468
10469 for (int i = 1; i <= 3; i++, nop++)
10470 {
10471 if (! signature_args[signature][i])
10472 break;
10473 tree arg = CALL_EXPR_ARG (exp, i - 1);
10474 if (arg == error_mark_node)
10475 return const0_rtx;
10476
10477 machine_mode opmode;
10478 tree optype;
10479 if (signature_args[signature][i] & 8)
10480 {
10481 opmode = ptr_mode;
10482 optype = ptr_type_node;
10483 }
10484 else
10485 {
10486 opmode = insn_data[icode].operand[nop].mode;
10487 optype = (*lang_hooks.types.type_for_mode) (opmode, 0);
10488 }
10489
10490 machine_mode argmode = TYPE_MODE (TREE_TYPE (arg));
10491 if (argmode != opmode)
10492 arg = build1 (NOP_EXPR, optype, arg);
10493 op[nop] = expand_expr (arg, NULL_RTX, opmode, EXPAND_NORMAL);
10494 if (! (*insn_data[icode].operand[nop].predicate) (op[nop], opmode))
10495 op[nop] = copy_to_mode_reg (opmode, op[nop]);
10496 }
10497
10498 rtx pat = NULL_RTX;
10499
10500 switch (nop)
10501 {
10502 case 1:
10503 pat = (*insn_data[d->icode].genfun) (op[0]);
10504 break;
10505 case 2:
10506 pat = (*insn_data[d->icode].genfun) (op[0], op[1]);
10507 break;
10508 case 3:
10509 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2]);
10510 break;
10511 case 4:
10512 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2], op[3]);
10513 break;
10514 default:
10515 gcc_unreachable ();
10516 }
10517 if (! pat)
10518 return NULL_RTX;
10519 emit_insn (pat);
10520 return target;
10521 }
10522
10523 /* Implement TARGET_HARD_REGNO_NREGS. On the SH all but the XD regs are
10524 UNITS_PER_WORD bits wide. */
10525
10526 static unsigned int
sh_hard_regno_nregs(unsigned int regno,machine_mode mode)10527 sh_hard_regno_nregs (unsigned int regno, machine_mode mode)
10528 {
10529 if (XD_REGISTER_P (regno))
10530 return CEIL (GET_MODE_SIZE (mode), 2 * UNITS_PER_WORD);
10531 return CEIL (GET_MODE_SIZE (mode), UNITS_PER_WORD);
10532 }
10533
10534 /* Implement TARGET_HARD_REGNO_MODE_OK.
10535
10536 We can allow any mode in any general register. The special registers
10537 only allow SImode. Don't allow any mode in the PR.
10538
10539 We cannot hold DCmode values in the XD registers because alter_reg
10540 handles subregs of them incorrectly. We could work around this by
10541 spacing the XD registers like the DR registers, but this would require
10542 additional memory in every compilation to hold larger register vectors.
10543 We could hold SFmode / SCmode values in XD registers, but that
10544 would require a tertiary reload when reloading from / to memory,
10545 and a secondary reload to reload from / to general regs; that
10546 seems to be a losing proposition.
10547
10548 We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
10549 it won't be ferried through GP registers first. */
10550 static bool
sh_hard_regno_mode_ok(unsigned int regno,machine_mode mode)10551 sh_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
10552 {
10553 if (SPECIAL_REGISTER_P (regno))
10554 return mode == SImode;
10555
10556 if (regno == FPUL_REG)
10557 return (mode == SImode || mode == SFmode);
10558
10559 if (FP_REGISTER_P (regno) && mode == SFmode)
10560 return true;
10561
10562 if (mode == V2SFmode)
10563 {
10564 if (((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 2 == 0)
10565 || GENERAL_REGISTER_P (regno)))
10566 return true;
10567 else
10568 return false;
10569 }
10570
10571 if (mode == V4SFmode)
10572 {
10573 if ((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 4 == 0)
10574 || GENERAL_REGISTER_P (regno))
10575 return true;
10576 else
10577 return false;
10578 }
10579
10580 if (mode == V16SFmode)
10581 return regno == FIRST_XD_REG;
10582
10583 if (FP_REGISTER_P (regno))
10584 {
10585 if (mode == SFmode
10586 || mode == SImode
10587 || ((TARGET_SH2E) && mode == SCmode)
10588 || (((TARGET_FPU_DOUBLE && mode == DFmode) || mode == DCmode)
10589 && ((regno - FIRST_FP_REG) & 1) == 0)
10590 || (TARGET_SH4 && mode == TImode
10591 && ((regno - FIRST_FP_REG) & 3) == 0))
10592 return true;
10593 else
10594 return false;
10595 }
10596
10597 if (XD_REGISTER_P (regno))
10598 return mode == DFmode;
10599
10600 if (regno == PR_REG)
10601 return mode == SImode;
10602
10603 if (regno == FPSCR_REG)
10604 return mode == SImode;
10605
10606 return true;
10607 }
10608
10609 /* Implement TARGET_MODES_TIEABLE_P.
10610
10611 If TARGET_HARD_REGNO_MODE_OK could produce different values for MODE1
10612 and MODE2, for any hard reg, then this must be false for correct output.
10613 That's the case for xd registers: we don't hold SFmode values in
10614 them, so we can't tie an SFmode pseudos with one in another
10615 floating-point mode. */
10616
10617 static bool
sh_modes_tieable_p(machine_mode mode1,machine_mode mode2)10618 sh_modes_tieable_p (machine_mode mode1, machine_mode mode2)
10619 {
10620 return (mode1 == mode2
10621 || (GET_MODE_CLASS (mode1) == GET_MODE_CLASS (mode2)
10622 && (mode1 != SFmode && mode2 != SFmode)));
10623 }
10624
10625 /* Specify the modes required to caller save a given hard regno.
10626 choose_hard_reg_mode chooses mode based on TARGET_HARD_REGNO_MODE_OK
10627 and returns ?Imode for float regs when sh_hard_regno_mode_ok
10628 permits integer modes on them. That makes LRA's split process
10629 unhappy. See PR55212.
10630 */
10631 machine_mode
sh_hard_regno_caller_save_mode(unsigned int regno,unsigned int nregs,machine_mode mode)10632 sh_hard_regno_caller_save_mode (unsigned int regno, unsigned int nregs,
10633 machine_mode mode)
10634 {
10635 if (FP_REGISTER_P (regno)
10636 && (mode == SFmode
10637 || mode == SCmode
10638 || ((mode == DFmode || mode == DCmode)
10639 && ((regno - FIRST_FP_REG) & 1) == 0)))
10640 return mode;
10641
10642 return choose_hard_reg_mode (regno, nregs, false);
10643 }
10644
10645 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
10646 static bool
sh_can_change_mode_class(machine_mode from,machine_mode to,reg_class_t rclass)10647 sh_can_change_mode_class (machine_mode from, machine_mode to,
10648 reg_class_t rclass)
10649 {
10650 /* We want to enable the use of SUBREGs as a means to
10651 VEC_SELECT a single element of a vector. */
10652
10653 /* This effectively disallows using GENERAL_REGS for SFmode vector subregs.
10654 This can be problematic when SFmode vector subregs need to be accessed
10655 on the stack with displacement addressing, as it happens with -O0.
10656 Thus we disallow the mode change for -O0. */
10657 if (to == SFmode && VECTOR_MODE_P (from) && GET_MODE_INNER (from) == SFmode)
10658 return optimize ? !reg_classes_intersect_p (GENERAL_REGS, rclass) : true;
10659
10660 if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
10661 {
10662 if (TARGET_LITTLE_ENDIAN)
10663 {
10664 if (GET_MODE_SIZE (to) < 8 || GET_MODE_SIZE (from) < 8)
10665 return !reg_classes_intersect_p (DF_REGS, rclass);
10666 }
10667 else
10668 {
10669 if (GET_MODE_SIZE (from) < 8)
10670 return !reg_classes_intersect_p (DF_REGS, rclass);
10671 }
10672 }
10673 return true;
10674 }
10675
10676 /* Return true if registers in machine mode MODE will likely be
10677 allocated to registers in small register classes. */
10678 bool
sh_small_register_classes_for_mode_p(machine_mode mode ATTRIBUTE_UNUSED)10679 sh_small_register_classes_for_mode_p (machine_mode mode ATTRIBUTE_UNUSED)
10680 {
10681 return true;
10682 }
10683
10684 /* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times
10685 that label is used. */
10686 void
sh_mark_label(rtx address,int nuses)10687 sh_mark_label (rtx address, int nuses)
10688 {
10689 if (GOTOFF_P (address))
10690 {
10691 /* Extract the label or symbol. */
10692 address = XEXP (address, 0);
10693 if (GET_CODE (address) == PLUS)
10694 address = XEXP (address, 0);
10695 address = XVECEXP (address, 0, 0);
10696 }
10697 if (GET_CODE (address) == LABEL_REF
10698 && LABEL_P (XEXP (address, 0)))
10699 LABEL_NUSES (XEXP (address, 0)) += nuses;
10700 }
10701
10702 /* Compute extra cost of moving data between one register class
10703 and another.
10704
10705 If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
10706 uses this information. Hence, the general register <-> floating point
10707 register information here is not used for SFmode. */
10708 static int
sh_register_move_cost(machine_mode mode,reg_class_t srcclass,reg_class_t dstclass)10709 sh_register_move_cost (machine_mode mode,
10710 reg_class_t srcclass, reg_class_t dstclass)
10711 {
10712 if (dstclass == T_REGS || dstclass == PR_REGS)
10713 return 10;
10714
10715 if (dstclass == MAC_REGS && srcclass == MAC_REGS)
10716 return 4;
10717
10718 if (mode == SImode && TARGET_FMOVD
10719 && REGCLASS_HAS_FP_REG (srcclass)
10720 && REGCLASS_HAS_FP_REG (dstclass))
10721 return 4;
10722
10723 if (REGCLASS_HAS_FP_REG (dstclass) && srcclass == T_REGS)
10724 return ((TARGET_HARD_SH4 && !optimize_size) ? 10 : 7);
10725
10726 if ((REGCLASS_HAS_FP_REG (dstclass) && srcclass == MAC_REGS)
10727 || (dstclass == MAC_REGS && REGCLASS_HAS_FP_REG (srcclass)))
10728 return 9;
10729
10730 if ((REGCLASS_HAS_FP_REG (dstclass)
10731 && REGCLASS_HAS_GENERAL_REG (srcclass))
10732 || (REGCLASS_HAS_GENERAL_REG (dstclass)
10733 && REGCLASS_HAS_FP_REG (srcclass)))
10734 {
10735 /* Discourage trying to use fp regs for a pointer. This also
10736 discourages fp regs with SImode because Pmode is an alias
10737 of SImode on this target. See PR target/48596. */
10738 int addend = (mode == Pmode) ? 40 : 0;
10739
10740 return ((TARGET_FMOVD ? 8 : 12) + addend)
10741 * ((GET_MODE_SIZE (mode) + 7) / 8U);
10742 }
10743
10744 if ((dstclass == FPUL_REGS
10745 && REGCLASS_HAS_GENERAL_REG (srcclass))
10746 || (srcclass == FPUL_REGS
10747 && REGCLASS_HAS_GENERAL_REG (dstclass)))
10748 return 5;
10749
10750 if ((dstclass == FPUL_REGS
10751 && (srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS))
10752 || (srcclass == FPUL_REGS
10753 && (dstclass == PR_REGS || dstclass == MAC_REGS)))
10754 return 7;
10755
10756 if ((srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
10757 || (dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
10758 return 4;
10759
10760 if (TARGET_FMOVD
10761 && ! REGCLASS_HAS_GENERAL_REG (srcclass)
10762 && ! REGCLASS_HAS_GENERAL_REG (dstclass))
10763 return 2 * ((GET_MODE_SIZE (mode) + 7) / 8U);
10764
10765 return 2 * ((GET_MODE_SIZE (mode) + 3) / 4U);
10766 }
10767
10768 static rtx
emit_load_ptr(rtx reg,rtx addr)10769 emit_load_ptr (rtx reg, rtx addr)
10770 {
10771 rtx mem = gen_const_mem (ptr_mode, addr);
10772
10773 if (Pmode != ptr_mode)
10774 mem = gen_rtx_SIGN_EXTEND (Pmode, mem);
10775 return emit_move_insn (reg, mem);
10776 }
10777
10778 static void
sh_output_mi_thunk(FILE * file,tree thunk_fndecl ATTRIBUTE_UNUSED,HOST_WIDE_INT delta,HOST_WIDE_INT vcall_offset,tree function)10779 sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
10780 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
10781 tree function)
10782 {
10783 CUMULATIVE_ARGS cum;
10784 int structure_value_byref = 0;
10785 rtx this_rtx, this_value, sibcall, funexp;
10786 rtx_insn *insns;
10787 tree funtype = TREE_TYPE (function);
10788 int simple_add = CONST_OK_FOR_ADD (delta);
10789 int did_load = 0;
10790 rtx scratch0, scratch1, scratch2;
10791
10792 reload_completed = 1;
10793 epilogue_completed = 1;
10794 crtl->uses_only_leaf_regs = 1;
10795
10796 emit_note (NOTE_INSN_PROLOGUE_END);
10797
10798 /* Find the "this" pointer. We have such a wide range of ABIs for the
10799 SH that it's best to do this completely machine independently.
10800 "this" is passed as first argument, unless a structure return pointer
10801 comes first, in which case "this" comes second. */
10802 INIT_CUMULATIVE_ARGS (cum, funtype, NULL_RTX, 0, 1);
10803 #ifndef PCC_STATIC_STRUCT_RETURN
10804 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
10805 structure_value_byref = 1;
10806 #endif /* not PCC_STATIC_STRUCT_RETURN */
10807 if (structure_value_byref && sh_struct_value_rtx (function, 0) == 0)
10808 {
10809 tree ptype = build_pointer_type (TREE_TYPE (funtype));
10810
10811 sh_function_arg_advance (pack_cumulative_args (&cum), Pmode, ptype, true);
10812 }
10813 this_rtx
10814 = sh_function_arg (pack_cumulative_args (&cum), Pmode, ptr_type_node, true);
10815
10816 /* For SHcompact, we only have r0 for a scratch register: r1 is the
10817 static chain pointer (even if you can't have nested virtual functions
10818 right now, someone might implement them sometime), and the rest of the
10819 registers are used for argument passing, are callee-saved, or reserved. */
10820 /* We need to check call_used_regs / fixed_regs in case -fcall_saved-reg /
10821 -ffixed-reg has been used. */
10822 if (! call_used_regs[0] || fixed_regs[0])
10823 error ("r0 needs to be available as a call-clobbered register");
10824 scratch0 = scratch1 = scratch2 = gen_rtx_REG (Pmode, 0);
10825
10826 {
10827 if (call_used_regs[1] && ! fixed_regs[1])
10828 scratch1 = gen_rtx_REG (ptr_mode, 1);
10829 /* N.B., if not TARGET_HITACHI, register 2 is used to pass the pointer
10830 pointing where to return struct values. */
10831 if (call_used_regs[3] && ! fixed_regs[3])
10832 scratch2 = gen_rtx_REG (Pmode, 3);
10833 }
10834
10835 this_value = plus_constant (Pmode, this_rtx, delta);
10836 if (vcall_offset
10837 && (simple_add || scratch0 != scratch1)
10838 && strict_memory_address_p (ptr_mode, this_value))
10839 {
10840 emit_load_ptr (scratch0, this_value);
10841 did_load = 1;
10842 }
10843
10844 if (!delta)
10845 ; /* Do nothing. */
10846 else if (simple_add)
10847 emit_move_insn (this_rtx, this_value);
10848 else
10849 {
10850 emit_move_insn (scratch1, GEN_INT (delta));
10851 emit_insn (gen_add2_insn (this_rtx, scratch1));
10852 }
10853
10854 if (vcall_offset)
10855 {
10856 rtx offset_addr;
10857
10858 if (!did_load)
10859 emit_load_ptr (scratch0, this_rtx);
10860
10861 offset_addr = plus_constant (Pmode, scratch0, vcall_offset);
10862 if (strict_memory_address_p (ptr_mode, offset_addr))
10863 ; /* Do nothing. */
10864 else if (scratch0 != scratch1)
10865 {
10866 /* scratch0 != scratch1, and we have indexed loads. Get better
10867 schedule by loading the offset into r1 and using an indexed
10868 load - then the load of r1 can issue before the load from
10869 (this_rtx + delta) finishes. */
10870 emit_move_insn (scratch1, GEN_INT (vcall_offset));
10871 offset_addr = gen_rtx_PLUS (Pmode, scratch0, scratch1);
10872 }
10873 else if (CONST_OK_FOR_ADD (vcall_offset))
10874 {
10875 emit_insn (gen_add2_insn (scratch0, GEN_INT (vcall_offset)));
10876 offset_addr = scratch0;
10877 }
10878 else if (scratch0 != scratch1)
10879 {
10880 emit_move_insn (scratch1, GEN_INT (vcall_offset));
10881 emit_insn (gen_add2_insn (scratch0, scratch1));
10882 offset_addr = scratch0;
10883 }
10884 else
10885 gcc_unreachable (); /* FIXME */
10886 emit_load_ptr (scratch0, offset_addr);
10887
10888 if (Pmode != ptr_mode)
10889 scratch0 = gen_rtx_TRUNCATE (ptr_mode, scratch0);
10890 emit_insn (gen_add2_insn (this_rtx, scratch0));
10891 }
10892
10893 /* Generate a tail call to the target function. */
10894 if (! TREE_USED (function))
10895 {
10896 assemble_external (function);
10897 TREE_USED (function) = 1;
10898 }
10899 funexp = XEXP (DECL_RTL (function), 0);
10900 /* If the function is overridden, so is the thunk, hence we don't
10901 need GOT addressing even if this is a public symbol. */
10902 #if 0
10903 if (TARGET_SH1 && ! flag_weak)
10904 sibcall = gen_sibcalli_thunk (funexp, const0_rtx);
10905 else
10906 #endif
10907 if (TARGET_SH2 && flag_pic)
10908 {
10909 if (TARGET_FDPIC)
10910 {
10911 sibcall = gen_sibcall_pcrel_fdpic (funexp, const0_rtx);
10912 XEXP (XVECEXP (sibcall, 0, 3), 0) = scratch2;
10913 }
10914 else
10915 {
10916 sibcall = gen_sibcall_pcrel (funexp, const0_rtx);
10917 XEXP (XVECEXP (sibcall, 0, 2), 0) = scratch2;
10918 }
10919 }
10920 else
10921 {
10922 emit_move_insn (scratch2, funexp);
10923 funexp = gen_rtx_MEM (FUNCTION_MODE, scratch2);
10924 sibcall = gen_sibcall (funexp, const0_rtx, NULL_RTX);
10925 }
10926 sibcall = emit_call_insn (sibcall);
10927 SIBLING_CALL_P (sibcall) = 1;
10928 use_reg (&CALL_INSN_FUNCTION_USAGE (sibcall), this_rtx);
10929 emit_barrier ();
10930
10931 /* Run just enough of rest_of_compilation to do scheduling and get
10932 the insns emitted. Note that use_thunk calls
10933 assemble_start_function and assemble_end_function. */
10934
10935 insns = get_insns ();
10936
10937 if (optimize > 0)
10938 {
10939 if (! cfun->cfg)
10940 init_flow (cfun);
10941 split_all_insns_noflow ();
10942 }
10943
10944 sh_reorg ();
10945 shorten_branches (insns);
10946 final_start_function (insns, file, 1);
10947 final (insns, file, 1);
10948 final_end_function ();
10949
10950 reload_completed = 0;
10951 epilogue_completed = 0;
10952 }
10953
10954 /* Return an RTX pair for the address and call site label of a function
10955 NAME of kind KIND, placing the result in TARGET if not NULL. For
10956 SFUNC_STATIC, if FDPIC, the LAB member of result will be set to
10957 (const_int 0) if jsr should be used, or a label_ref if bsrf should
10958 be used. For FDPIC, both SFUNC_GOT and SFUNC_STATIC will return the
10959 address of the function itself, not a function descriptor, so they
10960 can only be used with functions not using the FDPIC register that
10961 are known to be called directory without a PLT entry. */
10962
10963 function_symbol_result
function_symbol(rtx target,const char * name,sh_function_kind kind)10964 function_symbol (rtx target, const char *name, sh_function_kind kind)
10965 {
10966 /* If this is not an ordinary function, the name usually comes from a
10967 string literal or an sprintf buffer. Make sure we use the same
10968 string consistently, so that cse will be able to unify address loads. */
10969 if (kind != FUNCTION_ORDINARY)
10970 name = IDENTIFIER_POINTER (get_identifier (name));
10971 rtx sym = gen_rtx_SYMBOL_REF (Pmode, name);
10972 rtx lab = const0_rtx;
10973 SYMBOL_REF_FLAGS (sym) = SYMBOL_FLAG_FUNCTION;
10974 if (flag_pic)
10975 switch (kind)
10976 {
10977 case FUNCTION_ORDINARY:
10978 break;
10979 case SFUNC_GOT:
10980 {
10981 rtx reg = target ? target : gen_reg_rtx (Pmode);
10982
10983 emit_insn (gen_symGOT2reg (reg, sym));
10984 sym = reg;
10985 break;
10986 }
10987 case SFUNC_STATIC:
10988 {
10989 rtx reg = target ? target : gen_reg_rtx (Pmode);
10990
10991 if (TARGET_FDPIC)
10992 {
10993 /* We use PC-relative calls, since GOTOFF can only refer
10994 to writable data. This works along with sh_sfunc_call. */
10995 lab = PATTERN (gen_call_site ());
10996 emit_insn (gen_sym_label2reg (reg, sym, lab));
10997 }
10998 else
10999 {
11000 /* ??? To allow cse to work, we use GOTOFF relocations.
11001 we could add combiner patterns to transform this into
11002 straight pc-relative calls with sym2PIC / bsrf when
11003 label load and function call are still 1:1 and in the
11004 same basic block during combine. */
11005 emit_insn (gen_symGOTOFF2reg (reg, sym));
11006 }
11007
11008 sym = reg;
11009 break;
11010 }
11011 }
11012 if (target && sym != target)
11013 {
11014 emit_move_insn (target, sym);
11015 return function_symbol_result (target, lab);
11016 }
11017 return function_symbol_result (sym, lab);
11018 }
11019
11020 /* Find the number of the first general purpose register in S that
11021 is not set. */
11022 static int
scavenge_reg(HARD_REG_SET * s)11023 scavenge_reg (HARD_REG_SET *s)
11024 {
11025 for (int r = FIRST_GENERAL_REG; r <= LAST_GENERAL_REG; r++)
11026 if (TEST_HARD_REG_BIT (*s, r))
11027 return r;
11028 return -1;
11029 }
11030
11031 rtx
sh_get_pr_initial_val(void)11032 sh_get_pr_initial_val (void)
11033 {
11034 /* If we haven't finished rtl generation, there might be a nonlocal label
11035 that we haven't seen yet.
11036 ??? get_hard_reg_initial_val fails if it is called after register
11037 allocation has started, unless it has been called before for the
11038 same register. And even then, we end in trouble if we didn't use
11039 the register in the same basic block before. So call
11040 get_hard_reg_initial_val now and wrap it in an unspec if we might
11041 need to replace it. */
11042 /* ??? We also must do this for TARGET_SH1 in general, because otherwise
11043 combine can put the pseudo returned by get_hard_reg_initial_val into
11044 instructions that need a general purpose registers, which will fail to
11045 be recognized when the pseudo becomes allocated to PR. */
11046 rtx val = get_hard_reg_initial_val (Pmode, PR_REG);
11047 return gen_rtx_UNSPEC (SImode, gen_rtvec (1, val), UNSPEC_RA);
11048 }
11049
11050 bool
sh_expand_t_scc(rtx operands[])11051 sh_expand_t_scc (rtx operands[])
11052 {
11053 enum rtx_code code = GET_CODE (operands[1]);
11054 rtx target = operands[0];
11055 rtx op0 = operands[2];
11056 rtx op1 = operands[3];
11057 rtx result = target;
11058
11059 if (!REG_P (op0) || REGNO (op0) != T_REG
11060 || !CONST_INT_P (op1))
11061 return false;
11062 if (!REG_P (result))
11063 result = gen_reg_rtx (SImode);
11064 HOST_WIDE_INT val = INTVAL (op1);
11065 if ((code == EQ && val == 1) || (code == NE && val == 0))
11066 emit_insn (gen_movt (result, get_t_reg_rtx ()));
11067 else if ((code == EQ && val == 0) || (code == NE && val == 1))
11068 emit_insn (gen_movnegt (result, get_t_reg_rtx ()));
11069 else if (code == EQ || code == NE)
11070 emit_insn (gen_move_insn (result, GEN_INT (code == NE)));
11071 else
11072 return false;
11073 if (result != target)
11074 emit_move_insn (target, result);
11075 return true;
11076 }
11077
11078 /* INSN is an sfunc; return the rtx that describes the address used. */
11079 static rtx
extract_sfunc_addr(rtx insn)11080 extract_sfunc_addr (rtx insn)
11081 {
11082 rtx pattern = PATTERN (insn);
11083 const int len = XVECLEN (pattern, 0);
11084 for (int i = 0; i < len; i++)
11085 {
11086 rtx part = XVECEXP (pattern, 0, i);
11087 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == Pmode
11088 && GENERAL_REGISTER_P (true_regnum (XEXP (part, 0))))
11089 return XEXP (part, 0);
11090 }
11091 gcc_assert (GET_CODE (XVECEXP (pattern, 0, 0)) == UNSPEC_VOLATILE);
11092 return XVECEXP (XVECEXP (pattern, 0, 0), 0, 1);
11093 }
11094
11095 /* Verify that the register in use_sfunc_addr still agrees with the address
11096 used in the sfunc. This prevents fill_slots_from_thread from changing
11097 use_sfunc_addr.
11098 INSN is the use_sfunc_addr instruction, and REG is the register it
11099 guards. */
11100 bool
check_use_sfunc_addr(rtx_insn * insn,rtx reg)11101 check_use_sfunc_addr (rtx_insn *insn, rtx reg)
11102 {
11103 /* Search for the sfunc. It should really come right after INSN. */
11104 while ((insn = NEXT_INSN (insn)))
11105 {
11106 if (LABEL_P (insn) || JUMP_P (insn))
11107 break;
11108 if (! INSN_P (insn))
11109 continue;
11110
11111 if (rtx_sequence *seq = dyn_cast<rtx_sequence *> (PATTERN (insn)))
11112 insn = seq->insn (0);
11113 if (GET_CODE (PATTERN (insn)) != PARALLEL
11114 || get_attr_type (insn) != TYPE_SFUNC)
11115 continue;
11116 return rtx_equal_p (extract_sfunc_addr (insn), reg);
11117 }
11118 gcc_unreachable ();
11119 }
11120
11121 /* This function returns a constant rtx that represents 2**15 / pi in
11122 SFmode. It's used to scale a fixed-point signed 16.16-bit fraction
11123 of a full circle back to an SFmode value, i.e. 0x10000 maps to 2*pi. */
11124 static GTY(()) rtx sh_fsca_sf2int_rtx;
11125
11126 rtx
sh_fsca_sf2int(void)11127 sh_fsca_sf2int (void)
11128 {
11129 if (! sh_fsca_sf2int_rtx)
11130 {
11131 REAL_VALUE_TYPE rv;
11132
11133 real_from_string (&rv, "10430.378350470453");
11134 sh_fsca_sf2int_rtx = const_double_from_real_value (rv, SFmode);
11135 }
11136
11137 return sh_fsca_sf2int_rtx;
11138 }
11139
11140 /* This function returns a constant rtx that represents pi / 2**15 in
11141 SFmode. It's used to scale SFmode angles, in radians, to a
11142 fixed-point signed 16.16-bit fraction of a full circle, i.e. 2*pi
11143 maps to 0x10000. */
11144 static GTY(()) rtx sh_fsca_int2sf_rtx;
11145
11146 rtx
sh_fsca_int2sf(void)11147 sh_fsca_int2sf (void)
11148 {
11149 if (! sh_fsca_int2sf_rtx)
11150 {
11151 REAL_VALUE_TYPE rv;
11152
11153 real_from_string (&rv, "9.587379924285257e-5");
11154 sh_fsca_int2sf_rtx = const_double_from_real_value (rv, SFmode);
11155 }
11156
11157 return sh_fsca_int2sf_rtx;
11158 }
11159
11160 /* Initialize the CUMULATIVE_ARGS structure. */
11161 void
sh_init_cumulative_args(CUMULATIVE_ARGS * pcum,tree fntype,rtx libname ATTRIBUTE_UNUSED,tree fndecl,signed int n_named_args,machine_mode mode)11162 sh_init_cumulative_args (CUMULATIVE_ARGS * pcum,
11163 tree fntype,
11164 rtx libname ATTRIBUTE_UNUSED,
11165 tree fndecl,
11166 signed int n_named_args,
11167 machine_mode mode)
11168 {
11169 pcum->arg_count [(int) SH_ARG_FLOAT] = 0;
11170 pcum->free_single_fp_reg = 0;
11171 pcum->outgoing = n_named_args != -1;
11172
11173 /* FIXME: Should we check TARGET_HITACHI here ??? */
11174 pcum->renesas_abi = sh_attr_renesas_p (fntype);
11175
11176 if (fntype)
11177 {
11178 pcum->force_mem = ((TARGET_HITACHI || pcum->renesas_abi)
11179 && aggregate_value_p (TREE_TYPE (fntype), fndecl));
11180 pcum->prototype_p = prototype_p (fntype);
11181 pcum->arg_count [(int) SH_ARG_INT] = false;
11182 }
11183 else
11184 {
11185 pcum->arg_count [(int) SH_ARG_INT] = 0;
11186 pcum->prototype_p = false;
11187 if (mode != VOIDmode)
11188 {
11189 /* If the default ABI is the Renesas ABI then all library
11190 calls must assume that the library will be using the
11191 Renesas ABI. So if the function would return its result
11192 in memory then we must force the address of this memory
11193 block onto the stack. Ideally we would like to call
11194 targetm.calls.return_in_memory() here but we do not have
11195 the TYPE or the FNDECL available so we synthesize the
11196 contents of that function as best we can. */
11197 pcum->force_mem =
11198 (TARGET_DEFAULT & MASK_HITACHI)
11199 && (mode == BLKmode
11200 || (GET_MODE_SIZE (mode) > 4
11201 && !(mode == DFmode
11202 && TARGET_FPU_DOUBLE)));
11203 }
11204 else
11205 pcum->force_mem = false;
11206 }
11207 }
11208
11209 rtx
sh_gen_truncate(machine_mode mode,rtx x,int need_sign_ext)11210 sh_gen_truncate (machine_mode mode, rtx x, int need_sign_ext)
11211 {
11212 enum rtx_code code = TRUNCATE;
11213
11214 if (GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND)
11215 {
11216 rtx inner = XEXP (x, 0);
11217 machine_mode inner_mode = GET_MODE (inner);
11218
11219 if (inner_mode == mode)
11220 return inner;
11221 else if (GET_MODE_SIZE (inner_mode) >= GET_MODE_SIZE (mode))
11222 x = inner;
11223 else if (GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (mode)
11224 && (! need_sign_ext || GET_CODE (x) == SIGN_EXTEND))
11225 {
11226 code = GET_CODE (x);
11227 x = inner;
11228 }
11229 }
11230 return gen_rtx_fmt_e (code, mode, x);
11231 }
11232
11233 /* Load and store depend on the highpart of the address. However,
11234 set_attr_alternative does not give well-defined results before reload,
11235 so we must look at the rtl ourselves to see if any of the feeding
11236 registers is used in a memref.
11237
11238 Return true iff INSN contains a MEM. */
11239 bool
sh_contains_memref_p(rtx insn)11240 sh_contains_memref_p (rtx insn)
11241 {
11242 subrtx_iterator::array_type array;
11243 FOR_EACH_SUBRTX (iter, array, PATTERN (insn), NONCONST)
11244 if (MEM_P (*iter))
11245 return true;
11246 return false;
11247 }
11248
11249 /* Return true iff INSN loads a banked register. */
11250 bool
sh_loads_bankedreg_p(rtx insn)11251 sh_loads_bankedreg_p (rtx insn)
11252 {
11253 if (GET_CODE (PATTERN (insn)) == SET)
11254 {
11255 rtx op = SET_DEST (PATTERN(insn));
11256 if (REG_P (op) && BANKED_REGISTER_P (REGNO (op)))
11257 return true;
11258 }
11259
11260 return false;
11261 }
11262
11263 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
11264 static reg_class_t
sh_preferred_reload_class(rtx x ATTRIBUTE_UNUSED,reg_class_t rclass)11265 sh_preferred_reload_class (rtx x ATTRIBUTE_UNUSED, reg_class_t rclass)
11266 {
11267 return rclass;
11268 }
11269
11270 /* Implement TARGET_SECONDARY_RELOAD. */
11271 static reg_class_t
sh_secondary_reload(bool in_p,rtx x,reg_class_t rclass_i,machine_mode mode,secondary_reload_info * sri)11272 sh_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
11273 machine_mode mode, secondary_reload_info *sri)
11274 {
11275 enum reg_class rclass = (enum reg_class) rclass_i;
11276
11277 if (MEM_P (x) && GET_CODE (XEXP (x, 0)) == PLUS
11278 && REG_P (XEXP (XEXP (x, 0), 0))
11279 && REGNO (XEXP (XEXP (x, 0), 0)) == GBR_REG)
11280 return rclass == R0_REGS ? NO_REGS : R0_REGS;
11281
11282 if (MEM_P (x) && REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) == GBR_REG)
11283 return rclass == R0_REGS ? NO_REGS : R0_REGS;
11284
11285 if (REG_P (x) && REGNO (x) == GBR_REG)
11286 return NO_REGS;
11287
11288 if (in_p)
11289 {
11290 if (REGCLASS_HAS_FP_REG (rclass)
11291 && immediate_operand ((x), mode)
11292 && ! ((fp_zero_operand (x) || fp_one_operand (x)) && mode == SFmode))
11293 switch (mode)
11294 {
11295 case E_SFmode:
11296 sri->icode = CODE_FOR_reload_insf__frn;
11297 return NO_REGS;
11298 case E_DFmode:
11299 sri->icode = CODE_FOR_reload_indf__frn;
11300 return NO_REGS;
11301 case E_SImode:
11302 /* ??? If we knew that we are in the appropriate mode -
11303 single precision - we could use a reload pattern directly. */
11304 return FPUL_REGS;
11305 default:
11306 abort ();
11307 }
11308 if (rclass == FPUL_REGS
11309 && ((REG_P (x) && (REGNO (x) == MACL_REG || REGNO (x) == MACH_REG
11310 || REGNO (x) == T_REG))
11311 || GET_CODE (x) == PLUS))
11312 return GENERAL_REGS;
11313 if (rclass == FPUL_REGS && immediate_operand (x, mode))
11314 {
11315 if (satisfies_constraint_I08 (x) || fp_zero_operand (x))
11316 return GENERAL_REGS;
11317 else if (mode == SFmode)
11318 return FP_REGS;
11319 sri->icode = CODE_FOR_reload_insi__i_fpul;
11320 return NO_REGS;
11321 }
11322 if (rclass == FPSCR_REGS
11323 && ((REG_P (x) && REGNO (x) >= FIRST_PSEUDO_REGISTER)
11324 || (MEM_P (x) && GET_CODE (XEXP (x, 0)) == PLUS)))
11325 return GENERAL_REGS;
11326 } /* end of input-only processing. */
11327
11328 if (((REGCLASS_HAS_FP_REG (rclass)
11329 && (REG_P (x)
11330 && (GENERAL_OR_AP_REGISTER_P (REGNO (x))
11331 || (FP_REGISTER_P (REGNO (x)) && mode == SImode
11332 && TARGET_FMOVD))))
11333 || (REGCLASS_HAS_GENERAL_REG (rclass)
11334 && REG_P (x)
11335 && FP_REGISTER_P (REGNO (x))))
11336 && (mode == SFmode || mode == SImode))
11337 return FPUL_REGS;
11338 if ((rclass == FPUL_REGS
11339 || (REGCLASS_HAS_FP_REG (rclass) && mode == SImode))
11340 && (MEM_P (x)
11341 || (REG_P (x)
11342 && (REGNO (x) >= FIRST_PSEUDO_REGISTER
11343 || REGNO (x) == T_REG
11344 || system_reg_operand (x, VOIDmode)))))
11345 {
11346 if (rclass == FPUL_REGS)
11347 return GENERAL_REGS;
11348 return NO_REGS; // LRA wants NO_REGS here, it used to be FPUL_REGS;
11349 }
11350
11351 if ((rclass == MAC_REGS || rclass == PR_REGS)
11352 && REG_P (x) && ! GENERAL_REGISTER_P (REGNO (x))
11353 && rclass != REGNO_REG_CLASS (REGNO (x)))
11354 return GENERAL_REGS;
11355
11356 /* If here fall back to loading FPUL register through general registers.
11357 This case can happen when movsi_ie insn is picked initially to
11358 load/store the FPUL register from/to another register, and then the
11359 other register is allocated on the stack. */
11360 if (rclass == FPUL_REGS && true_regnum (x) == -1)
11361 return GENERAL_REGS;
11362
11363 /* Force mov.b / mov.w displacement addressing insn to use R0 as
11364 the other operand.
11365 On SH2A could also just leave it alone here, which would result in a
11366 4 byte move insn being generated instead. However, for this to work
11367 the insns must have the appropriate alternatives. */
11368 if ((mode == QImode || mode == HImode) && rclass != R0_REGS
11369 && satisfies_constraint_Sdd (x)
11370 && sh_disp_addr_displacement (x)
11371 <= sh_max_mov_insn_displacement (mode, false))
11372 return R0_REGS;
11373
11374 /* When reload is trying to address a QImode or HImode subreg on the stack,
11375 force any subreg byte into R0_REGS, as this is going to become a
11376 displacement address.
11377 We could restrict this to SUBREG_BYTE (x) > 0, but if the actual reg
11378 is on the stack, the memref to it might already require a displacement
11379 and that has to be added to the final address. At this point we don't
11380 know the cumulative displacement so we assume the worst case. */
11381 if ((mode == QImode || mode == HImode) && rclass != R0_REGS
11382 && GET_CODE (x) == SUBREG && true_regnum (x) == -1)
11383 return R0_REGS;
11384
11385 return NO_REGS;
11386 }
11387
11388 /* Return true if SUBST can't safely replace its equivalent during RA. */
11389 static bool
sh_cannot_substitute_mem_equiv_p(rtx)11390 sh_cannot_substitute_mem_equiv_p (rtx)
11391 {
11392 /* If SUBST is mem[base+index] or QI/HImode mem[base+disp], the insn
11393 uses R0 and may cause spill failure when R0 is already used.
11394 We have to return true for that case at least.
11395 Moreover SH has strong R0 parity and also have not enough numbers of
11396 the hard registers to make the equiv substitution win in the size
11397 and the speed on average working sets. The pseudos produced to
11398 hold the equiv values can't get good hard registers for bad cases
11399 and end up memory save/restore insns which make the code worse. */
11400 return true;
11401 }
11402
11403 /* Implement TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT. */
11404 static bool
sh_legitimize_address_displacement(rtx * offset1,rtx * offset2,poly_int64 orig_offset,machine_mode mode)11405 sh_legitimize_address_displacement (rtx *offset1, rtx *offset2,
11406 poly_int64 orig_offset,
11407 machine_mode mode)
11408 {
11409 if ((TARGET_FPU_DOUBLE && mode == DFmode)
11410 || (TARGET_SH2E && mode == SFmode))
11411 return false;
11412
11413 struct disp_adjust adj = sh_find_mov_disp_adjust (mode, orig_offset);
11414 if (adj.offset_adjust != NULL_RTX && adj.mov_disp != NULL_RTX)
11415 {
11416 *offset1 = adj.offset_adjust;
11417 *offset2 = adj.mov_disp;
11418 return true;
11419 }
11420
11421 return false;
11422 }
11423
11424 /* Return true if movsf insn should be splited with an additional
11425 register. */
11426 bool
sh_movsf_ie_ra_split_p(rtx op0,rtx op1,rtx op2)11427 sh_movsf_ie_ra_split_p (rtx op0, rtx op1, rtx op2)
11428 {
11429 /* op0 == op1 */
11430 if (rtx_equal_p (op0, op1))
11431 return true;
11432 /* fy, FQ, reg */
11433 if (GET_CODE (op1) == CONST_DOUBLE
11434 && ! satisfies_constraint_G (op1)
11435 && ! satisfies_constraint_H (op1)
11436 && REG_P (op0)
11437 && REG_P (op2))
11438 return true;
11439 /* f, r, y */
11440 if (REG_P (op0) && FP_REGISTER_P (REGNO (op0))
11441 && REG_P (op1) && GENERAL_REGISTER_P (REGNO (op1))
11442 && REG_P (op2) && (REGNO (op2) == FPUL_REG))
11443 return true;
11444 /* r, f, y */
11445 if (REG_P (op1) && FP_REGISTER_P (REGNO (op1))
11446 && REG_P (op0) && GENERAL_REGISTER_P (REGNO (op0))
11447 && REG_P (op2) && (REGNO (op2) == FPUL_REG))
11448 return true;
11449
11450 return false;
11451 }
11452
11453 static void
sh_conditional_register_usage(void)11454 sh_conditional_register_usage (void)
11455 {
11456 for (int regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++)
11457 if (! VALID_REGISTER_P (regno))
11458 fixed_regs[regno] = call_used_regs[regno] = 1;
11459 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */
11460 if (flag_pic)
11461 {
11462 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
11463 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
11464 }
11465 if (TARGET_FDPIC)
11466 {
11467 fixed_regs[PIC_REG] = 1;
11468 call_used_regs[PIC_REG] = 1;
11469 call_really_used_regs[PIC_REG] = 1;
11470 }
11471 /* Renesas saves and restores mac registers on call. */
11472 if (TARGET_HITACHI && ! TARGET_NOMACSAVE)
11473 {
11474 call_really_used_regs[MACH_REG] = 0;
11475 call_really_used_regs[MACL_REG] = 0;
11476 }
11477
11478 for (int regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++)
11479 if (! fixed_regs[regno] && call_really_used_regs[regno])
11480 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno);
11481
11482 call_really_used_regs[FPSCR_MODES_REG] = 0;
11483 call_really_used_regs[FPSCR_STAT_REG] = 0;
11484 }
11485
11486 /* Implement TARGET_LEGITIMATE_CONSTANT_P
11487
11488 can_store_by_pieces constructs VOIDmode CONST_DOUBLEs. */
11489 static bool
sh_legitimate_constant_p(machine_mode mode,rtx x)11490 sh_legitimate_constant_p (machine_mode mode, rtx x)
11491 {
11492 if (SH_OFFSETS_MUST_BE_WITHIN_SECTIONS_P)
11493 {
11494 rtx base, offset;
11495 split_const (x, &base, &offset);
11496
11497 if (GET_CODE (base) == SYMBOL_REF
11498 && !offset_within_block_p (base, INTVAL (offset)))
11499 return false;
11500 }
11501
11502 if (TARGET_FDPIC
11503 && (SYMBOLIC_CONST_P (x)
11504 || (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
11505 && SYMBOLIC_CONST_P (XEXP (XEXP (x, 0), 0)))))
11506 return false;
11507
11508 return GET_CODE (x) != CONST_DOUBLE
11509 || mode == DFmode || mode == SFmode
11510 || mode == DImode || GET_MODE (x) == VOIDmode;
11511 }
11512
11513 enum sh_divide_strategy_e sh_div_strategy = SH_DIV_STRATEGY_DEFAULT;
11514
11515 static void
sh_init_sync_libfuncs(void)11516 sh_init_sync_libfuncs (void)
11517 {
11518 init_sync_libfuncs (UNITS_PER_WORD);
11519 }
11520
11521 /* Return true if it is appropriate to emit `ret' instructions in the
11522 body of a function. */
11523 bool
sh_can_use_simple_return_p(void)11524 sh_can_use_simple_return_p (void)
11525 {
11526 if (! reload_completed || frame_pointer_needed)
11527 return false;
11528
11529 /* Moving prologue around does't reduce the size. */
11530 if (optimize_function_for_size_p (cfun))
11531 return false;
11532
11533 /* Finally, allow for pr save. */
11534 HARD_REG_SET live_regs_mask;
11535 int d = calc_live_regs (&live_regs_mask);
11536
11537 if (rounded_frame_size (d) > 4)
11538 return false;
11539
11540 return true;
11541 }
11542
11543 /*------------------------------------------------------------------------------
11544 Address mode optimization support code
11545 */
11546
11547 typedef HOST_WIDE_INT disp_t;
11548 static const disp_t MIN_DISP = HOST_WIDE_INT_MIN;
11549 static const disp_t MAX_DISP = HOST_WIDE_INT_MAX;
11550 static const disp_t INVALID_DISP = MAX_DISP;
11551
11552 /* A memory reference which is described by a base register and a
11553 displacement. */
11554 class base_reg_disp
11555 {
11556 public:
11557 base_reg_disp (rtx br, disp_t d);
11558
11559 bool is_reg (void) const;
11560 bool is_disp (void) const;
11561 rtx reg (void) const;
11562 disp_t disp (void) const;
11563
11564 private:
11565 rtx reg_;
11566 disp_t disp_;
11567 };
11568
11569 inline
base_reg_disp(rtx br,disp_t d)11570 base_reg_disp::base_reg_disp (rtx br, disp_t d)
11571 : reg_ (br), disp_ (d)
11572 {
11573 }
11574
11575 inline bool
is_reg(void)11576 base_reg_disp::is_reg (void) const
11577 {
11578 return reg_ != NULL_RTX && disp_ != INVALID_DISP;
11579 }
11580
11581 inline bool
is_disp(void)11582 base_reg_disp::is_disp (void) const
11583 {
11584 return reg_ == NULL_RTX && disp_ != INVALID_DISP;
11585 }
11586
11587 inline rtx
reg(void)11588 base_reg_disp::reg (void) const
11589 {
11590 return reg_;
11591 }
11592
11593 inline disp_t
disp(void)11594 base_reg_disp::disp (void) const
11595 {
11596 return disp_;
11597 }
11598
11599 /* Find the base register and calculate the displacement for a given
11600 address rtx 'x'. */
11601 static base_reg_disp
11602 sh_find_base_reg_disp (rtx_insn* insn, rtx x, disp_t disp = 0,
11603 rtx base_reg = NULL)
11604 {
11605 if (REG_P (x))
11606 {
11607 if (REGNO (x) == GBR_REG)
11608 return base_reg_disp (x, disp);
11609
11610 /* We've reached a hard-reg. This is probably the point where
11611 function args are copied to pseudos. Do not go any further and
11612 stick to the pseudo. If the original mem addr was in a hard reg
11613 from the beginning, it will become the base reg. */
11614 if (REGNO (x) < FIRST_PSEUDO_REGISTER)
11615 return base_reg_disp (base_reg != NULL ? base_reg : x, disp);
11616
11617 /* Find the def of the reg and trace it. If there are more than one
11618 defs and they are not the same, assume it's not safe to proceed. */
11619 rtx_insn* last_i = NULL;
11620 rtx last_set = NULL;
11621 for (df_ref d = DF_REG_DEF_CHAIN (REGNO (x)); d != NULL;
11622 d = DF_REF_NEXT_REG (d))
11623 {
11624 rtx set = const_cast<rtx> (set_of (x, DF_REF_INSN (d)));
11625
11626 /* Accept multiple defs, as long as they are equal. */
11627 if (last_set == NULL || rtx_equal_p (last_set, set))
11628 {
11629 last_i = DF_REF_INSN (d);
11630 last_set = set;
11631 }
11632 else
11633 {
11634 last_i = NULL;
11635 last_set = NULL;
11636 break;
11637 }
11638 }
11639
11640 if (last_set != NULL && last_i != NULL)
11641 return sh_find_base_reg_disp (last_i, XEXP (last_set, 1), disp,
11642 XEXP (last_set, 0));
11643
11644 /* When here, no previous insn was found that sets the reg.
11645 The input reg is already the base reg. */
11646 return base_reg_disp (x, disp);
11647 }
11648
11649 else if (GET_CODE (x) == PLUS)
11650 {
11651 base_reg_disp left_val = sh_find_base_reg_disp (insn, XEXP (x, 0));
11652 base_reg_disp right_val = sh_find_base_reg_disp (insn, XEXP (x, 1));
11653
11654 /* Either left or right val must be a reg.
11655 We don't handle the case of 'reg + reg' here. */
11656 if (left_val.is_reg () && right_val.is_disp ())
11657 return base_reg_disp (left_val.reg (), left_val.disp ()
11658 + right_val.disp () + disp);
11659 else if (right_val.is_reg () && left_val.is_disp ())
11660 return base_reg_disp (right_val.reg (), right_val.disp ()
11661 + left_val.disp () + disp);
11662 else
11663 return base_reg_disp (base_reg, disp);
11664 }
11665
11666 else if (CONST_INT_P (x))
11667 return base_reg_disp (NULL, disp + INTVAL (x));
11668
11669 /* Didn't find anything useful. */
11670 return base_reg_disp (base_reg, disp);
11671 }
11672
11673 /* Given an insn and a memory operand, try to find an equivalent GBR
11674 based memory address and return the corresponding new memory address.
11675 Return NULL_RTX if not found. */
11676 rtx
sh_find_equiv_gbr_addr(rtx_insn * insn,rtx mem)11677 sh_find_equiv_gbr_addr (rtx_insn* insn, rtx mem)
11678 {
11679 if (!MEM_P (mem) || gbr_address_mem (mem, GET_MODE (mem)))
11680 return NULL_RTX;
11681
11682 /* Leave post/pre inc/dec or any other side effect addresses alone. */
11683 if (side_effects_p (XEXP (mem, 0)))
11684 return NULL_RTX;
11685
11686 /* When not optimizing there might be no dataflow available. */
11687 if (df == NULL)
11688 return NULL_RTX;
11689
11690 base_reg_disp gbr_disp = sh_find_base_reg_disp (insn, XEXP (mem, 0));
11691
11692 if (gbr_disp.is_reg () && REGNO (gbr_disp.reg ()) == GBR_REG)
11693 {
11694 /* If GBR is marked as call clobbered we bail out if we see a call.
11695 FIXME: Actually should check if this mem refers to the gbr value
11696 before or after the call. If there is a store_gbr preceeding this
11697 mem, it's safe to use GBR for this mem.
11698
11699 If GBR is not marked as call clobbered, but there is some other
11700 def than a call, it's probably a load_gbr upon which we also
11701 bail out to be on the safe side.
11702 FIXME: Should check if we have a use-after-def case, such as
11703 the call case above. */
11704 for (df_ref d = DF_REG_DEF_CHAIN (GBR_REG); d != NULL;
11705 d = DF_REF_NEXT_REG (d))
11706 {
11707 if (CALL_P (DF_REF_INSN (d)))
11708 {
11709 if (REGNO_REG_SET_P (regs_invalidated_by_call_regset, GBR_REG))
11710 return NULL_RTX;
11711 else
11712 continue;
11713 }
11714 else
11715 return NULL_RTX;
11716 }
11717
11718 rtx disp = GEN_INT (gbr_disp.disp ());
11719 if (gbr_displacement (disp, GET_MODE (mem)))
11720 return gen_rtx_PLUS (SImode, gen_rtx_REG (SImode, GBR_REG), disp);
11721 }
11722
11723 return NULL_RTX;
11724 }
11725
11726 /*------------------------------------------------------------------------------
11727 Manual insn combine support code.
11728 */
11729
11730 /* Return true if the specified insn contains any UNSPECs or
11731 UNSPEC_VOLATILEs. */
11732 static bool
sh_unspec_insn_p(rtx x)11733 sh_unspec_insn_p (rtx x)
11734 {
11735 subrtx_iterator::array_type array;
11736 FOR_EACH_SUBRTX (i, array, x, ALL)
11737 if (*i != NULL
11738 && (GET_CODE (*i) == UNSPEC || GET_CODE (*i) == UNSPEC_VOLATILE))
11739 return true;
11740
11741 return false;
11742 }
11743
11744 /* Return true if the register operands of the specified insn are modified
11745 between the specified from and to insns (exclusive of those two). */
11746 bool
sh_insn_operands_modified_between_p(rtx_insn * operands_insn,const rtx_insn * from,const rtx_insn * to)11747 sh_insn_operands_modified_between_p (rtx_insn* operands_insn,
11748 const rtx_insn* from,
11749 const rtx_insn* to)
11750 {
11751 /* FIXME: Return true for multiple sets for now. */
11752 rtx s = single_set (operands_insn);
11753 if (s == NULL_RTX)
11754 return true;
11755
11756 subrtx_iterator::array_type array;
11757 FOR_EACH_SUBRTX (i, array, SET_SRC (s), ALL)
11758 if (*i != NULL &&
11759 ((REG_P (*i) || SUBREG_P (*i)) && reg_set_between_p (*i, from, to)))
11760 return true;
11761
11762 return false;
11763 }
11764
11765 /* Given an insn, determine whether it's a 'nott' insn, i.e. an insn that
11766 negates the T bit and stores the result in the T bit. */
11767 bool
sh_is_nott_insn(const rtx_insn * i)11768 sh_is_nott_insn (const rtx_insn* i)
11769 {
11770 return i != NULL && GET_CODE (PATTERN (i)) == SET
11771 && t_reg_operand (XEXP (PATTERN (i), 0), VOIDmode)
11772 && negt_reg_operand (XEXP (PATTERN (i), 1), VOIDmode);
11773 }
11774
11775 rtx
sh_movt_set_dest(const rtx_insn * i)11776 sh_movt_set_dest (const rtx_insn* i)
11777 {
11778 return i == NULL ? NULL : sh_movt_set_dest (PATTERN (i));
11779 }
11780
11781 rtx
sh_movt_set_dest(const_rtx pat)11782 sh_movt_set_dest (const_rtx pat)
11783 {
11784 return GET_CODE (pat) == SET
11785 && arith_reg_dest (XEXP (pat, 0), SImode)
11786 && t_reg_operand (XEXP (pat, 1), VOIDmode) ? XEXP (pat, 0) : NULL;
11787 }
11788
11789 /* Given an insn, check whether it's a 'movrt' kind of insn, i.e. an insn
11790 that stores the negated T bit in a register, and return the destination
11791 register rtx, or null. */
11792 rtx
sh_movrt_set_dest(const rtx_insn * i)11793 sh_movrt_set_dest (const rtx_insn* i)
11794 {
11795 return i == NULL ? NULL : sh_movrt_set_dest (PATTERN (i));
11796 }
11797
11798 rtx
sh_movrt_set_dest(const_rtx pat)11799 sh_movrt_set_dest (const_rtx pat)
11800 {
11801 /* The negc movrt replacement is inside a parallel. */
11802 if (GET_CODE (pat) == PARALLEL)
11803 pat = XVECEXP (pat, 0, 0);
11804
11805 return GET_CODE (pat) == SET
11806 && arith_reg_dest (XEXP (pat, 0), SImode)
11807 && negt_reg_operand (XEXP (pat, 1), VOIDmode) ? XEXP (pat, 0) : NULL;
11808
11809 }
11810
11811 /* Given an insn and a reg number, tell whether the reg dies or is unused
11812 after the insn. */
11813 bool
sh_reg_dead_or_unused_after_insn(const rtx_insn * i,int regno)11814 sh_reg_dead_or_unused_after_insn (const rtx_insn* i, int regno)
11815 {
11816 return find_regno_note (i, REG_DEAD, regno) != NULL
11817 || find_regno_note (i, REG_UNUSED, regno) != NULL;
11818 }
11819
11820 /* Given an insn and a reg number, remove reg dead or reg unused notes to
11821 mark it as being used after the insn. */
11822 void
sh_remove_reg_dead_or_unused_notes(rtx_insn * i,int regno)11823 sh_remove_reg_dead_or_unused_notes (rtx_insn* i, int regno)
11824 {
11825 if (rtx n = find_regno_note (i, REG_DEAD, regno))
11826 remove_note (i, n);
11827 if (rtx n = find_regno_note (i, REG_UNUSED, regno))
11828 remove_note (i, n);
11829 }
11830
11831 /* Given an insn check if it contains any post/pre inc/dec mem operands and
11832 add the REG_INC notes accordingly.
11833 FIXME: This function is very similar to lra.c (add_auto_inc_notes).
11834 FIXME: This function is currently used by peephole2 patterns because
11835 the peephole2 pass does not preserve REG_INC notes. If the notes
11836 are dropped the following passes will do wrong things. */
11837 rtx_insn*
sh_check_add_incdec_notes(rtx_insn * i)11838 sh_check_add_incdec_notes (rtx_insn* i)
11839 {
11840 struct for_each_inc_dec_clb
11841 {
11842 static int func (rtx mem ATTRIBUTE_UNUSED, rtx op ATTRIBUTE_UNUSED,
11843 rtx dest, rtx src ATTRIBUTE_UNUSED,
11844 rtx srcoff ATTRIBUTE_UNUSED, void* arg)
11845 {
11846 gcc_assert (REG_P (dest));
11847
11848 rtx_insn* i = (rtx_insn*)arg;
11849 if (find_regno_note (i, REG_INC, REGNO (dest)) == NULL)
11850 add_reg_note (i, REG_INC, dest);
11851
11852 return 0;
11853 }
11854 };
11855
11856 for_each_inc_dec (PATTERN (i), for_each_inc_dec_clb::func, i);
11857 return i;
11858 }
11859
11860 /* Given a move insn destiation and a source, make sure that the move source
11861 operand is not a post-inc mem load with the same address reg as the
11862 destination. Returns the modified source operand with the post-inc removed
11863 if necessary. */
11864 rtx
sh_remove_overlapping_post_inc(rtx dst,rtx src)11865 sh_remove_overlapping_post_inc (rtx dst, rtx src)
11866 {
11867 if (!MEM_P (src))
11868 return src;
11869
11870 rtx addr = XEXP (src, 0);
11871
11872 if (GET_CODE (addr) == POST_INC
11873 && reg_overlap_mentioned_p (XEXP (addr, 0), dst))
11874 return replace_equiv_address (src, XEXP (addr, 0));
11875
11876 gcc_assert (GET_CODE (addr) != POST_MODIFY);
11877 return src;
11878 }
11879
11880 /* Emit a move insn that is safe to be used in peephole patterns. */
11881 rtx_insn*
sh_peephole_emit_move_insn(rtx dst,rtx src)11882 sh_peephole_emit_move_insn (rtx dst, rtx src)
11883 {
11884 return sh_check_add_incdec_notes (
11885 emit_move_insn (dst, sh_remove_overlapping_post_inc (dst, src)));
11886 }
11887
11888 /* Given an op rtx and an insn, try to find out whether the result of the
11889 specified op consists only of logical operations on T bit stores. */
11890 bool
sh_is_logical_t_store_expr(rtx op,rtx_insn * insn)11891 sh_is_logical_t_store_expr (rtx op, rtx_insn* insn)
11892 {
11893 if (!logical_operator (op, SImode))
11894 return false;
11895
11896 rtx ops[2] = { XEXP (op, 0), XEXP (op, 1) };
11897 int op_is_t_count = 0;
11898
11899 for (int i = 0; i < 2; ++i)
11900 {
11901 if (t_reg_operand (ops[i], VOIDmode)
11902 || negt_reg_operand (ops[i], VOIDmode))
11903 op_is_t_count++;
11904
11905 else
11906 {
11907 set_of_reg op_set = sh_find_set_of_reg
11908 (ops[i], insn, prev_nonnote_nondebug_insn_bb);
11909 if (op_set.set_src == NULL_RTX)
11910 continue;
11911
11912 if (t_reg_operand (op_set.set_src, VOIDmode)
11913 || negt_reg_operand (op_set.set_src, VOIDmode)
11914 || sh_is_logical_t_store_expr (op_set.set_src, op_set.insn))
11915 op_is_t_count++;
11916 }
11917 }
11918
11919 return op_is_t_count == 2;
11920 }
11921
11922 /* Given the operand that is extended in a sign/zero extend insn, and the
11923 insn, try to figure out whether the sign/zero extension can be replaced
11924 by a simple reg-reg copy. If so, the replacement reg rtx is returned,
11925 NULL_RTX otherwise. */
11926 rtx
sh_try_omit_signzero_extend(rtx extended_op,rtx_insn * insn)11927 sh_try_omit_signzero_extend (rtx extended_op, rtx_insn* insn)
11928 {
11929 if (REG_P (extended_op))
11930 extended_op = extended_op;
11931 else if (GET_CODE (extended_op) == SUBREG && REG_P (SUBREG_REG (extended_op)))
11932 extended_op = SUBREG_REG (extended_op);
11933 else
11934 return NULL_RTX;
11935
11936 /* Reg moves must be of the same mode. */
11937 if (GET_MODE (extended_op) != SImode)
11938 return NULL_RTX;
11939
11940 set_of_reg s = sh_find_set_of_reg (extended_op, insn,
11941 prev_nonnote_nondebug_insn_bb);
11942 if (s.set_src == NULL_RTX)
11943 return NULL_RTX;
11944
11945 if (t_reg_operand (s.set_src, VOIDmode)
11946 || negt_reg_operand (s.set_src, VOIDmode))
11947 return extended_op;
11948
11949 /* If the zero extended reg was formed by a logical operation, check the
11950 operands of the logical operation. If both originated from T bit
11951 stores the zero extension can be eliminated. */
11952 else if (sh_is_logical_t_store_expr (s.set_src, s.insn))
11953 return extended_op;
11954
11955 return NULL_RTX;
11956 }
11957
11958 /* Given the current insn, which is assumed to be a movrt_negc insn, try to
11959 figure out whether it should be converted into a movt-xor sequence in
11960 the movrt_negc splitter.
11961 Returns true if insns have been modified and the splitter has succeeded. */
11962 bool
sh_split_movrt_negc_to_movt_xor(rtx_insn * curr_insn,rtx operands[])11963 sh_split_movrt_negc_to_movt_xor (rtx_insn* curr_insn, rtx operands[])
11964 {
11965 /* In cases such as
11966 tst r4,r4
11967 mov #-1,r1
11968 negc r1,r1
11969 tst r4,r4
11970 we can replace the T bit clobbering negc with a movt-xor sequence and
11971 eliminate the redundant comparison.
11972 Because the xor insn depends on register allocation results, allow this
11973 only before reload. */
11974 if (!can_create_pseudo_p ())
11975 return false;
11976
11977 set_of_reg t_before_negc = sh_find_set_of_reg
11978 (get_t_reg_rtx (), curr_insn, prev_nonnote_nondebug_insn_bb);
11979 set_of_reg t_after_negc = sh_find_set_of_reg
11980 (get_t_reg_rtx (), curr_insn, next_nonnote_nondebug_insn_bb);
11981
11982 if (t_before_negc.set_rtx != NULL_RTX && t_after_negc.set_rtx != NULL_RTX
11983 && rtx_equal_p (t_before_negc.set_rtx, t_after_negc.set_rtx)
11984 && !reg_used_between_p (get_t_reg_rtx (), curr_insn, t_after_negc.insn)
11985 && !sh_insn_operands_modified_between_p (t_before_negc.insn,
11986 t_before_negc.insn,
11987 t_after_negc.insn)
11988 && !modified_between_p (get_t_reg_rtx (), curr_insn, t_after_negc.insn)
11989 && !sh_unspec_insn_p (t_after_negc.insn)
11990 && !volatile_insn_p (PATTERN (t_after_negc.insn))
11991 && !side_effects_p (PATTERN (t_after_negc.insn))
11992 && !may_trap_or_fault_p (PATTERN (t_after_negc.insn)))
11993 {
11994 emit_insn (gen_movrt_xor (operands[0], get_t_reg_rtx ()));
11995 set_insn_deleted (t_after_negc.insn);
11996 return true;
11997 }
11998 else
11999 return false;
12000 }
12001
12002 /* Given a reg and the current insn, see if the value of the reg originated
12003 from a sign or zero extension and return the discovered information. */
12004 sh_extending_set_of_reg
sh_find_extending_set_of_reg(rtx reg,rtx_insn * curr_insn)12005 sh_find_extending_set_of_reg (rtx reg, rtx_insn* curr_insn)
12006 {
12007 if (reg == NULL)
12008 return sh_extending_set_of_reg (curr_insn);
12009
12010 if (SUBREG_P (reg))
12011 reg = SUBREG_REG (reg);
12012
12013 if (!REG_P (reg))
12014 return sh_extending_set_of_reg (curr_insn);
12015
12016 /* FIXME: Also search the predecessor basic blocks. It seems that checking
12017 only the adjacent predecessor blocks would cover most of the cases.
12018 Also try to look through the first extension that we hit. There are some
12019 cases, where a zero_extend is followed an (implicit) sign_extend, and it
12020 fails to see the sign_extend. */
12021 sh_extending_set_of_reg result = sh_find_set_of_reg
12022 (reg, curr_insn, prev_nonnote_nondebug_insn_bb, true);
12023
12024 if (result.set_src != NULL)
12025 {
12026 if (GET_CODE (result.set_src) == SIGN_EXTEND
12027 || GET_CODE (result.set_src) == ZERO_EXTEND)
12028 {
12029 if (dump_file)
12030 fprintf (dump_file, "sh_find_extending_set_of_reg: reg %d is "
12031 "explicitly sign/zero extended in insn %d\n",
12032 REGNO (reg), INSN_UID (result.insn));
12033 result.from_mode = GET_MODE (XEXP (result.set_src, 0));
12034 result.ext_code = GET_CODE (result.set_src);
12035 }
12036 else if (MEM_P (result.set_src)
12037 && (GET_MODE (result.set_src) == QImode
12038 || GET_MODE (result.set_src) == HImode)
12039 && !sh_unspec_insn_p (result.insn))
12040 {
12041 /* On SH QIHImode memory loads always sign extend. However, in
12042 some cases where it seems that the higher bits are not
12043 interesting, the loads will not be expanded as sign extending
12044 insns, but as QIHImode loads into QIHImode regs. We report that
12045 the reg has been sign extended by the mem load. When it is used
12046 as such, we must convert the mem load into a sign extending insn,
12047 see also sh_extending_set_of_reg::use_as_extended_reg. */
12048 if (dump_file)
12049 fprintf (dump_file, "sh_find_extending_set_of_reg: reg %d is "
12050 "implicitly sign extended in insn %d\n",
12051 REGNO (reg), INSN_UID (result.insn));
12052 result.from_mode = GET_MODE (result.set_src);
12053 result.ext_code = SIGN_EXTEND;
12054 }
12055 }
12056
12057 return result;
12058 }
12059
12060 /* Given a reg that is known to be sign or zero extended at some insn,
12061 take the appropriate measures so that the extended value can be used as
12062 a reg at the specified insn and return the resulting reg rtx. */
12063 rtx
use_as_extended_reg(rtx_insn * use_at_insn)12064 sh_extending_set_of_reg::use_as_extended_reg (rtx_insn* use_at_insn) const
12065 {
12066 gcc_assert (insn != NULL && set_src != NULL && set_rtx != NULL);
12067 gcc_assert (ext_code == SIGN_EXTEND || ext_code == ZERO_EXTEND);
12068 gcc_assert (from_mode == QImode || from_mode == HImode);
12069
12070 if (MEM_P (set_src) && ext_code == SIGN_EXTEND)
12071 {
12072 if (dump_file)
12073 fprintf (dump_file,
12074 "use_as_extended_reg: converting non-extending mem load in "
12075 "insn %d into sign-extending load\n", INSN_UID (insn));
12076
12077 rtx r = gen_reg_rtx (SImode);
12078 rtx_insn* i0;
12079 if (from_mode == QImode)
12080 i0 = emit_insn_after (gen_extendqisi2 (r, set_src), insn);
12081 else if (from_mode == HImode)
12082 i0 = emit_insn_after (gen_extendhisi2 (r, set_src), insn);
12083 else
12084 gcc_unreachable ();
12085
12086 emit_insn_after (
12087 gen_move_insn (XEXP (set_rtx, 0),
12088 gen_lowpart (GET_MODE (set_src), r)), i0);
12089 set_insn_deleted (insn);
12090 return r;
12091 }
12092 else
12093 {
12094 rtx extension_dst = XEXP (set_rtx, 0);
12095 if (GET_MODE (extension_dst) != SImode)
12096 extension_dst = simplify_gen_subreg (SImode, extension_dst,
12097 GET_MODE (extension_dst), 0);
12098 if (modified_between_p (extension_dst, insn, use_at_insn))
12099 {
12100 if (dump_file)
12101 fprintf (dump_file,
12102 "use_as_extended_reg: dest reg %d of extending insn %d is "
12103 "modified, inserting a reg-reg copy\n",
12104 REGNO (extension_dst), INSN_UID (insn));
12105
12106 rtx r = gen_reg_rtx (SImode);
12107 emit_insn_after (gen_move_insn (r, extension_dst), insn);
12108 return r;
12109 }
12110 else
12111 {
12112 sh_remove_reg_dead_or_unused_notes (insn, REGNO (extension_dst));
12113 return extension_dst;
12114 }
12115 }
12116 }
12117
12118 bool
can_use_as_unextended_reg(void)12119 sh_extending_set_of_reg::can_use_as_unextended_reg (void) const
12120 {
12121 if ((ext_code == SIGN_EXTEND || ext_code == ZERO_EXTEND)
12122 && (from_mode == QImode || from_mode == HImode)
12123 && set_src != NULL)
12124 return arith_reg_operand (XEXP (set_src, 0), from_mode);
12125 else
12126 return false;
12127 }
12128
12129 rtx
use_as_unextended_reg(rtx_insn * use_at_insn)12130 sh_extending_set_of_reg::use_as_unextended_reg (rtx_insn* use_at_insn) const
12131 {
12132 gcc_assert (can_use_as_unextended_reg ());
12133
12134 rtx r = XEXP (set_src, 0);
12135 rtx r0 = simplify_gen_subreg (SImode, r, from_mode, 0);
12136
12137 if (modified_between_p (r, insn, use_at_insn))
12138 {
12139 rtx r1 = gen_reg_rtx (SImode);
12140 emit_insn_after (gen_move_insn (r1, r0), insn);
12141 return r1;
12142 }
12143 else
12144 {
12145 sh_remove_reg_dead_or_unused_notes (insn, SUBREG_P (r)
12146 ? REGNO (SUBREG_REG (r))
12147 : REGNO (r));
12148 return r0;
12149 }
12150 }
12151
12152 /* Given the current insn, which is assumed to be the *tst<mode>_t_subregs insn,
12153 perform the necessary checks on the operands and split it accordingly. */
12154 void
sh_split_tst_subregs(rtx_insn * curr_insn,machine_mode subreg_mode,int subreg_offset,rtx operands[])12155 sh_split_tst_subregs (rtx_insn* curr_insn, machine_mode subreg_mode,
12156 int subreg_offset, rtx operands[])
12157 {
12158 gcc_assert (subreg_mode == QImode || subreg_mode == HImode);
12159
12160 sh_extending_set_of_reg eop0 = sh_find_extending_set_of_reg (operands[0],
12161 curr_insn);
12162 sh_extending_set_of_reg eop1 = sh_find_extending_set_of_reg (operands[1],
12163 curr_insn);
12164
12165 /* If one of the operands is known to be zero extended, that's already
12166 sufficient to mask out the unwanted high bits. */
12167 if (eop0.ext_code == ZERO_EXTEND && eop0.from_mode == subreg_mode)
12168 {
12169 emit_insn (gen_tstsi_t (eop0.use_as_extended_reg (curr_insn),
12170 operands[1]));
12171 return;
12172 }
12173 if (eop1.ext_code == ZERO_EXTEND && eop1.from_mode == subreg_mode)
12174 {
12175 emit_insn (gen_tstsi_t (operands[0],
12176 eop1.use_as_extended_reg (curr_insn)));
12177 return;
12178 }
12179
12180 /* None of the operands seem to be zero extended.
12181 If both are sign extended it's OK, too. */
12182 if (eop0.ext_code == SIGN_EXTEND && eop1.ext_code == SIGN_EXTEND
12183 && eop0.from_mode == subreg_mode && eop1.from_mode == subreg_mode)
12184 {
12185 emit_insn (gen_tstsi_t (eop0.use_as_extended_reg (curr_insn),
12186 eop1.use_as_extended_reg (curr_insn)));
12187 return;
12188 }
12189
12190 /* Otherwise we have to insert a zero extension on one of the operands to
12191 mask out the unwanted high bits.
12192 Prefer the operand that has no known extension. */
12193 if (eop0.ext_code != UNKNOWN && eop1.ext_code == UNKNOWN)
12194 std::swap (operands[0], operands[1]);
12195
12196 rtx tmp0 = gen_reg_rtx (SImode);
12197 rtx tmp1 = simplify_gen_subreg (subreg_mode, operands[0],
12198 GET_MODE (operands[0]), subreg_offset);
12199 emit_insn (subreg_mode == QImode
12200 ? gen_zero_extendqisi2 (tmp0, tmp1)
12201 : gen_zero_extendhisi2 (tmp0, tmp1));
12202 emit_insn (gen_tstsi_t (tmp0, operands[1]));
12203 }
12204
12205 /* A helper class to increment/decrement a counter variable each time a
12206 function is entered/left. */
12207 class scope_counter
12208 {
12209 public:
scope_counter(int & counter)12210 scope_counter (int& counter) : m_counter (counter) { ++m_counter; }
12211
~scope_counter(void)12212 ~scope_counter (void)
12213 {
12214 --m_counter;
12215 gcc_assert (m_counter >= 0);
12216 }
12217
count(void)12218 int count (void) const { return m_counter; }
12219
12220 private:
12221 int& m_counter;
12222 };
12223
12224 /* Given an rtx x, determine whether the expression can be used to create
12225 an insn that calulates x and stores the result in the T bit.
12226 This is used by the 'treg_set_expr' predicate to construct insns sequences
12227 where T bit results are fed into other insns, such as addc, subc, negc
12228 insns.
12229
12230 FIXME: The patterns that expand 'treg_set_expr' operands tend to
12231 distinguish between 'positive' and 'negative' forms. For now this has to
12232 be done in the preparation code. We could also introduce
12233 'pos_treg_set_expr' and 'neg_treg_set_expr' predicates for that and write
12234 two different patterns for the 'postive' and 'negative' forms. However,
12235 the total amount of lines of code seems to be about the same and the
12236 '{pos|neg}_treg_set_expr' predicates would be more expensive, because the
12237 recog function would need to look inside the expression by temporarily
12238 splitting it. */
12239 static int sh_recog_treg_set_expr_reent_count = 0;
12240
12241 bool
sh_recog_treg_set_expr(rtx op,machine_mode mode)12242 sh_recog_treg_set_expr (rtx op, machine_mode mode)
12243 {
12244 scope_counter recursion (sh_recog_treg_set_expr_reent_count);
12245
12246 /* Limit the recursion count to avoid nested expressions which we can't
12247 resolve to a single treg set insn. */
12248 if (recursion.count () > 1)
12249 return false;
12250
12251 /* Early accept known possible operands before doing recog. */
12252 if (op == const0_rtx || op == const1_rtx || t_reg_operand (op, mode)
12253 || negt_reg_operand (op, mode))
12254 return true;
12255
12256 /* Early reject impossible operands before doing recog.
12257 There are some (set ((t) (subreg ...))) patterns, but we must be careful
12258 not to allow any invalid reg-reg or mem-reg moves, or else other passes
12259 such as lower-subreg will bail out. Some insns such as SH4A movua are
12260 done with UNSPEC, so must reject those, too, or else it would result
12261 in an invalid reg -> treg move. */
12262 if (CONST_INT_P (op) || register_operand (op, mode)
12263 || memory_operand (op, mode) || sh_unspec_insn_p (op))
12264 return false;
12265
12266 if (!can_create_pseudo_p ())
12267 return false;
12268
12269 /* expand_debug_locations may call this to compute rtx costs at
12270 very early stage. In that case, don't make new insns here to
12271 avoid codegen differences with -g. */
12272 if (currently_expanding_to_rtl)
12273 return false;
12274
12275 /* We are going to invoke recog in a re-entrant way and thus
12276 have to capture its current state and restore it afterwards. */
12277 recog_data_d prev_recog_data = recog_data;
12278
12279 rtx_insn* i = make_insn_raw (gen_rtx_SET (get_t_reg_rtx (), op));
12280 SET_PREV_INSN (i) = NULL;
12281 SET_NEXT_INSN (i) = NULL;
12282
12283 /* If the comparison op doesn't have a result mode, set it to SImode. */
12284 machine_mode prev_op_mode = GET_MODE (op);
12285 if (COMPARISON_P (op) && prev_op_mode == VOIDmode)
12286 PUT_MODE (op, SImode);
12287
12288 int result = recog (PATTERN (i), i, 0);
12289
12290 /* It seems there is no insn like that. Create a negated version and
12291 try again. If we hit a negated form, we'll allow that and append a
12292 nott sequence when splitting out the insns. Insns that do the split
12293 can then remove the trailing nott if they know how to deal with it. */
12294 if (result < 0 && COMPARISON_P (op))
12295 {
12296 machine_mode cmp_mode = GET_MODE (XEXP (op, 0));
12297 if (cmp_mode == VOIDmode)
12298 cmp_mode = GET_MODE (XEXP (op, 1));
12299
12300 rtx_code prev_code = GET_CODE (op);
12301 PUT_CODE (op, reverse_condition (GET_CODE (op)));
12302 result = recog (PATTERN (i), i, 0);
12303 PUT_CODE (op, prev_code);
12304 }
12305
12306 PUT_MODE (op, prev_op_mode);
12307 recog_data = prev_recog_data;
12308 return result >= 0;
12309 }
12310
12311 /* Returns true when recog of a 'treg_set_expr' is currently in progress.
12312 This can be used as a condition for insn/split patterns to allow certain
12313 T bit setting patters only to be matched as sub expressions of other
12314 patterns. */
12315 bool
sh_in_recog_treg_set_expr(void)12316 sh_in_recog_treg_set_expr (void)
12317 {
12318 return sh_recog_treg_set_expr_reent_count > 0;
12319 }
12320
12321 /* Given an rtx x, which is assumed to be some expression that has been
12322 matched by the 'treg_set_expr' predicate before, split and emit the
12323 insns that are necessary to calculate the expression and store the result
12324 in the T bit.
12325 The splitting is done recursively similar to 'try_split' in emit-rt.c.
12326 Unfortunately we can't use 'try_split' here directly, as it tries to invoke
12327 'delete_insn' which then causes the DF parts to bail out, because we
12328 currently are inside another gen_split* function and would invoke
12329 'try_split' in a reentrant way. */
12330 static std::pair<rtx_insn*, rtx_insn*>
12331 sh_try_split_insn_simple (rtx_insn* i, rtx_insn* curr_insn, int n = 0)
12332 {
12333 if (dump_file)
12334 {
12335 fprintf (dump_file, "sh_try_split_insn_simple n = %d i = \n", n);
12336 print_rtl_single (dump_file, i);
12337 fprintf (dump_file, "\n");
12338 }
12339
12340 rtx_insn* seq = split_insns (PATTERN (i), curr_insn);
12341
12342 if (seq == NULL)
12343 return std::make_pair (i, i);
12344
12345 /* Avoid infinite splitter loops if any insn of the result matches
12346 the original pattern. */
12347 for (rtx_insn* s = seq; s != NULL; s = NEXT_INSN (s))
12348 if (INSN_P (s) && rtx_equal_p (PATTERN (s), PATTERN (i)))
12349 return std::make_pair (i, i);
12350
12351 unshare_all_rtl_in_chain (seq);
12352
12353 /* 'seq' is now a replacement for 'i'. Assuming that 'i' is an insn in
12354 a linked list, replace the single insn with the new insns. */
12355 rtx_insn* seqlast = seq;
12356 while (NEXT_INSN (seqlast) != NULL)
12357 seqlast = NEXT_INSN (seqlast);
12358
12359 if (rtx_insn* iprev = PREV_INSN (i))
12360 SET_NEXT_INSN (iprev) = seq;
12361 if (rtx_insn* inext = NEXT_INSN (i))
12362 SET_PREV_INSN (inext) = seqlast;
12363
12364 SET_PREV_INSN (seq) = PREV_INSN (i);
12365 SET_NEXT_INSN (seqlast) = NEXT_INSN (i);
12366
12367 SET_PREV_INSN (i) = NULL;
12368 SET_NEXT_INSN (i) = NULL;
12369
12370 /* Recursively split all insns. */
12371 for (i = seq; ; i = NEXT_INSN (i))
12372 {
12373 std::pair<rtx_insn*, rtx_insn*> ii =
12374 sh_try_split_insn_simple (i, curr_insn, n + 1);
12375 if (i == seq)
12376 seq = ii.first;
12377 if (i == seqlast)
12378 {
12379 seqlast = ii.second;
12380 break;
12381 }
12382 i = ii.first;
12383 }
12384
12385 return std::make_pair (seq, seqlast);
12386 }
12387
12388 sh_treg_insns
sh_split_treg_set_expr(rtx x,rtx_insn * curr_insn)12389 sh_split_treg_set_expr (rtx x, rtx_insn* curr_insn)
12390 {
12391 if (t_reg_operand (x, VOIDmode))
12392 return sh_treg_insns ();
12393
12394 scope_counter in_treg_set_expr (sh_recog_treg_set_expr_reent_count);
12395
12396 rtx_insn* i = make_insn_raw (gen_rtx_SET (get_t_reg_rtx (), x));
12397 SET_PREV_INSN (i) = NULL;
12398 SET_NEXT_INSN (i) = NULL;
12399
12400 if (dump_file)
12401 {
12402 fprintf (dump_file, "split_treg_set_expr insn:\n");
12403 print_rtl (dump_file, i);
12404 fprintf (dump_file, "\n");
12405 }
12406
12407 /* If the insn is not found, we will try a negated form and append
12408 a nott. */
12409 bool append_nott = false;
12410
12411 /* We are going to invoke recog/split_insns in a re-entrant way and thus
12412 have to capture its current state and restore it afterwards. */
12413 recog_data_d prev_recog_data = recog_data;
12414
12415 if (negt_reg_operand (x, GET_MODE (x)))
12416 {
12417 /* This is a normal movt followed by a nott. It will be converted
12418 into a movrt after initial expansion. */
12419 XEXP (PATTERN (i), 1) = get_t_reg_rtx ();
12420 append_nott = true;
12421 }
12422 else
12423 {
12424 /* If the comparison op doesn't have a mode set, set it to SImode. */
12425 if (COMPARISON_P (x) && GET_MODE (x) == VOIDmode)
12426 PUT_MODE (x, SImode);
12427
12428 int insn_code = recog (PATTERN (i), i, 0);
12429
12430 if (insn_code < 0 && COMPARISON_P (x))
12431 {
12432 machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
12433 if (cmp_mode == VOIDmode)
12434 cmp_mode = GET_MODE (XEXP (x, 1));
12435
12436 PUT_CODE (x, reverse_condition (GET_CODE (x)));
12437 insn_code = recog (PATTERN (i), i, 0);
12438 append_nott = true;
12439 }
12440
12441 gcc_assert (insn_code >= 0);
12442 }
12443
12444 /* Try to recursively split the insn. Some insns might refuse to split
12445 any further while we are in the treg_set_expr splitting phase. They
12446 will be emitted as part of the outer insn and then split again. */
12447 std::pair<rtx_insn*, rtx_insn*> insnlist =
12448 sh_try_split_insn_simple (i, curr_insn);
12449
12450 /* Restore recog state. */
12451 recog_data = prev_recog_data;
12452
12453 rtx_insn* nott_insn = sh_is_nott_insn (insnlist.second)
12454 ? insnlist.second
12455 : NULL;
12456 if (dump_file)
12457 {
12458 fprintf (dump_file, "split_treg_set_expr insnlist:\n");
12459 print_rtl (dump_file, insnlist.first);
12460 fprintf (dump_file, "\n");
12461
12462 if (nott_insn != NULL)
12463 fprintf (dump_file, "trailing nott insn %d\n", INSN_UID (nott_insn));
12464 }
12465
12466 emit_insn (insnlist.first);
12467
12468 if (nott_insn != NULL && append_nott)
12469 {
12470 if (dump_file)
12471 fprintf (dump_file, "removing trailing nott\n");
12472 remove_insn (nott_insn);
12473 nott_insn = NULL;
12474 append_nott = false;
12475 }
12476
12477 if (append_nott)
12478 nott_insn = emit_insn (gen_nott (get_t_reg_rtx ()));
12479
12480 rtx_insn* first_insn = get_insns ();
12481
12482 if (dump_file)
12483 {
12484 fprintf (dump_file, "resulting insns:\n");
12485 print_rtl (dump_file, first_insn);
12486 fprintf (dump_file, "\n");
12487 }
12488
12489 return sh_treg_insns (first_insn, nott_insn);
12490 }
12491
12492 /*------------------------------------------------------------------------------
12493 Mode switching support code.
12494 */
12495
12496 static void
sh_emit_mode_set(int entity ATTRIBUTE_UNUSED,int mode,int prev_mode,HARD_REG_SET regs_live ATTRIBUTE_UNUSED)12497 sh_emit_mode_set (int entity ATTRIBUTE_UNUSED, int mode,
12498 int prev_mode, HARD_REG_SET regs_live ATTRIBUTE_UNUSED)
12499 {
12500 if ((TARGET_SH4A_FP || TARGET_SH4_300)
12501 && prev_mode != FP_MODE_NONE && prev_mode != mode)
12502 {
12503 emit_insn (gen_toggle_pr ());
12504 if (TARGET_FMOVD)
12505 emit_insn (gen_toggle_sz ());
12506 }
12507 else if (mode != FP_MODE_NONE)
12508 {
12509 rtx tmp = gen_reg_rtx (SImode);
12510 emit_insn (gen_sts_fpscr (tmp));
12511 rtx i = NULL;
12512
12513 const unsigned HOST_WIDE_INT fpbits =
12514 TARGET_FMOVD ? (FPSCR_PR | FPSCR_SZ) : FPSCR_PR;
12515
12516 if (prev_mode != FP_MODE_NONE && prev_mode != mode)
12517 i = gen_xorsi3 (tmp, tmp, force_reg (SImode, GEN_INT (fpbits)));
12518 else if (mode == FP_MODE_SINGLE)
12519 i = gen_andsi3 (tmp, tmp, force_reg (SImode, GEN_INT (~fpbits)));
12520 else if (mode == FP_MODE_DOUBLE)
12521 i = gen_iorsi3 (tmp, tmp, force_reg (SImode, GEN_INT (fpbits)));
12522 else
12523 gcc_unreachable ();
12524
12525 emit_insn (i);
12526 emit_insn (gen_lds_fpscr (tmp));
12527 }
12528 }
12529
12530 static int
sh_mode_needed(int entity ATTRIBUTE_UNUSED,rtx_insn * insn)12531 sh_mode_needed (int entity ATTRIBUTE_UNUSED, rtx_insn *insn)
12532 {
12533 return recog_memoized (insn) >= 0 ? get_attr_fp_mode (insn) : FP_MODE_NONE;
12534 }
12535
12536 static int
sh_mode_after(int entity ATTRIBUTE_UNUSED,int mode,rtx_insn * insn)12537 sh_mode_after (int entity ATTRIBUTE_UNUSED, int mode, rtx_insn *insn)
12538 {
12539 if (TARGET_HITACHI && recog_memoized (insn) >= 0 &&
12540 get_attr_fp_set (insn) != FP_SET_NONE)
12541 return (int) get_attr_fp_set (insn);
12542 else
12543 return mode;
12544 }
12545
12546 static int
sh_mode_entry(int entity ATTRIBUTE_UNUSED)12547 sh_mode_entry (int entity ATTRIBUTE_UNUSED)
12548 {
12549 return NORMAL_MODE (entity);
12550 }
12551
12552 static int
sh_mode_exit(int entity ATTRIBUTE_UNUSED)12553 sh_mode_exit (int entity ATTRIBUTE_UNUSED)
12554 {
12555 return sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (entity);
12556 }
12557
12558 static int
sh_mode_priority(int entity ATTRIBUTE_UNUSED,int n)12559 sh_mode_priority (int entity ATTRIBUTE_UNUSED, int n)
12560 {
12561 return ((TARGET_FPU_SINGLE != 0) ^ (n) ? FP_MODE_SINGLE : FP_MODE_DOUBLE);
12562 }
12563
12564 /*------------------------------------------------------------------------------
12565 Misc
12566 */
12567
12568 /* Return true if we use LRA instead of reload pass. */
12569 bool
sh_lra_p(void)12570 sh_lra_p (void)
12571 {
12572 return sh_lra_flag;
12573 }
12574
12575 /* Implement TARGET_USE_BY_PIECES_INFRASTRUCTURE_P. */
12576
12577 static bool
sh_use_by_pieces_infrastructure_p(unsigned HOST_WIDE_INT size,unsigned int align,enum by_pieces_operation op,bool speed_p)12578 sh_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size,
12579 unsigned int align,
12580 enum by_pieces_operation op,
12581 bool speed_p)
12582 {
12583 switch (op)
12584 {
12585 case MOVE_BY_PIECES:
12586 return by_pieces_ninsns (size, align, MOVE_MAX_PIECES + 1, op)
12587 < (!speed_p ? 2 : (align >= 32) ? 16 : 2);
12588 case STORE_BY_PIECES:
12589 case SET_BY_PIECES:
12590 return by_pieces_ninsns (size, align, STORE_MAX_PIECES + 1, op)
12591 < (!speed_p ? 2 : (align >= 32) ? 16 : 2);
12592 default:
12593 return default_use_by_pieces_infrastructure_p (size, align,
12594 op, speed_p);
12595 }
12596 }
12597
12598 bool
sh_cannot_force_const_mem_p(machine_mode mode ATTRIBUTE_UNUSED,rtx x ATTRIBUTE_UNUSED)12599 sh_cannot_force_const_mem_p (machine_mode mode ATTRIBUTE_UNUSED,
12600 rtx x ATTRIBUTE_UNUSED)
12601 {
12602 return TARGET_FDPIC;
12603 }
12604
12605 /* Emit insns to load the function address from FUNCDESC (an FDPIC
12606 function descriptor) into r1 and the GOT address into r12,
12607 returning an rtx for r1. */
12608
12609 rtx
sh_load_function_descriptor(rtx funcdesc)12610 sh_load_function_descriptor (rtx funcdesc)
12611 {
12612 rtx r1 = gen_rtx_REG (Pmode, R1_REG);
12613 rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG);
12614 rtx fnaddr = gen_rtx_MEM (Pmode, funcdesc);
12615 rtx gotaddr = gen_rtx_MEM (Pmode, plus_constant (Pmode, funcdesc, 4));
12616
12617 emit_move_insn (r1, fnaddr);
12618 /* The ABI requires the entry point address to be loaded first, so
12619 prevent the load from being moved after that of the GOT
12620 address. */
12621 emit_insn (gen_blockage ());
12622 emit_move_insn (pic_reg, gotaddr);
12623 return r1;
12624 }
12625
12626 /* Return an rtx holding the initial value of the FDPIC register (the
12627 FDPIC pointer passed in from the caller). */
12628
12629 rtx
sh_get_fdpic_reg_initial_val(void)12630 sh_get_fdpic_reg_initial_val (void)
12631 {
12632 return get_hard_reg_initial_val (Pmode, PIC_REG);
12633 }
12634
12635 #include "gt-sh.h"
12636