1 /* DWARF2 EH unwinding support for MIPS Linux.
2 Copyright (C) 2004-2018 Free Software Foundation, Inc.
3
4 This file is part of GCC.
5
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 Under Section 7 of GPL version 3, you are granted additional
17 permissions described in the GCC Runtime Library Exception, version
18 3.1, as published by the Free Software Foundation.
19
20 You should have received a copy of the GNU General Public License and
21 a copy of the GCC Runtime Library Exception along with this program;
22 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
23 <http://www.gnu.org/licenses/>. */
24
25 #ifndef inhibit_libc
26 /* Do code reading to identify a signal frame, and set the frame
27 state data appropriately. See unwind-dw2.c for the structs. */
28
29 #include <signal.h>
30 #include <sys/syscall.h>
31
32 /* The third parameter to the signal handler points to something with
33 * this structure defined in asm/ucontext.h, but the name clashes with
34 * struct ucontext from sys/ucontext.h so this private copy is used. */
35 typedef struct _sig_ucontext {
36 unsigned long uc_flags;
37 struct _sig_ucontext *uc_link;
38 stack_t uc_stack;
39 struct sigcontext uc_mcontext;
40 sigset_t uc_sigmask;
41 } _sig_ucontext_t;
42
43 #define MD_FALLBACK_FRAME_STATE_FOR mips_fallback_frame_state
44
45 static _Unwind_Reason_Code
mips_fallback_frame_state(struct _Unwind_Context * context,_Unwind_FrameState * fs)46 mips_fallback_frame_state (struct _Unwind_Context *context,
47 _Unwind_FrameState *fs)
48 {
49 u_int32_t *pc = (u_int32_t *) context->ra;
50 struct sigcontext *sc;
51 _Unwind_Ptr new_cfa, reg_offset;
52 int i;
53
54 /* A MIPS16 or microMIPS frame. Signal frames always use the standard
55 ISA encoding. */
56 if ((_Unwind_Ptr) pc & 3)
57 return _URC_END_OF_STACK;
58
59 /* 24021061 li v0, 0x1061 (rt_sigreturn)*/
60 /* 0000000c syscall */
61 /* or */
62 /* 24021017 li v0, 0x1017 (sigreturn) */
63 /* 0000000c syscall */
64 if (pc[1] != 0x0000000c)
65 return _URC_END_OF_STACK;
66 #if _MIPS_SIM == _ABIO32
67 if (pc[0] == (0x24020000 | __NR_sigreturn))
68 {
69 struct sigframe {
70 u_int32_t ass[4]; /* Argument save space for o32. */
71 u_int32_t trampoline[2];
72 struct sigcontext sigctx;
73 } *rt_ = context->cfa;
74 sc = &rt_->sigctx;
75 }
76 else
77 #endif
78 if (pc[0] == (0x24020000 | __NR_rt_sigreturn))
79 {
80 struct rt_sigframe {
81 u_int32_t ass[4]; /* Argument save space for o32. */
82 u_int32_t trampoline[2];
83 siginfo_t info;
84 _sig_ucontext_t uc;
85 } *rt_ = context->cfa;
86 sc = &rt_->uc.uc_mcontext;
87 }
88 else
89 return _URC_END_OF_STACK;
90
91 new_cfa = (_Unwind_Ptr) sc;
92 fs->regs.cfa_how = CFA_REG_OFFSET;
93 fs->regs.cfa_reg = __LIBGCC_STACK_POINTER_REGNUM__;
94 fs->regs.cfa_offset = new_cfa - (_Unwind_Ptr) context->cfa;
95
96 /* On o32 Linux, the register save slots in the sigcontext are
97 eight bytes. We need the lower half of each register slot,
98 so slide our view of the structure back four bytes. */
99 #if _MIPS_SIM == _ABIO32 && defined __MIPSEB__
100 reg_offset = 4;
101 #else
102 reg_offset = 0;
103 #endif
104
105 for (i = 0; i < 32; i++) {
106 fs->regs.reg[i].how = REG_SAVED_OFFSET;
107 fs->regs.reg[i].loc.offset
108 = (_Unwind_Ptr)&(sc->sc_regs[i]) + reg_offset - new_cfa;
109 }
110 /* "PC & -2" points to the faulting instruction, but the unwind code
111 searches for "(ADDR & -2) - 1". (See MASK_RETURN_ADDR for the source
112 of the -2 mask.) Adding 2 here ensures that "(ADDR & -2) - 1" is the
113 address of the second byte of the faulting instruction.
114
115 Note that setting fs->signal_frame would not work. As the comment
116 above MASK_RETURN_ADDR explains, MIPS unwinders must earch for an
117 odd-valued address. */
118 fs->regs.reg[__LIBGCC_DWARF_ALT_FRAME_RETURN_COLUMN__].how
119 = REG_SAVED_VAL_OFFSET;
120 fs->regs.reg[__LIBGCC_DWARF_ALT_FRAME_RETURN_COLUMN__].loc.offset
121 = (_Unwind_Ptr)(sc->sc_pc) + 2 - new_cfa;
122 fs->retaddr_column = __LIBGCC_DWARF_ALT_FRAME_RETURN_COLUMN__;
123
124 return _URC_NO_REASON;
125 }
126 #endif
127