1;; Pipeline model for Loongson-3A cores.
2
3;; Copyright (C) 2011-2018 Free Software Foundation, Inc.
4;;
5;; This file is part of GCC.
6;;
7;; GCC is free software; you can redistribute it and/or modify it
8;; under the terms of the GNU General Public License as published
9;; by the Free Software Foundation; either version 3, or (at your
10;; option) any later version.
11;;
12;; GCC is distributed in the hope that it will be useful, but WITHOUT
13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15;; License for more details.
16;;
17;; You should have received a copy of the GNU General Public License
18;; along with GCC; see the file COPYING3.  If not see
19;; <http://www.gnu.org/licenses/>.
20
21;; Uncomment the following line to output automata for debugging.
22;; (automata_option "v")
23
24;; Automaton for integer instructions.
25(define_automaton "ls3a_a_alu")
26
27;; Automaton for floating-point instructions.
28(define_automaton "ls3a_a_falu")
29
30;; Automaton for memory operations.
31(define_automaton "ls3a_a_mem")
32
33;; Describe the resources.
34
35(define_cpu_unit "ls3a_alu1" "ls3a_a_alu")
36(define_cpu_unit "ls3a_alu2" "ls3a_a_alu")
37(define_cpu_unit "ls3a_mem" "ls3a_a_mem")
38(define_cpu_unit "ls3a_falu1" "ls3a_a_falu")
39(define_cpu_unit "ls3a_falu2" "ls3a_a_falu")
40
41;; Describe instruction reservations.
42
43(define_insn_reservation "ls3a_arith" 1
44  (and (eq_attr "cpu" "loongson_3a")
45       (eq_attr "type" "arith,clz,const,logical,
46                        move,nop,shift,signext,slt"))
47  "ls3a_alu1 | ls3a_alu2")
48
49(define_insn_reservation "ls3a_branch" 1
50  (and (eq_attr "cpu" "loongson_3a")
51       (eq_attr "type" "branch,jump,call,condmove,trap"))
52  "ls3a_alu1")
53
54(define_insn_reservation "ls3a_mfhilo" 1
55  (and (eq_attr "cpu" "loongson_3a")
56       (eq_attr "type" "mfhi,mflo,mthi,mtlo"))
57  "ls3a_alu2")
58
59;; Operation imul3nc is fully pipelined.
60(define_insn_reservation "ls3a_imul3nc" 5
61  (and (eq_attr "cpu" "loongson_3a")
62       (eq_attr "type" "imul3nc"))
63  "ls3a_alu2")
64
65(define_insn_reservation "ls3a_imul" 7
66  (and (eq_attr "cpu" "loongson_3a")
67       (eq_attr "type" "imul,imadd"))
68  "ls3a_alu2 * 7")
69
70(define_insn_reservation "ls3a_idiv_si" 12
71  (and (eq_attr "cpu" "loongson_3a")
72       (and (eq_attr "type" "idiv")
73            (eq_attr "mode" "SI")))
74  "ls3a_alu2 * 12")
75
76(define_insn_reservation "ls3a_idiv_di" 25
77  (and (eq_attr "cpu" "loongson_3a")
78       (and (eq_attr "type" "idiv")
79            (eq_attr "mode" "DI")))
80  "ls3a_alu2 * 25")
81
82(define_insn_reservation "ls3a_load" 3
83  (and (eq_attr "cpu" "loongson_3a")
84       (eq_attr "type" "load"))
85  "ls3a_mem")
86
87(define_insn_reservation "ls3a_fpload" 4
88  (and (eq_attr "cpu" "loongson_3a")
89       (eq_attr "type" "load,mfc,mtc"))
90  "ls3a_mem")
91
92(define_insn_reservation "ls3a_prefetch" 0
93  (and (eq_attr "cpu" "loongson_3a")
94       (eq_attr "type" "prefetch,prefetchx"))
95  "ls3a_mem")
96
97(define_insn_reservation "ls3a_store" 0
98  (and (eq_attr "cpu" "loongson_3a")
99       (eq_attr "type" "store,fpstore,fpidxstore"))
100  "ls3a_mem")
101
102;; All the fp operations can be executed in FALU1.  Only fp add,
103;; sub, mul, madd can be executed in FALU2.  Try FALU2 firstly.
104(define_insn_reservation "ls3a_fadd" 6
105  (and (eq_attr "cpu" "loongson_3a")
106       (eq_attr "type" "fadd,fmul,fmadd"))
107  "ls3a_falu2 | ls3a_falu1")
108
109(define_insn_reservation "ls3a_fcmp" 2
110  (and (eq_attr "cpu" "loongson_3a")
111       (eq_attr "type" "fabs,fcmp,fmove,fneg"))
112  "ls3a_falu1")
113
114(define_insn_reservation "ls3a_fcvt" 4
115  (and (eq_attr "cpu" "loongson_3a")
116       (eq_attr "type" "fcvt"))
117  "ls3a_falu1")
118
119(define_insn_reservation "ls3a_fdiv_sf" 12
120  (and (eq_attr "cpu" "loongson_3a")
121       (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt")
122            (eq_attr "mode" "SF")))
123  "ls3a_falu1 * 12")
124
125(define_insn_reservation "ls3a_fdiv_df" 19
126  (and (eq_attr "cpu" "loongson_3a")
127       (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt")
128            (eq_attr "mode" "DF")))
129  "ls3a_falu1 * 19")
130
131;; Force single-dispatch for unknown or multi.
132(define_insn_reservation "ls3a_unknown" 1
133  (and (eq_attr "cpu" "loongson_3a")
134       (eq_attr "type" "unknown,multi,atomic,syncloop"))
135  "ls3a_alu1 + ls3a_alu2 + ls3a_falu1 + ls3a_falu2 + ls3a_mem")
136
137;; End of DFA-based pipeline description for loongson_3a
138