1 /* Definitions for option handling of Andes NDS32 cpu for GNU compiler
2    Copyright (C) 2012-2018 Free Software Foundation, Inc.
3    Contributed by Andes Technology Corporation.
4 
5    This file is part of GCC.
6 
7    GCC is free software; you can redistribute it and/or modify it
8    under the terms of the GNU General Public License as published
9    by the Free Software Foundation; either version 3, or (at your
10    option) any later version.
11 
12    GCC is distributed in the hope that it will be useful, but WITHOUT
13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15    License for more details.
16 
17    You should have received a copy of the GNU General Public License
18    along with GCC; see the file COPYING3.  If not see
19    <http://www.gnu.org/licenses/>.  */
20 
21 #ifndef NDS32_OPTS_H
22 #define NDS32_OPTS_H
23 
24 #define NDS32_DEFAULT_CACHE_BLOCK_SIZE 16
25 #define NDS32_DEFAULT_ISR_VECTOR_SIZE (TARGET_ISA_V3 ? 4 : 16)
26 
27 /* The various ANDES ISA.  */
28 enum nds32_arch_type
29 {
30   ARCH_V2,
31   ARCH_V3,
32   ARCH_V3M,
33   ARCH_V3F,
34   ARCH_V3S
35 };
36 
37 /* The various ANDES CPU.  */
38 enum nds32_cpu_type
39 {
40   CPU_N6,
41   CPU_N7,
42   CPU_N8,
43   CPU_E8,
44   CPU_N9,
45   CPU_SIMPLE
46 };
47 
48 /* The code model defines the address generation strategy.  */
49 enum nds32_cmodel_type
50 {
51   CMODEL_SMALL,
52   CMODEL_MEDIUM,
53   CMODEL_LARGE
54 };
55 
56 /* Multiply instruction configuration.  */
57 enum nds32_mul_type
58 {
59   MUL_TYPE_FAST_1,
60   MUL_TYPE_FAST_2,
61   MUL_TYPE_SLOW
62 };
63 
64 /* Register ports configuration.  */
65 enum nds32_register_ports
66 {
67   REG_PORT_3R2W,
68   REG_PORT_2R1W
69 };
70 
71 /* Which ABI to use.  */
72 enum abi_type
73 {
74   NDS32_ABI_V2,
75   NDS32_ABI_V2_FP_PLUS
76 };
77 
78 /* The various FPU number of registers.  */
79 enum float_reg_number
80 {
81   NDS32_CONFIG_FPU_0,
82   NDS32_CONFIG_FPU_1,
83   NDS32_CONFIG_FPU_2,
84   NDS32_CONFIG_FPU_3,
85   NDS32_CONFIG_FPU_4,
86   NDS32_CONFIG_FPU_5,
87   NDS32_CONFIG_FPU_6,
88   NDS32_CONFIG_FPU_7
89 };
90 
91 #endif
92