1 /* Definitions of target machine for GNU compiler, for IBM RS/6000. 2 Copyright (C) 1992-2018 Free Software Foundation, Inc. 3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published 9 by the Free Software Foundation; either version 3, or (at your 10 option) any later version. 11 12 GCC is distributed in the hope that it will be useful, but WITHOUT 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 License for more details. 16 17 Under Section 7 of GPL version 3, you are granted additional 18 permissions described in the GCC Runtime Library Exception, version 19 3.1, as published by the Free Software Foundation. 20 21 You should have received a copy of the GNU General Public License and 22 a copy of the GCC Runtime Library Exception along with this program; 23 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 24 <http://www.gnu.org/licenses/>. */ 25 26 /* Note that some other tm.h files include this one and then override 27 many of the definitions. */ 28 29 #ifndef RS6000_OPTS_H 30 #include "config/rs6000/rs6000-opts.h" 31 #endif 32 33 /* 128-bit floating point precision values. */ 34 #ifndef RS6000_MODES_H 35 #include "config/rs6000/rs6000-modes.h" 36 #endif 37 38 /* Definitions for the object file format. These are set at 39 compile-time. */ 40 41 #define OBJECT_XCOFF 1 42 #define OBJECT_ELF 2 43 #define OBJECT_PEF 3 44 #define OBJECT_MACHO 4 45 46 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF) 47 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF) 48 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF) 49 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO) 50 51 #ifndef TARGET_AIX 52 #define TARGET_AIX 0 53 #endif 54 55 #ifndef TARGET_AIX_OS 56 #define TARGET_AIX_OS 0 57 #endif 58 59 /* Control whether function entry points use a "dot" symbol when 60 ABI_AIX. */ 61 #define DOT_SYMBOLS 1 62 63 /* Default string to use for cpu if not specified. */ 64 #ifndef TARGET_CPU_DEFAULT 65 #define TARGET_CPU_DEFAULT ((char *)0) 66 #endif 67 68 /* If configured for PPC405, support PPC405CR Erratum77. */ 69 #ifdef CONFIG_PPC405CR 70 #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405) 71 #else 72 #define PPC405_ERRATUM77 0 73 #endif 74 75 #ifndef TARGET_PAIRED_FLOAT 76 #define TARGET_PAIRED_FLOAT 0 77 #endif 78 79 #ifdef HAVE_AS_POPCNTB 80 #define ASM_CPU_POWER5_SPEC "-mpower5" 81 #else 82 #define ASM_CPU_POWER5_SPEC "-mpower4" 83 #endif 84 85 #ifdef HAVE_AS_DFP 86 #define ASM_CPU_POWER6_SPEC "-mpower6 -maltivec" 87 #else 88 #define ASM_CPU_POWER6_SPEC "-mpower4 -maltivec" 89 #endif 90 91 #ifdef HAVE_AS_POPCNTD 92 #define ASM_CPU_POWER7_SPEC "-mpower7" 93 #else 94 #define ASM_CPU_POWER7_SPEC "-mpower4 -maltivec" 95 #endif 96 97 #ifdef HAVE_AS_POWER8 98 #define ASM_CPU_POWER8_SPEC "-mpower8" 99 #else 100 #define ASM_CPU_POWER8_SPEC ASM_CPU_POWER7_SPEC 101 #endif 102 103 #ifdef HAVE_AS_POWER9 104 #define ASM_CPU_POWER9_SPEC "-mpower9" 105 #else 106 #define ASM_CPU_POWER9_SPEC ASM_CPU_POWER8_SPEC 107 #endif 108 109 #ifdef HAVE_AS_DCI 110 #define ASM_CPU_476_SPEC "-m476" 111 #else 112 #define ASM_CPU_476_SPEC "-mpower4" 113 #endif 114 115 /* Common ASM definitions used by ASM_SPEC among the various targets for 116 handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to 117 provide the default assembler options if the user uses -mcpu=native, so if 118 you make changes here, make them also there. PR63177: Do not pass -mpower8 119 to the assembler if -mpower9-vector was also used. */ 120 #define ASM_CPU_SPEC \ 121 "%{!mcpu*: \ 122 %{mpowerpc64*: -mppc64} \ 123 %{!mpowerpc64*: %(asm_default)}} \ 124 %{mcpu=native: %(asm_cpu_native)} \ 125 %{mcpu=cell: -mcell} \ 126 %{mcpu=power3: -mppc64} \ 127 %{mcpu=power4: -mpower4} \ 128 %{mcpu=power5: %(asm_cpu_power5)} \ 129 %{mcpu=power5+: %(asm_cpu_power5)} \ 130 %{mcpu=power6: %(asm_cpu_power6) -maltivec} \ 131 %{mcpu=power6x: %(asm_cpu_power6) -maltivec} \ 132 %{mcpu=power7: %(asm_cpu_power7)} \ 133 %{mcpu=power8: %{!mpower9-vector: %(asm_cpu_power8)}} \ 134 %{mcpu=power9: %(asm_cpu_power9)} \ 135 %{mcpu=a2: -ma2} \ 136 %{mcpu=powerpc: -mppc} \ 137 %{mcpu=powerpc64le: %(asm_cpu_power8)} \ 138 %{mcpu=rs64a: -mppc64} \ 139 %{mcpu=401: -mppc} \ 140 %{mcpu=403: -m403} \ 141 %{mcpu=405: -m405} \ 142 %{mcpu=405fp: -m405} \ 143 %{mcpu=440: -m440} \ 144 %{mcpu=440fp: -m440} \ 145 %{mcpu=464: -m440} \ 146 %{mcpu=464fp: -m440} \ 147 %{mcpu=476: %(asm_cpu_476)} \ 148 %{mcpu=476fp: %(asm_cpu_476)} \ 149 %{mcpu=505: -mppc} \ 150 %{mcpu=601: -m601} \ 151 %{mcpu=602: -mppc} \ 152 %{mcpu=603: -mppc} \ 153 %{mcpu=603e: -mppc} \ 154 %{mcpu=ec603e: -mppc} \ 155 %{mcpu=604: -mppc} \ 156 %{mcpu=604e: -mppc} \ 157 %{mcpu=620: -mppc64} \ 158 %{mcpu=630: -mppc64} \ 159 %{mcpu=740: -mppc} \ 160 %{mcpu=750: -mppc} \ 161 %{mcpu=G3: -mppc} \ 162 %{mcpu=7400: -mppc -maltivec} \ 163 %{mcpu=7450: -mppc -maltivec} \ 164 %{mcpu=G4: -mppc -maltivec} \ 165 %{mcpu=801: -mppc} \ 166 %{mcpu=821: -mppc} \ 167 %{mcpu=823: -mppc} \ 168 %{mcpu=860: -mppc} \ 169 %{mcpu=970: -mpower4 -maltivec} \ 170 %{mcpu=G5: -mpower4 -maltivec} \ 171 %{mcpu=8540: -me500} \ 172 %{mcpu=8548: -me500} \ 173 %{mcpu=e300c2: -me300} \ 174 %{mcpu=e300c3: -me300} \ 175 %{mcpu=e500mc: -me500mc} \ 176 %{mcpu=e500mc64: -me500mc64} \ 177 %{mcpu=e5500: -me5500} \ 178 %{mcpu=e6500: -me6500} \ 179 %{maltivec: -maltivec} \ 180 %{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: %(asm_cpu_power7)}} \ 181 %{mpower8-vector|mcrypto|mdirect-move|mhtm: %{!mcpu*: %(asm_cpu_power8)}} \ 182 %{mpower9-vector: %{!mcpu*|mcpu=power8: %(asm_cpu_power9)}} \ 183 -many" 184 185 #define CPP_DEFAULT_SPEC "" 186 187 #define ASM_DEFAULT_SPEC "" 188 189 /* This macro defines names of additional specifications to put in the specs 190 that can be used in various specifications like CC1_SPEC. Its definition 191 is an initializer with a subgrouping for each command option. 192 193 Each subgrouping contains a string constant, that defines the 194 specification name, and a string constant that used by the GCC driver 195 program. 196 197 Do not define this macro if it does not need to do anything. */ 198 199 #define SUBTARGET_EXTRA_SPECS 200 201 #define EXTRA_SPECS \ 202 { "cpp_default", CPP_DEFAULT_SPEC }, \ 203 { "asm_cpu", ASM_CPU_SPEC }, \ 204 { "asm_cpu_native", ASM_CPU_NATIVE_SPEC }, \ 205 { "asm_default", ASM_DEFAULT_SPEC }, \ 206 { "cc1_cpu", CC1_CPU_SPEC }, \ 207 { "asm_cpu_power5", ASM_CPU_POWER5_SPEC }, \ 208 { "asm_cpu_power6", ASM_CPU_POWER6_SPEC }, \ 209 { "asm_cpu_power7", ASM_CPU_POWER7_SPEC }, \ 210 { "asm_cpu_power8", ASM_CPU_POWER8_SPEC }, \ 211 { "asm_cpu_power9", ASM_CPU_POWER9_SPEC }, \ 212 { "asm_cpu_476", ASM_CPU_476_SPEC }, \ 213 SUBTARGET_EXTRA_SPECS 214 215 /* -mcpu=native handling only makes sense with compiler running on 216 an PowerPC chip. If changing this condition, also change 217 the condition in driver-rs6000.c. */ 218 #if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX) 219 /* In driver-rs6000.c. */ 220 extern const char *host_detect_local_cpu (int argc, const char **argv); 221 #define EXTRA_SPEC_FUNCTIONS \ 222 { "local_cpu_detect", host_detect_local_cpu }, 223 #define HAVE_LOCAL_CPU_DETECT 224 #define ASM_CPU_NATIVE_SPEC "%:local_cpu_detect(asm)" 225 226 #else 227 #define ASM_CPU_NATIVE_SPEC "%(asm_default)" 228 #endif 229 230 #ifndef CC1_CPU_SPEC 231 #ifdef HAVE_LOCAL_CPU_DETECT 232 #define CC1_CPU_SPEC \ 233 "%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \ 234 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" 235 #else 236 #define CC1_CPU_SPEC "" 237 #endif 238 #endif 239 240 /* Architecture type. */ 241 242 /* Define TARGET_MFCRF if the target assembler does not support the 243 optional field operand for mfcr. */ 244 245 #ifndef HAVE_AS_MFCRF 246 #undef TARGET_MFCRF 247 #define TARGET_MFCRF 0 248 #endif 249 250 /* Define TARGET_POPCNTB if the target assembler does not support the 251 popcount byte instruction. */ 252 253 #ifndef HAVE_AS_POPCNTB 254 #undef TARGET_POPCNTB 255 #define TARGET_POPCNTB 0 256 #endif 257 258 /* Define TARGET_FPRND if the target assembler does not support the 259 fp rounding instructions. */ 260 261 #ifndef HAVE_AS_FPRND 262 #undef TARGET_FPRND 263 #define TARGET_FPRND 0 264 #endif 265 266 /* Define TARGET_CMPB if the target assembler does not support the 267 cmpb instruction. */ 268 269 #ifndef HAVE_AS_CMPB 270 #undef TARGET_CMPB 271 #define TARGET_CMPB 0 272 #endif 273 274 /* Define TARGET_MFPGPR if the target assembler does not support the 275 mffpr and mftgpr instructions. */ 276 277 #ifndef HAVE_AS_MFPGPR 278 #undef TARGET_MFPGPR 279 #define TARGET_MFPGPR 0 280 #endif 281 282 /* Define TARGET_DFP if the target assembler does not support decimal 283 floating point instructions. */ 284 #ifndef HAVE_AS_DFP 285 #undef TARGET_DFP 286 #define TARGET_DFP 0 287 #endif 288 289 /* Define TARGET_POPCNTD if the target assembler does not support the 290 popcount word and double word instructions. */ 291 292 #ifndef HAVE_AS_POPCNTD 293 #undef TARGET_POPCNTD 294 #define TARGET_POPCNTD 0 295 #endif 296 297 /* Define the ISA 2.07 flags as 0 if the target assembler does not support the 298 waitasecond instruction. Allow -mpower8-fusion, since it does not add new 299 instructions. */ 300 301 #ifndef HAVE_AS_POWER8 302 #undef TARGET_DIRECT_MOVE 303 #undef TARGET_CRYPTO 304 #undef TARGET_HTM 305 #undef TARGET_P8_VECTOR 306 #define TARGET_DIRECT_MOVE 0 307 #define TARGET_CRYPTO 0 308 #define TARGET_HTM 0 309 #define TARGET_P8_VECTOR 0 310 #endif 311 312 /* Define the ISA 3.0 flags as 0 if the target assembler does not support 313 Power9 instructions. Allow -mpower9-fusion, since it does not add new 314 instructions. Allow -misel, since it predates ISA 3.0 and does 315 not require any Power9 features. */ 316 317 #ifndef HAVE_AS_POWER9 318 #undef TARGET_FLOAT128_HW 319 #undef TARGET_MODULO 320 #undef TARGET_P9_VECTOR 321 #undef TARGET_P9_MINMAX 322 #undef TARGET_P9_MISC 323 #define TARGET_FLOAT128_HW 0 324 #define TARGET_MODULO 0 325 #define TARGET_P9_VECTOR 0 326 #define TARGET_P9_MINMAX 0 327 #define TARGET_P9_MISC 0 328 #endif 329 330 /* Define TARGET_LWSYNC_INSTRUCTION if the assembler knows about lwsync. If 331 not, generate the lwsync code as an integer constant. */ 332 #ifdef HAVE_AS_LWSYNC 333 #define TARGET_LWSYNC_INSTRUCTION 1 334 #else 335 #define TARGET_LWSYNC_INSTRUCTION 0 336 #endif 337 338 /* Define TARGET_TLS_MARKERS if the target assembler does not support 339 arg markers for __tls_get_addr calls. */ 340 #ifndef HAVE_AS_TLS_MARKERS 341 #undef TARGET_TLS_MARKERS 342 #define TARGET_TLS_MARKERS 0 343 #else 344 #define TARGET_TLS_MARKERS tls_markers 345 #endif 346 347 #ifndef TARGET_SECURE_PLT 348 #define TARGET_SECURE_PLT 0 349 #endif 350 351 #ifndef TARGET_CMODEL 352 #define TARGET_CMODEL CMODEL_SMALL 353 #endif 354 355 #define TARGET_32BIT (! TARGET_64BIT) 356 357 #ifndef HAVE_AS_TLS 358 #define HAVE_AS_TLS 0 359 #endif 360 361 #ifndef TARGET_LINK_STACK 362 #define TARGET_LINK_STACK 0 363 #endif 364 365 #ifndef SET_TARGET_LINK_STACK 366 #define SET_TARGET_LINK_STACK(X) do { } while (0) 367 #endif 368 369 #ifndef TARGET_FLOAT128_ENABLE_TYPE 370 #define TARGET_FLOAT128_ENABLE_TYPE 0 371 #endif 372 373 /* Return 1 for a symbol ref for a thread-local storage symbol. */ 374 #define RS6000_SYMBOL_REF_TLS_P(RTX) \ 375 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0) 376 377 #ifdef IN_LIBGCC2 378 /* For libgcc2 we make sure this is a compile time constant */ 379 #if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__) 380 #undef TARGET_POWERPC64 381 #define TARGET_POWERPC64 1 382 #else 383 #undef TARGET_POWERPC64 384 #define TARGET_POWERPC64 0 385 #endif 386 #else 387 /* The option machinery will define this. */ 388 #endif 389 390 #define TARGET_DEFAULT (MASK_MULTIPLE) 391 392 /* FPU operations supported. 393 Each use of TARGET_SINGLE_FLOAT or TARGET_DOUBLE_FLOAT must 394 also test TARGET_HARD_FLOAT. */ 395 #define TARGET_SINGLE_FLOAT 1 396 #define TARGET_DOUBLE_FLOAT 1 397 #define TARGET_SINGLE_FPU 0 398 #define TARGET_SIMPLE_FPU 0 399 #define TARGET_XILINX_FPU 0 400 401 /* Define generic processor types based upon current deployment. */ 402 #define PROCESSOR_COMMON PROCESSOR_PPC601 403 #define PROCESSOR_POWERPC PROCESSOR_PPC604 404 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A 405 406 /* Define the default processor. This is overridden by other tm.h files. */ 407 #define PROCESSOR_DEFAULT PROCESSOR_PPC603 408 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A 409 410 /* Specify the dialect of assembler to use. Only new mnemonics are supported 411 starting with GCC 4.8, i.e. just one dialect, but for backwards 412 compatibility with older inline asm ASSEMBLER_DIALECT needs to be 413 defined. */ 414 #define ASSEMBLER_DIALECT 1 415 416 /* Debug support */ 417 #define MASK_DEBUG_STACK 0x01 /* debug stack applications */ 418 #define MASK_DEBUG_ARG 0x02 /* debug argument handling */ 419 #define MASK_DEBUG_REG 0x04 /* debug register handling */ 420 #define MASK_DEBUG_ADDR 0x08 /* debug memory addressing */ 421 #define MASK_DEBUG_COST 0x10 /* debug rtx codes */ 422 #define MASK_DEBUG_TARGET 0x20 /* debug target attribute/pragma */ 423 #define MASK_DEBUG_BUILTIN 0x40 /* debug builtins */ 424 #define MASK_DEBUG_ALL (MASK_DEBUG_STACK \ 425 | MASK_DEBUG_ARG \ 426 | MASK_DEBUG_REG \ 427 | MASK_DEBUG_ADDR \ 428 | MASK_DEBUG_COST \ 429 | MASK_DEBUG_TARGET \ 430 | MASK_DEBUG_BUILTIN) 431 432 #define TARGET_DEBUG_STACK (rs6000_debug & MASK_DEBUG_STACK) 433 #define TARGET_DEBUG_ARG (rs6000_debug & MASK_DEBUG_ARG) 434 #define TARGET_DEBUG_REG (rs6000_debug & MASK_DEBUG_REG) 435 #define TARGET_DEBUG_ADDR (rs6000_debug & MASK_DEBUG_ADDR) 436 #define TARGET_DEBUG_COST (rs6000_debug & MASK_DEBUG_COST) 437 #define TARGET_DEBUG_TARGET (rs6000_debug & MASK_DEBUG_TARGET) 438 #define TARGET_DEBUG_BUILTIN (rs6000_debug & MASK_DEBUG_BUILTIN) 439 440 /* Helper macros for TFmode. Quad floating point (TFmode) can be either IBM 441 long double format that uses a pair of doubles, or IEEE 128-bit floating 442 point. KFmode was added as a way to represent IEEE 128-bit floating point, 443 even if the default for long double is the IBM long double format. 444 Similarly IFmode is the IBM long double format even if the default is IEEE 445 128-bit. Don't allow IFmode if -msoft-float. */ 446 #define FLOAT128_IEEE_P(MODE) \ 447 ((TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 \ 448 && ((MODE) == TFmode || (MODE) == TCmode)) \ 449 || ((MODE) == KFmode) || ((MODE) == KCmode)) 450 451 #define FLOAT128_IBM_P(MODE) \ 452 ((!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 \ 453 && ((MODE) == TFmode || (MODE) == TCmode)) \ 454 || (TARGET_HARD_FLOAT && ((MODE) == IFmode || (MODE) == ICmode))) 455 456 /* Helper macros to say whether a 128-bit floating point type can go in a 457 single vector register, or whether it needs paired scalar values. */ 458 #define FLOAT128_VECTOR_P(MODE) (TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE)) 459 460 #define FLOAT128_2REG_P(MODE) \ 461 (FLOAT128_IBM_P (MODE) \ 462 || ((MODE) == TDmode) \ 463 || (!TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE))) 464 465 /* Return true for floating point that does not use a vector register. */ 466 #define SCALAR_FLOAT_MODE_NOT_VECTOR_P(MODE) \ 467 (SCALAR_FLOAT_MODE_P (MODE) && !FLOAT128_VECTOR_P (MODE)) 468 469 /* Describe the vector unit used for arithmetic operations. */ 470 extern enum rs6000_vector rs6000_vector_unit[]; 471 472 #define VECTOR_UNIT_NONE_P(MODE) \ 473 (rs6000_vector_unit[(MODE)] == VECTOR_NONE) 474 475 #define VECTOR_UNIT_VSX_P(MODE) \ 476 (rs6000_vector_unit[(MODE)] == VECTOR_VSX) 477 478 #define VECTOR_UNIT_P8_VECTOR_P(MODE) \ 479 (rs6000_vector_unit[(MODE)] == VECTOR_P8_VECTOR) 480 481 #define VECTOR_UNIT_ALTIVEC_P(MODE) \ 482 (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC) 483 484 #define VECTOR_UNIT_VSX_OR_P8_VECTOR_P(MODE) \ 485 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \ 486 (int)VECTOR_VSX, \ 487 (int)VECTOR_P8_VECTOR)) 488 489 /* VECTOR_UNIT_ALTIVEC_OR_VSX_P is used in places where we are using either 490 altivec (VMX) or VSX vector instructions. P8 vector support is upwards 491 compatible, so allow it as well, rather than changing all of the uses of the 492 macro. */ 493 #define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \ 494 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \ 495 (int)VECTOR_ALTIVEC, \ 496 (int)VECTOR_P8_VECTOR)) 497 498 /* Describe whether to use VSX loads or Altivec loads. For now, just use the 499 same unit as the vector unit we are using, but we may want to migrate to 500 using VSX style loads even for types handled by altivec. */ 501 extern enum rs6000_vector rs6000_vector_mem[]; 502 503 #define VECTOR_MEM_NONE_P(MODE) \ 504 (rs6000_vector_mem[(MODE)] == VECTOR_NONE) 505 506 #define VECTOR_MEM_VSX_P(MODE) \ 507 (rs6000_vector_mem[(MODE)] == VECTOR_VSX) 508 509 #define VECTOR_MEM_P8_VECTOR_P(MODE) \ 510 (rs6000_vector_mem[(MODE)] == VECTOR_VSX) 511 512 #define VECTOR_MEM_ALTIVEC_P(MODE) \ 513 (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC) 514 515 #define VECTOR_MEM_VSX_OR_P8_VECTOR_P(MODE) \ 516 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \ 517 (int)VECTOR_VSX, \ 518 (int)VECTOR_P8_VECTOR)) 519 520 #define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \ 521 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \ 522 (int)VECTOR_ALTIVEC, \ 523 (int)VECTOR_P8_VECTOR)) 524 525 /* Return the alignment of a given vector type, which is set based on the 526 vector unit use. VSX for instance can load 32 or 64 bit aligned words 527 without problems, while Altivec requires 128-bit aligned vectors. */ 528 extern int rs6000_vector_align[]; 529 530 #define VECTOR_ALIGN(MODE) \ 531 ((rs6000_vector_align[(MODE)] != 0) \ 532 ? rs6000_vector_align[(MODE)] \ 533 : (int)GET_MODE_BITSIZE ((MODE))) 534 535 /* Determine the element order to use for vector instructions. By 536 default we use big-endian element order when targeting big-endian, 537 and little-endian element order when targeting little-endian. For 538 programs being ported from BE Power to LE Power, it can sometimes 539 be useful to use big-endian element order when targeting little-endian. 540 This is set via -maltivec=be, for example. */ 541 #define VECTOR_ELT_ORDER_BIG \ 542 (BYTES_BIG_ENDIAN || (rs6000_altivec_element_order == 2)) 543 544 /* Element number of the 64-bit value in a 128-bit vector that can be accessed 545 with scalar instructions. */ 546 #define VECTOR_ELEMENT_SCALAR_64BIT ((BYTES_BIG_ENDIAN) ? 0 : 1) 547 548 /* Element number of the 64-bit value in a 128-bit vector that can be accessed 549 with the ISA 3.0 MFVSRLD instructions. */ 550 #define VECTOR_ELEMENT_MFVSRLD_64BIT ((BYTES_BIG_ENDIAN) ? 1 : 0) 551 552 /* Alignment options for fields in structures for sub-targets following 553 AIX-like ABI. 554 ALIGN_POWER word-aligns FP doubles (default AIX ABI). 555 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size). 556 557 Override the macro definitions when compiling libobjc to avoid undefined 558 reference to rs6000_alignment_flags due to library's use of GCC alignment 559 macros which use the macros below. */ 560 561 #ifndef IN_TARGET_LIBS 562 #define MASK_ALIGN_POWER 0x00000000 563 #define MASK_ALIGN_NATURAL 0x00000001 564 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL) 565 #else 566 #define TARGET_ALIGN_NATURAL 0 567 #endif 568 569 /* We use values 126..128 to pick the appropriate long double type (IFmode, 570 KFmode, TFmode). */ 571 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size > 64) 572 #define TARGET_IEEEQUAD rs6000_ieeequad 573 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi 574 #define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL) 575 576 /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only. 577 Enable 32-bit fcfid's on any of the switches for newer ISA machines or 578 XILINX. */ 579 #define TARGET_FCFID (TARGET_POWERPC64 \ 580 || TARGET_PPC_GPOPT /* 970/power4 */ \ 581 || TARGET_POPCNTB /* ISA 2.02 */ \ 582 || TARGET_CMPB /* ISA 2.05 */ \ 583 || TARGET_POPCNTD /* ISA 2.06 */ \ 584 || TARGET_XILINX_FPU) 585 586 #define TARGET_FCTIDZ TARGET_FCFID 587 #define TARGET_STFIWX TARGET_PPC_GFXOPT 588 #define TARGET_LFIWAX TARGET_CMPB 589 #define TARGET_LFIWZX TARGET_POPCNTD 590 #define TARGET_FCFIDS TARGET_POPCNTD 591 #define TARGET_FCFIDU TARGET_POPCNTD 592 #define TARGET_FCFIDUS TARGET_POPCNTD 593 #define TARGET_FCTIDUZ TARGET_POPCNTD 594 #define TARGET_FCTIWUZ TARGET_POPCNTD 595 #define TARGET_CTZ TARGET_MODULO 596 #define TARGET_EXTSWSLI (TARGET_MODULO && TARGET_POWERPC64) 597 #define TARGET_MADDLD (TARGET_MODULO && TARGET_POWERPC64) 598 599 #define TARGET_XSCVDPSPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR) 600 #define TARGET_XSCVSPDPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR) 601 #define TARGET_VADDUQM (TARGET_P8_VECTOR && TARGET_POWERPC64) 602 #define TARGET_DIRECT_MOVE_128 (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \ 603 && TARGET_POWERPC64) 604 #define TARGET_VEXTRACTUB (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \ 605 && TARGET_POWERPC64) 606 607 /* Whether we should avoid (SUBREG:SI (REG:SF) and (SUBREG:SF (REG:SI). */ 608 #define TARGET_NO_SF_SUBREG TARGET_DIRECT_MOVE_64BIT 609 #define TARGET_ALLOW_SF_SUBREG (!TARGET_DIRECT_MOVE_64BIT) 610 611 /* This wants to be set for p8 and newer. On p7, overlapping unaligned 612 loads are slow. */ 613 #define TARGET_EFFICIENT_OVERLAPPING_UNALIGNED TARGET_EFFICIENT_UNALIGNED_VSX 614 615 /* Byte/char syncs were added as phased in for ISA 2.06B, but are not present 616 in power7, so conditionalize them on p8 features. TImode syncs need quad 617 memory support. */ 618 #define TARGET_SYNC_HI_QI (TARGET_QUAD_MEMORY \ 619 || TARGET_QUAD_MEMORY_ATOMIC \ 620 || TARGET_DIRECT_MOVE) 621 622 #define TARGET_SYNC_TI TARGET_QUAD_MEMORY_ATOMIC 623 624 /* Power7 has both 32-bit load and store integer for the FPRs, so we don't need 625 to allocate the SDmode stack slot to get the value into the proper location 626 in the register. */ 627 #define TARGET_NO_SDMODE_STACK (TARGET_LFIWZX && TARGET_STFIWX && TARGET_DFP) 628 629 /* ISA 3.0 has new min/max functions that don't need fast math that are being 630 phased in. Min/max using FSEL or XSMAXDP/XSMINDP do not return the correct 631 answers if the arguments are not in the normal range. */ 632 #define TARGET_MINMAX_SF (TARGET_SF_FPR && TARGET_PPC_GFXOPT \ 633 && (TARGET_P9_MINMAX || !flag_trapping_math)) 634 635 #define TARGET_MINMAX_DF (TARGET_DF_FPR && TARGET_PPC_GFXOPT \ 636 && (TARGET_P9_MINMAX || !flag_trapping_math)) 637 638 /* In switching from using target_flags to using rs6000_isa_flags, the options 639 machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map 640 OPTION_MASK_<xxx> back into MASK_<xxx>. */ 641 #define MASK_ALTIVEC OPTION_MASK_ALTIVEC 642 #define MASK_CMPB OPTION_MASK_CMPB 643 #define MASK_CRYPTO OPTION_MASK_CRYPTO 644 #define MASK_DFP OPTION_MASK_DFP 645 #define MASK_DIRECT_MOVE OPTION_MASK_DIRECT_MOVE 646 #define MASK_DLMZB OPTION_MASK_DLMZB 647 #define MASK_EABI OPTION_MASK_EABI 648 #define MASK_FLOAT128_KEYWORD OPTION_MASK_FLOAT128_KEYWORD 649 #define MASK_FLOAT128_HW OPTION_MASK_FLOAT128_HW 650 #define MASK_FPRND OPTION_MASK_FPRND 651 #define MASK_P8_FUSION OPTION_MASK_P8_FUSION 652 #define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT 653 #define MASK_HTM OPTION_MASK_HTM 654 #define MASK_ISEL OPTION_MASK_ISEL 655 #define MASK_MFCRF OPTION_MASK_MFCRF 656 #define MASK_MFPGPR OPTION_MASK_MFPGPR 657 #define MASK_MULHW OPTION_MASK_MULHW 658 #define MASK_MULTIPLE OPTION_MASK_MULTIPLE 659 #define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE 660 #define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR 661 #define MASK_P9_VECTOR OPTION_MASK_P9_VECTOR 662 #define MASK_P9_MISC OPTION_MASK_P9_MISC 663 #define MASK_POPCNTB OPTION_MASK_POPCNTB 664 #define MASK_POPCNTD OPTION_MASK_POPCNTD 665 #define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT 666 #define MASK_PPC_GPOPT OPTION_MASK_PPC_GPOPT 667 #define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION 668 #define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT 669 #define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN 670 #define MASK_UPDATE OPTION_MASK_UPDATE 671 #define MASK_VSX OPTION_MASK_VSX 672 673 #ifndef IN_LIBGCC2 674 #define MASK_POWERPC64 OPTION_MASK_POWERPC64 675 #endif 676 677 #ifdef TARGET_64BIT 678 #define MASK_64BIT OPTION_MASK_64BIT 679 #endif 680 681 #ifdef TARGET_LITTLE_ENDIAN 682 #define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN 683 #endif 684 685 #ifdef TARGET_REGNAMES 686 #define MASK_REGNAMES OPTION_MASK_REGNAMES 687 #endif 688 689 #ifdef TARGET_PROTOTYPE 690 #define MASK_PROTOTYPE OPTION_MASK_PROTOTYPE 691 #endif 692 693 #ifdef TARGET_MODULO 694 #define RS6000_BTM_MODULO OPTION_MASK_MODULO 695 #endif 696 697 698 /* For power systems, we want to enable Altivec and VSX builtins even if the 699 user did not use -maltivec or -mvsx to allow the builtins to be used inside 700 of #pragma GCC target or the target attribute to change the code level for a 701 given system. The Paired builtins are only enabled if you configure the 702 compiler for those builtins, and those machines don't support altivec or 703 VSX. */ 704 705 #define TARGET_EXTRA_BUILTINS (!TARGET_PAIRED_FLOAT \ 706 && ((TARGET_POWERPC64 \ 707 || TARGET_PPC_GPOPT /* 970/power4 */ \ 708 || TARGET_POPCNTB /* ISA 2.02 */ \ 709 || TARGET_CMPB /* ISA 2.05 */ \ 710 || TARGET_POPCNTD /* ISA 2.06 */ \ 711 || TARGET_ALTIVEC \ 712 || TARGET_VSX \ 713 || TARGET_HARD_FLOAT))) 714 715 /* E500 cores only support plain "sync", not lwsync. */ 716 #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \ 717 || rs6000_cpu == PROCESSOR_PPC8548) 718 719 720 /* Whether SF/DF operations are supported by the normal floating point unit 721 (or the vector/scalar unit). */ 722 #define TARGET_SF_FPR (TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT) 723 #define TARGET_DF_FPR (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) 724 725 /* Whether SF/DF operations are supported by any hardware. */ 726 #define TARGET_SF_INSN TARGET_SF_FPR 727 #define TARGET_DF_INSN TARGET_DF_FPR 728 729 /* Which machine supports the various reciprocal estimate instructions. */ 730 #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \ 731 && TARGET_SINGLE_FLOAT) 732 733 #define TARGET_FRE (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT \ 734 && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode))) 735 736 #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \ 737 && TARGET_PPC_GFXOPT && TARGET_SINGLE_FLOAT) 738 739 #define TARGET_FRSQRTE (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT \ 740 && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode))) 741 742 /* Conditions to allow TOC fusion for loading/storing integers. */ 743 #define TARGET_TOC_FUSION_INT (TARGET_P8_FUSION \ 744 && TARGET_TOC_FUSION \ 745 && (TARGET_CMODEL != CMODEL_SMALL) \ 746 && TARGET_POWERPC64) 747 748 /* Conditions to allow TOC fusion for loading/storing floating point. */ 749 #define TARGET_TOC_FUSION_FP (TARGET_P9_FUSION \ 750 && TARGET_TOC_FUSION \ 751 && (TARGET_CMODEL != CMODEL_SMALL) \ 752 && TARGET_POWERPC64 \ 753 && TARGET_HARD_FLOAT \ 754 && TARGET_SINGLE_FLOAT \ 755 && TARGET_DOUBLE_FLOAT) 756 757 /* Macro to say whether we can do optimizations where we need to do parts of 758 the calculation in 64-bit GPRs and then is transfered to the vector 759 registers. Do not allow -maltivec=be for these optimizations, because it 760 adds to the complexity of the code. */ 761 #define TARGET_DIRECT_MOVE_64BIT (TARGET_DIRECT_MOVE \ 762 && TARGET_P8_VECTOR \ 763 && TARGET_POWERPC64 \ 764 && (rs6000_altivec_element_order != 2)) 765 766 /* Whether the various reciprocal divide/square root estimate instructions 767 exist, and whether we should automatically generate code for the instruction 768 by default. */ 769 #define RS6000_RECIP_MASK_HAVE_RE 0x1 /* have RE instruction. */ 770 #define RS6000_RECIP_MASK_AUTO_RE 0x2 /* generate RE by default. */ 771 #define RS6000_RECIP_MASK_HAVE_RSQRTE 0x4 /* have RSQRTE instruction. */ 772 #define RS6000_RECIP_MASK_AUTO_RSQRTE 0x8 /* gen. RSQRTE by default. */ 773 774 extern unsigned char rs6000_recip_bits[]; 775 776 #define RS6000_RECIP_HAVE_RE_P(MODE) \ 777 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RE) 778 779 #define RS6000_RECIP_AUTO_RE_P(MODE) \ 780 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RE) 781 782 #define RS6000_RECIP_HAVE_RSQRTE_P(MODE) \ 783 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RSQRTE) 784 785 #define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \ 786 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE) 787 788 /* The default CPU for TARGET_OPTION_OVERRIDE. */ 789 #define OPTION_TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT 790 791 /* Target pragma. */ 792 #define REGISTER_TARGET_PRAGMAS() do { \ 793 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \ 794 targetm.target_option.pragma_parse = rs6000_pragma_target_parse; \ 795 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \ 796 rs6000_target_modify_macros_ptr = rs6000_target_modify_macros; \ 797 } while (0) 798 799 /* Target #defines. */ 800 #define TARGET_CPU_CPP_BUILTINS() \ 801 rs6000_cpu_cpp_builtins (pfile) 802 803 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order 804 we're compiling for. Some configurations may need to override it. */ 805 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \ 806 do \ 807 { \ 808 if (BYTES_BIG_ENDIAN) \ 809 { \ 810 builtin_define ("__BIG_ENDIAN__"); \ 811 builtin_define ("_BIG_ENDIAN"); \ 812 builtin_assert ("machine=bigendian"); \ 813 } \ 814 else \ 815 { \ 816 builtin_define ("__LITTLE_ENDIAN__"); \ 817 builtin_define ("_LITTLE_ENDIAN"); \ 818 builtin_assert ("machine=littleendian"); \ 819 } \ 820 } \ 821 while (0) 822 823 /* Target machine storage layout. */ 824 825 /* Define this macro if it is advisable to hold scalars in registers 826 in a wider mode than that declared by the program. In such cases, 827 the value is constrained to be within the bounds of the declared 828 type, but kept valid in the wider mode. The signedness of the 829 extension may differ from that of the type. */ 830 831 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ 832 if (GET_MODE_CLASS (MODE) == MODE_INT \ 833 && GET_MODE_SIZE (MODE) < (TARGET_32BIT ? 4 : 8)) \ 834 (MODE) = TARGET_32BIT ? SImode : DImode; 835 836 /* Define this if most significant bit is lowest numbered 837 in instructions that operate on numbered bit-fields. */ 838 /* That is true on RS/6000. */ 839 #define BITS_BIG_ENDIAN 1 840 841 /* Define this if most significant byte of a word is the lowest numbered. */ 842 /* That is true on RS/6000. */ 843 #define BYTES_BIG_ENDIAN 1 844 845 /* Define this if most significant word of a multiword number is lowest 846 numbered. 847 848 For RS/6000 we can decide arbitrarily since there are no machine 849 instructions for them. Might as well be consistent with bits and bytes. */ 850 #define WORDS_BIG_ENDIAN 1 851 852 /* This says that for the IBM long double the larger magnitude double 853 comes first. It's really a two element double array, and arrays 854 don't index differently between little- and big-endian. */ 855 #define LONG_DOUBLE_LARGE_FIRST 1 856 857 #define MAX_BITS_PER_WORD 64 858 859 /* Width of a word, in units (bytes). */ 860 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8) 861 #ifdef IN_LIBGCC2 862 #define MIN_UNITS_PER_WORD UNITS_PER_WORD 863 #else 864 #define MIN_UNITS_PER_WORD 4 865 #endif 866 #define UNITS_PER_FP_WORD 8 867 #define UNITS_PER_ALTIVEC_WORD 16 868 #define UNITS_PER_VSX_WORD 16 869 #define UNITS_PER_PAIRED_WORD 8 870 871 /* Type used for ptrdiff_t, as a string used in a declaration. */ 872 #define PTRDIFF_TYPE "int" 873 874 /* Type used for size_t, as a string used in a declaration. */ 875 #define SIZE_TYPE "long unsigned int" 876 877 /* Type used for wchar_t, as a string used in a declaration. */ 878 #define WCHAR_TYPE "short unsigned int" 879 880 /* Width of wchar_t in bits. */ 881 #define WCHAR_TYPE_SIZE 16 882 883 /* A C expression for the size in bits of the type `short' on the 884 target machine. If you don't define this, the default is half a 885 word. (If this would be less than one storage unit, it is 886 rounded up to one unit.) */ 887 #define SHORT_TYPE_SIZE 16 888 889 /* A C expression for the size in bits of the type `int' on the 890 target machine. If you don't define this, the default is one 891 word. */ 892 #define INT_TYPE_SIZE 32 893 894 /* A C expression for the size in bits of the type `long' on the 895 target machine. If you don't define this, the default is one 896 word. */ 897 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64) 898 899 /* A C expression for the size in bits of the type `long long' on the 900 target machine. If you don't define this, the default is two 901 words. */ 902 #define LONG_LONG_TYPE_SIZE 64 903 904 /* A C expression for the size in bits of the type `float' on the 905 target machine. If you don't define this, the default is one 906 word. */ 907 #define FLOAT_TYPE_SIZE 32 908 909 /* A C expression for the size in bits of the type `double' on the 910 target machine. If you don't define this, the default is two 911 words. */ 912 #define DOUBLE_TYPE_SIZE 64 913 914 /* A C expression for the size in bits of the type `long double' on the target 915 machine. If you don't define this, the default is two words. */ 916 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size 917 918 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */ 919 #define WIDEST_HARDWARE_FP_SIZE 64 920 921 /* Width in bits of a pointer. 922 See also the macro `Pmode' defined below. */ 923 extern unsigned rs6000_pointer_size; 924 #define POINTER_SIZE rs6000_pointer_size 925 926 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 927 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64) 928 929 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 930 #define STACK_BOUNDARY \ 931 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI && !TARGET_VSX) \ 932 ? 64 : 128) 933 934 /* Allocation boundary (in *bits*) for the code of a function. */ 935 #define FUNCTION_BOUNDARY 32 936 937 /* No data type wants to be aligned rounder than this. */ 938 #define BIGGEST_ALIGNMENT 128 939 940 /* Alignment of field after `int : 0' in a structure. */ 941 #define EMPTY_FIELD_BOUNDARY 32 942 943 /* Every structure's size must be a multiple of this. */ 944 #define STRUCTURE_SIZE_BOUNDARY 8 945 946 /* A bit-field declared as `int' forces `int' alignment for the struct. */ 947 #define PCC_BITFIELD_TYPE_MATTERS 1 948 949 enum data_align { align_abi, align_opt, align_both }; 950 951 /* A C expression to compute the alignment for a variables in the 952 local store. TYPE is the data type, and ALIGN is the alignment 953 that the object would ordinarily have. */ 954 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ 955 rs6000_data_alignment (TYPE, ALIGN, align_both) 956 957 /* Make arrays of chars word-aligned for the same reasons. */ 958 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 959 rs6000_data_alignment (TYPE, ALIGN, align_opt) 960 961 /* Align vectors to 128 bits. */ 962 #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \ 963 rs6000_data_alignment (TYPE, ALIGN, align_abi) 964 965 /* Nonzero if move instructions will actually fail to work 966 when given unaligned data. */ 967 #define STRICT_ALIGNMENT 0 968 969 /* Standard register usage. */ 970 971 /* Number of actual hardware registers. 972 The hardware registers are assigned numbers for the compiler 973 from 0 to just below FIRST_PSEUDO_REGISTER. 974 All registers that the compiler knows about must be given numbers, 975 even those that are not normally considered general registers. 976 977 RS/6000 has 32 fixed-point registers, 32 floating-point registers, 978 a count register, a link register, and 8 condition register fields, 979 which we view here as separate registers. AltiVec adds 32 vector 980 registers and a VRsave register. 981 982 In addition, the difference between the frame and argument pointers is 983 a function of the number of registers saved, so we need to have a 984 register for AP that will later be eliminated in favor of SP or FP. 985 This is a normal register, but it is fixed. 986 987 We also create a pseudo register for float/int conversions, that will 988 really represent the memory location used. It is represented here as 989 a register, in order to work around problems in allocating stack storage 990 in inline functions. 991 992 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame 993 pointer, which is eventually eliminated in favor of SP or FP. 994 995 The 3 HTM registers aren't also included in DWARF_FRAME_REGISTERS. */ 996 997 #define FIRST_PSEUDO_REGISTER 115 998 999 /* This must be included for pre gcc 3.0 glibc compatibility. */ 1000 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77 1001 1002 /* The sfp register and 3 HTM registers 1003 aren't included in DWARF_FRAME_REGISTERS. */ 1004 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 4) 1005 1006 /* Use standard DWARF numbering for DWARF debugging information. */ 1007 #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number ((REGNO), 0) 1008 1009 /* Use gcc hard register numbering for eh_frame. */ 1010 #define DWARF_FRAME_REGNUM(REGNO) (REGNO) 1011 1012 /* Map register numbers held in the call frame info that gcc has 1013 collected using DWARF_FRAME_REGNUM to those that should be output in 1014 .debug_frame and .eh_frame. */ 1015 #define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \ 1016 rs6000_dbx_register_number ((REGNO), (FOR_EH)? 2 : 1) 1017 1018 /* 1 for registers that have pervasive standard uses 1019 and are not available for the register allocator. 1020 1021 On RS/6000, r1 is used for the stack. On Darwin, r2 is available 1022 as a local register; for all other OS's r2 is the TOC pointer. 1023 1024 On System V implementations, r13 is fixed and not available for use. */ 1025 1026 #define FIXED_REGISTERS \ 1027 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \ 1028 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1029 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1030 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1031 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ 1032 /* AltiVec registers. */ \ 1033 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1034 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1035 1, 1 \ 1036 , 1, 1, 1, 1 \ 1037 } 1038 1039 /* 1 for registers not available across function calls. 1040 These must include the FIXED_REGISTERS and also any 1041 registers that can be used without being saved. 1042 The latter must include the registers where values are returned 1043 and the register where structure-value addresses are passed. 1044 Aside from that, you can include as many other registers as you like. */ 1045 1046 #define CALL_USED_REGISTERS \ 1047 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ 1048 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1049 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ 1050 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1051 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \ 1052 /* AltiVec registers. */ \ 1053 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1054 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1055 1, 1 \ 1056 , 1, 1, 1, 1 \ 1057 } 1058 1059 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that 1060 the entire set of `FIXED_REGISTERS' be included. 1061 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS'). 1062 This macro is optional. If not specified, it defaults to the value 1063 of `CALL_USED_REGISTERS'. */ 1064 1065 #define CALL_REALLY_USED_REGISTERS \ 1066 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ 1067 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1068 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ 1069 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1070 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \ 1071 /* AltiVec registers. */ \ 1072 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1073 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1074 0, 0 \ 1075 , 0, 0, 0, 0 \ 1076 } 1077 1078 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1) 1079 1080 #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20) 1081 #define FIRST_SAVED_FP_REGNO (14+32) 1082 #define FIRST_SAVED_GP_REGNO (FIXED_R13 ? 14 : 13) 1083 1084 /* List the order in which to allocate registers. Each register must be 1085 listed once, even those in FIXED_REGISTERS. 1086 1087 We allocate in the following order: 1088 fp0 (not saved or used for anything) 1089 fp13 - fp2 (not saved; incoming fp arg registers) 1090 fp1 (not saved; return value) 1091 fp31 - fp14 (saved; order given to save least number) 1092 cr7, cr5 (not saved or special) 1093 cr6 (not saved, but used for vector operations) 1094 cr1 (not saved, but used for FP operations) 1095 cr0 (not saved, but used for arithmetic operations) 1096 cr4, cr3, cr2 (saved) 1097 r9 (not saved; best for TImode) 1098 r10, r8-r4 (not saved; highest first for less conflict with params) 1099 r3 (not saved; return value register) 1100 r11 (not saved; later alloc to help shrink-wrap) 1101 r0 (not saved; cannot be base reg) 1102 r31 - r13 (saved; order given to save least number) 1103 r12 (not saved; if used for DImode or DFmode would use r13) 1104 ctr (not saved; when we have the choice ctr is better) 1105 lr (saved) 1106 r1, r2, ap, ca (fixed) 1107 v0 - v1 (not saved or used for anything) 1108 v13 - v3 (not saved; incoming vector arg registers) 1109 v2 (not saved; incoming vector arg reg; return value) 1110 v19 - v14 (not saved or used for anything) 1111 v31 - v20 (saved; order given to save least number) 1112 vrsave, vscr (fixed) 1113 sfp (fixed) 1114 tfhar (fixed) 1115 tfiar (fixed) 1116 texasr (fixed) 1117 */ 1118 1119 #if FIXED_R2 == 1 1120 #define MAYBE_R2_AVAILABLE 1121 #define MAYBE_R2_FIXED 2, 1122 #else 1123 #define MAYBE_R2_AVAILABLE 2, 1124 #define MAYBE_R2_FIXED 1125 #endif 1126 1127 #if FIXED_R13 == 1 1128 #define EARLY_R12 12, 1129 #define LATE_R12 1130 #else 1131 #define EARLY_R12 1132 #define LATE_R12 12, 1133 #endif 1134 1135 #define REG_ALLOC_ORDER \ 1136 {32, \ 1137 /* move fr13 (ie 45) later, so if we need TFmode, it does */ \ 1138 /* not use fr14 which is a saved register. */ \ 1139 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 45, \ 1140 33, \ 1141 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ 1142 50, 49, 48, 47, 46, \ 1143 75, 73, 74, 69, 68, 72, 71, 70, \ 1144 MAYBE_R2_AVAILABLE \ 1145 9, 10, 8, 7, 6, 5, 4, \ 1146 3, EARLY_R12 11, 0, \ 1147 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \ 1148 18, 17, 16, 15, 14, 13, LATE_R12 \ 1149 66, 65, \ 1150 1, MAYBE_R2_FIXED 67, 76, \ 1151 /* AltiVec registers. */ \ 1152 77, 78, \ 1153 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \ 1154 79, \ 1155 96, 95, 94, 93, 92, 91, \ 1156 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \ 1157 109, 110, \ 1158 111, 112, 113, 114 \ 1159 } 1160 1161 /* True if register is floating-point. */ 1162 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63) 1163 1164 /* True if register is a condition register. */ 1165 #define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO) 1166 1167 /* True if register is a condition register, but not cr0. */ 1168 #define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO) 1169 1170 /* True if register is an integer register. */ 1171 #define INT_REGNO_P(N) \ 1172 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM) 1173 1174 /* PAIRED SIMD registers are just the FPRs. */ 1175 #define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63) 1176 1177 /* True if register is the CA register. */ 1178 #define CA_REGNO_P(N) ((N) == CA_REGNO) 1179 1180 /* True if register is an AltiVec register. */ 1181 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO) 1182 1183 /* True if register is a VSX register. */ 1184 #define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N)) 1185 1186 /* Alternate name for any vector register supporting floating point, no matter 1187 which instruction set(s) are available. */ 1188 #define VFLOAT_REGNO_P(N) \ 1189 (ALTIVEC_REGNO_P (N) || (TARGET_VSX && FP_REGNO_P (N))) 1190 1191 /* Alternate name for any vector register supporting integer, no matter which 1192 instruction set(s) are available. */ 1193 #define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N) 1194 1195 /* Alternate name for any vector register supporting logical operations, no 1196 matter which instruction set(s) are available. Allow GPRs as well as the 1197 vector registers. */ 1198 #define VLOGICAL_REGNO_P(N) \ 1199 (INT_REGNO_P (N) || ALTIVEC_REGNO_P (N) \ 1200 || (TARGET_VSX && FP_REGNO_P (N))) \ 1201 1202 /* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate 1203 enough space to account for vectors in FP regs. However, TFmode/TDmode 1204 should not use VSX instructions to do a caller save. */ 1205 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 1206 ((NREGS) <= rs6000_hard_regno_nregs[MODE][REGNO] \ 1207 ? (MODE) \ 1208 : TARGET_VSX \ 1209 && ((MODE) == VOIDmode || ALTIVEC_OR_VSX_VECTOR_MODE (MODE)) \ 1210 && FP_REGNO_P (REGNO) \ 1211 ? V2DFmode \ 1212 : FLOAT128_IBM_P (MODE) && FP_REGNO_P (REGNO) \ 1213 ? DFmode \ 1214 : (MODE) == TDmode && FP_REGNO_P (REGNO) \ 1215 ? DImode \ 1216 : choose_hard_reg_mode ((REGNO), (NREGS), false)) 1217 1218 #define VSX_VECTOR_MODE(MODE) \ 1219 ((MODE) == V4SFmode \ 1220 || (MODE) == V2DFmode) \ 1221 1222 /* Note KFmode and possibly TFmode (i.e. IEEE 128-bit floating point) are not 1223 really a vector, but we want to treat it as a vector for moves, and 1224 such. */ 1225 1226 #define ALTIVEC_VECTOR_MODE(MODE) \ 1227 ((MODE) == V16QImode \ 1228 || (MODE) == V8HImode \ 1229 || (MODE) == V4SFmode \ 1230 || (MODE) == V4SImode \ 1231 || FLOAT128_VECTOR_P (MODE)) 1232 1233 #define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \ 1234 (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \ 1235 || (MODE) == V2DImode || (MODE) == V1TImode) 1236 1237 #define PAIRED_VECTOR_MODE(MODE) \ 1238 ((MODE) == V2SFmode) 1239 1240 /* Post-reload, we can't use any new AltiVec registers, as we already 1241 emitted the vrsave mask. */ 1242 1243 #define HARD_REGNO_RENAME_OK(SRC, DST) \ 1244 (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST)) 1245 1246 /* Specify the cost of a branch insn; roughly the number of extra insns that 1247 should be added to avoid a branch. 1248 1249 Set this to 3 on the RS/6000 since that is roughly the average cost of an 1250 unscheduled conditional branch. */ 1251 1252 #define BRANCH_COST(speed_p, predictable_p) 3 1253 1254 /* Override BRANCH_COST heuristic which empirically produces worse 1255 performance for removing short circuiting from the logical ops. */ 1256 1257 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0 1258 1259 /* Specify the registers used for certain standard purposes. 1260 The values of these macros are register numbers. */ 1261 1262 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */ 1263 /* #define PC_REGNUM */ 1264 1265 /* Register to use for pushing function arguments. */ 1266 #define STACK_POINTER_REGNUM 1 1267 1268 /* Base register for access to local variables of the function. */ 1269 #define HARD_FRAME_POINTER_REGNUM 31 1270 1271 /* Base register for access to local variables of the function. */ 1272 #define FRAME_POINTER_REGNUM 111 1273 1274 /* Base register for access to arguments of the function. */ 1275 #define ARG_POINTER_REGNUM 67 1276 1277 /* Place to put static chain when calling a function that requires it. */ 1278 #define STATIC_CHAIN_REGNUM 11 1279 1280 /* Base register for access to thread local storage variables. */ 1281 #define TLS_REGNUM ((TARGET_64BIT) ? 13 : 2) 1282 1283 1284 /* Define the classes of registers for register constraints in the 1285 machine description. Also define ranges of constants. 1286 1287 One of the classes must always be named ALL_REGS and include all hard regs. 1288 If there is more than one class, another class must be named NO_REGS 1289 and contain no registers. 1290 1291 The name GENERAL_REGS must be the name of a class (or an alias for 1292 another name such as ALL_REGS). This is the class of registers 1293 that is allowed by "g" or "r" in a register constraint. 1294 Also, registers outside this class are allocated only when 1295 instructions express preferences for them. 1296 1297 The classes must be numbered in nondecreasing order; that is, 1298 a larger-numbered class must never be contained completely 1299 in a smaller-numbered class. 1300 1301 For any two classes, it is very desirable that there be another 1302 class that represents their union. */ 1303 1304 /* The RS/6000 has three types of registers, fixed-point, floating-point, and 1305 condition registers, plus three special registers, CTR, and the link 1306 register. AltiVec adds a vector register class. VSX registers overlap the 1307 FPR registers and the Altivec registers. 1308 1309 However, r0 is special in that it cannot be used as a base register. 1310 So make a class for registers valid as base registers. 1311 1312 Also, cr0 is the only condition code register that can be used in 1313 arithmetic insns, so make a separate class for it. */ 1314 1315 enum reg_class 1316 { 1317 NO_REGS, 1318 BASE_REGS, 1319 GENERAL_REGS, 1320 FLOAT_REGS, 1321 ALTIVEC_REGS, 1322 VSX_REGS, 1323 VRSAVE_REGS, 1324 VSCR_REGS, 1325 SPR_REGS, 1326 NON_SPECIAL_REGS, 1327 LINK_REGS, 1328 CTR_REGS, 1329 LINK_OR_CTR_REGS, 1330 SPECIAL_REGS, 1331 SPEC_OR_GEN_REGS, 1332 CR0_REGS, 1333 CR_REGS, 1334 NON_FLOAT_REGS, 1335 CA_REGS, 1336 ALL_REGS, 1337 LIM_REG_CLASSES 1338 }; 1339 1340 #define N_REG_CLASSES (int) LIM_REG_CLASSES 1341 1342 /* Give names of register classes as strings for dump file. */ 1343 1344 #define REG_CLASS_NAMES \ 1345 { \ 1346 "NO_REGS", \ 1347 "BASE_REGS", \ 1348 "GENERAL_REGS", \ 1349 "FLOAT_REGS", \ 1350 "ALTIVEC_REGS", \ 1351 "VSX_REGS", \ 1352 "VRSAVE_REGS", \ 1353 "VSCR_REGS", \ 1354 "SPR_REGS", \ 1355 "NON_SPECIAL_REGS", \ 1356 "LINK_REGS", \ 1357 "CTR_REGS", \ 1358 "LINK_OR_CTR_REGS", \ 1359 "SPECIAL_REGS", \ 1360 "SPEC_OR_GEN_REGS", \ 1361 "CR0_REGS", \ 1362 "CR_REGS", \ 1363 "NON_FLOAT_REGS", \ 1364 "CA_REGS", \ 1365 "ALL_REGS" \ 1366 } 1367 1368 /* Define which registers fit in which classes. 1369 This is an initializer for a vector of HARD_REG_SET 1370 of length N_REG_CLASSES. */ 1371 1372 #define REG_CLASS_CONTENTS \ 1373 { \ 1374 /* NO_REGS. */ \ 1375 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ 1376 /* BASE_REGS. */ \ 1377 { 0xfffffffe, 0x00000000, 0x00000008, 0x00008000 }, \ 1378 /* GENERAL_REGS. */ \ 1379 { 0xffffffff, 0x00000000, 0x00000008, 0x00008000 }, \ 1380 /* FLOAT_REGS. */ \ 1381 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, \ 1382 /* ALTIVEC_REGS. */ \ 1383 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, \ 1384 /* VSX_REGS. */ \ 1385 { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff }, \ 1386 /* VRSAVE_REGS. */ \ 1387 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, \ 1388 /* VSCR_REGS. */ \ 1389 { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, \ 1390 /* SPR_REGS. */ \ 1391 { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, \ 1392 /* NON_SPECIAL_REGS. */ \ 1393 { 0xffffffff, 0xffffffff, 0x00000008, 0x00008000 }, \ 1394 /* LINK_REGS. */ \ 1395 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, \ 1396 /* CTR_REGS. */ \ 1397 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, \ 1398 /* LINK_OR_CTR_REGS. */ \ 1399 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, \ 1400 /* SPECIAL_REGS. */ \ 1401 { 0x00000000, 0x00000000, 0x00000006, 0x00002000 }, \ 1402 /* SPEC_OR_GEN_REGS. */ \ 1403 { 0xffffffff, 0x00000000, 0x0000000e, 0x0000a000 }, \ 1404 /* CR0_REGS. */ \ 1405 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, \ 1406 /* CR_REGS. */ \ 1407 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, \ 1408 /* NON_FLOAT_REGS. */ \ 1409 { 0xffffffff, 0x00000000, 0x00000ffe, 0x00008000 }, \ 1410 /* CA_REGS. */ \ 1411 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, \ 1412 /* ALL_REGS. */ \ 1413 { 0xffffffff, 0xffffffff, 0xfffffffe, 0x0001ffff } \ 1414 } 1415 1416 /* The same information, inverted: 1417 Return the class number of the smallest class containing 1418 reg number REGNO. This could be a conditional expression 1419 or could index an array. */ 1420 1421 extern enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER]; 1422 1423 #define REGNO_REG_CLASS(REGNO) \ 1424 (gcc_checking_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)),\ 1425 rs6000_regno_regclass[(REGNO)]) 1426 1427 /* Register classes for various constraints that are based on the target 1428 switches. */ 1429 enum r6000_reg_class_enum { 1430 RS6000_CONSTRAINT_d, /* fpr registers for double values */ 1431 RS6000_CONSTRAINT_f, /* fpr registers for single values */ 1432 RS6000_CONSTRAINT_v, /* Altivec registers */ 1433 RS6000_CONSTRAINT_wa, /* Any VSX register */ 1434 RS6000_CONSTRAINT_wb, /* Altivec register if ISA 3.0 vector. */ 1435 RS6000_CONSTRAINT_wd, /* VSX register for V2DF */ 1436 RS6000_CONSTRAINT_we, /* VSX register if ISA 3.0 vector. */ 1437 RS6000_CONSTRAINT_wf, /* VSX register for V4SF */ 1438 RS6000_CONSTRAINT_wg, /* FPR register for -mmfpgpr */ 1439 RS6000_CONSTRAINT_wh, /* FPR register for direct moves. */ 1440 RS6000_CONSTRAINT_wi, /* FPR/VSX register to hold DImode */ 1441 RS6000_CONSTRAINT_wj, /* FPR/VSX register for DImode direct moves. */ 1442 RS6000_CONSTRAINT_wk, /* FPR/VSX register for DFmode direct moves. */ 1443 RS6000_CONSTRAINT_wl, /* FPR register for LFIWAX */ 1444 RS6000_CONSTRAINT_wm, /* VSX register for direct move */ 1445 RS6000_CONSTRAINT_wo, /* VSX register for power9 vector. */ 1446 RS6000_CONSTRAINT_wp, /* VSX reg for IEEE 128-bit fp TFmode. */ 1447 RS6000_CONSTRAINT_wq, /* VSX reg for IEEE 128-bit fp KFmode. */ 1448 RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */ 1449 RS6000_CONSTRAINT_ws, /* VSX register for DF */ 1450 RS6000_CONSTRAINT_wt, /* VSX register for TImode */ 1451 RS6000_CONSTRAINT_wu, /* Altivec register for float load/stores. */ 1452 RS6000_CONSTRAINT_wv, /* Altivec register for double load/stores. */ 1453 RS6000_CONSTRAINT_ww, /* FP or VSX register for vsx float ops. */ 1454 RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */ 1455 RS6000_CONSTRAINT_wy, /* VSX register for SF */ 1456 RS6000_CONSTRAINT_wz, /* FPR register for LFIWZX */ 1457 RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */ 1458 RS6000_CONSTRAINT_wH, /* Altivec register for 32-bit integers. */ 1459 RS6000_CONSTRAINT_wI, /* VSX register for 32-bit integers. */ 1460 RS6000_CONSTRAINT_wJ, /* VSX register for 8/16-bit integers. */ 1461 RS6000_CONSTRAINT_wK, /* Altivec register for 16/32-bit integers. */ 1462 RS6000_CONSTRAINT_MAX 1463 }; 1464 1465 extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX]; 1466 1467 /* The class value for index registers, and the one for base regs. */ 1468 #define INDEX_REG_CLASS GENERAL_REGS 1469 #define BASE_REG_CLASS BASE_REGS 1470 1471 /* Return whether a given register class can hold VSX objects. */ 1472 #define VSX_REG_CLASS_P(CLASS) \ 1473 ((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS) 1474 1475 /* Return whether a given register class targets general purpose registers. */ 1476 #define GPR_REG_CLASS_P(CLASS) ((CLASS) == GENERAL_REGS || (CLASS) == BASE_REGS) 1477 1478 /* Given an rtx X being reloaded into a reg required to be 1479 in class CLASS, return the class of reg to actually use. 1480 In general this is just CLASS; but on some machines 1481 in some cases it is preferable to use a more restrictive class. 1482 1483 On the RS/6000, we have to return NO_REGS when we want to reload a 1484 floating-point CONST_DOUBLE to force it to be copied to memory. 1485 1486 We also don't want to reload integer values into floating-point 1487 registers if we can at all help it. In fact, this can 1488 cause reload to die, if it tries to generate a reload of CTR 1489 into a FP register and discovers it doesn't have the memory location 1490 required. 1491 1492 ??? Would it be a good idea to have reload do the converse, that is 1493 try to reload floating modes into FP registers if possible? 1494 */ 1495 1496 #define PREFERRED_RELOAD_CLASS(X,CLASS) \ 1497 rs6000_preferred_reload_class_ptr (X, CLASS) 1498 1499 /* Return the register class of a scratch register needed to copy IN into 1500 or out of a register in CLASS in MODE. If it can be done directly, 1501 NO_REGS is returned. */ 1502 1503 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \ 1504 rs6000_secondary_reload_class_ptr (CLASS, MODE, IN) 1505 1506 /* Return the maximum number of consecutive registers 1507 needed to represent mode MODE in a register of class CLASS. 1508 1509 On RS/6000, this is the size of MODE in words, except in the FP regs, where 1510 a single reg is enough for two words, unless we have VSX, where the FP 1511 registers can hold 128 bits. */ 1512 #define CLASS_MAX_NREGS(CLASS, MODE) rs6000_class_max_nregs[(MODE)][(CLASS)] 1513 1514 /* Stack layout; function entry, exit and calling. */ 1515 1516 /* Define this if pushing a word on the stack 1517 makes the stack pointer a smaller address. */ 1518 #define STACK_GROWS_DOWNWARD 1 1519 1520 /* Offsets recorded in opcodes are a multiple of this alignment factor. */ 1521 #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8))) 1522 1523 /* Define this to nonzero if the nominal address of the stack frame 1524 is at the high-address end of the local variables; 1525 that is, each additional local variable allocated 1526 goes at a more negative offset in the frame. 1527 1528 On the RS/6000, we grow upwards, from the area after the outgoing 1529 arguments. */ 1530 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 \ 1531 || (flag_sanitize & SANITIZE_ADDRESS) != 0) 1532 1533 /* Size of the fixed area on the stack */ 1534 #define RS6000_SAVE_AREA \ 1535 ((DEFAULT_ABI == ABI_V4 ? 8 : DEFAULT_ABI == ABI_ELFv2 ? 16 : 24) \ 1536 << (TARGET_64BIT ? 1 : 0)) 1537 1538 /* Stack offset for toc save slot. */ 1539 #define RS6000_TOC_SAVE_SLOT \ 1540 ((DEFAULT_ABI == ABI_ELFv2 ? 12 : 20) << (TARGET_64BIT ? 1 : 0)) 1541 1542 /* Align an address */ 1543 #define RS6000_ALIGN(n,a) ROUND_UP ((n), (a)) 1544 1545 /* Offset within stack frame to start allocating local variables at. 1546 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1547 first local allocated. Otherwise, it is the offset to the BEGINNING 1548 of the first local allocated. 1549 1550 On the RS/6000, the frame pointer is the same as the stack pointer, 1551 except for dynamic allocations. So we start after the fixed area and 1552 outgoing parameter area. 1553 1554 If the function uses dynamic stack space (CALLS_ALLOCA is set), that 1555 space needs to be aligned to STACK_BOUNDARY, i.e. the sum of the 1556 sizes of the fixed area and the parameter area must be a multiple of 1557 STACK_BOUNDARY. */ 1558 1559 #define RS6000_STARTING_FRAME_OFFSET \ 1560 (cfun->calls_alloca \ 1561 ? (RS6000_ALIGN (crtl->outgoing_args_size + RS6000_SAVE_AREA, \ 1562 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8 )) \ 1563 : (RS6000_ALIGN (crtl->outgoing_args_size, \ 1564 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \ 1565 + RS6000_SAVE_AREA)) 1566 1567 /* Offset from the stack pointer register to an item dynamically 1568 allocated on the stack, e.g., by `alloca'. 1569 1570 The default value for this macro is `STACK_POINTER_OFFSET' plus the 1571 length of the outgoing arguments. The default is correct for most 1572 machines. See `function.c' for details. 1573 1574 This value must be a multiple of STACK_BOUNDARY (hard coded in 1575 `emit-rtl.c'). */ 1576 #define STACK_DYNAMIC_OFFSET(FUNDECL) \ 1577 RS6000_ALIGN (crtl->outgoing_args_size.to_constant () \ 1578 + STACK_POINTER_OFFSET, \ 1579 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) 1580 1581 /* If we generate an insn to push BYTES bytes, 1582 this says how many the stack pointer really advances by. 1583 On RS/6000, don't define this because there are no push insns. */ 1584 /* #define PUSH_ROUNDING(BYTES) */ 1585 1586 /* Offset of first parameter from the argument pointer register value. 1587 On the RS/6000, we define the argument pointer to the start of the fixed 1588 area. */ 1589 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA 1590 1591 /* Offset from the argument pointer register value to the top of 1592 stack. This is different from FIRST_PARM_OFFSET because of the 1593 register save area. */ 1594 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 1595 1596 /* Define this if stack space is still allocated for a parameter passed 1597 in a register. The value is the number of bytes allocated to this 1598 area. */ 1599 #define REG_PARM_STACK_SPACE(FNDECL) \ 1600 rs6000_reg_parm_stack_space ((FNDECL), false) 1601 1602 /* Define this macro if space guaranteed when compiling a function body 1603 is different to space required when making a call, a situation that 1604 can arise with K&R style function definitions. */ 1605 #define INCOMING_REG_PARM_STACK_SPACE(FNDECL) \ 1606 rs6000_reg_parm_stack_space ((FNDECL), true) 1607 1608 /* Define this if the above stack space is to be considered part of the 1609 space allocated by the caller. */ 1610 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 1611 1612 /* This is the difference between the logical top of stack and the actual sp. 1613 1614 For the RS/6000, sp points past the fixed area. */ 1615 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA 1616 1617 /* Define this if the maximum size of all the outgoing args is to be 1618 accumulated and pushed during the prologue. The amount can be 1619 found in the variable crtl->outgoing_args_size. */ 1620 #define ACCUMULATE_OUTGOING_ARGS 1 1621 1622 /* Define how to find the value returned by a library function 1623 assuming the value has mode MODE. */ 1624 1625 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE)) 1626 1627 /* DRAFT_V4_STRUCT_RET defaults off. */ 1628 #define DRAFT_V4_STRUCT_RET 0 1629 1630 /* Let TARGET_RETURN_IN_MEMORY control what happens. */ 1631 #define DEFAULT_PCC_STRUCT_RETURN 0 1632 1633 /* Mode of stack savearea. 1634 FUNCTION is VOIDmode because calling convention maintains SP. 1635 BLOCK needs Pmode for SP. 1636 NONLOCAL needs twice Pmode to maintain both backchain and SP. */ 1637 #define STACK_SAVEAREA_MODE(LEVEL) \ 1638 (LEVEL == SAVE_FUNCTION ? VOIDmode \ 1639 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : PTImode) : Pmode) 1640 1641 /* Minimum and maximum general purpose registers used to hold arguments. */ 1642 #define GP_ARG_MIN_REG 3 1643 #define GP_ARG_MAX_REG 10 1644 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1) 1645 1646 /* Minimum and maximum floating point registers used to hold arguments. */ 1647 #define FP_ARG_MIN_REG 33 1648 #define FP_ARG_AIX_MAX_REG 45 1649 #define FP_ARG_V4_MAX_REG 40 1650 #define FP_ARG_MAX_REG (DEFAULT_ABI == ABI_V4 \ 1651 ? FP_ARG_V4_MAX_REG : FP_ARG_AIX_MAX_REG) 1652 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1) 1653 1654 /* Minimum and maximum AltiVec registers used to hold arguments. */ 1655 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2) 1656 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11) 1657 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1) 1658 1659 /* Maximum number of registers per ELFv2 homogeneous aggregate argument. */ 1660 #define AGGR_ARG_NUM_REG 8 1661 1662 /* Return registers */ 1663 #define GP_ARG_RETURN GP_ARG_MIN_REG 1664 #define FP_ARG_RETURN FP_ARG_MIN_REG 1665 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2) 1666 #define FP_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? FP_ARG_RETURN \ 1667 : (FP_ARG_RETURN + AGGR_ARG_NUM_REG - 1)) 1668 #define ALTIVEC_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 \ 1669 ? (ALTIVEC_ARG_RETURN \ 1670 + (TARGET_FLOAT128_TYPE ? 1 : 0)) \ 1671 : (ALTIVEC_ARG_RETURN + AGGR_ARG_NUM_REG - 1)) 1672 1673 /* Flags for the call/call_value rtl operations set up by function_arg */ 1674 #define CALL_NORMAL 0x00000000 /* no special processing */ 1675 /* Bits in 0x00000001 are unused. */ 1676 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */ 1677 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */ 1678 #define CALL_LONG 0x00000008 /* always call indirect */ 1679 #define CALL_LIBCALL 0x00000010 /* libcall */ 1680 1681 /* We don't have prologue and epilogue functions to save/restore 1682 everything for most ABIs. */ 1683 #define WORLD_SAVE_P(INFO) 0 1684 1685 /* 1 if N is a possible register number for a function value 1686 as seen by the caller. 1687 1688 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */ 1689 #define FUNCTION_VALUE_REGNO_P(N) \ 1690 ((N) == GP_ARG_RETURN \ 1691 || (IN_RANGE ((N), FP_ARG_RETURN, FP_ARG_MAX_RETURN) \ 1692 && TARGET_HARD_FLOAT) \ 1693 || (IN_RANGE ((N), ALTIVEC_ARG_RETURN, ALTIVEC_ARG_MAX_RETURN) \ 1694 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)) 1695 1696 /* 1 if N is a possible register number for function argument passing. 1697 On RS/6000, these are r3-r10 and fp1-fp13. 1698 On AltiVec, v2 - v13 are used for passing vectors. */ 1699 #define FUNCTION_ARG_REGNO_P(N) \ 1700 (IN_RANGE ((N), GP_ARG_MIN_REG, GP_ARG_MAX_REG) \ 1701 || (IN_RANGE ((N), ALTIVEC_ARG_MIN_REG, ALTIVEC_ARG_MAX_REG) \ 1702 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \ 1703 || (IN_RANGE ((N), FP_ARG_MIN_REG, FP_ARG_MAX_REG) \ 1704 && TARGET_HARD_FLOAT)) 1705 1706 /* Define a data type for recording info about an argument list 1707 during the scan of that argument list. This data type should 1708 hold all necessary information about the function itself 1709 and about the args processed so far, enough to enable macros 1710 such as FUNCTION_ARG to determine where the next arg should go. 1711 1712 On the RS/6000, this is a structure. The first element is the number of 1713 total argument words, the second is used to store the next 1714 floating-point register number, and the third says how many more args we 1715 have prototype types for. 1716 1717 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is 1718 the next available GP register, `fregno' is the next available FP 1719 register, and `words' is the number of words used on the stack. 1720 1721 The varargs/stdarg support requires that this structure's size 1722 be a multiple of sizeof(int). */ 1723 1724 typedef struct rs6000_args 1725 { 1726 int words; /* # words used for passing GP registers */ 1727 int fregno; /* next available FP register */ 1728 int vregno; /* next available AltiVec register */ 1729 int nargs_prototype; /* # args left in the current prototype */ 1730 int prototype; /* Whether a prototype was defined */ 1731 int stdarg; /* Whether function is a stdarg function. */ 1732 int call_cookie; /* Do special things for this call */ 1733 int sysv_gregno; /* next available GP register */ 1734 int intoffset; /* running offset in struct (darwin64) */ 1735 int use_stack; /* any part of struct on stack (darwin64) */ 1736 int floats_in_gpr; /* count of SFmode floats taking up 1737 GPR space (darwin64) */ 1738 int named; /* false for varargs params */ 1739 int escapes; /* if function visible outside tu */ 1740 int libcall; /* If this is a compiler generated call. */ 1741 } CUMULATIVE_ARGS; 1742 1743 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1744 for a call to a function whose data type is FNTYPE. 1745 For a library call, FNTYPE is 0. */ 1746 1747 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1748 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, \ 1749 N_NAMED_ARGS, FNDECL, VOIDmode) 1750 1751 /* Similar, but when scanning the definition of a procedure. We always 1752 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */ 1753 1754 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \ 1755 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, \ 1756 1000, current_function_decl, VOIDmode) 1757 1758 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */ 1759 1760 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \ 1761 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, \ 1762 0, NULL_TREE, MODE) 1763 1764 #define PAD_VARARGS_DOWN \ 1765 (targetm.calls.function_arg_padding (TYPE_MODE (type), type) == PAD_DOWNWARD) 1766 1767 /* Output assembler code to FILE to increment profiler label # LABELNO 1768 for profiling a function entry. */ 1769 1770 #define FUNCTION_PROFILER(FILE, LABELNO) \ 1771 output_function_profiler ((FILE), (LABELNO)); 1772 1773 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1774 the stack pointer does not matter. No definition is equivalent to 1775 always zero. 1776 1777 On the RS/6000, this is nonzero because we can restore the stack from 1778 its backpointer, which we maintain. */ 1779 #define EXIT_IGNORE_STACK 1 1780 1781 /* Define this macro as a C expression that is nonzero for registers 1782 that are used by the epilogue or the return' pattern. The stack 1783 and frame pointer registers are already be assumed to be used as 1784 needed. */ 1785 1786 #define EPILOGUE_USES(REGNO) \ 1787 ((reload_completed && (REGNO) == LR_REGNO) \ 1788 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \ 1789 || (crtl->calls_eh_return \ 1790 && TARGET_AIX \ 1791 && (REGNO) == 2)) 1792 1793 1794 /* Length in units of the trampoline for entering a nested function. */ 1795 1796 #define TRAMPOLINE_SIZE rs6000_trampoline_size () 1797 1798 /* Definitions for __builtin_return_address and __builtin_frame_address. 1799 __builtin_return_address (0) should give link register (LR_REGNO), enable 1800 this. */ 1801 /* This should be uncommented, so that the link register is used, but 1802 currently this would result in unmatched insns and spilling fixed 1803 registers so we'll leave it for another day. When these problems are 1804 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX. 1805 (mrs) */ 1806 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */ 1807 1808 /* Number of bytes into the frame return addresses can be found. See 1809 rs6000_stack_info in rs6000.c for more information on how the different 1810 abi's store the return address. */ 1811 #define RETURN_ADDRESS_OFFSET \ 1812 ((DEFAULT_ABI == ABI_V4 ? 4 : 8) << (TARGET_64BIT ? 1 : 0)) 1813 1814 /* The current return address is in link register (65). The return address 1815 of anything farther back is accessed normally at an offset of 8 from the 1816 frame pointer. */ 1817 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 1818 (rs6000_return_addr (COUNT, FRAME)) 1819 1820 1821 /* Definitions for register eliminations. 1822 1823 We have two registers that can be eliminated on the RS/6000. First, the 1824 frame pointer register can often be eliminated in favor of the stack 1825 pointer register. Secondly, the argument pointer register can always be 1826 eliminated; it is replaced with either the stack or frame pointer. 1827 1828 In addition, we use the elimination mechanism to see if r30 is needed 1829 Initially we assume that it isn't. If it is, we spill it. This is done 1830 by making it an eliminable register. We replace it with itself so that 1831 if it isn't needed, then existing uses won't be modified. */ 1832 1833 /* This is an array of structures. Each structure initializes one pair 1834 of eliminable registers. The "from" register number is given first, 1835 followed by "to". Eliminations of the same "from" register are listed 1836 in order of preference. */ 1837 #define ELIMINABLE_REGS \ 1838 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1839 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1840 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1841 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1842 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1843 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } } 1844 1845 /* Define the offset between two registers, one to be eliminated, and the other 1846 its replacement, at the start of a routine. */ 1847 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1848 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO)) 1849 1850 /* Addressing modes, and classification of registers for them. */ 1851 1852 #define HAVE_PRE_DECREMENT 1 1853 #define HAVE_PRE_INCREMENT 1 1854 #define HAVE_PRE_MODIFY_DISP 1 1855 #define HAVE_PRE_MODIFY_REG 1 1856 1857 /* Macros to check register numbers against specific register classes. */ 1858 1859 /* These assume that REGNO is a hard or pseudo reg number. 1860 They give nonzero only if REGNO is a hard reg of the suitable class 1861 or a pseudo reg currently allocated to a suitable hard reg. 1862 Since they use reg_renumber, they are safe only once reg_renumber 1863 has been allocated, which happens in reginfo.c during register 1864 allocation. */ 1865 1866 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1867 ((REGNO) < FIRST_PSEUDO_REGISTER \ 1868 ? (REGNO) <= 31 || (REGNO) == 67 \ 1869 || (REGNO) == FRAME_POINTER_REGNUM \ 1870 : (reg_renumber[REGNO] >= 0 \ 1871 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \ 1872 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) 1873 1874 #define REGNO_OK_FOR_BASE_P(REGNO) \ 1875 ((REGNO) < FIRST_PSEUDO_REGISTER \ 1876 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \ 1877 || (REGNO) == FRAME_POINTER_REGNUM \ 1878 : (reg_renumber[REGNO] > 0 \ 1879 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \ 1880 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) 1881 1882 /* Nonzero if X is a hard reg that can be used as an index 1883 or if it is a pseudo reg in the non-strict case. */ 1884 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \ 1885 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ 1886 || REGNO_OK_FOR_INDEX_P (REGNO (X))) 1887 1888 /* Nonzero if X is a hard reg that can be used as a base reg 1889 or if it is a pseudo reg in the non-strict case. */ 1890 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \ 1891 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ 1892 || REGNO_OK_FOR_BASE_P (REGNO (X))) 1893 1894 1895 /* Maximum number of registers that can appear in a valid memory address. */ 1896 1897 #define MAX_REGS_PER_ADDRESS 2 1898 1899 /* Recognize any constant value that is a valid address. */ 1900 1901 #define CONSTANT_ADDRESS_P(X) \ 1902 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 1903 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ 1904 || GET_CODE (X) == HIGH) 1905 1906 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15) 1907 #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \ 1908 && EASY_VECTOR_15((n) >> 1) \ 1909 && ((n) & 1) == 0) 1910 1911 #define EASY_VECTOR_MSB(n,mode) \ 1912 ((((unsigned HOST_WIDE_INT) (n)) & GET_MODE_MASK (mode)) == \ 1913 ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1)) 1914 1915 1916 /* Try a machine-dependent way of reloading an illegitimate address 1917 operand. If we find one, push the reload and jump to WIN. This 1918 macro is used in only one place: `find_reloads_address' in reload.c. 1919 1920 Implemented on rs6000 by rs6000_legitimize_reload_address. 1921 Note that (X) is evaluated twice; this is safe in current usage. */ 1922 1923 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ 1924 do { \ 1925 int win; \ 1926 (X) = rs6000_legitimize_reload_address_ptr ((X), (MODE), (OPNUM), \ 1927 (int)(TYPE), (IND_LEVELS), &win); \ 1928 if ( win ) \ 1929 goto WIN; \ 1930 } while (0) 1931 1932 #define FIND_BASE_TERM rs6000_find_base_term 1933 1934 /* The register number of the register used to address a table of 1935 static data addresses in memory. In some cases this register is 1936 defined by a processor's "application binary interface" (ABI). 1937 When this macro is defined, RTL is generated for this register 1938 once, as with the stack pointer and frame pointer registers. If 1939 this macro is not defined, it is up to the machine-dependent files 1940 to allocate such a register (if necessary). */ 1941 1942 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30 1943 #define PIC_OFFSET_TABLE_REGNUM \ 1944 (TARGET_TOC ? TOC_REGISTER \ 1945 : flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM \ 1946 : INVALID_REGNUM) 1947 1948 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2) 1949 1950 /* Define this macro if the register defined by 1951 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define 1952 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */ 1953 1954 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */ 1955 1956 /* A C expression that is nonzero if X is a legitimate immediate 1957 operand on the target machine when generating position independent 1958 code. You can assume that X satisfies `CONSTANT_P', so you need 1959 not check this. You can also assume FLAG_PIC is true, so you need 1960 not check it either. You need not define this macro if all 1961 constants (including `SYMBOL_REF') can be immediate operands when 1962 generating position independent code. */ 1963 1964 /* #define LEGITIMATE_PIC_OPERAND_P (X) */ 1965 1966 /* Specify the machine mode that this machine uses 1967 for the index in the tablejump instruction. */ 1968 #define CASE_VECTOR_MODE SImode 1969 1970 /* Define as C expression which evaluates to nonzero if the tablejump 1971 instruction expects the table to contain offsets from the address of the 1972 table. 1973 Do not define this if the table should contain absolute addresses. */ 1974 #define CASE_VECTOR_PC_RELATIVE 1 1975 1976 /* Define this as 1 if `char' should by default be signed; else as 0. */ 1977 #define DEFAULT_SIGNED_CHAR 0 1978 1979 /* An integer expression for the size in bits of the largest integer machine 1980 mode that should actually be used. */ 1981 1982 /* Allow pairs of registers to be used, which is the intent of the default. */ 1983 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode) 1984 1985 /* Max number of bytes we can move from memory to memory 1986 in one reasonably fast instruction. */ 1987 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8) 1988 #define MAX_MOVE_MAX 8 1989 1990 /* Nonzero if access to memory by bytes is no faster than for words. 1991 Also nonzero if doing byte operations (specifically shifts) in registers 1992 is undesirable. */ 1993 #define SLOW_BYTE_ACCESS 1 1994 1995 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 1996 will either zero-extend or sign-extend. The value of this macro should 1997 be the code that says which one of the two operations is implicitly 1998 done, UNKNOWN if none. */ 1999 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 2000 2001 /* Define if loading short immediate values into registers sign extends. */ 2002 #define SHORT_IMMEDIATES_SIGN_EXTEND 1 2003 2004 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */ 2005 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2006 ((VALUE) = GET_MODE_BITSIZE (MODE), 2) 2007 2008 /* The CTZ patterns that are implemented in terms of CLZ return -1 for input of 2009 zero. The hardware instructions added in Power9 and the sequences using 2010 popcount return 32 or 64. */ 2011 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2012 (TARGET_CTZ || TARGET_POPCNTD \ 2013 ? ((VALUE) = GET_MODE_BITSIZE (MODE), 2) \ 2014 : ((VALUE) = -1, 2)) 2015 2016 /* Specify the machine mode that pointers have. 2017 After generation of rtl, the compiler makes no further distinction 2018 between pointers and any other objects of this machine mode. */ 2019 extern scalar_int_mode rs6000_pmode; 2020 #define Pmode rs6000_pmode 2021 2022 /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */ 2023 #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode) 2024 2025 /* Mode of a function address in a call instruction (for indexing purposes). 2026 Doesn't matter on RS/6000. */ 2027 #define FUNCTION_MODE SImode 2028 2029 /* Define this if addresses of constant functions 2030 shouldn't be put through pseudo regs where they can be cse'd. 2031 Desirable on machines where ordinary constants are expensive 2032 but a CALL with constant address is cheap. */ 2033 #define NO_FUNCTION_CSE 1 2034 2035 /* Define this to be nonzero if shift instructions ignore all but the low-order 2036 few bits. 2037 2038 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED 2039 have been dropped from the PowerPC architecture. */ 2040 #define SHIFT_COUNT_TRUNCATED 0 2041 2042 /* Adjust the length of an INSN. LENGTH is the currently-computed length and 2043 should be adjusted to reflect any required changes. This macro is used when 2044 there is some systematic length adjustment required that would be difficult 2045 to express in the length attribute. */ 2046 2047 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */ 2048 2049 /* Given a comparison code (EQ, NE, etc.) and the first operand of a 2050 COMPARE, return the mode to be used for the comparison. For 2051 floating-point, CCFPmode should be used. CCUNSmode should be used 2052 for unsigned comparisons. CCEQmode should be used when we are 2053 doing an inequality comparison on the result of a 2054 comparison. CCmode should be used in all other cases. */ 2055 2056 #define SELECT_CC_MODE(OP,X,Y) \ 2057 (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \ 2058 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \ 2059 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \ 2060 ? CCEQmode : CCmode)) 2061 2062 /* Can the condition code MODE be safely reversed? This is safe in 2063 all cases on this port, because at present it doesn't use the 2064 trapping FP comparisons (fcmpo). */ 2065 #define REVERSIBLE_CC_MODE(MODE) 1 2066 2067 /* Given a condition code and a mode, return the inverse condition. */ 2068 #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE) 2069 2070 2071 /* Target cpu costs. */ 2072 2073 struct processor_costs { 2074 const int mulsi; /* cost of SImode multiplication. */ 2075 const int mulsi_const; /* cost of SImode multiplication by constant. */ 2076 const int mulsi_const9; /* cost of SImode mult by short constant. */ 2077 const int muldi; /* cost of DImode multiplication. */ 2078 const int divsi; /* cost of SImode division. */ 2079 const int divdi; /* cost of DImode division. */ 2080 const int fp; /* cost of simple SFmode and DFmode insns. */ 2081 const int dmul; /* cost of DFmode multiplication (and fmadd). */ 2082 const int sdiv; /* cost of SFmode division (fdivs). */ 2083 const int ddiv; /* cost of DFmode division (fdiv). */ 2084 const int cache_line_size; /* cache line size in bytes. */ 2085 const int l1_cache_size; /* size of l1 cache, in kilobytes. */ 2086 const int l2_cache_size; /* size of l2 cache, in kilobytes. */ 2087 const int simultaneous_prefetches; /* number of parallel prefetch 2088 operations. */ 2089 const int sfdf_convert; /* cost of SF->DF conversion. */ 2090 }; 2091 2092 extern const struct processor_costs *rs6000_cost; 2093 2094 /* Control the assembler format that we output. */ 2095 2096 /* A C string constant describing how to begin a comment in the target 2097 assembler language. The compiler assumes that the comment will end at 2098 the end of the line. */ 2099 #define ASM_COMMENT_START " #" 2100 2101 /* Flag to say the TOC is initialized */ 2102 extern int toc_initialized; 2103 2104 /* Macro to output a special constant pool entry. Go to WIN if we output 2105 it. Otherwise, it is written the usual way. 2106 2107 On the RS/6000, toc entries are handled this way. */ 2108 2109 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \ 2110 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \ 2111 { \ 2112 output_toc (FILE, X, LABELNO, MODE); \ 2113 goto WIN; \ 2114 } \ 2115 } 2116 2117 #ifdef HAVE_GAS_WEAK 2118 #define RS6000_WEAK 1 2119 #else 2120 #define RS6000_WEAK 0 2121 #endif 2122 2123 #if RS6000_WEAK 2124 /* Used in lieu of ASM_WEAKEN_LABEL. */ 2125 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \ 2126 rs6000_asm_weaken_decl ((FILE), (DECL), (NAME), (VAL)) 2127 #endif 2128 2129 #if HAVE_GAS_WEAKREF 2130 #define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \ 2131 do \ 2132 { \ 2133 fputs ("\t.weakref\t", (FILE)); \ 2134 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 2135 fputs (", ", (FILE)); \ 2136 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ 2137 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ 2138 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ 2139 { \ 2140 fputs ("\n\t.weakref\t.", (FILE)); \ 2141 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 2142 fputs (", .", (FILE)); \ 2143 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ 2144 } \ 2145 fputc ('\n', (FILE)); \ 2146 } while (0) 2147 #endif 2148 2149 /* This implements the `alias' attribute. */ 2150 #undef ASM_OUTPUT_DEF_FROM_DECLS 2151 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \ 2152 do \ 2153 { \ 2154 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ 2155 const char *name = IDENTIFIER_POINTER (TARGET); \ 2156 if (TREE_CODE (DECL) == FUNCTION_DECL \ 2157 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ 2158 { \ 2159 if (TREE_PUBLIC (DECL)) \ 2160 { \ 2161 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ 2162 { \ 2163 fputs ("\t.globl\t.", FILE); \ 2164 RS6000_OUTPUT_BASENAME (FILE, alias); \ 2165 putc ('\n', FILE); \ 2166 } \ 2167 } \ 2168 else if (TARGET_XCOFF) \ 2169 { \ 2170 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ 2171 { \ 2172 fputs ("\t.lglobl\t.", FILE); \ 2173 RS6000_OUTPUT_BASENAME (FILE, alias); \ 2174 putc ('\n', FILE); \ 2175 fputs ("\t.lglobl\t", FILE); \ 2176 RS6000_OUTPUT_BASENAME (FILE, alias); \ 2177 putc ('\n', FILE); \ 2178 } \ 2179 } \ 2180 fputs ("\t.set\t.", FILE); \ 2181 RS6000_OUTPUT_BASENAME (FILE, alias); \ 2182 fputs (",.", FILE); \ 2183 RS6000_OUTPUT_BASENAME (FILE, name); \ 2184 fputc ('\n', FILE); \ 2185 } \ 2186 ASM_OUTPUT_DEF (FILE, alias, name); \ 2187 } \ 2188 while (0) 2189 2190 #define TARGET_ASM_FILE_START rs6000_file_start 2191 2192 /* Output to assembler file text saying following lines 2193 may contain character constants, extra white space, comments, etc. */ 2194 2195 #define ASM_APP_ON "" 2196 2197 /* Output to assembler file text saying following lines 2198 no longer contain unusual constructs. */ 2199 2200 #define ASM_APP_OFF "" 2201 2202 /* How to refer to registers in assembler output. 2203 This sequence is indexed by compiler's hard-register-number (see above). */ 2204 2205 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ 2206 2207 #define REGISTER_NAMES \ 2208 { \ 2209 &rs6000_reg_names[ 0][0], /* r0 */ \ 2210 &rs6000_reg_names[ 1][0], /* r1 */ \ 2211 &rs6000_reg_names[ 2][0], /* r2 */ \ 2212 &rs6000_reg_names[ 3][0], /* r3 */ \ 2213 &rs6000_reg_names[ 4][0], /* r4 */ \ 2214 &rs6000_reg_names[ 5][0], /* r5 */ \ 2215 &rs6000_reg_names[ 6][0], /* r6 */ \ 2216 &rs6000_reg_names[ 7][0], /* r7 */ \ 2217 &rs6000_reg_names[ 8][0], /* r8 */ \ 2218 &rs6000_reg_names[ 9][0], /* r9 */ \ 2219 &rs6000_reg_names[10][0], /* r10 */ \ 2220 &rs6000_reg_names[11][0], /* r11 */ \ 2221 &rs6000_reg_names[12][0], /* r12 */ \ 2222 &rs6000_reg_names[13][0], /* r13 */ \ 2223 &rs6000_reg_names[14][0], /* r14 */ \ 2224 &rs6000_reg_names[15][0], /* r15 */ \ 2225 &rs6000_reg_names[16][0], /* r16 */ \ 2226 &rs6000_reg_names[17][0], /* r17 */ \ 2227 &rs6000_reg_names[18][0], /* r18 */ \ 2228 &rs6000_reg_names[19][0], /* r19 */ \ 2229 &rs6000_reg_names[20][0], /* r20 */ \ 2230 &rs6000_reg_names[21][0], /* r21 */ \ 2231 &rs6000_reg_names[22][0], /* r22 */ \ 2232 &rs6000_reg_names[23][0], /* r23 */ \ 2233 &rs6000_reg_names[24][0], /* r24 */ \ 2234 &rs6000_reg_names[25][0], /* r25 */ \ 2235 &rs6000_reg_names[26][0], /* r26 */ \ 2236 &rs6000_reg_names[27][0], /* r27 */ \ 2237 &rs6000_reg_names[28][0], /* r28 */ \ 2238 &rs6000_reg_names[29][0], /* r29 */ \ 2239 &rs6000_reg_names[30][0], /* r30 */ \ 2240 &rs6000_reg_names[31][0], /* r31 */ \ 2241 \ 2242 &rs6000_reg_names[32][0], /* fr0 */ \ 2243 &rs6000_reg_names[33][0], /* fr1 */ \ 2244 &rs6000_reg_names[34][0], /* fr2 */ \ 2245 &rs6000_reg_names[35][0], /* fr3 */ \ 2246 &rs6000_reg_names[36][0], /* fr4 */ \ 2247 &rs6000_reg_names[37][0], /* fr5 */ \ 2248 &rs6000_reg_names[38][0], /* fr6 */ \ 2249 &rs6000_reg_names[39][0], /* fr7 */ \ 2250 &rs6000_reg_names[40][0], /* fr8 */ \ 2251 &rs6000_reg_names[41][0], /* fr9 */ \ 2252 &rs6000_reg_names[42][0], /* fr10 */ \ 2253 &rs6000_reg_names[43][0], /* fr11 */ \ 2254 &rs6000_reg_names[44][0], /* fr12 */ \ 2255 &rs6000_reg_names[45][0], /* fr13 */ \ 2256 &rs6000_reg_names[46][0], /* fr14 */ \ 2257 &rs6000_reg_names[47][0], /* fr15 */ \ 2258 &rs6000_reg_names[48][0], /* fr16 */ \ 2259 &rs6000_reg_names[49][0], /* fr17 */ \ 2260 &rs6000_reg_names[50][0], /* fr18 */ \ 2261 &rs6000_reg_names[51][0], /* fr19 */ \ 2262 &rs6000_reg_names[52][0], /* fr20 */ \ 2263 &rs6000_reg_names[53][0], /* fr21 */ \ 2264 &rs6000_reg_names[54][0], /* fr22 */ \ 2265 &rs6000_reg_names[55][0], /* fr23 */ \ 2266 &rs6000_reg_names[56][0], /* fr24 */ \ 2267 &rs6000_reg_names[57][0], /* fr25 */ \ 2268 &rs6000_reg_names[58][0], /* fr26 */ \ 2269 &rs6000_reg_names[59][0], /* fr27 */ \ 2270 &rs6000_reg_names[60][0], /* fr28 */ \ 2271 &rs6000_reg_names[61][0], /* fr29 */ \ 2272 &rs6000_reg_names[62][0], /* fr30 */ \ 2273 &rs6000_reg_names[63][0], /* fr31 */ \ 2274 \ 2275 &rs6000_reg_names[64][0], /* was mq */ \ 2276 &rs6000_reg_names[65][0], /* lr */ \ 2277 &rs6000_reg_names[66][0], /* ctr */ \ 2278 &rs6000_reg_names[67][0], /* ap */ \ 2279 \ 2280 &rs6000_reg_names[68][0], /* cr0 */ \ 2281 &rs6000_reg_names[69][0], /* cr1 */ \ 2282 &rs6000_reg_names[70][0], /* cr2 */ \ 2283 &rs6000_reg_names[71][0], /* cr3 */ \ 2284 &rs6000_reg_names[72][0], /* cr4 */ \ 2285 &rs6000_reg_names[73][0], /* cr5 */ \ 2286 &rs6000_reg_names[74][0], /* cr6 */ \ 2287 &rs6000_reg_names[75][0], /* cr7 */ \ 2288 \ 2289 &rs6000_reg_names[76][0], /* ca */ \ 2290 \ 2291 &rs6000_reg_names[77][0], /* v0 */ \ 2292 &rs6000_reg_names[78][0], /* v1 */ \ 2293 &rs6000_reg_names[79][0], /* v2 */ \ 2294 &rs6000_reg_names[80][0], /* v3 */ \ 2295 &rs6000_reg_names[81][0], /* v4 */ \ 2296 &rs6000_reg_names[82][0], /* v5 */ \ 2297 &rs6000_reg_names[83][0], /* v6 */ \ 2298 &rs6000_reg_names[84][0], /* v7 */ \ 2299 &rs6000_reg_names[85][0], /* v8 */ \ 2300 &rs6000_reg_names[86][0], /* v9 */ \ 2301 &rs6000_reg_names[87][0], /* v10 */ \ 2302 &rs6000_reg_names[88][0], /* v11 */ \ 2303 &rs6000_reg_names[89][0], /* v12 */ \ 2304 &rs6000_reg_names[90][0], /* v13 */ \ 2305 &rs6000_reg_names[91][0], /* v14 */ \ 2306 &rs6000_reg_names[92][0], /* v15 */ \ 2307 &rs6000_reg_names[93][0], /* v16 */ \ 2308 &rs6000_reg_names[94][0], /* v17 */ \ 2309 &rs6000_reg_names[95][0], /* v18 */ \ 2310 &rs6000_reg_names[96][0], /* v19 */ \ 2311 &rs6000_reg_names[97][0], /* v20 */ \ 2312 &rs6000_reg_names[98][0], /* v21 */ \ 2313 &rs6000_reg_names[99][0], /* v22 */ \ 2314 &rs6000_reg_names[100][0], /* v23 */ \ 2315 &rs6000_reg_names[101][0], /* v24 */ \ 2316 &rs6000_reg_names[102][0], /* v25 */ \ 2317 &rs6000_reg_names[103][0], /* v26 */ \ 2318 &rs6000_reg_names[104][0], /* v27 */ \ 2319 &rs6000_reg_names[105][0], /* v28 */ \ 2320 &rs6000_reg_names[106][0], /* v29 */ \ 2321 &rs6000_reg_names[107][0], /* v30 */ \ 2322 &rs6000_reg_names[108][0], /* v31 */ \ 2323 &rs6000_reg_names[109][0], /* vrsave */ \ 2324 &rs6000_reg_names[110][0], /* vscr */ \ 2325 &rs6000_reg_names[111][0], /* sfp */ \ 2326 &rs6000_reg_names[112][0], /* tfhar */ \ 2327 &rs6000_reg_names[113][0], /* tfiar */ \ 2328 &rs6000_reg_names[114][0], /* texasr */ \ 2329 } 2330 2331 /* Table of additional register names to use in user input. */ 2332 2333 #define ADDITIONAL_REGISTER_NAMES \ 2334 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \ 2335 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \ 2336 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \ 2337 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \ 2338 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \ 2339 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \ 2340 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \ 2341 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \ 2342 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \ 2343 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \ 2344 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \ 2345 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \ 2346 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \ 2347 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \ 2348 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \ 2349 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \ 2350 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \ 2351 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \ 2352 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \ 2353 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \ 2354 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \ 2355 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \ 2356 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \ 2357 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \ 2358 {"vrsave", 109}, {"vscr", 110}, \ 2359 /* no additional names for: lr, ctr, ap */ \ 2360 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \ 2361 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \ 2362 {"cc", 68}, {"sp", 1}, {"toc", 2}, \ 2363 /* CA is only part of XER, but we do not model the other parts (yet). */ \ 2364 {"xer", 76}, \ 2365 /* VSX registers overlaid on top of FR, Altivec registers */ \ 2366 {"vs0", 32}, {"vs1", 33}, {"vs2", 34}, {"vs3", 35}, \ 2367 {"vs4", 36}, {"vs5", 37}, {"vs6", 38}, {"vs7", 39}, \ 2368 {"vs8", 40}, {"vs9", 41}, {"vs10", 42}, {"vs11", 43}, \ 2369 {"vs12", 44}, {"vs13", 45}, {"vs14", 46}, {"vs15", 47}, \ 2370 {"vs16", 48}, {"vs17", 49}, {"vs18", 50}, {"vs19", 51}, \ 2371 {"vs20", 52}, {"vs21", 53}, {"vs22", 54}, {"vs23", 55}, \ 2372 {"vs24", 56}, {"vs25", 57}, {"vs26", 58}, {"vs27", 59}, \ 2373 {"vs28", 60}, {"vs29", 61}, {"vs30", 62}, {"vs31", 63}, \ 2374 {"vs32", 77}, {"vs33", 78}, {"vs34", 79}, {"vs35", 80}, \ 2375 {"vs36", 81}, {"vs37", 82}, {"vs38", 83}, {"vs39", 84}, \ 2376 {"vs40", 85}, {"vs41", 86}, {"vs42", 87}, {"vs43", 88}, \ 2377 {"vs44", 89}, {"vs45", 90}, {"vs46", 91}, {"vs47", 92}, \ 2378 {"vs48", 93}, {"vs49", 94}, {"vs50", 95}, {"vs51", 96}, \ 2379 {"vs52", 97}, {"vs53", 98}, {"vs54", 99}, {"vs55", 100}, \ 2380 {"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \ 2381 {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108}, \ 2382 /* Transactional Memory Facility (HTM) Registers. */ \ 2383 {"tfhar", 112}, {"tfiar", 113}, {"texasr", 114}, \ 2384 } 2385 2386 /* This is how to output an element of a case-vector that is relative. */ 2387 2388 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 2389 do { char buf[100]; \ 2390 fputs ("\t.long ", FILE); \ 2391 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \ 2392 assemble_name (FILE, buf); \ 2393 putc ('-', FILE); \ 2394 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \ 2395 assemble_name (FILE, buf); \ 2396 putc ('\n', FILE); \ 2397 } while (0) 2398 2399 /* This is how to output an assembler line 2400 that says to advance the location counter 2401 to a multiple of 2**LOG bytes. */ 2402 2403 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 2404 if ((LOG) != 0) \ 2405 fprintf (FILE, "\t.align %d\n", (LOG)) 2406 2407 /* How to align the given loop. */ 2408 #define LOOP_ALIGN(LABEL) rs6000_loop_align(LABEL) 2409 2410 /* Alignment guaranteed by __builtin_malloc. */ 2411 /* FIXME: 128-bit alignment is guaranteed by glibc for TARGET_64BIT. 2412 However, specifying the stronger guarantee currently leads to 2413 a regression in SPEC CPU2006 437.leslie3d. The stronger 2414 guarantee should be implemented here once that's fixed. */ 2415 #define MALLOC_ABI_ALIGNMENT (64) 2416 2417 /* Pick up the return address upon entry to a procedure. Used for 2418 dwarf2 unwind information. This also enables the table driven 2419 mechanism. */ 2420 2421 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO) 2422 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO) 2423 2424 /* Describe how we implement __builtin_eh_return. */ 2425 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM) 2426 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10) 2427 2428 /* Print operand X (an rtx) in assembler syntax to file FILE. 2429 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 2430 For `%' followed by punctuation, CODE is the punctuation and X is null. */ 2431 2432 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 2433 2434 /* Define which CODE values are valid. */ 2435 2436 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '&') 2437 2438 /* Print a memory address as an operand to reference that memory location. */ 2439 2440 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) 2441 2442 /* For switching between functions with different target attributes. */ 2443 #define SWITCHABLE_TARGET 1 2444 2445 /* uncomment for disabling the corresponding default options */ 2446 /* #define MACHINE_no_sched_interblock */ 2447 /* #define MACHINE_no_sched_speculative */ 2448 /* #define MACHINE_no_sched_speculative_load */ 2449 2450 /* General flags. */ 2451 extern int frame_pointer_needed; 2452 2453 /* Classification of the builtin functions as to which switches enable the 2454 builtin, and what attributes it should have. We used to use the target 2455 flags macros, but we've run out of bits, so we now map the options into new 2456 settings used here. */ 2457 2458 /* Builtin attributes. */ 2459 #define RS6000_BTC_SPECIAL 0x00000000 /* Special function. */ 2460 #define RS6000_BTC_UNARY 0x00000001 /* normal unary function. */ 2461 #define RS6000_BTC_BINARY 0x00000002 /* normal binary function. */ 2462 #define RS6000_BTC_TERNARY 0x00000003 /* normal ternary function. */ 2463 #define RS6000_BTC_PREDICATE 0x00000004 /* predicate function. */ 2464 #define RS6000_BTC_ABS 0x00000005 /* Altivec/VSX ABS function. */ 2465 #define RS6000_BTC_DST 0x00000007 /* Altivec DST function. */ 2466 #define RS6000_BTC_TYPE_MASK 0x0000000f /* Mask to isolate types */ 2467 2468 #define RS6000_BTC_MISC 0x00000000 /* No special attributes. */ 2469 #define RS6000_BTC_CONST 0x00000100 /* Neither uses, nor 2470 modifies global state. */ 2471 #define RS6000_BTC_PURE 0x00000200 /* reads global 2472 state/mem and does 2473 not modify global state. */ 2474 #define RS6000_BTC_FP 0x00000400 /* depends on rounding mode. */ 2475 #define RS6000_BTC_ATTR_MASK 0x00000700 /* Mask of the attributes. */ 2476 2477 /* Miscellaneous information. */ 2478 #define RS6000_BTC_SPR 0x01000000 /* function references SPRs. */ 2479 #define RS6000_BTC_VOID 0x02000000 /* function has no return value. */ 2480 #define RS6000_BTC_CR 0x04000000 /* function references a CR. */ 2481 #define RS6000_BTC_OVERLOADED 0x08000000 /* function is overloaded. */ 2482 #define RS6000_BTC_MISC_MASK 0x1f000000 /* Mask of the misc info. */ 2483 2484 /* Convenience macros to document the instruction type. */ 2485 #define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches mem. */ 2486 #define RS6000_BTC_SAT RS6000_BTC_MISC /* saturate sets VSCR. */ 2487 2488 /* Builtin targets. For now, we reuse the masks for those options that are in 2489 target flags, and pick two random bits for paired and ldbl128, which 2490 aren't in target_flags. */ 2491 #define RS6000_BTM_ALWAYS 0 /* Always enabled. */ 2492 #define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */ 2493 #define RS6000_BTM_CMPB MASK_CMPB /* ISA 2.05: compare bytes. */ 2494 #define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */ 2495 #define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */ 2496 #define RS6000_BTM_P9_VECTOR MASK_P9_VECTOR /* ISA 3.0 vector. */ 2497 #define RS6000_BTM_P9_MISC MASK_P9_MISC /* ISA 3.0 misc. non-vector */ 2498 #define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */ 2499 #define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */ 2500 #define RS6000_BTM_PAIRED MASK_MULHW /* 750CL paired insns. */ 2501 #define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */ 2502 #define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */ 2503 #define RS6000_BTM_FRSQRTE MASK_PPC_GFXOPT /* FRSQRTE instruction. */ 2504 #define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */ 2505 #define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */ 2506 #define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */ 2507 #define RS6000_BTM_DFP MASK_DFP /* Decimal floating point. */ 2508 #define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */ 2509 #define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */ 2510 #define RS6000_BTM_64BIT MASK_64BIT /* 64-bit addressing. */ 2511 #define RS6000_BTM_POWERPC64 MASK_POWERPC64 /* 64-bit registers. */ 2512 #define RS6000_BTM_FLOAT128 MASK_FLOAT128_KEYWORD /* IEEE 128-bit float. */ 2513 #define RS6000_BTM_FLOAT128_HW MASK_FLOAT128_HW /* IEEE 128-bit float h/w. */ 2514 2515 #define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \ 2516 | RS6000_BTM_VSX \ 2517 | RS6000_BTM_P8_VECTOR \ 2518 | RS6000_BTM_P9_VECTOR \ 2519 | RS6000_BTM_P9_MISC \ 2520 | RS6000_BTM_MODULO \ 2521 | RS6000_BTM_CRYPTO \ 2522 | RS6000_BTM_FRE \ 2523 | RS6000_BTM_FRES \ 2524 | RS6000_BTM_FRSQRTE \ 2525 | RS6000_BTM_FRSQRTES \ 2526 | RS6000_BTM_HTM \ 2527 | RS6000_BTM_POPCNTD \ 2528 | RS6000_BTM_CELL \ 2529 | RS6000_BTM_DFP \ 2530 | RS6000_BTM_HARD_FLOAT \ 2531 | RS6000_BTM_LDBL128 \ 2532 | RS6000_BTM_POWERPC64 \ 2533 | RS6000_BTM_FLOAT128 \ 2534 | RS6000_BTM_FLOAT128_HW) 2535 2536 /* Define builtin enum index. */ 2537 2538 #undef RS6000_BUILTIN_0 2539 #undef RS6000_BUILTIN_1 2540 #undef RS6000_BUILTIN_2 2541 #undef RS6000_BUILTIN_3 2542 #undef RS6000_BUILTIN_A 2543 #undef RS6000_BUILTIN_D 2544 #undef RS6000_BUILTIN_H 2545 #undef RS6000_BUILTIN_P 2546 #undef RS6000_BUILTIN_Q 2547 #undef RS6000_BUILTIN_X 2548 2549 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2550 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2551 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2552 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2553 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2554 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2555 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2556 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2557 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2558 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2559 2560 enum rs6000_builtins 2561 { 2562 #include "rs6000-builtin.def" 2563 2564 RS6000_BUILTIN_COUNT 2565 }; 2566 2567 #undef RS6000_BUILTIN_0 2568 #undef RS6000_BUILTIN_1 2569 #undef RS6000_BUILTIN_2 2570 #undef RS6000_BUILTIN_3 2571 #undef RS6000_BUILTIN_A 2572 #undef RS6000_BUILTIN_D 2573 #undef RS6000_BUILTIN_H 2574 #undef RS6000_BUILTIN_P 2575 #undef RS6000_BUILTIN_Q 2576 #undef RS6000_BUILTIN_X 2577 2578 enum rs6000_builtin_type_index 2579 { 2580 RS6000_BTI_NOT_OPAQUE, 2581 RS6000_BTI_opaque_V2SI, 2582 RS6000_BTI_opaque_V2SF, 2583 RS6000_BTI_opaque_p_V2SI, 2584 RS6000_BTI_opaque_V4SI, 2585 RS6000_BTI_V16QI, /* __vector signed char */ 2586 RS6000_BTI_V1TI, 2587 RS6000_BTI_V2SI, 2588 RS6000_BTI_V2SF, 2589 RS6000_BTI_V2DI, 2590 RS6000_BTI_V2DF, 2591 RS6000_BTI_V4HI, 2592 RS6000_BTI_V4SI, 2593 RS6000_BTI_V4SF, 2594 RS6000_BTI_V8HI, 2595 RS6000_BTI_unsigned_V16QI, /* __vector unsigned char */ 2596 RS6000_BTI_unsigned_V1TI, 2597 RS6000_BTI_unsigned_V8HI, 2598 RS6000_BTI_unsigned_V4SI, 2599 RS6000_BTI_unsigned_V2DI, 2600 RS6000_BTI_bool_char, /* __bool char */ 2601 RS6000_BTI_bool_short, /* __bool short */ 2602 RS6000_BTI_bool_int, /* __bool int */ 2603 RS6000_BTI_bool_long_long, /* __bool long long */ 2604 RS6000_BTI_pixel, /* __pixel (16 bits arranged as 4 2605 channels of 1, 5, 5, and 5 bits 2606 respectively as packed with the 2607 vpkpx insn. __pixel is only 2608 meaningful as a vector type. 2609 There is no corresponding scalar 2610 __pixel data type.) */ 2611 RS6000_BTI_bool_V16QI, /* __vector __bool char */ 2612 RS6000_BTI_bool_V8HI, /* __vector __bool short */ 2613 RS6000_BTI_bool_V4SI, /* __vector __bool int */ 2614 RS6000_BTI_bool_V2DI, /* __vector __bool long */ 2615 RS6000_BTI_pixel_V8HI, /* __vector __pixel */ 2616 RS6000_BTI_long, /* long_integer_type_node */ 2617 RS6000_BTI_unsigned_long, /* long_unsigned_type_node */ 2618 RS6000_BTI_long_long, /* long_long_integer_type_node */ 2619 RS6000_BTI_unsigned_long_long, /* long_long_unsigned_type_node */ 2620 RS6000_BTI_INTQI, /* (signed) intQI_type_node */ 2621 RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */ 2622 RS6000_BTI_INTHI, /* intHI_type_node */ 2623 RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */ 2624 RS6000_BTI_INTSI, /* intSI_type_node (signed) */ 2625 RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */ 2626 RS6000_BTI_INTDI, /* intDI_type_node */ 2627 RS6000_BTI_UINTDI, /* unsigned_intDI_type_node */ 2628 RS6000_BTI_INTTI, /* intTI_type_node */ 2629 RS6000_BTI_UINTTI, /* unsigned_intTI_type_node */ 2630 RS6000_BTI_float, /* float_type_node */ 2631 RS6000_BTI_double, /* double_type_node */ 2632 RS6000_BTI_long_double, /* long_double_type_node */ 2633 RS6000_BTI_dfloat64, /* dfloat64_type_node */ 2634 RS6000_BTI_dfloat128, /* dfloat128_type_node */ 2635 RS6000_BTI_void, /* void_type_node */ 2636 RS6000_BTI_ieee128_float, /* ieee 128-bit floating point */ 2637 RS6000_BTI_ibm128_float, /* IBM 128-bit floating point */ 2638 RS6000_BTI_const_str, /* pointer to const char * */ 2639 RS6000_BTI_MAX 2640 }; 2641 2642 2643 #define opaque_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SI]) 2644 #define opaque_V2SF_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SF]) 2645 #define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI]) 2646 #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI]) 2647 #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI]) 2648 #define V1TI_type_node (rs6000_builtin_types[RS6000_BTI_V1TI]) 2649 #define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI]) 2650 #define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF]) 2651 #define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI]) 2652 #define V2SF_type_node (rs6000_builtin_types[RS6000_BTI_V2SF]) 2653 #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI]) 2654 #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI]) 2655 #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF]) 2656 #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI]) 2657 #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI]) 2658 #define unsigned_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V1TI]) 2659 #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI]) 2660 #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI]) 2661 #define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI]) 2662 #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char]) 2663 #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short]) 2664 #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int]) 2665 #define bool_long_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long_long]) 2666 #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel]) 2667 #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI]) 2668 #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI]) 2669 #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI]) 2670 #define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI]) 2671 #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI]) 2672 2673 #define long_long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_long]) 2674 #define long_long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long_long]) 2675 #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long]) 2676 #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long]) 2677 #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI]) 2678 #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI]) 2679 #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI]) 2680 #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI]) 2681 #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI]) 2682 #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI]) 2683 #define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI]) 2684 #define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI]) 2685 #define intTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTTI]) 2686 #define uintTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTTI]) 2687 #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float]) 2688 #define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double]) 2689 #define long_double_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_double]) 2690 #define dfloat64_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat64]) 2691 #define dfloat128_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat128]) 2692 #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void]) 2693 #define ieee128_float_type_node (rs6000_builtin_types[RS6000_BTI_ieee128_float]) 2694 #define ibm128_float_type_node (rs6000_builtin_types[RS6000_BTI_ibm128_float]) 2695 #define const_str_type_node (rs6000_builtin_types[RS6000_BTI_const_str]) 2696 2697 extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX]; 2698 extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT]; 2699 2700 #define TARGET_SUPPORTS_WIDE_INT 1 2701 2702 #if (GCC_VERSION >= 3000) 2703 #pragma GCC poison TARGET_FLOAT128 OPTION_MASK_FLOAT128 MASK_FLOAT128 2704 #endif 2705