1 /***************************************************************************** 2 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 4 more contributor license agreements. See the NOTICE file distributed 5 with this work for additional information regarding copyright ownership. 6 Accellera licenses this file to you under the Apache License, Version 2.0 7 (the "License"); you may not use this file except in compliance with the 8 License. You may obtain a copy of the License at 9 10 http://www.apache.org/licenses/LICENSE-2.0 11 12 Unless required by applicable law or agreed to in writing, software 13 distributed under the License is distributed on an "AS IS" BASIS, 14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 15 implied. See the License for the specific language governing 16 permissions and limitations under the License. 17 18 *****************************************************************************/ 19 20 /***************************************************************************** 21 22 decode.h -- Instruction Decode Unit. 23 24 Original Author: Martin Wang, Synopsys, Inc. 25 26 *****************************************************************************/ 27 28 /***************************************************************************** 29 30 MODIFICATION LOG - modifiers, enter your name, affiliation, date and 31 changes you are making here. 32 33 Name, Affiliation, Date: 34 Description of Modification: 35 36 *****************************************************************************/ 37 38 39 struct decode : sc_module { 40 sc_in<bool> resetin; // input reset 41 sc_in<unsigned> instruction; // fetched instruction 42 sc_in<unsigned> pred_instruction; // fetched instruction 43 sc_in<bool> instruction_valid; // input valid 44 sc_in<bool> pred_inst_valid; // input valid 45 sc_in<bool> destreg_write; // register write enable 46 sc_in<unsigned> destreg_write_src; // which register to write? 47 sc_in<signed> alu_dataout; // data from ALU 48 sc_in<signed> dram_dataout; // data from Dcache 49 sc_in<bool> dram_rd_valid; // Dcache read data valid 50 sc_in<unsigned> dram_write_src; // Dcache data write to which reg 51 sc_in<signed> fpu_dout; // data from FPU 52 sc_in<bool> fpu_valid; // FPU data valid 53 sc_in<unsigned> fpu_destout; // write to which register 54 sc_in<bool> clear_branch; // clear outstanding branch 55 sc_in<bool> display_done; // display to monitor done 56 sc_in<unsigned > pc; // program counter from IFU 57 sc_in<bool> pred_on; // branch prediction is on 58 sc_out<unsigned > br_instruction_address; // branch invoke instruction 59 sc_out<bool> next_pc; // next pc ++ ? 60 sc_out<bool> branch_valid; // branch valid signal 61 sc_out<unsigned > branch_target_address; // branch target address 62 sc_out<bool> mem_access; // memory access valid 63 sc_out<unsigned > mem_address; // memory physical address 64 sc_out<int> alu_op; // ALU/FPU/MMU Opcode 65 sc_out<bool> mem_write; // memory write enable 66 sc_out<unsigned> alu_src; // destination register number 67 sc_out<bool> reg_write; // not implemented 68 sc_out<signed int> src_A; // operand A 69 sc_out<signed int> src_B; // operand B 70 sc_out<bool> forward_A; // data forwarding to operand A 71 sc_out<bool> forward_B; // data forwarding to operand B 72 sc_out<bool> stall_fetch; // stall fetch due to branch 73 sc_out<bool> decode_valid; // decoder output valid 74 sc_out<bool> float_valid; // enable FPU 75 sc_out<bool> mmx_valid; // enable MMU 76 sc_out<bool> pid_valid; // load process ID 77 sc_out<signed> pid_data; // process ID value 78 sc_in_clk CLK; 79 80 81 signed int cpu_reg[32]; //CPU register 82 signed int vcpu_reg[32]; //virtual CPU register 83 bool cpu_reg_lock[32]; //lock architectural state register 84 unsigned int pc_reg; //pc register 85 unsigned int jalpc_reg; //jump back register 86 87 //Constructor SC_CTORdecode88 SC_CTOR(decode) { 89 SC_CTHREAD(entry, CLK.pos()); 90 FILE *fp = fopen("register.img","r"); 91 int size=0; 92 unsigned mem_word; 93 printf("** ALERT ** ID: initialize Architectural Registers\n"); 94 while (fscanf(fp,"%x", &mem_word) != EOF) { 95 cpu_reg[size] = mem_word; 96 size++; 97 } 98 pc_reg = 0; 99 jalpc_reg = 0; 100 for (int j =0; j<32; j++) vcpu_reg[j] = 0; 101 for (int k =0; k<32; k++) cpu_reg_lock[k] = 0; 102 } 103 104 // Process functionality in member function below 105 void entry(); 106 }; 107 108 109