1 /***************************************************************************** 2 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 4 more contributor license agreements. See the NOTICE file distributed 5 with this work for additional information regarding copyright ownership. 6 Accellera licenses this file to you under the Apache License, Version 2.0 7 (the "License"); you may not use this file except in compliance with the 8 License. You may obtain a copy of the License at 9 10 http://www.apache.org/licenses/LICENSE-2.0 11 12 Unless required by applicable law or agreed to in writing, software 13 distributed under the License is distributed on an "AS IS" BASIS, 14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 15 implied. See the License for the specific language governing 16 permissions and limitations under the License. 17 18 *****************************************************************************/ 19 20 //===================================================================== 21 /// @file at_target_ooo_2_phase.h 22 // 23 /// @brief A 2 phase target that has been created to force out of order 24 /// processing of transactions 25 // 26 //===================================================================== 27 // Original Authors: 28 // Bill Bunton, ESLX 29 // Charles Wilson, ESLX 30 // Jack Donovan, ESLX 31 //===================================================================== 32 33 #ifndef __AT_TARGET_OOO_2_PHASE_H__ 34 #define __AT_TARGET_OOO_2_PHASE_H__ 35 36 #include "tlm.h" // TLM headers 37 #include "tlm_utils/peq_with_get.h" // Payload event queue FIFO 38 #include "memory.h" 39 40 class at_target_ooo_2_phase /// at_target_ooo_2_phase 41 : public sc_core::sc_module /// inherit from SC module base clase 42 , virtual public tlm::tlm_fw_transport_if<> /// inherit from TLM "forward interface" 43 { 44 // Member Methods ===================================================== 45 46 public: 47 //===================================================================== 48 /// @fn at_initiator_1_phase 49 /// 50 /// @brief Constructor for Single Phase AT target 51 /// 52 /// @details 53 /// Generic Single Phase target used in several examples. 54 /// Constructor offers several parameters for customization 55 /// 56 //===================================================================== 57 58 at_target_ooo_2_phase 59 ( sc_core::sc_module_name module_name ///< SC module name 60 , const unsigned int ID ///< target ID 61 , const char *memory_socket ///< socket name 62 , sc_dt::uint64 memory_size ///< memory size (bytes) 63 , unsigned int memory_width ///< memory width (bytes) 64 , const sc_core::sc_time accept_delay ///< accept delay (SC_TIME, SC_NS) 65 , const sc_core::sc_time read_response_delay ///< read response delay (SC_TIME, SC_NS) 66 , const sc_core::sc_time write_response_delay ///< write response delay (SC_TIME, SC_NS) 67 ); 68 69 //===================================================================== 70 /// @brief Implementation of call from Initiator. 71 // 72 /// @details 73 /// This is the ultimate destination of the nb_transport_fw call from 74 /// the initiator after being routed trough a Bus 75 // 76 //===================================================================== 77 78 tlm::tlm_sync_enum // sync status 79 nb_transport_fw 80 ( tlm::tlm_generic_payload &gp ///< generic payoad pointer 81 , tlm::tlm_phase &phase ///< transaction phase 82 , sc_core::sc_time &delay_time ///< time taken for transport 83 ); 84 85 //===================================================================== 86 /// @fn at_target_ooo_2_phase::begin_response_method 87 /// 88 /// @brief Response Processing 89 /// 90 /// @details 91 /// This routine takes transaction responses from the m_response_PEQ. 92 /// It contains the state machine to manage the communication path 93 /// back to the initiator. This method is registered as an SC_METHOD 94 /// with the SystemC kernal and is sensitive to m_response_PEQ.get_event() 95 //===================================================================== 96 97 void 98 begin_response_method 99 ( void 100 ); 101 102 private: 103 104 /// helper function for printing memory transactions 105 void 106 print_memory_transaction_helper 107 ( const int &ID 108 , std::ostringstream &partial_msg 109 , tlm::tlm_generic_payload &trans 110 ); 111 112 //============================================================================== 113 // Methods not Implemented for this Example 114 115 /// b_transport() - Blocking Transport 116 void // returns nothing 117 b_transport 118 ( tlm::tlm_generic_payload &payload // ref to payload 119 , sc_core::sc_time &delay_time // delay time 120 ); 121 122 123 /// Not implemented for this example but required by interface 124 bool // success / failure 125 get_direct_mem_ptr 126 ( tlm::tlm_generic_payload &payload, // address + extensions 127 tlm::tlm_dmi &dmi_data // DMI data 128 ); 129 130 131 /// Not implemented for this example but required by interface 132 unsigned int // result 133 transport_dbg 134 ( tlm::tlm_generic_payload &payload // debug payload 135 ); 136 137 // Member Variables =================================================== 138 139 public: 140 141 typedef tlm::tlm_generic_payload *gp_ptr; ///< generic payload pointer 142 143 tlm::tlm_target_socket<> m_memory_socket; ///< target socket 144 145 private: 146 147 const unsigned int m_ID; ///< target ID 148 sc_dt::uint64 m_memory_size; ///< memory size (bytes) 149 unsigned int m_memory_width; ///< word size (bytes) 150 const sc_core::sc_time m_accept_delay; ///< accept delay 151 const sc_core::sc_time m_read_response_delay; ///< read response delay 152 const sc_core::sc_time m_write_response_delay; ///< write response delays 153 unsigned long m_request_count; ///< used to calc synch transactions 154 155 bool m_nb_trans_fw_prev_warning; 156 bool m_begin_resp_method_prev_warning; 157 bool m_trans_dbg_prev_warning; 158 bool m_get_dm_ptr_prev_warning; 159 tlm_utils::peq_with_get<tlm::tlm_generic_payload> 160 m_response_PEQ; ///< response payload event queue 161 sc_core::sc_time m_peq_delay_time; 162 sc_core::sc_time m_delay_for_out_of_order; 163 memory m_target_memory; 164 sc_core::sc_event m_end_resp_rcvd_event; 165 166 }; 167 168 169 #endif /* __AT_TARGET_OOO_2_PHASE_H__ */ 170