1;; Mips.md Machine Description for MIPS based processors 2;; Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 3;; 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. 4;; Contributed by A. Lichnewsky, lich@inria.inria.fr 5;; Changes by Michael Meissner, meissner@osf.org 6;; 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and 7;; Brendan Eich, brendan@microunity.com. 8 9;; This file is part of GCC. 10 11;; GCC is free software; you can redistribute it and/or modify 12;; it under the terms of the GNU General Public License as published by 13;; the Free Software Foundation; either version 2, or (at your option) 14;; any later version. 15 16;; GCC is distributed in the hope that it will be useful, 17;; but WITHOUT ANY WARRANTY; without even the implied warranty of 18;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19;; GNU General Public License for more details. 20 21;; You should have received a copy of the GNU General Public License 22;; along with GCC; see the file COPYING. If not, write to 23;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, 24;; Boston, MA 02110-1301, USA. 25 26(define_constants 27 [(UNSPEC_LOAD_DF_LOW 0) 28 (UNSPEC_LOAD_DF_HIGH 1) 29 (UNSPEC_STORE_DF_HIGH 2) 30 (UNSPEC_GET_FNADDR 3) 31 (UNSPEC_BLOCKAGE 4) 32 (UNSPEC_CPRESTORE 5) 33 (UNSPEC_EH_RECEIVER 6) 34 (UNSPEC_EH_RETURN 7) 35 (UNSPEC_CONSTTABLE_INT 8) 36 (UNSPEC_CONSTTABLE_FLOAT 9) 37 (UNSPEC_ALIGN 14) 38 (UNSPEC_HIGH 17) 39 (UNSPEC_LOAD_LEFT 18) 40 (UNSPEC_LOAD_RIGHT 19) 41 (UNSPEC_STORE_LEFT 20) 42 (UNSPEC_STORE_RIGHT 21) 43 (UNSPEC_LOADGP 22) 44 (UNSPEC_LOAD_CALL 23) 45 (UNSPEC_LOAD_GOT 24) 46 (UNSPEC_GP 25) 47 (UNSPEC_MFHILO 26) 48 (UNSPEC_TLS_LDM 27) 49 (UNSPEC_TLS_GET_TP 28) 50 51 (UNSPEC_ADDRESS_FIRST 100) 52 53 (FAKE_CALL_REGNO 79) 54 55 ;; For MIPS Paired-Singled Floating Point Instructions. 56 57 (UNSPEC_MOVE_TF_PS 200) 58 (UNSPEC_C 201) 59 60 ;; MIPS64/MIPS32R2 alnv.ps 61 (UNSPEC_ALNV_PS 202) 62 63 ;; MIPS-3D instructions 64 (UNSPEC_CABS 203) 65 66 (UNSPEC_ADDR_PS 204) 67 (UNSPEC_CVT_PW_PS 205) 68 (UNSPEC_CVT_PS_PW 206) 69 (UNSPEC_MULR_PS 207) 70 71 (UNSPEC_RSQRT1 208) 72 (UNSPEC_RSQRT2 209) 73 (UNSPEC_RECIP1 210) 74 (UNSPEC_RECIP2 211) 75 76 ;; MIPS DSP ASE Revision 0.98 3/24/2005 77 (UNSPEC_ADDQ 300) 78 (UNSPEC_ADDQ_S 301) 79 (UNSPEC_SUBQ 302) 80 (UNSPEC_SUBQ_S 303) 81 (UNSPEC_ADDSC 304) 82 (UNSPEC_ADDWC 305) 83 (UNSPEC_MODSUB 306) 84 (UNSPEC_RADDU_W_QB 307) 85 (UNSPEC_ABSQ_S 308) 86 (UNSPEC_PRECRQ_QB_PH 309) 87 (UNSPEC_PRECRQ_PH_W 310) 88 (UNSPEC_PRECRQ_RS_PH_W 311) 89 (UNSPEC_PRECRQU_S_QB_PH 312) 90 (UNSPEC_PRECEQ_W_PHL 313) 91 (UNSPEC_PRECEQ_W_PHR 314) 92 (UNSPEC_PRECEQU_PH_QBL 315) 93 (UNSPEC_PRECEQU_PH_QBR 316) 94 (UNSPEC_PRECEQU_PH_QBLA 317) 95 (UNSPEC_PRECEQU_PH_QBRA 318) 96 (UNSPEC_PRECEU_PH_QBL 319) 97 (UNSPEC_PRECEU_PH_QBR 320) 98 (UNSPEC_PRECEU_PH_QBLA 321) 99 (UNSPEC_PRECEU_PH_QBRA 322) 100 (UNSPEC_SHLL 323) 101 (UNSPEC_SHLL_S 324) 102 (UNSPEC_SHRL_QB 325) 103 (UNSPEC_SHRA_PH 326) 104 (UNSPEC_SHRA_R 327) 105 (UNSPEC_MULEU_S_PH_QBL 328) 106 (UNSPEC_MULEU_S_PH_QBR 329) 107 (UNSPEC_MULQ_RS_PH 330) 108 (UNSPEC_MULEQ_S_W_PHL 331) 109 (UNSPEC_MULEQ_S_W_PHR 332) 110 (UNSPEC_DPAU_H_QBL 333) 111 (UNSPEC_DPAU_H_QBR 334) 112 (UNSPEC_DPSU_H_QBL 335) 113 (UNSPEC_DPSU_H_QBR 336) 114 (UNSPEC_DPAQ_S_W_PH 337) 115 (UNSPEC_DPSQ_S_W_PH 338) 116 (UNSPEC_MULSAQ_S_W_PH 339) 117 (UNSPEC_DPAQ_SA_L_W 340) 118 (UNSPEC_DPSQ_SA_L_W 341) 119 (UNSPEC_MAQ_S_W_PHL 342) 120 (UNSPEC_MAQ_S_W_PHR 343) 121 (UNSPEC_MAQ_SA_W_PHL 344) 122 (UNSPEC_MAQ_SA_W_PHR 345) 123 (UNSPEC_BITREV 346) 124 (UNSPEC_INSV 347) 125 (UNSPEC_REPL_QB 348) 126 (UNSPEC_REPL_PH 349) 127 (UNSPEC_CMP_EQ 350) 128 (UNSPEC_CMP_LT 351) 129 (UNSPEC_CMP_LE 352) 130 (UNSPEC_CMPGU_EQ_QB 353) 131 (UNSPEC_CMPGU_LT_QB 354) 132 (UNSPEC_CMPGU_LE_QB 355) 133 (UNSPEC_PICK 356) 134 (UNSPEC_PACKRL_PH 357) 135 (UNSPEC_EXTR_W 358) 136 (UNSPEC_EXTR_R_W 359) 137 (UNSPEC_EXTR_RS_W 360) 138 (UNSPEC_EXTR_S_H 361) 139 (UNSPEC_EXTP 362) 140 (UNSPEC_EXTPDP 363) 141 (UNSPEC_SHILO 364) 142 (UNSPEC_MTHLIP 365) 143 (UNSPEC_WRDSP 366) 144 (UNSPEC_RDDSP 367) 145 ] 146) 147 148(include "predicates.md") 149 150;; .................... 151;; 152;; Attributes 153;; 154;; .................... 155 156(define_attr "got" "unset,xgot_high,load" 157 (const_string "unset")) 158 159;; For jal instructions, this attribute is DIRECT when the target address 160;; is symbolic and INDIRECT when it is a register. 161(define_attr "jal" "unset,direct,indirect" 162 (const_string "unset")) 163 164;; This attribute is YES if the instruction is a jal macro (not a 165;; real jal instruction). 166;; 167;; jal is always a macro in SVR4 PIC since it includes an instruction to 168;; restore $gp. Direct jals are also macros in NewABI PIC since they 169;; load the target address into $25. 170(define_attr "jal_macro" "no,yes" 171 (cond [(eq_attr "jal" "direct") 172 (symbol_ref "TARGET_ABICALLS != 0") 173 (eq_attr "jal" "indirect") 174 (symbol_ref "(TARGET_ABICALLS && !TARGET_NEWABI) != 0")] 175 (const_string "no"))) 176 177;; Classification of each insn. 178;; branch conditional branch 179;; jump unconditional jump 180;; call unconditional call 181;; load load instruction(s) 182;; fpload floating point load 183;; fpidxload floating point indexed load 184;; store store instruction(s) 185;; fpstore floating point store 186;; fpidxstore floating point indexed store 187;; prefetch memory prefetch (register + offset) 188;; prefetchx memory indexed prefetch (register + register) 189;; condmove conditional moves 190;; xfer transfer to/from coprocessor 191;; mthilo transfer to hi/lo registers 192;; mfhilo transfer from hi/lo registers 193;; const load constant 194;; arith integer arithmetic and logical instructions 195;; shift integer shift instructions 196;; slt set less than instructions 197;; clz the clz and clo instructions 198;; trap trap if instructions 199;; imul integer multiply 2 operands 200;; imul3 integer multiply 3 operands 201;; imadd integer multiply-add 202;; idiv integer divide 203;; fmove floating point register move 204;; fadd floating point add/subtract 205;; fmul floating point multiply 206;; fmadd floating point multiply-add 207;; fdiv floating point divide 208;; frdiv floating point reciprocal divide 209;; frdiv1 floating point reciprocal divide step 1 210;; frdiv2 floating point reciprocal divide step 2 211;; fabs floating point absolute value 212;; fneg floating point negation 213;; fcmp floating point compare 214;; fcvt floating point convert 215;; fsqrt floating point square root 216;; frsqrt floating point reciprocal square root 217;; frsqrt1 floating point reciprocal square root step1 218;; frsqrt2 floating point reciprocal square root step2 219;; multi multiword sequence (or user asm statements) 220;; nop no operation 221(define_attr "type" 222 "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,prefetch,prefetchx,condmove,xfer,mthilo,mfhilo,const,arith,shift,slt,clz,trap,imul,imul3,imadd,idiv,fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,frsqrt1,frsqrt2,multi,nop" 223 (cond [(eq_attr "jal" "!unset") (const_string "call") 224 (eq_attr "got" "load") (const_string "load")] 225 (const_string "unknown"))) 226 227;; Main data type used by the insn 228(define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW" 229 (const_string "unknown")) 230 231;; Mode for conversion types (fcvt) 232;; I2S integer to float single (SI/DI to SF) 233;; I2D integer to float double (SI/DI to DF) 234;; S2I float to integer (SF to SI/DI) 235;; D2I float to integer (DF to SI/DI) 236;; D2S double to float single 237;; S2D float single to double 238 239(define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D" 240 (const_string "unknown")) 241 242;; Is this an extended instruction in mips16 mode? 243(define_attr "extended_mips16" "no,yes" 244 (const_string "no")) 245 246;; Length of instruction in bytes. 247(define_attr "length" "" 248 (cond [;; Direct branch instructions have a range of [-0x40000,0x3fffc]. 249 ;; If a branch is outside this range, we have a choice of two 250 ;; sequences. For PIC, an out-of-range branch like: 251 ;; 252 ;; bne r1,r2,target 253 ;; dslot 254 ;; 255 ;; becomes the equivalent of: 256 ;; 257 ;; beq r1,r2,1f 258 ;; dslot 259 ;; la $at,target 260 ;; jr $at 261 ;; nop 262 ;; 1: 263 ;; 264 ;; where the load address can be up to three instructions long 265 ;; (lw, nop, addiu). 266 ;; 267 ;; The non-PIC case is similar except that we use a direct 268 ;; jump instead of an la/jr pair. Since the target of this 269 ;; jump is an absolute 28-bit bit address (the other bits 270 ;; coming from the address of the delay slot) this form cannot 271 ;; cross a 256MB boundary. We could provide the option of 272 ;; using la/jr in this case too, but we do not do so at 273 ;; present. 274 ;; 275 ;; Note that this value does not account for the delay slot 276 ;; instruction, whose length is added separately. If the RTL 277 ;; pattern has no explicit delay slot, mips_adjust_insn_length 278 ;; will add the length of the implicit nop. The values for 279 ;; forward and backward branches will be different as well. 280 (eq_attr "type" "branch") 281 (cond [(and (le (minus (match_dup 1) (pc)) (const_int 131064)) 282 (le (minus (pc) (match_dup 1)) (const_int 131068))) 283 (const_int 4) 284 (ne (symbol_ref "flag_pic") (const_int 0)) 285 (const_int 24) 286 ] (const_int 12)) 287 288 (eq_attr "got" "load") 289 (const_int 4) 290 (eq_attr "got" "xgot_high") 291 (const_int 8) 292 293 (eq_attr "type" "const") 294 (symbol_ref "mips_const_insns (operands[1]) * 4") 295 (eq_attr "type" "load,fpload") 296 (symbol_ref "mips_fetch_insns (operands[1]) * 4") 297 (eq_attr "type" "store,fpstore") 298 (symbol_ref "mips_fetch_insns (operands[0]) * 4") 299 300 ;; In the worst case, a call macro will take 8 instructions: 301 ;; 302 ;; lui $25,%call_hi(FOO) 303 ;; addu $25,$25,$28 304 ;; lw $25,%call_lo(FOO)($25) 305 ;; nop 306 ;; jalr $25 307 ;; nop 308 ;; lw $gp,X($sp) 309 ;; nop 310 (eq_attr "jal_macro" "yes") 311 (const_int 32) 312 313 (and (eq_attr "extended_mips16" "yes") 314 (ne (symbol_ref "TARGET_MIPS16") (const_int 0))) 315 (const_int 8) 316 317 ;; Various VR4120 errata require a nop to be inserted after a macc 318 ;; instruction. The assembler does this for us, so account for 319 ;; the worst-case length here. 320 (and (eq_attr "type" "imadd") 321 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0))) 322 (const_int 8) 323 324 ;; VR4120 errata MD(4): if there are consecutive dmult instructions, 325 ;; the result of the second one is missed. The assembler should work 326 ;; around this by inserting a nop after the first dmult. 327 (and (eq_attr "type" "imul,imul3") 328 (and (eq_attr "mode" "DI") 329 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0)))) 330 (const_int 8) 331 332 (eq_attr "type" "idiv") 333 (symbol_ref "mips_idiv_insns () * 4") 334 ] (const_int 4))) 335 336;; Attribute describing the processor. This attribute must match exactly 337;; with the processor_type enumeration in mips.h. 338(define_attr "cpu" 339 "r3000,4kc,4kp,5kc,5kf,20kc,24k,24kx,m4k,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sr71000" 340 (const (symbol_ref "mips_tune"))) 341 342;; The type of hardware hazard associated with this instruction. 343;; DELAY means that the next instruction cannot read the result 344;; of this one. HILO means that the next two instructions cannot 345;; write to HI or LO. 346(define_attr "hazard" "none,delay,hilo" 347 (cond [(and (eq_attr "type" "load,fpload,fpidxload") 348 (ne (symbol_ref "ISA_HAS_LOAD_DELAY") (const_int 0))) 349 (const_string "delay") 350 351 (and (eq_attr "type" "xfer") 352 (ne (symbol_ref "ISA_HAS_XFER_DELAY") (const_int 0))) 353 (const_string "delay") 354 355 (and (eq_attr "type" "fcmp") 356 (ne (symbol_ref "ISA_HAS_FCMP_DELAY") (const_int 0))) 357 (const_string "delay") 358 359 ;; The r4000 multiplication patterns include an mflo instruction. 360 (and (eq_attr "type" "imul") 361 (ne (symbol_ref "TARGET_FIX_R4000") (const_int 0))) 362 (const_string "hilo") 363 364 (and (eq_attr "type" "mfhilo") 365 (eq (symbol_ref "ISA_HAS_HILO_INTERLOCKS") (const_int 0))) 366 (const_string "hilo")] 367 (const_string "none"))) 368 369;; Is it a single instruction? 370(define_attr "single_insn" "no,yes" 371 (symbol_ref "get_attr_length (insn) == (TARGET_MIPS16 ? 2 : 4)")) 372 373;; Can the instruction be put into a delay slot? 374(define_attr "can_delay" "no,yes" 375 (if_then_else (and (eq_attr "type" "!branch,call,jump") 376 (and (eq_attr "hazard" "none") 377 (eq_attr "single_insn" "yes"))) 378 (const_string "yes") 379 (const_string "no"))) 380 381;; Attribute defining whether or not we can use the branch-likely instructions 382(define_attr "branch_likely" "no,yes" 383 (const 384 (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0)) 385 (const_string "yes") 386 (const_string "no")))) 387 388;; True if an instruction might assign to hi or lo when reloaded. 389;; This is used by the TUNE_MACC_CHAINS code. 390(define_attr "may_clobber_hilo" "no,yes" 391 (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthilo") 392 (const_string "yes") 393 (const_string "no"))) 394 395;; Describe a user's asm statement. 396(define_asm_attributes 397 [(set_attr "type" "multi") 398 (set_attr "can_delay" "no")]) 399 400;; This mode macro allows 32-bit and 64-bit GPR patterns to be generated 401;; from the same template. 402(define_mode_macro GPR [SI (DI "TARGET_64BIT")]) 403 404;; This mode macro allows :P to be used for patterns that operate on 405;; pointer-sized quantities. Exactly one of the two alternatives will match. 406(define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")]) 407 408;; This mode macro allows :MOVECC to be used anywhere that a 409;; conditional-move-type condition is needed. 410(define_mode_macro MOVECC [SI (DI "TARGET_64BIT") (CC "TARGET_HARD_FLOAT")]) 411 412;; This mode macro allows the QI and HI extension patterns to be defined from 413;; the same template. 414(define_mode_macro SHORT [QI HI]) 415 416;; This mode macro allows :ANYF to be used wherever a scalar or vector 417;; floating-point mode is allowed. 418(define_mode_macro ANYF [(SF "TARGET_HARD_FLOAT") 419 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT") 420 (V2SF "TARGET_PAIRED_SINGLE_FLOAT")]) 421 422;; Like ANYF, but only applies to scalar modes. 423(define_mode_macro SCALARF [(SF "TARGET_HARD_FLOAT") 424 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")]) 425 426;; In GPR templates, a string like "<d>subu" will expand to "subu" in the 427;; 32-bit version and "dsubu" in the 64-bit version. 428(define_mode_attr d [(SI "") (DI "d")]) 429 430;; This attribute gives the length suffix for a sign- or zero-extension 431;; instruction. 432(define_mode_attr size [(QI "b") (HI "h")]) 433 434;; This attributes gives the mode mask of a SHORT. 435(define_mode_attr mask [(QI "0x00ff") (HI "0xffff")]) 436 437;; Mode attributes for GPR loads and stores. 438(define_mode_attr load [(SI "lw") (DI "ld")]) 439(define_mode_attr store [(SI "sw") (DI "sd")]) 440 441;; Similarly for MIPS IV indexed FPR loads and stores. 442(define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")]) 443(define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")]) 444 445;; The unextended ranges of the MIPS16 addiu and daddiu instructions 446;; are different. Some forms of unextended addiu have an 8-bit immediate 447;; field but the equivalent daddiu has only a 5-bit field. 448(define_mode_attr si8_di5 [(SI "8") (DI "5")]) 449 450;; This attribute gives the best constraint to use for registers of 451;; a given mode. 452(define_mode_attr reg [(SI "d") (DI "d") (CC "z")]) 453 454;; This attribute gives the format suffix for floating-point operations. 455(define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")]) 456 457;; This attribute gives the upper-case mode name for one unit of a 458;; floating-point mode. 459(define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF")]) 460 461;; This attribute works around the early SB-1 rev2 core "F2" erratum: 462;; 463;; In certain cases, div.s and div.ps may have a rounding error 464;; and/or wrong inexact flag. 465;; 466;; Therefore, we only allow div.s if not working around SB-1 rev2 467;; errata or if a slight loss of precision is OK. 468(define_mode_attr divide_condition 469 [DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations") 470 (V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")]) 471 472; This attribute gives the condition for which sqrt instructions exist. 473(define_mode_attr sqrt_condition 474 [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")]) 475 476; This attribute gives the condition for which recip and rsqrt instructions 477; exist. 478(define_mode_attr recip_condition 479 [(SF "ISA_HAS_FP4") (DF "ISA_HAS_FP4") (V2SF "TARGET_SB1")]) 480 481;; This code macro allows all branch instructions to be generated from 482;; a single define_expand template. 483(define_code_macro any_cond [unordered ordered unlt unge uneq ltgt unle ungt 484 eq ne gt ge lt le gtu geu ltu leu]) 485 486;; This code macro allows signed and unsigned widening multiplications 487;; to use the same template. 488(define_code_macro any_extend [sign_extend zero_extend]) 489 490;; This code macro allows the three shift instructions to be generated 491;; from the same template. 492(define_code_macro any_shift [ashift ashiftrt lshiftrt]) 493 494;; This code macro allows all native floating-point comparisons to be 495;; generated from the same template. 496(define_code_macro fcond [unordered uneq unlt unle eq lt le]) 497 498;; This code macro is used for comparisons that can be implemented 499;; by swapping the operands. 500(define_code_macro swapped_fcond [ge gt unge ungt]) 501 502;; <u> expands to an empty string when doing a signed operation and 503;; "u" when doing an unsigned operation. 504(define_code_attr u [(sign_extend "") (zero_extend "u")]) 505 506;; <su> is like <u>, but the signed form expands to "s" rather than "". 507(define_code_attr su [(sign_extend "s") (zero_extend "u")]) 508 509;; <optab> expands to the name of the optab for a particular code. 510(define_code_attr optab [(ashift "ashl") 511 (ashiftrt "ashr") 512 (lshiftrt "lshr")]) 513 514;; <insn> expands to the name of the insn that implements a particular code. 515(define_code_attr insn [(ashift "sll") 516 (ashiftrt "sra") 517 (lshiftrt "srl")]) 518 519;; <fcond> is the c.cond.fmt condition associated with a particular code. 520(define_code_attr fcond [(unordered "un") 521 (uneq "ueq") 522 (unlt "ult") 523 (unle "ule") 524 (eq "eq") 525 (lt "lt") 526 (le "le")]) 527 528;; Similar, but for swapped conditions. 529(define_code_attr swapped_fcond [(ge "le") 530 (gt "lt") 531 (unge "ule") 532 (ungt "ult")]) 533 534;; ......................... 535;; 536;; Branch, call and jump delay slots 537;; 538;; ......................... 539 540(define_delay (and (eq_attr "type" "branch") 541 (eq (symbol_ref "TARGET_MIPS16") (const_int 0))) 542 [(eq_attr "can_delay" "yes") 543 (nil) 544 (and (eq_attr "branch_likely" "yes") 545 (eq_attr "can_delay" "yes"))]) 546 547(define_delay (eq_attr "type" "jump") 548 [(eq_attr "can_delay" "yes") 549 (nil) 550 (nil)]) 551 552(define_delay (and (eq_attr "type" "call") 553 (eq_attr "jal_macro" "no")) 554 [(eq_attr "can_delay" "yes") 555 (nil) 556 (nil)]) 557 558;; Pipeline descriptions. 559;; 560;; generic.md provides a fallback for processors without a specific 561;; pipeline description. It is derived from the old define_function_unit 562;; version and uses the "alu" and "imuldiv" units declared below. 563;; 564;; Some of the processor-specific files are also derived from old 565;; define_function_unit descriptions and simply override the parts of 566;; generic.md that don't apply. The other processor-specific files 567;; are self-contained. 568(define_automaton "alu,imuldiv") 569 570(define_cpu_unit "alu" "alu") 571(define_cpu_unit "imuldiv" "imuldiv") 572 573(include "4k.md") 574(include "5k.md") 575(include "24k.md") 576(include "3000.md") 577(include "4000.md") 578(include "4100.md") 579(include "4130.md") 580(include "4300.md") 581(include "4600.md") 582(include "5000.md") 583(include "5400.md") 584(include "5500.md") 585(include "6000.md") 586(include "7000.md") 587(include "9000.md") 588(include "sb1.md") 589(include "sr71k.md") 590(include "generic.md") 591 592;; 593;; .................... 594;; 595;; CONDITIONAL TRAPS 596;; 597;; .................... 598;; 599 600(define_insn "trap" 601 [(trap_if (const_int 1) (const_int 0))] 602 "" 603{ 604 if (ISA_HAS_COND_TRAP) 605 return "teq\t$0,$0"; 606 else if (TARGET_MIPS16) 607 return "break 0"; 608 else 609 return "break"; 610} 611 [(set_attr "type" "trap")]) 612 613(define_expand "conditional_trap" 614 [(trap_if (match_operator 0 "comparison_operator" 615 [(match_dup 2) (match_dup 3)]) 616 (match_operand 1 "const_int_operand"))] 617 "ISA_HAS_COND_TRAP" 618{ 619 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT 620 && operands[1] == const0_rtx) 621 { 622 mips_gen_conditional_trap (operands); 623 DONE; 624 } 625 else 626 FAIL; 627}) 628 629(define_insn "*conditional_trap<mode>" 630 [(trap_if (match_operator:GPR 0 "trap_comparison_operator" 631 [(match_operand:GPR 1 "reg_or_0_operand" "dJ") 632 (match_operand:GPR 2 "arith_operand" "dI")]) 633 (const_int 0))] 634 "ISA_HAS_COND_TRAP" 635 "t%C0\t%z1,%2" 636 [(set_attr "type" "trap")]) 637 638;; 639;; .................... 640;; 641;; ADDITION 642;; 643;; .................... 644;; 645 646(define_insn "add<mode>3" 647 [(set (match_operand:ANYF 0 "register_operand" "=f") 648 (plus:ANYF (match_operand:ANYF 1 "register_operand" "f") 649 (match_operand:ANYF 2 "register_operand" "f")))] 650 "" 651 "add.<fmt>\t%0,%1,%2" 652 [(set_attr "type" "fadd") 653 (set_attr "mode" "<UNITMODE>")]) 654 655(define_expand "add<mode>3" 656 [(set (match_operand:GPR 0 "register_operand") 657 (plus:GPR (match_operand:GPR 1 "register_operand") 658 (match_operand:GPR 2 "arith_operand")))] 659 "") 660 661(define_insn "*add<mode>3" 662 [(set (match_operand:GPR 0 "register_operand" "=d,d") 663 (plus:GPR (match_operand:GPR 1 "register_operand" "d,d") 664 (match_operand:GPR 2 "arith_operand" "d,Q")))] 665 "!TARGET_MIPS16" 666 "@ 667 <d>addu\t%0,%1,%2 668 <d>addiu\t%0,%1,%2" 669 [(set_attr "type" "arith") 670 (set_attr "mode" "<MODE>")]) 671 672;; We need to recognize MIPS16 stack pointer additions explicitly, since 673;; we don't have a constraint for $sp. These insns will be generated by 674;; the save_restore_insns functions. 675 676(define_insn "*add<mode>3_sp1" 677 [(set (reg:GPR 29) 678 (plus:GPR (reg:GPR 29) 679 (match_operand:GPR 0 "const_arith_operand" "")))] 680 "TARGET_MIPS16" 681 "<d>addiu\t%$,%$,%0" 682 [(set_attr "type" "arith") 683 (set_attr "mode" "<MODE>") 684 (set (attr "length") (if_then_else (match_operand 0 "m16_simm8_8") 685 (const_int 4) 686 (const_int 8)))]) 687 688(define_insn "*add<mode>3_sp2" 689 [(set (match_operand:GPR 0 "register_operand" "=d") 690 (plus:GPR (reg:GPR 29) 691 (match_operand:GPR 1 "const_arith_operand" "")))] 692 "TARGET_MIPS16" 693 "<d>addiu\t%0,%$,%1" 694 [(set_attr "type" "arith") 695 (set_attr "mode" "<MODE>") 696 (set (attr "length") (if_then_else (match_operand 1 "m16_uimm<si8_di5>_4") 697 (const_int 4) 698 (const_int 8)))]) 699 700(define_insn "*add<mode>3_mips16" 701 [(set (match_operand:GPR 0 "register_operand" "=d,d,d") 702 (plus:GPR (match_operand:GPR 1 "register_operand" "0,d,d") 703 (match_operand:GPR 2 "arith_operand" "Q,O,d")))] 704 "TARGET_MIPS16" 705 "@ 706 <d>addiu\t%0,%2 707 <d>addiu\t%0,%1,%2 708 <d>addu\t%0,%1,%2" 709 [(set_attr "type" "arith") 710 (set_attr "mode" "<MODE>") 711 (set_attr_alternative "length" 712 [(if_then_else (match_operand 2 "m16_simm<si8_di5>_1") 713 (const_int 4) 714 (const_int 8)) 715 (if_then_else (match_operand 2 "m16_simm4_1") 716 (const_int 4) 717 (const_int 8)) 718 (const_int 4)])]) 719 720 721;; On the mips16, we can sometimes split an add of a constant which is 722;; a 4 byte instruction into two adds which are both 2 byte 723;; instructions. There are two cases: one where we are adding a 724;; constant plus a register to another register, and one where we are 725;; simply adding a constant to a register. 726 727(define_split 728 [(set (match_operand:SI 0 "register_operand") 729 (plus:SI (match_dup 0) 730 (match_operand:SI 1 "const_int_operand")))] 731 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE 732 && REG_P (operands[0]) 733 && M16_REG_P (REGNO (operands[0])) 734 && GET_CODE (operands[1]) == CONST_INT 735 && ((INTVAL (operands[1]) > 0x7f 736 && INTVAL (operands[1]) <= 0x7f + 0x7f) 737 || (INTVAL (operands[1]) < - 0x80 738 && INTVAL (operands[1]) >= - 0x80 - 0x80))" 739 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1))) 740 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))] 741{ 742 HOST_WIDE_INT val = INTVAL (operands[1]); 743 744 if (val >= 0) 745 { 746 operands[1] = GEN_INT (0x7f); 747 operands[2] = GEN_INT (val - 0x7f); 748 } 749 else 750 { 751 operands[1] = GEN_INT (- 0x80); 752 operands[2] = GEN_INT (val + 0x80); 753 } 754}) 755 756(define_split 757 [(set (match_operand:SI 0 "register_operand") 758 (plus:SI (match_operand:SI 1 "register_operand") 759 (match_operand:SI 2 "const_int_operand")))] 760 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE 761 && REG_P (operands[0]) 762 && M16_REG_P (REGNO (operands[0])) 763 && REG_P (operands[1]) 764 && M16_REG_P (REGNO (operands[1])) 765 && REGNO (operands[0]) != REGNO (operands[1]) 766 && GET_CODE (operands[2]) == CONST_INT 767 && ((INTVAL (operands[2]) > 0x7 768 && INTVAL (operands[2]) <= 0x7 + 0x7f) 769 || (INTVAL (operands[2]) < - 0x8 770 && INTVAL (operands[2]) >= - 0x8 - 0x80))" 771 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2))) 772 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))] 773{ 774 HOST_WIDE_INT val = INTVAL (operands[2]); 775 776 if (val >= 0) 777 { 778 operands[2] = GEN_INT (0x7); 779 operands[3] = GEN_INT (val - 0x7); 780 } 781 else 782 { 783 operands[2] = GEN_INT (- 0x8); 784 operands[3] = GEN_INT (val + 0x8); 785 } 786}) 787 788(define_split 789 [(set (match_operand:DI 0 "register_operand") 790 (plus:DI (match_dup 0) 791 (match_operand:DI 1 "const_int_operand")))] 792 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE 793 && REG_P (operands[0]) 794 && M16_REG_P (REGNO (operands[0])) 795 && GET_CODE (operands[1]) == CONST_INT 796 && ((INTVAL (operands[1]) > 0xf 797 && INTVAL (operands[1]) <= 0xf + 0xf) 798 || (INTVAL (operands[1]) < - 0x10 799 && INTVAL (operands[1]) >= - 0x10 - 0x10))" 800 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1))) 801 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))] 802{ 803 HOST_WIDE_INT val = INTVAL (operands[1]); 804 805 if (val >= 0) 806 { 807 operands[1] = GEN_INT (0xf); 808 operands[2] = GEN_INT (val - 0xf); 809 } 810 else 811 { 812 operands[1] = GEN_INT (- 0x10); 813 operands[2] = GEN_INT (val + 0x10); 814 } 815}) 816 817(define_split 818 [(set (match_operand:DI 0 "register_operand") 819 (plus:DI (match_operand:DI 1 "register_operand") 820 (match_operand:DI 2 "const_int_operand")))] 821 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE 822 && REG_P (operands[0]) 823 && M16_REG_P (REGNO (operands[0])) 824 && REG_P (operands[1]) 825 && M16_REG_P (REGNO (operands[1])) 826 && REGNO (operands[0]) != REGNO (operands[1]) 827 && GET_CODE (operands[2]) == CONST_INT 828 && ((INTVAL (operands[2]) > 0x7 829 && INTVAL (operands[2]) <= 0x7 + 0xf) 830 || (INTVAL (operands[2]) < - 0x8 831 && INTVAL (operands[2]) >= - 0x8 - 0x10))" 832 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2))) 833 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] 834{ 835 HOST_WIDE_INT val = INTVAL (operands[2]); 836 837 if (val >= 0) 838 { 839 operands[2] = GEN_INT (0x7); 840 operands[3] = GEN_INT (val - 0x7); 841 } 842 else 843 { 844 operands[2] = GEN_INT (- 0x8); 845 operands[3] = GEN_INT (val + 0x8); 846 } 847}) 848 849(define_insn "*addsi3_extended" 850 [(set (match_operand:DI 0 "register_operand" "=d,d") 851 (sign_extend:DI 852 (plus:SI (match_operand:SI 1 "register_operand" "d,d") 853 (match_operand:SI 2 "arith_operand" "d,Q"))))] 854 "TARGET_64BIT && !TARGET_MIPS16" 855 "@ 856 addu\t%0,%1,%2 857 addiu\t%0,%1,%2" 858 [(set_attr "type" "arith") 859 (set_attr "mode" "SI")]) 860 861;; Split this insn so that the addiu splitters can have a crack at it. 862;; Use a conservative length estimate until the split. 863(define_insn_and_split "*addsi3_extended_mips16" 864 [(set (match_operand:DI 0 "register_operand" "=d,d,d") 865 (sign_extend:DI 866 (plus:SI (match_operand:SI 1 "register_operand" "0,d,d") 867 (match_operand:SI 2 "arith_operand" "Q,O,d"))))] 868 "TARGET_64BIT && TARGET_MIPS16" 869 "#" 870 "&& reload_completed" 871 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))] 872 { operands[3] = gen_lowpart (SImode, operands[0]); } 873 [(set_attr "type" "arith") 874 (set_attr "mode" "SI") 875 (set_attr "extended_mips16" "yes")]) 876 877;; 878;; .................... 879;; 880;; SUBTRACTION 881;; 882;; .................... 883;; 884 885(define_insn "sub<mode>3" 886 [(set (match_operand:ANYF 0 "register_operand" "=f") 887 (minus:ANYF (match_operand:ANYF 1 "register_operand" "f") 888 (match_operand:ANYF 2 "register_operand" "f")))] 889 "" 890 "sub.<fmt>\t%0,%1,%2" 891 [(set_attr "type" "fadd") 892 (set_attr "mode" "<UNITMODE>")]) 893 894(define_insn "sub<mode>3" 895 [(set (match_operand:GPR 0 "register_operand" "=d") 896 (minus:GPR (match_operand:GPR 1 "register_operand" "d") 897 (match_operand:GPR 2 "register_operand" "d")))] 898 "" 899 "<d>subu\t%0,%1,%2" 900 [(set_attr "type" "arith") 901 (set_attr "mode" "<MODE>")]) 902 903(define_insn "*subsi3_extended" 904 [(set (match_operand:DI 0 "register_operand" "=d") 905 (sign_extend:DI 906 (minus:SI (match_operand:SI 1 "register_operand" "d") 907 (match_operand:SI 2 "register_operand" "d"))))] 908 "TARGET_64BIT" 909 "subu\t%0,%1,%2" 910 [(set_attr "type" "arith") 911 (set_attr "mode" "DI")]) 912 913;; 914;; .................... 915;; 916;; MULTIPLICATION 917;; 918;; .................... 919;; 920 921(define_expand "mul<mode>3" 922 [(set (match_operand:SCALARF 0 "register_operand") 923 (mult:SCALARF (match_operand:SCALARF 1 "register_operand") 924 (match_operand:SCALARF 2 "register_operand")))] 925 "" 926 "") 927 928(define_insn "*mul<mode>3" 929 [(set (match_operand:SCALARF 0 "register_operand" "=f") 930 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f") 931 (match_operand:SCALARF 2 "register_operand" "f")))] 932 "!TARGET_4300_MUL_FIX" 933 "mul.<fmt>\t%0,%1,%2" 934 [(set_attr "type" "fmul") 935 (set_attr "mode" "<MODE>")]) 936 937;; Early VR4300 silicon has a CPU bug where multiplies with certain 938;; operands may corrupt immediately following multiplies. This is a 939;; simple fix to insert NOPs. 940 941(define_insn "*mul<mode>3_r4300" 942 [(set (match_operand:SCALARF 0 "register_operand" "=f") 943 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f") 944 (match_operand:SCALARF 2 "register_operand" "f")))] 945 "TARGET_4300_MUL_FIX" 946 "mul.<fmt>\t%0,%1,%2\;nop" 947 [(set_attr "type" "fmul") 948 (set_attr "mode" "<MODE>") 949 (set_attr "length" "8")]) 950 951(define_insn "mulv2sf3" 952 [(set (match_operand:V2SF 0 "register_operand" "=f") 953 (mult:V2SF (match_operand:V2SF 1 "register_operand" "f") 954 (match_operand:V2SF 2 "register_operand" "f")))] 955 "TARGET_PAIRED_SINGLE_FLOAT" 956 "mul.ps\t%0,%1,%2" 957 [(set_attr "type" "fmul") 958 (set_attr "mode" "SF")]) 959 960;; The original R4000 has a cpu bug. If a double-word or a variable 961;; shift executes while an integer multiplication is in progress, the 962;; shift may give an incorrect result. Avoid this by keeping the mflo 963;; with the mult on the R4000. 964;; 965;; From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0" 966;; (also valid for MIPS R4000MC processors): 967;; 968;; "16. R4000PC, R4000SC: Please refer to errata 28 for an update to 969;; this errata description. 970;; The following code sequence causes the R4000 to incorrectly 971;; execute the Double Shift Right Arithmetic 32 (dsra32) 972;; instruction. If the dsra32 instruction is executed during an 973;; integer multiply, the dsra32 will only shift by the amount in 974;; specified in the instruction rather than the amount plus 32 975;; bits. 976;; instruction 1: mult rs,rt integer multiply 977;; instruction 2-12: dsra32 rd,rt,rs doubleword shift 978;; right arithmetic + 32 979;; Workaround: A dsra32 instruction placed after an integer 980;; multiply should not be one of the 11 instructions after the 981;; multiply instruction." 982;; 983;; and: 984;; 985;; "28. R4000PC, R4000SC: The text from errata 16 should be replaced by 986;; the following description. 987;; All extended shifts (shift by n+32) and variable shifts (32 and 988;; 64-bit versions) may produce incorrect results under the 989;; following conditions: 990;; 1) An integer multiply is currently executing 991;; 2) These types of shift instructions are executed immediately 992;; following an integer divide instruction. 993;; Workaround: 994;; 1) Make sure no integer multiply is running wihen these 995;; instruction are executed. If this cannot be predicted at 996;; compile time, then insert a "mfhi" to R0 instruction 997;; immediately after the integer multiply instruction. This 998;; will cause the integer multiply to complete before the shift 999;; is executed. 1000;; 2) Separate integer divide and these two classes of shift 1001;; instructions by another instruction or a noop." 1002;; 1003;; These processors have PRId values of 0x00004220 and 0x00004300, 1004;; respectively. 1005 1006(define_expand "mul<mode>3" 1007 [(set (match_operand:GPR 0 "register_operand") 1008 (mult:GPR (match_operand:GPR 1 "register_operand") 1009 (match_operand:GPR 2 "register_operand")))] 1010 "" 1011{ 1012 if (GENERATE_MULT3_<MODE>) 1013 emit_insn (gen_mul<mode>3_mult3 (operands[0], operands[1], operands[2])); 1014 else if (!TARGET_FIX_R4000) 1015 emit_insn (gen_mul<mode>3_internal (operands[0], operands[1], 1016 operands[2])); 1017 else 1018 emit_insn (gen_mul<mode>3_r4000 (operands[0], operands[1], operands[2])); 1019 DONE; 1020}) 1021 1022(define_insn "mulsi3_mult3" 1023 [(set (match_operand:SI 0 "register_operand" "=d,l") 1024 (mult:SI (match_operand:SI 1 "register_operand" "d,d") 1025 (match_operand:SI 2 "register_operand" "d,d"))) 1026 (clobber (match_scratch:SI 3 "=h,h")) 1027 (clobber (match_scratch:SI 4 "=l,X"))] 1028 "GENERATE_MULT3_SI" 1029{ 1030 if (which_alternative == 1) 1031 return "mult\t%1,%2"; 1032 if (TARGET_MAD 1033 || TARGET_MIPS5400 1034 || TARGET_MIPS5500 1035 || TARGET_MIPS7000 1036 || TARGET_MIPS9000 1037 || ISA_MIPS32 1038 || ISA_MIPS32R2 1039 || ISA_MIPS64) 1040 return "mul\t%0,%1,%2"; 1041 return "mult\t%0,%1,%2"; 1042} 1043 [(set_attr "type" "imul3,imul") 1044 (set_attr "mode" "SI")]) 1045 1046(define_insn "muldi3_mult3" 1047 [(set (match_operand:DI 0 "register_operand" "=d") 1048 (mult:DI (match_operand:DI 1 "register_operand" "d") 1049 (match_operand:DI 2 "register_operand" "d"))) 1050 (clobber (match_scratch:DI 3 "=h")) 1051 (clobber (match_scratch:DI 4 "=l"))] 1052 "TARGET_64BIT && GENERATE_MULT3_DI" 1053 "dmult\t%0,%1,%2" 1054 [(set_attr "type" "imul3") 1055 (set_attr "mode" "DI")]) 1056 1057;; If a register gets allocated to LO, and we spill to memory, the reload 1058;; will include a move from LO to a GPR. Merge it into the multiplication 1059;; if it can set the GPR directly. 1060;; 1061;; Operand 0: LO 1062;; Operand 1: GPR (1st multiplication operand) 1063;; Operand 2: GPR (2nd multiplication operand) 1064;; Operand 3: HI 1065;; Operand 4: GPR (destination) 1066(define_peephole2 1067 [(parallel 1068 [(set (match_operand:SI 0 "register_operand") 1069 (mult:SI (match_operand:SI 1 "register_operand") 1070 (match_operand:SI 2 "register_operand"))) 1071 (clobber (match_operand:SI 3 "register_operand")) 1072 (clobber (scratch:SI))]) 1073 (set (match_operand:SI 4 "register_operand") 1074 (unspec [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))] 1075 "GENERATE_MULT3_SI && peep2_reg_dead_p (2, operands[0])" 1076 [(parallel 1077 [(set (match_dup 4) 1078 (mult:SI (match_dup 1) 1079 (match_dup 2))) 1080 (clobber (match_dup 3)) 1081 (clobber (match_dup 0))])]) 1082 1083(define_insn "mul<mode>3_internal" 1084 [(set (match_operand:GPR 0 "register_operand" "=l") 1085 (mult:GPR (match_operand:GPR 1 "register_operand" "d") 1086 (match_operand:GPR 2 "register_operand" "d"))) 1087 (clobber (match_scratch:GPR 3 "=h"))] 1088 "!TARGET_FIX_R4000" 1089 "<d>mult\t%1,%2" 1090 [(set_attr "type" "imul") 1091 (set_attr "mode" "<MODE>")]) 1092 1093(define_insn "mul<mode>3_r4000" 1094 [(set (match_operand:GPR 0 "register_operand" "=d") 1095 (mult:GPR (match_operand:GPR 1 "register_operand" "d") 1096 (match_operand:GPR 2 "register_operand" "d"))) 1097 (clobber (match_scratch:GPR 3 "=h")) 1098 (clobber (match_scratch:GPR 4 "=l"))] 1099 "TARGET_FIX_R4000" 1100 "<d>mult\t%1,%2\;mflo\t%0" 1101 [(set_attr "type" "imul") 1102 (set_attr "mode" "<MODE>") 1103 (set_attr "length" "8")]) 1104 1105;; On the VR4120 and VR4130, it is better to use "mtlo $0; macc" instead 1106;; of "mult; mflo". They have the same latency, but the first form gives 1107;; us an extra cycle to compute the operands. 1108 1109;; Operand 0: LO 1110;; Operand 1: GPR (1st multiplication operand) 1111;; Operand 2: GPR (2nd multiplication operand) 1112;; Operand 3: HI 1113;; Operand 4: GPR (destination) 1114(define_peephole2 1115 [(parallel 1116 [(set (match_operand:SI 0 "register_operand") 1117 (mult:SI (match_operand:SI 1 "register_operand") 1118 (match_operand:SI 2 "register_operand"))) 1119 (clobber (match_operand:SI 3 "register_operand"))]) 1120 (set (match_operand:SI 4 "register_operand") 1121 (unspec:SI [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))] 1122 "ISA_HAS_MACC && !GENERATE_MULT3_SI" 1123 [(set (match_dup 0) 1124 (const_int 0)) 1125 (parallel 1126 [(set (match_dup 0) 1127 (plus:SI (mult:SI (match_dup 1) 1128 (match_dup 2)) 1129 (match_dup 0))) 1130 (set (match_dup 4) 1131 (plus:SI (mult:SI (match_dup 1) 1132 (match_dup 2)) 1133 (match_dup 0))) 1134 (clobber (match_dup 3))])]) 1135 1136;; Multiply-accumulate patterns 1137 1138;; For processors that can copy the output to a general register: 1139;; 1140;; The all-d alternative is needed because the combiner will find this 1141;; pattern and then register alloc/reload will move registers around to 1142;; make them fit, and we don't want to trigger unnecessary loads to LO. 1143;; 1144;; The last alternative should be made slightly less desirable, but adding 1145;; "?" to the constraint is too strong, and causes values to be loaded into 1146;; LO even when that's more costly. For now, using "*d" mostly does the 1147;; trick. 1148(define_insn "*mul_acc_si" 1149 [(set (match_operand:SI 0 "register_operand" "=l,*d,*d") 1150 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d") 1151 (match_operand:SI 2 "register_operand" "d,d,d")) 1152 (match_operand:SI 3 "register_operand" "0,l,*d"))) 1153 (clobber (match_scratch:SI 4 "=h,h,h")) 1154 (clobber (match_scratch:SI 5 "=X,3,l")) 1155 (clobber (match_scratch:SI 6 "=X,X,&d"))] 1156 "(TARGET_MIPS3900 1157 || ISA_HAS_MADD_MSUB) 1158 && !TARGET_MIPS16" 1159{ 1160 static const char *const madd[] = { "madd\t%1,%2", "madd\t%0,%1,%2" }; 1161 if (which_alternative == 2) 1162 return "#"; 1163 if (ISA_HAS_MADD_MSUB && which_alternative != 0) 1164 return "#"; 1165 return madd[which_alternative]; 1166} 1167 [(set_attr "type" "imadd,imadd,multi") 1168 (set_attr "mode" "SI") 1169 (set_attr "length" "4,4,8")]) 1170 1171;; Split the above insn if we failed to get LO allocated. 1172(define_split 1173 [(set (match_operand:SI 0 "register_operand") 1174 (plus:SI (mult:SI (match_operand:SI 1 "register_operand") 1175 (match_operand:SI 2 "register_operand")) 1176 (match_operand:SI 3 "register_operand"))) 1177 (clobber (match_scratch:SI 4)) 1178 (clobber (match_scratch:SI 5)) 1179 (clobber (match_scratch:SI 6))] 1180 "reload_completed && !TARGET_DEBUG_D_MODE 1181 && GP_REG_P (true_regnum (operands[0])) 1182 && GP_REG_P (true_regnum (operands[3]))" 1183 [(parallel [(set (match_dup 6) 1184 (mult:SI (match_dup 1) (match_dup 2))) 1185 (clobber (match_dup 4)) 1186 (clobber (match_dup 5))]) 1187 (set (match_dup 0) (plus:SI (match_dup 6) (match_dup 3)))] 1188 "") 1189 1190;; Splitter to copy result of MADD to a general register 1191(define_split 1192 [(set (match_operand:SI 0 "register_operand") 1193 (plus:SI (mult:SI (match_operand:SI 1 "register_operand") 1194 (match_operand:SI 2 "register_operand")) 1195 (match_operand:SI 3 "register_operand"))) 1196 (clobber (match_scratch:SI 4)) 1197 (clobber (match_scratch:SI 5)) 1198 (clobber (match_scratch:SI 6))] 1199 "reload_completed && !TARGET_DEBUG_D_MODE 1200 && GP_REG_P (true_regnum (operands[0])) 1201 && true_regnum (operands[3]) == LO_REGNUM" 1202 [(parallel [(set (match_dup 3) 1203 (plus:SI (mult:SI (match_dup 1) (match_dup 2)) 1204 (match_dup 3))) 1205 (clobber (match_dup 4)) 1206 (clobber (match_dup 5)) 1207 (clobber (match_dup 6))]) 1208 (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))] 1209 "") 1210 1211(define_insn "*macc" 1212 [(set (match_operand:SI 0 "register_operand" "=l,d") 1213 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d") 1214 (match_operand:SI 2 "register_operand" "d,d")) 1215 (match_operand:SI 3 "register_operand" "0,l"))) 1216 (clobber (match_scratch:SI 4 "=h,h")) 1217 (clobber (match_scratch:SI 5 "=X,3"))] 1218 "ISA_HAS_MACC" 1219{ 1220 if (which_alternative == 1) 1221 return "macc\t%0,%1,%2"; 1222 else if (TARGET_MIPS5500) 1223 return "madd\t%1,%2"; 1224 else 1225 /* The VR4130 assumes that there is a two-cycle latency between a macc 1226 that "writes" to $0 and an instruction that reads from it. We avoid 1227 this by assigning to $1 instead. */ 1228 return "%[macc\t%@,%1,%2%]"; 1229} 1230 [(set_attr "type" "imadd") 1231 (set_attr "mode" "SI")]) 1232 1233(define_insn "*msac" 1234 [(set (match_operand:SI 0 "register_operand" "=l,d") 1235 (minus:SI (match_operand:SI 1 "register_operand" "0,l") 1236 (mult:SI (match_operand:SI 2 "register_operand" "d,d") 1237 (match_operand:SI 3 "register_operand" "d,d")))) 1238 (clobber (match_scratch:SI 4 "=h,h")) 1239 (clobber (match_scratch:SI 5 "=X,1"))] 1240 "ISA_HAS_MSAC" 1241{ 1242 if (which_alternative == 1) 1243 return "msac\t%0,%2,%3"; 1244 else if (TARGET_MIPS5500) 1245 return "msub\t%2,%3"; 1246 else 1247 return "msac\t$0,%2,%3"; 1248} 1249 [(set_attr "type" "imadd") 1250 (set_attr "mode" "SI")]) 1251 1252;; An msac-like instruction implemented using negation and a macc. 1253(define_insn_and_split "*msac_using_macc" 1254 [(set (match_operand:SI 0 "register_operand" "=l,d") 1255 (minus:SI (match_operand:SI 1 "register_operand" "0,l") 1256 (mult:SI (match_operand:SI 2 "register_operand" "d,d") 1257 (match_operand:SI 3 "register_operand" "d,d")))) 1258 (clobber (match_scratch:SI 4 "=h,h")) 1259 (clobber (match_scratch:SI 5 "=X,1")) 1260 (clobber (match_scratch:SI 6 "=d,d"))] 1261 "ISA_HAS_MACC && !ISA_HAS_MSAC" 1262 "#" 1263 "&& reload_completed" 1264 [(set (match_dup 6) 1265 (neg:SI (match_dup 3))) 1266 (parallel 1267 [(set (match_dup 0) 1268 (plus:SI (mult:SI (match_dup 2) 1269 (match_dup 6)) 1270 (match_dup 1))) 1271 (clobber (match_dup 4)) 1272 (clobber (match_dup 5))])] 1273 "" 1274 [(set_attr "type" "imadd") 1275 (set_attr "length" "8")]) 1276 1277;; Patterns generated by the define_peephole2 below. 1278 1279(define_insn "*macc2" 1280 [(set (match_operand:SI 0 "register_operand" "=l") 1281 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d") 1282 (match_operand:SI 2 "register_operand" "d")) 1283 (match_dup 0))) 1284 (set (match_operand:SI 3 "register_operand" "=d") 1285 (plus:SI (mult:SI (match_dup 1) 1286 (match_dup 2)) 1287 (match_dup 0))) 1288 (clobber (match_scratch:SI 4 "=h"))] 1289 "ISA_HAS_MACC && reload_completed" 1290 "macc\t%3,%1,%2" 1291 [(set_attr "type" "imadd") 1292 (set_attr "mode" "SI")]) 1293 1294(define_insn "*msac2" 1295 [(set (match_operand:SI 0 "register_operand" "=l") 1296 (minus:SI (match_dup 0) 1297 (mult:SI (match_operand:SI 1 "register_operand" "d") 1298 (match_operand:SI 2 "register_operand" "d")))) 1299 (set (match_operand:SI 3 "register_operand" "=d") 1300 (minus:SI (match_dup 0) 1301 (mult:SI (match_dup 1) 1302 (match_dup 2)))) 1303 (clobber (match_scratch:SI 4 "=h"))] 1304 "ISA_HAS_MSAC && reload_completed" 1305 "msac\t%3,%1,%2" 1306 [(set_attr "type" "imadd") 1307 (set_attr "mode" "SI")]) 1308 1309;; Convert macc $0,<r1>,<r2> & mflo <r3> into macc <r3>,<r1>,<r2> 1310;; Similarly msac. 1311;; 1312;; Operand 0: LO 1313;; Operand 1: macc/msac 1314;; Operand 2: HI 1315;; Operand 3: GPR (destination) 1316(define_peephole2 1317 [(parallel 1318 [(set (match_operand:SI 0 "register_operand") 1319 (match_operand:SI 1 "macc_msac_operand")) 1320 (clobber (match_operand:SI 2 "register_operand")) 1321 (clobber (scratch:SI))]) 1322 (set (match_operand:SI 3 "register_operand") 1323 (unspec:SI [(match_dup 0) (match_dup 2)] UNSPEC_MFHILO))] 1324 "" 1325 [(parallel [(set (match_dup 0) 1326 (match_dup 1)) 1327 (set (match_dup 3) 1328 (match_dup 1)) 1329 (clobber (match_dup 2))])] 1330 "") 1331 1332;; When we have a three-address multiplication instruction, it should 1333;; be faster to do a separate multiply and add, rather than moving 1334;; something into LO in order to use a macc instruction. 1335;; 1336;; This peephole needs a scratch register to cater for the case when one 1337;; of the multiplication operands is the same as the destination. 1338;; 1339;; Operand 0: GPR (scratch) 1340;; Operand 1: LO 1341;; Operand 2: GPR (addend) 1342;; Operand 3: GPR (destination) 1343;; Operand 4: macc/msac 1344;; Operand 5: HI 1345;; Operand 6: new multiplication 1346;; Operand 7: new addition/subtraction 1347(define_peephole2 1348 [(match_scratch:SI 0 "d") 1349 (set (match_operand:SI 1 "register_operand") 1350 (match_operand:SI 2 "register_operand")) 1351 (match_dup 0) 1352 (parallel 1353 [(set (match_operand:SI 3 "register_operand") 1354 (match_operand:SI 4 "macc_msac_operand")) 1355 (clobber (match_operand:SI 5 "register_operand")) 1356 (clobber (match_dup 1))])] 1357 "GENERATE_MULT3_SI 1358 && true_regnum (operands[1]) == LO_REGNUM 1359 && peep2_reg_dead_p (2, operands[1]) 1360 && GP_REG_P (true_regnum (operands[3]))" 1361 [(parallel [(set (match_dup 0) 1362 (match_dup 6)) 1363 (clobber (match_dup 5)) 1364 (clobber (match_dup 1))]) 1365 (set (match_dup 3) 1366 (match_dup 7))] 1367{ 1368 operands[6] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1); 1369 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode, 1370 operands[2], operands[0]); 1371}) 1372 1373;; Same as above, except LO is the initial target of the macc. 1374;; 1375;; Operand 0: GPR (scratch) 1376;; Operand 1: LO 1377;; Operand 2: GPR (addend) 1378;; Operand 3: macc/msac 1379;; Operand 4: HI 1380;; Operand 5: GPR (destination) 1381;; Operand 6: new multiplication 1382;; Operand 7: new addition/subtraction 1383(define_peephole2 1384 [(match_scratch:SI 0 "d") 1385 (set (match_operand:SI 1 "register_operand") 1386 (match_operand:SI 2 "register_operand")) 1387 (match_dup 0) 1388 (parallel 1389 [(set (match_dup 1) 1390 (match_operand:SI 3 "macc_msac_operand")) 1391 (clobber (match_operand:SI 4 "register_operand")) 1392 (clobber (scratch:SI))]) 1393 (match_dup 0) 1394 (set (match_operand:SI 5 "register_operand") 1395 (unspec:SI [(match_dup 1) (match_dup 4)] UNSPEC_MFHILO))] 1396 "GENERATE_MULT3_SI && peep2_reg_dead_p (3, operands[1])" 1397 [(parallel [(set (match_dup 0) 1398 (match_dup 6)) 1399 (clobber (match_dup 4)) 1400 (clobber (match_dup 1))]) 1401 (set (match_dup 5) 1402 (match_dup 7))] 1403{ 1404 operands[6] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1); 1405 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode, 1406 operands[2], operands[0]); 1407}) 1408 1409(define_insn "*mul_sub_si" 1410 [(set (match_operand:SI 0 "register_operand" "=l,*d,*d") 1411 (minus:SI (match_operand:SI 1 "register_operand" "0,l,*d") 1412 (mult:SI (match_operand:SI 2 "register_operand" "d,d,d") 1413 (match_operand:SI 3 "register_operand" "d,d,d")))) 1414 (clobber (match_scratch:SI 4 "=h,h,h")) 1415 (clobber (match_scratch:SI 5 "=X,1,l")) 1416 (clobber (match_scratch:SI 6 "=X,X,&d"))] 1417 "ISA_HAS_MADD_MSUB" 1418 "@ 1419 msub\t%2,%3 1420 # 1421 #" 1422 [(set_attr "type" "imadd,multi,multi") 1423 (set_attr "mode" "SI") 1424 (set_attr "length" "4,8,8")]) 1425 1426;; Split the above insn if we failed to get LO allocated. 1427(define_split 1428 [(set (match_operand:SI 0 "register_operand") 1429 (minus:SI (match_operand:SI 1 "register_operand") 1430 (mult:SI (match_operand:SI 2 "register_operand") 1431 (match_operand:SI 3 "register_operand")))) 1432 (clobber (match_scratch:SI 4)) 1433 (clobber (match_scratch:SI 5)) 1434 (clobber (match_scratch:SI 6))] 1435 "reload_completed && !TARGET_DEBUG_D_MODE 1436 && GP_REG_P (true_regnum (operands[0])) 1437 && GP_REG_P (true_regnum (operands[1]))" 1438 [(parallel [(set (match_dup 6) 1439 (mult:SI (match_dup 2) (match_dup 3))) 1440 (clobber (match_dup 4)) 1441 (clobber (match_dup 5))]) 1442 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 6)))] 1443 "") 1444 1445;; Splitter to copy result of MSUB to a general register 1446(define_split 1447 [(set (match_operand:SI 0 "register_operand") 1448 (minus:SI (match_operand:SI 1 "register_operand") 1449 (mult:SI (match_operand:SI 2 "register_operand") 1450 (match_operand:SI 3 "register_operand")))) 1451 (clobber (match_scratch:SI 4)) 1452 (clobber (match_scratch:SI 5)) 1453 (clobber (match_scratch:SI 6))] 1454 "reload_completed && !TARGET_DEBUG_D_MODE 1455 && GP_REG_P (true_regnum (operands[0])) 1456 && true_regnum (operands[1]) == LO_REGNUM" 1457 [(parallel [(set (match_dup 1) 1458 (minus:SI (match_dup 1) 1459 (mult:SI (match_dup 2) (match_dup 3)))) 1460 (clobber (match_dup 4)) 1461 (clobber (match_dup 5)) 1462 (clobber (match_dup 6))]) 1463 (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))] 1464 "") 1465 1466(define_insn "*muls" 1467 [(set (match_operand:SI 0 "register_operand" "=l,d") 1468 (neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d") 1469 (match_operand:SI 2 "register_operand" "d,d")))) 1470 (clobber (match_scratch:SI 3 "=h,h")) 1471 (clobber (match_scratch:SI 4 "=X,l"))] 1472 "ISA_HAS_MULS" 1473 "@ 1474 muls\t$0,%1,%2 1475 muls\t%0,%1,%2" 1476 [(set_attr "type" "imul,imul3") 1477 (set_attr "mode" "SI")]) 1478 1479;; ??? We could define a mulditi3 pattern when TARGET_64BIT. 1480 1481(define_expand "<u>mulsidi3" 1482 [(parallel 1483 [(set (match_operand:DI 0 "register_operand") 1484 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand")) 1485 (any_extend:DI (match_operand:SI 2 "register_operand")))) 1486 (clobber (scratch:DI)) 1487 (clobber (scratch:DI)) 1488 (clobber (scratch:DI))])] 1489 "!TARGET_64BIT || !TARGET_FIX_R4000" 1490{ 1491 if (!TARGET_64BIT) 1492 { 1493 if (!TARGET_FIX_R4000) 1494 emit_insn (gen_<u>mulsidi3_32bit_internal (operands[0], operands[1], 1495 operands[2])); 1496 else 1497 emit_insn (gen_<u>mulsidi3_32bit_r4000 (operands[0], operands[1], 1498 operands[2])); 1499 DONE; 1500 } 1501}) 1502 1503(define_insn "<u>mulsidi3_32bit_internal" 1504 [(set (match_operand:DI 0 "register_operand" "=x") 1505 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 1506 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))] 1507 "!TARGET_64BIT && !TARGET_FIX_R4000" 1508 "mult<u>\t%1,%2" 1509 [(set_attr "type" "imul") 1510 (set_attr "mode" "SI")]) 1511 1512(define_insn "<u>mulsidi3_32bit_r4000" 1513 [(set (match_operand:DI 0 "register_operand" "=d") 1514 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 1515 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))) 1516 (clobber (match_scratch:DI 3 "=x"))] 1517 "!TARGET_64BIT && TARGET_FIX_R4000" 1518 "mult<u>\t%1,%2\;mflo\t%L0;mfhi\t%M0" 1519 [(set_attr "type" "imul") 1520 (set_attr "mode" "SI") 1521 (set_attr "length" "12")]) 1522 1523(define_insn_and_split "*<u>mulsidi3_64bit" 1524 [(set (match_operand:DI 0 "register_operand" "=d") 1525 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 1526 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))) 1527 (clobber (match_scratch:DI 3 "=l")) 1528 (clobber (match_scratch:DI 4 "=h")) 1529 (clobber (match_scratch:DI 5 "=d"))] 1530 "TARGET_64BIT && !TARGET_FIX_R4000" 1531 "#" 1532 "&& reload_completed" 1533 [(parallel 1534 [(set (match_dup 3) 1535 (sign_extend:DI 1536 (mult:SI (match_dup 1) 1537 (match_dup 2)))) 1538 (set (match_dup 4) 1539 (ashiftrt:DI 1540 (mult:DI (any_extend:DI (match_dup 1)) 1541 (any_extend:DI (match_dup 2))) 1542 (const_int 32)))]) 1543 1544 ;; OP5 <- LO, OP0 <- HI 1545 (set (match_dup 5) (unspec:DI [(match_dup 3) (match_dup 4)] UNSPEC_MFHILO)) 1546 (set (match_dup 0) (unspec:DI [(match_dup 4) (match_dup 3)] UNSPEC_MFHILO)) 1547 1548 ;; Zero-extend OP5. 1549 (set (match_dup 5) 1550 (ashift:DI (match_dup 5) 1551 (const_int 32))) 1552 (set (match_dup 5) 1553 (lshiftrt:DI (match_dup 5) 1554 (const_int 32))) 1555 1556 ;; Shift OP0 into place. 1557 (set (match_dup 0) 1558 (ashift:DI (match_dup 0) 1559 (const_int 32))) 1560 1561 ;; OR the two halves together 1562 (set (match_dup 0) 1563 (ior:DI (match_dup 0) 1564 (match_dup 5)))] 1565 "" 1566 [(set_attr "type" "imul") 1567 (set_attr "mode" "SI") 1568 (set_attr "length" "24")]) 1569 1570(define_insn "*<u>mulsidi3_64bit_parts" 1571 [(set (match_operand:DI 0 "register_operand" "=l") 1572 (sign_extend:DI 1573 (mult:SI (match_operand:SI 2 "register_operand" "d") 1574 (match_operand:SI 3 "register_operand" "d")))) 1575 (set (match_operand:DI 1 "register_operand" "=h") 1576 (ashiftrt:DI 1577 (mult:DI (any_extend:DI (match_dup 2)) 1578 (any_extend:DI (match_dup 3))) 1579 (const_int 32)))] 1580 "TARGET_64BIT && !TARGET_FIX_R4000" 1581 "mult<u>\t%2,%3" 1582 [(set_attr "type" "imul") 1583 (set_attr "mode" "SI")]) 1584 1585;; Widening multiply with negation. 1586(define_insn "*muls<u>_di" 1587 [(set (match_operand:DI 0 "register_operand" "=x") 1588 (neg:DI 1589 (mult:DI 1590 (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 1591 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))] 1592 "!TARGET_64BIT && ISA_HAS_MULS" 1593 "muls<u>\t$0,%1,%2" 1594 [(set_attr "type" "imul") 1595 (set_attr "mode" "SI")]) 1596 1597(define_insn "*msac<u>_di" 1598 [(set (match_operand:DI 0 "register_operand" "=x") 1599 (minus:DI 1600 (match_operand:DI 3 "register_operand" "0") 1601 (mult:DI 1602 (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 1603 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))] 1604 "!TARGET_64BIT && ISA_HAS_MSAC" 1605{ 1606 if (TARGET_MIPS5500) 1607 return "msub<u>\t%1,%2"; 1608 else 1609 return "msac<u>\t$0,%1,%2"; 1610} 1611 [(set_attr "type" "imadd") 1612 (set_attr "mode" "SI")]) 1613 1614;; _highpart patterns 1615 1616(define_expand "<su>mulsi3_highpart" 1617 [(set (match_operand:SI 0 "register_operand") 1618 (truncate:SI 1619 (lshiftrt:DI 1620 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand")) 1621 (any_extend:DI (match_operand:SI 2 "register_operand"))) 1622 (const_int 32))))] 1623 "ISA_HAS_MULHI || !TARGET_FIX_R4000" 1624{ 1625 if (ISA_HAS_MULHI) 1626 emit_insn (gen_<su>mulsi3_highpart_mulhi_internal (operands[0], 1627 operands[1], 1628 operands[2])); 1629 else 1630 emit_insn (gen_<su>mulsi3_highpart_internal (operands[0], operands[1], 1631 operands[2])); 1632 DONE; 1633}) 1634 1635(define_insn "<su>mulsi3_highpart_internal" 1636 [(set (match_operand:SI 0 "register_operand" "=h") 1637 (truncate:SI 1638 (lshiftrt:DI 1639 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 1640 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))) 1641 (const_int 32)))) 1642 (clobber (match_scratch:SI 3 "=l"))] 1643 "!ISA_HAS_MULHI && !TARGET_FIX_R4000" 1644 "mult<u>\t%1,%2" 1645 [(set_attr "type" "imul") 1646 (set_attr "mode" "SI")]) 1647 1648(define_insn "<su>mulsi3_highpart_mulhi_internal" 1649 [(set (match_operand:SI 0 "register_operand" "=h,d") 1650 (truncate:SI 1651 (lshiftrt:DI 1652 (mult:DI 1653 (any_extend:DI (match_operand:SI 1 "register_operand" "d,d")) 1654 (any_extend:DI (match_operand:SI 2 "register_operand" "d,d"))) 1655 (const_int 32)))) 1656 (clobber (match_scratch:SI 3 "=l,l")) 1657 (clobber (match_scratch:SI 4 "=X,h"))] 1658 "ISA_HAS_MULHI" 1659 "@ 1660 mult<u>\t%1,%2 1661 mulhi<u>\t%0,%1,%2" 1662 [(set_attr "type" "imul,imul3") 1663 (set_attr "mode" "SI")]) 1664 1665(define_insn "*<su>mulsi3_highpart_neg_mulhi_internal" 1666 [(set (match_operand:SI 0 "register_operand" "=h,d") 1667 (truncate:SI 1668 (lshiftrt:DI 1669 (neg:DI 1670 (mult:DI 1671 (any_extend:DI (match_operand:SI 1 "register_operand" "d,d")) 1672 (any_extend:DI (match_operand:SI 2 "register_operand" "d,d")))) 1673 (const_int 32)))) 1674 (clobber (match_scratch:SI 3 "=l,l")) 1675 (clobber (match_scratch:SI 4 "=X,h"))] 1676 "ISA_HAS_MULHI" 1677 "@ 1678 mulshi<u>\t%.,%1,%2 1679 mulshi<u>\t%0,%1,%2" 1680 [(set_attr "type" "imul,imul3") 1681 (set_attr "mode" "SI")]) 1682 1683;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120 1684;; errata MD(0), which says that dmultu does not always produce the 1685;; correct result. 1686(define_insn "<su>muldi3_highpart" 1687 [(set (match_operand:DI 0 "register_operand" "=h") 1688 (truncate:DI 1689 (lshiftrt:TI 1690 (mult:TI 1691 (any_extend:TI (match_operand:DI 1 "register_operand" "d")) 1692 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))) 1693 (const_int 64)))) 1694 (clobber (match_scratch:DI 3 "=l"))] 1695 "TARGET_64BIT && !TARGET_FIX_R4000 1696 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)" 1697 "dmult<u>\t%1,%2" 1698 [(set_attr "type" "imul") 1699 (set_attr "mode" "DI")]) 1700 1701;; The R4650 supports a 32 bit multiply/ 64 bit accumulate 1702;; instruction. The HI/LO registers are used as a 64 bit accumulator. 1703 1704(define_insn "madsi" 1705 [(set (match_operand:SI 0 "register_operand" "+l") 1706 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d") 1707 (match_operand:SI 2 "register_operand" "d")) 1708 (match_dup 0))) 1709 (clobber (match_scratch:SI 3 "=h"))] 1710 "TARGET_MAD" 1711 "mad\t%1,%2" 1712 [(set_attr "type" "imadd") 1713 (set_attr "mode" "SI")]) 1714 1715(define_insn "*<su>mul_acc_di" 1716 [(set (match_operand:DI 0 "register_operand" "=x") 1717 (plus:DI 1718 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 1719 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))) 1720 (match_operand:DI 3 "register_operand" "0")))] 1721 "(TARGET_MAD || ISA_HAS_MACC) 1722 && !TARGET_64BIT" 1723{ 1724 if (TARGET_MAD) 1725 return "mad<u>\t%1,%2"; 1726 else if (TARGET_MIPS5500) 1727 return "madd<u>\t%1,%2"; 1728 else 1729 /* See comment in *macc. */ 1730 return "%[macc<u>\t%@,%1,%2%]"; 1731} 1732 [(set_attr "type" "imadd") 1733 (set_attr "mode" "SI")]) 1734 1735;; Floating point multiply accumulate instructions. 1736 1737(define_insn "*madd<mode>" 1738 [(set (match_operand:ANYF 0 "register_operand" "=f") 1739 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f") 1740 (match_operand:ANYF 2 "register_operand" "f")) 1741 (match_operand:ANYF 3 "register_operand" "f")))] 1742 "ISA_HAS_FP4 && TARGET_FUSED_MADD" 1743 "madd.<fmt>\t%0,%3,%1,%2" 1744 [(set_attr "type" "fmadd") 1745 (set_attr "mode" "<UNITMODE>")]) 1746 1747(define_insn "*msub<mode>" 1748 [(set (match_operand:ANYF 0 "register_operand" "=f") 1749 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f") 1750 (match_operand:ANYF 2 "register_operand" "f")) 1751 (match_operand:ANYF 3 "register_operand" "f")))] 1752 "ISA_HAS_FP4 && TARGET_FUSED_MADD" 1753 "msub.<fmt>\t%0,%3,%1,%2" 1754 [(set_attr "type" "fmadd") 1755 (set_attr "mode" "<UNITMODE>")]) 1756 1757(define_insn "*nmadd<mode>" 1758 [(set (match_operand:ANYF 0 "register_operand" "=f") 1759 (neg:ANYF (plus:ANYF 1760 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f") 1761 (match_operand:ANYF 2 "register_operand" "f")) 1762 (match_operand:ANYF 3 "register_operand" "f"))))] 1763 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD 1764 && HONOR_SIGNED_ZEROS (<MODE>mode)" 1765 "nmadd.<fmt>\t%0,%3,%1,%2" 1766 [(set_attr "type" "fmadd") 1767 (set_attr "mode" "<UNITMODE>")]) 1768 1769(define_insn "*nmadd<mode>_fastmath" 1770 [(set (match_operand:ANYF 0 "register_operand" "=f") 1771 (minus:ANYF 1772 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")) 1773 (match_operand:ANYF 2 "register_operand" "f")) 1774 (match_operand:ANYF 3 "register_operand" "f")))] 1775 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD 1776 && !HONOR_SIGNED_ZEROS (<MODE>mode)" 1777 "nmadd.<fmt>\t%0,%3,%1,%2" 1778 [(set_attr "type" "fmadd") 1779 (set_attr "mode" "<UNITMODE>")]) 1780 1781(define_insn "*nmsub<mode>" 1782 [(set (match_operand:ANYF 0 "register_operand" "=f") 1783 (neg:ANYF (minus:ANYF 1784 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f") 1785 (match_operand:ANYF 3 "register_operand" "f")) 1786 (match_operand:ANYF 1 "register_operand" "f"))))] 1787 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD 1788 && HONOR_SIGNED_ZEROS (<MODE>mode)" 1789 "nmsub.<fmt>\t%0,%1,%2,%3" 1790 [(set_attr "type" "fmadd") 1791 (set_attr "mode" "<UNITMODE>")]) 1792 1793(define_insn "*nmsub<mode>_fastmath" 1794 [(set (match_operand:ANYF 0 "register_operand" "=f") 1795 (minus:ANYF 1796 (match_operand:ANYF 1 "register_operand" "f") 1797 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f") 1798 (match_operand:ANYF 3 "register_operand" "f"))))] 1799 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD 1800 && !HONOR_SIGNED_ZEROS (<MODE>mode)" 1801 "nmsub.<fmt>\t%0,%1,%2,%3" 1802 [(set_attr "type" "fmadd") 1803 (set_attr "mode" "<UNITMODE>")]) 1804 1805;; 1806;; .................... 1807;; 1808;; DIVISION and REMAINDER 1809;; 1810;; .................... 1811;; 1812 1813(define_expand "div<mode>3" 1814 [(set (match_operand:ANYF 0 "register_operand") 1815 (div:ANYF (match_operand:ANYF 1 "reg_or_1_operand") 1816 (match_operand:ANYF 2 "register_operand")))] 1817 "<divide_condition>" 1818{ 1819 if (const_1_operand (operands[1], <MODE>mode)) 1820 if (!(ISA_HAS_FP4 && flag_unsafe_math_optimizations)) 1821 operands[1] = force_reg (<MODE>mode, operands[1]); 1822}) 1823 1824;; These patterns work around the early SB-1 rev2 core "F1" erratum: 1825;; 1826;; If an mfc1 or dmfc1 happens to access the floating point register 1827;; file at the same time a long latency operation (div, sqrt, recip, 1828;; sqrt) iterates an intermediate result back through the floating 1829;; point register file bypass, then instead returning the correct 1830;; register value the mfc1 or dmfc1 operation returns the intermediate 1831;; result of the long latency operation. 1832;; 1833;; The workaround is to insert an unconditional 'mov' from/to the 1834;; long latency op destination register. 1835 1836(define_insn "*div<mode>3" 1837 [(set (match_operand:ANYF 0 "register_operand" "=f") 1838 (div:ANYF (match_operand:ANYF 1 "register_operand" "f") 1839 (match_operand:ANYF 2 "register_operand" "f")))] 1840 "<divide_condition>" 1841{ 1842 if (TARGET_FIX_SB1) 1843 return "div.<fmt>\t%0,%1,%2\;mov.<fmt>\t%0,%0"; 1844 else 1845 return "div.<fmt>\t%0,%1,%2"; 1846} 1847 [(set_attr "type" "fdiv") 1848 (set_attr "mode" "<UNITMODE>") 1849 (set (attr "length") 1850 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0)) 1851 (const_int 8) 1852 (const_int 4)))]) 1853 1854(define_insn "*recip<mode>3" 1855 [(set (match_operand:ANYF 0 "register_operand" "=f") 1856 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "") 1857 (match_operand:ANYF 2 "register_operand" "f")))] 1858 "<recip_condition> && flag_unsafe_math_optimizations" 1859{ 1860 if (TARGET_FIX_SB1) 1861 return "recip.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0"; 1862 else 1863 return "recip.<fmt>\t%0,%2"; 1864} 1865 [(set_attr "type" "frdiv") 1866 (set_attr "mode" "<UNITMODE>") 1867 (set (attr "length") 1868 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0)) 1869 (const_int 8) 1870 (const_int 4)))]) 1871 1872;; VR4120 errata MD(A1): signed division instructions do not work correctly 1873;; with negative operands. We use special libgcc functions instead. 1874(define_insn "divmod<mode>4" 1875 [(set (match_operand:GPR 0 "register_operand" "=l") 1876 (div:GPR (match_operand:GPR 1 "register_operand" "d") 1877 (match_operand:GPR 2 "register_operand" "d"))) 1878 (set (match_operand:GPR 3 "register_operand" "=h") 1879 (mod:GPR (match_dup 1) 1880 (match_dup 2)))] 1881 "!TARGET_FIX_VR4120" 1882 { return mips_output_division ("<d>div\t$0,%1,%2", operands); } 1883 [(set_attr "type" "idiv") 1884 (set_attr "mode" "<MODE>")]) 1885 1886(define_insn "udivmod<mode>4" 1887 [(set (match_operand:GPR 0 "register_operand" "=l") 1888 (udiv:GPR (match_operand:GPR 1 "register_operand" "d") 1889 (match_operand:GPR 2 "register_operand" "d"))) 1890 (set (match_operand:GPR 3 "register_operand" "=h") 1891 (umod:GPR (match_dup 1) 1892 (match_dup 2)))] 1893 "" 1894 { return mips_output_division ("<d>divu\t$0,%1,%2", operands); } 1895 [(set_attr "type" "idiv") 1896 (set_attr "mode" "<MODE>")]) 1897 1898;; 1899;; .................... 1900;; 1901;; SQUARE ROOT 1902;; 1903;; .................... 1904 1905;; These patterns work around the early SB-1 rev2 core "F1" erratum (see 1906;; "*div[sd]f3" comment for details). 1907 1908(define_insn "sqrt<mode>2" 1909 [(set (match_operand:ANYF 0 "register_operand" "=f") 1910 (sqrt:ANYF (match_operand:ANYF 1 "register_operand" "f")))] 1911 "<sqrt_condition>" 1912{ 1913 if (TARGET_FIX_SB1) 1914 return "sqrt.<fmt>\t%0,%1\;mov.<fmt>\t%0,%0"; 1915 else 1916 return "sqrt.<fmt>\t%0,%1"; 1917} 1918 [(set_attr "type" "fsqrt") 1919 (set_attr "mode" "<UNITMODE>") 1920 (set (attr "length") 1921 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0)) 1922 (const_int 8) 1923 (const_int 4)))]) 1924 1925(define_insn "*rsqrt<mode>a" 1926 [(set (match_operand:ANYF 0 "register_operand" "=f") 1927 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "") 1928 (sqrt:ANYF (match_operand:ANYF 2 "register_operand" "f"))))] 1929 "<recip_condition> && flag_unsafe_math_optimizations" 1930{ 1931 if (TARGET_FIX_SB1) 1932 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0"; 1933 else 1934 return "rsqrt.<fmt>\t%0,%2"; 1935} 1936 [(set_attr "type" "frsqrt") 1937 (set_attr "mode" "<UNITMODE>") 1938 (set (attr "length") 1939 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0)) 1940 (const_int 8) 1941 (const_int 4)))]) 1942 1943(define_insn "*rsqrt<mode>b" 1944 [(set (match_operand:ANYF 0 "register_operand" "=f") 1945 (sqrt:ANYF (div:ANYF (match_operand:ANYF 1 "const_1_operand" "") 1946 (match_operand:ANYF 2 "register_operand" "f"))))] 1947 "<recip_condition> && flag_unsafe_math_optimizations" 1948{ 1949 if (TARGET_FIX_SB1) 1950 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0"; 1951 else 1952 return "rsqrt.<fmt>\t%0,%2"; 1953} 1954 [(set_attr "type" "frsqrt") 1955 (set_attr "mode" "<UNITMODE>") 1956 (set (attr "length") 1957 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0)) 1958 (const_int 8) 1959 (const_int 4)))]) 1960 1961;; 1962;; .................... 1963;; 1964;; ABSOLUTE VALUE 1965;; 1966;; .................... 1967 1968;; Do not use the integer abs macro instruction, since that signals an 1969;; exception on -2147483648 (sigh). 1970 1971(define_insn "abs<mode>2" 1972 [(set (match_operand:ANYF 0 "register_operand" "=f") 1973 (abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))] 1974 "" 1975 "abs.<fmt>\t%0,%1" 1976 [(set_attr "type" "fabs") 1977 (set_attr "mode" "<UNITMODE>")]) 1978 1979;; 1980;; ................... 1981;; 1982;; Count leading zeroes. 1983;; 1984;; ................... 1985;; 1986 1987(define_insn "clz<mode>2" 1988 [(set (match_operand:GPR 0 "register_operand" "=d") 1989 (clz:GPR (match_operand:GPR 1 "register_operand" "d")))] 1990 "ISA_HAS_CLZ_CLO" 1991 "<d>clz\t%0,%1" 1992 [(set_attr "type" "clz") 1993 (set_attr "mode" "<MODE>")]) 1994 1995;; 1996;; .................... 1997;; 1998;; NEGATION and ONE'S COMPLEMENT 1999;; 2000;; .................... 2001 2002(define_insn "negsi2" 2003 [(set (match_operand:SI 0 "register_operand" "=d") 2004 (neg:SI (match_operand:SI 1 "register_operand" "d")))] 2005 "" 2006{ 2007 if (TARGET_MIPS16) 2008 return "neg\t%0,%1"; 2009 else 2010 return "subu\t%0,%.,%1"; 2011} 2012 [(set_attr "type" "arith") 2013 (set_attr "mode" "SI")]) 2014 2015(define_insn "negdi2" 2016 [(set (match_operand:DI 0 "register_operand" "=d") 2017 (neg:DI (match_operand:DI 1 "register_operand" "d")))] 2018 "TARGET_64BIT && !TARGET_MIPS16" 2019 "dsubu\t%0,%.,%1" 2020 [(set_attr "type" "arith") 2021 (set_attr "mode" "DI")]) 2022 2023(define_insn "neg<mode>2" 2024 [(set (match_operand:ANYF 0 "register_operand" "=f") 2025 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))] 2026 "" 2027 "neg.<fmt>\t%0,%1" 2028 [(set_attr "type" "fneg") 2029 (set_attr "mode" "<UNITMODE>")]) 2030 2031(define_insn "one_cmpl<mode>2" 2032 [(set (match_operand:GPR 0 "register_operand" "=d") 2033 (not:GPR (match_operand:GPR 1 "register_operand" "d")))] 2034 "" 2035{ 2036 if (TARGET_MIPS16) 2037 return "not\t%0,%1"; 2038 else 2039 return "nor\t%0,%.,%1"; 2040} 2041 [(set_attr "type" "arith") 2042 (set_attr "mode" "<MODE>")]) 2043 2044;; 2045;; .................... 2046;; 2047;; LOGICAL 2048;; 2049;; .................... 2050;; 2051 2052;; Many of these instructions use trivial define_expands, because we 2053;; want to use a different set of constraints when TARGET_MIPS16. 2054 2055(define_expand "and<mode>3" 2056 [(set (match_operand:GPR 0 "register_operand") 2057 (and:GPR (match_operand:GPR 1 "register_operand") 2058 (match_operand:GPR 2 "uns_arith_operand")))] 2059 "" 2060{ 2061 if (TARGET_MIPS16) 2062 operands[2] = force_reg (<MODE>mode, operands[2]); 2063}) 2064 2065(define_insn "*and<mode>3" 2066 [(set (match_operand:GPR 0 "register_operand" "=d,d") 2067 (and:GPR (match_operand:GPR 1 "register_operand" "%d,d") 2068 (match_operand:GPR 2 "uns_arith_operand" "d,K")))] 2069 "!TARGET_MIPS16" 2070 "@ 2071 and\t%0,%1,%2 2072 andi\t%0,%1,%x2" 2073 [(set_attr "type" "arith") 2074 (set_attr "mode" "<MODE>")]) 2075 2076(define_insn "*and<mode>3_mips16" 2077 [(set (match_operand:GPR 0 "register_operand" "=d") 2078 (and:GPR (match_operand:GPR 1 "register_operand" "%0") 2079 (match_operand:GPR 2 "register_operand" "d")))] 2080 "TARGET_MIPS16" 2081 "and\t%0,%2" 2082 [(set_attr "type" "arith") 2083 (set_attr "mode" "<MODE>")]) 2084 2085(define_expand "ior<mode>3" 2086 [(set (match_operand:GPR 0 "register_operand") 2087 (ior:GPR (match_operand:GPR 1 "register_operand") 2088 (match_operand:GPR 2 "uns_arith_operand")))] 2089 "" 2090{ 2091 if (TARGET_MIPS16) 2092 operands[2] = force_reg (<MODE>mode, operands[2]); 2093}) 2094 2095(define_insn "*ior<mode>3" 2096 [(set (match_operand:GPR 0 "register_operand" "=d,d") 2097 (ior:GPR (match_operand:GPR 1 "register_operand" "%d,d") 2098 (match_operand:GPR 2 "uns_arith_operand" "d,K")))] 2099 "!TARGET_MIPS16" 2100 "@ 2101 or\t%0,%1,%2 2102 ori\t%0,%1,%x2" 2103 [(set_attr "type" "arith") 2104 (set_attr "mode" "<MODE>")]) 2105 2106(define_insn "*ior<mode>3_mips16" 2107 [(set (match_operand:GPR 0 "register_operand" "=d") 2108 (ior:GPR (match_operand:GPR 1 "register_operand" "%0") 2109 (match_operand:GPR 2 "register_operand" "d")))] 2110 "TARGET_MIPS16" 2111 "or\t%0,%2" 2112 [(set_attr "type" "arith") 2113 (set_attr "mode" "<MODE>")]) 2114 2115(define_expand "xor<mode>3" 2116 [(set (match_operand:GPR 0 "register_operand") 2117 (xor:GPR (match_operand:GPR 1 "register_operand") 2118 (match_operand:GPR 2 "uns_arith_operand")))] 2119 "" 2120 "") 2121 2122(define_insn "" 2123 [(set (match_operand:GPR 0 "register_operand" "=d,d") 2124 (xor:GPR (match_operand:GPR 1 "register_operand" "%d,d") 2125 (match_operand:GPR 2 "uns_arith_operand" "d,K")))] 2126 "!TARGET_MIPS16" 2127 "@ 2128 xor\t%0,%1,%2 2129 xori\t%0,%1,%x2" 2130 [(set_attr "type" "arith") 2131 (set_attr "mode" "<MODE>")]) 2132 2133(define_insn "" 2134 [(set (match_operand:GPR 0 "register_operand" "=d,t,t") 2135 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d") 2136 (match_operand:GPR 2 "uns_arith_operand" "d,K,d")))] 2137 "TARGET_MIPS16" 2138 "@ 2139 xor\t%0,%2 2140 cmpi\t%1,%2 2141 cmp\t%1,%2" 2142 [(set_attr "type" "arith") 2143 (set_attr "mode" "<MODE>") 2144 (set_attr_alternative "length" 2145 [(const_int 4) 2146 (if_then_else (match_operand:VOID 2 "m16_uimm8_1") 2147 (const_int 4) 2148 (const_int 8)) 2149 (const_int 4)])]) 2150 2151(define_insn "*nor<mode>3" 2152 [(set (match_operand:GPR 0 "register_operand" "=d") 2153 (and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d")) 2154 (not:GPR (match_operand:GPR 2 "register_operand" "d"))))] 2155 "!TARGET_MIPS16" 2156 "nor\t%0,%1,%2" 2157 [(set_attr "type" "arith") 2158 (set_attr "mode" "<MODE>")]) 2159 2160;; 2161;; .................... 2162;; 2163;; TRUNCATION 2164;; 2165;; .................... 2166 2167 2168 2169(define_insn "truncdfsf2" 2170 [(set (match_operand:SF 0 "register_operand" "=f") 2171 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))] 2172 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" 2173 "cvt.s.d\t%0,%1" 2174 [(set_attr "type" "fcvt") 2175 (set_attr "cnv_mode" "D2S") 2176 (set_attr "mode" "SF")]) 2177 2178;; Integer truncation patterns. Truncating SImode values to smaller 2179;; modes is a no-op, as it is for most other GCC ports. Truncating 2180;; DImode values to SImode is not a no-op for TARGET_64BIT since we 2181;; need to make sure that the lower 32 bits are properly sign-extended 2182;; (see TRULY_NOOP_TRUNCATION). Truncating DImode values into modes 2183;; smaller than SImode is equivalent to two separate truncations: 2184;; 2185;; A B 2186;; DI ---> HI == DI ---> SI ---> HI 2187;; DI ---> QI == DI ---> SI ---> QI 2188;; 2189;; Step A needs a real instruction but step B does not. 2190 2191(define_insn "truncdisi2" 2192 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,m") 2193 (truncate:SI (match_operand:DI 1 "register_operand" "d,d")))] 2194 "TARGET_64BIT" 2195 "@ 2196 sll\t%0,%1,0 2197 sw\t%1,%0" 2198 [(set_attr "type" "shift,store") 2199 (set_attr "mode" "SI") 2200 (set_attr "extended_mips16" "yes,*")]) 2201 2202(define_insn "truncdihi2" 2203 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,m") 2204 (truncate:HI (match_operand:DI 1 "register_operand" "d,d")))] 2205 "TARGET_64BIT" 2206 "@ 2207 sll\t%0,%1,0 2208 sh\t%1,%0" 2209 [(set_attr "type" "shift,store") 2210 (set_attr "mode" "SI") 2211 (set_attr "extended_mips16" "yes,*")]) 2212 2213(define_insn "truncdiqi2" 2214 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,m") 2215 (truncate:QI (match_operand:DI 1 "register_operand" "d,d")))] 2216 "TARGET_64BIT" 2217 "@ 2218 sll\t%0,%1,0 2219 sb\t%1,%0" 2220 [(set_attr "type" "shift,store") 2221 (set_attr "mode" "SI") 2222 (set_attr "extended_mips16" "yes,*")]) 2223 2224;; Combiner patterns to optimize shift/truncate combinations. 2225 2226(define_insn "" 2227 [(set (match_operand:SI 0 "register_operand" "=d") 2228 (truncate:SI 2229 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") 2230 (match_operand:DI 2 "const_arith_operand" ""))))] 2231 "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) >= 32" 2232 "dsra\t%0,%1,%2" 2233 [(set_attr "type" "shift") 2234 (set_attr "mode" "SI")]) 2235 2236(define_insn "" 2237 [(set (match_operand:SI 0 "register_operand" "=d") 2238 (truncate:SI (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") 2239 (const_int 32))))] 2240 "TARGET_64BIT && !TARGET_MIPS16" 2241 "dsra\t%0,%1,32" 2242 [(set_attr "type" "shift") 2243 (set_attr "mode" "SI")]) 2244 2245 2246;; Combiner patterns for truncate/sign_extend combinations. They use 2247;; the shift/truncate patterns above. 2248 2249(define_insn_and_split "" 2250 [(set (match_operand:SI 0 "register_operand" "=d") 2251 (sign_extend:SI 2252 (truncate:HI (match_operand:DI 1 "register_operand" "d"))))] 2253 "TARGET_64BIT && !TARGET_MIPS16" 2254 "#" 2255 "&& reload_completed" 2256 [(set (match_dup 2) 2257 (ashift:DI (match_dup 1) 2258 (const_int 48))) 2259 (set (match_dup 0) 2260 (truncate:SI (ashiftrt:DI (match_dup 2) 2261 (const_int 48))))] 2262 { operands[2] = gen_lowpart (DImode, operands[0]); }) 2263 2264(define_insn_and_split "" 2265 [(set (match_operand:SI 0 "register_operand" "=d") 2266 (sign_extend:SI 2267 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))] 2268 "TARGET_64BIT && !TARGET_MIPS16" 2269 "#" 2270 "&& reload_completed" 2271 [(set (match_dup 2) 2272 (ashift:DI (match_dup 1) 2273 (const_int 56))) 2274 (set (match_dup 0) 2275 (truncate:SI (ashiftrt:DI (match_dup 2) 2276 (const_int 56))))] 2277 { operands[2] = gen_lowpart (DImode, operands[0]); }) 2278 2279 2280;; Combiner patterns to optimize truncate/zero_extend combinations. 2281 2282(define_insn "" 2283 [(set (match_operand:SI 0 "register_operand" "=d") 2284 (zero_extend:SI (truncate:HI 2285 (match_operand:DI 1 "register_operand" "d"))))] 2286 "TARGET_64BIT && !TARGET_MIPS16" 2287 "andi\t%0,%1,0xffff" 2288 [(set_attr "type" "arith") 2289 (set_attr "mode" "SI")]) 2290 2291(define_insn "" 2292 [(set (match_operand:SI 0 "register_operand" "=d") 2293 (zero_extend:SI (truncate:QI 2294 (match_operand:DI 1 "register_operand" "d"))))] 2295 "TARGET_64BIT && !TARGET_MIPS16" 2296 "andi\t%0,%1,0xff" 2297 [(set_attr "type" "arith") 2298 (set_attr "mode" "SI")]) 2299 2300(define_insn "" 2301 [(set (match_operand:HI 0 "register_operand" "=d") 2302 (zero_extend:HI (truncate:QI 2303 (match_operand:DI 1 "register_operand" "d"))))] 2304 "TARGET_64BIT && !TARGET_MIPS16" 2305 "andi\t%0,%1,0xff" 2306 [(set_attr "type" "arith") 2307 (set_attr "mode" "HI")]) 2308 2309;; 2310;; .................... 2311;; 2312;; ZERO EXTENSION 2313;; 2314;; .................... 2315 2316;; Extension insns. 2317 2318(define_insn_and_split "zero_extendsidi2" 2319 [(set (match_operand:DI 0 "register_operand" "=d,d") 2320 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))] 2321 "TARGET_64BIT" 2322 "@ 2323 # 2324 lwu\t%0,%1" 2325 "&& reload_completed && REG_P (operands[1])" 2326 [(set (match_dup 0) 2327 (ashift:DI (match_dup 1) (const_int 32))) 2328 (set (match_dup 0) 2329 (lshiftrt:DI (match_dup 0) (const_int 32)))] 2330 { operands[1] = gen_lowpart (DImode, operands[1]); } 2331 [(set_attr "type" "multi,load") 2332 (set_attr "mode" "DI") 2333 (set_attr "length" "8,*")]) 2334 2335(define_expand "zero_extend<SHORT:mode><GPR:mode>2" 2336 [(set (match_operand:GPR 0 "register_operand") 2337 (zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))] 2338 "" 2339{ 2340 if (TARGET_MIPS16 && !GENERATE_MIPS16E 2341 && !memory_operand (operands[1], <SHORT:MODE>mode)) 2342 { 2343 emit_insn (gen_and<GPR:mode>3 (operands[0], 2344 gen_lowpart (<GPR:MODE>mode, operands[1]), 2345 force_reg (<GPR:MODE>mode, 2346 GEN_INT (<SHORT:mask>)))); 2347 DONE; 2348 } 2349}) 2350 2351(define_insn "*zero_extend<SHORT:mode><GPR:mode>2" 2352 [(set (match_operand:GPR 0 "register_operand" "=d,d") 2353 (zero_extend:GPR 2354 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))] 2355 "!TARGET_MIPS16" 2356 "@ 2357 andi\t%0,%1,<SHORT:mask> 2358 l<SHORT:size>u\t%0,%1" 2359 [(set_attr "type" "arith,load") 2360 (set_attr "mode" "<GPR:MODE>")]) 2361 2362(define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16e" 2363 [(set (match_operand:GPR 0 "register_operand" "=d") 2364 (zero_extend:GPR (match_operand:SHORT 1 "register_operand" "0")))] 2365 "GENERATE_MIPS16E" 2366 "ze<SHORT:size>\t%0" 2367 [(set_attr "type" "arith") 2368 (set_attr "mode" "<GPR:MODE>")]) 2369 2370(define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16" 2371 [(set (match_operand:GPR 0 "register_operand" "=d") 2372 (zero_extend:GPR (match_operand:SHORT 1 "memory_operand" "m")))] 2373 "TARGET_MIPS16" 2374 "l<SHORT:size>u\t%0,%1" 2375 [(set_attr "type" "load") 2376 (set_attr "mode" "<GPR:MODE>")]) 2377 2378(define_expand "zero_extendqihi2" 2379 [(set (match_operand:HI 0 "register_operand") 2380 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand")))] 2381 "" 2382{ 2383 if (TARGET_MIPS16 && !memory_operand (operands[1], QImode)) 2384 { 2385 emit_insn (gen_zero_extendqisi2 (gen_lowpart (SImode, operands[0]), 2386 operands[1])); 2387 DONE; 2388 } 2389}) 2390 2391(define_insn "*zero_extendqihi2" 2392 [(set (match_operand:HI 0 "register_operand" "=d,d") 2393 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))] 2394 "!TARGET_MIPS16" 2395 "@ 2396 andi\t%0,%1,0x00ff 2397 lbu\t%0,%1" 2398 [(set_attr "type" "arith,load") 2399 (set_attr "mode" "HI")]) 2400 2401(define_insn "*zero_extendqihi2_mips16" 2402 [(set (match_operand:HI 0 "register_operand" "=d") 2403 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] 2404 "TARGET_MIPS16" 2405 "lbu\t%0,%1" 2406 [(set_attr "type" "load") 2407 (set_attr "mode" "HI")]) 2408 2409;; 2410;; .................... 2411;; 2412;; SIGN EXTENSION 2413;; 2414;; .................... 2415 2416;; Extension insns. 2417;; Those for integer source operand are ordered widest source type first. 2418 2419;; When TARGET_64BIT, all SImode integer registers should already be in 2420;; sign-extended form (see TRULY_NOOP_TRUNCATION and truncdisi2). We can 2421;; therefore get rid of register->register instructions if we constrain 2422;; the source to be in the same register as the destination. 2423;; 2424;; The register alternative has type "arith" so that the pre-reload 2425;; scheduler will treat it as a move. This reflects what happens if 2426;; the register alternative needs a reload. 2427(define_insn_and_split "extendsidi2" 2428 [(set (match_operand:DI 0 "register_operand" "=d,d") 2429 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,m")))] 2430 "TARGET_64BIT" 2431 "@ 2432 # 2433 lw\t%0,%1" 2434 "&& reload_completed && register_operand (operands[1], VOIDmode)" 2435 [(const_int 0)] 2436{ 2437 emit_note (NOTE_INSN_DELETED); 2438 DONE; 2439} 2440 [(set_attr "type" "arith,load") 2441 (set_attr "mode" "DI")]) 2442 2443(define_expand "extend<SHORT:mode><GPR:mode>2" 2444 [(set (match_operand:GPR 0 "register_operand") 2445 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))] 2446 "") 2447 2448(define_insn "*extend<SHORT:mode><GPR:mode>2_mips16e" 2449 [(set (match_operand:GPR 0 "register_operand" "=d,d") 2450 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand" "0,m")))] 2451 "GENERATE_MIPS16E" 2452 "@ 2453 se<SHORT:size>\t%0 2454 l<SHORT:size>\t%0,%1" 2455 [(set_attr "type" "arith,load") 2456 (set_attr "mode" "<GPR:MODE>")]) 2457 2458(define_insn_and_split "*extend<SHORT:mode><GPR:mode>2" 2459 [(set (match_operand:GPR 0 "register_operand" "=d,d") 2460 (sign_extend:GPR 2461 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))] 2462 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E" 2463 "@ 2464 # 2465 l<SHORT:size>\t%0,%1" 2466 "&& reload_completed && REG_P (operands[1])" 2467 [(set (match_dup 0) (ashift:GPR (match_dup 1) (match_dup 2))) 2468 (set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))] 2469{ 2470 operands[1] = gen_lowpart (<GPR:MODE>mode, operands[1]); 2471 operands[2] = GEN_INT (GET_MODE_BITSIZE (<GPR:MODE>mode) 2472 - GET_MODE_BITSIZE (<SHORT:MODE>mode)); 2473} 2474 [(set_attr "type" "arith,load") 2475 (set_attr "mode" "<GPR:MODE>") 2476 (set_attr "length" "8,*")]) 2477 2478(define_insn "*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>" 2479 [(set (match_operand:GPR 0 "register_operand" "=d,d") 2480 (sign_extend:GPR 2481 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))] 2482 "ISA_HAS_SEB_SEH" 2483 "@ 2484 se<SHORT:size>\t%0,%1 2485 l<SHORT:size>\t%0,%1" 2486 [(set_attr "type" "arith,load") 2487 (set_attr "mode" "<GPR:MODE>")]) 2488 2489;; This pattern generates the same code as extendqisi2; split it into 2490;; that form after reload. 2491(define_insn_and_split "extendqihi2" 2492 [(set (match_operand:HI 0 "register_operand" "=d,d") 2493 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))] 2494 "" 2495 "#" 2496 "reload_completed" 2497 [(set (match_dup 0) (sign_extend:SI (match_dup 1)))] 2498 { operands[0] = gen_lowpart (SImode, operands[0]); } 2499 [(set_attr "type" "arith,load") 2500 (set_attr "mode" "SI") 2501 (set_attr "length" "8,*")]) 2502 2503(define_insn "extendsfdf2" 2504 [(set (match_operand:DF 0 "register_operand" "=f") 2505 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))] 2506 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" 2507 "cvt.d.s\t%0,%1" 2508 [(set_attr "type" "fcvt") 2509 (set_attr "cnv_mode" "S2D") 2510 (set_attr "mode" "DF")]) 2511 2512;; 2513;; .................... 2514;; 2515;; CONVERSIONS 2516;; 2517;; .................... 2518 2519(define_expand "fix_truncdfsi2" 2520 [(set (match_operand:SI 0 "register_operand") 2521 (fix:SI (match_operand:DF 1 "register_operand")))] 2522 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" 2523{ 2524 if (!ISA_HAS_TRUNC_W) 2525 { 2526 emit_insn (gen_fix_truncdfsi2_macro (operands[0], operands[1])); 2527 DONE; 2528 } 2529}) 2530 2531(define_insn "fix_truncdfsi2_insn" 2532 [(set (match_operand:SI 0 "register_operand" "=f") 2533 (fix:SI (match_operand:DF 1 "register_operand" "f")))] 2534 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && ISA_HAS_TRUNC_W" 2535 "trunc.w.d %0,%1" 2536 [(set_attr "type" "fcvt") 2537 (set_attr "mode" "DF") 2538 (set_attr "cnv_mode" "D2I") 2539 (set_attr "length" "4")]) 2540 2541(define_insn "fix_truncdfsi2_macro" 2542 [(set (match_operand:SI 0 "register_operand" "=f") 2543 (fix:SI (match_operand:DF 1 "register_operand" "f"))) 2544 (clobber (match_scratch:DF 2 "=d"))] 2545 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !ISA_HAS_TRUNC_W" 2546{ 2547 if (set_nomacro) 2548 return ".set\tmacro\;trunc.w.d %0,%1,%2\;.set\tnomacro"; 2549 else 2550 return "trunc.w.d %0,%1,%2"; 2551} 2552 [(set_attr "type" "fcvt") 2553 (set_attr "mode" "DF") 2554 (set_attr "cnv_mode" "D2I") 2555 (set_attr "length" "36")]) 2556 2557(define_expand "fix_truncsfsi2" 2558 [(set (match_operand:SI 0 "register_operand") 2559 (fix:SI (match_operand:SF 1 "register_operand")))] 2560 "TARGET_HARD_FLOAT" 2561{ 2562 if (!ISA_HAS_TRUNC_W) 2563 { 2564 emit_insn (gen_fix_truncsfsi2_macro (operands[0], operands[1])); 2565 DONE; 2566 } 2567}) 2568 2569(define_insn "fix_truncsfsi2_insn" 2570 [(set (match_operand:SI 0 "register_operand" "=f") 2571 (fix:SI (match_operand:SF 1 "register_operand" "f")))] 2572 "TARGET_HARD_FLOAT && ISA_HAS_TRUNC_W" 2573 "trunc.w.s %0,%1" 2574 [(set_attr "type" "fcvt") 2575 (set_attr "mode" "SF") 2576 (set_attr "cnv_mode" "S2I") 2577 (set_attr "length" "4")]) 2578 2579(define_insn "fix_truncsfsi2_macro" 2580 [(set (match_operand:SI 0 "register_operand" "=f") 2581 (fix:SI (match_operand:SF 1 "register_operand" "f"))) 2582 (clobber (match_scratch:SF 2 "=d"))] 2583 "TARGET_HARD_FLOAT && !ISA_HAS_TRUNC_W" 2584{ 2585 if (set_nomacro) 2586 return ".set\tmacro\;trunc.w.s %0,%1,%2\;.set\tnomacro"; 2587 else 2588 return "trunc.w.s %0,%1,%2"; 2589} 2590 [(set_attr "type" "fcvt") 2591 (set_attr "mode" "SF") 2592 (set_attr "cnv_mode" "S2I") 2593 (set_attr "length" "36")]) 2594 2595 2596(define_insn "fix_truncdfdi2" 2597 [(set (match_operand:DI 0 "register_operand" "=f") 2598 (fix:DI (match_operand:DF 1 "register_operand" "f")))] 2599 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT" 2600 "trunc.l.d %0,%1" 2601 [(set_attr "type" "fcvt") 2602 (set_attr "mode" "DF") 2603 (set_attr "cnv_mode" "D2I") 2604 (set_attr "length" "4")]) 2605 2606 2607(define_insn "fix_truncsfdi2" 2608 [(set (match_operand:DI 0 "register_operand" "=f") 2609 (fix:DI (match_operand:SF 1 "register_operand" "f")))] 2610 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT" 2611 "trunc.l.s %0,%1" 2612 [(set_attr "type" "fcvt") 2613 (set_attr "mode" "SF") 2614 (set_attr "cnv_mode" "S2I") 2615 (set_attr "length" "4")]) 2616 2617 2618(define_insn "floatsidf2" 2619 [(set (match_operand:DF 0 "register_operand" "=f") 2620 (float:DF (match_operand:SI 1 "register_operand" "f")))] 2621 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" 2622 "cvt.d.w\t%0,%1" 2623 [(set_attr "type" "fcvt") 2624 (set_attr "mode" "DF") 2625 (set_attr "cnv_mode" "I2D") 2626 (set_attr "length" "4")]) 2627 2628 2629(define_insn "floatdidf2" 2630 [(set (match_operand:DF 0 "register_operand" "=f") 2631 (float:DF (match_operand:DI 1 "register_operand" "f")))] 2632 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT" 2633 "cvt.d.l\t%0,%1" 2634 [(set_attr "type" "fcvt") 2635 (set_attr "mode" "DF") 2636 (set_attr "cnv_mode" "I2D") 2637 (set_attr "length" "4")]) 2638 2639 2640(define_insn "floatsisf2" 2641 [(set (match_operand:SF 0 "register_operand" "=f") 2642 (float:SF (match_operand:SI 1 "register_operand" "f")))] 2643 "TARGET_HARD_FLOAT" 2644 "cvt.s.w\t%0,%1" 2645 [(set_attr "type" "fcvt") 2646 (set_attr "mode" "SF") 2647 (set_attr "cnv_mode" "I2S") 2648 (set_attr "length" "4")]) 2649 2650 2651(define_insn "floatdisf2" 2652 [(set (match_operand:SF 0 "register_operand" "=f") 2653 (float:SF (match_operand:DI 1 "register_operand" "f")))] 2654 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT" 2655 "cvt.s.l\t%0,%1" 2656 [(set_attr "type" "fcvt") 2657 (set_attr "mode" "SF") 2658 (set_attr "cnv_mode" "I2S") 2659 (set_attr "length" "4")]) 2660 2661 2662(define_expand "fixuns_truncdfsi2" 2663 [(set (match_operand:SI 0 "register_operand") 2664 (unsigned_fix:SI (match_operand:DF 1 "register_operand")))] 2665 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" 2666{ 2667 rtx reg1 = gen_reg_rtx (DFmode); 2668 rtx reg2 = gen_reg_rtx (DFmode); 2669 rtx reg3 = gen_reg_rtx (SImode); 2670 rtx label1 = gen_label_rtx (); 2671 rtx label2 = gen_label_rtx (); 2672 REAL_VALUE_TYPE offset; 2673 2674 real_2expN (&offset, 31); 2675 2676 if (reg1) /* Turn off complaints about unreached code. */ 2677 { 2678 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode)); 2679 do_pending_stack_adjust (); 2680 2681 emit_insn (gen_cmpdf (operands[1], reg1)); 2682 emit_jump_insn (gen_bge (label1)); 2683 2684 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1])); 2685 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, 2686 gen_rtx_LABEL_REF (VOIDmode, label2))); 2687 emit_barrier (); 2688 2689 emit_label (label1); 2690 emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1)); 2691 emit_move_insn (reg3, GEN_INT (trunc_int_for_mode 2692 (BITMASK_HIGH, SImode))); 2693 2694 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2)); 2695 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3)); 2696 2697 emit_label (label2); 2698 2699 /* Allow REG_NOTES to be set on last insn (labels don't have enough 2700 fields, and can't be used for REG_NOTES anyway). */ 2701 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx)); 2702 DONE; 2703 } 2704}) 2705 2706 2707(define_expand "fixuns_truncdfdi2" 2708 [(set (match_operand:DI 0 "register_operand") 2709 (unsigned_fix:DI (match_operand:DF 1 "register_operand")))] 2710 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT" 2711{ 2712 rtx reg1 = gen_reg_rtx (DFmode); 2713 rtx reg2 = gen_reg_rtx (DFmode); 2714 rtx reg3 = gen_reg_rtx (DImode); 2715 rtx label1 = gen_label_rtx (); 2716 rtx label2 = gen_label_rtx (); 2717 REAL_VALUE_TYPE offset; 2718 2719 real_2expN (&offset, 63); 2720 2721 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode)); 2722 do_pending_stack_adjust (); 2723 2724 emit_insn (gen_cmpdf (operands[1], reg1)); 2725 emit_jump_insn (gen_bge (label1)); 2726 2727 emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1])); 2728 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, 2729 gen_rtx_LABEL_REF (VOIDmode, label2))); 2730 emit_barrier (); 2731 2732 emit_label (label1); 2733 emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1)); 2734 emit_move_insn (reg3, GEN_INT (BITMASK_HIGH)); 2735 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32))); 2736 2737 emit_insn (gen_fix_truncdfdi2 (operands[0], reg2)); 2738 emit_insn (gen_iordi3 (operands[0], operands[0], reg3)); 2739 2740 emit_label (label2); 2741 2742 /* Allow REG_NOTES to be set on last insn (labels don't have enough 2743 fields, and can't be used for REG_NOTES anyway). */ 2744 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx)); 2745 DONE; 2746}) 2747 2748 2749(define_expand "fixuns_truncsfsi2" 2750 [(set (match_operand:SI 0 "register_operand") 2751 (unsigned_fix:SI (match_operand:SF 1 "register_operand")))] 2752 "TARGET_HARD_FLOAT" 2753{ 2754 rtx reg1 = gen_reg_rtx (SFmode); 2755 rtx reg2 = gen_reg_rtx (SFmode); 2756 rtx reg3 = gen_reg_rtx (SImode); 2757 rtx label1 = gen_label_rtx (); 2758 rtx label2 = gen_label_rtx (); 2759 REAL_VALUE_TYPE offset; 2760 2761 real_2expN (&offset, 31); 2762 2763 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode)); 2764 do_pending_stack_adjust (); 2765 2766 emit_insn (gen_cmpsf (operands[1], reg1)); 2767 emit_jump_insn (gen_bge (label1)); 2768 2769 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1])); 2770 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, 2771 gen_rtx_LABEL_REF (VOIDmode, label2))); 2772 emit_barrier (); 2773 2774 emit_label (label1); 2775 emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1)); 2776 emit_move_insn (reg3, GEN_INT (trunc_int_for_mode 2777 (BITMASK_HIGH, SImode))); 2778 2779 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2)); 2780 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3)); 2781 2782 emit_label (label2); 2783 2784 /* Allow REG_NOTES to be set on last insn (labels don't have enough 2785 fields, and can't be used for REG_NOTES anyway). */ 2786 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx)); 2787 DONE; 2788}) 2789 2790 2791(define_expand "fixuns_truncsfdi2" 2792 [(set (match_operand:DI 0 "register_operand") 2793 (unsigned_fix:DI (match_operand:SF 1 "register_operand")))] 2794 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT" 2795{ 2796 rtx reg1 = gen_reg_rtx (SFmode); 2797 rtx reg2 = gen_reg_rtx (SFmode); 2798 rtx reg3 = gen_reg_rtx (DImode); 2799 rtx label1 = gen_label_rtx (); 2800 rtx label2 = gen_label_rtx (); 2801 REAL_VALUE_TYPE offset; 2802 2803 real_2expN (&offset, 63); 2804 2805 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode)); 2806 do_pending_stack_adjust (); 2807 2808 emit_insn (gen_cmpsf (operands[1], reg1)); 2809 emit_jump_insn (gen_bge (label1)); 2810 2811 emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1])); 2812 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, 2813 gen_rtx_LABEL_REF (VOIDmode, label2))); 2814 emit_barrier (); 2815 2816 emit_label (label1); 2817 emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1)); 2818 emit_move_insn (reg3, GEN_INT (BITMASK_HIGH)); 2819 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32))); 2820 2821 emit_insn (gen_fix_truncsfdi2 (operands[0], reg2)); 2822 emit_insn (gen_iordi3 (operands[0], operands[0], reg3)); 2823 2824 emit_label (label2); 2825 2826 /* Allow REG_NOTES to be set on last insn (labels don't have enough 2827 fields, and can't be used for REG_NOTES anyway). */ 2828 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx)); 2829 DONE; 2830}) 2831 2832;; 2833;; .................... 2834;; 2835;; DATA MOVEMENT 2836;; 2837;; .................... 2838 2839;; Bit field extract patterns which use lwl/lwr or ldl/ldr. 2840 2841(define_expand "extv" 2842 [(set (match_operand 0 "register_operand") 2843 (sign_extract (match_operand:QI 1 "memory_operand") 2844 (match_operand 2 "immediate_operand") 2845 (match_operand 3 "immediate_operand")))] 2846 "!TARGET_MIPS16" 2847{ 2848 if (mips_expand_unaligned_load (operands[0], operands[1], 2849 INTVAL (operands[2]), 2850 INTVAL (operands[3]))) 2851 DONE; 2852 else 2853 FAIL; 2854}) 2855 2856(define_expand "extzv" 2857 [(set (match_operand 0 "register_operand") 2858 (zero_extract (match_operand 1 "nonimmediate_operand") 2859 (match_operand 2 "immediate_operand") 2860 (match_operand 3 "immediate_operand")))] 2861 "!TARGET_MIPS16" 2862{ 2863 if (mips_expand_unaligned_load (operands[0], operands[1], 2864 INTVAL (operands[2]), 2865 INTVAL (operands[3]))) 2866 DONE; 2867 else if (mips_use_ins_ext_p (operands[1], operands[2], operands[3])) 2868 { 2869 if (GET_MODE (operands[0]) == DImode) 2870 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], 2871 operands[3])); 2872 else 2873 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], 2874 operands[3])); 2875 DONE; 2876 } 2877 else 2878 FAIL; 2879}) 2880 2881(define_insn "extzv<mode>" 2882 [(set (match_operand:GPR 0 "register_operand" "=d") 2883 (zero_extract:GPR (match_operand:GPR 1 "register_operand" "d") 2884 (match_operand:SI 2 "immediate_operand" "I") 2885 (match_operand:SI 3 "immediate_operand" "I")))] 2886 "mips_use_ins_ext_p (operands[1], operands[2], operands[3])" 2887 "<d>ext\t%0,%1,%3,%2" 2888 [(set_attr "type" "arith") 2889 (set_attr "mode" "<MODE>")]) 2890 2891 2892(define_expand "insv" 2893 [(set (zero_extract (match_operand 0 "nonimmediate_operand") 2894 (match_operand 1 "immediate_operand") 2895 (match_operand 2 "immediate_operand")) 2896 (match_operand 3 "reg_or_0_operand"))] 2897 "!TARGET_MIPS16" 2898{ 2899 if (mips_expand_unaligned_store (operands[0], operands[3], 2900 INTVAL (operands[1]), 2901 INTVAL (operands[2]))) 2902 DONE; 2903 else if (mips_use_ins_ext_p (operands[0], operands[1], operands[2])) 2904 { 2905 if (GET_MODE (operands[0]) == DImode) 2906 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], 2907 operands[3])); 2908 else 2909 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], 2910 operands[3])); 2911 DONE; 2912 } 2913 else 2914 FAIL; 2915}) 2916 2917(define_insn "insv<mode>" 2918 [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand" "+d") 2919 (match_operand:SI 1 "immediate_operand" "I") 2920 (match_operand:SI 2 "immediate_operand" "I")) 2921 (match_operand:GPR 3 "reg_or_0_operand" "dJ"))] 2922 "mips_use_ins_ext_p (operands[0], operands[1], operands[2])" 2923 "<d>ins\t%0,%z3,%2,%1" 2924 [(set_attr "type" "arith") 2925 (set_attr "mode" "<MODE>")]) 2926 2927;; Unaligned word moves generated by the bit field patterns. 2928;; 2929;; As far as the rtl is concerned, both the left-part and right-part 2930;; instructions can access the whole field. However, the real operand 2931;; refers to just the first or the last byte (depending on endianness). 2932;; We therefore use two memory operands to each instruction, one to 2933;; describe the rtl effect and one to use in the assembly output. 2934;; 2935;; Operands 0 and 1 are the rtl-level target and source respectively. 2936;; This allows us to use the standard length calculations for the "load" 2937;; and "store" type attributes. 2938 2939(define_insn "mov_<load>l" 2940 [(set (match_operand:GPR 0 "register_operand" "=d") 2941 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m") 2942 (match_operand:QI 2 "memory_operand" "m")] 2943 UNSPEC_LOAD_LEFT))] 2944 "!TARGET_MIPS16" 2945 "<load>l\t%0,%2" 2946 [(set_attr "type" "load") 2947 (set_attr "mode" "<MODE>")]) 2948 2949(define_insn "mov_<load>r" 2950 [(set (match_operand:GPR 0 "register_operand" "=d") 2951 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m") 2952 (match_operand:QI 2 "memory_operand" "m") 2953 (match_operand:GPR 3 "register_operand" "0")] 2954 UNSPEC_LOAD_RIGHT))] 2955 "!TARGET_MIPS16" 2956 "<load>r\t%0,%2" 2957 [(set_attr "type" "load") 2958 (set_attr "mode" "<MODE>")]) 2959 2960(define_insn "mov_<store>l" 2961 [(set (match_operand:BLK 0 "memory_operand" "=m") 2962 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ") 2963 (match_operand:QI 2 "memory_operand" "m")] 2964 UNSPEC_STORE_LEFT))] 2965 "!TARGET_MIPS16" 2966 "<store>l\t%z1,%2" 2967 [(set_attr "type" "store") 2968 (set_attr "mode" "<MODE>")]) 2969 2970(define_insn "mov_<store>r" 2971 [(set (match_operand:BLK 0 "memory_operand" "+m") 2972 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ") 2973 (match_operand:QI 2 "memory_operand" "m") 2974 (match_dup 0)] 2975 UNSPEC_STORE_RIGHT))] 2976 "!TARGET_MIPS16" 2977 "<store>r\t%z1,%2" 2978 [(set_attr "type" "store") 2979 (set_attr "mode" "<MODE>")]) 2980 2981;; An instruction to calculate the high part of a 64-bit SYMBOL_GENERAL. 2982;; The required value is: 2983;; 2984;; (%highest(op1) << 48) + (%higher(op1) << 32) + (%hi(op1) << 16) 2985;; 2986;; which translates to: 2987;; 2988;; lui op0,%highest(op1) 2989;; daddiu op0,op0,%higher(op1) 2990;; dsll op0,op0,16 2991;; daddiu op0,op0,%hi(op1) 2992;; dsll op0,op0,16 2993;; 2994;; The split is deferred until after flow2 to allow the peephole2 below 2995;; to take effect. 2996(define_insn_and_split "*lea_high64" 2997 [(set (match_operand:DI 0 "register_operand" "=d") 2998 (high:DI (match_operand:DI 1 "general_symbolic_operand" "")))] 2999 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS" 3000 "#" 3001 "&& flow2_completed" 3002 [(set (match_dup 0) (high:DI (match_dup 2))) 3003 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 2))) 3004 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16))) 3005 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3))) 3006 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))] 3007{ 3008 operands[2] = mips_unspec_address (operands[1], SYMBOL_64_HIGH); 3009 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_MID); 3010} 3011 [(set_attr "length" "20")]) 3012 3013;; Use a scratch register to reduce the latency of the above pattern 3014;; on superscalar machines. The optimized sequence is: 3015;; 3016;; lui op1,%highest(op2) 3017;; lui op0,%hi(op2) 3018;; daddiu op1,op1,%higher(op2) 3019;; dsll32 op1,op1,0 3020;; daddu op1,op1,op0 3021(define_peephole2 3022 [(set (match_operand:DI 1 "register_operand") 3023 (high:DI (match_operand:DI 2 "general_symbolic_operand"))) 3024 (match_scratch:DI 0 "d")] 3025 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS" 3026 [(set (match_dup 1) (high:DI (match_dup 3))) 3027 (set (match_dup 0) (high:DI (match_dup 4))) 3028 (set (match_dup 1) (lo_sum:DI (match_dup 1) (match_dup 3))) 3029 (set (match_dup 1) (ashift:DI (match_dup 1) (const_int 32))) 3030 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 0)))] 3031{ 3032 operands[3] = mips_unspec_address (operands[2], SYMBOL_64_HIGH); 3033 operands[4] = mips_unspec_address (operands[2], SYMBOL_64_LOW); 3034}) 3035 3036;; On most targets, the expansion of (lo_sum (high X) X) for a 64-bit 3037;; SYMBOL_GENERAL X will take 6 cycles. This next pattern allows combine 3038;; to merge the HIGH and LO_SUM parts of a move if the HIGH part is only 3039;; used once. We can then use the sequence: 3040;; 3041;; lui op0,%highest(op1) 3042;; lui op2,%hi(op1) 3043;; daddiu op0,op0,%higher(op1) 3044;; daddiu op2,op2,%lo(op1) 3045;; dsll32 op0,op0,0 3046;; daddu op0,op0,op2 3047;; 3048;; which takes 4 cycles on most superscalar targets. 3049(define_insn_and_split "*lea64" 3050 [(set (match_operand:DI 0 "register_operand" "=d") 3051 (match_operand:DI 1 "general_symbolic_operand" "")) 3052 (clobber (match_scratch:DI 2 "=&d"))] 3053 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS && cse_not_expected" 3054 "#" 3055 "&& reload_completed" 3056 [(set (match_dup 0) (high:DI (match_dup 3))) 3057 (set (match_dup 2) (high:DI (match_dup 4))) 3058 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3))) 3059 (set (match_dup 2) (lo_sum:DI (match_dup 2) (match_dup 4))) 3060 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32))) 3061 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))] 3062{ 3063 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_HIGH); 3064 operands[4] = mips_unspec_address (operands[1], SYMBOL_64_LOW); 3065} 3066 [(set_attr "length" "24")]) 3067 3068;; Insns to fetch a global symbol from a big GOT. 3069 3070(define_insn_and_split "*xgot_hi<mode>" 3071 [(set (match_operand:P 0 "register_operand" "=d") 3072 (high:P (match_operand:P 1 "global_got_operand" "")))] 3073 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT" 3074 "#" 3075 "&& reload_completed" 3076 [(set (match_dup 0) (high:P (match_dup 2))) 3077 (set (match_dup 0) (plus:P (match_dup 0) (match_dup 3)))] 3078{ 3079 operands[2] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_GLOBAL); 3080 operands[3] = pic_offset_table_rtx; 3081} 3082 [(set_attr "got" "xgot_high") 3083 (set_attr "mode" "<MODE>")]) 3084 3085(define_insn_and_split "*xgot_lo<mode>" 3086 [(set (match_operand:P 0 "register_operand" "=d") 3087 (lo_sum:P (match_operand:P 1 "register_operand" "d") 3088 (match_operand:P 2 "global_got_operand" "")))] 3089 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT" 3090 "#" 3091 "&& reload_completed" 3092 [(set (match_dup 0) 3093 (unspec:P [(match_dup 1) (match_dup 3)] UNSPEC_LOAD_GOT))] 3094 { operands[3] = mips_unspec_address (operands[2], SYMBOL_GOTOFF_GLOBAL); } 3095 [(set_attr "got" "load") 3096 (set_attr "mode" "<MODE>")]) 3097 3098;; Insns to fetch a global symbol from a normal GOT. 3099 3100(define_insn_and_split "*got_disp<mode>" 3101 [(set (match_operand:P 0 "register_operand" "=d") 3102 (match_operand:P 1 "global_got_operand" ""))] 3103 "TARGET_EXPLICIT_RELOCS && !TARGET_XGOT" 3104 "#" 3105 "&& reload_completed" 3106 [(set (match_dup 0) 3107 (unspec:P [(match_dup 2) (match_dup 3)] UNSPEC_LOAD_GOT))] 3108{ 3109 operands[2] = pic_offset_table_rtx; 3110 operands[3] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_GLOBAL); 3111} 3112 [(set_attr "got" "load") 3113 (set_attr "mode" "<MODE>")]) 3114 3115;; Insns for loading the high part of a local symbol. 3116 3117(define_insn_and_split "*got_page<mode>" 3118 [(set (match_operand:P 0 "register_operand" "=d") 3119 (high:P (match_operand:P 1 "local_got_operand" "")))] 3120 "TARGET_EXPLICIT_RELOCS" 3121 "#" 3122 "&& reload_completed" 3123 [(set (match_dup 0) 3124 (unspec:P [(match_dup 2) (match_dup 3)] UNSPEC_LOAD_GOT))] 3125{ 3126 operands[2] = pic_offset_table_rtx; 3127 operands[3] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_PAGE); 3128} 3129 [(set_attr "got" "load") 3130 (set_attr "mode" "<MODE>")]) 3131 3132;; Lower-level instructions for loading an address from the GOT. 3133;; We could use MEMs, but an unspec gives more optimization 3134;; opportunities. 3135 3136(define_insn "load_got<mode>" 3137 [(set (match_operand:P 0 "register_operand" "=d") 3138 (unspec:P [(match_operand:P 1 "register_operand" "d") 3139 (match_operand:P 2 "immediate_operand" "")] 3140 UNSPEC_LOAD_GOT))] 3141 "" 3142 "<load>\t%0,%R2(%1)" 3143 [(set_attr "type" "load") 3144 (set_attr "mode" "<MODE>") 3145 (set_attr "length" "4")]) 3146 3147;; Instructions for adding the low 16 bits of an address to a register. 3148;; Operand 2 is the address: print_operand works out which relocation 3149;; should be applied. 3150 3151(define_insn "*low<mode>" 3152 [(set (match_operand:P 0 "register_operand" "=d") 3153 (lo_sum:P (match_operand:P 1 "register_operand" "d") 3154 (match_operand:P 2 "immediate_operand" "")))] 3155 "!TARGET_MIPS16" 3156 "<d>addiu\t%0,%1,%R2" 3157 [(set_attr "type" "arith") 3158 (set_attr "mode" "<MODE>")]) 3159 3160(define_insn "*low<mode>_mips16" 3161 [(set (match_operand:P 0 "register_operand" "=d") 3162 (lo_sum:P (match_operand:P 1 "register_operand" "0") 3163 (match_operand:P 2 "immediate_operand" "")))] 3164 "TARGET_MIPS16" 3165 "<d>addiu\t%0,%R2" 3166 [(set_attr "type" "arith") 3167 (set_attr "mode" "<MODE>") 3168 (set_attr "length" "8")]) 3169 3170;; 64-bit integer moves 3171 3172;; Unlike most other insns, the move insns can't be split with 3173;; different predicates, because register spilling and other parts of 3174;; the compiler, have memoized the insn number already. 3175 3176(define_expand "movdi" 3177 [(set (match_operand:DI 0 "") 3178 (match_operand:DI 1 ""))] 3179 "" 3180{ 3181 if (mips_legitimize_move (DImode, operands[0], operands[1])) 3182 DONE; 3183}) 3184 3185;; For mips16, we need a special case to handle storing $31 into 3186;; memory, since we don't have a constraint to match $31. This 3187;; instruction can be generated by save_restore_insns. 3188 3189(define_insn "*mov<mode>_ra" 3190 [(set (match_operand:GPR 0 "stack_operand" "=m") 3191 (reg:GPR 31))] 3192 "TARGET_MIPS16" 3193 "<store>\t$31,%0" 3194 [(set_attr "type" "store") 3195 (set_attr "mode" "<MODE>")]) 3196 3197(define_insn "*movdi_32bit" 3198 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*B*C*D,*B*C*D,*d,*m") 3199 (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))] 3200 "!TARGET_64BIT && !TARGET_MIPS16 3201 && (register_operand (operands[0], DImode) 3202 || reg_or_0_operand (operands[1], DImode))" 3203 { return mips_output_move (operands[0], operands[1]); } 3204 [(set_attr "type" "arith,arith,load,store,mthilo,mfhilo,xfer,load,xfer,store") 3205 (set_attr "mode" "DI") 3206 (set_attr "length" "8,16,*,*,8,8,8,*,8,*")]) 3207 3208(define_insn "*movdi_32bit_mips16" 3209 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d") 3210 (match_operand:DI 1 "move_operand" "d,d,y,K,N,m,d,*x"))] 3211 "!TARGET_64BIT && TARGET_MIPS16 3212 && (register_operand (operands[0], DImode) 3213 || register_operand (operands[1], DImode))" 3214 { return mips_output_move (operands[0], operands[1]); } 3215 [(set_attr "type" "arith,arith,arith,arith,arith,load,store,mfhilo") 3216 (set_attr "mode" "DI") 3217 (set_attr "length" "8,8,8,8,12,*,*,8")]) 3218 3219(define_insn "*movdi_64bit" 3220 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*f,*d,*m,*x,*B*C*D,*B*C*D,*d,*m") 3221 (match_operand:DI 1 "move_operand" "d,U,T,m,dJ,*f,*d*J,*m,*f,*f,*J*d,*d,*m,*B*C*D,*B*C*D"))] 3222 "TARGET_64BIT && !TARGET_MIPS16 3223 && (register_operand (operands[0], DImode) 3224 || reg_or_0_operand (operands[1], DImode))" 3225 { return mips_output_move (operands[0], operands[1]); } 3226 [(set_attr "type" "arith,const,const,load,store,fmove,xfer,fpload,xfer,fpstore,mthilo,xfer,load,xfer,store") 3227 (set_attr "mode" "DI") 3228 (set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,8,*,8,*")]) 3229 3230(define_insn "*movdi_64bit_mips16" 3231 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,m") 3232 (match_operand:DI 1 "move_operand" "d,d,y,K,N,U,m,d"))] 3233 "TARGET_64BIT && TARGET_MIPS16 3234 && (register_operand (operands[0], DImode) 3235 || register_operand (operands[1], DImode))" 3236 { return mips_output_move (operands[0], operands[1]); } 3237 [(set_attr "type" "arith,arith,arith,arith,arith,const,load,store") 3238 (set_attr "mode" "DI") 3239 (set_attr_alternative "length" 3240 [(const_int 4) 3241 (const_int 4) 3242 (const_int 4) 3243 (if_then_else (match_operand:VOID 1 "m16_uimm8_1") 3244 (const_int 4) 3245 (const_int 8)) 3246 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1") 3247 (const_int 8) 3248 (const_int 12)) 3249 (const_string "*") 3250 (const_string "*") 3251 (const_string "*")])]) 3252 3253 3254;; On the mips16, we can split ld $r,N($r) into an add and a load, 3255;; when the original load is a 4 byte instruction but the add and the 3256;; load are 2 2 byte instructions. 3257 3258(define_split 3259 [(set (match_operand:DI 0 "register_operand") 3260 (mem:DI (plus:DI (match_dup 0) 3261 (match_operand:DI 1 "const_int_operand"))))] 3262 "TARGET_64BIT && TARGET_MIPS16 && reload_completed 3263 && !TARGET_DEBUG_D_MODE 3264 && REG_P (operands[0]) 3265 && M16_REG_P (REGNO (operands[0])) 3266 && GET_CODE (operands[1]) == CONST_INT 3267 && ((INTVAL (operands[1]) < 0 3268 && INTVAL (operands[1]) >= -0x10) 3269 || (INTVAL (operands[1]) >= 32 * 8 3270 && INTVAL (operands[1]) <= 31 * 8 + 0x8) 3271 || (INTVAL (operands[1]) >= 0 3272 && INTVAL (operands[1]) < 32 * 8 3273 && (INTVAL (operands[1]) & 7) != 0))" 3274 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1))) 3275 (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))] 3276{ 3277 HOST_WIDE_INT val = INTVAL (operands[1]); 3278 3279 if (val < 0) 3280 operands[2] = const0_rtx; 3281 else if (val >= 32 * 8) 3282 { 3283 int off = val & 7; 3284 3285 operands[1] = GEN_INT (0x8 + off); 3286 operands[2] = GEN_INT (val - off - 0x8); 3287 } 3288 else 3289 { 3290 int off = val & 7; 3291 3292 operands[1] = GEN_INT (off); 3293 operands[2] = GEN_INT (val - off); 3294 } 3295}) 3296 3297;; 32-bit Integer moves 3298 3299;; Unlike most other insns, the move insns can't be split with 3300;; different predicates, because register spilling and other parts of 3301;; the compiler, have memoized the insn number already. 3302 3303(define_expand "movsi" 3304 [(set (match_operand:SI 0 "") 3305 (match_operand:SI 1 ""))] 3306 "" 3307{ 3308 if (mips_legitimize_move (SImode, operands[0], operands[1])) 3309 DONE; 3310}) 3311 3312;; The difference between these two is whether or not ints are allowed 3313;; in FP registers (off by default, use -mdebugh to enable). 3314 3315(define_insn "*movsi_internal" 3316 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m") 3317 (match_operand:SI 1 "move_operand" "d,U,T,m,dJ,*f,*d*J,*m,*f,*f,*z,*d,*J*d,*A,*d,*m,*B*C*D,*B*C*D"))] 3318 "!TARGET_MIPS16 3319 && (register_operand (operands[0], SImode) 3320 || reg_or_0_operand (operands[1], SImode))" 3321 { return mips_output_move (operands[0], operands[1]); } 3322 [(set_attr "type" "arith,const,const,load,store,fmove,xfer,fpload,xfer,fpstore,xfer,xfer,mthilo,mfhilo,xfer,load,xfer,store") 3323 (set_attr "mode" "SI") 3324 (set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,4,4,4,4,*,4,*")]) 3325 3326(define_insn "*movsi_mips16" 3327 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,m") 3328 (match_operand:SI 1 "move_operand" "d,d,y,K,N,U,m,d"))] 3329 "TARGET_MIPS16 3330 && (register_operand (operands[0], SImode) 3331 || register_operand (operands[1], SImode))" 3332 { return mips_output_move (operands[0], operands[1]); } 3333 [(set_attr "type" "arith,arith,arith,arith,arith,const,load,store") 3334 (set_attr "mode" "SI") 3335 (set_attr_alternative "length" 3336 [(const_int 4) 3337 (const_int 4) 3338 (const_int 4) 3339 (if_then_else (match_operand:VOID 1 "m16_uimm8_1") 3340 (const_int 4) 3341 (const_int 8)) 3342 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1") 3343 (const_int 8) 3344 (const_int 12)) 3345 (const_string "*") 3346 (const_string "*") 3347 (const_string "*")])]) 3348 3349;; On the mips16, we can split lw $r,N($r) into an add and a load, 3350;; when the original load is a 4 byte instruction but the add and the 3351;; load are 2 2 byte instructions. 3352 3353(define_split 3354 [(set (match_operand:SI 0 "register_operand") 3355 (mem:SI (plus:SI (match_dup 0) 3356 (match_operand:SI 1 "const_int_operand"))))] 3357 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE 3358 && REG_P (operands[0]) 3359 && M16_REG_P (REGNO (operands[0])) 3360 && GET_CODE (operands[1]) == CONST_INT 3361 && ((INTVAL (operands[1]) < 0 3362 && INTVAL (operands[1]) >= -0x80) 3363 || (INTVAL (operands[1]) >= 32 * 4 3364 && INTVAL (operands[1]) <= 31 * 4 + 0x7c) 3365 || (INTVAL (operands[1]) >= 0 3366 && INTVAL (operands[1]) < 32 * 4 3367 && (INTVAL (operands[1]) & 3) != 0))" 3368 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1))) 3369 (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))] 3370{ 3371 HOST_WIDE_INT val = INTVAL (operands[1]); 3372 3373 if (val < 0) 3374 operands[2] = const0_rtx; 3375 else if (val >= 32 * 4) 3376 { 3377 int off = val & 3; 3378 3379 operands[1] = GEN_INT (0x7c + off); 3380 operands[2] = GEN_INT (val - off - 0x7c); 3381 } 3382 else 3383 { 3384 int off = val & 3; 3385 3386 operands[1] = GEN_INT (off); 3387 operands[2] = GEN_INT (val - off); 3388 } 3389}) 3390 3391;; On the mips16, we can split a load of certain constants into a load 3392;; and an add. This turns a 4 byte instruction into 2 2 byte 3393;; instructions. 3394 3395(define_split 3396 [(set (match_operand:SI 0 "register_operand") 3397 (match_operand:SI 1 "const_int_operand"))] 3398 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE 3399 && REG_P (operands[0]) 3400 && M16_REG_P (REGNO (operands[0])) 3401 && GET_CODE (operands[1]) == CONST_INT 3402 && INTVAL (operands[1]) >= 0x100 3403 && INTVAL (operands[1]) <= 0xff + 0x7f" 3404 [(set (match_dup 0) (match_dup 1)) 3405 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))] 3406{ 3407 int val = INTVAL (operands[1]); 3408 3409 operands[1] = GEN_INT (0xff); 3410 operands[2] = GEN_INT (val - 0xff); 3411}) 3412 3413;; This insn handles moving CCmode values. It's really just a 3414;; slightly simplified copy of movsi_internal2, with additional cases 3415;; to move a condition register to a general register and to move 3416;; between the general registers and the floating point registers. 3417 3418(define_insn "movcc" 3419 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*m,*d,*f,*f,*f,*m") 3420 (match_operand:CC 1 "general_operand" "z,*d,*m,*d,*f,*d,*f,*m,*f"))] 3421 "ISA_HAS_8CC && TARGET_HARD_FLOAT" 3422 { return mips_output_move (operands[0], operands[1]); } 3423 [(set_attr "type" "xfer,arith,load,store,xfer,xfer,fmove,fpload,fpstore") 3424 (set_attr "mode" "SI") 3425 (set_attr "length" "8,4,*,*,4,4,4,*,*")]) 3426 3427;; Reload condition code registers. reload_incc and reload_outcc 3428;; both handle moves from arbitrary operands into condition code 3429;; registers. reload_incc handles the more common case in which 3430;; a source operand is constrained to be in a condition-code 3431;; register, but has not been allocated to one. 3432;; 3433;; Sometimes, such as in movcc, we have a CCmode destination whose 3434;; constraints do not include 'z'. reload_outcc handles the case 3435;; when such an operand is allocated to a condition-code register. 3436;; 3437;; Note that reloads from a condition code register to some 3438;; other location can be done using ordinary moves. Moving 3439;; into a GPR takes a single movcc, moving elsewhere takes 3440;; two. We can leave these cases to the generic reload code. 3441(define_expand "reload_incc" 3442 [(set (match_operand:CC 0 "fcc_reload_operand" "=z") 3443 (match_operand:CC 1 "general_operand" "")) 3444 (clobber (match_operand:TF 2 "register_operand" "=&f"))] 3445 "ISA_HAS_8CC && TARGET_HARD_FLOAT" 3446{ 3447 mips_emit_fcc_reload (operands[0], operands[1], operands[2]); 3448 DONE; 3449}) 3450 3451(define_expand "reload_outcc" 3452 [(set (match_operand:CC 0 "fcc_reload_operand" "=z") 3453 (match_operand:CC 1 "register_operand" "")) 3454 (clobber (match_operand:TF 2 "register_operand" "=&f"))] 3455 "ISA_HAS_8CC && TARGET_HARD_FLOAT" 3456{ 3457 mips_emit_fcc_reload (operands[0], operands[1], operands[2]); 3458 DONE; 3459}) 3460 3461;; MIPS4 supports loading and storing a floating point register from 3462;; the sum of two general registers. We use two versions for each of 3463;; these four instructions: one where the two general registers are 3464;; SImode, and one where they are DImode. This is because general 3465;; registers will be in SImode when they hold 32 bit values, but, 3466;; since the 32 bit values are always sign extended, the [ls][wd]xc1 3467;; instructions will still work correctly. 3468 3469;; ??? Perhaps it would be better to support these instructions by 3470;; modifying GO_IF_LEGITIMATE_ADDRESS and friends. However, since 3471;; these instructions can only be used to load and store floating 3472;; point registers, that would probably cause trouble in reload. 3473 3474(define_insn "*<ANYF:loadx>_<P:mode>" 3475 [(set (match_operand:ANYF 0 "register_operand" "=f") 3476 (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d") 3477 (match_operand:P 2 "register_operand" "d"))))] 3478 "ISA_HAS_FP4" 3479 "<ANYF:loadx>\t%0,%1(%2)" 3480 [(set_attr "type" "fpidxload") 3481 (set_attr "mode" "<ANYF:UNITMODE>")]) 3482 3483(define_insn "*<ANYF:storex>_<P:mode>" 3484 [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d") 3485 (match_operand:P 2 "register_operand" "d"))) 3486 (match_operand:ANYF 0 "register_operand" "f"))] 3487 "ISA_HAS_FP4" 3488 "<ANYF:storex>\t%0,%1(%2)" 3489 [(set_attr "type" "fpidxstore") 3490 (set_attr "mode" "<ANYF:UNITMODE>")]) 3491 3492;; 16-bit Integer moves 3493 3494;; Unlike most other insns, the move insns can't be split with 3495;; different predicates, because register spilling and other parts of 3496;; the compiler, have memoized the insn number already. 3497;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND. 3498 3499(define_expand "movhi" 3500 [(set (match_operand:HI 0 "") 3501 (match_operand:HI 1 ""))] 3502 "" 3503{ 3504 if (mips_legitimize_move (HImode, operands[0], operands[1])) 3505 DONE; 3506}) 3507 3508(define_insn "*movhi_internal" 3509 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*f,*x") 3510 (match_operand:HI 1 "move_operand" "d,I,m,dJ,*f,*d,*f,*d"))] 3511 "!TARGET_MIPS16 3512 && (register_operand (operands[0], HImode) 3513 || reg_or_0_operand (operands[1], HImode))" 3514 "@ 3515 move\t%0,%1 3516 li\t%0,%1 3517 lhu\t%0,%1 3518 sh\t%z1,%0 3519 mfc1\t%0,%1 3520 mtc1\t%1,%0 3521 mov.s\t%0,%1 3522 mt%0\t%1" 3523 [(set_attr "type" "arith,arith,load,store,xfer,xfer,fmove,mthilo") 3524 (set_attr "mode" "HI") 3525 (set_attr "length" "4,4,*,*,4,4,4,4")]) 3526 3527(define_insn "*movhi_mips16" 3528 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m") 3529 (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d"))] 3530 "TARGET_MIPS16 3531 && (register_operand (operands[0], HImode) 3532 || register_operand (operands[1], HImode))" 3533 "@ 3534 move\t%0,%1 3535 move\t%0,%1 3536 move\t%0,%1 3537 li\t%0,%1 3538 # 3539 lhu\t%0,%1 3540 sh\t%1,%0" 3541 [(set_attr "type" "arith,arith,arith,arith,arith,load,store") 3542 (set_attr "mode" "HI") 3543 (set_attr_alternative "length" 3544 [(const_int 4) 3545 (const_int 4) 3546 (const_int 4) 3547 (if_then_else (match_operand:VOID 1 "m16_uimm8_1") 3548 (const_int 4) 3549 (const_int 8)) 3550 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1") 3551 (const_int 8) 3552 (const_int 12)) 3553 (const_string "*") 3554 (const_string "*")])]) 3555 3556 3557;; On the mips16, we can split lh $r,N($r) into an add and a load, 3558;; when the original load is a 4 byte instruction but the add and the 3559;; load are 2 2 byte instructions. 3560 3561(define_split 3562 [(set (match_operand:HI 0 "register_operand") 3563 (mem:HI (plus:SI (match_dup 0) 3564 (match_operand:SI 1 "const_int_operand"))))] 3565 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE 3566 && REG_P (operands[0]) 3567 && M16_REG_P (REGNO (operands[0])) 3568 && GET_CODE (operands[1]) == CONST_INT 3569 && ((INTVAL (operands[1]) < 0 3570 && INTVAL (operands[1]) >= -0x80) 3571 || (INTVAL (operands[1]) >= 32 * 2 3572 && INTVAL (operands[1]) <= 31 * 2 + 0x7e) 3573 || (INTVAL (operands[1]) >= 0 3574 && INTVAL (operands[1]) < 32 * 2 3575 && (INTVAL (operands[1]) & 1) != 0))" 3576 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1))) 3577 (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))] 3578{ 3579 HOST_WIDE_INT val = INTVAL (operands[1]); 3580 3581 if (val < 0) 3582 operands[2] = const0_rtx; 3583 else if (val >= 32 * 2) 3584 { 3585 int off = val & 1; 3586 3587 operands[1] = GEN_INT (0x7e + off); 3588 operands[2] = GEN_INT (val - off - 0x7e); 3589 } 3590 else 3591 { 3592 int off = val & 1; 3593 3594 operands[1] = GEN_INT (off); 3595 operands[2] = GEN_INT (val - off); 3596 } 3597}) 3598 3599;; 8-bit Integer moves 3600 3601;; Unlike most other insns, the move insns can't be split with 3602;; different predicates, because register spilling and other parts of 3603;; the compiler, have memoized the insn number already. 3604;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND. 3605 3606(define_expand "movqi" 3607 [(set (match_operand:QI 0 "") 3608 (match_operand:QI 1 ""))] 3609 "" 3610{ 3611 if (mips_legitimize_move (QImode, operands[0], operands[1])) 3612 DONE; 3613}) 3614 3615(define_insn "*movqi_internal" 3616 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*f,*x") 3617 (match_operand:QI 1 "move_operand" "d,I,m,dJ,*f,*d,*f,*d"))] 3618 "!TARGET_MIPS16 3619 && (register_operand (operands[0], QImode) 3620 || reg_or_0_operand (operands[1], QImode))" 3621 "@ 3622 move\t%0,%1 3623 li\t%0,%1 3624 lbu\t%0,%1 3625 sb\t%z1,%0 3626 mfc1\t%0,%1 3627 mtc1\t%1,%0 3628 mov.s\t%0,%1 3629 mt%0\t%1" 3630 [(set_attr "type" "arith,arith,load,store,xfer,xfer,fmove,mthilo") 3631 (set_attr "mode" "QI") 3632 (set_attr "length" "4,4,*,*,4,4,4,4")]) 3633 3634(define_insn "*movqi_mips16" 3635 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m") 3636 (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d"))] 3637 "TARGET_MIPS16 3638 && (register_operand (operands[0], QImode) 3639 || register_operand (operands[1], QImode))" 3640 "@ 3641 move\t%0,%1 3642 move\t%0,%1 3643 move\t%0,%1 3644 li\t%0,%1 3645 # 3646 lbu\t%0,%1 3647 sb\t%1,%0" 3648 [(set_attr "type" "arith,arith,arith,arith,arith,load,store") 3649 (set_attr "mode" "QI") 3650 (set_attr "length" "4,4,4,4,8,*,*")]) 3651 3652;; On the mips16, we can split lb $r,N($r) into an add and a load, 3653;; when the original load is a 4 byte instruction but the add and the 3654;; load are 2 2 byte instructions. 3655 3656(define_split 3657 [(set (match_operand:QI 0 "register_operand") 3658 (mem:QI (plus:SI (match_dup 0) 3659 (match_operand:SI 1 "const_int_operand"))))] 3660 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE 3661 && REG_P (operands[0]) 3662 && M16_REG_P (REGNO (operands[0])) 3663 && GET_CODE (operands[1]) == CONST_INT 3664 && ((INTVAL (operands[1]) < 0 3665 && INTVAL (operands[1]) >= -0x80) 3666 || (INTVAL (operands[1]) >= 32 3667 && INTVAL (operands[1]) <= 31 + 0x7f))" 3668 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1))) 3669 (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))] 3670{ 3671 HOST_WIDE_INT val = INTVAL (operands[1]); 3672 3673 if (val < 0) 3674 operands[2] = const0_rtx; 3675 else 3676 { 3677 operands[1] = GEN_INT (0x7f); 3678 operands[2] = GEN_INT (val - 0x7f); 3679 } 3680}) 3681 3682;; 32-bit floating point moves 3683 3684(define_expand "movsf" 3685 [(set (match_operand:SF 0 "") 3686 (match_operand:SF 1 ""))] 3687 "" 3688{ 3689 if (mips_legitimize_move (SFmode, operands[0], operands[1])) 3690 DONE; 3691}) 3692 3693(define_insn "*movsf_hardfloat" 3694 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m") 3695 (match_operand:SF 1 "move_operand" "f,G,m,f,G,*d,*f,*G*d,*m,*d"))] 3696 "TARGET_HARD_FLOAT 3697 && (register_operand (operands[0], SFmode) 3698 || reg_or_0_operand (operands[1], SFmode))" 3699 { return mips_output_move (operands[0], operands[1]); } 3700 [(set_attr "type" "fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store") 3701 (set_attr "mode" "SF") 3702 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")]) 3703 3704(define_insn "*movsf_softfloat" 3705 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m") 3706 (match_operand:SF 1 "move_operand" "Gd,m,d"))] 3707 "TARGET_SOFT_FLOAT && !TARGET_MIPS16 3708 && (register_operand (operands[0], SFmode) 3709 || reg_or_0_operand (operands[1], SFmode))" 3710 { return mips_output_move (operands[0], operands[1]); } 3711 [(set_attr "type" "arith,load,store") 3712 (set_attr "mode" "SF") 3713 (set_attr "length" "4,*,*")]) 3714 3715(define_insn "*movsf_mips16" 3716 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,m") 3717 (match_operand:SF 1 "move_operand" "d,d,y,m,d"))] 3718 "TARGET_MIPS16 3719 && (register_operand (operands[0], SFmode) 3720 || register_operand (operands[1], SFmode))" 3721 { return mips_output_move (operands[0], operands[1]); } 3722 [(set_attr "type" "arith,arith,arith,load,store") 3723 (set_attr "mode" "SF") 3724 (set_attr "length" "4,4,4,*,*")]) 3725 3726 3727;; 64-bit floating point moves 3728 3729(define_expand "movdf" 3730 [(set (match_operand:DF 0 "") 3731 (match_operand:DF 1 ""))] 3732 "" 3733{ 3734 if (mips_legitimize_move (DFmode, operands[0], operands[1])) 3735 DONE; 3736}) 3737 3738(define_insn "*movdf_hardfloat_64bit" 3739 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m") 3740 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))] 3741 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_64BIT 3742 && (register_operand (operands[0], DFmode) 3743 || reg_or_0_operand (operands[1], DFmode))" 3744 { return mips_output_move (operands[0], operands[1]); } 3745 [(set_attr "type" "fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store") 3746 (set_attr "mode" "DF") 3747 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")]) 3748 3749(define_insn "*movdf_hardfloat_32bit" 3750 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m") 3751 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))] 3752 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT 3753 && (register_operand (operands[0], DFmode) 3754 || reg_or_0_operand (operands[1], DFmode))" 3755 { return mips_output_move (operands[0], operands[1]); } 3756 [(set_attr "type" "fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store") 3757 (set_attr "mode" "DF") 3758 (set_attr "length" "4,8,*,*,*,8,8,8,*,*")]) 3759 3760(define_insn "*movdf_softfloat" 3761 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m,d,f,f") 3762 (match_operand:DF 1 "move_operand" "dG,m,dG,f,d,f"))] 3763 "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16 3764 && (register_operand (operands[0], DFmode) 3765 || reg_or_0_operand (operands[1], DFmode))" 3766 { return mips_output_move (operands[0], operands[1]); } 3767 [(set_attr "type" "arith,load,store,xfer,xfer,fmove") 3768 (set_attr "mode" "DF") 3769 (set_attr "length" "8,*,*,4,4,4")]) 3770 3771(define_insn "*movdf_mips16" 3772 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,m") 3773 (match_operand:DF 1 "move_operand" "d,d,y,m,d"))] 3774 "TARGET_MIPS16 3775 && (register_operand (operands[0], DFmode) 3776 || register_operand (operands[1], DFmode))" 3777 { return mips_output_move (operands[0], operands[1]); } 3778 [(set_attr "type" "arith,arith,arith,load,store") 3779 (set_attr "mode" "DF") 3780 (set_attr "length" "8,8,8,*,*")]) 3781 3782(define_split 3783 [(set (match_operand:DI 0 "nonimmediate_operand") 3784 (match_operand:DI 1 "move_operand"))] 3785 "reload_completed && !TARGET_64BIT 3786 && mips_split_64bit_move_p (operands[0], operands[1])" 3787 [(const_int 0)] 3788{ 3789 mips_split_64bit_move (operands[0], operands[1]); 3790 DONE; 3791}) 3792 3793(define_split 3794 [(set (match_operand:DF 0 "nonimmediate_operand") 3795 (match_operand:DF 1 "move_operand"))] 3796 "reload_completed && !TARGET_64BIT 3797 && mips_split_64bit_move_p (operands[0], operands[1])" 3798 [(const_int 0)] 3799{ 3800 mips_split_64bit_move (operands[0], operands[1]); 3801 DONE; 3802}) 3803 3804;; When generating mips16 code, split moves of negative constants into 3805;; a positive "li" followed by a negation. 3806(define_split 3807 [(set (match_operand 0 "register_operand") 3808 (match_operand 1 "const_int_operand"))] 3809 "TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0" 3810 [(set (match_dup 2) 3811 (match_dup 3)) 3812 (set (match_dup 2) 3813 (neg:SI (match_dup 2)))] 3814{ 3815 operands[2] = gen_lowpart (SImode, operands[0]); 3816 operands[3] = GEN_INT (-INTVAL (operands[1])); 3817}) 3818 3819;; 64-bit paired-single floating point moves 3820 3821(define_expand "movv2sf" 3822 [(set (match_operand:V2SF 0) 3823 (match_operand:V2SF 1))] 3824 "TARGET_PAIRED_SINGLE_FLOAT" 3825{ 3826 if (mips_legitimize_move (V2SFmode, operands[0], operands[1])) 3827 DONE; 3828}) 3829 3830(define_insn "movv2sf_hardfloat_64bit" 3831 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m") 3832 (match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))] 3833 "TARGET_PAIRED_SINGLE_FLOAT 3834 && TARGET_64BIT 3835 && (register_operand (operands[0], V2SFmode) 3836 || reg_or_0_operand (operands[1], V2SFmode))" 3837 { return mips_output_move (operands[0], operands[1]); } 3838 [(set_attr "type" "fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store") 3839 (set_attr "mode" "SF") 3840 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")]) 3841 3842;; The HI and LO registers are not truly independent. If we move an mthi 3843;; instruction before an mflo instruction, it will make the result of the 3844;; mflo unpredictable. The same goes for mtlo and mfhi. 3845;; 3846;; We cope with this by making the mflo and mfhi patterns use both HI and LO. 3847;; Operand 1 is the register we want, operand 2 is the other one. 3848;; 3849;; When generating VR4120 or VR4130 code, we use macc{,hi} and 3850;; dmacc{,hi} instead of mfhi and mflo. This avoids both the normal 3851;; MIPS III hi/lo hazards and the errata related to -mfix-vr4130. 3852 3853(define_expand "mfhilo_<mode>" 3854 [(set (match_operand:GPR 0 "register_operand") 3855 (unspec:GPR [(match_operand:GPR 1 "register_operand") 3856 (match_operand:GPR 2 "register_operand")] 3857 UNSPEC_MFHILO))]) 3858 3859(define_insn "*mfhilo_<mode>" 3860 [(set (match_operand:GPR 0 "register_operand" "=d,d") 3861 (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l") 3862 (match_operand:GPR 2 "register_operand" "l,h")] 3863 UNSPEC_MFHILO))] 3864 "!ISA_HAS_MACCHI" 3865 "mf%1\t%0" 3866 [(set_attr "type" "mfhilo") 3867 (set_attr "mode" "<MODE>")]) 3868 3869(define_insn "*mfhilo_<mode>_macc" 3870 [(set (match_operand:GPR 0 "register_operand" "=d,d") 3871 (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l") 3872 (match_operand:GPR 2 "register_operand" "l,h")] 3873 UNSPEC_MFHILO))] 3874 "ISA_HAS_MACCHI" 3875{ 3876 if (REGNO (operands[1]) == HI_REGNUM) 3877 return "<d>macchi\t%0,%.,%."; 3878 else 3879 return "<d>macc\t%0,%.,%."; 3880} 3881 [(set_attr "type" "mfhilo") 3882 (set_attr "mode" "<MODE>")]) 3883 3884;; Patterns for loading or storing part of a paired floating point 3885;; register. We need them because odd-numbered floating-point registers 3886;; are not fully independent: see mips_split_64bit_move. 3887 3888;; Load the low word of operand 0 with operand 1. 3889(define_insn "load_df_low" 3890 [(set (match_operand:DF 0 "register_operand" "=f,f") 3891 (unspec:DF [(match_operand:SI 1 "general_operand" "dJ,m")] 3892 UNSPEC_LOAD_DF_LOW))] 3893 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT" 3894{ 3895 operands[0] = mips_subword (operands[0], 0); 3896 return mips_output_move (operands[0], operands[1]); 3897} 3898 [(set_attr "type" "xfer,fpload") 3899 (set_attr "mode" "SF")]) 3900 3901;; Load the high word of operand 0 from operand 1, preserving the value 3902;; in the low word. 3903(define_insn "load_df_high" 3904 [(set (match_operand:DF 0 "register_operand" "=f,f") 3905 (unspec:DF [(match_operand:SI 1 "general_operand" "dJ,m") 3906 (match_operand:DF 2 "register_operand" "0,0")] 3907 UNSPEC_LOAD_DF_HIGH))] 3908 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT" 3909{ 3910 operands[0] = mips_subword (operands[0], 1); 3911 return mips_output_move (operands[0], operands[1]); 3912} 3913 [(set_attr "type" "xfer,fpload") 3914 (set_attr "mode" "SF")]) 3915 3916;; Store the high word of operand 1 in operand 0. The corresponding 3917;; low-word move is done in the normal way. 3918(define_insn "store_df_high" 3919 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,m") 3920 (unspec:SI [(match_operand:DF 1 "register_operand" "f,f")] 3921 UNSPEC_STORE_DF_HIGH))] 3922 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT" 3923{ 3924 operands[1] = mips_subword (operands[1], 1); 3925 return mips_output_move (operands[0], operands[1]); 3926} 3927 [(set_attr "type" "xfer,fpstore") 3928 (set_attr "mode" "SF")]) 3929 3930;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset 3931;; of _gp from the start of this function. Operand 1 is the incoming 3932;; function address. 3933(define_insn_and_split "loadgp" 3934 [(unspec_volatile [(match_operand 0 "" "") 3935 (match_operand 1 "register_operand" "")] UNSPEC_LOADGP)] 3936 "TARGET_ABICALLS && TARGET_NEWABI" 3937 "#" 3938 "" 3939 [(set (match_dup 2) (match_dup 3)) 3940 (set (match_dup 2) (match_dup 4)) 3941 (set (match_dup 2) (match_dup 5))] 3942{ 3943 operands[2] = pic_offset_table_rtx; 3944 operands[3] = gen_rtx_HIGH (Pmode, operands[0]); 3945 operands[4] = gen_rtx_PLUS (Pmode, operands[2], operands[1]); 3946 operands[5] = gen_rtx_LO_SUM (Pmode, operands[2], operands[0]); 3947} 3948 [(set_attr "length" "12")]) 3949 3950;; The use of gp is hidden when not using explicit relocations. 3951;; This blockage instruction prevents the gp load from being 3952;; scheduled after an implicit use of gp. It also prevents 3953;; the load from being deleted as dead. 3954(define_insn "loadgp_blockage" 3955 [(unspec_volatile [(reg:DI 28)] UNSPEC_BLOCKAGE)] 3956 "" 3957 "" 3958 [(set_attr "type" "unknown") 3959 (set_attr "mode" "none") 3960 (set_attr "length" "0")]) 3961 3962;; Emit a .cprestore directive, which normally expands to a single store 3963;; instruction. Note that we continue to use .cprestore for explicit reloc 3964;; code so that jals inside inline asms will work correctly. 3965(define_insn "cprestore" 3966 [(unspec_volatile [(match_operand 0 "const_int_operand" "I,i")] 3967 UNSPEC_CPRESTORE)] 3968 "" 3969{ 3970 if (set_nomacro && which_alternative == 1) 3971 return ".set\tmacro\;.cprestore\t%0\;.set\tnomacro"; 3972 else 3973 return ".cprestore\t%0"; 3974} 3975 [(set_attr "type" "store") 3976 (set_attr "length" "4,12")]) 3977 3978;; Block moves, see mips.c for more details. 3979;; Argument 0 is the destination 3980;; Argument 1 is the source 3981;; Argument 2 is the length 3982;; Argument 3 is the alignment 3983 3984(define_expand "movmemsi" 3985 [(parallel [(set (match_operand:BLK 0 "general_operand") 3986 (match_operand:BLK 1 "general_operand")) 3987 (use (match_operand:SI 2 "")) 3988 (use (match_operand:SI 3 "const_int_operand"))])] 3989 "!TARGET_MIPS16 && !TARGET_MEMCPY" 3990{ 3991 if (mips_expand_block_move (operands[0], operands[1], operands[2])) 3992 DONE; 3993 else 3994 FAIL; 3995}) 3996 3997;; 3998;; .................... 3999;; 4000;; SHIFTS 4001;; 4002;; .................... 4003 4004(define_expand "<optab><mode>3" 4005 [(set (match_operand:GPR 0 "register_operand") 4006 (any_shift:GPR (match_operand:GPR 1 "register_operand") 4007 (match_operand:SI 2 "arith_operand")))] 4008 "" 4009{ 4010 /* On the mips16, a shift of more than 8 is a four byte instruction, 4011 so, for a shift between 8 and 16, it is just as fast to do two 4012 shifts of 8 or less. If there is a lot of shifting going on, we 4013 may win in CSE. Otherwise combine will put the shifts back 4014 together again. This can be called by function_arg, so we must 4015 be careful not to allocate a new register if we've reached the 4016 reload pass. */ 4017 if (TARGET_MIPS16 4018 && optimize 4019 && GET_CODE (operands[2]) == CONST_INT 4020 && INTVAL (operands[2]) > 8 4021 && INTVAL (operands[2]) <= 16 4022 && !reload_in_progress 4023 && !reload_completed) 4024 { 4025 rtx temp = gen_reg_rtx (<MODE>mode); 4026 4027 emit_insn (gen_<optab><mode>3 (temp, operands[1], GEN_INT (8))); 4028 emit_insn (gen_<optab><mode>3 (operands[0], temp, 4029 GEN_INT (INTVAL (operands[2]) - 8))); 4030 DONE; 4031 } 4032}) 4033 4034(define_insn "*<optab><mode>3" 4035 [(set (match_operand:GPR 0 "register_operand" "=d") 4036 (any_shift:GPR (match_operand:GPR 1 "register_operand" "d") 4037 (match_operand:SI 2 "arith_operand" "dI")))] 4038 "!TARGET_MIPS16" 4039{ 4040 if (GET_CODE (operands[2]) == CONST_INT) 4041 operands[2] = GEN_INT (INTVAL (operands[2]) 4042 & (GET_MODE_BITSIZE (<MODE>mode) - 1)); 4043 4044 return "<d><insn>\t%0,%1,%2"; 4045} 4046 [(set_attr "type" "shift") 4047 (set_attr "mode" "<MODE>")]) 4048 4049(define_insn "*<optab>si3_extend" 4050 [(set (match_operand:DI 0 "register_operand" "=d") 4051 (sign_extend:DI 4052 (any_shift:SI (match_operand:SI 1 "register_operand" "d") 4053 (match_operand:SI 2 "arith_operand" "dI"))))] 4054 "TARGET_64BIT && !TARGET_MIPS16" 4055{ 4056 if (GET_CODE (operands[2]) == CONST_INT) 4057 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); 4058 4059 return "<insn>\t%0,%1,%2"; 4060} 4061 [(set_attr "type" "shift") 4062 (set_attr "mode" "SI")]) 4063 4064(define_insn "*<optab>si3_mips16" 4065 [(set (match_operand:SI 0 "register_operand" "=d,d") 4066 (any_shift:SI (match_operand:SI 1 "register_operand" "0,d") 4067 (match_operand:SI 2 "arith_operand" "d,I")))] 4068 "TARGET_MIPS16" 4069{ 4070 if (which_alternative == 0) 4071 return "<insn>\t%0,%2"; 4072 4073 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); 4074 return "<insn>\t%0,%1,%2"; 4075} 4076 [(set_attr "type" "shift") 4077 (set_attr "mode" "SI") 4078 (set_attr_alternative "length" 4079 [(const_int 4) 4080 (if_then_else (match_operand 2 "m16_uimm3_b") 4081 (const_int 4) 4082 (const_int 8))])]) 4083 4084;; We need separate DImode MIPS16 patterns because of the irregularity 4085;; of right shifts. 4086(define_insn "*ashldi3_mips16" 4087 [(set (match_operand:DI 0 "register_operand" "=d,d") 4088 (ashift:DI (match_operand:DI 1 "register_operand" "0,d") 4089 (match_operand:SI 2 "arith_operand" "d,I")))] 4090 "TARGET_64BIT && TARGET_MIPS16" 4091{ 4092 if (which_alternative == 0) 4093 return "dsll\t%0,%2"; 4094 4095 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); 4096 return "dsll\t%0,%1,%2"; 4097} 4098 [(set_attr "type" "shift") 4099 (set_attr "mode" "DI") 4100 (set_attr_alternative "length" 4101 [(const_int 4) 4102 (if_then_else (match_operand 2 "m16_uimm3_b") 4103 (const_int 4) 4104 (const_int 8))])]) 4105 4106(define_insn "*ashrdi3_mips16" 4107 [(set (match_operand:DI 0 "register_operand" "=d,d") 4108 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0") 4109 (match_operand:SI 2 "arith_operand" "d,I")))] 4110 "TARGET_64BIT && TARGET_MIPS16" 4111{ 4112 if (GET_CODE (operands[2]) == CONST_INT) 4113 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); 4114 4115 return "dsra\t%0,%2"; 4116} 4117 [(set_attr "type" "shift") 4118 (set_attr "mode" "DI") 4119 (set_attr_alternative "length" 4120 [(const_int 4) 4121 (if_then_else (match_operand 2 "m16_uimm3_b") 4122 (const_int 4) 4123 (const_int 8))])]) 4124 4125(define_insn "*lshrdi3_mips16" 4126 [(set (match_operand:DI 0 "register_operand" "=d,d") 4127 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0") 4128 (match_operand:SI 2 "arith_operand" "d,I")))] 4129 "TARGET_64BIT && TARGET_MIPS16" 4130{ 4131 if (GET_CODE (operands[2]) == CONST_INT) 4132 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); 4133 4134 return "dsrl\t%0,%2"; 4135} 4136 [(set_attr "type" "shift") 4137 (set_attr "mode" "DI") 4138 (set_attr_alternative "length" 4139 [(const_int 4) 4140 (if_then_else (match_operand 2 "m16_uimm3_b") 4141 (const_int 4) 4142 (const_int 8))])]) 4143 4144;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts. 4145 4146(define_split 4147 [(set (match_operand:GPR 0 "register_operand") 4148 (any_shift:GPR (match_operand:GPR 1 "register_operand") 4149 (match_operand:GPR 2 "const_int_operand")))] 4150 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE 4151 && GET_CODE (operands[2]) == CONST_INT 4152 && INTVAL (operands[2]) > 8 4153 && INTVAL (operands[2]) <= 16" 4154 [(set (match_dup 0) (any_shift:GPR (match_dup 1) (const_int 8))) 4155 (set (match_dup 0) (any_shift:GPR (match_dup 0) (match_dup 2)))] 4156 { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); }) 4157 4158;; If we load a byte on the mips16 as a bitfield, the resulting 4159;; sequence of instructions is too complicated for combine, because it 4160;; involves four instructions: a load, a shift, a constant load into a 4161;; register, and an and (the key problem here is that the mips16 does 4162;; not have and immediate). We recognize a shift of a load in order 4163;; to make it simple enough for combine to understand. 4164;; 4165;; The length here is the worst case: the length of the split version 4166;; will be more accurate. 4167(define_insn_and_split "" 4168 [(set (match_operand:SI 0 "register_operand" "=d") 4169 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m") 4170 (match_operand:SI 2 "immediate_operand" "I")))] 4171 "TARGET_MIPS16" 4172 "#" 4173 "" 4174 [(set (match_dup 0) (match_dup 1)) 4175 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))] 4176 "" 4177 [(set_attr "type" "load") 4178 (set_attr "mode" "SI") 4179 (set_attr "length" "16")]) 4180 4181(define_insn "rotr<mode>3" 4182 [(set (match_operand:GPR 0 "register_operand" "=d") 4183 (rotatert:GPR (match_operand:GPR 1 "register_operand" "d") 4184 (match_operand:SI 2 "arith_operand" "dI")))] 4185 "ISA_HAS_ROTR_<MODE>" 4186{ 4187 if (GET_CODE (operands[2]) == CONST_INT) 4188 gcc_assert (INTVAL (operands[2]) >= 0 4189 && INTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)); 4190 4191 return "<d>ror\t%0,%1,%2"; 4192} 4193 [(set_attr "type" "shift") 4194 (set_attr "mode" "<MODE>")]) 4195 4196;; 4197;; .................... 4198;; 4199;; COMPARISONS 4200;; 4201;; .................... 4202 4203;; Flow here is rather complex: 4204;; 4205;; 1) The cmp{si,di,sf,df} routine is called. It deposits the arguments 4206;; into cmp_operands[] but generates no RTL. 4207;; 4208;; 2) The appropriate branch define_expand is called, which then 4209;; creates the appropriate RTL for the comparison and branch. 4210;; Different CC modes are used, based on what type of branch is 4211;; done, so that we can constrain things appropriately. There 4212;; are assumptions in the rest of GCC that break if we fold the 4213;; operands into the branches for integer operations, and use cc0 4214;; for floating point, so we use the fp status register instead. 4215;; If needed, an appropriate temporary is created to hold the 4216;; of the integer compare. 4217 4218(define_expand "cmp<mode>" 4219 [(set (cc0) 4220 (compare:CC (match_operand:GPR 0 "register_operand") 4221 (match_operand:GPR 1 "nonmemory_operand")))] 4222 "" 4223{ 4224 cmp_operands[0] = operands[0]; 4225 cmp_operands[1] = operands[1]; 4226 DONE; 4227}) 4228 4229(define_expand "cmp<mode>" 4230 [(set (cc0) 4231 (compare:CC (match_operand:SCALARF 0 "register_operand") 4232 (match_operand:SCALARF 1 "register_operand")))] 4233 "" 4234{ 4235 cmp_operands[0] = operands[0]; 4236 cmp_operands[1] = operands[1]; 4237 DONE; 4238}) 4239 4240;; 4241;; .................... 4242;; 4243;; CONDITIONAL BRANCHES 4244;; 4245;; .................... 4246 4247;; Conditional branches on floating-point equality tests. 4248 4249(define_insn "branch_fp" 4250 [(set (pc) 4251 (if_then_else 4252 (match_operator:CC 0 "comparison_operator" 4253 [(match_operand:CC 2 "register_operand" "z") 4254 (const_int 0)]) 4255 (label_ref (match_operand 1 "" "")) 4256 (pc)))] 4257 "TARGET_HARD_FLOAT" 4258{ 4259 return mips_output_conditional_branch (insn, 4260 operands, 4261 /*two_operands_p=*/0, 4262 /*float_p=*/1, 4263 /*inverted_p=*/0, 4264 get_attr_length (insn)); 4265} 4266 [(set_attr "type" "branch") 4267 (set_attr "mode" "none")]) 4268 4269(define_insn "branch_fp_inverted" 4270 [(set (pc) 4271 (if_then_else 4272 (match_operator:CC 0 "comparison_operator" 4273 [(match_operand:CC 2 "register_operand" "z") 4274 (const_int 0)]) 4275 (pc) 4276 (label_ref (match_operand 1 "" ""))))] 4277 "TARGET_HARD_FLOAT" 4278{ 4279 return mips_output_conditional_branch (insn, 4280 operands, 4281 /*two_operands_p=*/0, 4282 /*float_p=*/1, 4283 /*inverted_p=*/1, 4284 get_attr_length (insn)); 4285} 4286 [(set_attr "type" "branch") 4287 (set_attr "mode" "none")]) 4288 4289;; Conditional branches on comparisons with zero. 4290 4291(define_insn "*branch_zero<mode>" 4292 [(set (pc) 4293 (if_then_else 4294 (match_operator:GPR 0 "comparison_operator" 4295 [(match_operand:GPR 2 "register_operand" "d") 4296 (const_int 0)]) 4297 (label_ref (match_operand 1 "" "")) 4298 (pc)))] 4299 "!TARGET_MIPS16" 4300{ 4301 return mips_output_conditional_branch (insn, 4302 operands, 4303 /*two_operands_p=*/0, 4304 /*float_p=*/0, 4305 /*inverted_p=*/0, 4306 get_attr_length (insn)); 4307} 4308 [(set_attr "type" "branch") 4309 (set_attr "mode" "none")]) 4310 4311(define_insn "*branch_zero<mode>_inverted" 4312 [(set (pc) 4313 (if_then_else 4314 (match_operator:GPR 0 "comparison_operator" 4315 [(match_operand:GPR 2 "register_operand" "d") 4316 (const_int 0)]) 4317 (pc) 4318 (label_ref (match_operand 1 "" ""))))] 4319 "!TARGET_MIPS16" 4320{ 4321 return mips_output_conditional_branch (insn, 4322 operands, 4323 /*two_operands_p=*/0, 4324 /*float_p=*/0, 4325 /*inverted_p=*/1, 4326 get_attr_length (insn)); 4327} 4328 [(set_attr "type" "branch") 4329 (set_attr "mode" "none")]) 4330 4331;; Conditional branch on equality comparison. 4332 4333(define_insn "*branch_equality<mode>" 4334 [(set (pc) 4335 (if_then_else 4336 (match_operator:GPR 0 "equality_operator" 4337 [(match_operand:GPR 2 "register_operand" "d") 4338 (match_operand:GPR 3 "register_operand" "d")]) 4339 (label_ref (match_operand 1 "" "")) 4340 (pc)))] 4341 "!TARGET_MIPS16" 4342{ 4343 return mips_output_conditional_branch (insn, 4344 operands, 4345 /*two_operands_p=*/1, 4346 /*float_p=*/0, 4347 /*inverted_p=*/0, 4348 get_attr_length (insn)); 4349} 4350 [(set_attr "type" "branch") 4351 (set_attr "mode" "none")]) 4352 4353(define_insn "*branch_equality<mode>_inverted" 4354 [(set (pc) 4355 (if_then_else 4356 (match_operator:GPR 0 "equality_operator" 4357 [(match_operand:GPR 2 "register_operand" "d") 4358 (match_operand:GPR 3 "register_operand" "d")]) 4359 (pc) 4360 (label_ref (match_operand 1 "" ""))))] 4361 "!TARGET_MIPS16" 4362{ 4363 return mips_output_conditional_branch (insn, 4364 operands, 4365 /*two_operands_p=*/1, 4366 /*float_p=*/0, 4367 /*inverted_p=*/1, 4368 get_attr_length (insn)); 4369} 4370 [(set_attr "type" "branch") 4371 (set_attr "mode" "none")]) 4372 4373;; MIPS16 branches 4374 4375(define_insn "*branch_equality<mode>_mips16" 4376 [(set (pc) 4377 (if_then_else 4378 (match_operator:GPR 0 "equality_operator" 4379 [(match_operand:GPR 1 "register_operand" "d,t") 4380 (const_int 0)]) 4381 (match_operand 2 "pc_or_label_operand" "") 4382 (match_operand 3 "pc_or_label_operand" "")))] 4383 "TARGET_MIPS16" 4384{ 4385 if (operands[2] != pc_rtx) 4386 { 4387 if (which_alternative == 0) 4388 return "b%C0z\t%1,%2"; 4389 else 4390 return "bt%C0z\t%2"; 4391 } 4392 else 4393 { 4394 if (which_alternative == 0) 4395 return "b%N0z\t%1,%3"; 4396 else 4397 return "bt%N0z\t%3"; 4398 } 4399} 4400 [(set_attr "type" "branch") 4401 (set_attr "mode" "none") 4402 (set_attr "length" "8")]) 4403 4404(define_expand "b<code>" 4405 [(set (pc) 4406 (if_then_else (any_cond:CC (cc0) 4407 (const_int 0)) 4408 (label_ref (match_operand 0 "")) 4409 (pc)))] 4410 "" 4411{ 4412 gen_conditional_branch (operands, <CODE>); 4413 DONE; 4414}) 4415 4416;; 4417;; .................... 4418;; 4419;; SETTING A REGISTER FROM A COMPARISON 4420;; 4421;; .................... 4422 4423(define_expand "seq" 4424 [(set (match_operand:SI 0 "register_operand") 4425 (eq:SI (match_dup 1) 4426 (match_dup 2)))] 4427 "" 4428 { if (mips_emit_scc (EQ, operands[0])) DONE; else FAIL; }) 4429 4430(define_insn "*seq_<mode>" 4431 [(set (match_operand:GPR 0 "register_operand" "=d") 4432 (eq:GPR (match_operand:GPR 1 "register_operand" "d") 4433 (const_int 0)))] 4434 "!TARGET_MIPS16" 4435 "sltu\t%0,%1,1" 4436 [(set_attr "type" "slt") 4437 (set_attr "mode" "<MODE>")]) 4438 4439(define_insn "*seq_<mode>_mips16" 4440 [(set (match_operand:GPR 0 "register_operand" "=t") 4441 (eq:GPR (match_operand:GPR 1 "register_operand" "d") 4442 (const_int 0)))] 4443 "TARGET_MIPS16" 4444 "sltu\t%1,1" 4445 [(set_attr "type" "slt") 4446 (set_attr "mode" "<MODE>")]) 4447 4448;; "sne" uses sltu instructions in which the first operand is $0. 4449;; This isn't possible in mips16 code. 4450 4451(define_expand "sne" 4452 [(set (match_operand:SI 0 "register_operand") 4453 (ne:SI (match_dup 1) 4454 (match_dup 2)))] 4455 "!TARGET_MIPS16" 4456 { if (mips_emit_scc (NE, operands[0])) DONE; else FAIL; }) 4457 4458(define_insn "*sne_<mode>" 4459 [(set (match_operand:GPR 0 "register_operand" "=d") 4460 (ne:GPR (match_operand:GPR 1 "register_operand" "d") 4461 (const_int 0)))] 4462 "!TARGET_MIPS16" 4463 "sltu\t%0,%.,%1" 4464 [(set_attr "type" "slt") 4465 (set_attr "mode" "<MODE>")]) 4466 4467(define_expand "sgt" 4468 [(set (match_operand:SI 0 "register_operand") 4469 (gt:SI (match_dup 1) 4470 (match_dup 2)))] 4471 "" 4472 { if (mips_emit_scc (GT, operands[0])) DONE; else FAIL; }) 4473 4474(define_insn "*sgt_<mode>" 4475 [(set (match_operand:GPR 0 "register_operand" "=d") 4476 (gt:GPR (match_operand:GPR 1 "register_operand" "d") 4477 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))] 4478 "!TARGET_MIPS16" 4479 "slt\t%0,%z2,%1" 4480 [(set_attr "type" "slt") 4481 (set_attr "mode" "<MODE>")]) 4482 4483(define_insn "*sgt_<mode>_mips16" 4484 [(set (match_operand:GPR 0 "register_operand" "=t") 4485 (gt:GPR (match_operand:GPR 1 "register_operand" "d") 4486 (match_operand:GPR 2 "register_operand" "d")))] 4487 "TARGET_MIPS16" 4488 "slt\t%2,%1" 4489 [(set_attr "type" "slt") 4490 (set_attr "mode" "<MODE>")]) 4491 4492(define_expand "sge" 4493 [(set (match_operand:SI 0 "register_operand") 4494 (ge:SI (match_dup 1) 4495 (match_dup 2)))] 4496 "" 4497 { if (mips_emit_scc (GE, operands[0])) DONE; else FAIL; }) 4498 4499(define_insn "*sge_<mode>" 4500 [(set (match_operand:GPR 0 "register_operand" "=d") 4501 (ge:GPR (match_operand:GPR 1 "register_operand" "d") 4502 (const_int 1)))] 4503 "!TARGET_MIPS16" 4504 "slt\t%0,%.,%1" 4505 [(set_attr "type" "slt") 4506 (set_attr "mode" "<MODE>")]) 4507 4508(define_expand "slt" 4509 [(set (match_operand:SI 0 "register_operand") 4510 (lt:SI (match_dup 1) 4511 (match_dup 2)))] 4512 "" 4513 { if (mips_emit_scc (LT, operands[0])) DONE; else FAIL; }) 4514 4515(define_insn "*slt_<mode>" 4516 [(set (match_operand:GPR 0 "register_operand" "=d") 4517 (lt:GPR (match_operand:GPR 1 "register_operand" "d") 4518 (match_operand:GPR 2 "arith_operand" "dI")))] 4519 "!TARGET_MIPS16" 4520 "slt\t%0,%1,%2" 4521 [(set_attr "type" "slt") 4522 (set_attr "mode" "<MODE>")]) 4523 4524(define_insn "*slt_<mode>_mips16" 4525 [(set (match_operand:GPR 0 "register_operand" "=t,t") 4526 (lt:GPR (match_operand:GPR 1 "register_operand" "d,d") 4527 (match_operand:GPR 2 "arith_operand" "d,I")))] 4528 "TARGET_MIPS16" 4529 "slt\t%1,%2" 4530 [(set_attr "type" "slt") 4531 (set_attr "mode" "<MODE>") 4532 (set_attr_alternative "length" 4533 [(const_int 4) 4534 (if_then_else (match_operand 2 "m16_uimm8_1") 4535 (const_int 4) 4536 (const_int 8))])]) 4537 4538(define_expand "sle" 4539 [(set (match_operand:SI 0 "register_operand") 4540 (le:SI (match_dup 1) 4541 (match_dup 2)))] 4542 "" 4543 { if (mips_emit_scc (LE, operands[0])) DONE; else FAIL; }) 4544 4545(define_insn "*sle_<mode>" 4546 [(set (match_operand:GPR 0 "register_operand" "=d") 4547 (le:GPR (match_operand:GPR 1 "register_operand" "d") 4548 (match_operand:GPR 2 "sle_operand" "")))] 4549 "!TARGET_MIPS16" 4550{ 4551 operands[2] = GEN_INT (INTVAL (operands[2]) + 1); 4552 return "slt\t%0,%1,%2"; 4553} 4554 [(set_attr "type" "slt") 4555 (set_attr "mode" "<MODE>")]) 4556 4557(define_insn "*sle_<mode>_mips16" 4558 [(set (match_operand:GPR 0 "register_operand" "=t") 4559 (le:GPR (match_operand:GPR 1 "register_operand" "d") 4560 (match_operand:GPR 2 "sle_operand" "")))] 4561 "TARGET_MIPS16" 4562{ 4563 operands[2] = GEN_INT (INTVAL (operands[2]) + 1); 4564 return "slt\t%1,%2"; 4565} 4566 [(set_attr "type" "slt") 4567 (set_attr "mode" "<MODE>") 4568 (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1") 4569 (const_int 4) 4570 (const_int 8)))]) 4571 4572(define_expand "sgtu" 4573 [(set (match_operand:SI 0 "register_operand") 4574 (gtu:SI (match_dup 1) 4575 (match_dup 2)))] 4576 "" 4577 { if (mips_emit_scc (GTU, operands[0])) DONE; else FAIL; }) 4578 4579(define_insn "*sgtu_<mode>" 4580 [(set (match_operand:GPR 0 "register_operand" "=d") 4581 (gtu:GPR (match_operand:GPR 1 "register_operand" "d") 4582 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))] 4583 "!TARGET_MIPS16" 4584 "sltu\t%0,%z2,%1" 4585 [(set_attr "type" "slt") 4586 (set_attr "mode" "<MODE>")]) 4587 4588(define_insn "*sgtu_<mode>_mips16" 4589 [(set (match_operand:GPR 0 "register_operand" "=t") 4590 (gtu:GPR (match_operand:GPR 1 "register_operand" "d") 4591 (match_operand:GPR 2 "register_operand" "d")))] 4592 "TARGET_MIPS16" 4593 "sltu\t%2,%1" 4594 [(set_attr "type" "slt") 4595 (set_attr "mode" "<MODE>")]) 4596 4597(define_expand "sgeu" 4598 [(set (match_operand:SI 0 "register_operand") 4599 (geu:SI (match_dup 1) 4600 (match_dup 2)))] 4601 "" 4602 { if (mips_emit_scc (GEU, operands[0])) DONE; else FAIL; }) 4603 4604(define_insn "*sge_<mode>" 4605 [(set (match_operand:GPR 0 "register_operand" "=d") 4606 (geu:GPR (match_operand:GPR 1 "register_operand" "d") 4607 (const_int 1)))] 4608 "!TARGET_MIPS16" 4609 "sltu\t%0,%.,%1" 4610 [(set_attr "type" "slt") 4611 (set_attr "mode" "<MODE>")]) 4612 4613(define_expand "sltu" 4614 [(set (match_operand:SI 0 "register_operand") 4615 (ltu:SI (match_dup 1) 4616 (match_dup 2)))] 4617 "" 4618 { if (mips_emit_scc (LTU, operands[0])) DONE; else FAIL; }) 4619 4620(define_insn "*sltu_<mode>" 4621 [(set (match_operand:GPR 0 "register_operand" "=d") 4622 (ltu:GPR (match_operand:GPR 1 "register_operand" "d") 4623 (match_operand:GPR 2 "arith_operand" "dI")))] 4624 "!TARGET_MIPS16" 4625 "sltu\t%0,%1,%2" 4626 [(set_attr "type" "slt") 4627 (set_attr "mode" "<MODE>")]) 4628 4629(define_insn "*sltu_<mode>_mips16" 4630 [(set (match_operand:GPR 0 "register_operand" "=t,t") 4631 (ltu:GPR (match_operand:GPR 1 "register_operand" "d,d") 4632 (match_operand:GPR 2 "arith_operand" "d,I")))] 4633 "TARGET_MIPS16" 4634 "sltu\t%1,%2" 4635 [(set_attr "type" "slt") 4636 (set_attr "mode" "<MODE>") 4637 (set_attr_alternative "length" 4638 [(const_int 4) 4639 (if_then_else (match_operand 2 "m16_uimm8_1") 4640 (const_int 4) 4641 (const_int 8))])]) 4642 4643(define_expand "sleu" 4644 [(set (match_operand:SI 0 "register_operand") 4645 (leu:SI (match_dup 1) 4646 (match_dup 2)))] 4647 "" 4648 { if (mips_emit_scc (LEU, operands[0])) DONE; else FAIL; }) 4649 4650(define_insn "*sleu_<mode>" 4651 [(set (match_operand:GPR 0 "register_operand" "=d") 4652 (leu:GPR (match_operand:GPR 1 "register_operand" "d") 4653 (match_operand:GPR 2 "sleu_operand" "")))] 4654 "!TARGET_MIPS16" 4655{ 4656 operands[2] = GEN_INT (INTVAL (operands[2]) + 1); 4657 return "sltu\t%0,%1,%2"; 4658} 4659 [(set_attr "type" "slt") 4660 (set_attr "mode" "<MODE>")]) 4661 4662(define_insn "*sleu_<mode>_mips16" 4663 [(set (match_operand:GPR 0 "register_operand" "=t") 4664 (leu:GPR (match_operand:GPR 1 "register_operand" "d") 4665 (match_operand:GPR 2 "sleu_operand" "")))] 4666 "TARGET_MIPS16" 4667{ 4668 operands[2] = GEN_INT (INTVAL (operands[2]) + 1); 4669 return "sltu\t%1,%2"; 4670} 4671 [(set_attr "type" "slt") 4672 (set_attr "mode" "<MODE>") 4673 (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1") 4674 (const_int 4) 4675 (const_int 8)))]) 4676 4677;; 4678;; .................... 4679;; 4680;; FLOATING POINT COMPARISONS 4681;; 4682;; .................... 4683 4684(define_insn "s<code>_<mode>" 4685 [(set (match_operand:CC 0 "register_operand" "=z") 4686 (fcond:CC (match_operand:SCALARF 1 "register_operand" "f") 4687 (match_operand:SCALARF 2 "register_operand" "f")))] 4688 "" 4689 "c.<fcond>.<fmt>\t%Z0%1,%2" 4690 [(set_attr "type" "fcmp") 4691 (set_attr "mode" "FPSW")]) 4692 4693(define_insn "s<code>_<mode>" 4694 [(set (match_operand:CC 0 "register_operand" "=z") 4695 (swapped_fcond:CC (match_operand:SCALARF 1 "register_operand" "f") 4696 (match_operand:SCALARF 2 "register_operand" "f")))] 4697 "" 4698 "c.<swapped_fcond>.<fmt>\t%Z0%2,%1" 4699 [(set_attr "type" "fcmp") 4700 (set_attr "mode" "FPSW")]) 4701 4702;; 4703;; .................... 4704;; 4705;; UNCONDITIONAL BRANCHES 4706;; 4707;; .................... 4708 4709;; Unconditional branches. 4710 4711(define_insn "jump" 4712 [(set (pc) 4713 (label_ref (match_operand 0 "" "")))] 4714 "!TARGET_MIPS16" 4715{ 4716 if (flag_pic) 4717 { 4718 if (get_attr_length (insn) <= 8) 4719 return "%*b\t%l0%/"; 4720 else 4721 { 4722 output_asm_insn (mips_output_load_label (), operands); 4723 return "%*jr\t%@%/%]"; 4724 } 4725 } 4726 else 4727 return "%*j\t%l0%/"; 4728} 4729 [(set_attr "type" "jump") 4730 (set_attr "mode" "none") 4731 (set (attr "length") 4732 ;; We can't use `j' when emitting PIC. Emit a branch if it's 4733 ;; in range, otherwise load the address of the branch target into 4734 ;; $at and then jump to it. 4735 (if_then_else 4736 (ior (eq (symbol_ref "flag_pic") (const_int 0)) 4737 (lt (abs (minus (match_dup 0) 4738 (plus (pc) (const_int 4)))) 4739 (const_int 131072))) 4740 (const_int 4) (const_int 16)))]) 4741 4742;; We need a different insn for the mips16, because a mips16 branch 4743;; does not have a delay slot. 4744 4745(define_insn "" 4746 [(set (pc) 4747 (label_ref (match_operand 0 "" "")))] 4748 "TARGET_MIPS16" 4749 "b\t%l0" 4750 [(set_attr "type" "branch") 4751 (set_attr "mode" "none") 4752 (set_attr "length" "8")]) 4753 4754(define_expand "indirect_jump" 4755 [(set (pc) (match_operand 0 "register_operand"))] 4756 "" 4757{ 4758 operands[0] = force_reg (Pmode, operands[0]); 4759 if (Pmode == SImode) 4760 emit_jump_insn (gen_indirect_jumpsi (operands[0])); 4761 else 4762 emit_jump_insn (gen_indirect_jumpdi (operands[0])); 4763 DONE; 4764}) 4765 4766(define_insn "indirect_jump<mode>" 4767 [(set (pc) (match_operand:P 0 "register_operand" "d"))] 4768 "" 4769 "%*j\t%0%/" 4770 [(set_attr "type" "jump") 4771 (set_attr "mode" "none")]) 4772 4773(define_expand "tablejump" 4774 [(set (pc) 4775 (match_operand 0 "register_operand")) 4776 (use (label_ref (match_operand 1 "")))] 4777 "" 4778{ 4779 if (TARGET_MIPS16) 4780 operands[0] = expand_binop (Pmode, add_optab, 4781 convert_to_mode (Pmode, operands[0], false), 4782 gen_rtx_LABEL_REF (Pmode, operands[1]), 4783 0, 0, OPTAB_WIDEN); 4784 else if (TARGET_GPWORD) 4785 operands[0] = expand_binop (Pmode, add_optab, operands[0], 4786 pic_offset_table_rtx, 0, 0, OPTAB_WIDEN); 4787 4788 if (Pmode == SImode) 4789 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1])); 4790 else 4791 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1])); 4792 DONE; 4793}) 4794 4795(define_insn "tablejump<mode>" 4796 [(set (pc) 4797 (match_operand:P 0 "register_operand" "d")) 4798 (use (label_ref (match_operand 1 "" "")))] 4799 "" 4800 "%*j\t%0%/" 4801 [(set_attr "type" "jump") 4802 (set_attr "mode" "none")]) 4803 4804;; For TARGET_ABICALLS, we save the gp in the jmp_buf as well. 4805;; While it is possible to either pull it off the stack (in the 4806;; o32 case) or recalculate it given t9 and our target label, 4807;; it takes 3 or 4 insns to do so. 4808 4809(define_expand "builtin_setjmp_setup" 4810 [(use (match_operand 0 "register_operand"))] 4811 "TARGET_ABICALLS" 4812{ 4813 rtx addr; 4814 4815 addr = plus_constant (operands[0], GET_MODE_SIZE (Pmode) * 3); 4816 emit_move_insn (gen_rtx_MEM (Pmode, addr), pic_offset_table_rtx); 4817 DONE; 4818}) 4819 4820;; Restore the gp that we saved above. Despite the earlier comment, it seems 4821;; that older code did recalculate the gp from $25. Continue to jump through 4822;; $25 for compatibility (we lose nothing by doing so). 4823 4824(define_expand "builtin_longjmp" 4825 [(use (match_operand 0 "register_operand"))] 4826 "TARGET_ABICALLS" 4827{ 4828 /* The elements of the buffer are, in order: */ 4829 int W = GET_MODE_SIZE (Pmode); 4830 rtx fp = gen_rtx_MEM (Pmode, operands[0]); 4831 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 1*W)); 4832 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2*W)); 4833 rtx gpv = gen_rtx_MEM (Pmode, plus_constant (operands[0], 3*W)); 4834 rtx pv = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM); 4835 /* Use gen_raw_REG to avoid being given pic_offset_table_rtx. 4836 The target is bound to be using $28 as the global pointer 4837 but the current function might not be. */ 4838 rtx gp = gen_raw_REG (Pmode, GLOBAL_POINTER_REGNUM); 4839 4840 /* This bit is similar to expand_builtin_longjmp except that it 4841 restores $gp as well. */ 4842 emit_move_insn (hard_frame_pointer_rtx, fp); 4843 emit_move_insn (pv, lab); 4844 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX); 4845 emit_move_insn (gp, gpv); 4846 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx)); 4847 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx)); 4848 emit_insn (gen_rtx_USE (VOIDmode, gp)); 4849 emit_indirect_jump (pv); 4850 DONE; 4851}) 4852 4853;; 4854;; .................... 4855;; 4856;; Function prologue/epilogue 4857;; 4858;; .................... 4859;; 4860 4861(define_expand "prologue" 4862 [(const_int 1)] 4863 "" 4864{ 4865 mips_expand_prologue (); 4866 DONE; 4867}) 4868 4869;; Block any insns from being moved before this point, since the 4870;; profiling call to mcount can use various registers that aren't 4871;; saved or used to pass arguments. 4872 4873(define_insn "blockage" 4874 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)] 4875 "" 4876 "" 4877 [(set_attr "type" "unknown") 4878 (set_attr "mode" "none") 4879 (set_attr "length" "0")]) 4880 4881(define_expand "epilogue" 4882 [(const_int 2)] 4883 "" 4884{ 4885 mips_expand_epilogue (false); 4886 DONE; 4887}) 4888 4889(define_expand "sibcall_epilogue" 4890 [(const_int 2)] 4891 "" 4892{ 4893 mips_expand_epilogue (true); 4894 DONE; 4895}) 4896 4897;; Trivial return. Make it look like a normal return insn as that 4898;; allows jump optimizations to work better. 4899 4900(define_insn "return" 4901 [(return)] 4902 "mips_can_use_return_insn ()" 4903 "%*j\t$31%/" 4904 [(set_attr "type" "jump") 4905 (set_attr "mode" "none")]) 4906 4907;; Normal return. 4908 4909(define_insn "return_internal" 4910 [(return) 4911 (use (match_operand 0 "pmode_register_operand" ""))] 4912 "" 4913 "%*j\t%0%/" 4914 [(set_attr "type" "jump") 4915 (set_attr "mode" "none")]) 4916 4917;; This is used in compiling the unwind routines. 4918(define_expand "eh_return" 4919 [(use (match_operand 0 "general_operand"))] 4920 "" 4921{ 4922 enum machine_mode gpr_mode = TARGET_64BIT ? DImode : SImode; 4923 4924 if (GET_MODE (operands[0]) != gpr_mode) 4925 operands[0] = convert_to_mode (gpr_mode, operands[0], 0); 4926 if (TARGET_64BIT) 4927 emit_insn (gen_eh_set_lr_di (operands[0])); 4928 else 4929 emit_insn (gen_eh_set_lr_si (operands[0])); 4930 4931 DONE; 4932}) 4933 4934;; Clobber the return address on the stack. We can't expand this 4935;; until we know where it will be put in the stack frame. 4936 4937(define_insn "eh_set_lr_si" 4938 [(unspec [(match_operand:SI 0 "register_operand" "d")] UNSPEC_EH_RETURN) 4939 (clobber (match_scratch:SI 1 "=&d"))] 4940 "! TARGET_64BIT" 4941 "#") 4942 4943(define_insn "eh_set_lr_di" 4944 [(unspec [(match_operand:DI 0 "register_operand" "d")] UNSPEC_EH_RETURN) 4945 (clobber (match_scratch:DI 1 "=&d"))] 4946 "TARGET_64BIT" 4947 "#") 4948 4949(define_split 4950 [(unspec [(match_operand 0 "register_operand")] UNSPEC_EH_RETURN) 4951 (clobber (match_scratch 1))] 4952 "reload_completed && !TARGET_DEBUG_D_MODE" 4953 [(const_int 0)] 4954{ 4955 mips_set_return_address (operands[0], operands[1]); 4956 DONE; 4957}) 4958 4959(define_insn_and_split "exception_receiver" 4960 [(set (reg:SI 28) 4961 (unspec_volatile:SI [(const_int 0)] UNSPEC_EH_RECEIVER))] 4962 "TARGET_ABICALLS && TARGET_OLDABI" 4963 "#" 4964 "&& reload_completed" 4965 [(const_int 0)] 4966{ 4967 mips_restore_gp (); 4968 DONE; 4969} 4970 [(set_attr "type" "load") 4971 (set_attr "length" "12")]) 4972 4973;; 4974;; .................... 4975;; 4976;; FUNCTION CALLS 4977;; 4978;; .................... 4979 4980;; Instructions to load a call address from the GOT. The address might 4981;; point to a function or to a lazy binding stub. In the latter case, 4982;; the stub will use the dynamic linker to resolve the function, which 4983;; in turn will change the GOT entry to point to the function's real 4984;; address. 4985;; 4986;; This means that every call, even pure and constant ones, can 4987;; potentially modify the GOT entry. And once a stub has been called, 4988;; we must not call it again. 4989;; 4990;; We represent this restriction using an imaginary fixed register that 4991;; acts like a GOT version number. By making the register call-clobbered, 4992;; we tell the target-independent code that the address could be changed 4993;; by any call insn. 4994(define_insn "load_call<mode>" 4995 [(set (match_operand:P 0 "register_operand" "=c") 4996 (unspec:P [(match_operand:P 1 "register_operand" "r") 4997 (match_operand:P 2 "immediate_operand" "") 4998 (reg:P FAKE_CALL_REGNO)] 4999 UNSPEC_LOAD_CALL))] 5000 "TARGET_ABICALLS" 5001 "<load>\t%0,%R2(%1)" 5002 [(set_attr "type" "load") 5003 (set_attr "mode" "<MODE>") 5004 (set_attr "length" "4")]) 5005 5006;; Sibling calls. All these patterns use jump instructions. 5007 5008;; If TARGET_SIBCALLS, call_insn_operand will only accept constant 5009;; addresses if a direct jump is acceptable. Since the 'S' constraint 5010;; is defined in terms of call_insn_operand, the same is true of the 5011;; constraints. 5012 5013;; When we use an indirect jump, we need a register that will be 5014;; preserved by the epilogue. Since TARGET_ABICALLS forces us to 5015;; use $25 for this purpose -- and $25 is never clobbered by the 5016;; epilogue -- we might as well use it for !TARGET_ABICALLS as well. 5017 5018(define_expand "sibcall" 5019 [(parallel [(call (match_operand 0 "") 5020 (match_operand 1 "")) 5021 (use (match_operand 2 "")) ;; next_arg_reg 5022 (use (match_operand 3 ""))])] ;; struct_value_size_rtx 5023 "TARGET_SIBCALLS" 5024{ 5025 mips_expand_call (0, XEXP (operands[0], 0), operands[1], operands[2], true); 5026 DONE; 5027}) 5028 5029(define_insn "sibcall_internal" 5030 [(call (mem:SI (match_operand 0 "call_insn_operand" "j,S")) 5031 (match_operand 1 "" ""))] 5032 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)" 5033 "@ 5034 %*jr\t%0%/ 5035 %*j\t%0%/" 5036 [(set_attr "type" "call")]) 5037 5038(define_expand "sibcall_value" 5039 [(parallel [(set (match_operand 0 "") 5040 (call (match_operand 1 "") 5041 (match_operand 2 ""))) 5042 (use (match_operand 3 ""))])] ;; next_arg_reg 5043 "TARGET_SIBCALLS" 5044{ 5045 mips_expand_call (operands[0], XEXP (operands[1], 0), 5046 operands[2], operands[3], true); 5047 DONE; 5048}) 5049 5050(define_insn "sibcall_value_internal" 5051 [(set (match_operand 0 "register_operand" "=df,df") 5052 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S")) 5053 (match_operand 2 "" "")))] 5054 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)" 5055 "@ 5056 %*jr\t%1%/ 5057 %*j\t%1%/" 5058 [(set_attr "type" "call")]) 5059 5060(define_insn "sibcall_value_multiple_internal" 5061 [(set (match_operand 0 "register_operand" "=df,df") 5062 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S")) 5063 (match_operand 2 "" ""))) 5064 (set (match_operand 3 "register_operand" "=df,df") 5065 (call (mem:SI (match_dup 1)) 5066 (match_dup 2)))] 5067 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)" 5068 "@ 5069 %*jr\t%1%/ 5070 %*j\t%1%/" 5071 [(set_attr "type" "call")]) 5072 5073(define_expand "call" 5074 [(parallel [(call (match_operand 0 "") 5075 (match_operand 1 "")) 5076 (use (match_operand 2 "")) ;; next_arg_reg 5077 (use (match_operand 3 ""))])] ;; struct_value_size_rtx 5078 "" 5079{ 5080 mips_expand_call (0, XEXP (operands[0], 0), operands[1], operands[2], false); 5081 DONE; 5082}) 5083 5084;; This instruction directly corresponds to an assembly-language "jal". 5085;; There are four cases: 5086;; 5087;; - -mno-abicalls: 5088;; Both symbolic and register destinations are OK. The pattern 5089;; always expands to a single mips instruction. 5090;; 5091;; - -mabicalls/-mno-explicit-relocs: 5092;; Again, both symbolic and register destinations are OK. 5093;; The call is treated as a multi-instruction black box. 5094;; 5095;; - -mabicalls/-mexplicit-relocs with n32 or n64: 5096;; Only "jal $25" is allowed. This expands to a single "jalr $25" 5097;; instruction. 5098;; 5099;; - -mabicalls/-mexplicit-relocs with o32 or o64: 5100;; Only "jal $25" is allowed. The call is actually two instructions: 5101;; "jalr $25" followed by an insn to reload $gp. 5102;; 5103;; In the last case, we can generate the individual instructions with 5104;; a define_split. There are several things to be wary of: 5105;; 5106;; - We can't expose the load of $gp before reload. If we did, 5107;; it might get removed as dead, but reload can introduce new 5108;; uses of $gp by rematerializing constants. 5109;; 5110;; - We shouldn't restore $gp after calls that never return. 5111;; It isn't valid to insert instructions between a noreturn 5112;; call and the following barrier. 5113;; 5114;; - The splitter deliberately changes the liveness of $gp. The unsplit 5115;; instruction preserves $gp and so have no effect on its liveness. 5116;; But once we generate the separate insns, it becomes obvious that 5117;; $gp is not live on entry to the call. 5118;; 5119;; ??? The operands[2] = insn check is a hack to make the original insn 5120;; available to the splitter. 5121(define_insn_and_split "call_internal" 5122 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S")) 5123 (match_operand 1 "" "")) 5124 (clobber (reg:SI 31))] 5125 "" 5126 { return TARGET_SPLIT_CALLS ? "#" : "%*jal\t%0%/"; } 5127 "reload_completed && TARGET_SPLIT_CALLS && (operands[2] = insn)" 5128 [(const_int 0)] 5129{ 5130 emit_call_insn (gen_call_split (operands[0], operands[1])); 5131 if (!find_reg_note (operands[2], REG_NORETURN, 0)) 5132 mips_restore_gp (); 5133 DONE; 5134} 5135 [(set_attr "jal" "indirect,direct") 5136 (set_attr "extended_mips16" "no,yes")]) 5137 5138(define_insn "call_split" 5139 [(call (mem:SI (match_operand 0 "call_insn_operand" "c")) 5140 (match_operand 1 "" "")) 5141 (clobber (reg:SI 31)) 5142 (clobber (reg:SI 28))] 5143 "TARGET_SPLIT_CALLS" 5144 "%*jalr\t%0%/" 5145 [(set_attr "type" "call")]) 5146 5147(define_expand "call_value" 5148 [(parallel [(set (match_operand 0 "") 5149 (call (match_operand 1 "") 5150 (match_operand 2 ""))) 5151 (use (match_operand 3 ""))])] ;; next_arg_reg 5152 "" 5153{ 5154 mips_expand_call (operands[0], XEXP (operands[1], 0), 5155 operands[2], operands[3], false); 5156 DONE; 5157}) 5158 5159;; See comment for call_internal. 5160(define_insn_and_split "call_value_internal" 5161 [(set (match_operand 0 "register_operand" "=df,df") 5162 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S")) 5163 (match_operand 2 "" ""))) 5164 (clobber (reg:SI 31))] 5165 "" 5166 { return TARGET_SPLIT_CALLS ? "#" : "%*jal\t%1%/"; } 5167 "reload_completed && TARGET_SPLIT_CALLS && (operands[3] = insn)" 5168 [(const_int 0)] 5169{ 5170 emit_call_insn (gen_call_value_split (operands[0], operands[1], 5171 operands[2])); 5172 if (!find_reg_note (operands[3], REG_NORETURN, 0)) 5173 mips_restore_gp (); 5174 DONE; 5175} 5176 [(set_attr "jal" "indirect,direct") 5177 (set_attr "extended_mips16" "no,yes")]) 5178 5179(define_insn "call_value_split" 5180 [(set (match_operand 0 "register_operand" "=df") 5181 (call (mem:SI (match_operand 1 "call_insn_operand" "c")) 5182 (match_operand 2 "" ""))) 5183 (clobber (reg:SI 31)) 5184 (clobber (reg:SI 28))] 5185 "TARGET_SPLIT_CALLS" 5186 "%*jalr\t%1%/" 5187 [(set_attr "type" "call")]) 5188 5189;; See comment for call_internal. 5190(define_insn_and_split "call_value_multiple_internal" 5191 [(set (match_operand 0 "register_operand" "=df,df") 5192 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S")) 5193 (match_operand 2 "" ""))) 5194 (set (match_operand 3 "register_operand" "=df,df") 5195 (call (mem:SI (match_dup 1)) 5196 (match_dup 2))) 5197 (clobber (reg:SI 31))] 5198 "" 5199 { return TARGET_SPLIT_CALLS ? "#" : "%*jal\t%1%/"; } 5200 "reload_completed && TARGET_SPLIT_CALLS && (operands[4] = insn)" 5201 [(const_int 0)] 5202{ 5203 emit_call_insn (gen_call_value_multiple_split (operands[0], operands[1], 5204 operands[2], operands[3])); 5205 if (!find_reg_note (operands[4], REG_NORETURN, 0)) 5206 mips_restore_gp (); 5207 DONE; 5208} 5209 [(set_attr "jal" "indirect,direct") 5210 (set_attr "extended_mips16" "no,yes")]) 5211 5212(define_insn "call_value_multiple_split" 5213 [(set (match_operand 0 "register_operand" "=df") 5214 (call (mem:SI (match_operand 1 "call_insn_operand" "c")) 5215 (match_operand 2 "" ""))) 5216 (set (match_operand 3 "register_operand" "=df") 5217 (call (mem:SI (match_dup 1)) 5218 (match_dup 2))) 5219 (clobber (reg:SI 31)) 5220 (clobber (reg:SI 28))] 5221 "TARGET_SPLIT_CALLS" 5222 "%*jalr\t%1%/" 5223 [(set_attr "type" "call")]) 5224 5225;; Call subroutine returning any type. 5226 5227(define_expand "untyped_call" 5228 [(parallel [(call (match_operand 0 "") 5229 (const_int 0)) 5230 (match_operand 1 "") 5231 (match_operand 2 "")])] 5232 "" 5233{ 5234 int i; 5235 5236 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx)); 5237 5238 for (i = 0; i < XVECLEN (operands[2], 0); i++) 5239 { 5240 rtx set = XVECEXP (operands[2], 0, i); 5241 emit_move_insn (SET_DEST (set), SET_SRC (set)); 5242 } 5243 5244 emit_insn (gen_blockage ()); 5245 DONE; 5246}) 5247 5248;; 5249;; .................... 5250;; 5251;; MISC. 5252;; 5253;; .................... 5254;; 5255 5256 5257(define_insn "prefetch" 5258 [(prefetch (match_operand:QI 0 "address_operand" "p") 5259 (match_operand 1 "const_int_operand" "n") 5260 (match_operand 2 "const_int_operand" "n"))] 5261 "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS" 5262{ 5263 operands[1] = mips_prefetch_cookie (operands[1], operands[2]); 5264 return "pref\t%1,%a0"; 5265} 5266 [(set_attr "type" "prefetch")]) 5267 5268(define_insn "*prefetch_indexed_<mode>" 5269 [(prefetch (plus:P (match_operand:P 0 "register_operand" "d") 5270 (match_operand:P 1 "register_operand" "d")) 5271 (match_operand 2 "const_int_operand" "n") 5272 (match_operand 3 "const_int_operand" "n"))] 5273 "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" 5274{ 5275 operands[2] = mips_prefetch_cookie (operands[2], operands[3]); 5276 return "prefx\t%2,%1(%0)"; 5277} 5278 [(set_attr "type" "prefetchx")]) 5279 5280(define_insn "nop" 5281 [(const_int 0)] 5282 "" 5283 "%(nop%)" 5284 [(set_attr "type" "nop") 5285 (set_attr "mode" "none")]) 5286 5287;; Like nop, but commented out when outside a .set noreorder block. 5288(define_insn "hazard_nop" 5289 [(const_int 1)] 5290 "" 5291 { 5292 if (set_noreorder) 5293 return "nop"; 5294 else 5295 return "#nop"; 5296 } 5297 [(set_attr "type" "nop")]) 5298 5299;; MIPS4 Conditional move instructions. 5300 5301(define_insn "*mov<GPR:mode>_on_<MOVECC:mode>" 5302 [(set (match_operand:GPR 0 "register_operand" "=d,d") 5303 (if_then_else:GPR 5304 (match_operator:MOVECC 4 "equality_operator" 5305 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>") 5306 (const_int 0)]) 5307 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0") 5308 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))] 5309 "ISA_HAS_CONDMOVE" 5310 "@ 5311 mov%T4\t%0,%z2,%1 5312 mov%t4\t%0,%z3,%1" 5313 [(set_attr "type" "condmove") 5314 (set_attr "mode" "<GPR:MODE>")]) 5315 5316(define_insn "*mov<SCALARF:mode>_on_<MOVECC:mode>" 5317 [(set (match_operand:SCALARF 0 "register_operand" "=f,f") 5318 (if_then_else:SCALARF 5319 (match_operator:MOVECC 4 "equality_operator" 5320 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>") 5321 (const_int 0)]) 5322 (match_operand:SCALARF 2 "register_operand" "f,0") 5323 (match_operand:SCALARF 3 "register_operand" "0,f")))] 5324 "ISA_HAS_CONDMOVE" 5325 "@ 5326 mov%T4.<fmt>\t%0,%2,%1 5327 mov%t4.<fmt>\t%0,%3,%1" 5328 [(set_attr "type" "condmove") 5329 (set_attr "mode" "<SCALARF:MODE>")]) 5330 5331;; These are the main define_expand's used to make conditional moves. 5332 5333(define_expand "mov<mode>cc" 5334 [(set (match_dup 4) (match_operand 1 "comparison_operator")) 5335 (set (match_operand:GPR 0 "register_operand") 5336 (if_then_else:GPR (match_dup 5) 5337 (match_operand:GPR 2 "reg_or_0_operand") 5338 (match_operand:GPR 3 "reg_or_0_operand")))] 5339 "ISA_HAS_CONDMOVE" 5340{ 5341 gen_conditional_move (operands); 5342 DONE; 5343}) 5344 5345(define_expand "mov<mode>cc" 5346 [(set (match_dup 4) (match_operand 1 "comparison_operator")) 5347 (set (match_operand:SCALARF 0 "register_operand") 5348 (if_then_else:SCALARF (match_dup 5) 5349 (match_operand:SCALARF 2 "register_operand") 5350 (match_operand:SCALARF 3 "register_operand")))] 5351 "ISA_HAS_CONDMOVE" 5352{ 5353 gen_conditional_move (operands); 5354 DONE; 5355}) 5356 5357;; 5358;; .................... 5359;; 5360;; mips16 inline constant tables 5361;; 5362;; .................... 5363;; 5364 5365(define_insn "consttable_int" 5366 [(unspec_volatile [(match_operand 0 "consttable_operand" "") 5367 (match_operand 1 "const_int_operand" "")] 5368 UNSPEC_CONSTTABLE_INT)] 5369 "TARGET_MIPS16" 5370{ 5371 assemble_integer (operands[0], INTVAL (operands[1]), 5372 BITS_PER_UNIT * INTVAL (operands[1]), 1); 5373 return ""; 5374} 5375 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))]) 5376 5377(define_insn "consttable_float" 5378 [(unspec_volatile [(match_operand 0 "consttable_operand" "")] 5379 UNSPEC_CONSTTABLE_FLOAT)] 5380 "TARGET_MIPS16" 5381{ 5382 REAL_VALUE_TYPE d; 5383 5384 gcc_assert (GET_CODE (operands[0]) == CONST_DOUBLE); 5385 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]); 5386 assemble_real (d, GET_MODE (operands[0]), 5387 GET_MODE_BITSIZE (GET_MODE (operands[0]))); 5388 return ""; 5389} 5390 [(set (attr "length") 5391 (symbol_ref "GET_MODE_SIZE (GET_MODE (operands[0]))"))]) 5392 5393(define_insn "align" 5394 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPEC_ALIGN)] 5395 "" 5396 ".align\t%0" 5397 [(set (attr "length") (symbol_ref "(1 << INTVAL (operands[0])) - 1"))]) 5398 5399(define_split 5400 [(match_operand 0 "small_data_pattern")] 5401 "reload_completed" 5402 [(match_dup 0)] 5403 { operands[0] = mips_rewrite_small_data (operands[0]); }) 5404 5405; Thread-Local Storage 5406 5407; The TLS base pointer is accessed via "rdhwr $v1, $29". No current 5408; MIPS architecture defines this register, and no current 5409; implementation provides it; instead, any OS which supports TLS is 5410; expected to trap and emulate this instruction. rdhwr is part of the 5411; MIPS 32r2 specification, but we use it on any architecture because 5412; we expect it to be emulated. Use .set to force the assembler to 5413; accept it. 5414 5415(define_insn "tls_get_tp_<mode>" 5416 [(set (match_operand:P 0 "register_operand" "=v") 5417 (unspec:P [(const_int 0)] 5418 UNSPEC_TLS_GET_TP))] 5419 "HAVE_AS_TLS && !TARGET_MIPS16" 5420 ".set\tpush\;.set\tmips32r2\t\;rdhwr\t%0,$29\;.set\tpop" 5421 [(set_attr "type" "unknown") 5422 (set_attr "mode" "<MODE>")]) 5423 5424; The MIPS Paired-Single Floating Point and MIPS-3D Instructions. 5425 5426(include "mips-ps-3d.md") 5427 5428; The MIPS DSP Instructions. 5429 5430(include "mips-dsp.md") 5431