1 /* Analyze RTL for C-Compiler
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
10 version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
20 02110-1301, USA. */
21
22
23 #include "config.h"
24 #include "system.h"
25 #include "coretypes.h"
26 #include "tm.h"
27 #include "toplev.h"
28 #include "rtl.h"
29 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "recog.h"
32 #include "target.h"
33 #include "output.h"
34 #include "tm_p.h"
35 #include "flags.h"
36 #include "real.h"
37 #include "regs.h"
38 #include "function.h"
39
40 /* Forward declarations */
41 static int global_reg_mentioned_p_1 (rtx *, void *);
42 static void set_of_1 (rtx, rtx, void *);
43 static bool covers_regno_p (rtx, unsigned int);
44 static bool covers_regno_no_parallel_p (rtx, unsigned int);
45 static int rtx_referenced_p_1 (rtx *, void *);
46 static int computed_jump_p_1 (rtx);
47 static void parms_set (rtx, rtx, void *);
48
49 static unsigned HOST_WIDE_INT cached_nonzero_bits (rtx, enum machine_mode,
50 rtx, enum machine_mode,
51 unsigned HOST_WIDE_INT);
52 static unsigned HOST_WIDE_INT nonzero_bits1 (rtx, enum machine_mode, rtx,
53 enum machine_mode,
54 unsigned HOST_WIDE_INT);
55 static unsigned int cached_num_sign_bit_copies (rtx, enum machine_mode, rtx,
56 enum machine_mode,
57 unsigned int);
58 static unsigned int num_sign_bit_copies1 (rtx, enum machine_mode, rtx,
59 enum machine_mode, unsigned int);
60
61 /* Offset of the first 'e', 'E' or 'V' operand for each rtx code, or
62 -1 if a code has no such operand. */
63 static int non_rtx_starting_operands[NUM_RTX_CODE];
64
65 /* Bit flags that specify the machine subtype we are compiling for.
66 Bits are tested using macros TARGET_... defined in the tm.h file
67 and set by `-m...' switches. Must be defined in rtlanal.c. */
68
69 int target_flags;
70
71 /* Return 1 if the value of X is unstable
72 (would be different at a different point in the program).
73 The frame pointer, arg pointer, etc. are considered stable
74 (within one function) and so is anything marked `unchanging'. */
75
76 int
rtx_unstable_p(rtx x)77 rtx_unstable_p (rtx x)
78 {
79 RTX_CODE code = GET_CODE (x);
80 int i;
81 const char *fmt;
82
83 switch (code)
84 {
85 case MEM:
86 return !MEM_READONLY_P (x) || rtx_unstable_p (XEXP (x, 0));
87
88 case CONST:
89 case CONST_INT:
90 case CONST_DOUBLE:
91 case CONST_VECTOR:
92 case SYMBOL_REF:
93 case LABEL_REF:
94 return 0;
95
96 case REG:
97 /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */
98 if (x == frame_pointer_rtx || x == hard_frame_pointer_rtx
99 /* The arg pointer varies if it is not a fixed register. */
100 || (x == arg_pointer_rtx && fixed_regs[ARG_POINTER_REGNUM]))
101 return 0;
102 #ifndef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
103 /* ??? When call-clobbered, the value is stable modulo the restore
104 that must happen after a call. This currently screws up local-alloc
105 into believing that the restore is not needed. */
106 if (x == pic_offset_table_rtx)
107 return 0;
108 #endif
109 return 1;
110
111 case ASM_OPERANDS:
112 if (MEM_VOLATILE_P (x))
113 return 1;
114
115 /* Fall through. */
116
117 default:
118 break;
119 }
120
121 fmt = GET_RTX_FORMAT (code);
122 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
123 if (fmt[i] == 'e')
124 {
125 if (rtx_unstable_p (XEXP (x, i)))
126 return 1;
127 }
128 else if (fmt[i] == 'E')
129 {
130 int j;
131 for (j = 0; j < XVECLEN (x, i); j++)
132 if (rtx_unstable_p (XVECEXP (x, i, j)))
133 return 1;
134 }
135
136 return 0;
137 }
138
139 /* Return 1 if X has a value that can vary even between two
140 executions of the program. 0 means X can be compared reliably
141 against certain constants or near-constants.
142 FOR_ALIAS is nonzero if we are called from alias analysis; if it is
143 zero, we are slightly more conservative.
144 The frame pointer and the arg pointer are considered constant. */
145
146 int
rtx_varies_p(rtx x,int for_alias)147 rtx_varies_p (rtx x, int for_alias)
148 {
149 RTX_CODE code;
150 int i;
151 const char *fmt;
152
153 if (!x)
154 return 0;
155
156 code = GET_CODE (x);
157 switch (code)
158 {
159 case MEM:
160 return !MEM_READONLY_P (x) || rtx_varies_p (XEXP (x, 0), for_alias);
161
162 case CONST:
163 case CONST_INT:
164 case CONST_DOUBLE:
165 case CONST_VECTOR:
166 case SYMBOL_REF:
167 case LABEL_REF:
168 return 0;
169
170 case REG:
171 /* Note that we have to test for the actual rtx used for the frame
172 and arg pointers and not just the register number in case we have
173 eliminated the frame and/or arg pointer and are using it
174 for pseudos. */
175 if (x == frame_pointer_rtx || x == hard_frame_pointer_rtx
176 /* The arg pointer varies if it is not a fixed register. */
177 || (x == arg_pointer_rtx && fixed_regs[ARG_POINTER_REGNUM]))
178 return 0;
179 if (x == pic_offset_table_rtx
180 #ifdef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
181 /* ??? When call-clobbered, the value is stable modulo the restore
182 that must happen after a call. This currently screws up
183 local-alloc into believing that the restore is not needed, so we
184 must return 0 only if we are called from alias analysis. */
185 && for_alias
186 #endif
187 )
188 return 0;
189 return 1;
190
191 case LO_SUM:
192 /* The operand 0 of a LO_SUM is considered constant
193 (in fact it is related specifically to operand 1)
194 during alias analysis. */
195 return (! for_alias && rtx_varies_p (XEXP (x, 0), for_alias))
196 || rtx_varies_p (XEXP (x, 1), for_alias);
197
198 case ASM_OPERANDS:
199 if (MEM_VOLATILE_P (x))
200 return 1;
201
202 /* Fall through. */
203
204 default:
205 break;
206 }
207
208 fmt = GET_RTX_FORMAT (code);
209 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
210 if (fmt[i] == 'e')
211 {
212 if (rtx_varies_p (XEXP (x, i), for_alias))
213 return 1;
214 }
215 else if (fmt[i] == 'E')
216 {
217 int j;
218 for (j = 0; j < XVECLEN (x, i); j++)
219 if (rtx_varies_p (XVECEXP (x, i, j), for_alias))
220 return 1;
221 }
222
223 return 0;
224 }
225
226 /* Return nonzero if the use of X as an address in a MEM can cause a trap.
227 MODE is the mode of the MEM (not that of X) and UNALIGNED_MEMS controls
228 whether nonzero is returned for unaligned memory accesses on strict
229 alignment machines. */
230
231 static int
rtx_addr_can_trap_p_1(rtx x,enum machine_mode mode,bool unaligned_mems)232 rtx_addr_can_trap_p_1 (rtx x, enum machine_mode mode, bool unaligned_mems)
233 {
234 enum rtx_code code = GET_CODE (x);
235
236 switch (code)
237 {
238 case SYMBOL_REF:
239 return SYMBOL_REF_WEAK (x);
240
241 case LABEL_REF:
242 return 0;
243
244 case REG:
245 /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */
246 if (x == frame_pointer_rtx || x == hard_frame_pointer_rtx
247 || x == stack_pointer_rtx
248 /* The arg pointer varies if it is not a fixed register. */
249 || (x == arg_pointer_rtx && fixed_regs[ARG_POINTER_REGNUM]))
250 return 0;
251 /* All of the virtual frame registers are stack references. */
252 if (REGNO (x) >= FIRST_VIRTUAL_REGISTER
253 && REGNO (x) <= LAST_VIRTUAL_REGISTER)
254 return 0;
255 return 1;
256
257 case CONST:
258 return rtx_addr_can_trap_p_1 (XEXP (x, 0), mode, unaligned_mems);
259
260 case PLUS:
261 /* An address is assumed not to trap if:
262 - it is an address that can't trap plus a constant integer,
263 with the proper remainder modulo the mode size if we are
264 considering unaligned memory references. */
265 if (!rtx_addr_can_trap_p_1 (XEXP (x, 0), mode, unaligned_mems)
266 && GET_CODE (XEXP (x, 1)) == CONST_INT)
267 {
268 HOST_WIDE_INT offset;
269
270 if (!STRICT_ALIGNMENT
271 || !unaligned_mems
272 || GET_MODE_SIZE (mode) == 0)
273 return 0;
274
275 offset = INTVAL (XEXP (x, 1));
276
277 #ifdef SPARC_STACK_BOUNDARY_HACK
278 /* ??? The SPARC port may claim a STACK_BOUNDARY higher than
279 the real alignment of %sp. However, when it does this, the
280 alignment of %sp+STACK_POINTER_OFFSET is STACK_BOUNDARY. */
281 if (SPARC_STACK_BOUNDARY_HACK
282 && (XEXP (x, 0) == stack_pointer_rtx
283 || XEXP (x, 0) == hard_frame_pointer_rtx))
284 offset -= STACK_POINTER_OFFSET;
285 #endif
286
287 return offset % GET_MODE_SIZE (mode) != 0;
288 }
289
290 /* - or it is the pic register plus a constant. */
291 if (XEXP (x, 0) == pic_offset_table_rtx && CONSTANT_P (XEXP (x, 1)))
292 return 0;
293
294 return 1;
295
296 case LO_SUM:
297 case PRE_MODIFY:
298 return rtx_addr_can_trap_p_1 (XEXP (x, 1), mode, unaligned_mems);
299
300 case PRE_DEC:
301 case PRE_INC:
302 case POST_DEC:
303 case POST_INC:
304 case POST_MODIFY:
305 return rtx_addr_can_trap_p_1 (XEXP (x, 0), mode, unaligned_mems);
306
307 default:
308 break;
309 }
310
311 /* If it isn't one of the case above, it can cause a trap. */
312 return 1;
313 }
314
315 /* Return nonzero if the use of X as an address in a MEM can cause a trap. */
316
317 int
rtx_addr_can_trap_p(rtx x)318 rtx_addr_can_trap_p (rtx x)
319 {
320 return rtx_addr_can_trap_p_1 (x, VOIDmode, false);
321 }
322
323 /* Return true if X is an address that is known to not be zero. */
324
325 bool
nonzero_address_p(rtx x)326 nonzero_address_p (rtx x)
327 {
328 enum rtx_code code = GET_CODE (x);
329
330 switch (code)
331 {
332 case SYMBOL_REF:
333 return !SYMBOL_REF_WEAK (x);
334
335 case LABEL_REF:
336 return true;
337
338 case REG:
339 /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */
340 if (x == frame_pointer_rtx || x == hard_frame_pointer_rtx
341 || x == stack_pointer_rtx
342 || (x == arg_pointer_rtx && fixed_regs[ARG_POINTER_REGNUM]))
343 return true;
344 /* All of the virtual frame registers are stack references. */
345 if (REGNO (x) >= FIRST_VIRTUAL_REGISTER
346 && REGNO (x) <= LAST_VIRTUAL_REGISTER)
347 return true;
348 return false;
349
350 case CONST:
351 return nonzero_address_p (XEXP (x, 0));
352
353 case PLUS:
354 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
355 {
356 /* Pointers aren't allowed to wrap. If we've got a register
357 that is known to be a pointer, and a positive offset, then
358 the composite can't be zero. */
359 if (INTVAL (XEXP (x, 1)) > 0
360 && REG_P (XEXP (x, 0))
361 && REG_POINTER (XEXP (x, 0)))
362 return true;
363
364 return nonzero_address_p (XEXP (x, 0));
365 }
366 /* Handle PIC references. */
367 else if (XEXP (x, 0) == pic_offset_table_rtx
368 && CONSTANT_P (XEXP (x, 1)))
369 return true;
370 return false;
371
372 case PRE_MODIFY:
373 /* Similar to the above; allow positive offsets. Further, since
374 auto-inc is only allowed in memories, the register must be a
375 pointer. */
376 if (GET_CODE (XEXP (x, 1)) == CONST_INT
377 && INTVAL (XEXP (x, 1)) > 0)
378 return true;
379 return nonzero_address_p (XEXP (x, 0));
380
381 case PRE_INC:
382 /* Similarly. Further, the offset is always positive. */
383 return true;
384
385 case PRE_DEC:
386 case POST_DEC:
387 case POST_INC:
388 case POST_MODIFY:
389 return nonzero_address_p (XEXP (x, 0));
390
391 case LO_SUM:
392 return nonzero_address_p (XEXP (x, 1));
393
394 default:
395 break;
396 }
397
398 /* If it isn't one of the case above, might be zero. */
399 return false;
400 }
401
402 /* Return 1 if X refers to a memory location whose address
403 cannot be compared reliably with constant addresses,
404 or if X refers to a BLKmode memory object.
405 FOR_ALIAS is nonzero if we are called from alias analysis; if it is
406 zero, we are slightly more conservative. */
407
408 int
rtx_addr_varies_p(rtx x,int for_alias)409 rtx_addr_varies_p (rtx x, int for_alias)
410 {
411 enum rtx_code code;
412 int i;
413 const char *fmt;
414
415 if (x == 0)
416 return 0;
417
418 code = GET_CODE (x);
419 if (code == MEM)
420 return GET_MODE (x) == BLKmode || rtx_varies_p (XEXP (x, 0), for_alias);
421
422 fmt = GET_RTX_FORMAT (code);
423 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
424 if (fmt[i] == 'e')
425 {
426 if (rtx_addr_varies_p (XEXP (x, i), for_alias))
427 return 1;
428 }
429 else if (fmt[i] == 'E')
430 {
431 int j;
432 for (j = 0; j < XVECLEN (x, i); j++)
433 if (rtx_addr_varies_p (XVECEXP (x, i, j), for_alias))
434 return 1;
435 }
436 return 0;
437 }
438
439 /* Return the value of the integer term in X, if one is apparent;
440 otherwise return 0.
441 Only obvious integer terms are detected.
442 This is used in cse.c with the `related_value' field. */
443
444 HOST_WIDE_INT
get_integer_term(rtx x)445 get_integer_term (rtx x)
446 {
447 if (GET_CODE (x) == CONST)
448 x = XEXP (x, 0);
449
450 if (GET_CODE (x) == MINUS
451 && GET_CODE (XEXP (x, 1)) == CONST_INT)
452 return - INTVAL (XEXP (x, 1));
453 if (GET_CODE (x) == PLUS
454 && GET_CODE (XEXP (x, 1)) == CONST_INT)
455 return INTVAL (XEXP (x, 1));
456 return 0;
457 }
458
459 /* If X is a constant, return the value sans apparent integer term;
460 otherwise return 0.
461 Only obvious integer terms are detected. */
462
463 rtx
get_related_value(rtx x)464 get_related_value (rtx x)
465 {
466 if (GET_CODE (x) != CONST)
467 return 0;
468 x = XEXP (x, 0);
469 if (GET_CODE (x) == PLUS
470 && GET_CODE (XEXP (x, 1)) == CONST_INT)
471 return XEXP (x, 0);
472 else if (GET_CODE (x) == MINUS
473 && GET_CODE (XEXP (x, 1)) == CONST_INT)
474 return XEXP (x, 0);
475 return 0;
476 }
477
478 /* A subroutine of global_reg_mentioned_p, returns 1 if *LOC mentions
479 a global register. */
480
481 static int
global_reg_mentioned_p_1(rtx * loc,void * data ATTRIBUTE_UNUSED)482 global_reg_mentioned_p_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
483 {
484 int regno;
485 rtx x = *loc;
486
487 if (! x)
488 return 0;
489
490 switch (GET_CODE (x))
491 {
492 case SUBREG:
493 if (REG_P (SUBREG_REG (x)))
494 {
495 if (REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
496 && global_regs[subreg_regno (x)])
497 return 1;
498 return 0;
499 }
500 break;
501
502 case REG:
503 regno = REGNO (x);
504 if (regno < FIRST_PSEUDO_REGISTER && global_regs[regno])
505 return 1;
506 return 0;
507
508 case SCRATCH:
509 case PC:
510 case CC0:
511 case CONST_INT:
512 case CONST_DOUBLE:
513 case CONST:
514 case LABEL_REF:
515 return 0;
516
517 case CALL:
518 /* A non-constant call might use a global register. */
519 return 1;
520
521 default:
522 break;
523 }
524
525 return 0;
526 }
527
528 /* Returns nonzero if X mentions a global register. */
529
530 int
global_reg_mentioned_p(rtx x)531 global_reg_mentioned_p (rtx x)
532 {
533 if (INSN_P (x))
534 {
535 if (CALL_P (x))
536 {
537 if (! CONST_OR_PURE_CALL_P (x))
538 return 1;
539 x = CALL_INSN_FUNCTION_USAGE (x);
540 if (x == 0)
541 return 0;
542 }
543 else
544 x = PATTERN (x);
545 }
546
547 return for_each_rtx (&x, global_reg_mentioned_p_1, NULL);
548 }
549
550 /* Return the number of places FIND appears within X. If COUNT_DEST is
551 zero, we do not count occurrences inside the destination of a SET. */
552
553 int
count_occurrences(rtx x,rtx find,int count_dest)554 count_occurrences (rtx x, rtx find, int count_dest)
555 {
556 int i, j;
557 enum rtx_code code;
558 const char *format_ptr;
559 int count;
560
561 if (x == find)
562 return 1;
563
564 code = GET_CODE (x);
565
566 switch (code)
567 {
568 case REG:
569 case CONST_INT:
570 case CONST_DOUBLE:
571 case CONST_VECTOR:
572 case SYMBOL_REF:
573 case CODE_LABEL:
574 case PC:
575 case CC0:
576 return 0;
577
578 case MEM:
579 if (MEM_P (find) && rtx_equal_p (x, find))
580 return 1;
581 break;
582
583 case SET:
584 if (SET_DEST (x) == find && ! count_dest)
585 return count_occurrences (SET_SRC (x), find, count_dest);
586 break;
587
588 default:
589 break;
590 }
591
592 format_ptr = GET_RTX_FORMAT (code);
593 count = 0;
594
595 for (i = 0; i < GET_RTX_LENGTH (code); i++)
596 {
597 switch (*format_ptr++)
598 {
599 case 'e':
600 count += count_occurrences (XEXP (x, i), find, count_dest);
601 break;
602
603 case 'E':
604 for (j = 0; j < XVECLEN (x, i); j++)
605 count += count_occurrences (XVECEXP (x, i, j), find, count_dest);
606 break;
607 }
608 }
609 return count;
610 }
611
612 /* Nonzero if register REG appears somewhere within IN.
613 Also works if REG is not a register; in this case it checks
614 for a subexpression of IN that is Lisp "equal" to REG. */
615
616 int
reg_mentioned_p(rtx reg,rtx in)617 reg_mentioned_p (rtx reg, rtx in)
618 {
619 const char *fmt;
620 int i;
621 enum rtx_code code;
622
623 if (in == 0)
624 return 0;
625
626 if (reg == in)
627 return 1;
628
629 if (GET_CODE (in) == LABEL_REF)
630 return reg == XEXP (in, 0);
631
632 code = GET_CODE (in);
633
634 switch (code)
635 {
636 /* Compare registers by number. */
637 case REG:
638 return REG_P (reg) && REGNO (in) == REGNO (reg);
639
640 /* These codes have no constituent expressions
641 and are unique. */
642 case SCRATCH:
643 case CC0:
644 case PC:
645 return 0;
646
647 case CONST_INT:
648 case CONST_VECTOR:
649 case CONST_DOUBLE:
650 /* These are kept unique for a given value. */
651 return 0;
652
653 default:
654 break;
655 }
656
657 if (GET_CODE (reg) == code && rtx_equal_p (reg, in))
658 return 1;
659
660 fmt = GET_RTX_FORMAT (code);
661
662 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
663 {
664 if (fmt[i] == 'E')
665 {
666 int j;
667 for (j = XVECLEN (in, i) - 1; j >= 0; j--)
668 if (reg_mentioned_p (reg, XVECEXP (in, i, j)))
669 return 1;
670 }
671 else if (fmt[i] == 'e'
672 && reg_mentioned_p (reg, XEXP (in, i)))
673 return 1;
674 }
675 return 0;
676 }
677
678 /* Return 1 if in between BEG and END, exclusive of BEG and END, there is
679 no CODE_LABEL insn. */
680
681 int
no_labels_between_p(rtx beg,rtx end)682 no_labels_between_p (rtx beg, rtx end)
683 {
684 rtx p;
685 if (beg == end)
686 return 0;
687 for (p = NEXT_INSN (beg); p != end; p = NEXT_INSN (p))
688 if (LABEL_P (p))
689 return 0;
690 return 1;
691 }
692
693 /* Nonzero if register REG is used in an insn between
694 FROM_INSN and TO_INSN (exclusive of those two). */
695
696 int
reg_used_between_p(rtx reg,rtx from_insn,rtx to_insn)697 reg_used_between_p (rtx reg, rtx from_insn, rtx to_insn)
698 {
699 rtx insn;
700
701 if (from_insn == to_insn)
702 return 0;
703
704 for (insn = NEXT_INSN (from_insn); insn != to_insn; insn = NEXT_INSN (insn))
705 if (INSN_P (insn)
706 && (reg_overlap_mentioned_p (reg, PATTERN (insn))
707 || (CALL_P (insn) && find_reg_fusage (insn, USE, reg))))
708 return 1;
709 return 0;
710 }
711
712 /* Nonzero if the old value of X, a register, is referenced in BODY. If X
713 is entirely replaced by a new value and the only use is as a SET_DEST,
714 we do not consider it a reference. */
715
716 int
reg_referenced_p(rtx x,rtx body)717 reg_referenced_p (rtx x, rtx body)
718 {
719 int i;
720
721 switch (GET_CODE (body))
722 {
723 case SET:
724 if (reg_overlap_mentioned_p (x, SET_SRC (body)))
725 return 1;
726
727 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
728 of a REG that occupies all of the REG, the insn references X if
729 it is mentioned in the destination. */
730 if (GET_CODE (SET_DEST (body)) != CC0
731 && GET_CODE (SET_DEST (body)) != PC
732 && !REG_P (SET_DEST (body))
733 && ! (GET_CODE (SET_DEST (body)) == SUBREG
734 && REG_P (SUBREG_REG (SET_DEST (body)))
735 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (body))))
736 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
737 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (body)))
738 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
739 && reg_overlap_mentioned_p (x, SET_DEST (body)))
740 return 1;
741 return 0;
742
743 case ASM_OPERANDS:
744 for (i = ASM_OPERANDS_INPUT_LENGTH (body) - 1; i >= 0; i--)
745 if (reg_overlap_mentioned_p (x, ASM_OPERANDS_INPUT (body, i)))
746 return 1;
747 return 0;
748
749 case CALL:
750 case USE:
751 case IF_THEN_ELSE:
752 return reg_overlap_mentioned_p (x, body);
753
754 case TRAP_IF:
755 return reg_overlap_mentioned_p (x, TRAP_CONDITION (body));
756
757 case PREFETCH:
758 return reg_overlap_mentioned_p (x, XEXP (body, 0));
759
760 case UNSPEC:
761 case UNSPEC_VOLATILE:
762 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
763 if (reg_overlap_mentioned_p (x, XVECEXP (body, 0, i)))
764 return 1;
765 return 0;
766
767 case PARALLEL:
768 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
769 if (reg_referenced_p (x, XVECEXP (body, 0, i)))
770 return 1;
771 return 0;
772
773 case CLOBBER:
774 if (MEM_P (XEXP (body, 0)))
775 if (reg_overlap_mentioned_p (x, XEXP (XEXP (body, 0), 0)))
776 return 1;
777 return 0;
778
779 case COND_EXEC:
780 if (reg_overlap_mentioned_p (x, COND_EXEC_TEST (body)))
781 return 1;
782 return reg_referenced_p (x, COND_EXEC_CODE (body));
783
784 default:
785 return 0;
786 }
787 }
788
789 /* Nonzero if register REG is set or clobbered in an insn between
790 FROM_INSN and TO_INSN (exclusive of those two). */
791
792 int
reg_set_between_p(rtx reg,rtx from_insn,rtx to_insn)793 reg_set_between_p (rtx reg, rtx from_insn, rtx to_insn)
794 {
795 rtx insn;
796
797 if (from_insn == to_insn)
798 return 0;
799
800 for (insn = NEXT_INSN (from_insn); insn != to_insn; insn = NEXT_INSN (insn))
801 if (INSN_P (insn) && reg_set_p (reg, insn))
802 return 1;
803 return 0;
804 }
805
806 /* Internals of reg_set_between_p. */
807 int
reg_set_p(rtx reg,rtx insn)808 reg_set_p (rtx reg, rtx insn)
809 {
810 /* We can be passed an insn or part of one. If we are passed an insn,
811 check if a side-effect of the insn clobbers REG. */
812 if (INSN_P (insn)
813 && (FIND_REG_INC_NOTE (insn, reg)
814 || (CALL_P (insn)
815 && ((REG_P (reg)
816 && REGNO (reg) < FIRST_PSEUDO_REGISTER
817 && TEST_HARD_REG_BIT (regs_invalidated_by_call,
818 REGNO (reg)))
819 || MEM_P (reg)
820 || find_reg_fusage (insn, CLOBBER, reg)))))
821 return 1;
822
823 return set_of (reg, insn) != NULL_RTX;
824 }
825
826 /* Similar to reg_set_between_p, but check all registers in X. Return 0
827 only if none of them are modified between START and END. Return 1 if
828 X contains a MEM; this routine does usememory aliasing. */
829
830 int
modified_between_p(rtx x,rtx start,rtx end)831 modified_between_p (rtx x, rtx start, rtx end)
832 {
833 enum rtx_code code = GET_CODE (x);
834 const char *fmt;
835 int i, j;
836 rtx insn;
837
838 if (start == end)
839 return 0;
840
841 switch (code)
842 {
843 case CONST_INT:
844 case CONST_DOUBLE:
845 case CONST_VECTOR:
846 case CONST:
847 case SYMBOL_REF:
848 case LABEL_REF:
849 return 0;
850
851 case PC:
852 case CC0:
853 return 1;
854
855 case MEM:
856 if (modified_between_p (XEXP (x, 0), start, end))
857 return 1;
858 if (MEM_READONLY_P (x))
859 return 0;
860 for (insn = NEXT_INSN (start); insn != end; insn = NEXT_INSN (insn))
861 if (memory_modified_in_insn_p (x, insn))
862 return 1;
863 return 0;
864 break;
865
866 case REG:
867 return reg_set_between_p (x, start, end);
868
869 default:
870 break;
871 }
872
873 fmt = GET_RTX_FORMAT (code);
874 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
875 {
876 if (fmt[i] == 'e' && modified_between_p (XEXP (x, i), start, end))
877 return 1;
878
879 else if (fmt[i] == 'E')
880 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
881 if (modified_between_p (XVECEXP (x, i, j), start, end))
882 return 1;
883 }
884
885 return 0;
886 }
887
888 /* Similar to reg_set_p, but check all registers in X. Return 0 only if none
889 of them are modified in INSN. Return 1 if X contains a MEM; this routine
890 does use memory aliasing. */
891
892 int
modified_in_p(rtx x,rtx insn)893 modified_in_p (rtx x, rtx insn)
894 {
895 enum rtx_code code = GET_CODE (x);
896 const char *fmt;
897 int i, j;
898
899 switch (code)
900 {
901 case CONST_INT:
902 case CONST_DOUBLE:
903 case CONST_VECTOR:
904 case CONST:
905 case SYMBOL_REF:
906 case LABEL_REF:
907 return 0;
908
909 case PC:
910 case CC0:
911 return 1;
912
913 case MEM:
914 if (modified_in_p (XEXP (x, 0), insn))
915 return 1;
916 if (MEM_READONLY_P (x))
917 return 0;
918 if (memory_modified_in_insn_p (x, insn))
919 return 1;
920 return 0;
921 break;
922
923 case REG:
924 return reg_set_p (x, insn);
925
926 default:
927 break;
928 }
929
930 fmt = GET_RTX_FORMAT (code);
931 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
932 {
933 if (fmt[i] == 'e' && modified_in_p (XEXP (x, i), insn))
934 return 1;
935
936 else if (fmt[i] == 'E')
937 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
938 if (modified_in_p (XVECEXP (x, i, j), insn))
939 return 1;
940 }
941
942 return 0;
943 }
944
945 /* Helper function for set_of. */
946 struct set_of_data
947 {
948 rtx found;
949 rtx pat;
950 };
951
952 static void
set_of_1(rtx x,rtx pat,void * data1)953 set_of_1 (rtx x, rtx pat, void *data1)
954 {
955 struct set_of_data *data = (struct set_of_data *) (data1);
956 if (rtx_equal_p (x, data->pat)
957 || (!MEM_P (x) && reg_overlap_mentioned_p (data->pat, x)))
958 data->found = pat;
959 }
960
961 /* Give an INSN, return a SET or CLOBBER expression that does modify PAT
962 (either directly or via STRICT_LOW_PART and similar modifiers). */
963 rtx
set_of(rtx pat,rtx insn)964 set_of (rtx pat, rtx insn)
965 {
966 struct set_of_data data;
967 data.found = NULL_RTX;
968 data.pat = pat;
969 note_stores (INSN_P (insn) ? PATTERN (insn) : insn, set_of_1, &data);
970 return data.found;
971 }
972
973 /* Given an INSN, return a SET expression if this insn has only a single SET.
974 It may also have CLOBBERs, USEs, or SET whose output
975 will not be used, which we ignore. */
976
977 rtx
single_set_2(rtx insn,rtx pat)978 single_set_2 (rtx insn, rtx pat)
979 {
980 rtx set = NULL;
981 int set_verified = 1;
982 int i;
983
984 if (GET_CODE (pat) == PARALLEL)
985 {
986 for (i = 0; i < XVECLEN (pat, 0); i++)
987 {
988 rtx sub = XVECEXP (pat, 0, i);
989 switch (GET_CODE (sub))
990 {
991 case USE:
992 case CLOBBER:
993 break;
994
995 case SET:
996 /* We can consider insns having multiple sets, where all
997 but one are dead as single set insns. In common case
998 only single set is present in the pattern so we want
999 to avoid checking for REG_UNUSED notes unless necessary.
1000
1001 When we reach set first time, we just expect this is
1002 the single set we are looking for and only when more
1003 sets are found in the insn, we check them. */
1004 if (!set_verified)
1005 {
1006 if (find_reg_note (insn, REG_UNUSED, SET_DEST (set))
1007 && !side_effects_p (set))
1008 set = NULL;
1009 else
1010 set_verified = 1;
1011 }
1012 if (!set)
1013 set = sub, set_verified = 0;
1014 else if (!find_reg_note (insn, REG_UNUSED, SET_DEST (sub))
1015 || side_effects_p (sub))
1016 return NULL_RTX;
1017 break;
1018
1019 default:
1020 return NULL_RTX;
1021 }
1022 }
1023 }
1024 return set;
1025 }
1026
1027 /* Given an INSN, return nonzero if it has more than one SET, else return
1028 zero. */
1029
1030 int
multiple_sets(rtx insn)1031 multiple_sets (rtx insn)
1032 {
1033 int found;
1034 int i;
1035
1036 /* INSN must be an insn. */
1037 if (! INSN_P (insn))
1038 return 0;
1039
1040 /* Only a PARALLEL can have multiple SETs. */
1041 if (GET_CODE (PATTERN (insn)) == PARALLEL)
1042 {
1043 for (i = 0, found = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1044 if (GET_CODE (XVECEXP (PATTERN (insn), 0, i)) == SET)
1045 {
1046 /* If we have already found a SET, then return now. */
1047 if (found)
1048 return 1;
1049 else
1050 found = 1;
1051 }
1052 }
1053
1054 /* Either zero or one SET. */
1055 return 0;
1056 }
1057
1058 /* Return nonzero if the destination of SET equals the source
1059 and there are no side effects. */
1060
1061 int
set_noop_p(rtx set)1062 set_noop_p (rtx set)
1063 {
1064 rtx src = SET_SRC (set);
1065 rtx dst = SET_DEST (set);
1066
1067 if (dst == pc_rtx && src == pc_rtx)
1068 return 1;
1069
1070 if (MEM_P (dst) && MEM_P (src))
1071 return rtx_equal_p (dst, src) && !side_effects_p (dst);
1072
1073 if (GET_CODE (dst) == ZERO_EXTRACT)
1074 return rtx_equal_p (XEXP (dst, 0), src)
1075 && ! BYTES_BIG_ENDIAN && XEXP (dst, 2) == const0_rtx
1076 && !side_effects_p (src);
1077
1078 if (GET_CODE (dst) == STRICT_LOW_PART)
1079 dst = XEXP (dst, 0);
1080
1081 if (GET_CODE (src) == SUBREG && GET_CODE (dst) == SUBREG)
1082 {
1083 if (SUBREG_BYTE (src) != SUBREG_BYTE (dst))
1084 return 0;
1085 src = SUBREG_REG (src);
1086 dst = SUBREG_REG (dst);
1087 }
1088
1089 return (REG_P (src) && REG_P (dst)
1090 && REGNO (src) == REGNO (dst));
1091 }
1092
1093 /* Return nonzero if an insn consists only of SETs, each of which only sets a
1094 value to itself. */
1095
1096 int
noop_move_p(rtx insn)1097 noop_move_p (rtx insn)
1098 {
1099 rtx pat = PATTERN (insn);
1100
1101 if (INSN_CODE (insn) == NOOP_MOVE_INSN_CODE)
1102 return 1;
1103
1104 /* Insns carrying these notes are useful later on. */
1105 if (find_reg_note (insn, REG_EQUAL, NULL_RTX))
1106 return 0;
1107
1108 /* For now treat an insn with a REG_RETVAL note as a
1109 a special insn which should not be considered a no-op. */
1110 if (find_reg_note (insn, REG_RETVAL, NULL_RTX))
1111 return 0;
1112
1113 if (GET_CODE (pat) == SET && set_noop_p (pat))
1114 return 1;
1115
1116 if (GET_CODE (pat) == PARALLEL)
1117 {
1118 int i;
1119 /* If nothing but SETs of registers to themselves,
1120 this insn can also be deleted. */
1121 for (i = 0; i < XVECLEN (pat, 0); i++)
1122 {
1123 rtx tem = XVECEXP (pat, 0, i);
1124
1125 if (GET_CODE (tem) == USE
1126 || GET_CODE (tem) == CLOBBER)
1127 continue;
1128
1129 if (GET_CODE (tem) != SET || ! set_noop_p (tem))
1130 return 0;
1131 }
1132
1133 return 1;
1134 }
1135 return 0;
1136 }
1137
1138
1139 /* Return the last thing that X was assigned from before *PINSN. If VALID_TO
1140 is not NULL_RTX then verify that the object is not modified up to VALID_TO.
1141 If the object was modified, if we hit a partial assignment to X, or hit a
1142 CODE_LABEL first, return X. If we found an assignment, update *PINSN to
1143 point to it. ALLOW_HWREG is set to 1 if hardware registers are allowed to
1144 be the src. */
1145
1146 rtx
find_last_value(rtx x,rtx * pinsn,rtx valid_to,int allow_hwreg)1147 find_last_value (rtx x, rtx *pinsn, rtx valid_to, int allow_hwreg)
1148 {
1149 rtx p;
1150
1151 for (p = PREV_INSN (*pinsn); p && !LABEL_P (p);
1152 p = PREV_INSN (p))
1153 if (INSN_P (p))
1154 {
1155 rtx set = single_set (p);
1156 rtx note = find_reg_note (p, REG_EQUAL, NULL_RTX);
1157
1158 if (set && rtx_equal_p (x, SET_DEST (set)))
1159 {
1160 rtx src = SET_SRC (set);
1161
1162 if (note && GET_CODE (XEXP (note, 0)) != EXPR_LIST)
1163 src = XEXP (note, 0);
1164
1165 if ((valid_to == NULL_RTX
1166 || ! modified_between_p (src, PREV_INSN (p), valid_to))
1167 /* Reject hard registers because we don't usually want
1168 to use them; we'd rather use a pseudo. */
1169 && (! (REG_P (src)
1170 && REGNO (src) < FIRST_PSEUDO_REGISTER) || allow_hwreg))
1171 {
1172 *pinsn = p;
1173 return src;
1174 }
1175 }
1176
1177 /* If set in non-simple way, we don't have a value. */
1178 if (reg_set_p (x, p))
1179 break;
1180 }
1181
1182 return x;
1183 }
1184
1185 /* Return nonzero if register in range [REGNO, ENDREGNO)
1186 appears either explicitly or implicitly in X
1187 other than being stored into.
1188
1189 References contained within the substructure at LOC do not count.
1190 LOC may be zero, meaning don't ignore anything. */
1191
1192 int
refers_to_regno_p(unsigned int regno,unsigned int endregno,rtx x,rtx * loc)1193 refers_to_regno_p (unsigned int regno, unsigned int endregno, rtx x,
1194 rtx *loc)
1195 {
1196 int i;
1197 unsigned int x_regno;
1198 RTX_CODE code;
1199 const char *fmt;
1200
1201 repeat:
1202 /* The contents of a REG_NONNEG note is always zero, so we must come here
1203 upon repeat in case the last REG_NOTE is a REG_NONNEG note. */
1204 if (x == 0)
1205 return 0;
1206
1207 code = GET_CODE (x);
1208
1209 switch (code)
1210 {
1211 case REG:
1212 x_regno = REGNO (x);
1213
1214 /* If we modifying the stack, frame, or argument pointer, it will
1215 clobber a virtual register. In fact, we could be more precise,
1216 but it isn't worth it. */
1217 if ((x_regno == STACK_POINTER_REGNUM
1218 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1219 || x_regno == ARG_POINTER_REGNUM
1220 #endif
1221 || x_regno == FRAME_POINTER_REGNUM)
1222 && regno >= FIRST_VIRTUAL_REGISTER && regno <= LAST_VIRTUAL_REGISTER)
1223 return 1;
1224
1225 return (endregno > x_regno
1226 && regno < x_regno + (x_regno < FIRST_PSEUDO_REGISTER
1227 ? hard_regno_nregs[x_regno][GET_MODE (x)]
1228 : 1));
1229
1230 case SUBREG:
1231 /* If this is a SUBREG of a hard reg, we can see exactly which
1232 registers are being modified. Otherwise, handle normally. */
1233 if (REG_P (SUBREG_REG (x))
1234 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER)
1235 {
1236 unsigned int inner_regno = subreg_regno (x);
1237 unsigned int inner_endregno
1238 = inner_regno + (inner_regno < FIRST_PSEUDO_REGISTER
1239 ? hard_regno_nregs[inner_regno][GET_MODE (x)] : 1);
1240
1241 return endregno > inner_regno && regno < inner_endregno;
1242 }
1243 break;
1244
1245 case CLOBBER:
1246 case SET:
1247 if (&SET_DEST (x) != loc
1248 /* Note setting a SUBREG counts as referring to the REG it is in for
1249 a pseudo but not for hard registers since we can
1250 treat each word individually. */
1251 && ((GET_CODE (SET_DEST (x)) == SUBREG
1252 && loc != &SUBREG_REG (SET_DEST (x))
1253 && REG_P (SUBREG_REG (SET_DEST (x)))
1254 && REGNO (SUBREG_REG (SET_DEST (x))) >= FIRST_PSEUDO_REGISTER
1255 && refers_to_regno_p (regno, endregno,
1256 SUBREG_REG (SET_DEST (x)), loc))
1257 || (!REG_P (SET_DEST (x))
1258 && refers_to_regno_p (regno, endregno, SET_DEST (x), loc))))
1259 return 1;
1260
1261 if (code == CLOBBER || loc == &SET_SRC (x))
1262 return 0;
1263 x = SET_SRC (x);
1264 goto repeat;
1265
1266 default:
1267 break;
1268 }
1269
1270 /* X does not match, so try its subexpressions. */
1271
1272 fmt = GET_RTX_FORMAT (code);
1273 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1274 {
1275 if (fmt[i] == 'e' && loc != &XEXP (x, i))
1276 {
1277 if (i == 0)
1278 {
1279 x = XEXP (x, 0);
1280 goto repeat;
1281 }
1282 else
1283 if (refers_to_regno_p (regno, endregno, XEXP (x, i), loc))
1284 return 1;
1285 }
1286 else if (fmt[i] == 'E')
1287 {
1288 int j;
1289 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1290 if (loc != &XVECEXP (x, i, j)
1291 && refers_to_regno_p (regno, endregno, XVECEXP (x, i, j), loc))
1292 return 1;
1293 }
1294 }
1295 return 0;
1296 }
1297
1298 /* Nonzero if modifying X will affect IN. If X is a register or a SUBREG,
1299 we check if any register number in X conflicts with the relevant register
1300 numbers. If X is a constant, return 0. If X is a MEM, return 1 iff IN
1301 contains a MEM (we don't bother checking for memory addresses that can't
1302 conflict because we expect this to be a rare case. */
1303
1304 int
reg_overlap_mentioned_p(rtx x,rtx in)1305 reg_overlap_mentioned_p (rtx x, rtx in)
1306 {
1307 unsigned int regno, endregno;
1308
1309 /* If either argument is a constant, then modifying X can not
1310 affect IN. Here we look at IN, we can profitably combine
1311 CONSTANT_P (x) with the switch statement below. */
1312 if (CONSTANT_P (in))
1313 return 0;
1314
1315 recurse:
1316 switch (GET_CODE (x))
1317 {
1318 case STRICT_LOW_PART:
1319 case ZERO_EXTRACT:
1320 case SIGN_EXTRACT:
1321 /* Overly conservative. */
1322 x = XEXP (x, 0);
1323 goto recurse;
1324
1325 case SUBREG:
1326 regno = REGNO (SUBREG_REG (x));
1327 if (regno < FIRST_PSEUDO_REGISTER)
1328 regno = subreg_regno (x);
1329 goto do_reg;
1330
1331 case REG:
1332 regno = REGNO (x);
1333 do_reg:
1334 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
1335 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
1336 return refers_to_regno_p (regno, endregno, in, (rtx*) 0);
1337
1338 case MEM:
1339 {
1340 const char *fmt;
1341 int i;
1342
1343 if (MEM_P (in))
1344 return 1;
1345
1346 fmt = GET_RTX_FORMAT (GET_CODE (in));
1347 for (i = GET_RTX_LENGTH (GET_CODE (in)) - 1; i >= 0; i--)
1348 if (fmt[i] == 'e')
1349 {
1350 if (reg_overlap_mentioned_p (x, XEXP (in, i)))
1351 return 1;
1352 }
1353 else if (fmt[i] == 'E')
1354 {
1355 int j;
1356 for (j = XVECLEN (in, i) - 1; j >= 0; --j)
1357 if (reg_overlap_mentioned_p (x, XVECEXP (in, i, j)))
1358 return 1;
1359 }
1360
1361 return 0;
1362 }
1363
1364 case SCRATCH:
1365 case PC:
1366 case CC0:
1367 return reg_mentioned_p (x, in);
1368
1369 case PARALLEL:
1370 {
1371 int i;
1372
1373 /* If any register in here refers to it we return true. */
1374 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
1375 if (XEXP (XVECEXP (x, 0, i), 0) != 0
1376 && reg_overlap_mentioned_p (XEXP (XVECEXP (x, 0, i), 0), in))
1377 return 1;
1378 return 0;
1379 }
1380
1381 default:
1382 gcc_assert (CONSTANT_P (x));
1383 return 0;
1384 }
1385 }
1386
1387 /* Call FUN on each register or MEM that is stored into or clobbered by X.
1388 (X would be the pattern of an insn).
1389 FUN receives two arguments:
1390 the REG, MEM, CC0 or PC being stored in or clobbered,
1391 the SET or CLOBBER rtx that does the store.
1392
1393 If the item being stored in or clobbered is a SUBREG of a hard register,
1394 the SUBREG will be passed. */
1395
1396 void
note_stores(rtx x,void (* fun)(rtx,rtx,void *),void * data)1397 note_stores (rtx x, void (*fun) (rtx, rtx, void *), void *data)
1398 {
1399 int i;
1400
1401 if (GET_CODE (x) == COND_EXEC)
1402 x = COND_EXEC_CODE (x);
1403
1404 if (GET_CODE (x) == SET || GET_CODE (x) == CLOBBER)
1405 {
1406 rtx dest = SET_DEST (x);
1407
1408 while ((GET_CODE (dest) == SUBREG
1409 && (!REG_P (SUBREG_REG (dest))
1410 || REGNO (SUBREG_REG (dest)) >= FIRST_PSEUDO_REGISTER))
1411 || GET_CODE (dest) == ZERO_EXTRACT
1412 || GET_CODE (dest) == STRICT_LOW_PART)
1413 dest = XEXP (dest, 0);
1414
1415 /* If we have a PARALLEL, SET_DEST is a list of EXPR_LIST expressions,
1416 each of whose first operand is a register. */
1417 if (GET_CODE (dest) == PARALLEL)
1418 {
1419 for (i = XVECLEN (dest, 0) - 1; i >= 0; i--)
1420 if (XEXP (XVECEXP (dest, 0, i), 0) != 0)
1421 (*fun) (XEXP (XVECEXP (dest, 0, i), 0), x, data);
1422 }
1423 else
1424 (*fun) (dest, x, data);
1425 }
1426
1427 else if (GET_CODE (x) == PARALLEL)
1428 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
1429 note_stores (XVECEXP (x, 0, i), fun, data);
1430 }
1431
1432 /* Like notes_stores, but call FUN for each expression that is being
1433 referenced in PBODY, a pointer to the PATTERN of an insn. We only call
1434 FUN for each expression, not any interior subexpressions. FUN receives a
1435 pointer to the expression and the DATA passed to this function.
1436
1437 Note that this is not quite the same test as that done in reg_referenced_p
1438 since that considers something as being referenced if it is being
1439 partially set, while we do not. */
1440
1441 void
note_uses(rtx * pbody,void (* fun)(rtx *,void *),void * data)1442 note_uses (rtx *pbody, void (*fun) (rtx *, void *), void *data)
1443 {
1444 rtx body = *pbody;
1445 int i;
1446
1447 switch (GET_CODE (body))
1448 {
1449 case COND_EXEC:
1450 (*fun) (&COND_EXEC_TEST (body), data);
1451 note_uses (&COND_EXEC_CODE (body), fun, data);
1452 return;
1453
1454 case PARALLEL:
1455 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
1456 note_uses (&XVECEXP (body, 0, i), fun, data);
1457 return;
1458
1459 case USE:
1460 (*fun) (&XEXP (body, 0), data);
1461 return;
1462
1463 case ASM_OPERANDS:
1464 for (i = ASM_OPERANDS_INPUT_LENGTH (body) - 1; i >= 0; i--)
1465 (*fun) (&ASM_OPERANDS_INPUT (body, i), data);
1466 return;
1467
1468 case TRAP_IF:
1469 (*fun) (&TRAP_CONDITION (body), data);
1470 return;
1471
1472 case PREFETCH:
1473 (*fun) (&XEXP (body, 0), data);
1474 return;
1475
1476 case UNSPEC:
1477 case UNSPEC_VOLATILE:
1478 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
1479 (*fun) (&XVECEXP (body, 0, i), data);
1480 return;
1481
1482 case CLOBBER:
1483 if (MEM_P (XEXP (body, 0)))
1484 (*fun) (&XEXP (XEXP (body, 0), 0), data);
1485 return;
1486
1487 case SET:
1488 {
1489 rtx dest = SET_DEST (body);
1490
1491 /* For sets we replace everything in source plus registers in memory
1492 expression in store and operands of a ZERO_EXTRACT. */
1493 (*fun) (&SET_SRC (body), data);
1494
1495 if (GET_CODE (dest) == ZERO_EXTRACT)
1496 {
1497 (*fun) (&XEXP (dest, 1), data);
1498 (*fun) (&XEXP (dest, 2), data);
1499 }
1500
1501 while (GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART)
1502 dest = XEXP (dest, 0);
1503
1504 if (MEM_P (dest))
1505 (*fun) (&XEXP (dest, 0), data);
1506 }
1507 return;
1508
1509 default:
1510 /* All the other possibilities never store. */
1511 (*fun) (pbody, data);
1512 return;
1513 }
1514 }
1515
1516 /* Return nonzero if X's old contents don't survive after INSN.
1517 This will be true if X is (cc0) or if X is a register and
1518 X dies in INSN or because INSN entirely sets X.
1519
1520 "Entirely set" means set directly and not through a SUBREG, or
1521 ZERO_EXTRACT, so no trace of the old contents remains.
1522 Likewise, REG_INC does not count.
1523
1524 REG may be a hard or pseudo reg. Renumbering is not taken into account,
1525 but for this use that makes no difference, since regs don't overlap
1526 during their lifetimes. Therefore, this function may be used
1527 at any time after deaths have been computed (in flow.c).
1528
1529 If REG is a hard reg that occupies multiple machine registers, this
1530 function will only return 1 if each of those registers will be replaced
1531 by INSN. */
1532
1533 int
dead_or_set_p(rtx insn,rtx x)1534 dead_or_set_p (rtx insn, rtx x)
1535 {
1536 unsigned int regno, last_regno;
1537 unsigned int i;
1538
1539 /* Can't use cc0_rtx below since this file is used by genattrtab.c. */
1540 if (GET_CODE (x) == CC0)
1541 return 1;
1542
1543 gcc_assert (REG_P (x));
1544
1545 regno = REGNO (x);
1546 last_regno = (regno >= FIRST_PSEUDO_REGISTER ? regno
1547 : regno + hard_regno_nregs[regno][GET_MODE (x)] - 1);
1548
1549 for (i = regno; i <= last_regno; i++)
1550 if (! dead_or_set_regno_p (insn, i))
1551 return 0;
1552
1553 return 1;
1554 }
1555
1556 /* Return TRUE iff DEST is a register or subreg of a register and
1557 doesn't change the number of words of the inner register, and any
1558 part of the register is TEST_REGNO. */
1559
1560 static bool
covers_regno_no_parallel_p(rtx dest,unsigned int test_regno)1561 covers_regno_no_parallel_p (rtx dest, unsigned int test_regno)
1562 {
1563 unsigned int regno, endregno;
1564
1565 if (GET_CODE (dest) == SUBREG
1566 && (((GET_MODE_SIZE (GET_MODE (dest))
1567 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1568 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
1569 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
1570 dest = SUBREG_REG (dest);
1571
1572 if (!REG_P (dest))
1573 return false;
1574
1575 regno = REGNO (dest);
1576 endregno = (regno >= FIRST_PSEUDO_REGISTER ? regno + 1
1577 : regno + hard_regno_nregs[regno][GET_MODE (dest)]);
1578 return (test_regno >= regno && test_regno < endregno);
1579 }
1580
1581 /* Like covers_regno_no_parallel_p, but also handles PARALLELs where
1582 any member matches the covers_regno_no_parallel_p criteria. */
1583
1584 static bool
covers_regno_p(rtx dest,unsigned int test_regno)1585 covers_regno_p (rtx dest, unsigned int test_regno)
1586 {
1587 if (GET_CODE (dest) == PARALLEL)
1588 {
1589 /* Some targets place small structures in registers for return
1590 values of functions, and those registers are wrapped in
1591 PARALLELs that we may see as the destination of a SET. */
1592 int i;
1593
1594 for (i = XVECLEN (dest, 0) - 1; i >= 0; i--)
1595 {
1596 rtx inner = XEXP (XVECEXP (dest, 0, i), 0);
1597 if (inner != NULL_RTX
1598 && covers_regno_no_parallel_p (inner, test_regno))
1599 return true;
1600 }
1601
1602 return false;
1603 }
1604 else
1605 return covers_regno_no_parallel_p (dest, test_regno);
1606 }
1607
1608 /* Utility function for dead_or_set_p to check an individual register. Also
1609 called from flow.c. */
1610
1611 int
dead_or_set_regno_p(rtx insn,unsigned int test_regno)1612 dead_or_set_regno_p (rtx insn, unsigned int test_regno)
1613 {
1614 rtx pattern;
1615
1616 /* See if there is a death note for something that includes TEST_REGNO. */
1617 if (find_regno_note (insn, REG_DEAD, test_regno))
1618 return 1;
1619
1620 if (CALL_P (insn)
1621 && find_regno_fusage (insn, CLOBBER, test_regno))
1622 return 1;
1623
1624 pattern = PATTERN (insn);
1625
1626 if (GET_CODE (pattern) == COND_EXEC)
1627 pattern = COND_EXEC_CODE (pattern);
1628
1629 if (GET_CODE (pattern) == SET)
1630 return covers_regno_p (SET_DEST (pattern), test_regno);
1631 else if (GET_CODE (pattern) == PARALLEL)
1632 {
1633 int i;
1634
1635 for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--)
1636 {
1637 rtx body = XVECEXP (pattern, 0, i);
1638
1639 if (GET_CODE (body) == COND_EXEC)
1640 body = COND_EXEC_CODE (body);
1641
1642 if ((GET_CODE (body) == SET || GET_CODE (body) == CLOBBER)
1643 && covers_regno_p (SET_DEST (body), test_regno))
1644 return 1;
1645 }
1646 }
1647
1648 return 0;
1649 }
1650
1651 /* Return the reg-note of kind KIND in insn INSN, if there is one.
1652 If DATUM is nonzero, look for one whose datum is DATUM. */
1653
1654 rtx
find_reg_note(rtx insn,enum reg_note kind,rtx datum)1655 find_reg_note (rtx insn, enum reg_note kind, rtx datum)
1656 {
1657 rtx link;
1658
1659 /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */
1660 if (! INSN_P (insn))
1661 return 0;
1662 if (datum == 0)
1663 {
1664 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1665 if (REG_NOTE_KIND (link) == kind)
1666 return link;
1667 return 0;
1668 }
1669
1670 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1671 if (REG_NOTE_KIND (link) == kind && datum == XEXP (link, 0))
1672 return link;
1673 return 0;
1674 }
1675
1676 /* Return the reg-note of kind KIND in insn INSN which applies to register
1677 number REGNO, if any. Return 0 if there is no such reg-note. Note that
1678 the REGNO of this NOTE need not be REGNO if REGNO is a hard register;
1679 it might be the case that the note overlaps REGNO. */
1680
1681 rtx
find_regno_note(rtx insn,enum reg_note kind,unsigned int regno)1682 find_regno_note (rtx insn, enum reg_note kind, unsigned int regno)
1683 {
1684 rtx link;
1685
1686 /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */
1687 if (! INSN_P (insn))
1688 return 0;
1689
1690 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1691 if (REG_NOTE_KIND (link) == kind
1692 /* Verify that it is a register, so that scratch and MEM won't cause a
1693 problem here. */
1694 && REG_P (XEXP (link, 0))
1695 && REGNO (XEXP (link, 0)) <= regno
1696 && ((REGNO (XEXP (link, 0))
1697 + (REGNO (XEXP (link, 0)) >= FIRST_PSEUDO_REGISTER ? 1
1698 : hard_regno_nregs[REGNO (XEXP (link, 0))]
1699 [GET_MODE (XEXP (link, 0))]))
1700 > regno))
1701 return link;
1702 return 0;
1703 }
1704
1705 /* Return a REG_EQUIV or REG_EQUAL note if insn has only a single set and
1706 has such a note. */
1707
1708 rtx
find_reg_equal_equiv_note(rtx insn)1709 find_reg_equal_equiv_note (rtx insn)
1710 {
1711 rtx link;
1712
1713 if (!INSN_P (insn))
1714 return 0;
1715 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1716 if (REG_NOTE_KIND (link) == REG_EQUAL
1717 || REG_NOTE_KIND (link) == REG_EQUIV)
1718 {
1719 if (single_set (insn) == 0)
1720 return 0;
1721 return link;
1722 }
1723 return NULL;
1724 }
1725
1726 /* Return true if DATUM, or any overlap of DATUM, of kind CODE is found
1727 in the CALL_INSN_FUNCTION_USAGE information of INSN. */
1728
1729 int
find_reg_fusage(rtx insn,enum rtx_code code,rtx datum)1730 find_reg_fusage (rtx insn, enum rtx_code code, rtx datum)
1731 {
1732 /* If it's not a CALL_INSN, it can't possibly have a
1733 CALL_INSN_FUNCTION_USAGE field, so don't bother checking. */
1734 if (!CALL_P (insn))
1735 return 0;
1736
1737 gcc_assert (datum);
1738
1739 if (!REG_P (datum))
1740 {
1741 rtx link;
1742
1743 for (link = CALL_INSN_FUNCTION_USAGE (insn);
1744 link;
1745 link = XEXP (link, 1))
1746 if (GET_CODE (XEXP (link, 0)) == code
1747 && rtx_equal_p (datum, XEXP (XEXP (link, 0), 0)))
1748 return 1;
1749 }
1750 else
1751 {
1752 unsigned int regno = REGNO (datum);
1753
1754 /* CALL_INSN_FUNCTION_USAGE information cannot contain references
1755 to pseudo registers, so don't bother checking. */
1756
1757 if (regno < FIRST_PSEUDO_REGISTER)
1758 {
1759 unsigned int end_regno
1760 = regno + hard_regno_nregs[regno][GET_MODE (datum)];
1761 unsigned int i;
1762
1763 for (i = regno; i < end_regno; i++)
1764 if (find_regno_fusage (insn, code, i))
1765 return 1;
1766 }
1767 }
1768
1769 return 0;
1770 }
1771
1772 /* Return true if REGNO, or any overlap of REGNO, of kind CODE is found
1773 in the CALL_INSN_FUNCTION_USAGE information of INSN. */
1774
1775 int
find_regno_fusage(rtx insn,enum rtx_code code,unsigned int regno)1776 find_regno_fusage (rtx insn, enum rtx_code code, unsigned int regno)
1777 {
1778 rtx link;
1779
1780 /* CALL_INSN_FUNCTION_USAGE information cannot contain references
1781 to pseudo registers, so don't bother checking. */
1782
1783 if (regno >= FIRST_PSEUDO_REGISTER
1784 || !CALL_P (insn) )
1785 return 0;
1786
1787 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
1788 {
1789 unsigned int regnote;
1790 rtx op, reg;
1791
1792 if (GET_CODE (op = XEXP (link, 0)) == code
1793 && REG_P (reg = XEXP (op, 0))
1794 && (regnote = REGNO (reg)) <= regno
1795 && regnote + hard_regno_nregs[regnote][GET_MODE (reg)] > regno)
1796 return 1;
1797 }
1798
1799 return 0;
1800 }
1801
1802 /* Return true if INSN is a call to a pure function. */
1803
1804 int
pure_call_p(rtx insn)1805 pure_call_p (rtx insn)
1806 {
1807 rtx link;
1808
1809 if (!CALL_P (insn) || ! CONST_OR_PURE_CALL_P (insn))
1810 return 0;
1811
1812 /* Look for the note that differentiates const and pure functions. */
1813 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
1814 {
1815 rtx u, m;
1816
1817 if (GET_CODE (u = XEXP (link, 0)) == USE
1818 && MEM_P (m = XEXP (u, 0)) && GET_MODE (m) == BLKmode
1819 && GET_CODE (XEXP (m, 0)) == SCRATCH)
1820 return 1;
1821 }
1822
1823 return 0;
1824 }
1825
1826 /* Remove register note NOTE from the REG_NOTES of INSN. */
1827
1828 void
remove_note(rtx insn,rtx note)1829 remove_note (rtx insn, rtx note)
1830 {
1831 rtx link;
1832
1833 if (note == NULL_RTX)
1834 return;
1835
1836 if (REG_NOTES (insn) == note)
1837 {
1838 REG_NOTES (insn) = XEXP (note, 1);
1839 return;
1840 }
1841
1842 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1843 if (XEXP (link, 1) == note)
1844 {
1845 XEXP (link, 1) = XEXP (note, 1);
1846 return;
1847 }
1848
1849 gcc_unreachable ();
1850 }
1851
1852 /* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and
1853 return 1 if it is found. A simple equality test is used to determine if
1854 NODE matches. */
1855
1856 int
in_expr_list_p(rtx listp,rtx node)1857 in_expr_list_p (rtx listp, rtx node)
1858 {
1859 rtx x;
1860
1861 for (x = listp; x; x = XEXP (x, 1))
1862 if (node == XEXP (x, 0))
1863 return 1;
1864
1865 return 0;
1866 }
1867
1868 /* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and
1869 remove that entry from the list if it is found.
1870
1871 A simple equality test is used to determine if NODE matches. */
1872
1873 void
remove_node_from_expr_list(rtx node,rtx * listp)1874 remove_node_from_expr_list (rtx node, rtx *listp)
1875 {
1876 rtx temp = *listp;
1877 rtx prev = NULL_RTX;
1878
1879 while (temp)
1880 {
1881 if (node == XEXP (temp, 0))
1882 {
1883 /* Splice the node out of the list. */
1884 if (prev)
1885 XEXP (prev, 1) = XEXP (temp, 1);
1886 else
1887 *listp = XEXP (temp, 1);
1888
1889 return;
1890 }
1891
1892 prev = temp;
1893 temp = XEXP (temp, 1);
1894 }
1895 }
1896
1897 /* Nonzero if X contains any volatile instructions. These are instructions
1898 which may cause unpredictable machine state instructions, and thus no
1899 instructions should be moved or combined across them. This includes
1900 only volatile asms and UNSPEC_VOLATILE instructions. */
1901
1902 int
volatile_insn_p(rtx x)1903 volatile_insn_p (rtx x)
1904 {
1905 RTX_CODE code;
1906
1907 code = GET_CODE (x);
1908 switch (code)
1909 {
1910 case LABEL_REF:
1911 case SYMBOL_REF:
1912 case CONST_INT:
1913 case CONST:
1914 case CONST_DOUBLE:
1915 case CONST_VECTOR:
1916 case CC0:
1917 case PC:
1918 case REG:
1919 case SCRATCH:
1920 case CLOBBER:
1921 case ADDR_VEC:
1922 case ADDR_DIFF_VEC:
1923 case CALL:
1924 case MEM:
1925 return 0;
1926
1927 case UNSPEC_VOLATILE:
1928 /* case TRAP_IF: This isn't clear yet. */
1929 return 1;
1930
1931 case ASM_INPUT:
1932 case ASM_OPERANDS:
1933 if (MEM_VOLATILE_P (x))
1934 return 1;
1935
1936 default:
1937 break;
1938 }
1939
1940 /* Recursively scan the operands of this expression. */
1941
1942 {
1943 const char *fmt = GET_RTX_FORMAT (code);
1944 int i;
1945
1946 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1947 {
1948 if (fmt[i] == 'e')
1949 {
1950 if (volatile_insn_p (XEXP (x, i)))
1951 return 1;
1952 }
1953 else if (fmt[i] == 'E')
1954 {
1955 int j;
1956 for (j = 0; j < XVECLEN (x, i); j++)
1957 if (volatile_insn_p (XVECEXP (x, i, j)))
1958 return 1;
1959 }
1960 }
1961 }
1962 return 0;
1963 }
1964
1965 /* Nonzero if X contains any volatile memory references
1966 UNSPEC_VOLATILE operations or volatile ASM_OPERANDS expressions. */
1967
1968 int
volatile_refs_p(rtx x)1969 volatile_refs_p (rtx x)
1970 {
1971 RTX_CODE code;
1972
1973 code = GET_CODE (x);
1974 switch (code)
1975 {
1976 case LABEL_REF:
1977 case SYMBOL_REF:
1978 case CONST_INT:
1979 case CONST:
1980 case CONST_DOUBLE:
1981 case CONST_VECTOR:
1982 case CC0:
1983 case PC:
1984 case REG:
1985 case SCRATCH:
1986 case CLOBBER:
1987 case ADDR_VEC:
1988 case ADDR_DIFF_VEC:
1989 return 0;
1990
1991 case UNSPEC_VOLATILE:
1992 return 1;
1993
1994 case MEM:
1995 case ASM_INPUT:
1996 case ASM_OPERANDS:
1997 if (MEM_VOLATILE_P (x))
1998 return 1;
1999
2000 default:
2001 break;
2002 }
2003
2004 /* Recursively scan the operands of this expression. */
2005
2006 {
2007 const char *fmt = GET_RTX_FORMAT (code);
2008 int i;
2009
2010 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2011 {
2012 if (fmt[i] == 'e')
2013 {
2014 if (volatile_refs_p (XEXP (x, i)))
2015 return 1;
2016 }
2017 else if (fmt[i] == 'E')
2018 {
2019 int j;
2020 for (j = 0; j < XVECLEN (x, i); j++)
2021 if (volatile_refs_p (XVECEXP (x, i, j)))
2022 return 1;
2023 }
2024 }
2025 }
2026 return 0;
2027 }
2028
2029 /* Similar to above, except that it also rejects register pre- and post-
2030 incrementing. */
2031
2032 int
side_effects_p(rtx x)2033 side_effects_p (rtx x)
2034 {
2035 RTX_CODE code;
2036
2037 code = GET_CODE (x);
2038 switch (code)
2039 {
2040 case LABEL_REF:
2041 case SYMBOL_REF:
2042 case CONST_INT:
2043 case CONST:
2044 case CONST_DOUBLE:
2045 case CONST_VECTOR:
2046 case CC0:
2047 case PC:
2048 case REG:
2049 case SCRATCH:
2050 case ADDR_VEC:
2051 case ADDR_DIFF_VEC:
2052 return 0;
2053
2054 case CLOBBER:
2055 /* Reject CLOBBER with a non-VOID mode. These are made by combine.c
2056 when some combination can't be done. If we see one, don't think
2057 that we can simplify the expression. */
2058 return (GET_MODE (x) != VOIDmode);
2059
2060 case PRE_INC:
2061 case PRE_DEC:
2062 case POST_INC:
2063 case POST_DEC:
2064 case PRE_MODIFY:
2065 case POST_MODIFY:
2066 case CALL:
2067 case UNSPEC_VOLATILE:
2068 /* case TRAP_IF: This isn't clear yet. */
2069 return 1;
2070
2071 case MEM:
2072 case ASM_INPUT:
2073 case ASM_OPERANDS:
2074 if (MEM_VOLATILE_P (x))
2075 return 1;
2076
2077 default:
2078 break;
2079 }
2080
2081 /* Recursively scan the operands of this expression. */
2082
2083 {
2084 const char *fmt = GET_RTX_FORMAT (code);
2085 int i;
2086
2087 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2088 {
2089 if (fmt[i] == 'e')
2090 {
2091 if (side_effects_p (XEXP (x, i)))
2092 return 1;
2093 }
2094 else if (fmt[i] == 'E')
2095 {
2096 int j;
2097 for (j = 0; j < XVECLEN (x, i); j++)
2098 if (side_effects_p (XVECEXP (x, i, j)))
2099 return 1;
2100 }
2101 }
2102 }
2103 return 0;
2104 }
2105
2106 /* Return nonzero if evaluating rtx X might cause a trap. UNALIGNED_MEMS
2107 controls whether nonzero is returned for unaligned memory accesses on
2108 strict alignment machines. */
2109
2110 static int
may_trap_p_1(rtx x,bool unaligned_mems)2111 may_trap_p_1 (rtx x, bool unaligned_mems)
2112 {
2113 int i;
2114 enum rtx_code code;
2115 const char *fmt;
2116
2117 if (x == 0)
2118 return 0;
2119 code = GET_CODE (x);
2120 switch (code)
2121 {
2122 /* Handle these cases quickly. */
2123 case CONST_INT:
2124 case CONST_DOUBLE:
2125 case CONST_VECTOR:
2126 case SYMBOL_REF:
2127 case LABEL_REF:
2128 case CONST:
2129 case PC:
2130 case CC0:
2131 case REG:
2132 case SCRATCH:
2133 return 0;
2134
2135 case ASM_INPUT:
2136 case UNSPEC_VOLATILE:
2137 case TRAP_IF:
2138 return 1;
2139
2140 case ASM_OPERANDS:
2141 return MEM_VOLATILE_P (x);
2142
2143 /* Memory ref can trap unless it's a static var or a stack slot. */
2144 case MEM:
2145 if (MEM_NOTRAP_P (x)
2146 && (!STRICT_ALIGNMENT || !unaligned_mems))
2147 return 0;
2148 return
2149 rtx_addr_can_trap_p_1 (XEXP (x, 0), GET_MODE (x), unaligned_mems);
2150
2151 /* Division by a non-constant might trap. */
2152 case DIV:
2153 case MOD:
2154 case UDIV:
2155 case UMOD:
2156 if (HONOR_SNANS (GET_MODE (x)))
2157 return 1;
2158 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2159 return flag_trapping_math;
2160 if (!CONSTANT_P (XEXP (x, 1)) || (XEXP (x, 1) == const0_rtx))
2161 return 1;
2162 break;
2163
2164 case EXPR_LIST:
2165 /* An EXPR_LIST is used to represent a function call. This
2166 certainly may trap. */
2167 return 1;
2168
2169 case GE:
2170 case GT:
2171 case LE:
2172 case LT:
2173 case LTGT:
2174 case COMPARE:
2175 /* Some floating point comparisons may trap. */
2176 if (!flag_trapping_math)
2177 break;
2178 /* ??? There is no machine independent way to check for tests that trap
2179 when COMPARE is used, though many targets do make this distinction.
2180 For instance, sparc uses CCFPE for compares which generate exceptions
2181 and CCFP for compares which do not generate exceptions. */
2182 if (HONOR_NANS (GET_MODE (x)))
2183 return 1;
2184 /* But often the compare has some CC mode, so check operand
2185 modes as well. */
2186 if (HONOR_NANS (GET_MODE (XEXP (x, 0)))
2187 || HONOR_NANS (GET_MODE (XEXP (x, 1))))
2188 return 1;
2189 break;
2190
2191 case EQ:
2192 case NE:
2193 if (HONOR_SNANS (GET_MODE (x)))
2194 return 1;
2195 /* Often comparison is CC mode, so check operand modes. */
2196 if (HONOR_SNANS (GET_MODE (XEXP (x, 0)))
2197 || HONOR_SNANS (GET_MODE (XEXP (x, 1))))
2198 return 1;
2199 break;
2200
2201 case FIX:
2202 /* Conversion of floating point might trap. */
2203 if (flag_trapping_math && HONOR_NANS (GET_MODE (XEXP (x, 0))))
2204 return 1;
2205 break;
2206
2207 case NEG:
2208 case ABS:
2209 case SUBREG:
2210 /* These operations don't trap even with floating point. */
2211 break;
2212
2213 default:
2214 /* Any floating arithmetic may trap. */
2215 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT
2216 && flag_trapping_math)
2217 return 1;
2218 }
2219
2220 fmt = GET_RTX_FORMAT (code);
2221 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2222 {
2223 if (fmt[i] == 'e')
2224 {
2225 if (may_trap_p_1 (XEXP (x, i), unaligned_mems))
2226 return 1;
2227 }
2228 else if (fmt[i] == 'E')
2229 {
2230 int j;
2231 for (j = 0; j < XVECLEN (x, i); j++)
2232 if (may_trap_p_1 (XVECEXP (x, i, j), unaligned_mems))
2233 return 1;
2234 }
2235 }
2236 return 0;
2237 }
2238
2239 /* Return nonzero if evaluating rtx X might cause a trap. */
2240
2241 int
may_trap_p(rtx x)2242 may_trap_p (rtx x)
2243 {
2244 return may_trap_p_1 (x, false);
2245 }
2246
2247 /* Same as above, but additionally return non-zero if evaluating rtx X might
2248 cause a fault. We define a fault for the purpose of this function as a
2249 erroneous execution condition that cannot be encountered during the normal
2250 execution of a valid program; the typical example is an unaligned memory
2251 access on a strict alignment machine. The compiler guarantees that it
2252 doesn't generate code that will fault from a valid program, but this
2253 guarantee doesn't mean anything for individual instructions. Consider
2254 the following example:
2255
2256 struct S { int d; union { char *cp; int *ip; }; };
2257
2258 int foo(struct S *s)
2259 {
2260 if (s->d == 1)
2261 return *s->ip;
2262 else
2263 return *s->cp;
2264 }
2265
2266 on a strict alignment machine. In a valid program, foo will never be
2267 invoked on a structure for which d is equal to 1 and the underlying
2268 unique field of the union not aligned on a 4-byte boundary, but the
2269 expression *s->ip might cause a fault if considered individually.
2270
2271 At the RTL level, potentially problematic expressions will almost always
2272 verify may_trap_p; for example, the above dereference can be emitted as
2273 (mem:SI (reg:P)) and this expression is may_trap_p for a generic register.
2274 However, suppose that foo is inlined in a caller that causes s->cp to
2275 point to a local character variable and guarantees that s->d is not set
2276 to 1; foo may have been effectively translated into pseudo-RTL as:
2277
2278 if ((reg:SI) == 1)
2279 (set (reg:SI) (mem:SI (%fp - 7)))
2280 else
2281 (set (reg:QI) (mem:QI (%fp - 7)))
2282
2283 Now (mem:SI (%fp - 7)) is considered as not may_trap_p since it is a
2284 memory reference to a stack slot, but it will certainly cause a fault
2285 on a strict alignment machine. */
2286
2287 int
may_trap_or_fault_p(rtx x)2288 may_trap_or_fault_p (rtx x)
2289 {
2290 return may_trap_p_1 (x, true);
2291 }
2292
2293 /* Return nonzero if X contains a comparison that is not either EQ or NE,
2294 i.e., an inequality. */
2295
2296 int
inequality_comparisons_p(rtx x)2297 inequality_comparisons_p (rtx x)
2298 {
2299 const char *fmt;
2300 int len, i;
2301 enum rtx_code code = GET_CODE (x);
2302
2303 switch (code)
2304 {
2305 case REG:
2306 case SCRATCH:
2307 case PC:
2308 case CC0:
2309 case CONST_INT:
2310 case CONST_DOUBLE:
2311 case CONST_VECTOR:
2312 case CONST:
2313 case LABEL_REF:
2314 case SYMBOL_REF:
2315 return 0;
2316
2317 case LT:
2318 case LTU:
2319 case GT:
2320 case GTU:
2321 case LE:
2322 case LEU:
2323 case GE:
2324 case GEU:
2325 return 1;
2326
2327 default:
2328 break;
2329 }
2330
2331 len = GET_RTX_LENGTH (code);
2332 fmt = GET_RTX_FORMAT (code);
2333
2334 for (i = 0; i < len; i++)
2335 {
2336 if (fmt[i] == 'e')
2337 {
2338 if (inequality_comparisons_p (XEXP (x, i)))
2339 return 1;
2340 }
2341 else if (fmt[i] == 'E')
2342 {
2343 int j;
2344 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2345 if (inequality_comparisons_p (XVECEXP (x, i, j)))
2346 return 1;
2347 }
2348 }
2349
2350 return 0;
2351 }
2352
2353 /* Replace any occurrence of FROM in X with TO. The function does
2354 not enter into CONST_DOUBLE for the replace.
2355
2356 Note that copying is not done so X must not be shared unless all copies
2357 are to be modified. */
2358
2359 rtx
replace_rtx(rtx x,rtx from,rtx to)2360 replace_rtx (rtx x, rtx from, rtx to)
2361 {
2362 int i, j;
2363 const char *fmt;
2364
2365 /* The following prevents loops occurrence when we change MEM in
2366 CONST_DOUBLE onto the same CONST_DOUBLE. */
2367 if (x != 0 && GET_CODE (x) == CONST_DOUBLE)
2368 return x;
2369
2370 if (x == from)
2371 return to;
2372
2373 /* Allow this function to make replacements in EXPR_LISTs. */
2374 if (x == 0)
2375 return 0;
2376
2377 if (GET_CODE (x) == SUBREG)
2378 {
2379 rtx new = replace_rtx (SUBREG_REG (x), from, to);
2380
2381 if (GET_CODE (new) == CONST_INT)
2382 {
2383 x = simplify_subreg (GET_MODE (x), new,
2384 GET_MODE (SUBREG_REG (x)),
2385 SUBREG_BYTE (x));
2386 gcc_assert (x);
2387 }
2388 else
2389 SUBREG_REG (x) = new;
2390
2391 return x;
2392 }
2393 else if (GET_CODE (x) == ZERO_EXTEND)
2394 {
2395 rtx new = replace_rtx (XEXP (x, 0), from, to);
2396
2397 if (GET_CODE (new) == CONST_INT)
2398 {
2399 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
2400 new, GET_MODE (XEXP (x, 0)));
2401 gcc_assert (x);
2402 }
2403 else
2404 XEXP (x, 0) = new;
2405
2406 return x;
2407 }
2408
2409 fmt = GET_RTX_FORMAT (GET_CODE (x));
2410 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
2411 {
2412 if (fmt[i] == 'e')
2413 XEXP (x, i) = replace_rtx (XEXP (x, i), from, to);
2414 else if (fmt[i] == 'E')
2415 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2416 XVECEXP (x, i, j) = replace_rtx (XVECEXP (x, i, j), from, to);
2417 }
2418
2419 return x;
2420 }
2421
2422 /* Throughout the rtx X, replace many registers according to REG_MAP.
2423 Return the replacement for X (which may be X with altered contents).
2424 REG_MAP[R] is the replacement for register R, or 0 for don't replace.
2425 NREGS is the length of REG_MAP; regs >= NREGS are not mapped.
2426
2427 We only support REG_MAP entries of REG or SUBREG. Also, hard registers
2428 should not be mapped to pseudos or vice versa since validate_change
2429 is not called.
2430
2431 If REPLACE_DEST is 1, replacements are also done in destinations;
2432 otherwise, only sources are replaced. */
2433
2434 rtx
replace_regs(rtx x,rtx * reg_map,unsigned int nregs,int replace_dest)2435 replace_regs (rtx x, rtx *reg_map, unsigned int nregs, int replace_dest)
2436 {
2437 enum rtx_code code;
2438 int i;
2439 const char *fmt;
2440
2441 if (x == 0)
2442 return x;
2443
2444 code = GET_CODE (x);
2445 switch (code)
2446 {
2447 case SCRATCH:
2448 case PC:
2449 case CC0:
2450 case CONST_INT:
2451 case CONST_DOUBLE:
2452 case CONST_VECTOR:
2453 case CONST:
2454 case SYMBOL_REF:
2455 case LABEL_REF:
2456 return x;
2457
2458 case REG:
2459 /* Verify that the register has an entry before trying to access it. */
2460 if (REGNO (x) < nregs && reg_map[REGNO (x)] != 0)
2461 {
2462 /* SUBREGs can't be shared. Always return a copy to ensure that if
2463 this replacement occurs more than once then each instance will
2464 get distinct rtx. */
2465 if (GET_CODE (reg_map[REGNO (x)]) == SUBREG)
2466 return copy_rtx (reg_map[REGNO (x)]);
2467 return reg_map[REGNO (x)];
2468 }
2469 return x;
2470
2471 case SUBREG:
2472 /* Prevent making nested SUBREGs. */
2473 if (REG_P (SUBREG_REG (x)) && REGNO (SUBREG_REG (x)) < nregs
2474 && reg_map[REGNO (SUBREG_REG (x))] != 0
2475 && GET_CODE (reg_map[REGNO (SUBREG_REG (x))]) == SUBREG)
2476 {
2477 rtx map_val = reg_map[REGNO (SUBREG_REG (x))];
2478 return simplify_gen_subreg (GET_MODE (x), map_val,
2479 GET_MODE (SUBREG_REG (x)),
2480 SUBREG_BYTE (x));
2481 }
2482 break;
2483
2484 case SET:
2485 if (replace_dest)
2486 SET_DEST (x) = replace_regs (SET_DEST (x), reg_map, nregs, 0);
2487
2488 else if (MEM_P (SET_DEST (x))
2489 || GET_CODE (SET_DEST (x)) == STRICT_LOW_PART)
2490 /* Even if we are not to replace destinations, replace register if it
2491 is CONTAINED in destination (destination is memory or
2492 STRICT_LOW_PART). */
2493 XEXP (SET_DEST (x), 0) = replace_regs (XEXP (SET_DEST (x), 0),
2494 reg_map, nregs, 0);
2495 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT)
2496 /* Similarly, for ZERO_EXTRACT we replace all operands. */
2497 break;
2498
2499 SET_SRC (x) = replace_regs (SET_SRC (x), reg_map, nregs, 0);
2500 return x;
2501
2502 default:
2503 break;
2504 }
2505
2506 fmt = GET_RTX_FORMAT (code);
2507 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2508 {
2509 if (fmt[i] == 'e')
2510 XEXP (x, i) = replace_regs (XEXP (x, i), reg_map, nregs, replace_dest);
2511 else if (fmt[i] == 'E')
2512 {
2513 int j;
2514 for (j = 0; j < XVECLEN (x, i); j++)
2515 XVECEXP (x, i, j) = replace_regs (XVECEXP (x, i, j), reg_map,
2516 nregs, replace_dest);
2517 }
2518 }
2519 return x;
2520 }
2521
2522 /* Replace occurrences of the old label in *X with the new one.
2523 DATA is a REPLACE_LABEL_DATA containing the old and new labels. */
2524
2525 int
replace_label(rtx * x,void * data)2526 replace_label (rtx *x, void *data)
2527 {
2528 rtx l = *x;
2529 rtx old_label = ((replace_label_data *) data)->r1;
2530 rtx new_label = ((replace_label_data *) data)->r2;
2531 bool update_label_nuses = ((replace_label_data *) data)->update_label_nuses;
2532
2533 if (l == NULL_RTX)
2534 return 0;
2535
2536 if (GET_CODE (l) == SYMBOL_REF
2537 && CONSTANT_POOL_ADDRESS_P (l))
2538 {
2539 rtx c = get_pool_constant (l);
2540 if (rtx_referenced_p (old_label, c))
2541 {
2542 rtx new_c, new_l;
2543 replace_label_data *d = (replace_label_data *) data;
2544
2545 /* Create a copy of constant C; replace the label inside
2546 but do not update LABEL_NUSES because uses in constant pool
2547 are not counted. */
2548 new_c = copy_rtx (c);
2549 d->update_label_nuses = false;
2550 for_each_rtx (&new_c, replace_label, data);
2551 d->update_label_nuses = update_label_nuses;
2552
2553 /* Add the new constant NEW_C to constant pool and replace
2554 the old reference to constant by new reference. */
2555 new_l = XEXP (force_const_mem (get_pool_mode (l), new_c), 0);
2556 *x = replace_rtx (l, l, new_l);
2557 }
2558 return 0;
2559 }
2560
2561 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
2562 field. This is not handled by for_each_rtx because it doesn't
2563 handle unprinted ('0') fields. */
2564 if (JUMP_P (l) && JUMP_LABEL (l) == old_label)
2565 JUMP_LABEL (l) = new_label;
2566
2567 if ((GET_CODE (l) == LABEL_REF
2568 || GET_CODE (l) == INSN_LIST)
2569 && XEXP (l, 0) == old_label)
2570 {
2571 XEXP (l, 0) = new_label;
2572 if (update_label_nuses)
2573 {
2574 ++LABEL_NUSES (new_label);
2575 --LABEL_NUSES (old_label);
2576 }
2577 return 0;
2578 }
2579
2580 return 0;
2581 }
2582
2583 /* When *BODY is equal to X or X is directly referenced by *BODY
2584 return nonzero, thus FOR_EACH_RTX stops traversing and returns nonzero
2585 too, otherwise FOR_EACH_RTX continues traversing *BODY. */
2586
2587 static int
rtx_referenced_p_1(rtx * body,void * x)2588 rtx_referenced_p_1 (rtx *body, void *x)
2589 {
2590 rtx y = (rtx) x;
2591
2592 if (*body == NULL_RTX)
2593 return y == NULL_RTX;
2594
2595 /* Return true if a label_ref *BODY refers to label Y. */
2596 if (GET_CODE (*body) == LABEL_REF && LABEL_P (y))
2597 return XEXP (*body, 0) == y;
2598
2599 /* If *BODY is a reference to pool constant traverse the constant. */
2600 if (GET_CODE (*body) == SYMBOL_REF
2601 && CONSTANT_POOL_ADDRESS_P (*body))
2602 return rtx_referenced_p (y, get_pool_constant (*body));
2603
2604 /* By default, compare the RTL expressions. */
2605 return rtx_equal_p (*body, y);
2606 }
2607
2608 /* Return true if X is referenced in BODY. */
2609
2610 int
rtx_referenced_p(rtx x,rtx body)2611 rtx_referenced_p (rtx x, rtx body)
2612 {
2613 return for_each_rtx (&body, rtx_referenced_p_1, x);
2614 }
2615
2616 /* If INSN is a tablejump return true and store the label (before jump table) to
2617 *LABELP and the jump table to *TABLEP. LABELP and TABLEP may be NULL. */
2618
2619 bool
tablejump_p(rtx insn,rtx * labelp,rtx * tablep)2620 tablejump_p (rtx insn, rtx *labelp, rtx *tablep)
2621 {
2622 rtx label, table;
2623
2624 if (JUMP_P (insn)
2625 && (label = JUMP_LABEL (insn)) != NULL_RTX
2626 && (table = next_active_insn (label)) != NULL_RTX
2627 && JUMP_P (table)
2628 && (GET_CODE (PATTERN (table)) == ADDR_VEC
2629 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
2630 {
2631 if (labelp)
2632 *labelp = label;
2633 if (tablep)
2634 *tablep = table;
2635 return true;
2636 }
2637 return false;
2638 }
2639
2640 /* A subroutine of computed_jump_p, return 1 if X contains a REG or MEM or
2641 constant that is not in the constant pool and not in the condition
2642 of an IF_THEN_ELSE. */
2643
2644 static int
computed_jump_p_1(rtx x)2645 computed_jump_p_1 (rtx x)
2646 {
2647 enum rtx_code code = GET_CODE (x);
2648 int i, j;
2649 const char *fmt;
2650
2651 switch (code)
2652 {
2653 case LABEL_REF:
2654 case PC:
2655 return 0;
2656
2657 case CONST:
2658 case CONST_INT:
2659 case CONST_DOUBLE:
2660 case CONST_VECTOR:
2661 case SYMBOL_REF:
2662 case REG:
2663 return 1;
2664
2665 case MEM:
2666 return ! (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
2667 && CONSTANT_POOL_ADDRESS_P (XEXP (x, 0)));
2668
2669 case IF_THEN_ELSE:
2670 return (computed_jump_p_1 (XEXP (x, 1))
2671 || computed_jump_p_1 (XEXP (x, 2)));
2672
2673 default:
2674 break;
2675 }
2676
2677 fmt = GET_RTX_FORMAT (code);
2678 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2679 {
2680 if (fmt[i] == 'e'
2681 && computed_jump_p_1 (XEXP (x, i)))
2682 return 1;
2683
2684 else if (fmt[i] == 'E')
2685 for (j = 0; j < XVECLEN (x, i); j++)
2686 if (computed_jump_p_1 (XVECEXP (x, i, j)))
2687 return 1;
2688 }
2689
2690 return 0;
2691 }
2692
2693 /* Return nonzero if INSN is an indirect jump (aka computed jump).
2694
2695 Tablejumps and casesi insns are not considered indirect jumps;
2696 we can recognize them by a (use (label_ref)). */
2697
2698 int
computed_jump_p(rtx insn)2699 computed_jump_p (rtx insn)
2700 {
2701 int i;
2702 if (JUMP_P (insn))
2703 {
2704 rtx pat = PATTERN (insn);
2705
2706 if (find_reg_note (insn, REG_LABEL, NULL_RTX))
2707 return 0;
2708 else if (GET_CODE (pat) == PARALLEL)
2709 {
2710 int len = XVECLEN (pat, 0);
2711 int has_use_labelref = 0;
2712
2713 for (i = len - 1; i >= 0; i--)
2714 if (GET_CODE (XVECEXP (pat, 0, i)) == USE
2715 && (GET_CODE (XEXP (XVECEXP (pat, 0, i), 0))
2716 == LABEL_REF))
2717 has_use_labelref = 1;
2718
2719 if (! has_use_labelref)
2720 for (i = len - 1; i >= 0; i--)
2721 if (GET_CODE (XVECEXP (pat, 0, i)) == SET
2722 && SET_DEST (XVECEXP (pat, 0, i)) == pc_rtx
2723 && computed_jump_p_1 (SET_SRC (XVECEXP (pat, 0, i))))
2724 return 1;
2725 }
2726 else if (GET_CODE (pat) == SET
2727 && SET_DEST (pat) == pc_rtx
2728 && computed_jump_p_1 (SET_SRC (pat)))
2729 return 1;
2730 }
2731 return 0;
2732 }
2733
2734 /* Optimized loop of for_each_rtx, trying to avoid useless recursive
2735 calls. Processes the subexpressions of EXP and passes them to F. */
2736 static int
for_each_rtx_1(rtx exp,int n,rtx_function f,void * data)2737 for_each_rtx_1 (rtx exp, int n, rtx_function f, void *data)
2738 {
2739 int result, i, j;
2740 const char *format = GET_RTX_FORMAT (GET_CODE (exp));
2741 rtx *x;
2742
2743 for (; format[n] != '\0'; n++)
2744 {
2745 switch (format[n])
2746 {
2747 case 'e':
2748 /* Call F on X. */
2749 x = &XEXP (exp, n);
2750 result = (*f) (x, data);
2751 if (result == -1)
2752 /* Do not traverse sub-expressions. */
2753 continue;
2754 else if (result != 0)
2755 /* Stop the traversal. */
2756 return result;
2757
2758 if (*x == NULL_RTX)
2759 /* There are no sub-expressions. */
2760 continue;
2761
2762 i = non_rtx_starting_operands[GET_CODE (*x)];
2763 if (i >= 0)
2764 {
2765 result = for_each_rtx_1 (*x, i, f, data);
2766 if (result != 0)
2767 return result;
2768 }
2769 break;
2770
2771 case 'V':
2772 case 'E':
2773 if (XVEC (exp, n) == 0)
2774 continue;
2775 for (j = 0; j < XVECLEN (exp, n); ++j)
2776 {
2777 /* Call F on X. */
2778 x = &XVECEXP (exp, n, j);
2779 result = (*f) (x, data);
2780 if (result == -1)
2781 /* Do not traverse sub-expressions. */
2782 continue;
2783 else if (result != 0)
2784 /* Stop the traversal. */
2785 return result;
2786
2787 if (*x == NULL_RTX)
2788 /* There are no sub-expressions. */
2789 continue;
2790
2791 i = non_rtx_starting_operands[GET_CODE (*x)];
2792 if (i >= 0)
2793 {
2794 result = for_each_rtx_1 (*x, i, f, data);
2795 if (result != 0)
2796 return result;
2797 }
2798 }
2799 break;
2800
2801 default:
2802 /* Nothing to do. */
2803 break;
2804 }
2805 }
2806
2807 return 0;
2808 }
2809
2810 /* Traverse X via depth-first search, calling F for each
2811 sub-expression (including X itself). F is also passed the DATA.
2812 If F returns -1, do not traverse sub-expressions, but continue
2813 traversing the rest of the tree. If F ever returns any other
2814 nonzero value, stop the traversal, and return the value returned
2815 by F. Otherwise, return 0. This function does not traverse inside
2816 tree structure that contains RTX_EXPRs, or into sub-expressions
2817 whose format code is `0' since it is not known whether or not those
2818 codes are actually RTL.
2819
2820 This routine is very general, and could (should?) be used to
2821 implement many of the other routines in this file. */
2822
2823 int
for_each_rtx(rtx * x,rtx_function f,void * data)2824 for_each_rtx (rtx *x, rtx_function f, void *data)
2825 {
2826 int result;
2827 int i;
2828
2829 /* Call F on X. */
2830 result = (*f) (x, data);
2831 if (result == -1)
2832 /* Do not traverse sub-expressions. */
2833 return 0;
2834 else if (result != 0)
2835 /* Stop the traversal. */
2836 return result;
2837
2838 if (*x == NULL_RTX)
2839 /* There are no sub-expressions. */
2840 return 0;
2841
2842 i = non_rtx_starting_operands[GET_CODE (*x)];
2843 if (i < 0)
2844 return 0;
2845
2846 return for_each_rtx_1 (*x, i, f, data);
2847 }
2848
2849
2850 /* Searches X for any reference to REGNO, returning the rtx of the
2851 reference found if any. Otherwise, returns NULL_RTX. */
2852
2853 rtx
regno_use_in(unsigned int regno,rtx x)2854 regno_use_in (unsigned int regno, rtx x)
2855 {
2856 const char *fmt;
2857 int i, j;
2858 rtx tem;
2859
2860 if (REG_P (x) && REGNO (x) == regno)
2861 return x;
2862
2863 fmt = GET_RTX_FORMAT (GET_CODE (x));
2864 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
2865 {
2866 if (fmt[i] == 'e')
2867 {
2868 if ((tem = regno_use_in (regno, XEXP (x, i))))
2869 return tem;
2870 }
2871 else if (fmt[i] == 'E')
2872 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2873 if ((tem = regno_use_in (regno , XVECEXP (x, i, j))))
2874 return tem;
2875 }
2876
2877 return NULL_RTX;
2878 }
2879
2880 /* Return a value indicating whether OP, an operand of a commutative
2881 operation, is preferred as the first or second operand. The higher
2882 the value, the stronger the preference for being the first operand.
2883 We use negative values to indicate a preference for the first operand
2884 and positive values for the second operand. */
2885
2886 int
commutative_operand_precedence(rtx op)2887 commutative_operand_precedence (rtx op)
2888 {
2889 enum rtx_code code = GET_CODE (op);
2890
2891 /* Constants always come the second operand. Prefer "nice" constants. */
2892 if (code == CONST_INT)
2893 return -7;
2894 if (code == CONST_DOUBLE)
2895 return -6;
2896 op = avoid_constant_pool_reference (op);
2897 code = GET_CODE (op);
2898
2899 switch (GET_RTX_CLASS (code))
2900 {
2901 case RTX_CONST_OBJ:
2902 if (code == CONST_INT)
2903 return -5;
2904 if (code == CONST_DOUBLE)
2905 return -4;
2906 return -3;
2907
2908 case RTX_EXTRA:
2909 /* SUBREGs of objects should come second. */
2910 if (code == SUBREG && OBJECT_P (SUBREG_REG (op)))
2911 return -2;
2912
2913 if (!CONSTANT_P (op))
2914 return 0;
2915 else
2916 /* As for RTX_CONST_OBJ. */
2917 return -3;
2918
2919 case RTX_OBJ:
2920 /* Complex expressions should be the first, so decrease priority
2921 of objects. */
2922 return -1;
2923
2924 case RTX_COMM_ARITH:
2925 /* Prefer operands that are themselves commutative to be first.
2926 This helps to make things linear. In particular,
2927 (and (and (reg) (reg)) (not (reg))) is canonical. */
2928 return 4;
2929
2930 case RTX_BIN_ARITH:
2931 /* If only one operand is a binary expression, it will be the first
2932 operand. In particular, (plus (minus (reg) (reg)) (neg (reg)))
2933 is canonical, although it will usually be further simplified. */
2934 return 2;
2935
2936 case RTX_UNARY:
2937 /* Then prefer NEG and NOT. */
2938 if (code == NEG || code == NOT)
2939 return 1;
2940
2941 default:
2942 return 0;
2943 }
2944 }
2945
2946 /* Return 1 iff it is necessary to swap operands of commutative operation
2947 in order to canonicalize expression. */
2948
2949 int
swap_commutative_operands_p(rtx x,rtx y)2950 swap_commutative_operands_p (rtx x, rtx y)
2951 {
2952 return (commutative_operand_precedence (x)
2953 < commutative_operand_precedence (y));
2954 }
2955
2956 /* Return 1 if X is an autoincrement side effect and the register is
2957 not the stack pointer. */
2958 int
auto_inc_p(rtx x)2959 auto_inc_p (rtx x)
2960 {
2961 switch (GET_CODE (x))
2962 {
2963 case PRE_INC:
2964 case POST_INC:
2965 case PRE_DEC:
2966 case POST_DEC:
2967 case PRE_MODIFY:
2968 case POST_MODIFY:
2969 /* There are no REG_INC notes for SP. */
2970 if (XEXP (x, 0) != stack_pointer_rtx)
2971 return 1;
2972 default:
2973 break;
2974 }
2975 return 0;
2976 }
2977
2978 /* Return 1 if the sequence of instructions beginning with FROM and up
2979 to and including TO is safe to move. If NEW_TO is non-NULL, and
2980 the sequence is not already safe to move, but can be easily
2981 extended to a sequence which is safe, then NEW_TO will point to the
2982 end of the extended sequence.
2983
2984 For now, this function only checks that the region contains whole
2985 exception regions, but it could be extended to check additional
2986 conditions as well. */
2987
2988 int
insns_safe_to_move_p(rtx from,rtx to,rtx * new_to)2989 insns_safe_to_move_p (rtx from, rtx to, rtx *new_to)
2990 {
2991 int eh_region_count = 0;
2992 int past_to_p = 0;
2993 rtx r = from;
2994
2995 /* By default, assume the end of the region will be what was
2996 suggested. */
2997 if (new_to)
2998 *new_to = to;
2999
3000 while (r)
3001 {
3002 if (NOTE_P (r))
3003 {
3004 switch (NOTE_LINE_NUMBER (r))
3005 {
3006 case NOTE_INSN_EH_REGION_BEG:
3007 ++eh_region_count;
3008 break;
3009
3010 case NOTE_INSN_EH_REGION_END:
3011 if (eh_region_count == 0)
3012 /* This sequence of instructions contains the end of
3013 an exception region, but not he beginning. Moving
3014 it will cause chaos. */
3015 return 0;
3016
3017 --eh_region_count;
3018 break;
3019
3020 default:
3021 break;
3022 }
3023 }
3024 else if (past_to_p)
3025 /* If we've passed TO, and we see a non-note instruction, we
3026 can't extend the sequence to a movable sequence. */
3027 return 0;
3028
3029 if (r == to)
3030 {
3031 if (!new_to)
3032 /* It's OK to move the sequence if there were matched sets of
3033 exception region notes. */
3034 return eh_region_count == 0;
3035
3036 past_to_p = 1;
3037 }
3038
3039 /* It's OK to move the sequence if there were matched sets of
3040 exception region notes. */
3041 if (past_to_p && eh_region_count == 0)
3042 {
3043 *new_to = r;
3044 return 1;
3045 }
3046
3047 /* Go to the next instruction. */
3048 r = NEXT_INSN (r);
3049 }
3050
3051 return 0;
3052 }
3053
3054 /* Return nonzero if IN contains a piece of rtl that has the address LOC. */
3055 int
loc_mentioned_in_p(rtx * loc,rtx in)3056 loc_mentioned_in_p (rtx *loc, rtx in)
3057 {
3058 enum rtx_code code = GET_CODE (in);
3059 const char *fmt = GET_RTX_FORMAT (code);
3060 int i, j;
3061
3062 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3063 {
3064 if (loc == &in->u.fld[i].rt_rtx)
3065 return 1;
3066 if (fmt[i] == 'e')
3067 {
3068 if (loc_mentioned_in_p (loc, XEXP (in, i)))
3069 return 1;
3070 }
3071 else if (fmt[i] == 'E')
3072 for (j = XVECLEN (in, i) - 1; j >= 0; j--)
3073 if (loc_mentioned_in_p (loc, XVECEXP (in, i, j)))
3074 return 1;
3075 }
3076 return 0;
3077 }
3078
3079 /* Helper function for subreg_lsb. Given a subreg's OUTER_MODE, INNER_MODE,
3080 and SUBREG_BYTE, return the bit offset where the subreg begins
3081 (counting from the least significant bit of the operand). */
3082
3083 unsigned int
subreg_lsb_1(enum machine_mode outer_mode,enum machine_mode inner_mode,unsigned int subreg_byte)3084 subreg_lsb_1 (enum machine_mode outer_mode,
3085 enum machine_mode inner_mode,
3086 unsigned int subreg_byte)
3087 {
3088 unsigned int bitpos;
3089 unsigned int byte;
3090 unsigned int word;
3091
3092 /* A paradoxical subreg begins at bit position 0. */
3093 if (GET_MODE_BITSIZE (outer_mode) > GET_MODE_BITSIZE (inner_mode))
3094 return 0;
3095
3096 if (WORDS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
3097 /* If the subreg crosses a word boundary ensure that
3098 it also begins and ends on a word boundary. */
3099 gcc_assert (!((subreg_byte % UNITS_PER_WORD
3100 + GET_MODE_SIZE (outer_mode)) > UNITS_PER_WORD
3101 && (subreg_byte % UNITS_PER_WORD
3102 || GET_MODE_SIZE (outer_mode) % UNITS_PER_WORD)));
3103
3104 if (WORDS_BIG_ENDIAN)
3105 word = (GET_MODE_SIZE (inner_mode)
3106 - (subreg_byte + GET_MODE_SIZE (outer_mode))) / UNITS_PER_WORD;
3107 else
3108 word = subreg_byte / UNITS_PER_WORD;
3109 bitpos = word * BITS_PER_WORD;
3110
3111 if (BYTES_BIG_ENDIAN)
3112 byte = (GET_MODE_SIZE (inner_mode)
3113 - (subreg_byte + GET_MODE_SIZE (outer_mode))) % UNITS_PER_WORD;
3114 else
3115 byte = subreg_byte % UNITS_PER_WORD;
3116 bitpos += byte * BITS_PER_UNIT;
3117
3118 return bitpos;
3119 }
3120
3121 /* Given a subreg X, return the bit offset where the subreg begins
3122 (counting from the least significant bit of the reg). */
3123
3124 unsigned int
subreg_lsb(rtx x)3125 subreg_lsb (rtx x)
3126 {
3127 return subreg_lsb_1 (GET_MODE (x), GET_MODE (SUBREG_REG (x)),
3128 SUBREG_BYTE (x));
3129 }
3130
3131 /* This function returns the regno offset of a subreg expression.
3132 xregno - A regno of an inner hard subreg_reg (or what will become one).
3133 xmode - The mode of xregno.
3134 offset - The byte offset.
3135 ymode - The mode of a top level SUBREG (or what may become one).
3136 RETURN - The regno offset which would be used. */
3137 unsigned int
subreg_regno_offset(unsigned int xregno,enum machine_mode xmode,unsigned int offset,enum machine_mode ymode)3138 subreg_regno_offset (unsigned int xregno, enum machine_mode xmode,
3139 unsigned int offset, enum machine_mode ymode)
3140 {
3141 int nregs_xmode, nregs_ymode, nregs_xmode_unit_int;
3142 int mode_multiple, nregs_multiple;
3143 int y_offset;
3144 enum machine_mode xmode_unit, xmode_unit_int;
3145
3146 gcc_assert (xregno < FIRST_PSEUDO_REGISTER);
3147
3148 if (GET_MODE_INNER (xmode) == VOIDmode)
3149 xmode_unit = xmode;
3150 else
3151 xmode_unit = GET_MODE_INNER (xmode);
3152
3153 if (FLOAT_MODE_P (xmode_unit))
3154 {
3155 xmode_unit_int = int_mode_for_mode (xmode_unit);
3156 if (xmode_unit_int == BLKmode)
3157 /* It's probably bad to be here; a port should have an integer mode
3158 that's the same size as anything of which it takes a SUBREG. */
3159 xmode_unit_int = xmode_unit;
3160 }
3161 else
3162 xmode_unit_int = xmode_unit;
3163
3164 nregs_xmode_unit_int = hard_regno_nregs[xregno][xmode_unit_int];
3165
3166 /* Adjust nregs_xmode to allow for 'holes'. */
3167 if (nregs_xmode_unit_int != hard_regno_nregs[xregno][xmode_unit])
3168 nregs_xmode = nregs_xmode_unit_int * GET_MODE_NUNITS (xmode);
3169 else
3170 nregs_xmode = hard_regno_nregs[xregno][xmode];
3171
3172 nregs_ymode = hard_regno_nregs[xregno][ymode];
3173
3174 /* If this is a big endian paradoxical subreg, which uses more actual
3175 hard registers than the original register, we must return a negative
3176 offset so that we find the proper highpart of the register. */
3177 if (offset == 0
3178 && nregs_ymode > nregs_xmode
3179 && (GET_MODE_SIZE (ymode) > UNITS_PER_WORD
3180 ? WORDS_BIG_ENDIAN : BYTES_BIG_ENDIAN))
3181 return nregs_xmode - nregs_ymode;
3182
3183 if (offset == 0 || nregs_xmode == nregs_ymode)
3184 return 0;
3185
3186 /* (TIGCC 20050324) Subregs of a 10-byte mode are special, hardcode them. */
3187 if (GET_MODE_SIZE (xmode) == 10)
3188 {
3189 gcc_assert (nregs_xmode == 3);
3190
3191 if (offset < 4)
3192 return 0;
3193 else if (offset < 8)
3194 return 1;
3195 else
3196 return 2;
3197 }
3198
3199 /* Size of ymode must not be greater than the size of xmode. */
3200 mode_multiple = GET_MODE_SIZE (xmode) / GET_MODE_SIZE (ymode);
3201 gcc_assert (mode_multiple != 0);
3202
3203 y_offset = offset / GET_MODE_SIZE (ymode);
3204 nregs_multiple = nregs_xmode / nregs_ymode;
3205 return (y_offset / (mode_multiple / nregs_multiple)) * nregs_ymode;
3206 }
3207
3208 /* This function returns true when the offset is representable via
3209 subreg_offset in the given regno.
3210 xregno - A regno of an inner hard subreg_reg (or what will become one).
3211 xmode - The mode of xregno.
3212 offset - The byte offset.
3213 ymode - The mode of a top level SUBREG (or what may become one).
3214 RETURN - Whether the offset is representable. */
3215 bool
subreg_offset_representable_p(unsigned int xregno,enum machine_mode xmode,unsigned int offset,enum machine_mode ymode)3216 subreg_offset_representable_p (unsigned int xregno, enum machine_mode xmode,
3217 unsigned int offset, enum machine_mode ymode)
3218 {
3219 int nregs_xmode, nregs_ymode, nregs_xmode_unit, nregs_xmode_unit_int;
3220 int mode_multiple, nregs_multiple;
3221 int y_offset;
3222 enum machine_mode xmode_unit, xmode_unit_int;
3223
3224 gcc_assert (xregno < FIRST_PSEUDO_REGISTER);
3225
3226 if (GET_MODE_INNER (xmode) == VOIDmode)
3227 xmode_unit = xmode;
3228 else
3229 xmode_unit = GET_MODE_INNER (xmode);
3230
3231 if (FLOAT_MODE_P (xmode_unit))
3232 {
3233 xmode_unit_int = int_mode_for_mode (xmode_unit);
3234 if (xmode_unit_int == BLKmode)
3235 /* It's probably bad to be here; a port should have an integer mode
3236 that's the same size as anything of which it takes a SUBREG. */
3237 xmode_unit_int = xmode_unit;
3238 }
3239 else
3240 xmode_unit_int = xmode_unit;
3241
3242 nregs_xmode_unit = hard_regno_nregs[xregno][xmode_unit];
3243 nregs_xmode_unit_int = hard_regno_nregs[xregno][xmode_unit_int];
3244
3245 /* If there are holes in a non-scalar mode in registers, we expect
3246 that it is made up of its units concatenated together. */
3247 if (nregs_xmode_unit != nregs_xmode_unit_int)
3248 {
3249 gcc_assert (nregs_xmode_unit * GET_MODE_NUNITS (xmode)
3250 == hard_regno_nregs[xregno][xmode]);
3251
3252 /* You can only ask for a SUBREG of a value with holes in the middle
3253 if you don't cross the holes. (Such a SUBREG should be done by
3254 picking a different register class, or doing it in memory if
3255 necessary.) An example of a value with holes is XCmode on 32-bit
3256 x86 with -m128bit-long-double; it's represented in 6 32-bit registers,
3257 3 for each part, but in memory it's two 128-bit parts.
3258 Padding is assumed to be at the end (not necessarily the 'high part')
3259 of each unit. */
3260 if (nregs_xmode_unit != nregs_xmode_unit_int
3261 && (offset / GET_MODE_SIZE (xmode_unit_int) + 1
3262 < GET_MODE_NUNITS (xmode))
3263 && (offset / GET_MODE_SIZE (xmode_unit_int)
3264 != ((offset + GET_MODE_SIZE (ymode) - 1)
3265 / GET_MODE_SIZE (xmode_unit_int))))
3266 return false;
3267
3268 nregs_xmode = nregs_xmode_unit_int * GET_MODE_NUNITS (xmode);
3269 }
3270 else
3271 nregs_xmode = hard_regno_nregs[xregno][xmode];
3272
3273 nregs_ymode = hard_regno_nregs[xregno][ymode];
3274
3275 /* Paradoxical subregs are otherwise valid. */
3276 if (offset == 0
3277 && nregs_ymode > nregs_xmode
3278 && (GET_MODE_SIZE (ymode) > UNITS_PER_WORD
3279 ? WORDS_BIG_ENDIAN : BYTES_BIG_ENDIAN))
3280 return true;
3281
3282 /* (TIGCC 20050324) Subregs of a 10-byte mode are special, hardcode them. */
3283 if (GET_MODE_SIZE (xmode) == 10)
3284 {
3285 switch (GET_MODE_SIZE (ymode))
3286 {
3287 case 1:
3288 return (offset == 3 || offset == 7 || offset == 9);
3289
3290 case 2:
3291 return (offset == 2 || offset == 6 || offset == 8);
3292
3293 case 4:
3294 return (offset == 0 || offset == 4);
3295
3296 case 8:
3297 return !offset;
3298
3299 default:
3300 return false;
3301 }
3302 }
3303
3304 /* Lowpart subregs are otherwise valid. */
3305 if (offset == subreg_lowpart_offset (ymode, xmode))
3306 return true;
3307
3308 /* This should always pass, otherwise we don't know how to verify
3309 the constraint. These conditions may be relaxed but
3310 subreg_regno_offset would need to be redesigned. */
3311 gcc_assert ((GET_MODE_SIZE (xmode) % GET_MODE_SIZE (ymode)) == 0);
3312 gcc_assert ((nregs_xmode % nregs_ymode) == 0);
3313
3314 /* The XMODE value can be seen as a vector of NREGS_XMODE
3315 values. The subreg must represent a lowpart of given field.
3316 Compute what field it is. */
3317 offset -= subreg_lowpart_offset (ymode,
3318 mode_for_size (GET_MODE_BITSIZE (xmode)
3319 / nregs_xmode,
3320 MODE_INT, 0));
3321
3322 /* Size of ymode must not be greater than the size of xmode. */
3323 mode_multiple = GET_MODE_SIZE (xmode) / GET_MODE_SIZE (ymode);
3324 gcc_assert (mode_multiple != 0);
3325
3326 y_offset = offset / GET_MODE_SIZE (ymode);
3327 nregs_multiple = nregs_xmode / nregs_ymode;
3328
3329 gcc_assert ((offset % GET_MODE_SIZE (ymode)) == 0);
3330 gcc_assert ((mode_multiple % nregs_multiple) == 0);
3331
3332 return (!(y_offset % (mode_multiple / nregs_multiple)));
3333 }
3334
3335 /* Return the final regno that a subreg expression refers to. */
3336 unsigned int
subreg_regno(rtx x)3337 subreg_regno (rtx x)
3338 {
3339 unsigned int ret;
3340 rtx subreg = SUBREG_REG (x);
3341 int regno = REGNO (subreg);
3342
3343 ret = regno + subreg_regno_offset (regno,
3344 GET_MODE (subreg),
3345 SUBREG_BYTE (x),
3346 GET_MODE (x));
3347 return ret;
3348
3349 }
3350 struct parms_set_data
3351 {
3352 int nregs;
3353 HARD_REG_SET regs;
3354 };
3355
3356 /* Helper function for noticing stores to parameter registers. */
3357 static void
parms_set(rtx x,rtx pat ATTRIBUTE_UNUSED,void * data)3358 parms_set (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
3359 {
3360 struct parms_set_data *d = data;
3361 if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER
3362 && TEST_HARD_REG_BIT (d->regs, REGNO (x)))
3363 {
3364 CLEAR_HARD_REG_BIT (d->regs, REGNO (x));
3365 d->nregs--;
3366 }
3367 }
3368
3369 /* Look backward for first parameter to be loaded.
3370 Note that loads of all parameters will not necessarily be
3371 found if CSE has eliminated some of them (e.g., an argument
3372 to the outer function is passed down as a parameter).
3373 Do not skip BOUNDARY. */
3374 rtx
find_first_parameter_load(rtx call_insn,rtx boundary)3375 find_first_parameter_load (rtx call_insn, rtx boundary)
3376 {
3377 struct parms_set_data parm;
3378 rtx p, before, first_set;
3379
3380 /* Since different machines initialize their parameter registers
3381 in different orders, assume nothing. Collect the set of all
3382 parameter registers. */
3383 CLEAR_HARD_REG_SET (parm.regs);
3384 parm.nregs = 0;
3385 for (p = CALL_INSN_FUNCTION_USAGE (call_insn); p; p = XEXP (p, 1))
3386 if (GET_CODE (XEXP (p, 0)) == USE
3387 && REG_P (XEXP (XEXP (p, 0), 0)))
3388 {
3389 gcc_assert (REGNO (XEXP (XEXP (p, 0), 0)) < FIRST_PSEUDO_REGISTER);
3390
3391 /* We only care about registers which can hold function
3392 arguments. */
3393 if (!FUNCTION_ARG_REGNO_P (REGNO (XEXP (XEXP (p, 0), 0))))
3394 continue;
3395
3396 SET_HARD_REG_BIT (parm.regs, REGNO (XEXP (XEXP (p, 0), 0)));
3397 parm.nregs++;
3398 }
3399 before = call_insn;
3400 first_set = call_insn;
3401
3402 /* Search backward for the first set of a register in this set. */
3403 while (parm.nregs && before != boundary)
3404 {
3405 before = PREV_INSN (before);
3406
3407 /* It is possible that some loads got CSEed from one call to
3408 another. Stop in that case. */
3409 if (CALL_P (before))
3410 break;
3411
3412 /* Our caller needs either ensure that we will find all sets
3413 (in case code has not been optimized yet), or take care
3414 for possible labels in a way by setting boundary to preceding
3415 CODE_LABEL. */
3416 if (LABEL_P (before))
3417 {
3418 gcc_assert (before == boundary);
3419 break;
3420 }
3421
3422 if (INSN_P (before))
3423 {
3424 int nregs_old = parm.nregs;
3425 note_stores (PATTERN (before), parms_set, &parm);
3426 /* If we found something that did not set a parameter reg,
3427 we're done. Do not keep going, as that might result
3428 in hoisting an insn before the setting of a pseudo
3429 that is used by the hoisted insn. */
3430 if (nregs_old != parm.nregs)
3431 first_set = before;
3432 else
3433 break;
3434 }
3435 }
3436 return first_set;
3437 }
3438
3439 /* Return true if we should avoid inserting code between INSN and preceding
3440 call instruction. */
3441
3442 bool
keep_with_call_p(rtx insn)3443 keep_with_call_p (rtx insn)
3444 {
3445 rtx set;
3446
3447 if (INSN_P (insn) && (set = single_set (insn)) != NULL)
3448 {
3449 if (REG_P (SET_DEST (set))
3450 && REGNO (SET_DEST (set)) < FIRST_PSEUDO_REGISTER
3451 && fixed_regs[REGNO (SET_DEST (set))]
3452 && general_operand (SET_SRC (set), VOIDmode))
3453 return true;
3454 if (REG_P (SET_SRC (set))
3455 && FUNCTION_VALUE_REGNO_P (REGNO (SET_SRC (set)))
3456 && REG_P (SET_DEST (set))
3457 && REGNO (SET_DEST (set)) >= FIRST_PSEUDO_REGISTER)
3458 return true;
3459 /* There may be a stack pop just after the call and before the store
3460 of the return register. Search for the actual store when deciding
3461 if we can break or not. */
3462 if (SET_DEST (set) == stack_pointer_rtx)
3463 {
3464 rtx i2 = next_nonnote_insn (insn);
3465 if (i2 && keep_with_call_p (i2))
3466 return true;
3467 }
3468 }
3469 return false;
3470 }
3471
3472 /* Return true if LABEL is a target of JUMP_INSN. This applies only
3473 to non-complex jumps. That is, direct unconditional, conditional,
3474 and tablejumps, but not computed jumps or returns. It also does
3475 not apply to the fallthru case of a conditional jump. */
3476
3477 bool
label_is_jump_target_p(rtx label,rtx jump_insn)3478 label_is_jump_target_p (rtx label, rtx jump_insn)
3479 {
3480 rtx tmp = JUMP_LABEL (jump_insn);
3481
3482 if (label == tmp)
3483 return true;
3484
3485 if (tablejump_p (jump_insn, NULL, &tmp))
3486 {
3487 rtvec vec = XVEC (PATTERN (tmp),
3488 GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC);
3489 int i, veclen = GET_NUM_ELEM (vec);
3490
3491 for (i = 0; i < veclen; ++i)
3492 if (XEXP (RTVEC_ELT (vec, i), 0) == label)
3493 return true;
3494 }
3495
3496 return false;
3497 }
3498
3499
3500 /* Return an estimate of the cost of computing rtx X.
3501 One use is in cse, to decide which expression to keep in the hash table.
3502 Another is in rtl generation, to pick the cheapest way to multiply.
3503 Other uses like the latter are expected in the future. */
3504
3505 int
rtx_cost(rtx x,enum rtx_code outer_code ATTRIBUTE_UNUSED)3506 rtx_cost (rtx x, enum rtx_code outer_code ATTRIBUTE_UNUSED)
3507 {
3508 int i, j;
3509 enum rtx_code code;
3510 const char *fmt;
3511 int total;
3512
3513 if (x == 0)
3514 return 0;
3515
3516 /* Compute the default costs of certain things.
3517 Note that targetm.rtx_costs can override the defaults. */
3518
3519 code = GET_CODE (x);
3520 switch (code)
3521 {
3522 case MULT:
3523 total = COSTS_N_INSNS (5);
3524 break;
3525 case DIV:
3526 case UDIV:
3527 case MOD:
3528 case UMOD:
3529 total = COSTS_N_INSNS (7);
3530 break;
3531 case USE:
3532 /* Used in loop.c and combine.c as a marker. */
3533 total = 0;
3534 break;
3535 default:
3536 total = COSTS_N_INSNS (1);
3537 }
3538
3539 switch (code)
3540 {
3541 case REG:
3542 return 0;
3543
3544 case SUBREG:
3545 total = 0;
3546 /* If we can't tie these modes, make this expensive. The larger
3547 the mode, the more expensive it is. */
3548 if (! MODES_TIEABLE_P (GET_MODE (x), GET_MODE (SUBREG_REG (x))))
3549 return COSTS_N_INSNS (2
3550 + GET_MODE_SIZE (GET_MODE (x)) / UNITS_PER_WORD);
3551 break;
3552
3553 default:
3554 if (targetm.rtx_costs (x, code, outer_code, &total))
3555 return total;
3556 break;
3557 }
3558
3559 /* Sum the costs of the sub-rtx's, plus cost of this operation,
3560 which is already in total. */
3561
3562 fmt = GET_RTX_FORMAT (code);
3563 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3564 if (fmt[i] == 'e')
3565 total += rtx_cost (XEXP (x, i), code);
3566 else if (fmt[i] == 'E')
3567 for (j = 0; j < XVECLEN (x, i); j++)
3568 total += rtx_cost (XVECEXP (x, i, j), code);
3569
3570 return total;
3571 }
3572
3573 /* Return cost of address expression X.
3574 Expect that X is properly formed address reference. */
3575
3576 int
address_cost(rtx x,enum machine_mode mode)3577 address_cost (rtx x, enum machine_mode mode)
3578 {
3579 /* We may be asked for cost of various unusual addresses, such as operands
3580 of push instruction. It is not worthwhile to complicate writing
3581 of the target hook by such cases. */
3582
3583 if (!memory_address_p (mode, x))
3584 return 1000;
3585
3586 return targetm.address_cost (x);
3587 }
3588
3589 /* If the target doesn't override, compute the cost as with arithmetic. */
3590
3591 int
default_address_cost(rtx x)3592 default_address_cost (rtx x)
3593 {
3594 return rtx_cost (x, MEM);
3595 }
3596
3597
3598 unsigned HOST_WIDE_INT
nonzero_bits(rtx x,enum machine_mode mode)3599 nonzero_bits (rtx x, enum machine_mode mode)
3600 {
3601 return cached_nonzero_bits (x, mode, NULL_RTX, VOIDmode, 0);
3602 }
3603
3604 unsigned int
num_sign_bit_copies(rtx x,enum machine_mode mode)3605 num_sign_bit_copies (rtx x, enum machine_mode mode)
3606 {
3607 return cached_num_sign_bit_copies (x, mode, NULL_RTX, VOIDmode, 0);
3608 }
3609
3610 /* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
3611 It avoids exponential behavior in nonzero_bits1 when X has
3612 identical subexpressions on the first or the second level. */
3613
3614 static unsigned HOST_WIDE_INT
cached_nonzero_bits(rtx x,enum machine_mode mode,rtx known_x,enum machine_mode known_mode,unsigned HOST_WIDE_INT known_ret)3615 cached_nonzero_bits (rtx x, enum machine_mode mode, rtx known_x,
3616 enum machine_mode known_mode,
3617 unsigned HOST_WIDE_INT known_ret)
3618 {
3619 if (x == known_x && mode == known_mode)
3620 return known_ret;
3621
3622 /* Try to find identical subexpressions. If found call
3623 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
3624 precomputed value for the subexpression as KNOWN_RET. */
3625
3626 if (ARITHMETIC_P (x))
3627 {
3628 rtx x0 = XEXP (x, 0);
3629 rtx x1 = XEXP (x, 1);
3630
3631 /* Check the first level. */
3632 if (x0 == x1)
3633 return nonzero_bits1 (x, mode, x0, mode,
3634 cached_nonzero_bits (x0, mode, known_x,
3635 known_mode, known_ret));
3636
3637 /* Check the second level. */
3638 if (ARITHMETIC_P (x0)
3639 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
3640 return nonzero_bits1 (x, mode, x1, mode,
3641 cached_nonzero_bits (x1, mode, known_x,
3642 known_mode, known_ret));
3643
3644 if (ARITHMETIC_P (x1)
3645 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
3646 return nonzero_bits1 (x, mode, x0, mode,
3647 cached_nonzero_bits (x0, mode, known_x,
3648 known_mode, known_ret));
3649 }
3650
3651 return nonzero_bits1 (x, mode, known_x, known_mode, known_ret);
3652 }
3653
3654 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
3655 We don't let nonzero_bits recur into num_sign_bit_copies, because that
3656 is less useful. We can't allow both, because that results in exponential
3657 run time recursion. There is a nullstone testcase that triggered
3658 this. This macro avoids accidental uses of num_sign_bit_copies. */
3659 #define cached_num_sign_bit_copies sorry_i_am_preventing_exponential_behavior
3660
3661 /* Given an expression, X, compute which bits in X can be nonzero.
3662 We don't care about bits outside of those defined in MODE.
3663
3664 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
3665 an arithmetic operation, we can do better. */
3666
3667 static unsigned HOST_WIDE_INT
nonzero_bits1(rtx x,enum machine_mode mode,rtx known_x,enum machine_mode known_mode,unsigned HOST_WIDE_INT known_ret)3668 nonzero_bits1 (rtx x, enum machine_mode mode, rtx known_x,
3669 enum machine_mode known_mode,
3670 unsigned HOST_WIDE_INT known_ret)
3671 {
3672 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
3673 unsigned HOST_WIDE_INT inner_nz;
3674 enum rtx_code code;
3675 unsigned int mode_width = GET_MODE_BITSIZE (mode);
3676
3677 /* For floating-point values, assume all bits are needed. */
3678 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
3679 return nonzero;
3680
3681 /* If X is wider than MODE, use its mode instead. */
3682 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
3683 {
3684 mode = GET_MODE (x);
3685 nonzero = GET_MODE_MASK (mode);
3686 mode_width = GET_MODE_BITSIZE (mode);
3687 }
3688
3689 if (mode_width > HOST_BITS_PER_WIDE_INT)
3690 /* Our only callers in this case look for single bit values. So
3691 just return the mode mask. Those tests will then be false. */
3692 return nonzero;
3693
3694 #ifndef WORD_REGISTER_OPERATIONS
3695 /* If MODE is wider than X, but both are a single word for both the host
3696 and target machines, we can compute this from which bits of the
3697 object might be nonzero in its own mode, taking into account the fact
3698 that on many CISC machines, accessing an object in a wider mode
3699 causes the high-order bits to become undefined. So they are
3700 not known to be zero. */
3701
3702 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
3703 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
3704 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
3705 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
3706 {
3707 nonzero &= cached_nonzero_bits (x, GET_MODE (x),
3708 known_x, known_mode, known_ret);
3709 nonzero |= GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x));
3710 return nonzero;
3711 }
3712 #endif
3713
3714 code = GET_CODE (x);
3715 switch (code)
3716 {
3717 case REG:
3718 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
3719 /* If pointers extend unsigned and this is a pointer in Pmode, say that
3720 all the bits above ptr_mode are known to be zero. */
3721 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
3722 && REG_POINTER (x))
3723 nonzero &= GET_MODE_MASK (ptr_mode);
3724 #endif
3725
3726 /* Include declared information about alignment of pointers. */
3727 /* ??? We don't properly preserve REG_POINTER changes across
3728 pointer-to-integer casts, so we can't trust it except for
3729 things that we know must be pointers. See execute/960116-1.c. */
3730 if ((x == stack_pointer_rtx
3731 || x == frame_pointer_rtx
3732 || x == arg_pointer_rtx)
3733 && REGNO_POINTER_ALIGN (REGNO (x)))
3734 {
3735 unsigned HOST_WIDE_INT alignment
3736 = REGNO_POINTER_ALIGN (REGNO (x)) / BITS_PER_UNIT;
3737
3738 #ifdef PUSH_ROUNDING
3739 /* If PUSH_ROUNDING is defined, it is possible for the
3740 stack to be momentarily aligned only to that amount,
3741 so we pick the least alignment. */
3742 if (x == stack_pointer_rtx && PUSH_ARGS)
3743 alignment = MIN ((unsigned HOST_WIDE_INT) PUSH_ROUNDING (1),
3744 alignment);
3745 #endif
3746
3747 nonzero &= ~(alignment - 1);
3748 }
3749
3750 {
3751 unsigned HOST_WIDE_INT nonzero_for_hook = nonzero;
3752 rtx new = rtl_hooks.reg_nonzero_bits (x, mode, known_x,
3753 known_mode, known_ret,
3754 &nonzero_for_hook);
3755
3756 if (new)
3757 nonzero_for_hook &= cached_nonzero_bits (new, mode, known_x,
3758 known_mode, known_ret);
3759
3760 return nonzero_for_hook;
3761 }
3762
3763 case CONST_INT:
3764 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
3765 /* If X is negative in MODE, sign-extend the value. */
3766 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
3767 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
3768 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
3769 #endif
3770
3771 return INTVAL (x);
3772
3773 case MEM:
3774 #ifdef LOAD_EXTEND_OP
3775 /* In many, if not most, RISC machines, reading a byte from memory
3776 zeros the rest of the register. Noticing that fact saves a lot
3777 of extra zero-extends. */
3778 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
3779 nonzero &= GET_MODE_MASK (GET_MODE (x));
3780 #endif
3781 break;
3782
3783 case EQ: case NE:
3784 case UNEQ: case LTGT:
3785 case GT: case GTU: case UNGT:
3786 case LT: case LTU: case UNLT:
3787 case GE: case GEU: case UNGE:
3788 case LE: case LEU: case UNLE:
3789 case UNORDERED: case ORDERED:
3790 /* If this produces an integer result, we know which bits are set.
3791 Code here used to clear bits outside the mode of X, but that is
3792 now done above. */
3793 /* Mind that MODE is the mode the caller wants to look at this
3794 operation in, and not the actual operation mode. We can wind
3795 up with (subreg:DI (gt:V4HI x y)), and we don't have anything
3796 that describes the results of a vector compare. */
3797 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT
3798 && mode_width <= HOST_BITS_PER_WIDE_INT)
3799 nonzero = STORE_FLAG_VALUE;
3800 break;
3801
3802 case NEG:
3803 #if 0
3804 /* Disabled to avoid exponential mutual recursion between nonzero_bits
3805 and num_sign_bit_copies. */
3806 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
3807 == GET_MODE_BITSIZE (GET_MODE (x)))
3808 nonzero = 1;
3809 #endif
3810
3811 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
3812 nonzero |= (GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x)));
3813 break;
3814
3815 case ABS:
3816 #if 0
3817 /* Disabled to avoid exponential mutual recursion between nonzero_bits
3818 and num_sign_bit_copies. */
3819 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
3820 == GET_MODE_BITSIZE (GET_MODE (x)))
3821 nonzero = 1;
3822 #endif
3823 break;
3824
3825 case TRUNCATE:
3826 nonzero &= (cached_nonzero_bits (XEXP (x, 0), mode,
3827 known_x, known_mode, known_ret)
3828 & GET_MODE_MASK (mode));
3829 break;
3830
3831 case ZERO_EXTEND:
3832 nonzero &= cached_nonzero_bits (XEXP (x, 0), mode,
3833 known_x, known_mode, known_ret);
3834 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
3835 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
3836 break;
3837
3838 case SIGN_EXTEND:
3839 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
3840 Otherwise, show all the bits in the outer mode but not the inner
3841 may be nonzero. */
3842 inner_nz = cached_nonzero_bits (XEXP (x, 0), mode,
3843 known_x, known_mode, known_ret);
3844 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
3845 {
3846 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
3847 if (inner_nz
3848 & (((HOST_WIDE_INT) 1
3849 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
3850 inner_nz |= (GET_MODE_MASK (mode)
3851 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
3852 }
3853
3854 nonzero &= inner_nz;
3855 break;
3856
3857 case AND:
3858 nonzero &= cached_nonzero_bits (XEXP (x, 0), mode,
3859 known_x, known_mode, known_ret)
3860 & cached_nonzero_bits (XEXP (x, 1), mode,
3861 known_x, known_mode, known_ret);
3862 break;
3863
3864 case XOR: case IOR:
3865 case UMIN: case UMAX: case SMIN: case SMAX:
3866 {
3867 unsigned HOST_WIDE_INT nonzero0 =
3868 cached_nonzero_bits (XEXP (x, 0), mode,
3869 known_x, known_mode, known_ret);
3870
3871 /* Don't call nonzero_bits for the second time if it cannot change
3872 anything. */
3873 if ((nonzero & nonzero0) != nonzero)
3874 nonzero &= nonzero0
3875 | cached_nonzero_bits (XEXP (x, 1), mode,
3876 known_x, known_mode, known_ret);
3877 }
3878 break;
3879
3880 case PLUS: case MINUS:
3881 case MULT:
3882 case DIV: case UDIV:
3883 case MOD: case UMOD:
3884 /* We can apply the rules of arithmetic to compute the number of
3885 high- and low-order zero bits of these operations. We start by
3886 computing the width (position of the highest-order nonzero bit)
3887 and the number of low-order zero bits for each value. */
3888 {
3889 unsigned HOST_WIDE_INT nz0 =
3890 cached_nonzero_bits (XEXP (x, 0), mode,
3891 known_x, known_mode, known_ret);
3892 unsigned HOST_WIDE_INT nz1 =
3893 cached_nonzero_bits (XEXP (x, 1), mode,
3894 known_x, known_mode, known_ret);
3895 int sign_index = GET_MODE_BITSIZE (GET_MODE (x)) - 1;
3896 int width0 = floor_log2 (nz0) + 1;
3897 int width1 = floor_log2 (nz1) + 1;
3898 int low0 = floor_log2 (nz0 & -nz0);
3899 int low1 = floor_log2 (nz1 & -nz1);
3900 HOST_WIDE_INT op0_maybe_minusp
3901 = (nz0 & ((HOST_WIDE_INT) 1 << sign_index));
3902 HOST_WIDE_INT op1_maybe_minusp
3903 = (nz1 & ((HOST_WIDE_INT) 1 << sign_index));
3904 unsigned int result_width = mode_width;
3905 int result_low = 0;
3906
3907 switch (code)
3908 {
3909 case PLUS:
3910 result_width = MAX (width0, width1) + 1;
3911 result_low = MIN (low0, low1);
3912 break;
3913 case MINUS:
3914 result_low = MIN (low0, low1);
3915 break;
3916 case MULT:
3917 result_width = width0 + width1;
3918 result_low = low0 + low1;
3919 break;
3920 case DIV:
3921 if (width1 == 0)
3922 break;
3923 if (! op0_maybe_minusp && ! op1_maybe_minusp)
3924 result_width = width0;
3925 break;
3926 case UDIV:
3927 if (width1 == 0)
3928 break;
3929 result_width = width0;
3930 break;
3931 case MOD:
3932 if (width1 == 0)
3933 break;
3934 if (! op0_maybe_minusp && ! op1_maybe_minusp)
3935 result_width = MIN (width0, width1);
3936 result_low = MIN (low0, low1);
3937 break;
3938 case UMOD:
3939 if (width1 == 0)
3940 break;
3941 result_width = MIN (width0, width1);
3942 result_low = MIN (low0, low1);
3943 break;
3944 default:
3945 gcc_unreachable ();
3946 }
3947
3948 if (result_width < mode_width)
3949 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
3950
3951 if (result_low > 0)
3952 nonzero &= ~(((HOST_WIDE_INT) 1 << result_low) - 1);
3953
3954 #ifdef POINTERS_EXTEND_UNSIGNED
3955 /* If pointers extend unsigned and this is an addition or subtraction
3956 to a pointer in Pmode, all the bits above ptr_mode are known to be
3957 zero. */
3958 if (POINTERS_EXTEND_UNSIGNED > 0 && GET_MODE (x) == Pmode
3959 && (code == PLUS || code == MINUS)
3960 && REG_P (XEXP (x, 0)) && REG_POINTER (XEXP (x, 0)))
3961 nonzero &= GET_MODE_MASK (ptr_mode);
3962 #endif
3963 }
3964 break;
3965
3966 case ZERO_EXTRACT:
3967 if (GET_CODE (XEXP (x, 1)) == CONST_INT
3968 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
3969 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
3970 break;
3971
3972 case SUBREG:
3973 /* If this is a SUBREG formed for a promoted variable that has
3974 been zero-extended, we know that at least the high-order bits
3975 are zero, though others might be too. */
3976
3977 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x) > 0)
3978 nonzero = GET_MODE_MASK (GET_MODE (x))
3979 & cached_nonzero_bits (SUBREG_REG (x), GET_MODE (x),
3980 known_x, known_mode, known_ret);
3981
3982 /* If the inner mode is a single word for both the host and target
3983 machines, we can compute this from which bits of the inner
3984 object might be nonzero. */
3985 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
3986 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
3987 <= HOST_BITS_PER_WIDE_INT))
3988 {
3989 nonzero &= cached_nonzero_bits (SUBREG_REG (x), mode,
3990 known_x, known_mode, known_ret);
3991
3992 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
3993 /* If this is a typical RISC machine, we only have to worry
3994 about the way loads are extended. */
3995 if ((LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
3996 ? (((nonzero
3997 & (((unsigned HOST_WIDE_INT) 1
3998 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1))))
3999 != 0))
4000 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
4001 || !MEM_P (SUBREG_REG (x)))
4002 #endif
4003 {
4004 /* On many CISC machines, accessing an object in a wider mode
4005 causes the high-order bits to become undefined. So they are
4006 not known to be zero. */
4007 if (GET_MODE_SIZE (GET_MODE (x))
4008 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
4009 nonzero |= (GET_MODE_MASK (GET_MODE (x))
4010 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
4011 }
4012 }
4013 break;
4014
4015 case ASHIFTRT:
4016 case LSHIFTRT:
4017 case ASHIFT:
4018 case ROTATE:
4019 /* The nonzero bits are in two classes: any bits within MODE
4020 that aren't in GET_MODE (x) are always significant. The rest of the
4021 nonzero bits are those that are significant in the operand of
4022 the shift when shifted the appropriate number of bits. This
4023 shows that high-order bits are cleared by the right shift and
4024 low-order bits by left shifts. */
4025 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4026 && INTVAL (XEXP (x, 1)) >= 0
4027 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
4028 {
4029 enum machine_mode inner_mode = GET_MODE (x);
4030 unsigned int width = GET_MODE_BITSIZE (inner_mode);
4031 int count = INTVAL (XEXP (x, 1));
4032 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
4033 unsigned HOST_WIDE_INT op_nonzero =
4034 cached_nonzero_bits (XEXP (x, 0), mode,
4035 known_x, known_mode, known_ret);
4036 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
4037 unsigned HOST_WIDE_INT outer = 0;
4038
4039 if (mode_width > width)
4040 outer = (op_nonzero & nonzero & ~mode_mask);
4041
4042 if (code == LSHIFTRT)
4043 inner >>= count;
4044 else if (code == ASHIFTRT)
4045 {
4046 inner >>= count;
4047
4048 /* If the sign bit may have been nonzero before the shift, we
4049 need to mark all the places it could have been copied to
4050 by the shift as possibly nonzero. */
4051 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
4052 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
4053 }
4054 else if (code == ASHIFT)
4055 inner <<= count;
4056 else
4057 inner = ((inner << (count % width)
4058 | (inner >> (width - (count % width)))) & mode_mask);
4059
4060 nonzero &= (outer | inner);
4061 }
4062 break;
4063
4064 case FFS:
4065 case POPCOUNT:
4066 /* This is at most the number of bits in the mode. */
4067 nonzero = ((HOST_WIDE_INT) 2 << (floor_log2 (mode_width))) - 1;
4068 break;
4069
4070 case CLZ:
4071 /* If CLZ has a known value at zero, then the nonzero bits are
4072 that value, plus the number of bits in the mode minus one. */
4073 if (CLZ_DEFINED_VALUE_AT_ZERO (mode, nonzero))
4074 nonzero |= ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width))) - 1;
4075 else
4076 nonzero = -1;
4077 break;
4078
4079 case CTZ:
4080 /* If CTZ has a known value at zero, then the nonzero bits are
4081 that value, plus the number of bits in the mode minus one. */
4082 if (CTZ_DEFINED_VALUE_AT_ZERO (mode, nonzero))
4083 nonzero |= ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width))) - 1;
4084 else
4085 nonzero = -1;
4086 break;
4087
4088 case PARITY:
4089 nonzero = 1;
4090 break;
4091
4092 case IF_THEN_ELSE:
4093 {
4094 unsigned HOST_WIDE_INT nonzero_true =
4095 cached_nonzero_bits (XEXP (x, 1), mode,
4096 known_x, known_mode, known_ret);
4097
4098 /* Don't call nonzero_bits for the second time if it cannot change
4099 anything. */
4100 if ((nonzero & nonzero_true) != nonzero)
4101 nonzero &= nonzero_true
4102 | cached_nonzero_bits (XEXP (x, 2), mode,
4103 known_x, known_mode, known_ret);
4104 }
4105 break;
4106
4107 default:
4108 break;
4109 }
4110
4111 return nonzero;
4112 }
4113
4114 /* See the macro definition above. */
4115 #undef cached_num_sign_bit_copies
4116
4117
4118 /* The function cached_num_sign_bit_copies is a wrapper around
4119 num_sign_bit_copies1. It avoids exponential behavior in
4120 num_sign_bit_copies1 when X has identical subexpressions on the
4121 first or the second level. */
4122
4123 static unsigned int
cached_num_sign_bit_copies(rtx x,enum machine_mode mode,rtx known_x,enum machine_mode known_mode,unsigned int known_ret)4124 cached_num_sign_bit_copies (rtx x, enum machine_mode mode, rtx known_x,
4125 enum machine_mode known_mode,
4126 unsigned int known_ret)
4127 {
4128 if (x == known_x && mode == known_mode)
4129 return known_ret;
4130
4131 /* Try to find identical subexpressions. If found call
4132 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
4133 the precomputed value for the subexpression as KNOWN_RET. */
4134
4135 if (ARITHMETIC_P (x))
4136 {
4137 rtx x0 = XEXP (x, 0);
4138 rtx x1 = XEXP (x, 1);
4139
4140 /* Check the first level. */
4141 if (x0 == x1)
4142 return
4143 num_sign_bit_copies1 (x, mode, x0, mode,
4144 cached_num_sign_bit_copies (x0, mode, known_x,
4145 known_mode,
4146 known_ret));
4147
4148 /* Check the second level. */
4149 if (ARITHMETIC_P (x0)
4150 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
4151 return
4152 num_sign_bit_copies1 (x, mode, x1, mode,
4153 cached_num_sign_bit_copies (x1, mode, known_x,
4154 known_mode,
4155 known_ret));
4156
4157 if (ARITHMETIC_P (x1)
4158 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
4159 return
4160 num_sign_bit_copies1 (x, mode, x0, mode,
4161 cached_num_sign_bit_copies (x0, mode, known_x,
4162 known_mode,
4163 known_ret));
4164 }
4165
4166 return num_sign_bit_copies1 (x, mode, known_x, known_mode, known_ret);
4167 }
4168
4169 /* Return the number of bits at the high-order end of X that are known to
4170 be equal to the sign bit. X will be used in mode MODE; if MODE is
4171 VOIDmode, X will be used in its own mode. The returned value will always
4172 be between 1 and the number of bits in MODE. */
4173
4174 static unsigned int
num_sign_bit_copies1(rtx x,enum machine_mode mode,rtx known_x,enum machine_mode known_mode,unsigned int known_ret)4175 num_sign_bit_copies1 (rtx x, enum machine_mode mode, rtx known_x,
4176 enum machine_mode known_mode,
4177 unsigned int known_ret)
4178 {
4179 enum rtx_code code = GET_CODE (x);
4180 unsigned int bitwidth = GET_MODE_BITSIZE (mode);
4181 int num0, num1, result;
4182 unsigned HOST_WIDE_INT nonzero;
4183
4184 /* If we weren't given a mode, use the mode of X. If the mode is still
4185 VOIDmode, we don't know anything. Likewise if one of the modes is
4186 floating-point. */
4187
4188 if (mode == VOIDmode)
4189 mode = GET_MODE (x);
4190
4191 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
4192 return 1;
4193
4194 /* For a smaller object, just ignore the high bits. */
4195 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
4196 {
4197 num0 = cached_num_sign_bit_copies (x, GET_MODE (x),
4198 known_x, known_mode, known_ret);
4199 return MAX (1,
4200 num0 - (int) (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth));
4201 }
4202
4203 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
4204 {
4205 #ifndef WORD_REGISTER_OPERATIONS
4206 /* If this machine does not do all register operations on the entire
4207 register and MODE is wider than the mode of X, we can say nothing
4208 at all about the high-order bits. */
4209 return 1;
4210 #else
4211 /* Likewise on machines that do, if the mode of the object is smaller
4212 than a word and loads of that size don't sign extend, we can say
4213 nothing about the high order bits. */
4214 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
4215 #ifdef LOAD_EXTEND_OP
4216 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
4217 #endif
4218 )
4219 return 1;
4220 #endif
4221 }
4222
4223 switch (code)
4224 {
4225 case REG:
4226
4227 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
4228 /* If pointers extend signed and this is a pointer in Pmode, say that
4229 all the bits above ptr_mode are known to be sign bit copies. */
4230 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
4231 && REG_POINTER (x))
4232 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
4233 #endif
4234
4235 {
4236 unsigned int copies_for_hook = 1, copies = 1;
4237 rtx new = rtl_hooks.reg_num_sign_bit_copies (x, mode, known_x,
4238 known_mode, known_ret,
4239 &copies_for_hook);
4240
4241 if (new)
4242 copies = cached_num_sign_bit_copies (new, mode, known_x,
4243 known_mode, known_ret);
4244
4245 if (copies > 1 || copies_for_hook > 1)
4246 return MAX (copies, copies_for_hook);
4247
4248 /* Else, use nonzero_bits to guess num_sign_bit_copies (see below). */
4249 }
4250 break;
4251
4252 case MEM:
4253 #ifdef LOAD_EXTEND_OP
4254 /* Some RISC machines sign-extend all loads of smaller than a word. */
4255 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
4256 return MAX (1, ((int) bitwidth
4257 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1));
4258 #endif
4259 break;
4260
4261 case CONST_INT:
4262 /* If the constant is negative, take its 1's complement and remask.
4263 Then see how many zero bits we have. */
4264 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
4265 if (bitwidth <= HOST_BITS_PER_WIDE_INT
4266 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
4267 nonzero = (~nonzero) & GET_MODE_MASK (mode);
4268
4269 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
4270
4271 case SUBREG:
4272 /* If this is a SUBREG for a promoted object that is sign-extended
4273 and we are looking at it in a wider mode, we know that at least the
4274 high-order bits are known to be sign bit copies. */
4275
4276 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
4277 {
4278 num0 = cached_num_sign_bit_copies (SUBREG_REG (x), mode,
4279 known_x, known_mode, known_ret);
4280 return MAX ((int) bitwidth
4281 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1,
4282 num0);
4283 }
4284
4285 /* For a smaller object, just ignore the high bits. */
4286 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
4287 {
4288 num0 = cached_num_sign_bit_copies (SUBREG_REG (x), VOIDmode,
4289 known_x, known_mode, known_ret);
4290 return MAX (1, (num0
4291 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
4292 - bitwidth)));
4293 }
4294
4295 #ifdef WORD_REGISTER_OPERATIONS
4296 #ifdef LOAD_EXTEND_OP
4297 /* For paradoxical SUBREGs on machines where all register operations
4298 affect the entire register, just look inside. Note that we are
4299 passing MODE to the recursive call, so the number of sign bit copies
4300 will remain relative to that mode, not the inner mode. */
4301
4302 /* This works only if loads sign extend. Otherwise, if we get a
4303 reload for the inner part, it may be loaded from the stack, and
4304 then we lose all sign bit copies that existed before the store
4305 to the stack. */
4306
4307 if ((GET_MODE_SIZE (GET_MODE (x))
4308 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
4309 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
4310 && MEM_P (SUBREG_REG (x)))
4311 return cached_num_sign_bit_copies (SUBREG_REG (x), mode,
4312 known_x, known_mode, known_ret);
4313 #endif
4314 #endif
4315 break;
4316
4317 case SIGN_EXTRACT:
4318 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4319 return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1)));
4320 break;
4321
4322 case SIGN_EXTEND:
4323 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4324 + cached_num_sign_bit_copies (XEXP (x, 0), VOIDmode,
4325 known_x, known_mode, known_ret));
4326
4327 case TRUNCATE:
4328 /* For a smaller object, just ignore the high bits. */
4329 num0 = cached_num_sign_bit_copies (XEXP (x, 0), VOIDmode,
4330 known_x, known_mode, known_ret);
4331 return MAX (1, (num0 - (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4332 - bitwidth)));
4333
4334 case NOT:
4335 return cached_num_sign_bit_copies (XEXP (x, 0), mode,
4336 known_x, known_mode, known_ret);
4337
4338 case ROTATE: case ROTATERT:
4339 /* If we are rotating left by a number of bits less than the number
4340 of sign bit copies, we can just subtract that amount from the
4341 number. */
4342 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4343 && INTVAL (XEXP (x, 1)) >= 0
4344 && INTVAL (XEXP (x, 1)) < (int) bitwidth)
4345 {
4346 num0 = cached_num_sign_bit_copies (XEXP (x, 0), mode,
4347 known_x, known_mode, known_ret);
4348 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
4349 : (int) bitwidth - INTVAL (XEXP (x, 1))));
4350 }
4351 break;
4352
4353 case NEG:
4354 /* In general, this subtracts one sign bit copy. But if the value
4355 is known to be positive, the number of sign bit copies is the
4356 same as that of the input. Finally, if the input has just one bit
4357 that might be nonzero, all the bits are copies of the sign bit. */
4358 num0 = cached_num_sign_bit_copies (XEXP (x, 0), mode,
4359 known_x, known_mode, known_ret);
4360 if (bitwidth > HOST_BITS_PER_WIDE_INT)
4361 return num0 > 1 ? num0 - 1 : 1;
4362
4363 nonzero = nonzero_bits (XEXP (x, 0), mode);
4364 if (nonzero == 1)
4365 return bitwidth;
4366
4367 if (num0 > 1
4368 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
4369 num0--;
4370
4371 return num0;
4372
4373 case IOR: case AND: case XOR:
4374 case SMIN: case SMAX: case UMIN: case UMAX:
4375 /* Logical operations will preserve the number of sign-bit copies.
4376 MIN and MAX operations always return one of the operands. */
4377 num0 = cached_num_sign_bit_copies (XEXP (x, 0), mode,
4378 known_x, known_mode, known_ret);
4379 num1 = cached_num_sign_bit_copies (XEXP (x, 1), mode,
4380 known_x, known_mode, known_ret);
4381 return MIN (num0, num1);
4382
4383 case PLUS: case MINUS:
4384 /* For addition and subtraction, we can have a 1-bit carry. However,
4385 if we are subtracting 1 from a positive number, there will not
4386 be such a carry. Furthermore, if the positive number is known to
4387 be 0 or 1, we know the result is either -1 or 0. */
4388
4389 if (code == PLUS && XEXP (x, 1) == constm1_rtx
4390 && bitwidth <= HOST_BITS_PER_WIDE_INT)
4391 {
4392 nonzero = nonzero_bits (XEXP (x, 0), mode);
4393 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
4394 return (nonzero == 1 || nonzero == 0 ? bitwidth
4395 : bitwidth - floor_log2 (nonzero) - 1);
4396 }
4397
4398 num0 = cached_num_sign_bit_copies (XEXP (x, 0), mode,
4399 known_x, known_mode, known_ret);
4400 num1 = cached_num_sign_bit_copies (XEXP (x, 1), mode,
4401 known_x, known_mode, known_ret);
4402 result = MAX (1, MIN (num0, num1) - 1);
4403
4404 #ifdef POINTERS_EXTEND_UNSIGNED
4405 /* If pointers extend signed and this is an addition or subtraction
4406 to a pointer in Pmode, all the bits above ptr_mode are known to be
4407 sign bit copies. */
4408 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
4409 && (code == PLUS || code == MINUS)
4410 && REG_P (XEXP (x, 0)) && REG_POINTER (XEXP (x, 0)))
4411 result = MAX ((int) (GET_MODE_BITSIZE (Pmode)
4412 - GET_MODE_BITSIZE (ptr_mode) + 1),
4413 result);
4414 #endif
4415 return result;
4416
4417 case MULT:
4418 /* The number of bits of the product is the sum of the number of
4419 bits of both terms. However, unless one of the terms if known
4420 to be positive, we must allow for an additional bit since negating
4421 a negative number can remove one sign bit copy. */
4422
4423 num0 = cached_num_sign_bit_copies (XEXP (x, 0), mode,
4424 known_x, known_mode, known_ret);
4425 num1 = cached_num_sign_bit_copies (XEXP (x, 1), mode,
4426 known_x, known_mode, known_ret);
4427
4428 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
4429 if (result > 0
4430 && (bitwidth > HOST_BITS_PER_WIDE_INT
4431 || (((nonzero_bits (XEXP (x, 0), mode)
4432 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
4433 && ((nonzero_bits (XEXP (x, 1), mode)
4434 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
4435 result--;
4436
4437 return MAX (1, result);
4438
4439 case UDIV:
4440 /* The result must be <= the first operand. If the first operand
4441 has the high bit set, we know nothing about the number of sign
4442 bit copies. */
4443 if (bitwidth > HOST_BITS_PER_WIDE_INT)
4444 return 1;
4445 else if ((nonzero_bits (XEXP (x, 0), mode)
4446 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
4447 return 1;
4448 else
4449 return cached_num_sign_bit_copies (XEXP (x, 0), mode,
4450 known_x, known_mode, known_ret);
4451
4452 case UMOD:
4453 /* The result must be <= the second operand. */
4454 return cached_num_sign_bit_copies (XEXP (x, 1), mode,
4455 known_x, known_mode, known_ret);
4456
4457 case DIV:
4458 /* Similar to unsigned division, except that we have to worry about
4459 the case where the divisor is negative, in which case we have
4460 to add 1. */
4461 result = cached_num_sign_bit_copies (XEXP (x, 0), mode,
4462 known_x, known_mode, known_ret);
4463 if (result > 1
4464 && (bitwidth > HOST_BITS_PER_WIDE_INT
4465 || (nonzero_bits (XEXP (x, 1), mode)
4466 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
4467 result--;
4468
4469 return result;
4470
4471 case MOD:
4472 result = cached_num_sign_bit_copies (XEXP (x, 1), mode,
4473 known_x, known_mode, known_ret);
4474 if (result > 1
4475 && (bitwidth > HOST_BITS_PER_WIDE_INT
4476 || (nonzero_bits (XEXP (x, 1), mode)
4477 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
4478 result--;
4479
4480 return result;
4481
4482 case ASHIFTRT:
4483 /* Shifts by a constant add to the number of bits equal to the
4484 sign bit. */
4485 num0 = cached_num_sign_bit_copies (XEXP (x, 0), mode,
4486 known_x, known_mode, known_ret);
4487 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4488 && INTVAL (XEXP (x, 1)) > 0)
4489 num0 = MIN ((int) bitwidth, num0 + INTVAL (XEXP (x, 1)));
4490
4491 return num0;
4492
4493 case ASHIFT:
4494 /* Left shifts destroy copies. */
4495 if (GET_CODE (XEXP (x, 1)) != CONST_INT
4496 || INTVAL (XEXP (x, 1)) < 0
4497 || INTVAL (XEXP (x, 1)) >= (int) bitwidth)
4498 return 1;
4499
4500 num0 = cached_num_sign_bit_copies (XEXP (x, 0), mode,
4501 known_x, known_mode, known_ret);
4502 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
4503
4504 case IF_THEN_ELSE:
4505 num0 = cached_num_sign_bit_copies (XEXP (x, 1), mode,
4506 known_x, known_mode, known_ret);
4507 num1 = cached_num_sign_bit_copies (XEXP (x, 2), mode,
4508 known_x, known_mode, known_ret);
4509 return MIN (num0, num1);
4510
4511 case EQ: case NE: case GE: case GT: case LE: case LT:
4512 case UNEQ: case LTGT: case UNGE: case UNGT: case UNLE: case UNLT:
4513 case GEU: case GTU: case LEU: case LTU:
4514 case UNORDERED: case ORDERED:
4515 /* If the constant is negative, take its 1's complement and remask.
4516 Then see how many zero bits we have. */
4517 nonzero = STORE_FLAG_VALUE;
4518 if (bitwidth <= HOST_BITS_PER_WIDE_INT
4519 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
4520 nonzero = (~nonzero) & GET_MODE_MASK (mode);
4521
4522 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
4523
4524 default:
4525 break;
4526 }
4527
4528 /* If we haven't been able to figure it out by one of the above rules,
4529 see if some of the high-order bits are known to be zero. If so,
4530 count those bits and return one less than that amount. If we can't
4531 safely compute the mask for this mode, always return BITWIDTH. */
4532
4533 bitwidth = GET_MODE_BITSIZE (mode);
4534 if (bitwidth > HOST_BITS_PER_WIDE_INT)
4535 return 1;
4536
4537 nonzero = nonzero_bits (x, mode);
4538 return nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
4539 ? 1 : bitwidth - floor_log2 (nonzero) - 1;
4540 }
4541
4542 /* Calculate the rtx_cost of a single instruction. A return value of
4543 zero indicates an instruction pattern without a known cost. */
4544
4545 int
insn_rtx_cost(rtx pat)4546 insn_rtx_cost (rtx pat)
4547 {
4548 int i, cost;
4549 rtx set;
4550
4551 /* Extract the single set rtx from the instruction pattern.
4552 We can't use single_set since we only have the pattern. */
4553 if (GET_CODE (pat) == SET)
4554 set = pat;
4555 else if (GET_CODE (pat) == PARALLEL)
4556 {
4557 set = NULL_RTX;
4558 for (i = 0; i < XVECLEN (pat, 0); i++)
4559 {
4560 rtx x = XVECEXP (pat, 0, i);
4561 if (GET_CODE (x) == SET)
4562 {
4563 if (set)
4564 return 0;
4565 set = x;
4566 }
4567 }
4568 if (!set)
4569 return 0;
4570 }
4571 else
4572 return 0;
4573
4574 cost = rtx_cost (SET_SRC (set), SET);
4575 return cost > 0 ? cost : COSTS_N_INSNS (1);
4576 }
4577
4578 /* Given an insn INSN and condition COND, return the condition in a
4579 canonical form to simplify testing by callers. Specifically:
4580
4581 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
4582 (2) Both operands will be machine operands; (cc0) will have been replaced.
4583 (3) If an operand is a constant, it will be the second operand.
4584 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
4585 for GE, GEU, and LEU.
4586
4587 If the condition cannot be understood, or is an inequality floating-point
4588 comparison which needs to be reversed, 0 will be returned.
4589
4590 If REVERSE is nonzero, then reverse the condition prior to canonizing it.
4591
4592 If EARLIEST is nonzero, it is a pointer to a place where the earliest
4593 insn used in locating the condition was found. If a replacement test
4594 of the condition is desired, it should be placed in front of that
4595 insn and we will be sure that the inputs are still valid.
4596
4597 If WANT_REG is nonzero, we wish the condition to be relative to that
4598 register, if possible. Therefore, do not canonicalize the condition
4599 further. If ALLOW_CC_MODE is nonzero, allow the condition returned
4600 to be a compare to a CC mode register.
4601
4602 If VALID_AT_INSN_P, the condition must be valid at both *EARLIEST
4603 and at INSN. */
4604
4605 rtx
canonicalize_condition(rtx insn,rtx cond,int reverse,rtx * earliest,rtx want_reg,int allow_cc_mode,int valid_at_insn_p)4606 canonicalize_condition (rtx insn, rtx cond, int reverse, rtx *earliest,
4607 rtx want_reg, int allow_cc_mode, int valid_at_insn_p)
4608 {
4609 enum rtx_code code;
4610 rtx prev = insn;
4611 rtx set;
4612 rtx tem;
4613 rtx op0, op1;
4614 int reverse_code = 0;
4615 enum machine_mode mode;
4616
4617 code = GET_CODE (cond);
4618 mode = GET_MODE (cond);
4619 op0 = XEXP (cond, 0);
4620 op1 = XEXP (cond, 1);
4621
4622 if (reverse)
4623 code = reversed_comparison_code (cond, insn);
4624 if (code == UNKNOWN)
4625 return 0;
4626
4627 if (earliest)
4628 *earliest = insn;
4629
4630 /* If we are comparing a register with zero, see if the register is set
4631 in the previous insn to a COMPARE or a comparison operation. Perform
4632 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
4633 in cse.c */
4634
4635 while ((GET_RTX_CLASS (code) == RTX_COMPARE
4636 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
4637 && op1 == CONST0_RTX (GET_MODE (op0))
4638 && op0 != want_reg)
4639 {
4640 /* Set nonzero when we find something of interest. */
4641 rtx x = 0;
4642
4643 #ifdef HAVE_cc0
4644 /* If comparison with cc0, import actual comparison from compare
4645 insn. */
4646 if (op0 == cc0_rtx)
4647 {
4648 if ((prev = prev_nonnote_insn (prev)) == 0
4649 || !NONJUMP_INSN_P (prev)
4650 || (set = single_set (prev)) == 0
4651 || SET_DEST (set) != cc0_rtx)
4652 return 0;
4653
4654 op0 = SET_SRC (set);
4655 op1 = CONST0_RTX (GET_MODE (op0));
4656 if (earliest)
4657 *earliest = prev;
4658 }
4659 #endif
4660
4661 /* If this is a COMPARE, pick up the two things being compared. */
4662 if (GET_CODE (op0) == COMPARE)
4663 {
4664 op1 = XEXP (op0, 1);
4665 op0 = XEXP (op0, 0);
4666 continue;
4667 }
4668 else if (!REG_P (op0))
4669 break;
4670
4671 /* Go back to the previous insn. Stop if it is not an INSN. We also
4672 stop if it isn't a single set or if it has a REG_INC note because
4673 we don't want to bother dealing with it. */
4674
4675 if ((prev = prev_nonnote_insn (prev)) == 0
4676 || !NONJUMP_INSN_P (prev)
4677 || FIND_REG_INC_NOTE (prev, NULL_RTX))
4678 break;
4679
4680 set = set_of (op0, prev);
4681
4682 if (set
4683 && (GET_CODE (set) != SET
4684 || !rtx_equal_p (SET_DEST (set), op0)))
4685 break;
4686
4687 /* If this is setting OP0, get what it sets it to if it looks
4688 relevant. */
4689 if (set)
4690 {
4691 enum machine_mode inner_mode = GET_MODE (SET_DEST (set));
4692 #ifdef FLOAT_STORE_FLAG_VALUE
4693 REAL_VALUE_TYPE fsfv;
4694 #endif
4695
4696 /* ??? We may not combine comparisons done in a CCmode with
4697 comparisons not done in a CCmode. This is to aid targets
4698 like Alpha that have an IEEE compliant EQ instruction, and
4699 a non-IEEE compliant BEQ instruction. The use of CCmode is
4700 actually artificial, simply to prevent the combination, but
4701 should not affect other platforms.
4702
4703 However, we must allow VOIDmode comparisons to match either
4704 CCmode or non-CCmode comparison, because some ports have
4705 modeless comparisons inside branch patterns.
4706
4707 ??? This mode check should perhaps look more like the mode check
4708 in simplify_comparison in combine. */
4709
4710 if ((GET_CODE (SET_SRC (set)) == COMPARE
4711 || (((code == NE
4712 || (code == LT
4713 && GET_MODE_CLASS (inner_mode) == MODE_INT
4714 && (GET_MODE_BITSIZE (inner_mode)
4715 <= HOST_BITS_PER_WIDE_INT)
4716 && (STORE_FLAG_VALUE
4717 & ((HOST_WIDE_INT) 1
4718 << (GET_MODE_BITSIZE (inner_mode) - 1))))
4719 #ifdef FLOAT_STORE_FLAG_VALUE
4720 || (code == LT
4721 && GET_MODE_CLASS (inner_mode) == MODE_FLOAT
4722 && (fsfv = FLOAT_STORE_FLAG_VALUE (inner_mode),
4723 REAL_VALUE_NEGATIVE (fsfv)))
4724 #endif
4725 ))
4726 && COMPARISON_P (SET_SRC (set))))
4727 && (((GET_MODE_CLASS (mode) == MODE_CC)
4728 == (GET_MODE_CLASS (inner_mode) == MODE_CC))
4729 || mode == VOIDmode || inner_mode == VOIDmode))
4730 x = SET_SRC (set);
4731 else if (((code == EQ
4732 || (code == GE
4733 && (GET_MODE_BITSIZE (inner_mode)
4734 <= HOST_BITS_PER_WIDE_INT)
4735 && GET_MODE_CLASS (inner_mode) == MODE_INT
4736 && (STORE_FLAG_VALUE
4737 & ((HOST_WIDE_INT) 1
4738 << (GET_MODE_BITSIZE (inner_mode) - 1))))
4739 #ifdef FLOAT_STORE_FLAG_VALUE
4740 || (code == GE
4741 && GET_MODE_CLASS (inner_mode) == MODE_FLOAT
4742 && (fsfv = FLOAT_STORE_FLAG_VALUE (inner_mode),
4743 REAL_VALUE_NEGATIVE (fsfv)))
4744 #endif
4745 ))
4746 && COMPARISON_P (SET_SRC (set))
4747 && (((GET_MODE_CLASS (mode) == MODE_CC)
4748 == (GET_MODE_CLASS (inner_mode) == MODE_CC))
4749 || mode == VOIDmode || inner_mode == VOIDmode))
4750
4751 {
4752 reverse_code = 1;
4753 x = SET_SRC (set);
4754 }
4755 else
4756 break;
4757 }
4758
4759 else if (reg_set_p (op0, prev))
4760 /* If this sets OP0, but not directly, we have to give up. */
4761 break;
4762
4763 if (x)
4764 {
4765 /* If the caller is expecting the condition to be valid at INSN,
4766 make sure X doesn't change before INSN. */
4767 if (valid_at_insn_p)
4768 if (modified_in_p (x, prev) || modified_between_p (x, prev, insn))
4769 break;
4770 if (COMPARISON_P (x))
4771 code = GET_CODE (x);
4772 if (reverse_code)
4773 {
4774 code = reversed_comparison_code (x, prev);
4775 if (code == UNKNOWN)
4776 return 0;
4777 reverse_code = 0;
4778 }
4779
4780 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
4781 if (earliest)
4782 *earliest = prev;
4783 }
4784 }
4785
4786 /* If constant is first, put it last. */
4787 if (CONSTANT_P (op0))
4788 code = swap_condition (code), tem = op0, op0 = op1, op1 = tem;
4789
4790 /* If OP0 is the result of a comparison, we weren't able to find what
4791 was really being compared, so fail. */
4792 if (!allow_cc_mode
4793 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
4794 return 0;
4795
4796 /* Canonicalize any ordered comparison with integers involving equality
4797 if we can do computations in the relevant mode and we do not
4798 overflow. */
4799
4800 if (GET_MODE_CLASS (GET_MODE (op0)) != MODE_CC
4801 && GET_CODE (op1) == CONST_INT
4802 && GET_MODE (op0) != VOIDmode
4803 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT)
4804 {
4805 HOST_WIDE_INT const_val = INTVAL (op1);
4806 unsigned HOST_WIDE_INT uconst_val = const_val;
4807 unsigned HOST_WIDE_INT max_val
4808 = (unsigned HOST_WIDE_INT) GET_MODE_MASK (GET_MODE (op0));
4809
4810 switch (code)
4811 {
4812 case LE:
4813 if ((unsigned HOST_WIDE_INT) const_val != max_val >> 1)
4814 code = LT, op1 = gen_int_mode (const_val + 1, GET_MODE (op0));
4815 break;
4816
4817 /* When cross-compiling, const_val might be sign-extended from
4818 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
4819 case GE:
4820 if ((HOST_WIDE_INT) (const_val & max_val)
4821 != (((HOST_WIDE_INT) 1
4822 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
4823 code = GT, op1 = gen_int_mode (const_val - 1, GET_MODE (op0));
4824 break;
4825
4826 case LEU:
4827 if (uconst_val < max_val)
4828 code = LTU, op1 = gen_int_mode (uconst_val + 1, GET_MODE (op0));
4829 break;
4830
4831 case GEU:
4832 if (uconst_val != 0)
4833 code = GTU, op1 = gen_int_mode (uconst_val - 1, GET_MODE (op0));
4834 break;
4835
4836 default:
4837 break;
4838 }
4839 }
4840
4841 /* Never return CC0; return zero instead. */
4842 if (CC0_P (op0))
4843 return 0;
4844
4845 return gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
4846 }
4847
4848 /* Given a jump insn JUMP, return the condition that will cause it to branch
4849 to its JUMP_LABEL. If the condition cannot be understood, or is an
4850 inequality floating-point comparison which needs to be reversed, 0 will
4851 be returned.
4852
4853 If EARLIEST is nonzero, it is a pointer to a place where the earliest
4854 insn used in locating the condition was found. If a replacement test
4855 of the condition is desired, it should be placed in front of that
4856 insn and we will be sure that the inputs are still valid. If EARLIEST
4857 is null, the returned condition will be valid at INSN.
4858
4859 If ALLOW_CC_MODE is nonzero, allow the condition returned to be a
4860 compare CC mode register.
4861
4862 VALID_AT_INSN_P is the same as for canonicalize_condition. */
4863
4864 rtx
get_condition(rtx jump,rtx * earliest,int allow_cc_mode,int valid_at_insn_p)4865 get_condition (rtx jump, rtx *earliest, int allow_cc_mode, int valid_at_insn_p)
4866 {
4867 rtx cond;
4868 int reverse;
4869 rtx set;
4870
4871 /* If this is not a standard conditional jump, we can't parse it. */
4872 if (!JUMP_P (jump)
4873 || ! any_condjump_p (jump))
4874 return 0;
4875 set = pc_set (jump);
4876
4877 cond = XEXP (SET_SRC (set), 0);
4878
4879 /* If this branches to JUMP_LABEL when the condition is false, reverse
4880 the condition. */
4881 reverse
4882 = GET_CODE (XEXP (SET_SRC (set), 2)) == LABEL_REF
4883 && XEXP (XEXP (SET_SRC (set), 2), 0) == JUMP_LABEL (jump);
4884
4885 return canonicalize_condition (jump, cond, reverse, earliest, NULL_RTX,
4886 allow_cc_mode, valid_at_insn_p);
4887 }
4888
4889
4890 /* Initialize non_rtx_starting_operands, which is used to speed up
4891 for_each_rtx. */
4892 void
init_rtlanal(void)4893 init_rtlanal (void)
4894 {
4895 int i;
4896 for (i = 0; i < NUM_RTX_CODE; i++)
4897 {
4898 const char *format = GET_RTX_FORMAT (i);
4899 const char *first = strpbrk (format, "eEV");
4900 non_rtx_starting_operands[i] = first ? first - format : -1;
4901 }
4902 }
4903