1/* File: startup_ARMCM7.S
2 * Purpose: startup file for Cortex-M7 devices. Should use with
3 *   GCC for ARM Embedded Processors
4 * Version: V1.00
5 * Date: 22 August 2014
6 *
7 */
8/* Copyright (c) 2011 - 2014 ARM LIMITED
9
10   All rights reserved.
11   Redistribution and use in source and binary forms, with or without
12   modification, are permitted provided that the following conditions are met:
13   - Redistributions of source code must retain the above copyright
14     notice, this list of conditions and the following disclaimer.
15   - Redistributions in binary form must reproduce the above copyright
16     notice, this list of conditions and the following disclaimer in the
17     documentation and/or other materials provided with the distribution.
18   - Neither the name of ARM nor the names of its contributors may be used
19     to endorse or promote products derived from this software without
20     specific prior written permission.
21   *
22   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
26   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32   POSSIBILITY OF SUCH DAMAGE.
33   ---------------------------------------------------------------------------*/
34
35
36	.syntax	unified
37	.arch	armv7-m
38
39	.section .stack
40	.align	3
41#ifdef __STACK_SIZE
42	.equ	Stack_Size, __STACK_SIZE
43#else
44	.equ	Stack_Size, 0x00000400
45#endif
46	.globl	__StackTop
47	.globl	__StackLimit
48__StackLimit:
49	.space	Stack_Size
50	.size	__StackLimit, . - __StackLimit
51__StackTop:
52	.size	__StackTop, . - __StackTop
53
54	.section .heap
55	.align	3
56#ifdef __HEAP_SIZE
57	.equ	Heap_Size, __HEAP_SIZE
58#else
59	.equ	Heap_Size, 0x00000C00
60#endif
61	.globl	__HeapBase
62	.globl	__HeapLimit
63__HeapBase:
64	.if	Heap_Size
65	.space	Heap_Size
66	.endif
67	.size	__HeapBase, . - __HeapBase
68__HeapLimit:
69	.size	__HeapLimit, . - __HeapLimit
70
71	.section .vectors
72	.align	2
73	.globl	__Vectors
74__Vectors:
75	.long	__StackTop            /* Top of Stack */
76	.long	Reset_Handler         /* Reset Handler */
77	.long	NMI_Handler           /* NMI Handler */
78	.long	HardFault_Handler     /* Hard Fault Handler */
79	.long	MemManage_Handler     /* MPU Fault Handler */
80	.long	BusFault_Handler      /* Bus Fault Handler */
81	.long	UsageFault_Handler    /* Usage Fault Handler */
82	.long	0                     /* Reserved */
83	.long	0                     /* Reserved */
84	.long	0                     /* Reserved */
85	.long	0                     /* Reserved */
86	.long	SVC_Handler           /* SVCall Handler */
87	.long	DebugMon_Handler      /* Debug Monitor Handler */
88	.long	0                     /* Reserved */
89	.long	PendSV_Handler        /* PendSV Handler */
90	.long	SysTick_Handler       /* SysTick Handler */
91
92	/* External interrupts */
93	.long	WDT_IRQHandler        /*  0:  Watchdog Timer            */
94	.long	RTC_IRQHandler        /*  1:  Real Time Clock           */
95	.long	TIM0_IRQHandler       /*  2:  Timer0 / Timer1           */
96	.long	TIM2_IRQHandler       /*  3:  Timer2 / Timer3           */
97	.long	MCIA_IRQHandler       /*  4:  MCIa                      */
98	.long	MCIB_IRQHandler       /*  5:  MCIb                      */
99	.long	UART0_IRQHandler      /*  6:  UART0 - DUT FPGA          */
100	.long	UART1_IRQHandler      /*  7:  UART1 - DUT FPGA          */
101	.long	UART2_IRQHandler      /*  8:  UART2 - DUT FPGA          */
102	.long	UART4_IRQHandler      /*  9:  UART4 - not connected     */
103	.long	AACI_IRQHandler       /* 10: AACI / AC97                */
104	.long	CLCD_IRQHandler       /* 11: CLCD Combined Interrupt    */
105	.long	ENET_IRQHandler       /* 12: Ethernet                   */
106	.long	USBDC_IRQHandler      /* 13: USB Device                 */
107	.long	USBHC_IRQHandler      /* 14: USB Host Controller        */
108	.long	CHLCD_IRQHandler      /* 15: Character LCD              */
109	.long	FLEXRAY_IRQHandler    /* 16: Flexray                    */
110	.long	CAN_IRQHandler        /* 17: CAN                        */
111	.long	LIN_IRQHandler        /* 18: LIN                        */
112	.long	I2C_IRQHandler        /* 19: I2C ADC/DAC                */
113	.long	0                     /* 20: Reserved                   */
114	.long	0                     /* 21: Reserved                   */
115	.long	0                     /* 22: Reserved                   */
116	.long	0                     /* 23: Reserved                   */
117	.long	0                     /* 24: Reserved                   */
118	.long	0                     /* 25: Reserved                   */
119	.long	0                     /* 26: Reserved                   */
120	.long	0                     /* 27: Reserved                   */
121	.long	CPU_CLCD_IRQHandler   /* 28: Reserved - CPU FPGA CLCD   */
122	.long	0                     /* 29: Reserved - CPU FPGA        */
123	.long	UART3_IRQHandler      /* 30: UART3    - CPU FPGA        */
124	.long	SPI_IRQHandler        /* 31: SPI Touchscreen - CPU FPGA */
125
126	.size	__Vectors, . - __Vectors
127
128	.text
129	.thumb
130	.thumb_func
131	.align	2
132	.globl	Reset_Handler
133	.type	Reset_Handler, %function
134Reset_Handler:
135/*  Firstly it copies data from read only memory to RAM. There are two schemes
136 *  to copy. One can copy more than one sections. Another can only copy
137 *  one section.  The former scheme needs more instructions and read-only
138 *  data to implement than the latter.
139 *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */
140
141#ifdef __STARTUP_COPY_MULTIPLE
142/*  Multiple sections scheme.
143 *
144 *  Between symbol address __copy_table_start__ and __copy_table_end__,
145 *  there are array of triplets, each of which specify:
146 *    offset 0: LMA of start of a section to copy from
147 *    offset 4: VMA of start of a section to copy to
148 *    offset 8: size of the section to copy. Must be multiply of 4
149 *
150 *  All addresses must be aligned to 4 bytes boundary.
151 */
152	ldr	r4, =__copy_table_start__
153	ldr	r5, =__copy_table_end__
154
155.L_loop0:
156	cmp	r4, r5
157	bge	.L_loop0_done
158	ldr	r1, [r4]
159	ldr	r2, [r4, #4]
160	ldr	r3, [r4, #8]
161
162.L_loop0_0:
163	subs	r3, #4
164	ittt	ge
165	ldrge	r0, [r1, r3]
166	strge	r0, [r2, r3]
167	bge	.L_loop0_0
168
169	adds	r4, #12
170	b	.L_loop0
171
172.L_loop0_done:
173#else
174/*  Single section scheme.
175 *
176 *  The ranges of copy from/to are specified by following symbols
177 *    __etext: LMA of start of the section to copy from. Usually end of text
178 *    __data_start__: VMA of start of the section to copy to
179 *    __data_end__: VMA of end of the section to copy to
180 *
181 *  All addresses must be aligned to 4 bytes boundary.
182 */
183	ldr	r1, =__etext
184	ldr	r2, =__data_start__
185	ldr	r3, =__data_end__
186
187.L_loop1:
188	cmp	r2, r3
189	ittt	lt
190	ldrlt	r0, [r1], #4
191	strlt	r0, [r2], #4
192	blt	.L_loop1
193#endif /*__STARTUP_COPY_MULTIPLE */
194
195/*  This part of work usually is done in C library startup code. Otherwise,
196 *  define this macro to enable it in this startup.
197 *
198 *  There are two schemes too. One can clear multiple BSS sections. Another
199 *  can only clear one section. The former is more size expensive than the
200 *  latter.
201 *
202 *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
203 *  Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
204 */
205#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
206/*  Multiple sections scheme.
207 *
208 *  Between symbol address __copy_table_start__ and __copy_table_end__,
209 *  there are array of tuples specifying:
210 *    offset 0: Start of a BSS section
211 *    offset 4: Size of this BSS section. Must be multiply of 4
212 */
213	ldr	r3, =__zero_table_start__
214	ldr	r4, =__zero_table_end__
215
216.L_loop2:
217	cmp	r3, r4
218	bge	.L_loop2_done
219	ldr	r1, [r3]
220	ldr	r2, [r3, #4]
221	movs	r0, 0
222
223.L_loop2_0:
224	subs	r2, #4
225	itt	ge
226	strge	r0, [r1, r2]
227	bge	.L_loop2_0
228
229	adds	r3, #8
230	b	.L_loop2
231.L_loop2_done:
232#elif defined (__STARTUP_CLEAR_BSS)
233/*  Single BSS section scheme.
234 *
235 *  The BSS section is specified by following symbols
236 *    __bss_start__: start of the BSS section.
237 *    __bss_end__: end of the BSS section.
238 *
239 *  Both addresses must be aligned to 4 bytes boundary.
240 */
241	ldr	r1, =__bss_start__
242	ldr	r2, =__bss_end__
243
244	movs	r0, 0
245.L_loop3:
246	cmp	r1, r2
247	itt	lt
248	strlt	r0, [r1], #4
249	blt	.L_loop3
250#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
251
252#ifndef __NO_SYSTEM_INIT
253	bl	SystemInit
254#endif
255
256#ifndef __START
257#define __START _start
258#endif
259	bl	__START
260
261	.pool
262	.size	Reset_Handler, . - Reset_Handler
263
264	.align	1
265	.thumb_func
266	.weak	Default_Handler
267	.type	Default_Handler, %function
268Default_Handler:
269	b	.
270	.size	Default_Handler, . - Default_Handler
271
272/*    Macro to define default handlers. Default handler
273 *    will be weak symbol and just dead loops. They can be
274 *    overwritten by other handlers */
275	.macro	def_irq_handler	handler_name
276	.weak	\handler_name
277	.set	\handler_name, Default_Handler
278	.endm
279
280	def_irq_handler	NMI_Handler
281	def_irq_handler	HardFault_Handler
282	def_irq_handler	MemManage_Handler
283	def_irq_handler	BusFault_Handler
284	def_irq_handler	UsageFault_Handler
285	def_irq_handler	SVC_Handler
286	def_irq_handler	DebugMon_Handler
287	def_irq_handler	PendSV_Handler
288	def_irq_handler	SysTick_Handler
289
290	def_irq_handler	WDT_IRQHandler
291	def_irq_handler	RTC_IRQHandler
292	def_irq_handler	TIM0_IRQHandler
293	def_irq_handler	TIM2_IRQHandler
294	def_irq_handler	MCIA_IRQHandler
295	def_irq_handler	MCIB_IRQHandler
296	def_irq_handler	UART0_IRQHandler
297	def_irq_handler	UART1_IRQHandler
298	def_irq_handler	UART2_IRQHandler
299	def_irq_handler	UART3_IRQHandler
300	def_irq_handler	UART4_IRQHandler
301	def_irq_handler	AACI_IRQHandler
302	def_irq_handler	CLCD_IRQHandler
303	def_irq_handler	ENET_IRQHandler
304	def_irq_handler	USBDC_IRQHandler
305	def_irq_handler	USBHC_IRQHandler
306	def_irq_handler	CHLCD_IRQHandler
307	def_irq_handler	FLEXRAY_IRQHandler
308	def_irq_handler	CAN_IRQHandler
309	def_irq_handler	LIN_IRQHandler
310	def_irq_handler	I2C_IRQHandler
311	def_irq_handler	CPU_CLCD_IRQHandler
312	def_irq_handler	SPI_IRQHandler
313
314	.end
315