1//==-- AArch64Schedule.td - AArch64 Scheduling Definitions -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9// Define TII for use in SchedVariant Predicates. 10// const MachineInstr *MI and const TargetSchedModel *SchedModel 11// are defined by default. 12def : PredicateProlog<[{ 13 const AArch64InstrInfo *TII = 14 static_cast<const AArch64InstrInfo*>(SchedModel->getInstrInfo()); 15 (void)TII; 16}]>; 17 18// AArch64 Scheduler Definitions 19 20def WriteImm : SchedWrite; // MOVN, MOVZ 21// TODO: Provide variants for MOV32/64imm Pseudos that dynamically 22// select the correct sequence of WriteImms. 23 24def WriteI : SchedWrite; // ALU 25def WriteISReg : SchedWrite; // ALU of Shifted-Reg 26def WriteIEReg : SchedWrite; // ALU of Extended-Reg 27def ReadI : SchedRead; // ALU 28def ReadISReg : SchedRead; // ALU of Shifted-Reg 29def ReadIEReg : SchedRead; // ALU of Extended-Reg 30def WriteExtr : SchedWrite; // EXTR shifts a reg pair 31def ReadExtrHi : SchedRead; // Read the high reg of the EXTR pair 32def WriteIS : SchedWrite; // Shift/Scale 33def WriteID32 : SchedWrite; // 32-bit Divide 34def WriteID64 : SchedWrite; // 64-bit Divide 35def ReadID : SchedRead; // 32/64-bit Divide 36def WriteIM32 : SchedWrite; // 32-bit Multiply 37def WriteIM64 : SchedWrite; // 64-bit Multiply 38def ReadIM : SchedRead; // 32/64-bit Multiply 39def ReadIMA : SchedRead; // 32/64-bit Multiply Accumulate 40def WriteBr : SchedWrite; // Branch 41def WriteBrReg : SchedWrite; // Indirect Branch 42 43def WriteLD : SchedWrite; // Load from base addr plus immediate offset 44def WriteST : SchedWrite; // Store to base addr plus immediate offset 45def WriteSTP : SchedWrite; // Store a register pair. 46def WriteAdr : SchedWrite; // Address pre/post increment. 47 48def WriteLDIdx : SchedWrite; // Load from a register index (maybe scaled). 49def WriteSTIdx : SchedWrite; // Store to a register index (maybe scaled). 50def ReadAdrBase : SchedRead; // Read the base resister of a reg-offset LD/ST. 51 52// Serialized two-level address load. 53// EXAMPLE: LOADGot 54def WriteLDAdr : WriteSequence<[WriteAdr, WriteLD]>; 55 56// Serialized two-level address lookup. 57// EXAMPLE: MOVaddr... 58def WriteAdrAdr : WriteSequence<[WriteAdr, WriteAdr]>; 59 60// The second register of a load-pair. 61// LDP,LDPSW,LDNP,LDXP,LDAXP 62def WriteLDHi : SchedWrite; 63 64// Store-exclusive is a store followed by a dependent load. 65def WriteSTX : WriteSequence<[WriteST, WriteLD]>; 66 67def WriteSys : SchedWrite; // Long, variable latency system ops. 68def WriteBarrier : SchedWrite; // Memory barrier. 69def WriteHint : SchedWrite; // Hint instruction. 70 71def WriteF : SchedWrite; // General floating-point ops. 72def WriteFCmp : SchedWrite; // Floating-point compare. 73def WriteFCvt : SchedWrite; // Float conversion. 74def WriteFCopy : SchedWrite; // Float-int register copy. 75def WriteFImm : SchedWrite; // Floating-point immediate. 76def WriteFMul : SchedWrite; // Floating-point multiply. 77def WriteFDiv : SchedWrite; // Floating-point division. 78 79def WriteV : SchedWrite; // Vector ops. 80def WriteVLD : SchedWrite; // Vector loads. 81def WriteVST : SchedWrite; // Vector stores. 82 83def WriteAtomic : SchedWrite; // Atomic memory operations (CAS, Swap, LDOP) 84 85// Read the unwritten lanes of the VLD's destination registers. 86def ReadVLD : SchedRead; 87 88// Sequential vector load and shuffle. 89def WriteVLDShuffle : WriteSequence<[WriteVLD, WriteV]>; 90def WriteVLDPairShuffle : WriteSequence<[WriteVLD, WriteV, WriteV]>; 91 92// Store a shuffled vector. 93def WriteVSTShuffle : WriteSequence<[WriteV, WriteVST]>; 94def WriteVSTPairShuffle : WriteSequence<[WriteV, WriteV, WriteVST]>; 95