1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mcpu=pwr7 -ppc-asm-full-reg-names -verify-machineinstrs \ 3; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \ 4; RUN: -check-prefix=P7BE 5; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -verify-machineinstrs \ 6; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \ 7; RUN: -check-prefix=P8LE 8; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -verify-machineinstrs \ 9; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \ 10; RUN: -check-prefix=P9LE 11 12; FIXME: P7BE for i128 looks wrong. 13define <1 x i128> @One1i128() { 14; P7BE-LABEL: One1i128: 15; P7BE: # %bb.0: # %entry 16; P7BE-NEXT: li r3, -1 17; P7BE-NEXT: li r4, -1 18; P7BE-NEXT: blr 19; 20; P8LE-LABEL: One1i128: 21; P8LE: # %bb.0: # %entry 22; P8LE-NEXT: xxleqv vs34, vs34, vs34 23; P8LE-NEXT: blr 24; 25; P9LE-LABEL: One1i128: 26; P9LE: # %bb.0: # %entry 27; P9LE-NEXT: xxleqv vs34, vs34, vs34 28; P9LE-NEXT: blr 29entry: 30 ret <1 x i128> <i128 -1> 31} 32 33define <2 x i64> @One2i64() { 34; P7BE-LABEL: One2i64: 35; P7BE: # %bb.0: # %entry 36; P7BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha 37; P7BE-NEXT: addi r3, r3, .LCPI1_0@toc@l 38; P7BE-NEXT: lxvd2x vs34, 0, r3 39; P7BE-NEXT: blr 40; 41; P8LE-LABEL: One2i64: 42; P8LE: # %bb.0: # %entry 43; P8LE-NEXT: xxleqv vs34, vs34, vs34 44; P8LE-NEXT: blr 45; 46; P9LE-LABEL: One2i64: 47; P9LE: # %bb.0: # %entry 48; P9LE-NEXT: xxleqv vs34, vs34, vs34 49; P9LE-NEXT: blr 50entry: 51 ret <2 x i64> <i64 -1, i64 -1> 52} 53 54define <4 x i32> @One4i32() { 55; P7BE-LABEL: One4i32: 56; P7BE: # %bb.0: # %entry 57; P7BE-NEXT: vspltisb v2, -1 58; P7BE-NEXT: blr 59; 60; P8LE-LABEL: One4i32: 61; P8LE: # %bb.0: # %entry 62; P8LE-NEXT: xxleqv vs34, vs34, vs34 63; P8LE-NEXT: blr 64; 65; P9LE-LABEL: One4i32: 66; P9LE: # %bb.0: # %entry 67; P9LE-NEXT: xxleqv vs34, vs34, vs34 68; P9LE-NEXT: blr 69entry: 70 ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1> 71} 72 73define <8 x i16> @One8i16() { 74; P7BE-LABEL: One8i16: 75; P7BE: # %bb.0: # %entry 76; P7BE-NEXT: vspltisb v2, -1 77; P7BE-NEXT: blr 78; 79; P8LE-LABEL: One8i16: 80; P8LE: # %bb.0: # %entry 81; P8LE-NEXT: xxleqv vs34, vs34, vs34 82; P8LE-NEXT: blr 83; 84; P9LE-LABEL: One8i16: 85; P9LE: # %bb.0: # %entry 86; P9LE-NEXT: xxleqv vs34, vs34, vs34 87; P9LE-NEXT: blr 88entry: 89 ret <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> 90} 91 92define <16 x i8> @One16i8() { 93; P7BE-LABEL: One16i8: 94; P7BE: # %bb.0: # %entry 95; P7BE-NEXT: vspltisb v2, -1 96; P7BE-NEXT: blr 97; 98; P8LE-LABEL: One16i8: 99; P8LE: # %bb.0: # %entry 100; P8LE-NEXT: xxleqv vs34, vs34, vs34 101; P8LE-NEXT: blr 102; 103; P9LE-LABEL: One16i8: 104; P9LE: # %bb.0: # %entry 105; P9LE-NEXT: xxleqv vs34, vs34, vs34 106; P9LE-NEXT: blr 107entry: 108 ret <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> 109} 110