1; RUN: llc -ppc-reduce-cr-logicals -verify-machineinstrs -tail-dup-placement=false < %s | FileCheck %s 2; RUN: llc -ppc-reduce-cr-logicals -verify-machineinstrs \ 3; RUN: -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s 4target datalayout = "E-m:e-i64:64-n32:64" 5target triple = "powerpc64-unknown-linux-gnu" 6 7; FIXME: We should check the operands to the cr* logical operation itself, but 8; unfortunately, FileCheck does not yet understand how to do arithmetic, so we 9; can't do so without introducing a register-allocation dependency. 10 11define signext i32 @testi32slt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { 12entry: 13 %cmp1 = icmp eq i32 %c3, %c4 14 %cmp3tmp = icmp eq i32 %c1, %c2 15 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1 16 %cond = select i1 %cmp3, i32 %a1, i32 %a2 17 ret i32 %cond 18 19; CHECK-LABEL: @testi32slt 20; CHECK-NO-ISEL-LABEL: @testi32slt 21; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 22; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 23; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 24; CHECK: isel 3, 7, 8, [[REG1]] 25; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 26; CHECK-NO-ISEL: ori 3, 8, 0 27; CHECK-NO-ISEL-NEXT: blr 28; CHECK-NO-ISEL: [[TRUE]] 29; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 30; CHECK-NO-ISEL-NEXT: blr 31; CHECK: blr 32} 33 34define signext i32 @testi32ult(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { 35entry: 36 %cmp1 = icmp eq i32 %c3, %c4 37 %cmp3tmp = icmp eq i32 %c1, %c2 38 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1 39 %cond = select i1 %cmp3, i32 %a1, i32 %a2 40 ret i32 %cond 41 42; CHECK-NO-ISEL-LABEL: @testi32ult 43; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 44; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 45; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 46; CHECK: isel 3, 7, 8, [[REG1]] 47; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 48; CHECK-NO-ISEL: ori 3, 8, 0 49; CHECK-NO-ISEL-NEXT: blr 50; CHECK-NO-ISEL: [[TRUE]] 51; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 52; CHECK-NO-ISEL-NEXT: blr 53; CHECK: blr 54} 55 56define signext i32 @testi32sle(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { 57entry: 58 %cmp1 = icmp eq i32 %c3, %c4 59 %cmp3tmp = icmp eq i32 %c1, %c2 60 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1 61 %cond = select i1 %cmp3, i32 %a1, i32 %a2 62 ret i32 %cond 63 64; CHECK-LABEL: @testi32sle 65; CHECK-NO-ISEL-LABEL: @testi32sle 66; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 67; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 68; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 69; CHECK: isel 3, 7, 8, [[REG1]] 70; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 71; CHECK-NO-ISEL: ori 3, 8, 0 72; CHECK-NO-ISEL-NEXT: blr 73; CHECK-NO-ISEL: [[TRUE]] 74; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 75; CHECK-NO-ISEL-NEXT: blr 76; CHECK: blr 77} 78 79define signext i32 @testi32ule(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { 80entry: 81 %cmp1 = icmp eq i32 %c3, %c4 82 %cmp3tmp = icmp eq i32 %c1, %c2 83 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1 84 %cond = select i1 %cmp3, i32 %a1, i32 %a2 85 ret i32 %cond 86 87; CHECK-LABEL: @testi32ule 88; CHECK-NO-ISEL-LABEL: @testi32ule 89; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 90; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 91; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 92; CHECK: isel 3, 7, 8, [[REG1]] 93; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 94; CHECK-NO-ISEL: ori 3, 8, 0 95; CHECK-NO-ISEL-NEXT: blr 96; CHECK-NO-ISEL: [[TRUE]] 97; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 98; CHECK-NO-ISEL-NEXT: blr 99; CHECK: blr 100} 101 102define signext i32 @testi32eq(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { 103entry: 104 %cmp1 = icmp eq i32 %c3, %c4 105 %cmp3tmp = icmp eq i32 %c1, %c2 106 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1 107 %cond = select i1 %cmp3, i32 %a1, i32 %a2 108 ret i32 %cond 109 110; CHECK-LABEL: @testi32eq 111; CHECK-NO-ISEL-LABEL: @testi32eq 112; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 113; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 114; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 115; CHECK: isel 3, 7, 8, [[REG1]] 116; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 117; CHECK-NO-ISEL: ori 3, 8, 0 118; CHECK-NO-ISEL-NEXT: blr 119; CHECK-NO-ISEL: [[TRUE]] 120; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 121; CHECK-NO-ISEL-NEXT: blr 122; CHECK: blr 123} 124 125define signext i32 @testi32sge(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { 126entry: 127 %cmp1 = icmp eq i32 %c3, %c4 128 %cmp3tmp = icmp eq i32 %c1, %c2 129 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1 130 %cond = select i1 %cmp3, i32 %a1, i32 %a2 131 ret i32 %cond 132 133; CHECK-LABEL: @testi32sge 134; CHECK-NO-ISEL-LABEL: @testi32sge 135; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 136; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 137; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 138; CHECK: isel 3, 7, 8, [[REG1]] 139; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 140; CHECK-NO-ISEL: ori 3, 8, 0 141; CHECK-NO-ISEL-NEXT: blr 142; CHECK-NO-ISEL: [[TRUE]] 143; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 144; CHECK-NO-ISEL-NEXT: blr 145; CHECK: blr 146} 147 148define signext i32 @testi32uge(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { 149entry: 150 %cmp1 = icmp eq i32 %c3, %c4 151 %cmp3tmp = icmp eq i32 %c1, %c2 152 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1 153 %cond = select i1 %cmp3, i32 %a1, i32 %a2 154 ret i32 %cond 155 156; CHECK-LABEL: @testi32uge 157; CHECK-NO-ISEL-LABEL: @testi32uge 158; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 159; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 160; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 161; CHECK: isel 3, 7, 8, [[REG1]] 162; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 163; CHECK-NO-ISEL: ori 3, 8, 0 164; CHECK-NO-ISEL-NEXT: blr 165; CHECK-NO-ISEL: [[TRUE]] 166; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 167; CHECK-NO-ISEL-NEXT: blr 168; CHECK: blr 169} 170 171define signext i32 @testi32sgt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { 172entry: 173 %cmp1 = icmp eq i32 %c3, %c4 174 %cmp3tmp = icmp eq i32 %c1, %c2 175 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1 176 %cond = select i1 %cmp3, i32 %a1, i32 %a2 177 ret i32 %cond 178 179; CHECK-LABEL: @testi32sgt 180; CHECK-NO-ISEL-LABEL: @testi32sgt 181; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 182; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 183; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 184; CHECK: isel 3, 7, 8, [[REG1]] 185; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 186; CHECK-NO-ISEL: ori 3, 8, 0 187; CHECK-NO-ISEL-NEXT: blr 188; CHECK-NO-ISEL: [[TRUE]] 189; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 190; CHECK-NO-ISEL-NEXT: blr 191; CHECK: blr 192} 193 194define signext i32 @testi32ugt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { 195entry: 196 %cmp1 = icmp eq i32 %c3, %c4 197 %cmp3tmp = icmp eq i32 %c1, %c2 198 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1 199 %cond = select i1 %cmp3, i32 %a1, i32 %a2 200 ret i32 %cond 201 202; CHECK-LABEL: @testi32ugt 203; CHECK-NO-ISEL-LABEL: @testi32ugt 204; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 205; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 206; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 207; CHECK: isel 3, 7, 8, [[REG1]] 208; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 209; CHECK-NO-ISEL: ori 3, 8, 0 210; CHECK-NO-ISEL-NEXT: blr 211; CHECK-NO-ISEL: [[TRUE]] 212; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 213; CHECK-NO-ISEL-NEXT: blr 214; CHECK: blr 215} 216 217define signext i32 @testi32ne(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { 218entry: 219 %cmp1 = icmp eq i32 %c3, %c4 220 %cmp3tmp = icmp eq i32 %c1, %c2 221 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1 222 %cond = select i1 %cmp3, i32 %a1, i32 %a2 223 ret i32 %cond 224 225; CHECK-LABEL: @testi32ne 226; CHECK-NO-ISEL-LABEL: @testi32ne 227; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 228; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 229; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 230; CHECK: isel 3, 7, 8, [[REG1]] 231; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 232; CHECK-NO-ISEL: ori 3, 8, 0 233; CHECK-NO-ISEL-NEXT: blr 234; CHECK-NO-ISEL: [[TRUE]] 235; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 236; CHECK-NO-ISEL-NEXT: blr 237; CHECK: blr 238} 239 240define i64 @testi64slt(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { 241entry: 242 %cmp1 = icmp eq i64 %c3, %c4 243 %cmp3tmp = icmp eq i64 %c1, %c2 244 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1 245 %cond = select i1 %cmp3, i64 %a1, i64 %a2 246 ret i64 %cond 247 248; CHECK-LABEL: @testi64slt 249; CHECK-NO-ISEL-LABEL: @testi64slt 250; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6 251; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4 252; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 253; CHECK: isel 3, 7, 8, [[REG1]] 254; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 255; CHECK-NO-ISEL: ori 3, 8, 0 256; CHECK-NO-ISEL-NEXT: blr 257; CHECK-NO-ISEL: [[TRUE]] 258; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 259; CHECK-NO-ISEL-NEXT: blr 260; CHECK: blr 261} 262 263define i64 @testi64ult(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { 264entry: 265 %cmp1 = icmp eq i64 %c3, %c4 266 %cmp3tmp = icmp eq i64 %c1, %c2 267 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1 268 %cond = select i1 %cmp3, i64 %a1, i64 %a2 269 ret i64 %cond 270 271; CHECK-LABEL: @testi64ult 272; CHECK-NO-ISEL-LABEL: @testi64ult 273; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6 274; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4 275; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 276; CHECK: isel 3, 7, 8, [[REG1]] 277; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 278; CHECK-NO-ISEL: ori 3, 8, 0 279; CHECK-NO-ISEL-NEXT: blr 280; CHECK-NO-ISEL: [[TRUE]] 281; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 282; CHECK-NO-ISEL-NEXT: blr 283; CHECK: blr 284} 285 286define i64 @testi64sle(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { 287entry: 288 %cmp1 = icmp eq i64 %c3, %c4 289 %cmp3tmp = icmp eq i64 %c1, %c2 290 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1 291 %cond = select i1 %cmp3, i64 %a1, i64 %a2 292 ret i64 %cond 293 294; CHECK-LABEL: @testi64sle 295; CHECK-NO-ISEL-LABEL: @testi64sle 296; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6 297; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4 298; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 299; CHECK: isel 3, 7, 8, [[REG1]] 300; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 301; CHECK-NO-ISEL: ori 3, 8, 0 302; CHECK-NO-ISEL-NEXT: blr 303; CHECK-NO-ISEL: [[TRUE]] 304; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 305; CHECK-NO-ISEL-NEXT: blr 306; CHECK: blr 307} 308 309define i64 @testi64ule(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { 310entry: 311 %cmp1 = icmp eq i64 %c3, %c4 312 %cmp3tmp = icmp eq i64 %c1, %c2 313 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1 314 %cond = select i1 %cmp3, i64 %a1, i64 %a2 315 ret i64 %cond 316 317; CHECK-LABEL: @testi64ule 318; CHECK-NO-ISEL-LABEL: @testi64ule 319; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6 320; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4 321; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 322; CHECK: isel 3, 7, 8, [[REG1]] 323; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 324; CHECK-NO-ISEL: ori 3, 8, 0 325; CHECK-NO-ISEL-NEXT: blr 326; CHECK-NO-ISEL: [[TRUE]] 327; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 328; CHECK-NO-ISEL-NEXT: blr 329; CHECK: blr 330} 331 332define i64 @testi64eq(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { 333entry: 334 %cmp1 = icmp eq i64 %c3, %c4 335 %cmp3tmp = icmp eq i64 %c1, %c2 336 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1 337 %cond = select i1 %cmp3, i64 %a1, i64 %a2 338 ret i64 %cond 339 340; CHECK-LABEL: @testi64eq 341; CHECK-NO-ISEL-LABEL: @testi64eq 342; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6 343; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4 344; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 345; CHECK: isel 3, 7, 8, [[REG1]] 346; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 347; CHECK-NO-ISEL: ori 3, 8, 0 348; CHECK-NO-ISEL-NEXT: blr 349; CHECK-NO-ISEL: [[TRUE]] 350; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 351; CHECK-NO-ISEL-NEXT: blr 352; CHECK: blr 353} 354 355define i64 @testi64sge(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { 356entry: 357 %cmp1 = icmp eq i64 %c3, %c4 358 %cmp3tmp = icmp eq i64 %c1, %c2 359 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1 360 %cond = select i1 %cmp3, i64 %a1, i64 %a2 361 ret i64 %cond 362 363; CHECK-LABEL: @testi64sge 364; CHECK-NO-ISEL-LABEL: @testi64sge 365; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6 366; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4 367; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 368; CHECK: isel 3, 7, 8, [[REG1]] 369; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 370; CHECK-NO-ISEL: ori 3, 8, 0 371; CHECK-NO-ISEL-NEXT: blr 372; CHECK-NO-ISEL: [[TRUE]] 373; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 374; CHECK-NO-ISEL-NEXT: blr 375; CHECK: blr 376} 377 378define i64 @testi64uge(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { 379entry: 380 %cmp1 = icmp eq i64 %c3, %c4 381 %cmp3tmp = icmp eq i64 %c1, %c2 382 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1 383 %cond = select i1 %cmp3, i64 %a1, i64 %a2 384 ret i64 %cond 385 386; CHECK-LABEL: @testi64uge 387; CHECK-NO-ISEL-LABEL: @testi64uge 388; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6 389; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4 390; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 391; CHECK: isel 3, 7, 8, [[REG1]] 392; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 393; CHECK-NO-ISEL: ori 3, 8, 0 394; CHECK-NO-ISEL-NEXT: blr 395; CHECK-NO-ISEL: [[TRUE]] 396; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 397; CHECK-NO-ISEL-NEXT: blr 398; CHECK: blr 399} 400 401define i64 @testi64sgt(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { 402entry: 403 %cmp1 = icmp eq i64 %c3, %c4 404 %cmp3tmp = icmp eq i64 %c1, %c2 405 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1 406 %cond = select i1 %cmp3, i64 %a1, i64 %a2 407 ret i64 %cond 408 409; CHECK-LABEL: @testi64sgt 410; CHECK-NO-ISEL-LABEL: @testi64sgt 411; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6 412; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4 413; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 414; CHECK: isel 3, 7, 8, [[REG1]] 415; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 416; CHECK-NO-ISEL: ori 3, 8, 0 417; CHECK-NO-ISEL-NEXT: blr 418; CHECK-NO-ISEL: [[TRUE]] 419; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 420; CHECK-NO-ISEL-NEXT: blr 421; CHECK: blr 422} 423 424define i64 @testi64ugt(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { 425entry: 426 %cmp1 = icmp eq i64 %c3, %c4 427 %cmp3tmp = icmp eq i64 %c1, %c2 428 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1 429 %cond = select i1 %cmp3, i64 %a1, i64 %a2 430 ret i64 %cond 431 432; CHECK-LABEL: @testi64ugt 433; CHECK-NO-ISEL-LABEL: @testi64ugt 434; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6 435; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4 436; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 437; CHECK: isel 3, 7, 8, [[REG1]] 438; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 439; CHECK-NO-ISEL: ori 3, 8, 0 440; CHECK-NO-ISEL-NEXT: blr 441; CHECK-NO-ISEL: [[TRUE]] 442; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 443; CHECK-NO-ISEL-NEXT: blr 444; CHECK: blr 445} 446 447define i64 @testi64ne(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { 448entry: 449 %cmp1 = icmp eq i64 %c3, %c4 450 %cmp3tmp = icmp eq i64 %c1, %c2 451 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1 452 %cond = select i1 %cmp3, i64 %a1, i64 %a2 453 ret i64 %cond 454 455; CHECK-LABEL: @testi64ne 456; CHECK-NO-ISEL-LABEL: @testi64ne 457; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6 458; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4 459; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 460; CHECK: isel 3, 7, 8, [[REG1]] 461; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 462; CHECK-NO-ISEL: ori 3, 8, 0 463; CHECK-NO-ISEL-NEXT: blr 464; CHECK-NO-ISEL: [[TRUE]] 465; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 466; CHECK-NO-ISEL-NEXT: blr 467; CHECK: blr 468} 469 470define float @testfloatslt(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 { 471entry: 472 %cmp1 = fcmp oeq float %c3, %c4 473 %cmp3tmp = fcmp oeq float %c1, %c2 474 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1 475 %cond = select i1 %cmp3, float %a1, float %a2 476 ret float %cond 477 478; CHECK-LABEL: @testfloatslt 479; CHECK: fcmpu {{[0-9]+}}, 3, 4 480; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]] 481; CHECK: fcmpu {{[0-9]+}}, 1, 2 482; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]] 483; CHECK: .LBB[[BB1]]: 484; CHECK: fmr 5, 6 485; CHECK: .LBB[[BB2]]: 486; CHECK: fmr 1, 5 487; CHECK: blr 488} 489 490define float @testfloatult(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 { 491entry: 492 %cmp1 = fcmp oeq float %c3, %c4 493 %cmp3tmp = fcmp oeq float %c1, %c2 494 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1 495 %cond = select i1 %cmp3, float %a1, float %a2 496 ret float %cond 497 498; CHECK-LABEL: @testfloatult 499; CHECK: fcmpu {{[0-9]+}}, 3, 4 500; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]] 501; CHECK: fcmpu {{[0-9]+}}, 1, 2 502; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]] 503; CHECK: .LBB[[BB1]]: 504; CHECK: fmr 5, 6 505; CHECK: .LBB[[BB2]]: 506; CHECK: fmr 1, 5 507; CHECK: blr 508} 509 510define float @testfloatsle(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 { 511entry: 512 %cmp1 = fcmp oeq float %c3, %c4 513 %cmp3tmp = fcmp oeq float %c1, %c2 514 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1 515 %cond = select i1 %cmp3, float %a1, float %a2 516 ret float %cond 517 518; CHECK-LABEL: @testfloatsle 519; CHECK: fcmpu {{[0-9]+}}, 3, 4 520; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]] 521; CHECK: fcmpu {{[0-9]+}}, 1, 2 522; CHECK: bc 12, 2, .LBB[[BB]] 523; CHECK: fmr 5, 6 524; CHECK: .LBB[[BB]]: 525; CHECK: fmr 1, 5 526; CHECK: blr 527} 528 529define float @testfloatule(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 { 530entry: 531 %cmp1 = fcmp oeq float %c3, %c4 532 %cmp3tmp = fcmp oeq float %c1, %c2 533 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1 534 %cond = select i1 %cmp3, float %a1, float %a2 535 ret float %cond 536 537; CHECK-LABEL: @testfloatule 538; CHECK: fcmpu {{[0-9]+}}, 3, 4 539; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] 540; CHECK: fcmpu {{[0-9]+}}, 1, 2 541; CHECK: bc 4, 2, .LBB[[BB]] 542; CHECK: fmr 5, 6 543; CHECK: .LBB[[BB]]: 544; CHECK: fmr 1, 5 545; CHECK: blr 546} 547 548define float @testfloateq(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 { 549entry: 550 %cmp1 = fcmp oeq float %c3, %c4 551 %cmp3tmp = fcmp oeq float %c1, %c2 552 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1 553 %cond = select i1 %cmp3, float %a1, float %a2 554 ret float %cond 555 556; CHECK-LABEL: @testfloateq 557; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 558; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 559; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 560; CHECK: bclr 12, [[REG1]], 0 561; CHECK: fmr 1, 6 562; CHECK: blr 563} 564 565define float @testfloatsge(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 { 566entry: 567 %cmp1 = fcmp oeq float %c3, %c4 568 %cmp3tmp = fcmp oeq float %c1, %c2 569 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1 570 %cond = select i1 %cmp3, float %a1, float %a2 571 ret float %cond 572 573; CHECK-LABEL: @testfloatsge 574; CHECK: fcmpu {{[0-9]+}}, 3, 4 575; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] 576; CHECK: fcmpu {{[0-9]+}}, 1, 2 577; CHECK: bc 4, 2, .LBB[[BB]] 578; CHECK: fmr 5, 6 579; CHECK: .LBB[[BB]]: 580; CHECK: fmr 1, 5 581; CHECK: blr 582} 583 584define float @testfloatuge(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 { 585entry: 586 %cmp1 = fcmp oeq float %c3, %c4 587 %cmp3tmp = fcmp oeq float %c1, %c2 588 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1 589 %cond = select i1 %cmp3, float %a1, float %a2 590 ret float %cond 591 592; CHECK-LABEL: @testfloatuge 593; CHECK: fcmpu {{[0-9]+}}, 3, 4 594; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]] 595; CHECK: fcmpu {{[0-9]+}}, 1, 2 596; CHECK: bc 12, 2, .LBB[[BB]] 597; CHECK: fmr 5, 6 598; CHECK: .LBB[[BB]]: 599; CHECK: fmr 1, 5 600; CHECK: blr 601} 602 603define float @testfloatsgt(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 { 604entry: 605 %cmp1 = fcmp oeq float %c3, %c4 606 %cmp3tmp = fcmp oeq float %c1, %c2 607 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1 608 %cond = select i1 %cmp3, float %a1, float %a2 609 ret float %cond 610 611; CHECK-LABEL: @testfloatsgt 612; CHECK: fcmpu {{[0-9]+}}, 3, 4 613; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]] 614; CHECK: fcmpu {{[0-9]+}}, 1, 2 615; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]] 616; CHECK: .LBB[[BB1]]: 617; CHECK: fmr 5, 6 618; CHECK: .LBB[[BB2]]: 619; CHECK: fmr 1, 5 620; CHECK: blr 621} 622 623define float @testfloatugt(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 { 624entry: 625 %cmp1 = fcmp oeq float %c3, %c4 626 %cmp3tmp = fcmp oeq float %c1, %c2 627 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1 628 %cond = select i1 %cmp3, float %a1, float %a2 629 ret float %cond 630 631; CHECK-LABEL: @testfloatugt 632; CHECK: fcmpu {{[0-9]+}}, 3, 4 633; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]] 634; CHECK: fcmpu {{[0-9]+}}, 1, 2 635; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]] 636; CHECK: .LBB[[BB1]]: 637; CHECK: fmr 5, 6 638; CHECK: .LBB[[BB2]]: 639; CHECK: fmr 1, 5 640; CHECK: blr 641} 642 643define float @testfloatne(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 { 644entry: 645 %cmp1 = fcmp oeq float %c3, %c4 646 %cmp3tmp = fcmp oeq float %c1, %c2 647 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1 648 %cond = select i1 %cmp3, float %a1, float %a2 649 ret float %cond 650 651; CHECK-LABEL: @testfloatne 652; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 653; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 654; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 655; CHECK: bclr 12, [[REG1]], 0 656; CHECK: fmr 1, 6 657; CHECK: blr 658} 659 660define double @testdoubleslt(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 { 661entry: 662 %cmp1 = fcmp oeq double %c3, %c4 663 %cmp3tmp = fcmp oeq double %c1, %c2 664 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1 665 %cond = select i1 %cmp3, double %a1, double %a2 666 ret double %cond 667 668; CHECK-LABEL: @testdoubleslt 669; CHECK: fcmpu {{[0-9]+}}, 3, 4 670; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]] 671; CHECK: fcmpu {{[0-9]+}}, 1, 2 672; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]] 673; CHECK: .LBB[[BB1]]: 674; CHECK: fmr 5, 6 675; CHECK: .LBB[[BB2]]: 676; CHECK: fmr 1, 5 677; CHECK: blr 678} 679 680define double @testdoubleult(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 { 681entry: 682 %cmp1 = fcmp oeq double %c3, %c4 683 %cmp3tmp = fcmp oeq double %c1, %c2 684 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1 685 %cond = select i1 %cmp3, double %a1, double %a2 686 ret double %cond 687 688; CHECK-LABEL: @testdoubleult 689; CHECK: fcmpu {{[0-9]+}}, 3, 4 690; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]] 691; CHECK: fcmpu {{[0-9]+}}, 1, 2 692; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]] 693; CHECK: .LBB[[BB1]]: 694; CHECK: fmr 5, 6 695; CHECK: .LBB[[BB2]]: 696; CHECK: fmr 1, 5 697; CHECK: blr 698} 699 700define double @testdoublesle(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 { 701entry: 702 %cmp1 = fcmp oeq double %c3, %c4 703 %cmp3tmp = fcmp oeq double %c1, %c2 704 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1 705 %cond = select i1 %cmp3, double %a1, double %a2 706 ret double %cond 707 708; CHECK-LABEL: @testdoublesle 709; CHECK: fcmpu {{[0-9]+}}, 3, 4 710; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]] 711; CHECK: fcmpu {{[0-9]+}}, 1, 2 712; CHECK: bc 12, 2, .LBB[[BB]] 713; CHECK: fmr 5, 6 714; CHECK: .LBB[[BB]]: 715; CHECK: fmr 1, 5 716; CHECK: blr 717} 718 719define double @testdoubleule(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 { 720entry: 721 %cmp1 = fcmp oeq double %c3, %c4 722 %cmp3tmp = fcmp oeq double %c1, %c2 723 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1 724 %cond = select i1 %cmp3, double %a1, double %a2 725 ret double %cond 726 727; CHECK-LABEL: @testdoubleule 728; CHECK: fcmpu {{[0-9]+}}, 3, 4 729; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] 730; CHECK: fcmpu {{[0-9]+}}, 1, 2 731; CHECK: bc 4, 2, .LBB[[BB]] 732; CHECK: fmr 5, 6 733; CHECK: .LBB[[BB]]: 734; CHECK: fmr 1, 5 735; CHECK: blr 736} 737 738define double @testdoubleeq(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 { 739entry: 740 %cmp1 = fcmp oeq double %c3, %c4 741 %cmp3tmp = fcmp oeq double %c1, %c2 742 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1 743 %cond = select i1 %cmp3, double %a1, double %a2 744 ret double %cond 745 746; CHECK-LABEL: @testdoubleeq 747; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 748; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 749; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 750; CHECK: bclr 12, [[REG1]], 0 751; CHECK: fmr 1, 6 752; CHECK: blr 753} 754 755define double @testdoublesge(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 { 756entry: 757 %cmp1 = fcmp oeq double %c3, %c4 758 %cmp3tmp = fcmp oeq double %c1, %c2 759 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1 760 %cond = select i1 %cmp3, double %a1, double %a2 761 ret double %cond 762 763; CHECK-LABEL: @testdoublesge 764; CHECK: fcmpu {{[0-9]+}}, 3, 4 765; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] 766; CHECK: fcmpu {{[0-9]+}}, 1, 2 767; CHECK: bc 4, 2, .LBB[[BB]] 768; CHECK: fmr 5, 6 769; CHECK: .LBB[[BB]]: 770; CHECK: fmr 1, 5 771; CHECK: blr 772} 773 774define double @testdoubleuge(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 { 775entry: 776 %cmp1 = fcmp oeq double %c3, %c4 777 %cmp3tmp = fcmp oeq double %c1, %c2 778 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1 779 %cond = select i1 %cmp3, double %a1, double %a2 780 ret double %cond 781 782; CHECK-LABEL: @testdoubleuge 783; CHECK: fcmpu {{[0-9]+}}, 3, 4 784; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]] 785; CHECK: fcmpu {{[0-9]+}}, 1, 2 786; CHECK: bc 12, 2, .LBB[[BB]] 787; CHECK: fmr 5, 6 788; CHECK: .LBB[[BB]]: 789; CHECK: fmr 1, 5 790; CHECK: blr 791} 792 793define double @testdoublesgt(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 { 794entry: 795 %cmp1 = fcmp oeq double %c3, %c4 796 %cmp3tmp = fcmp oeq double %c1, %c2 797 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1 798 %cond = select i1 %cmp3, double %a1, double %a2 799 ret double %cond 800 801; CHECK-LABEL: @testdoublesgt 802; CHECK: fcmpu {{[0-9]+}}, 3, 4 803; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]] 804; CHECK: fcmpu {{[0-9]+}}, 1, 2 805; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]] 806; CHECK: .LBB[[BB1]]: 807; CHECK: fmr 5, 6 808; CHECK: .LBB[[BB2]]: 809; CHECK: fmr 1, 5 810; CHECK: blr 811} 812 813define double @testdoubleugt(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 { 814entry: 815 %cmp1 = fcmp oeq double %c3, %c4 816 %cmp3tmp = fcmp oeq double %c1, %c2 817 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1 818 %cond = select i1 %cmp3, double %a1, double %a2 819 ret double %cond 820 821; CHECK-LABEL: @testdoubleugt 822; CHECK: fcmpu {{[0-9]+}}, 3, 4 823; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]] 824; CHECK: fcmpu {{[0-9]+}}, 1, 2 825; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]] 826; CHECK: .LBB[[BB1]]: 827; CHECK: fmr 5, 6 828; CHECK: .LBB[[BB2]]: 829; CHECK: fmr 1, 5 830; CHECK: blr 831} 832 833define double @testdoublene(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 { 834entry: 835 %cmp1 = fcmp oeq double %c3, %c4 836 %cmp3tmp = fcmp oeq double %c1, %c2 837 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1 838 %cond = select i1 %cmp3, double %a1, double %a2 839 ret double %cond 840 841; CHECK-LABEL: @testdoublene 842; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 843; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 844; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 845; CHECK: bclr 12, [[REG1]], 0 846; CHECK: fmr 1, 6 847; CHECK: blr 848} 849 850define <4 x float> @testv4floatslt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 { 851entry: 852 %cmp1 = fcmp oeq float %c3, %c4 853 %cmp3tmp = fcmp oeq float %c1, %c2 854 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1 855 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 856 ret <4 x float> %cond 857 858; CHECK-LABEL: @testv4floatslt 859; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 860; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] 861; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 862; CHECK: bclr 12, 2, 0 863; CHECK: .LBB[[BB]]: 864; CHECK: vmr 2, 3 865; CHECK: blr 866} 867 868define <4 x float> @testv4floatult(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 { 869entry: 870 %cmp1 = fcmp oeq float %c3, %c4 871 %cmp3tmp = fcmp oeq float %c1, %c2 872 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1 873 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 874 ret <4 x float> %cond 875 876; CHECK-LABEL: @testv4floatult 877; CHECK: fcmpu {{[0-9]+}}, 3, 4 878; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]] 879; CHECK: fcmpu {{[0-9]+}}, 1, 2 880; CHECK: bclr 4, 2, 0 881; CHECK: .LBB[[BB]]: 882; CHECK: vmr 2, 3 883; CHECK: blr 884} 885 886define <4 x float> @testv4floatsle(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 { 887entry: 888 %cmp1 = fcmp oeq float %c3, %c4 889 %cmp3tmp = fcmp oeq float %c1, %c2 890 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1 891 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 892 ret <4 x float> %cond 893 894; CHECK-LABEL: @testv4floatsle 895; CHECK: fcmpu {{[0-9]+}}, 3, 4 896; CHECK: bclr 4, 2, 0 897; CHECK: fcmpu {{[0-9]+}}, 1, 2 898; CHECK: bclr 12, 2, 0 899; CHECK: vmr 2, 3 900; CHECK: blr 901} 902 903define <4 x float> @testv4floatule(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 { 904entry: 905 %cmp1 = fcmp oeq float %c3, %c4 906 %cmp3tmp = fcmp oeq float %c1, %c2 907 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1 908 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 909 ret <4 x float> %cond 910 911; CHECK-LABEL: @testv4floatule 912; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 913; CHECK: bclr 12, 2, 0 914; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 915; CHECK: bclr 4, 2, 0 916; CHECK: vmr 2, 3 917; CHECK: blr 918} 919 920define <4 x float> @testv4floateq(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 { 921entry: 922 %cmp1 = fcmp oeq float %c3, %c4 923 %cmp3tmp = fcmp oeq float %c1, %c2 924 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1 925 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 926 ret <4 x float> %cond 927 928; CHECK-LABEL: @testv4floateq 929; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 930; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 931; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 932; CHECK: bclr 12, [[REG1]], 0 933; CHECK: vmr 2, 3 934; CHECK: blr 935} 936 937define <4 x float> @testv4floatsge(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 { 938entry: 939 %cmp1 = fcmp oeq float %c3, %c4 940 %cmp3tmp = fcmp oeq float %c1, %c2 941 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1 942 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 943 ret <4 x float> %cond 944 945; CHECK-LABEL: @testv4floatsge 946; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 947; CHECK: bclr 12, 2, 0 948; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 949; CHECK: bclr 4, 2, 0 950; CHECK: vmr 2, 3 951; CHECK: blr 952} 953 954define <4 x float> @testv4floatuge(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 { 955entry: 956 %cmp1 = fcmp oeq float %c3, %c4 957 %cmp3tmp = fcmp oeq float %c1, %c2 958 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1 959 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 960 ret <4 x float> %cond 961 962; CHECK-LABEL: @testv4floatuge 963; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 964; CHECK: bclr 4, 2, 0 965; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 966; CHECK: bclr 12, 2, 0 967; CHECK: vmr 2, 3 968; CHECK: blr 969} 970 971define <4 x float> @testv4floatsgt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 { 972entry: 973 %cmp1 = fcmp oeq float %c3, %c4 974 %cmp3tmp = fcmp oeq float %c1, %c2 975 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1 976 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 977 ret <4 x float> %cond 978 979; CHECK-LABEL: @testv4floatsgt 980; CHECK: fcmpu {{[0-9]+}}, 3, 4 981; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]] 982; CHECK: fcmpu {{[0-9]+}}, 1, 2 983; CHECK: bclr 4, 2, 0 984; CHECK: vmr 2, 3 985; CHECK: blr 986} 987 988define <4 x float> @testv4floatugt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 { 989entry: 990 %cmp1 = fcmp oeq float %c3, %c4 991 %cmp3tmp = fcmp oeq float %c1, %c2 992 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1 993 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 994 ret <4 x float> %cond 995 996; CHECK-LABEL: @testv4floatugt 997; CHECK: fcmpu {{[0-9]+}}, 3, 4 998; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] 999; CHECK: fcmpu {{[0-9]+}}, 1, 2 1000; CHECK: bclr 12, 2, 0 1001; CHECK: .LBB[[BB]] 1002; CHECK: vmr 2, 3 1003; CHECK: blr 1004} 1005 1006define <4 x float> @testv4floatne(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 { 1007entry: 1008 %cmp1 = fcmp oeq float %c3, %c4 1009 %cmp3tmp = fcmp oeq float %c1, %c2 1010 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1 1011 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 1012 ret <4 x float> %cond 1013 1014; CHECK-LABEL: @testv4floatne 1015; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1016; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1017; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1018; CHECK: bclr 12, [[REG1]], 0 1019; CHECK: vmr 2, 3 1020; CHECK: blr 1021} 1022 1023define ppc_fp128 @testppc_fp128eq(ppc_fp128 %c1, ppc_fp128 %c2, ppc_fp128 %c3, ppc_fp128 %c4, ppc_fp128 %a1, ppc_fp128 %a2) #0 { 1024entry: 1025 %cmp1 = fcmp oeq ppc_fp128 %c3, %c4 1026 %cmp3tmp = fcmp oeq ppc_fp128 %c1, %c2 1027 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1 1028 %cond = select i1 %cmp3, ppc_fp128 %a1, ppc_fp128 %a2 1029 ret ppc_fp128 %cond 1030 1031; FIXME: Because of the way that the late SELECT_* pseudo-instruction expansion 1032; works, we end up with two blocks with the same predicate. These could be 1033; combined. 1034 1035; CHECK-LABEL: @testppc_fp128eq 1036; CHECK-DAG: fcmpu {{[0-9]+}}, 6, 8 1037; CHECK-DAG: fcmpu {{[0-9]+}}, 5, 7 1038; CHECK-DAG: fcmpu {{[0-9]+}}, 2, 4 1039; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 3 1040; CHECK: crand [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1041; CHECK: crand [[REG2:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1042; CHECK: crxor [[REG3:[0-9]+]], [[REG2]], [[REG1]] 1043; CHECK: bc 12, [[REG3]], .LBB[[BB1:[0-9_]+]] 1044; CHECK: fmr 11, 9 1045; CHECK: .LBB[[BB1]]: 1046; CHECK: bc 12, [[REG3]], .LBB[[BB2:[0-9_]+]] 1047; CHECK: fmr 12, 10 1048; CHECK: .LBB[[BB2]]: 1049; CHECK-DAG: fmr 1, 11 1050; CHECK-DAG: fmr 2, 12 1051; CHECK: blr 1052} 1053 1054define <2 x double> @testv2doubleslt(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 { 1055entry: 1056 %cmp1 = fcmp oeq float %c3, %c4 1057 %cmp3tmp = fcmp oeq float %c1, %c2 1058 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1 1059 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2 1060 ret <2 x double> %cond 1061 1062; CHECK-LABEL: @testv2doubleslt 1063; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1064; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] 1065; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1066; CHECK: bclr 12, 2, 0 1067; CHECK: .LBB[[BB]]: 1068; CHECK: vmr 2, 3 1069; CHECK: blr 1070} 1071 1072define <2 x double> @testv2doubleult(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 { 1073entry: 1074 %cmp1 = fcmp oeq float %c3, %c4 1075 %cmp3tmp = fcmp oeq float %c1, %c2 1076 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1 1077 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2 1078 ret <2 x double> %cond 1079 1080; CHECK-LABEL: @testv2doubleult 1081; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1082; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]] 1083; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1084; CHECK: bclr 4, 2, 0 1085; CHECK: .LBB[[BB]]: 1086; CHECK: vmr 2, 3 1087; CHECK: blr 1088} 1089 1090define <2 x double> @testv2doublesle(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 { 1091entry: 1092 %cmp1 = fcmp oeq float %c3, %c4 1093 %cmp3tmp = fcmp oeq float %c1, %c2 1094 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1 1095 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2 1096 ret <2 x double> %cond 1097 1098; CHECK-LABEL: @testv2doublesle 1099; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1100; CHECK: bclr 4, 2, 0 1101; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1102; CHECK: bclr 12, 2, 0 1103; CHECK: vmr 2, 3 1104; CHECK: blr 1105} 1106 1107define <2 x double> @testv2doubleule(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 { 1108entry: 1109 %cmp1 = fcmp oeq float %c3, %c4 1110 %cmp3tmp = fcmp oeq float %c1, %c2 1111 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1 1112 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2 1113 ret <2 x double> %cond 1114 1115; CHECK-LABEL: @testv2doubleule 1116; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1117; CHECK: bclr 12, 2, 0 1118; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1119; CHECK: bclr 4, 2, 0 1120; CHECK: vmr 2, 3 1121; CHECK: blr 1122} 1123 1124define <2 x double> @testv2doubleeq(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 { 1125entry: 1126 %cmp1 = fcmp oeq float %c3, %c4 1127 %cmp3tmp = fcmp oeq float %c1, %c2 1128 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1 1129 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2 1130 ret <2 x double> %cond 1131 1132; CHECK-LABEL: @testv2doubleeq 1133; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1134; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1135; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1136; CHECK: bclr 12, [[REG1]], 0 1137; CHECK: vmr 2, 3 1138; CHECK: blr 1139} 1140 1141define <2 x double> @testv2doublesge(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 { 1142entry: 1143 %cmp1 = fcmp oeq float %c3, %c4 1144 %cmp3tmp = fcmp oeq float %c1, %c2 1145 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1 1146 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2 1147 ret <2 x double> %cond 1148 1149; CHECK-LABEL: @testv2doublesge 1150; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1151; CHECK: bclr 12, 2, 0 1152; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1153; CHECK: bclr 4, 2, 0 1154; CHECK: vmr 2, 3 1155; CHECK: blr 1156} 1157 1158define <2 x double> @testv2doubleuge(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 { 1159entry: 1160 %cmp1 = fcmp oeq float %c3, %c4 1161 %cmp3tmp = fcmp oeq float %c1, %c2 1162 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1 1163 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2 1164 ret <2 x double> %cond 1165 1166; CHECK-LABEL: @testv2doubleuge 1167; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1168; CHECK: bclr 4, 2, 0 1169; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1170; CHECK: bclr 12, 2, 0 1171; CHECK: vmr 2, 3 1172; CHECK: blr 1173} 1174 1175define <2 x double> @testv2doublesgt(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 { 1176entry: 1177 %cmp1 = fcmp oeq float %c3, %c4 1178 %cmp3tmp = fcmp oeq float %c1, %c2 1179 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1 1180 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2 1181 ret <2 x double> %cond 1182 1183; CHECK-LABEL: @testv2doublesgt 1184; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1185; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]] 1186; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1187; CHECK: bclr 4, 2, 0 1188; CHECK: .LBB[[BB]] 1189; CHECK: vmr 2, 3 1190; CHECK: blr 1191} 1192 1193define <2 x double> @testv2doubleugt(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 { 1194entry: 1195 %cmp1 = fcmp oeq float %c3, %c4 1196 %cmp3tmp = fcmp oeq float %c1, %c2 1197 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1 1198 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2 1199 ret <2 x double> %cond 1200 1201; CHECK-LABEL: @testv2doubleugt 1202; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1203; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] 1204; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1205; CHECK: bclr 12, 2, 0 1206; CHECK: .LBB[[BB]] 1207; CHECK: vmr 2, 3 1208; CHECK: blr 1209} 1210 1211define <2 x double> @testv2doublene(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 { 1212entry: 1213 %cmp1 = fcmp oeq float %c3, %c4 1214 %cmp3tmp = fcmp oeq float %c1, %c2 1215 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1 1216 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2 1217 ret <2 x double> %cond 1218 1219; CHECK-LABEL: @testv2doublene 1220; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1221; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1222; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1223; CHECK: bclr 12, [[REG1]], 0 1224; CHECK: vmr 2, 3 1225; CHECK: blr 1226} 1227 1228define <4 x double> @testqv4doubleslt(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 { 1229entry: 1230 %cmp1 = fcmp oeq float %c3, %c4 1231 %cmp3tmp = fcmp oeq float %c1, %c2 1232 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1 1233 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2 1234 ret <4 x double> %cond 1235 1236; CHECK-LABEL: @testqv4doubleslt 1237; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1238; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]] 1239; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1240; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]] 1241; CHECK: .LBB[[BB1]]: 1242; CHECK: qvfmr 5, 6 1243; CHECK: .LBB[[BB2]]: 1244; CHECK: qvfmr 1, 5 1245; CHECK: blr 1246} 1247 1248define <4 x double> @testqv4doubleult(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 { 1249entry: 1250 %cmp1 = fcmp oeq float %c3, %c4 1251 %cmp3tmp = fcmp oeq float %c1, %c2 1252 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1 1253 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2 1254 ret <4 x double> %cond 1255 1256; CHECK-LABEL: @testqv4doubleult 1257; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1258; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]] 1259; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1260; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]] 1261; CHECK: .LBB[[BB1]]: 1262; CHECK: qvfmr 5, 6 1263; CHECK: .LBB[[BB2]]: 1264; CHECK: qvfmr 1, 5 1265; CHECK: blr 1266} 1267 1268define <4 x double> @testqv4doublesle(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 { 1269entry: 1270 %cmp1 = fcmp oeq float %c3, %c4 1271 %cmp3tmp = fcmp oeq float %c1, %c2 1272 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1 1273 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2 1274 ret <4 x double> %cond 1275 1276; CHECK-LABEL: @testqv4doublesle 1277; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1278; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]] 1279; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1280; CHECK: bc 12, 2, .LBB[[BB]] 1281; CHECK: qvfmr 5, 6 1282; CHECK: .LBB[[BB]]: 1283; CHECK: qvfmr 1, 5 1284; CHECK: blr 1285} 1286 1287define <4 x double> @testqv4doubleule(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 { 1288entry: 1289 %cmp1 = fcmp oeq float %c3, %c4 1290 %cmp3tmp = fcmp oeq float %c1, %c2 1291 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1 1292 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2 1293 ret <4 x double> %cond 1294 1295; CHECK-LABEL: @testqv4doubleule 1296; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1297; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] 1298; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1299; CHECK: bc 4, 2, .LBB[[BB]] 1300; CHECK: qvfmr 5, 6 1301; CHECK: .LBB[[BB]]: 1302; CHECK: qvfmr 1, 5 1303; CHECK: blr 1304} 1305 1306define <4 x double> @testqv4doubleeq(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 { 1307entry: 1308 %cmp1 = fcmp oeq float %c3, %c4 1309 %cmp3tmp = fcmp oeq float %c1, %c2 1310 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1 1311 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2 1312 ret <4 x double> %cond 1313 1314; CHECK-LABEL: @testqv4doubleeq 1315; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1316; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1317; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1318; CHECK: bclr 12, [[REG1]], 0 1319; CHECK: qvfmr 1, 6 1320; CHECK: blr 1321} 1322 1323define <4 x double> @testqv4doublesge(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 { 1324entry: 1325 %cmp1 = fcmp oeq float %c3, %c4 1326 %cmp3tmp = fcmp oeq float %c1, %c2 1327 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1 1328 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2 1329 ret <4 x double> %cond 1330 1331; CHECK-LABEL: @testqv4doublesge 1332; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1333; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] 1334; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1335; CHECK: bc 4, 2, .LBB[[BB]] 1336; CHECK: qvfmr 5, 6 1337; CHECK: .LBB[[BB]]: 1338; CHECK: qvfmr 1, 5 1339; CHECK: blr 1340} 1341 1342define <4 x double> @testqv4doubleuge(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 { 1343entry: 1344 %cmp1 = fcmp oeq float %c3, %c4 1345 %cmp3tmp = fcmp oeq float %c1, %c2 1346 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1 1347 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2 1348 ret <4 x double> %cond 1349 1350; CHECK-LABEL: @testqv4doubleuge 1351; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1352; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]] 1353; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1354; CHECK: bc 12, 2, .LBB[[BB]] 1355; CHECK: qvfmr 5, 6 1356; CHECK: .LBB[[BB]]: 1357; CHECK: qvfmr 1, 5 1358; CHECK: blr 1359} 1360 1361define <4 x double> @testqv4doublesgt(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 { 1362entry: 1363 %cmp1 = fcmp oeq float %c3, %c4 1364 %cmp3tmp = fcmp oeq float %c1, %c2 1365 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1 1366 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2 1367 ret <4 x double> %cond 1368 1369; CHECK-LABEL: @testqv4doublesgt 1370; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1371; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]] 1372; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1373; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]] 1374; CHECK: .LBB[[BB1]]: 1375; CHECK: qvfmr 5, 6 1376; CHECK: .LBB[[BB2]]: 1377; CHECK: qvfmr 1, 5 1378; CHECK: blr 1379} 1380 1381define <4 x double> @testqv4doubleugt(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 { 1382entry: 1383 %cmp1 = fcmp oeq float %c3, %c4 1384 %cmp3tmp = fcmp oeq float %c1, %c2 1385 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1 1386 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2 1387 ret <4 x double> %cond 1388 1389; CHECK-LABEL: @testqv4doubleugt 1390; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1391; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]] 1392; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1393; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]] 1394; CHECK: .LBB[[BB1]]: 1395; CHECK: qvfmr 5, 6 1396; CHECK: .LBB[[BB2]]: 1397; CHECK: qvfmr 1, 5 1398; CHECK: blr 1399} 1400 1401define <4 x double> @testqv4doublene(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 { 1402entry: 1403 %cmp1 = fcmp oeq float %c3, %c4 1404 %cmp3tmp = fcmp oeq float %c1, %c2 1405 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1 1406 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2 1407 ret <4 x double> %cond 1408 1409; CHECK-LABEL: @testqv4doublene 1410; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1411; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1412; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1413; CHECK: bclr 12, [[REG1]], 0 1414; CHECK: qvfmr 1, 6 1415; CHECK: blr 1416} 1417 1418define <4 x float> @testqv4floatslt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 { 1419entry: 1420 %cmp1 = fcmp oeq float %c3, %c4 1421 %cmp3tmp = fcmp oeq float %c1, %c2 1422 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1 1423 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 1424 ret <4 x float> %cond 1425 1426; CHECK-LABEL: @testqv4floatslt 1427; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1428; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]] 1429; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1430; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]] 1431; CHECK: .LBB[[BB1]]: 1432; CHECK: qvfmr 5, 6 1433; CHECK: .LBB[[BB2]]: 1434; CHECK: qvfmr 1, 5 1435; CHECK: blr 1436} 1437 1438define <4 x float> @testqv4floatult(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 { 1439entry: 1440 %cmp1 = fcmp oeq float %c3, %c4 1441 %cmp3tmp = fcmp oeq float %c1, %c2 1442 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1 1443 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 1444 ret <4 x float> %cond 1445 1446; CHECK-LABEL: @testqv4floatult 1447; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1448; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]] 1449; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1450; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]] 1451; CHECK: .LBB[[BB1]]: 1452; CHECK: qvfmr 5, 6 1453; CHECK: .LBB[[BB2]]: 1454; CHECK: qvfmr 1, 5 1455; CHECK: blr 1456} 1457 1458define <4 x float> @testqv4floatsle(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 { 1459entry: 1460 %cmp1 = fcmp oeq float %c3, %c4 1461 %cmp3tmp = fcmp oeq float %c1, %c2 1462 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1 1463 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 1464 ret <4 x float> %cond 1465 1466; CHECK-LABEL: @testqv4floatsle 1467; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1468; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]] 1469; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1470; CHECK: bc 12, 2, .LBB[[BB]] 1471; CHECK: qvfmr 5, 6 1472; CHECK: .LBB[[BB]]: 1473; CHECK: qvfmr 1, 5 1474; CHECK: blr 1475} 1476 1477define <4 x float> @testqv4floatule(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 { 1478entry: 1479 %cmp1 = fcmp oeq float %c3, %c4 1480 %cmp3tmp = fcmp oeq float %c1, %c2 1481 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1 1482 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 1483 ret <4 x float> %cond 1484 1485; CHECK-LABEL: @testqv4floatule 1486; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1487; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] 1488; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1489; CHECK: bc 4, 2, .LBB[[BB]] 1490; CHECK: qvfmr 5, 6 1491; CHECK: .LBB[[BB]]: 1492; CHECK: qvfmr 1, 5 1493; CHECK: blr 1494} 1495 1496define <4 x float> @testqv4floateq(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 { 1497entry: 1498 %cmp1 = fcmp oeq float %c3, %c4 1499 %cmp3tmp = fcmp oeq float %c1, %c2 1500 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1 1501 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 1502 ret <4 x float> %cond 1503 1504; CHECK-LABEL: @testqv4floateq 1505; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1506; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1507; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1508; CHECK: bclr 12, [[REG1]], 0 1509; CHECK: qvfmr 1, 6 1510; CHECK: blr 1511} 1512 1513define <4 x float> @testqv4floatsge(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 { 1514entry: 1515 %cmp1 = fcmp oeq float %c3, %c4 1516 %cmp3tmp = fcmp oeq float %c1, %c2 1517 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1 1518 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 1519 ret <4 x float> %cond 1520 1521; CHECK-LABEL: @testqv4floatsge 1522; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1523; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] 1524; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1525; CHECK: bc 4, 2, .LBB[[BB]] 1526; CHECK: qvfmr 5, 6 1527; CHECK: .LBB[[BB]]: 1528; CHECK: qvfmr 1, 5 1529; CHECK: blr 1530} 1531 1532define <4 x float> @testqv4floatuge(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 { 1533entry: 1534 %cmp1 = fcmp oeq float %c3, %c4 1535 %cmp3tmp = fcmp oeq float %c1, %c2 1536 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1 1537 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 1538 ret <4 x float> %cond 1539 1540; CHECK-LABEL: @testqv4floatuge 1541; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1542; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]] 1543; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1544; CHECK: bc 12, 2, .LBB[[BB]] 1545; CHECK: qvfmr 5, 6 1546; CHECK: .LBB[[BB]]: 1547; CHECK: qvfmr 1, 5 1548; CHECK: blr 1549} 1550 1551define <4 x float> @testqv4floatsgt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 { 1552entry: 1553 %cmp1 = fcmp oeq float %c3, %c4 1554 %cmp3tmp = fcmp oeq float %c1, %c2 1555 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1 1556 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 1557 ret <4 x float> %cond 1558 1559; CHECK-LABEL: @testqv4floatsgt 1560; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1561; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]] 1562; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1563; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]] 1564; CHECK: .LBB[[BB1]]: 1565; CHECK: qvfmr 5, 6 1566; CHECK: .LBB[[BB2]]: 1567; CHECK: qvfmr 1, 5 1568; CHECK: blr 1569} 1570 1571define <4 x float> @testqv4floatugt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 { 1572entry: 1573 %cmp1 = fcmp oeq float %c3, %c4 1574 %cmp3tmp = fcmp oeq float %c1, %c2 1575 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1 1576 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 1577 ret <4 x float> %cond 1578 1579; CHECK-LABEL: @testqv4floatugt 1580; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1581; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]] 1582; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1583; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]] 1584; CHECK: .LBB[[BB1]]: 1585; CHECK: qvfmr 5, 6 1586; CHECK: .LBB[[BB2]]: 1587; CHECK: qvfmr 1, 5 1588; CHECK: blr 1589} 1590 1591define <4 x float> @testqv4floatne(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 { 1592entry: 1593 %cmp1 = fcmp oeq float %c3, %c4 1594 %cmp3tmp = fcmp oeq float %c1, %c2 1595 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1 1596 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 1597 ret <4 x float> %cond 1598 1599; CHECK-LABEL: @testqv4floatne 1600; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1601; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1602; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1603; CHECK: bclr 12, [[REG1]], 0 1604; CHECK: qvfmr 1, 6 1605; CHECK: blr 1606} 1607 1608define <4 x i1> @testqv4i1slt(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 { 1609entry: 1610 %cmp1 = fcmp oeq float %c3, %c4 1611 %cmp3tmp = fcmp oeq float %c1, %c2 1612 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1 1613 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2 1614 ret <4 x i1> %cond 1615 1616; CHECK-LABEL: @testqv4i1slt 1617; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1618; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]] 1619; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1620; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]] 1621; CHECK: .LBB[[BB1]]: 1622; CHECK: qvfmr 5, 6 1623; CHECK: .LBB[[BB2]]: 1624; CHECK: qvfmr 1, 5 1625; CHECK: blr 1626} 1627 1628define <4 x i1> @testqv4i1ult(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 { 1629entry: 1630 %cmp1 = fcmp oeq float %c3, %c4 1631 %cmp3tmp = fcmp oeq float %c1, %c2 1632 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1 1633 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2 1634 ret <4 x i1> %cond 1635 1636; CHECK-LABEL: @testqv4i1ult 1637; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1638; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]] 1639; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1640; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]] 1641; CHECK: .LBB[[BB1]]: 1642; CHECK: qvfmr 5, 6 1643; CHECK: .LBB[[BB2]]: 1644; CHECK: qvfmr 1, 5 1645; CHECK: blr 1646} 1647 1648define <4 x i1> @testqv4i1sle(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 { 1649entry: 1650 %cmp1 = fcmp oeq float %c3, %c4 1651 %cmp3tmp = fcmp oeq float %c1, %c2 1652 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1 1653 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2 1654 ret <4 x i1> %cond 1655 1656; CHECK-LABEL: @testqv4i1sle 1657; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1658; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]] 1659; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1660; CHECK: bc 12, 2, .LBB[[BB]] 1661; CHECK: qvfmr 5, 6 1662; CHECK: .LBB[[BB]]: 1663; CHECK: qvfmr 1, 5 1664; CHECK: blr 1665} 1666 1667define <4 x i1> @testqv4i1ule(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 { 1668entry: 1669 %cmp1 = fcmp oeq float %c3, %c4 1670 %cmp3tmp = fcmp oeq float %c1, %c2 1671 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1 1672 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2 1673 ret <4 x i1> %cond 1674 1675; CHECK-LABEL: @testqv4i1ule 1676; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1677; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] 1678; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1679; CHECK: bc 4, 2, .LBB[[BB]] 1680; CHECK: qvfmr 5, 6 1681; CHECK: .LBB[[BB]]: 1682; CHECK: qvfmr 1, 5 1683; CHECK: blr 1684} 1685 1686define <4 x i1> @testqv4i1eq(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 { 1687entry: 1688 %cmp1 = fcmp oeq float %c3, %c4 1689 %cmp3tmp = fcmp oeq float %c1, %c2 1690 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1 1691 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2 1692 ret <4 x i1> %cond 1693 1694; CHECK-LABEL: @testqv4i1eq 1695; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1696; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1697; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1698; CHECK: bclr 12, [[REG1]], 0 1699; CHECK: qvfmr 1, 6 1700; CHECK: blr 1701} 1702 1703define <4 x i1> @testqv4i1sge(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 { 1704entry: 1705 %cmp1 = fcmp oeq float %c3, %c4 1706 %cmp3tmp = fcmp oeq float %c1, %c2 1707 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1 1708 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2 1709 ret <4 x i1> %cond 1710 1711; CHECK-LABEL: @testqv4i1sge 1712; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1713; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] 1714; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1715; CHECK: bc 4, 2, .LBB[[BB]] 1716; CHECK: qvfmr 5, 6 1717; CHECK: .LBB[[BB]]: 1718; CHECK: qvfmr 1, 5 1719; CHECK: blr 1720} 1721 1722define <4 x i1> @testqv4i1uge(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 { 1723entry: 1724 %cmp1 = fcmp oeq float %c3, %c4 1725 %cmp3tmp = fcmp oeq float %c1, %c2 1726 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1 1727 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2 1728 ret <4 x i1> %cond 1729 1730; CHECK-LABEL: @testqv4i1uge 1731; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1732; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]] 1733; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1734; CHECK: bc 12, 2, .LBB[[BB]] 1735; CHECK: qvfmr 5, 6 1736; CHECK: .LBB[[BB]]: 1737; CHECK: qvfmr 1, 5 1738; CHECK: blr 1739} 1740 1741define <4 x i1> @testqv4i1sgt(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 { 1742entry: 1743 %cmp1 = fcmp oeq float %c3, %c4 1744 %cmp3tmp = fcmp oeq float %c1, %c2 1745 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1 1746 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2 1747 ret <4 x i1> %cond 1748 1749; CHECK-LABEL: @testqv4i1sgt 1750; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1751; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]] 1752; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1753; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]] 1754; CHECK: .LBB[[BB1]]: 1755; CHECK: qvfmr 5, 6 1756; CHECK: .LBB[[BB2]]: 1757; CHECK: qvfmr 1, 5 1758; CHECK: blr 1759} 1760 1761define <4 x i1> @testqv4i1ugt(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 { 1762entry: 1763 %cmp1 = fcmp oeq float %c3, %c4 1764 %cmp3tmp = fcmp oeq float %c1, %c2 1765 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1 1766 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2 1767 ret <4 x i1> %cond 1768 1769; CHECK-LABEL: @testqv4i1ugt 1770; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1771; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]] 1772; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1773; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]] 1774; CHECK: .LBB[[BB1]]: 1775; CHECK: qvfmr 5, 6 1776; CHECK: .LBB[[BB2]]: 1777; CHECK: qvfmr 1, 5 1778; CHECK: blr 1779} 1780 1781define <4 x i1> @testqv4i1ne(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 { 1782entry: 1783 %cmp1 = fcmp oeq float %c3, %c4 1784 %cmp3tmp = fcmp oeq float %c1, %c2 1785 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1 1786 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2 1787 ret <4 x i1> %cond 1788 1789; CHECK-LABEL: @testqv4i1ne 1790; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1791; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1792; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1793; CHECK: bclr 12, [[REG1]], 0 1794; CHECK: qvfmr 1, 6 1795; CHECK: blr 1796} 1797 1798attributes #0 = { nounwind readnone "target-cpu"="pwr7" } 1799attributes #1 = { nounwind readnone "target-cpu"="a2q" } 1800 1801