1; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr8 -ppc-vsr-nums-as-vr \ 2; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu \ 3; RUN: -O3 < %s | FileCheck %s 4 5; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \ 6; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \ 7; RUN: < %s | FileCheck %s --check-prefix=CHECK-P9 \ 8; RUN: --implicit-check-not xxswapd 9 10; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \ 11; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \ 12; RUN: -mattr=-power9-vector < %s | FileCheck %s --check-prefix=CHECK-P9-NOVECTOR 13 14; These tests verify that VSX swap optimization works when loading a scalar 15; into a vector register. 16 17 18@x = global <2 x double> <double 9.970000e+01, double -1.032220e+02>, align 16 19@z = global <2 x double> <double 2.332000e+01, double 3.111111e+01>, align 16 20@y = global double 1.780000e+00, align 8 21 22define void @bar0() { 23; CHECK-LABEL: bar0: 24; CHECK: # %bb.0: # %entry 25; CHECK: addis r3, r2, .LC0@toc@ha 26; CHECK: addis r4, r2, .LC1@toc@ha 27; CHECK: ld r3, .LC0@toc@l(r3) 28; CHECK: addis r3, r2, .LC2@toc@ha 29; CHECK: ld r3, .LC2@toc@l(r3) 30; CHECK: xxpermdi vs0, vs0, vs1, 1 31; CHECK: stxvd2x vs0, 0, r3 32; CHECK: blr 33; 34; CHECK-P9-NOVECTOR-LABEL: bar0: 35; CHECK-P9-NOVECTOR: # %bb.0: # %entry 36; CHECK-P9-NOVECTOR: addis r3, r2, .LC0@toc@ha 37; CHECK-P9-NOVECTOR: ld r3, .LC0@toc@l(r3) 38; CHECK-P9-NOVECTOR: addis r3, r2, .LC1@toc@ha 39; CHECK-P9-NOVECTOR: addis r3, r2, .LC2@toc@ha 40; CHECK-P9-NOVECTOR: ld r3, .LC2@toc@l(r3) 41; CHECK-P9-NOVECTOR: xxpermdi vs0, vs1, vs0, 1 42; CHECK-P9-NOVECTOR: stxvd2x vs0, 0, r3 43; CHECK-P9-NOVECTOR: blr 44; 45; CHECK-P9-LABEL: bar0: 46; CHECK-P9: # %bb.0: # %entry 47; CHECK-P9: addis r3, r2, .LC0@toc@ha 48; CHECK-P9: ld r3, .LC0@toc@l(r3) 49; CHECK-P9: lxvx vs0, 0, r3 50; CHECK-P9: addis r3, r2, .LC1@toc@ha 51; CHECK-P9: ld r3, .LC1@toc@l(r3) 52; CHECK-P9: lfd f1, 0(r3) 53; CHECK-P9: addis r3, r2, .LC2@toc@ha 54; CHECK-P9: ld r3, .LC2@toc@l(r3) 55; CHECK-P9: xxpermdi vs1, f1, f1, 2 56; CHECK-P9: xxpermdi vs0, vs0, vs1, 1 57; CHECK-P9: stxvx vs0, 0, r3 58; CHECK-P9: blr 59entry: 60 %0 = load <2 x double>, <2 x double>* @x, align 16 61 %1 = load double, double* @y, align 8 62 %vecins = insertelement <2 x double> %0, double %1, i32 0 63 store <2 x double> %vecins, <2 x double>* @z, align 16 64 ret void 65} 66 67define void @bar1() { 68; CHECK-LABEL: bar1: 69; CHECK: # %bb.0: # %entry 70; CHECK: addis r3, r2, .LC0@toc@ha 71; CHECK: addis r4, r2, .LC1@toc@ha 72; CHECK: ld r3, .LC0@toc@l(r3) 73; CHECK: addis r3, r2, .LC2@toc@ha 74; CHECK: ld r3, .LC2@toc@l(r3) 75; CHECK: xxmrghd vs0, vs1, vs0 76; CHECK: stxvd2x vs0, 0, r3 77; CHECK: blr 78; 79; CHECK-P9-NOVECTOR-LABEL: bar1: 80; CHECK-P9-NOVECTOR: # %bb.0: # %entry 81; CHECK-P9-NOVECTOR: addis r3, r2, .LC0@toc@ha 82; CHECK-P9-NOVECTOR: ld r3, .LC0@toc@l(r3) 83; CHECK-P9-NOVECTOR: addis r3, r2, .LC1@toc@ha 84; CHECK-P9-NOVECTOR: addis r3, r2, .LC2@toc@ha 85; CHECK-P9-NOVECTOR: ld r3, .LC2@toc@l(r3) 86; CHECK-P9-NOVECTOR: xxmrghd vs0, vs0, vs1 87; CHECK-P9-NOVECTOR: stxvd2x vs0, 0, r3 88; CHECK-P9-NOVECTOR: blr 89; 90; CHECK-P9-LABEL: bar1: 91; CHECK-P9: # %bb.0: # %entry 92; CHECK-P9: addis r3, r2, .LC0@toc@ha 93; CHECK-P9: ld r3, .LC0@toc@l(r3) 94; CHECK-P9: lxvx vs0, 0, r3 95; CHECK-P9: addis r3, r2, .LC1@toc@ha 96; CHECK-P9: ld r3, .LC1@toc@l(r3) 97; CHECK-P9: lfd f1, 0(r3) 98; CHECK-P9: addis r3, r2, .LC2@toc@ha 99; CHECK-P9: ld r3, .LC2@toc@l(r3) 100; CHECK-P9: xxpermdi vs1, f1, f1, 2 101; CHECK-P9: xxmrgld vs0, vs1, vs0 102; CHECK-P9: stxvx vs0, 0, r3 103; CHECK-P9: blr 104entry: 105 %0 = load <2 x double>, <2 x double>* @x, align 16 106 %1 = load double, double* @y, align 8 107 %vecins = insertelement <2 x double> %0, double %1, i32 1 108 store <2 x double> %vecins, <2 x double>* @z, align 16 109 ret void 110} 111 112