1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ 3; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \ 4; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl 5; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ 6; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \ 7; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl 8@glob = local_unnamed_addr global i32 0, align 4 9 10define signext i32 @test_ilesi(i32 signext %a, i32 signext %b) { 11; CHECK-LABEL: test_ilesi: 12; CHECK: # %bb.0: # %entry 13; CHECK-NEXT: sub r3, r4, r3 14; CHECK-NEXT: rldicl r3, r3, 1, 63 15; CHECK-NEXT: xori r3, r3, 1 16; CHECK-NEXT: blr 17; CHECK-BE-LABEL: test_ilesi: 18; CHECK-BE: # %bb.0: # %entry 19; CHECK-BE-NEXT: sub r3, r4, r3 20; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 21; CHECK-BE-NEXT: xori r3, r3, 1 22; CHECK-BE-NEXT: blr 23; 24; CHECK-LE-LABEL: test_ilesi: 25; CHECK-LE: # %bb.0: # %entry 26; CHECK-LE-NEXT: sub r3, r4, r3 27; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 28; CHECK-LE-NEXT: xori r3, r3, 1 29; CHECK-LE-NEXT: blr 30entry: 31 %cmp = icmp sle i32 %a, %b 32 %conv = zext i1 %cmp to i32 33 ret i32 %conv 34} 35 36define signext i32 @test_ilesi_sext(i32 signext %a, i32 signext %b) { 37; CHECK-LABEL: test_ilesi_sext: 38; CHECK: # %bb.0: # %entry 39; CHECK-NEXT: sub r3, r4, r3 40; CHECK-NEXT: rldicl r3, r3, 1, 63 41; CHECK-NEXT: addi r3, r3, -1 42; CHECK-NEXT: blr 43; CHECK-BE-LABEL: test_ilesi_sext: 44; CHECK-BE: # %bb.0: # %entry 45; CHECK-BE-NEXT: sub r3, r4, r3 46; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 47; CHECK-BE-NEXT: addi r3, r3, -1 48; CHECK-BE-NEXT: blr 49; 50; CHECK-LE-LABEL: test_ilesi_sext: 51; CHECK-LE: # %bb.0: # %entry 52; CHECK-LE-NEXT: sub r3, r4, r3 53; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 54; CHECK-LE-NEXT: addi r3, r3, -1 55; CHECK-LE-NEXT: blr 56entry: 57 %cmp = icmp sle i32 %a, %b 58 %sub = sext i1 %cmp to i32 59 ret i32 %sub 60} 61 62define void @test_ilesi_store(i32 signext %a, i32 signext %b) { 63; CHECK-LABEL: test_ilesi_store: 64; CHECK: # %bb.0: # %entry 65; CHECK-NEXT: sub r3, r4, r3 66; CHECK-NEXT: addis r5, r2, glob@toc@ha 67; CHECK-NEXT: rldicl r3, r3, 1, 63 68; CHECK-NEXT: xori r3, r3, 1 69; CHECK-NEXT: stw r3, glob@toc@l(r5) 70; CHECK-NEXT: blr 71; CHECK-BE-LABEL: test_ilesi_store: 72; CHECK-BE: # %bb.0: # %entry 73; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha 74; CHECK-BE-NEXT: sub r3, r4, r3 75; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) 76; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 77; CHECK-BE-NEXT: xori r3, r3, 1 78; CHECK-BE-NEXT: stw r3, 0(r4) 79; CHECK-BE-NEXT: blr 80; 81; CHECK-LE-LABEL: test_ilesi_store: 82; CHECK-LE: # %bb.0: # %entry 83; CHECK-LE-NEXT: sub r3, r4, r3 84; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha 85; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 86; CHECK-LE-NEXT: xori r3, r3, 1 87; CHECK-LE-NEXT: stw r3, glob@toc@l(r5) 88; CHECK-LE-NEXT: blr 89entry: 90 %cmp = icmp sle i32 %a, %b 91 %conv = zext i1 %cmp to i32 92 store i32 %conv, i32* @glob, align 4 93 ret void 94} 95 96define void @test_ilesi_sext_store(i32 signext %a, i32 signext %b) { 97; CHECK-LABEL: test_ilesi_sext_store: 98; CHECK: # %bb.0: # %entry 99; CHECK-NEXT: sub r3, r4, r3 100; CHECK-NEXT: addis r5, r2, glob@toc@ha 101; CHECK-NEXT: rldicl r3, r3, 1, 63 102; CHECK-NEXT: addi r3, r3, -1 103; CHECK-NEXT: stw r3, glob@toc@l(r5) 104; CHECK-NEXT: blr 105; CHECK-BE-LABEL: test_ilesi_sext_store: 106; CHECK-BE: # %bb.0: # %entry 107; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha 108; CHECK-BE-NEXT: sub r3, r4, r3 109; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) 110; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 111; CHECK-BE-NEXT: addi r3, r3, -1 112; CHECK-BE-NEXT: stw r3, 0(r4) 113; CHECK-BE-NEXT: blr 114; 115; CHECK-LE-LABEL: test_ilesi_sext_store: 116; CHECK-LE: # %bb.0: # %entry 117; CHECK-LE-NEXT: sub r3, r4, r3 118; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha 119; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 120; CHECK-LE-NEXT: addi r3, r3, -1 121; CHECK-LE-NEXT: stw r3, glob@toc@l(r5) 122; CHECK-LE-NEXT: blr 123entry: 124 %cmp = icmp sle i32 %a, %b 125 %sub = sext i1 %cmp to i32 126 store i32 %sub, i32* @glob, align 4 127 ret void 128} 129