1; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ 2; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ 3; RUN: FileCheck %s --check-prefix=CHECK-P8 4; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ 5; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ 6; RUN: FileCheck %s --check-prefix=CHECK-P9 7; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ 8; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ 9; RUN: FileCheck %s --check-prefix=CHECK-BE 10 11define void @test8(<8 x double>* nocapture %Sink, <8 x i16>* nocapture readonly %SrcPtr) { 12entry: 13 %0 = load <8 x i16>, <8 x i16>* %SrcPtr, align 16 14 %1 = uitofp <8 x i16> %0 to <8 x double> 15 store <8 x double> %1, <8 x double>* %Sink, align 16 16 ret void 17; CHECK-P9-LABEL: @test8 18; CHECK-P9: vperm 19; CHECK-P9: xvcvuxddp 20; CHECK-P9: vperm 21; CHECK-P9: xvcvuxddp 22; CHECK-P9: vperm 23; CHECK-P9: xvcvuxddp 24; CHECK-P9: vperm 25; CHECK-P9: xvcvuxddp 26; CHECK-P8-LABEL: @test8 27; CHECK-P8: vperm 28; CHECK-P8: vperm 29; CHECK-P8: vperm 30; CHECK-P8: vperm 31; CHECK-P8: xvcvuxddp 32; CHECK-P8: xvcvuxddp 33; CHECK-P8: xvcvuxddp 34; CHECK-P8: xvcvuxddp 35} 36 37define void @test4(<4 x double>* nocapture %Sink, <4 x i16>* nocapture readonly %SrcPtr) { 38entry: 39 %0 = load <4 x i16>, <4 x i16>* %SrcPtr, align 16 40 %1 = uitofp <4 x i16> %0 to <4 x double> 41 store <4 x double> %1, <4 x double>* %Sink, align 16 42 ret void 43; CHECK-P9-LABEL: @test4 44; CHECK-P9: vperm 45; CHECK-P9: xvcvuxddp 46; CHECK-P9: vperm 47; CHECK-P9: xvcvuxddp 48; CHECK-P8-LABEL: @test4 49; CHECK-P8: vperm 50; CHECK-P8: vperm 51; CHECK-P8: xvcvuxddp 52; CHECK-P8: xvcvuxddp 53} 54 55define void @test2(<2 x double>* nocapture %Sink, <2 x i16>* nocapture readonly %SrcPtr) { 56entry: 57 %0 = load <2 x i16>, <2 x i16>* %SrcPtr, align 16 58 %1 = uitofp <2 x i16> %0 to <2 x double> 59 store <2 x double> %1, <2 x double>* %Sink, align 16 60 ret void 61; CHECK-P9-LABEL: .LCPI2_0: 62; CHECK-P9-NEXT: .byte 31 63; CHECK-P9-NEXT: .byte 30 64; CHECK-P9-NEXT: .byte 13 65; CHECK-P9-NEXT: .byte 12 66; CHECK-P9-NEXT: .byte 11 67; CHECK-P9-NEXT: .byte 10 68; CHECK-P9-NEXT: .byte 9 69; CHECK-P9-NEXT: .byte 8 70; CHECK-P9-NEXT: .byte 29 71; CHECK-P9-NEXT: .byte 28 72; CHECK-P9-NEXT: .byte 5 73; CHECK-P9-NEXT: .byte 4 74; CHECK-P9-NEXT: .byte 3 75; CHECK-P9-NEXT: .byte 2 76; CHECK-P9-NEXT: .byte 1 77; CHECK-P9-NEXT: .byte 0 78; CHECK-P9: addi [[REG1:r[0-9]+]], {{r[0-9]+}}, .LCPI2_0@toc@l 79; CHECK-P9: lxvx [[REG2:v[0-9]+]], 0, [[REG1]] 80; CHECK-P9: vperm [[REG3:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, [[REG2]] 81; CHECK-P9: xvcvuxddp {{vs[0-9]+}}, [[REG3]] 82; CHECK-P8-LABEL: @test2 83; CHECK-P8: vperm [[REG1:v[0-9]+]] 84; CHECK-P8: xvcvuxddp {{vs[0-9]+}}, [[REG1]] 85; CHECK-BE-LABEL: .LCPI2_0: 86; CHECK-BE-NEXT: .byte 16 87; CHECK-BE-NEXT: .byte 17 88; CHECK-BE-NEXT: .byte 18 89; CHECK-BE-NEXT: .byte 19 90; CHECK-BE-NEXT: .byte 20 91; CHECK-BE-NEXT: .byte 21 92; CHECK-BE-NEXT: .byte 0 93; CHECK-BE-NEXT: .byte 1 94; CHECK-BE-NEXT: .byte 24 95; CHECK-BE-NEXT: .byte 25 96; CHECK-BE-NEXT: .byte 26 97; CHECK-BE-NEXT: .byte 27 98; CHECK-BE-NEXT: .byte 28 99; CHECK-BE-NEXT: .byte 29 100; CHECK-BE-NEXT: .byte 2 101; CHECK-BE-NEXT: .byte 3 102; CHECK-BE: addi [[REG1:r[0-9]+]], {{r[0-9]+}}, .LCPI2_0@toc@l 103; CHECK-BE: lxvx [[REG2:v[0-9]+]], 0, [[REG1]] 104; CHECK-BE: vperm [[REG3:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, [[REG2]] 105; CHECK-BE: xvcvuxddp {{vs[0-9]+}}, [[REG3]] 106} 107 108define void @stest8(<8 x double>* nocapture %Sink, <8 x i16>* nocapture readonly %SrcPtr) { 109entry: 110 %0 = load <8 x i16>, <8 x i16>* %SrcPtr, align 16 111 %1 = sitofp <8 x i16> %0 to <8 x double> 112 store <8 x double> %1, <8 x double>* %Sink, align 16 113 ret void 114; CHECK-P9-LABEL: @stest8 115; CHECK-P9: vperm 116; CHECK-P9: vextsh2d 117; CHECK-P9: xvcvsxddp 118; CHECK-P9: vperm 119; CHECK-P9: vextsh2d 120; CHECK-P9: xvcvsxddp 121; CHECK-P9: vperm 122; CHECK-P9: vextsh2d 123; CHECK-P9: xvcvsxddp 124; CHECK-P9: vperm 125; CHECK-P9: vextsh2d 126; CHECK-P9: xvcvsxddp 127} 128 129define void @stest4(<4 x double>* nocapture %Sink, <4 x i16>* nocapture readonly %SrcPtr) { 130entry: 131 %0 = load <4 x i16>, <4 x i16>* %SrcPtr, align 16 132 %1 = sitofp <4 x i16> %0 to <4 x double> 133 store <4 x double> %1, <4 x double>* %Sink, align 16 134 ret void 135; CHECK-P9-LABEL: @stest4 136; CHECK-P9: vperm 137; CHECK-P9: vextsh2d 138; CHECK-P9: xvcvsxddp 139; CHECK-P9: vperm 140; CHECK-P9: vextsh2d 141; CHECK-P9: xvcvsxddp 142} 143 144define void @stest2(<2 x double>* nocapture %Sink, <2 x i16>* nocapture readonly %SrcPtr) { 145entry: 146 %0 = load <2 x i16>, <2 x i16>* %SrcPtr, align 16 147 %1 = sitofp <2 x i16> %0 to <2 x double> 148 store <2 x double> %1, <2 x double>* %Sink, align 16 149 ret void 150; CHECK-P9-LABEL: .LCPI5_0: 151; CHECK-P9-NEXT: .byte 31 152; CHECK-P9-NEXT: .byte 30 153; CHECK-P9-NEXT: .byte 31 154; CHECK-P9-NEXT: .byte 31 155; CHECK-P9-NEXT: .byte 31 156; CHECK-P9-NEXT: .byte 31 157; CHECK-P9-NEXT: .byte 31 158; CHECK-P9-NEXT: .byte 31 159; CHECK-P9-NEXT: .byte 29 160; CHECK-P9-NEXT: .byte 28 161; CHECK-P9-NEXT: .byte 31 162; CHECK-P9-NEXT: .byte 31 163; CHECK-P9-NEXT: .byte 31 164; CHECK-P9-NEXT: .byte 31 165; CHECK-P9-NEXT: .byte 31 166; CHECK-P9-NEXT: .byte 31 167; CHECK-P9: vperm [[REG1:v[0-9]+]] 168; CHECK-P9: vextsh2d [[REG2:v[0-9]+]], [[REG1]] 169; CHECK-P9: xvcvsxddp {{vs[0-9]+}}, [[REG2]] 170; CHECK-BE-LABEL: .LCPI5_0: 171; CHECK-BE-NEXT: .byte 0 172; CHECK-BE-NEXT: .byte 0 173; CHECK-BE-NEXT: .byte 0 174; CHECK-BE-NEXT: .byte 0 175; CHECK-BE-NEXT: .byte 0 176; CHECK-BE-NEXT: .byte 0 177; CHECK-BE-NEXT: .byte 0 178; CHECK-BE-NEXT: .byte 1 179; CHECK-BE-NEXT: .byte 0 180; CHECK-BE-NEXT: .byte 0 181; CHECK-BE-NEXT: .byte 0 182; CHECK-BE-NEXT: .byte 0 183; CHECK-BE-NEXT: .byte 0 184; CHECK-BE-NEXT: .byte 0 185; CHECK-BE-NEXT: .byte 2 186; CHECK-BE-NEXT: .byte 3 187; CHECK-BE: addi [[REG1:r[0-9]+]], {{r[0-9]+}}, .LCPI5_0@toc@l 188; CHECK-BE: lxvx [[REG2:v[0-9]+]], 0, [[REG1]] 189; CHECK-BE: vperm [[REG3:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, [[REG2]] 190; CHECK-BE: vextsh2d [[REG4:v[0-9]+]], [[REG3]] 191; CHECK-BE: xvcvsxddp {{vs[0-9]+}}, [[REG4]] 192} 193