1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 < %s  | FileCheck %s
3
4; Test that DAGCombiner gets helped by computeKnownBitsForTargetNode().
5
6; SystemZISD::REPLICATE
7define i32 @f0(<4 x i32> %a0) {
8; CHECK-LABEL: f0:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    vgbm %v0, 0
11; CHECK-NEXT:    vceqf %v0, %v24, %v0
12; CHECK-NEXT:    vrepif %v1, 1
13; CHECK-NEXT:    vnc %v0, %v1, %v0
14; CHECK-NEXT:    vlgvf %r2, %v0, 3
15; CHECK-NEXT:    # kill: def $r2l killed $r2l killed $r2d
16; CHECK-NEXT:    br %r14
17  %cmp0 = icmp ne <4 x i32> %a0, zeroinitializer
18  %zxt0 = zext <4 x i1> %cmp0 to <4 x i32>
19  %ext0 = extractelement <4 x i32> %zxt0, i32 3
20  br label %exit
21
22exit:
23; The vector icmp+zext involves a REPLICATE of 1's. If KnownBits reflects
24; this, DAGCombiner can see that the i32 icmp and zext here are not needed.
25  %cmp1 = icmp ne i32 %ext0, 0
26  %zxt1 = zext i1 %cmp1 to i32
27  ret i32 %zxt1
28}
29
30; SystemZISD::JOIN_DWORDS (and REPLICATE)
31; The DAG XOR has JOIN_DWORDS and REPLICATE operands. With KnownBits properly set
32; for both these nodes, ICMP is used instead of TM during lowering because
33; adjustForRedundantAnd() succeeds.
34define void @f1() {
35; CHECK-LABEL: f1:
36; CHECK:       # %bb.0:
37; CHECK-NEXT:    clhhsi 0, 0
38; CHECK-NEXT:    lhi %r0, 0
39; CHECK-NEXT:    lochie %r0, 1
40; CHECK-NEXT:    lghi %r1, 1
41; CHECK-NEXT:    vlvgp %v0, %r0, %r1
42; CHECK-NEXT:    vrepig %v1, 1
43; CHECK-NEXT:    vx %v0, %v0, %v1
44; CHECK-NEXT:    vlgvf %r0, %v0, 1
45; CHECK-NEXT:    cijlh %r0, 0, .LBB1_3
46; CHECK-NEXT:  # %bb.1:
47; CHECK-NEXT:    vlgvf %r0, %v0, 3
48; CHECK-NEXT:    cijlh %r0, 0, .LBB1_3
49; CHECK-NEXT:  # %bb.2:
50; CHECK-NEXT:  .LBB1_3:
51  %1 = load i16, i16* null, align 2
52  %2 = icmp eq i16 %1, 0
53  %3 = insertelement <2 x i1> undef, i1 %2, i32 0
54  %4 = insertelement <2 x i1> %3, i1 true, i32 1
55  %5 = xor <2 x i1> %4, <i1 true, i1 true>
56  %6 = extractelement <2 x i1> %5, i32 0
57  %7 = extractelement <2 x i1> %5, i32 1
58  %8 = or i1 %6, %7
59  br i1 %8, label %10, label %9
60
61; <label>:8:                                      ; preds = %0
62  unreachable
63
64; <label>:9:                                      ; preds = %0
65  unreachable
66}
67