1::FROM-WRITER;
2design top
3{
4   device
5   {
6      architecture sa5p00;
7      device LFE5U-25F;
8      package CABGA381;
9      performance "8";
10   }
11   comp MULT
12   {
13      logical {
14         cellmodel-name MULT18;
15         program "MODE:MULT18X18D "
16         "MULT18X18D:::REG_PIPELINE_CLK=NONE,REG_PIPELINE_RST=RST0,REG_OUTPUT_RST=RST0,\"
17         "REG_INPUTA_RST=RST0,REG_INPUTB_RST=RST0,REG_INPUTA_RST=RST0,REG_INPUTB_RST=RST0,REG_INPUTA_CE=CE0,\"
18         "REG_INPUTB_CE=CE0,REG_PIPELINE_CE=CE0,SOURCEB_MODE=B_SHIFT,REG_INPUTA_CLK=NONE,REG_INPUTB_CLK=NONE,\"
19         "REG_INPUTC_CLK=NONE,REG_OUTPUT_CLK=${outclk}";
20      }
21      site ${loc};
22   }
23  comp SLICE_0
24  [,,,,A0,B0,D0,C0,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,]
25   {
26      logical
27      {
28         cellmodel-name SLICE;
29         program "MODE:LOGIC "
30                 "K0::H0=0 "
31                 "F0:F ";
32         primitive K0 i3_4_lut;
33      }
34      site R2C2A;
35   }
36
37   signal q_c
38   {
39      signal-pins
40         // drivers
41         (MULT, P0),
42         // loads
43         (SLICE_0, A0);
44      ${route}
45   }
46
47
48   signal a_c
49   {
50      signal-pins
51         // drivers
52         (SLICE_0, F0),
53         // loads
54         (MULT, A0);
55      route
56        ${rc}_JMULTA0.${rc}_JA0_MULT18,
57        ${rc}_JMUIA0.${rc}_JMULTA0;
58   }
59
60}
61