1 /* name, operand 1, operand 2, operand 3, OpCode, Rn pos, CPU model */ 2 "and", {OP_GPR, OP_GPR, OP_GPR }, {0x80, 2, CPU_ALL}, 3 "and", {OP_GPR, OP_GPR, OP_IMM }, {0x80, 2, CPU_ALL}, 4 "or", {OP_GPR, OP_GPR, OP_GPR }, {0x81, 2, CPU_ALL}, 5 "or", {OP_GPR, OP_GPR, OP_IMM }, {0x81, 2, CPU_ALL}, 6 "xor", {OP_GPR, OP_GPR, OP_GPR }, {0x82, 2, CPU_ALL}, 7 "xor", {OP_GPR, OP_GPR, OP_IMM }, {0x82, 2, CPU_ALL}, 8 "bitc", {OP_GPR, OP_GPR, OP_GPR }, {0x83, 2, CPU_ALL}, 9 "bitc", {OP_GPR, OP_GPR, OP_IMM }, {0x83, 2, CPU_ALL}, 10 11 "add", {OP_GPR, OP_GPR, OP_GPR }, {0x84, 2, CPU_ALL}, 12 "add", {OP_GPR, OP_GPR, OP_IMM }, {0x84, 2, CPU_ALL}, 13 "addc", {OP_GPR, OP_GPR, OP_GPR }, {0x85, 2, CPU_ALL}, 14 "addc", {OP_GPR, OP_GPR, OP_IMM }, {0x85, 2, CPU_ALL}, 15 "sub", {OP_GPR, OP_GPR, OP_GPR }, {0x86, 2, CPU_ALL}, 16 "sub", {OP_GPR, OP_GPR, OP_IMM }, {0x86, 2, CPU_ALL}, 17 "subb", {OP_GPR, OP_GPR, OP_GPR }, {0x87, 2, CPU_ALL}, 18 "subb", {OP_GPR, OP_GPR, OP_IMM }, {0x87, 2, CPU_ALL}, 19 "rsb", {OP_GPR, OP_GPR, OP_GPR }, {0x88, 2, CPU_ALL}, 20 "rsb", {OP_GPR, OP_GPR, OP_IMM }, {0x88, 2, CPU_ALL}, 21 "rsbb", {OP_GPR, OP_GPR, OP_GPR }, {0x89, 2, CPU_ALL}, 22 "rsbb", {OP_GPR, OP_GPR, OP_IMM }, {0x89, 2, CPU_ALL}, 23 24 "lls", {OP_GPR, OP_GPR, OP_GPR }, {0x8A, 2, CPU_ALL}, 25 "lls", {OP_GPR, OP_GPR, OP_IMM }, {0x8A, 2, CPU_ALL}, 26 "lrs", {OP_GPR, OP_GPR, OP_GPR }, {0x8B, 2, CPU_ALL}, 27 "lrs", {OP_GPR, OP_GPR, OP_IMM }, {0x8B, 2, CPU_ALL}, 28 "ars", {OP_GPR, OP_GPR, OP_GPR }, {0x8C, 2, CPU_ALL}, 29 "ars", {OP_GPR, OP_GPR, OP_IMM }, {0x8C, 2, CPU_ALL}, 30 "rotl", {OP_GPR, OP_GPR, OP_GPR }, {0x8D, 2, CPU_ALL}, 31 "rotl", {OP_GPR, OP_GPR, OP_IMM }, {0x8D, 2, CPU_ALL}, 32 "rotr", {OP_GPR, OP_GPR, OP_GPR }, {0x8E, 2, CPU_ALL}, 33 "rotr", {OP_GPR, OP_GPR, OP_IMM }, {0x8E, 2, CPU_ALL}, 34 35 "mul", {OP_GPR, OP_GPR, OP_GPR }, {0x8F, 2, CPU_ALL}, 36 "mul", {OP_GPR, OP_GPR, OP_IMM }, {0x8F, 2, CPU_ALL}, 37 "smul", {OP_GPR, OP_GPR, OP_GPR }, {0x90, 2, CPU_ALL}, 38 "smul", {OP_GPR, OP_GPR, OP_IMM }, {0x90, 2, CPU_ALL}, 39 "div", {OP_GPR, OP_GPR, OP_GPR }, {0x91, 2, CPU_ALL}, 40 "div", {OP_GPR, OP_GPR, OP_IMM }, {0x91, 2, CPU_ALL}, 41 "sdiv", {OP_GPR, OP_GPR, OP_GPR }, {0x92, 2, CPU_ALL}, 42 "sdiv", {OP_GPR, OP_GPR, OP_IMM }, {0x92, 2, CPU_ALL}, 43 44 /* P2 */ 45 46 "mov", {OP_GPR, OP_GPR }, {0x40, 1, CPU_ALL}, 47 "mov", {OP_GPR, OP_IMM }, {0x40, 1, CPU_ALL}, 48 "swp", {OP_GPR, OP_GPR }, {0x41, 1, CPU_ALL}, 49 "not", {OP_GPR, OP_GPR }, {0x42, 1, CPU_ALL}, 50 "not", {OP_GPR, OP_IMM }, {0x42, 1, CPU_ALL}, 51 52 "sigxb", {OP_GPR, OP_GPR }, {0x43, 1, CPU_ALL}, 53 "sigxb", {OP_GPR, OP_IMM }, {0x43, 1, CPU_ALL}, 54 "sigxw", {OP_GPR, OP_GPR }, {0x44, 1, CPU_ALL}, 55 "sigxw", {OP_GPR, OP_IMM }, {0x44, 1, CPU_ALL}, 56 57 "jmp", {OP_GPR, OP_GPR }, {0x4B, 1, CPU_ALL}, 58 "jmp", {OP_GPR, OP_IMM }, {0x4B, 1, CPU_ALL}, 59 "call", {OP_GPR, OP_GPR }, {0x4C, 1, CPU_ALL}, 60 "call", {OP_GPR, OP_IMM }, {0x4C, 1, CPU_ALL}, 61 62 /* Branch */ 63 "ifeq", {OP_GPR, OP_GPR }, {0x70, 1, CPU_ALL}, 64 "ifeq", {OP_GPR, OP_IMM }, {0x70, 1, CPU_ALL}, 65 "ifneq", {OP_GPR, OP_GPR }, {0x71, 1, CPU_ALL}, 66 "ifneq", {OP_GPR, OP_IMM }, {0x71, 1, CPU_ALL}, 67 68 "ifl", {OP_GPR, OP_GPR }, {0x72, 1, CPU_ALL}, 69 "ifl", {OP_GPR, OP_IMM }, {0x72, 1, CPU_ALL}, 70 "ifsl", {OP_GPR, OP_GPR }, {0x73, 1, CPU_ALL}, 71 "ifsl", {OP_GPR, OP_IMM }, {0x73, 1, CPU_ALL}, 72 "ifle", {OP_GPR, OP_GPR }, {0x74, 1, CPU_ALL}, 73 "ifle", {OP_GPR, OP_IMM }, {0x74, 1, CPU_ALL}, 74 "ifsle", {OP_GPR, OP_GPR }, {0x75, 1, CPU_ALL}, 75 "ifsle", {OP_GPR, OP_IMM }, {0x75, 1, CPU_ALL}, 76 77 "ifg", {OP_GPR, OP_GPR }, {0x76, 1, CPU_ALL}, 78 "ifg", {OP_GPR, OP_IMM }, {0x76, 1, CPU_ALL}, 79 "ifsg", {OP_GPR, OP_GPR }, {0x77, 1, CPU_ALL}, 80 "ifsg", {OP_GPR, OP_IMM }, {0x77, 1, CPU_ALL}, 81 "ifge", {OP_GPR, OP_GPR }, {0x78, 1, CPU_ALL}, 82 "ifge", {OP_GPR, OP_IMM }, {0x78, 1, CPU_ALL}, 83 "ifsge", {OP_GPR, OP_GPR }, {0x79, 1, CPU_ALL}, 84 "ifsge", {OP_GPR, OP_IMM }, {0x79, 1, CPU_ALL}, 85 86 "ifbits", {OP_GPR, OP_GPR }, {0x7A, 1, CPU_ALL}, 87 "ifbits", {OP_GPR, OP_IMM }, {0x7A, 1, CPU_ALL}, 88 "ifclear", {OP_GPR, OP_GPR }, {0x7B, 1, CPU_ALL}, 89 "ifclear", {OP_GPR, OP_IMM }, {0x7B, 1, CPU_ALL}, 90 91 /* P1 instructions */ 92 "xchgb", {OP_GPR }, {0x20, 0, CPU_ALL}, 93 "xchgb", {OP_IMM }, {0x20, 0, CPU_ALL}, 94 "xchgw", {OP_GPR }, {0x21, 0, CPU_ALL}, 95 "xchgw", {OP_IMM }, {0x21, 0, CPU_ALL}, 96 97 "getpc", {OP_GPR }, {0x22, 0, CPU_ALL}, 98 99 "pop", {OP_GPR }, {0x23, 0, CPU_ALL}, 100 "push", {OP_GPR }, {0x24, 0, CPU_ALL}, 101 "push", {OP_IMM }, {0x24, 0, CPU_ALL}, 102 103 "jmp", {OP_GPR }, {0x25, 0, CPU_ALL}, 104 "jmp", {OP_IMM }, {0x25, 0, CPU_ALL}, 105 "call", {OP_GPR }, {0x26, 0, CPU_ALL}, 106 "call", {OP_IMM }, {0x26, 0, CPU_ALL}, 107 108 "rjmp", {OP_GPR }, {0x27, 0, CPU_ALL}, 109 "rjmp", {OP_IMM }, {0x27, 0, CPU_ALL}, 110 "rcall", {OP_GPR }, {0x28, 0, CPU_ALL}, 111 "rcall", {OP_IMM }, {0x28, 0, CPU_ALL}, 112 113 "int", {OP_GPR }, {0x29, 0, CPU_ALL}, 114 "int", {OP_IMM }, {0x29, 0, CPU_ALL}, 115 116 /* NP instructions */ 117 "sleep", { }, {0x00, 0, CPU_ALL}, 118 "ret", { }, {0x01, 0, CPU_ALL}, 119 "rfi", { }, {0x02, 0, CPU_ALL}, 120 121 /* Load / Store*/ 122 /* Register Were to read */ 123 "load", {OP_GPR, OP_GPR, OP_GPR }, {0x93, 2, CPU_ALL}, 124 "load", {OP_GPR, OP_GPR, OP_IMM }, {0x93, 2, CPU_ALL}, 125 "load", {OP_GPR, OP_GPR }, {0x45, 1, CPU_ALL}, 126 "load", {OP_GPR, OP_IMM }, {0x45, 1, CPU_ALL}, 127 "loadw", {OP_GPR, OP_GPR, OP_GPR }, {0x94, 2, CPU_ALL}, 128 "loadw", {OP_GPR, OP_GPR, OP_IMM }, {0x94, 2, CPU_ALL}, 129 "loadw", {OP_GPR, OP_GPR }, {0x46, 1, CPU_ALL}, 130 "loadw", {OP_GPR, OP_IMM }, {0x46, 1, CPU_ALL}, 131 "loadb", {OP_GPR, OP_GPR, OP_GPR }, {0x95, 2, CPU_ALL}, 132 "loadb", {OP_GPR, OP_GPR, OP_IMM }, {0x95, 2, CPU_ALL}, 133 "loadb", {OP_GPR, OP_GPR }, {0x47, 1, CPU_ALL}, 134 "loadb", {OP_GPR, OP_IMM }, {0x47, 1, CPU_ALL}, 135 /* Were to write data to write */ 136 "store", {OP_GPR, OP_GPR, OP_GPR }, {0x96, 1, CPU_ALL}, 137 "store", {OP_GPR, OP_IMM, OP_GPR }, {0x96, 1, CPU_ALL}, 138 "store", {OP_GPR, OP_GPR }, {0x48, 0, CPU_ALL}, 139 "store", {OP_IMM, OP_GPR }, {0x48, 0, CPU_ALL}, 140 "storew", {OP_GPR, OP_GPR, OP_GPR }, {0x97, 1, CPU_ALL}, 141 "storew", {OP_GPR, OP_IMM, OP_GPR }, {0x97, 1, CPU_ALL}, 142 "storew", {OP_GPR, OP_GPR }, {0x49, 0, CPU_ALL}, 143 "storew", {OP_IMM, OP_GPR }, {0x49, 0, CPU_ALL}, 144 "storeb", {OP_GPR, OP_GPR, OP_GPR }, {0x98, 1, CPU_ALL}, 145 "storeb", {OP_GPR, OP_IMM, OP_GPR }, {0x98, 1, CPU_ALL}, 146 "storeb", {OP_GPR, OP_GPR }, {0x4A, 0, CPU_ALL}, 147 "storeb", {OP_IMM, OP_GPR }, {0x4A, 0, CPU_ALL}, 148 149 /* TODO Others */ 150 151