1 //===-- clear_cache.c - Implement __clear_cache ---------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "int_lib.h"
10 #include <assert.h>
11 #include <stddef.h>
12
13 #if __APPLE__
14 #include <libkern/OSCacheControl.h>
15 #endif
16
17 #if defined(_WIN32)
18 // Forward declare Win32 APIs since the GCC mode driver does not handle the
19 // newer SDKs as well as needed.
20 uint32_t FlushInstructionCache(uintptr_t hProcess, void *lpBaseAddress,
21 uintptr_t dwSize);
22 uintptr_t GetCurrentProcess(void);
23 #endif
24
25 #if defined(__FreeBSD__) && defined(__arm__)
26 // clang-format off
27 #include <sys/types.h>
28 #include <machine/sysarch.h>
29 // clang-format on
30 #endif
31
32 #if defined(__NetBSD__) && defined(__arm__)
33 #include <machine/sysarch.h>
34 #endif
35
36 #if defined(__OpenBSD__) && (defined(__arm__) || defined(__mips__))
37 // clang-format off
38 #include <sys/types.h>
39 #include <machine/sysarch.h>
40 // clang-format on
41 #endif
42
43 #if defined(__linux__) && defined(__mips__)
44 #include <sys/cachectl.h>
45 #include <sys/syscall.h>
46 #include <unistd.h>
47 #endif
48
49 // The compiler generates calls to __clear_cache() when creating
50 // trampoline functions on the stack for use with nested functions.
51 // It is expected to invalidate the instruction cache for the
52 // specified range.
53
__clear_cache(void * start,void * end)54 void __clear_cache(void *start, void *end) {
55 #if __i386__ || __x86_64__ || defined(_M_IX86) || defined(_M_X64)
56 // Intel processors have a unified instruction and data cache
57 // so there is nothing to do
58 #elif defined(_WIN32) && (defined(__arm__) || defined(__aarch64__))
59 FlushInstructionCache(GetCurrentProcess(), start, end - start);
60 #elif defined(__arm__) && !defined(__APPLE__)
61 #if defined(__FreeBSD__) || defined(__NetBSD__) || defined(__OpenBSD__)
62 struct arm_sync_icache_args arg;
63
64 arg.addr = (uintptr_t)start;
65 arg.len = (uintptr_t)end - (uintptr_t)start;
66
67 sysarch(ARM_SYNC_ICACHE, &arg);
68 #elif defined(__linux__)
69 // We used to include asm/unistd.h for the __ARM_NR_cacheflush define, but
70 // it also brought many other unused defines, as well as a dependency on
71 // kernel headers to be installed.
72 //
73 // This value is stable at least since Linux 3.13 and should remain so for
74 // compatibility reasons, warranting it's re-definition here.
75 #define __ARM_NR_cacheflush 0x0f0002
76 register int start_reg __asm("r0") = (int)(intptr_t)start;
77 const register int end_reg __asm("r1") = (int)(intptr_t)end;
78 const register int flags __asm("r2") = 0;
79 const register int syscall_nr __asm("r7") = __ARM_NR_cacheflush;
80 __asm __volatile("svc 0x0"
81 : "=r"(start_reg)
82 : "r"(syscall_nr), "r"(start_reg), "r"(end_reg), "r"(flags));
83 assert(start_reg == 0 && "Cache flush syscall failed.");
84 #else
85 compilerrt_abort();
86 #endif
87 #elif defined(__linux__) && defined(__mips__)
88 const uintptr_t start_int = (uintptr_t)start;
89 const uintptr_t end_int = (uintptr_t)end;
90 syscall(__NR_cacheflush, start, (end_int - start_int), BCACHE);
91 #elif defined(__mips__) && defined(__OpenBSD__)
92 cacheflush(start, (uintptr_t)end - (uintptr_t)start, BCACHE);
93 #elif defined(__aarch64__) && !defined(__APPLE__)
94 uint64_t xstart = (uint64_t)(uintptr_t)start;
95 uint64_t xend = (uint64_t)(uintptr_t)end;
96
97 // Get Cache Type Info.
98 static uint64_t ctr_el0 = 0;
99 if (ctr_el0 == 0)
100 __asm __volatile("mrs %0, ctr_el0" : "=r"(ctr_el0));
101
102 // The DC and IC instructions must use 64-bit registers so we don't use
103 // uintptr_t in case this runs in an IPL32 environment.
104 uint64_t addr;
105
106 // If CTR_EL0.IDC is set, data cache cleaning to the point of unification
107 // is not required for instruction to data coherence.
108 if (((ctr_el0 >> 28) & 0x1) == 0x0) {
109 const size_t dcache_line_size = 4 << ((ctr_el0 >> 16) & 15);
110 for (addr = xstart & ~(dcache_line_size - 1); addr < xend;
111 addr += dcache_line_size)
112 __asm __volatile("dc cvau, %0" ::"r"(addr));
113 }
114 __asm __volatile("dsb ish");
115
116 // If CTR_EL0.DIC is set, instruction cache invalidation to the point of
117 // unification is not required for instruction to data coherence.
118 if (((ctr_el0 >> 29) & 0x1) == 0x0) {
119 const size_t icache_line_size = 4 << ((ctr_el0 >> 0) & 15);
120 for (addr = xstart & ~(icache_line_size - 1); addr < xend;
121 addr += icache_line_size)
122 __asm __volatile("ic ivau, %0" ::"r"(addr));
123 }
124 __asm __volatile("isb sy");
125 #elif defined(__powerpc64__)
126 const size_t line_size = 32;
127 const size_t len = (uintptr_t)end - (uintptr_t)start;
128
129 const uintptr_t mask = ~(line_size - 1);
130 const uintptr_t start_line = ((uintptr_t)start) & mask;
131 const uintptr_t end_line = ((uintptr_t)start + len + line_size - 1) & mask;
132
133 for (uintptr_t line = start_line; line < end_line; line += line_size)
134 __asm__ volatile("dcbf 0, %0" : : "r"(line));
135 __asm__ volatile("sync");
136
137 for (uintptr_t line = start_line; line < end_line; line += line_size)
138 __asm__ volatile("icbi 0, %0" : : "r"(line));
139 __asm__ volatile("isync");
140 #elif defined(__sparc__)
141 const size_t dword_size = 8;
142 const size_t len = (uintptr_t)end - (uintptr_t)start;
143
144 const uintptr_t mask = ~(dword_size - 1);
145 const uintptr_t start_dword = ((uintptr_t)start) & mask;
146 const uintptr_t end_dword = ((uintptr_t)start + len + dword_size - 1) & mask;
147
148 for (uintptr_t dword = start_dword; dword < end_dword; dword += dword_size)
149 __asm__ volatile("flush %0" : : "r"(dword));
150 #elif defined(__riscv) && defined(__linux__)
151 #define __NR_riscv_flush_icache (244 + 15)
152 register void *start_reg __asm("a0") = start;
153 const register void *end_reg __asm("a1") = end;
154 const register long flags __asm("a2") = 0;
155 const register long syscall_nr __asm("a7") = __NR_riscv_flush_icache;
156 __asm __volatile("ecall"
157 : "=r"(start_reg)
158 : "r"(start_reg), "r"(end_reg), "r"(flags), "r"(syscall_nr));
159 assert(start_reg == 0 && "Cache flush syscall failed.");
160 #else
161 #if __APPLE__
162 // On Darwin, sys_icache_invalidate() provides this functionality
163 sys_icache_invalidate(start, end - start);
164 #else
165 compilerrt_abort();
166 #endif
167 #endif
168 }
169