1 //===-- X86TargetParser - Parser for X86 features ---------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements a target parser to recognise X86 hardware features.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/Support/X86TargetParser.h"
14 #include "llvm/ADT/Triple.h"
15 
16 using namespace llvm;
17 using namespace llvm::X86;
18 
19 namespace {
20 
21 /// Container class for CPU features.
22 /// This is a constexpr reimplementation of a subset of std::bitset. It would be
23 /// nice to use std::bitset directly, but it doesn't support constant
24 /// initialization.
25 class FeatureBitset {
26   static constexpr unsigned NUM_FEATURE_WORDS =
27       (X86::CPU_FEATURE_MAX + 31) / 32;
28 
29   // This cannot be a std::array, operator[] is not constexpr until C++17.
30   uint32_t Bits[NUM_FEATURE_WORDS] = {};
31 
32 public:
33   constexpr FeatureBitset() = default;
FeatureBitset(std::initializer_list<unsigned> Init)34   constexpr FeatureBitset(std::initializer_list<unsigned> Init) {
35     for (auto I : Init)
36       set(I);
37   }
38 
any() const39   bool any() const {
40     return llvm::any_of(Bits, [](uint64_t V) { return V != 0; });
41   }
42 
set(unsigned I)43   constexpr FeatureBitset &set(unsigned I) {
44     // GCC <6.2 crashes if this is written in a single statement.
45     uint32_t NewBits = Bits[I / 32] | (uint32_t(1) << (I % 32));
46     Bits[I / 32] = NewBits;
47     return *this;
48   }
49 
operator [](unsigned I) const50   constexpr bool operator[](unsigned I) const {
51     uint32_t Mask = uint32_t(1) << (I % 32);
52     return (Bits[I / 32] & Mask) != 0;
53   }
54 
operator &=(const FeatureBitset & RHS)55   constexpr FeatureBitset &operator&=(const FeatureBitset &RHS) {
56     for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) {
57       // GCC <6.2 crashes if this is written in a single statement.
58       uint32_t NewBits = Bits[I] & RHS.Bits[I];
59       Bits[I] = NewBits;
60     }
61     return *this;
62   }
63 
operator |=(const FeatureBitset & RHS)64   constexpr FeatureBitset &operator|=(const FeatureBitset &RHS) {
65     for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) {
66       // GCC <6.2 crashes if this is written in a single statement.
67       uint32_t NewBits = Bits[I] | RHS.Bits[I];
68       Bits[I] = NewBits;
69     }
70     return *this;
71   }
72 
73   // gcc 5.3 miscompiles this if we try to write this using operator&=.
operator &(const FeatureBitset & RHS) const74   constexpr FeatureBitset operator&(const FeatureBitset &RHS) const {
75     FeatureBitset Result;
76     for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
77       Result.Bits[I] = Bits[I] & RHS.Bits[I];
78     return Result;
79   }
80 
81   // gcc 5.3 miscompiles this if we try to write this using operator&=.
operator |(const FeatureBitset & RHS) const82   constexpr FeatureBitset operator|(const FeatureBitset &RHS) const {
83     FeatureBitset Result;
84     for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
85       Result.Bits[I] = Bits[I] | RHS.Bits[I];
86     return Result;
87   }
88 
operator ~() const89   constexpr FeatureBitset operator~() const {
90     FeatureBitset Result;
91     for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
92       Result.Bits[I] = ~Bits[I];
93     return Result;
94   }
95 
operator !=(const FeatureBitset & RHS) const96   constexpr bool operator!=(const FeatureBitset &RHS) const {
97     for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
98       if (Bits[I] != RHS.Bits[I])
99         return true;
100     return false;
101   }
102 };
103 
104 struct ProcInfo {
105   StringLiteral Name;
106   X86::CPUKind Kind;
107   unsigned KeyFeature;
108   FeatureBitset Features;
109 };
110 
111 struct FeatureInfo {
112   StringLiteral Name;
113   FeatureBitset ImpliedFeatures;
114 };
115 
116 } // end anonymous namespace
117 
118 #define X86_FEATURE(ENUM, STRING)                                              \
119   constexpr FeatureBitset Feature##ENUM = {X86::FEATURE_##ENUM};
120 #include "llvm/Support/X86TargetParser.def"
121 
122 // Pentium with MMX.
123 constexpr FeatureBitset FeaturesPentiumMMX =
124     FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
125 
126 // Pentium 2 and 3.
127 constexpr FeatureBitset FeaturesPentium2 =
128     FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeatureFXSR;
129 constexpr FeatureBitset FeaturesPentium3 = FeaturesPentium2 | FeatureSSE;
130 
131 // Pentium 4 CPUs
132 constexpr FeatureBitset FeaturesPentium4 = FeaturesPentium3 | FeatureSSE2;
133 constexpr FeatureBitset FeaturesPrescott = FeaturesPentium4 | FeatureSSE3;
134 constexpr FeatureBitset FeaturesNocona =
135     FeaturesPrescott | Feature64BIT | FeatureCMPXCHG16B;
136 
137 // Basic 64-bit capable CPU.
138 constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | Feature64BIT;
139 constexpr FeatureBitset FeaturesX86_64_V2 = FeaturesX86_64 | FeatureSAHF |
140                                             FeaturePOPCNT | FeatureSSE4_2 |
141                                             FeatureCMPXCHG16B;
142 constexpr FeatureBitset FeaturesX86_64_V3 =
143     FeaturesX86_64_V2 | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureF16C |
144     FeatureFMA | FeatureLZCNT | FeatureMOVBE | FeatureXSAVE;
145 constexpr FeatureBitset FeaturesX86_64_V4 = FeaturesX86_64_V3 |
146                                             FeatureAVX512BW | FeatureAVX512CD |
147                                             FeatureAVX512DQ | FeatureAVX512VL;
148 
149 // Intel Core CPUs
150 constexpr FeatureBitset FeaturesCore2 =
151     FeaturesNocona | FeatureSAHF | FeatureSSSE3;
152 constexpr FeatureBitset FeaturesPenryn = FeaturesCore2 | FeatureSSE4_1;
153 constexpr FeatureBitset FeaturesNehalem =
154     FeaturesPenryn | FeaturePOPCNT | FeatureSSE4_2;
155 constexpr FeatureBitset FeaturesWestmere = FeaturesNehalem | FeaturePCLMUL;
156 constexpr FeatureBitset FeaturesSandyBridge =
157     FeaturesWestmere | FeatureAVX | FeatureXSAVE | FeatureXSAVEOPT;
158 constexpr FeatureBitset FeaturesIvyBridge =
159     FeaturesSandyBridge | FeatureF16C | FeatureFSGSBASE | FeatureRDRND;
160 constexpr FeatureBitset FeaturesHaswell =
161     FeaturesIvyBridge | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureFMA |
162     FeatureINVPCID | FeatureLZCNT | FeatureMOVBE;
163 constexpr FeatureBitset FeaturesBroadwell =
164     FeaturesHaswell | FeatureADX | FeaturePRFCHW | FeatureRDSEED;
165 
166 // Intel Knights Landing and Knights Mill
167 // Knights Landing has feature parity with Broadwell.
168 constexpr FeatureBitset FeaturesKNL =
169     FeaturesBroadwell | FeatureAES | FeatureAVX512F | FeatureAVX512CD |
170     FeatureAVX512ER | FeatureAVX512PF | FeaturePREFETCHWT1;
171 constexpr FeatureBitset FeaturesKNM = FeaturesKNL | FeatureAVX512VPOPCNTDQ;
172 
173 // Intel Skylake processors.
174 constexpr FeatureBitset FeaturesSkylakeClient =
175     FeaturesBroadwell | FeatureAES | FeatureCLFLUSHOPT | FeatureXSAVEC |
176     FeatureXSAVES | FeatureSGX;
177 // SkylakeServer inherits all SkylakeClient features except SGX.
178 // FIXME: That doesn't match gcc.
179 constexpr FeatureBitset FeaturesSkylakeServer =
180     (FeaturesSkylakeClient & ~FeatureSGX) | FeatureAVX512F | FeatureAVX512CD |
181     FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureCLWB |
182     FeaturePKU;
183 constexpr FeatureBitset FeaturesCascadeLake =
184     FeaturesSkylakeServer | FeatureAVX512VNNI;
185 constexpr FeatureBitset FeaturesCooperLake =
186     FeaturesCascadeLake | FeatureAVX512BF16;
187 
188 // Intel 10nm processors.
189 constexpr FeatureBitset FeaturesCannonlake =
190     FeaturesSkylakeClient | FeatureAVX512F | FeatureAVX512CD | FeatureAVX512DQ |
191     FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | FeatureAVX512VBMI |
192     FeaturePKU | FeatureSHA;
193 constexpr FeatureBitset FeaturesICLClient =
194     FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 |
195     FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureCLWB | FeatureGFNI |
196     FeatureRDPID | FeatureVAES | FeatureVPCLMULQDQ;
197 constexpr FeatureBitset FeaturesICLServer =
198     FeaturesICLClient | FeaturePCONFIG | FeatureWBNOINVD;
199 constexpr FeatureBitset FeaturesTigerlake =
200     FeaturesICLClient | FeatureAVX512VP2INTERSECT | FeatureMOVDIR64B |
201     FeatureMOVDIRI | FeatureSHSTK | FeatureKL | FeatureWIDEKL;
202 constexpr FeatureBitset FeaturesSapphireRapids =
203     FeaturesICLServer | FeatureAMX_TILE | FeatureAMX_INT8 | FeatureAMX_BF16 |
204     FeatureAVX512BF16 | FeatureAVX512VP2INTERSECT | FeatureCLDEMOTE |
205     FeatureENQCMD | FeatureMOVDIR64B | FeatureMOVDIRI | FeaturePTWRITE |
206     FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureUINTR |
207     FeatureWAITPKG | FeatureAVXVNNI;
208 constexpr FeatureBitset FeaturesAlderlake =
209     FeaturesSkylakeClient | FeatureCLDEMOTE | FeatureHRESET | FeaturePTWRITE |
210     FeatureSERIALIZE | FeatureWAITPKG | FeatureAVXVNNI;
211 
212 // Intel Atom processors.
213 // Bonnell has feature parity with Core2 and adds MOVBE.
214 constexpr FeatureBitset FeaturesBonnell = FeaturesCore2 | FeatureMOVBE;
215 // Silvermont has parity with Westmere and Bonnell plus PRFCHW and RDRND.
216 constexpr FeatureBitset FeaturesSilvermont =
217     FeaturesBonnell | FeaturesWestmere | FeaturePRFCHW | FeatureRDRND;
218 constexpr FeatureBitset FeaturesGoldmont =
219     FeaturesSilvermont | FeatureAES | FeatureCLFLUSHOPT | FeatureFSGSBASE |
220     FeatureRDSEED | FeatureSHA | FeatureXSAVE | FeatureXSAVEC |
221     FeatureXSAVEOPT | FeatureXSAVES;
222 constexpr FeatureBitset FeaturesGoldmontPlus =
223     FeaturesGoldmont | FeaturePTWRITE | FeatureRDPID | FeatureSGX;
224 constexpr FeatureBitset FeaturesTremont =
225     FeaturesGoldmontPlus | FeatureCLWB | FeatureGFNI;
226 
227 // Geode Processor.
228 constexpr FeatureBitset FeaturesGeode =
229     FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
230 
231 // K6 processor.
232 constexpr FeatureBitset FeaturesK6 = FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
233 
234 // K7 and K8 architecture processors.
235 constexpr FeatureBitset FeaturesAthlon =
236     FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
237 constexpr FeatureBitset FeaturesAthlonXP =
238     FeaturesAthlon | FeatureFXSR | FeatureSSE;
239 constexpr FeatureBitset FeaturesK8 =
240     FeaturesAthlonXP | FeatureSSE2 | Feature64BIT;
241 constexpr FeatureBitset FeaturesK8SSE3 = FeaturesK8 | FeatureSSE3;
242 constexpr FeatureBitset FeaturesAMDFAM10 =
243     FeaturesK8SSE3 | FeatureCMPXCHG16B | FeatureLZCNT | FeaturePOPCNT |
244     FeaturePRFCHW | FeatureSAHF | FeatureSSE4_A;
245 
246 // Bobcat architecture processors.
247 constexpr FeatureBitset FeaturesBTVER1 =
248     FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT |
249     FeatureFXSR | FeatureLZCNT | FeatureMMX | FeaturePOPCNT | FeaturePRFCHW |
250     FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_A |
251     FeatureSAHF;
252 constexpr FeatureBitset FeaturesBTVER2 =
253     FeaturesBTVER1 | FeatureAES | FeatureAVX | FeatureBMI | FeatureF16C |
254     FeatureMOVBE | FeaturePCLMUL | FeatureXSAVE | FeatureXSAVEOPT;
255 
256 // AMD Bulldozer architecture processors.
257 constexpr FeatureBitset FeaturesBDVER1 =
258     FeatureX87 | FeatureAES | FeatureAVX | FeatureCMPXCHG8B |
259     FeatureCMPXCHG16B | Feature64BIT | FeatureFMA4 | FeatureFXSR | FeatureLWP |
260     FeatureLZCNT | FeatureMMX | FeaturePCLMUL | FeaturePOPCNT | FeaturePRFCHW |
261     FeatureSAHF | FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 |
262     FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4_A | FeatureXOP | FeatureXSAVE;
263 constexpr FeatureBitset FeaturesBDVER2 =
264     FeaturesBDVER1 | FeatureBMI | FeatureFMA | FeatureF16C | FeatureTBM;
265 constexpr FeatureBitset FeaturesBDVER3 =
266     FeaturesBDVER2 | FeatureFSGSBASE | FeatureXSAVEOPT;
267 constexpr FeatureBitset FeaturesBDVER4 = FeaturesBDVER3 | FeatureAVX2 |
268                                          FeatureBMI2 | FeatureMOVBE |
269                                          FeatureMWAITX | FeatureRDRND;
270 
271 // AMD Zen architecture processors.
272 constexpr FeatureBitset FeaturesZNVER1 =
273     FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 |
274     FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO |
275     FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT | FeatureF16C |
276     FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT | FeatureMMX |
277     FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT |
278     FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA |
279     FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 |
280     FeatureSSE4_2 | FeatureSSE4_A | FeatureXSAVE | FeatureXSAVEC |
281     FeatureXSAVEOPT | FeatureXSAVES;
282 constexpr FeatureBitset FeaturesZNVER2 =
283     FeaturesZNVER1 | FeatureCLWB | FeatureRDPID | FeatureWBNOINVD;
284 static constexpr FeatureBitset FeaturesZNVER3 = FeaturesZNVER2 |
285                                                 FeatureINVPCID | FeaturePKU |
286                                                 FeatureVAES | FeatureVPCLMULQDQ;
287 
288 constexpr ProcInfo Processors[] = {
289   // Empty processor. Include X87 and CMPXCHG8 for backwards compatibility.
290   { {""}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B },
291   // i386-generation processors.
292   { {"i386"}, CK_i386, ~0U, FeatureX87 },
293   // i486-generation processors.
294   { {"i486"}, CK_i486, ~0U, FeatureX87 },
295   { {"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX },
296   { {"winchip2"}, CK_WinChip2, ~0U, FeaturesPentiumMMX | Feature3DNOW },
297   { {"c3"}, CK_C3, ~0U, FeaturesPentiumMMX | Feature3DNOW },
298   // i586-generation processors, P5 microarchitecture based.
299   { {"i586"}, CK_i586, ~0U, FeatureX87 | FeatureCMPXCHG8B },
300   { {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B },
301   { {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX },
302   // i686-generation processors, P6 / Pentium M microarchitecture based.
303   { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureX87 | FeatureCMPXCHG8B },
304   { {"i686"}, CK_i686, ~0U, FeatureX87 | FeatureCMPXCHG8B },
305   { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2 },
306   { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3 },
307   { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3 },
308   { {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4 },
309   { {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3 },
310   { {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott },
311   // Netburst microarchitecture based processors.
312   { {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4 },
313   { {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4 },
314   { {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott },
315   { {"nocona"}, CK_Nocona, ~0U, FeaturesNocona },
316   // Core microarchitecture based processors.
317   { {"core2"}, CK_Core2, ~0U, FeaturesCore2 },
318   { {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn },
319   // Atom processors
320   { {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell },
321   { {"atom"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell },
322   { {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont },
323   { {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont },
324   { {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont },
325   { {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus },
326   { {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont },
327   // Nehalem microarchitecture based processors.
328   { {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem },
329   { {"corei7"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem },
330   // Westmere microarchitecture based processors.
331   { {"westmere"}, CK_Westmere, FEATURE_PCLMUL, FeaturesWestmere },
332   // Sandy Bridge microarchitecture based processors.
333   { {"sandybridge"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge },
334   { {"corei7-avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge },
335   // Ivy Bridge microarchitecture based processors.
336   { {"ivybridge"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge },
337   { {"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge },
338   // Haswell microarchitecture based processors.
339   { {"haswell"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell },
340   { {"core-avx2"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell },
341   // Broadwell microarchitecture based processors.
342   { {"broadwell"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell },
343   // Skylake client microarchitecture based processors.
344   { {"skylake"}, CK_SkylakeClient, FEATURE_AVX2, FeaturesSkylakeClient },
345   // Skylake server microarchitecture based processors.
346   { {"skylake-avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer },
347   { {"skx"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer },
348   // Cascadelake Server microarchitecture based processors.
349   { {"cascadelake"}, CK_Cascadelake, FEATURE_AVX512VNNI, FeaturesCascadeLake },
350   // Cooperlake Server microarchitecture based processors.
351   { {"cooperlake"}, CK_Cooperlake, FEATURE_AVX512BF16, FeaturesCooperLake },
352   // Cannonlake client microarchitecture based processors.
353   { {"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, FeaturesCannonlake },
354   // Icelake client microarchitecture based processors.
355   { {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient },
356   // Icelake server microarchitecture based processors.
357   { {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer },
358   // Tigerlake microarchitecture based processors.
359   { {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake },
360   // Sapphire Rapids microarchitecture based processors.
361   { {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512VP2INTERSECT, FeaturesSapphireRapids },
362   // Alderlake microarchitecture based processors.
363   { {"alderlake"}, CK_Alderlake, FEATURE_AVX2, FeaturesAlderlake },
364   // Knights Landing processor.
365   { {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL },
366   // Knights Mill processor.
367   { {"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, FeaturesKNM },
368   // Lakemont microarchitecture based processors.
369   { {"lakemont"}, CK_Lakemont, ~0U, FeatureCMPXCHG8B },
370   // K6 architecture processors.
371   { {"k6"}, CK_K6, ~0U, FeaturesK6 },
372   { {"k6-2"}, CK_K6_2, ~0U, FeaturesK6 | Feature3DNOW },
373   { {"k6-3"}, CK_K6_3, ~0U, FeaturesK6 | Feature3DNOW },
374   // K7 architecture processors.
375   { {"athlon"}, CK_Athlon, ~0U, FeaturesAthlon },
376   { {"athlon-tbird"}, CK_Athlon, ~0U, FeaturesAthlon },
377   { {"athlon-xp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
378   { {"athlon-mp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
379   { {"athlon-4"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
380   // K8 architecture processors.
381   { {"k8"}, CK_K8, ~0U, FeaturesK8 },
382   { {"athlon64"}, CK_K8, ~0U, FeaturesK8 },
383   { {"athlon-fx"}, CK_K8, ~0U, FeaturesK8 },
384   { {"opteron"}, CK_K8, ~0U, FeaturesK8 },
385   { {"k8-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
386   { {"athlon64-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
387   { {"opteron-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
388   { {"amdfam10"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 },
389   { {"barcelona"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 },
390   // Bobcat architecture processors.
391   { {"btver1"}, CK_BTVER1, FEATURE_SSE4_A, FeaturesBTVER1 },
392   { {"btver2"}, CK_BTVER2, FEATURE_BMI, FeaturesBTVER2 },
393   // Bulldozer architecture processors.
394   { {"bdver1"}, CK_BDVER1, FEATURE_XOP, FeaturesBDVER1 },
395   { {"bdver2"}, CK_BDVER2, FEATURE_FMA, FeaturesBDVER2 },
396   { {"bdver3"}, CK_BDVER3, FEATURE_FMA, FeaturesBDVER3 },
397   { {"bdver4"}, CK_BDVER4, FEATURE_AVX2, FeaturesBDVER4 },
398   // Zen architecture processors.
399   { {"znver1"}, CK_ZNVER1, FEATURE_AVX2, FeaturesZNVER1 },
400   { {"znver2"}, CK_ZNVER2, FEATURE_AVX2, FeaturesZNVER2 },
401   { {"znver3"}, CK_ZNVER3, FEATURE_AVX2, FeaturesZNVER3 },
402   // Generic 64-bit processor.
403   { {"x86-64"}, CK_x86_64, ~0U, FeaturesX86_64 },
404   { {"x86-64-v2"}, CK_x86_64_v2, ~0U, FeaturesX86_64_V2 },
405   { {"x86-64-v3"}, CK_x86_64_v3, ~0U, FeaturesX86_64_V3 },
406   { {"x86-64-v4"}, CK_x86_64_v4, ~0U, FeaturesX86_64_V4 },
407   // Geode processors.
408   { {"geode"}, CK_Geode, ~0U, FeaturesGeode },
409 };
410 
411 constexpr const char *NoTuneList[] = {"x86-64-v2", "x86-64-v3", "x86-64-v4"};
412 
parseArchX86(StringRef CPU,bool Only64Bit)413 X86::CPUKind llvm::X86::parseArchX86(StringRef CPU, bool Only64Bit) {
414   for (const auto &P : Processors)
415     if (P.Name == CPU && (P.Features[FEATURE_64BIT] || !Only64Bit))
416       return P.Kind;
417 
418   return CK_None;
419 }
420 
parseTuneCPU(StringRef CPU,bool Only64Bit)421 X86::CPUKind llvm::X86::parseTuneCPU(StringRef CPU, bool Only64Bit) {
422   if (llvm::is_contained(NoTuneList, CPU))
423     return CK_None;
424   return parseArchX86(CPU, Only64Bit);
425 }
426 
fillValidCPUArchList(SmallVectorImpl<StringRef> & Values,bool Only64Bit)427 void llvm::X86::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values,
428                                      bool Only64Bit) {
429   for (const auto &P : Processors)
430     if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit))
431       Values.emplace_back(P.Name);
432 }
433 
fillValidTuneCPUList(SmallVectorImpl<StringRef> & Values,bool Only64Bit)434 void llvm::X86::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values,
435                                      bool Only64Bit) {
436   for (const ProcInfo &P : Processors)
437     if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit) &&
438         !llvm::is_contained(NoTuneList, P.Name))
439       Values.emplace_back(P.Name);
440 }
441 
getKeyFeature(X86::CPUKind Kind)442 ProcessorFeatures llvm::X86::getKeyFeature(X86::CPUKind Kind) {
443   // FIXME: Can we avoid a linear search here? The table might be sorted by
444   // CPUKind so we could binary search?
445   for (const auto &P : Processors) {
446     if (P.Kind == Kind) {
447       assert(P.KeyFeature != ~0U && "Processor does not have a key feature.");
448       return static_cast<ProcessorFeatures>(P.KeyFeature);
449     }
450   }
451 
452   llvm_unreachable("Unable to find CPU kind!");
453 }
454 
455 // Features with no dependencies.
456 constexpr FeatureBitset ImpliedFeatures64BIT = {};
457 constexpr FeatureBitset ImpliedFeaturesADX = {};
458 constexpr FeatureBitset ImpliedFeaturesBMI = {};
459 constexpr FeatureBitset ImpliedFeaturesBMI2 = {};
460 constexpr FeatureBitset ImpliedFeaturesCLDEMOTE = {};
461 constexpr FeatureBitset ImpliedFeaturesCLFLUSHOPT = {};
462 constexpr FeatureBitset ImpliedFeaturesCLWB = {};
463 constexpr FeatureBitset ImpliedFeaturesCLZERO = {};
464 constexpr FeatureBitset ImpliedFeaturesCMOV = {};
465 constexpr FeatureBitset ImpliedFeaturesCMPXCHG16B = {};
466 constexpr FeatureBitset ImpliedFeaturesCMPXCHG8B = {};
467 constexpr FeatureBitset ImpliedFeaturesENQCMD = {};
468 constexpr FeatureBitset ImpliedFeaturesFSGSBASE = {};
469 constexpr FeatureBitset ImpliedFeaturesFXSR = {};
470 constexpr FeatureBitset ImpliedFeaturesINVPCID = {};
471 constexpr FeatureBitset ImpliedFeaturesLWP = {};
472 constexpr FeatureBitset ImpliedFeaturesLZCNT = {};
473 constexpr FeatureBitset ImpliedFeaturesMWAITX = {};
474 constexpr FeatureBitset ImpliedFeaturesMOVBE = {};
475 constexpr FeatureBitset ImpliedFeaturesMOVDIR64B = {};
476 constexpr FeatureBitset ImpliedFeaturesMOVDIRI = {};
477 constexpr FeatureBitset ImpliedFeaturesPCONFIG = {};
478 constexpr FeatureBitset ImpliedFeaturesPOPCNT = {};
479 constexpr FeatureBitset ImpliedFeaturesPKU = {};
480 constexpr FeatureBitset ImpliedFeaturesPREFETCHWT1 = {};
481 constexpr FeatureBitset ImpliedFeaturesPRFCHW = {};
482 constexpr FeatureBitset ImpliedFeaturesPTWRITE = {};
483 constexpr FeatureBitset ImpliedFeaturesRDPID = {};
484 constexpr FeatureBitset ImpliedFeaturesRDRND = {};
485 constexpr FeatureBitset ImpliedFeaturesRDSEED = {};
486 constexpr FeatureBitset ImpliedFeaturesRTM = {};
487 constexpr FeatureBitset ImpliedFeaturesSAHF = {};
488 constexpr FeatureBitset ImpliedFeaturesSERIALIZE = {};
489 constexpr FeatureBitset ImpliedFeaturesSGX = {};
490 constexpr FeatureBitset ImpliedFeaturesSHSTK = {};
491 constexpr FeatureBitset ImpliedFeaturesTBM = {};
492 constexpr FeatureBitset ImpliedFeaturesTSXLDTRK = {};
493 constexpr FeatureBitset ImpliedFeaturesUINTR = {};
494 constexpr FeatureBitset ImpliedFeaturesWAITPKG = {};
495 constexpr FeatureBitset ImpliedFeaturesWBNOINVD = {};
496 constexpr FeatureBitset ImpliedFeaturesVZEROUPPER = {};
497 constexpr FeatureBitset ImpliedFeaturesX87 = {};
498 constexpr FeatureBitset ImpliedFeaturesXSAVE = {};
499 
500 // Not really CPU features, but need to be in the table because clang uses
501 // target features to communicate them to the backend.
502 constexpr FeatureBitset ImpliedFeaturesRETPOLINE_EXTERNAL_THUNK = {};
503 constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_BRANCHES = {};
504 constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_CALLS = {};
505 constexpr FeatureBitset ImpliedFeaturesLVI_CFI = {};
506 constexpr FeatureBitset ImpliedFeaturesLVI_LOAD_HARDENING = {};
507 
508 // XSAVE features are dependent on basic XSAVE.
509 constexpr FeatureBitset ImpliedFeaturesXSAVEC = FeatureXSAVE;
510 constexpr FeatureBitset ImpliedFeaturesXSAVEOPT = FeatureXSAVE;
511 constexpr FeatureBitset ImpliedFeaturesXSAVES = FeatureXSAVE;
512 
513 // MMX->3DNOW->3DNOWA chain.
514 constexpr FeatureBitset ImpliedFeaturesMMX = {};
515 constexpr FeatureBitset ImpliedFeatures3DNOW = FeatureMMX;
516 constexpr FeatureBitset ImpliedFeatures3DNOWA = Feature3DNOW;
517 
518 // SSE/AVX/AVX512F chain.
519 constexpr FeatureBitset ImpliedFeaturesSSE = {};
520 constexpr FeatureBitset ImpliedFeaturesSSE2 = FeatureSSE;
521 constexpr FeatureBitset ImpliedFeaturesSSE3 = FeatureSSE2;
522 constexpr FeatureBitset ImpliedFeaturesSSSE3 = FeatureSSE3;
523 constexpr FeatureBitset ImpliedFeaturesSSE4_1 = FeatureSSSE3;
524 constexpr FeatureBitset ImpliedFeaturesSSE4_2 = FeatureSSE4_1;
525 constexpr FeatureBitset ImpliedFeaturesAVX = FeatureSSE4_2;
526 constexpr FeatureBitset ImpliedFeaturesAVX2 = FeatureAVX;
527 constexpr FeatureBitset ImpliedFeaturesAVX512F =
528     FeatureAVX2 | FeatureF16C | FeatureFMA;
529 
530 // Vector extensions that build on SSE or AVX.
531 constexpr FeatureBitset ImpliedFeaturesAES = FeatureSSE2;
532 constexpr FeatureBitset ImpliedFeaturesF16C = FeatureAVX;
533 constexpr FeatureBitset ImpliedFeaturesFMA = FeatureAVX;
534 constexpr FeatureBitset ImpliedFeaturesGFNI = FeatureSSE2;
535 constexpr FeatureBitset ImpliedFeaturesPCLMUL = FeatureSSE2;
536 constexpr FeatureBitset ImpliedFeaturesSHA = FeatureSSE2;
537 constexpr FeatureBitset ImpliedFeaturesVAES = FeatureAES | FeatureAVX;
538 constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ = FeatureAVX | FeaturePCLMUL;
539 
540 // AVX512 features.
541 constexpr FeatureBitset ImpliedFeaturesAVX512CD = FeatureAVX512F;
542 constexpr FeatureBitset ImpliedFeaturesAVX512BW = FeatureAVX512F;
543 constexpr FeatureBitset ImpliedFeaturesAVX512DQ = FeatureAVX512F;
544 constexpr FeatureBitset ImpliedFeaturesAVX512ER = FeatureAVX512F;
545 constexpr FeatureBitset ImpliedFeaturesAVX512PF = FeatureAVX512F;
546 constexpr FeatureBitset ImpliedFeaturesAVX512VL = FeatureAVX512F;
547 
548 constexpr FeatureBitset ImpliedFeaturesAVX512BF16 = FeatureAVX512BW;
549 constexpr FeatureBitset ImpliedFeaturesAVX512BITALG = FeatureAVX512BW;
550 constexpr FeatureBitset ImpliedFeaturesAVX512IFMA = FeatureAVX512F;
551 constexpr FeatureBitset ImpliedFeaturesAVX512VNNI = FeatureAVX512F;
552 constexpr FeatureBitset ImpliedFeaturesAVX512VPOPCNTDQ = FeatureAVX512F;
553 constexpr FeatureBitset ImpliedFeaturesAVX512VBMI = FeatureAVX512BW;
554 constexpr FeatureBitset ImpliedFeaturesAVX512VBMI2 = FeatureAVX512BW;
555 constexpr FeatureBitset ImpliedFeaturesAVX512VP2INTERSECT = FeatureAVX512F;
556 
557 // FIXME: These two aren't really implemented and just exist in the feature
558 // list for __builtin_cpu_supports. So omit their dependencies.
559 constexpr FeatureBitset ImpliedFeaturesAVX5124FMAPS = {};
560 constexpr FeatureBitset ImpliedFeaturesAVX5124VNNIW = {};
561 
562 // SSE4_A->FMA4->XOP chain.
563 constexpr FeatureBitset ImpliedFeaturesSSE4_A = FeatureSSE3;
564 constexpr FeatureBitset ImpliedFeaturesFMA4 = FeatureAVX | FeatureSSE4_A;
565 constexpr FeatureBitset ImpliedFeaturesXOP = FeatureFMA4;
566 
567 // AMX Features
568 constexpr FeatureBitset ImpliedFeaturesAMX_TILE = {};
569 constexpr FeatureBitset ImpliedFeaturesAMX_BF16 = FeatureAMX_TILE;
570 constexpr FeatureBitset ImpliedFeaturesAMX_INT8 = FeatureAMX_TILE;
571 constexpr FeatureBitset ImpliedFeaturesHRESET = {};
572 
573 // Key Locker Features
574 constexpr FeatureBitset ImpliedFeaturesKL = FeatureSSE2;
575 constexpr FeatureBitset ImpliedFeaturesWIDEKL = FeatureKL;
576 
577 // AVXVNNI Features
578 constexpr FeatureBitset ImpliedFeaturesAVXVNNI = FeatureAVX2;
579 
580 constexpr FeatureInfo FeatureInfos[X86::CPU_FEATURE_MAX] = {
581 #define X86_FEATURE(ENUM, STR) {{STR}, ImpliedFeatures##ENUM},
582 #include "llvm/Support/X86TargetParser.def"
583 };
584 
getFeaturesForCPU(StringRef CPU,SmallVectorImpl<StringRef> & EnabledFeatures)585 void llvm::X86::getFeaturesForCPU(StringRef CPU,
586                                   SmallVectorImpl<StringRef> &EnabledFeatures) {
587   auto I = llvm::find_if(Processors,
588                          [&](const ProcInfo &P) { return P.Name == CPU; });
589   assert(I != std::end(Processors) && "Processor not found!");
590 
591   FeatureBitset Bits = I->Features;
592 
593   // Remove the 64-bit feature which we only use to validate if a CPU can
594   // be used with 64-bit mode.
595   Bits &= ~Feature64BIT;
596 
597   // Add the string version of all set bits.
598   for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
599     if (Bits[i] && !FeatureInfos[i].Name.empty())
600       EnabledFeatures.push_back(FeatureInfos[i].Name);
601 }
602 
603 // For each feature that is (transitively) implied by this feature, set it.
getImpliedEnabledFeatures(FeatureBitset & Bits,const FeatureBitset & Implies)604 static void getImpliedEnabledFeatures(FeatureBitset &Bits,
605                                       const FeatureBitset &Implies) {
606   // Fast path: Implies is often empty.
607   if (!Implies.any())
608     return;
609   FeatureBitset Prev;
610   Bits |= Implies;
611   do {
612     Prev = Bits;
613     for (unsigned i = CPU_FEATURE_MAX; i;)
614       if (Bits[--i])
615         Bits |= FeatureInfos[i].ImpliedFeatures;
616   } while (Prev != Bits);
617 }
618 
619 /// Create bit vector of features that are implied disabled if the feature
620 /// passed in Value is disabled.
getImpliedDisabledFeatures(FeatureBitset & Bits,unsigned Value)621 static void getImpliedDisabledFeatures(FeatureBitset &Bits, unsigned Value) {
622   // Check all features looking for any dependent on this feature. If we find
623   // one, mark it and recursively find any feature that depend on it.
624   FeatureBitset Prev;
625   Bits.set(Value);
626   do {
627     Prev = Bits;
628     for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
629       if ((FeatureInfos[i].ImpliedFeatures & Bits).any())
630         Bits.set(i);
631   } while (Prev != Bits);
632 }
633 
updateImpliedFeatures(StringRef Feature,bool Enabled,StringMap<bool> & Features)634 void llvm::X86::updateImpliedFeatures(
635     StringRef Feature, bool Enabled,
636     StringMap<bool> &Features) {
637   auto I = llvm::find_if(
638       FeatureInfos, [&](const FeatureInfo &FI) { return FI.Name == Feature; });
639   if (I == std::end(FeatureInfos)) {
640     // FIXME: This shouldn't happen, but may not have all features in the table
641     // yet.
642     return;
643   }
644 
645   FeatureBitset ImpliedBits;
646   if (Enabled)
647     getImpliedEnabledFeatures(ImpliedBits, I->ImpliedFeatures);
648   else
649     getImpliedDisabledFeatures(ImpliedBits,
650                                std::distance(std::begin(FeatureInfos), I));
651 
652   // Update the map entry for all implied features.
653   for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
654     if (ImpliedBits[i] && !FeatureInfos[i].Name.empty())
655       Features[FeatureInfos[i].Name] = Enabled;
656 }
657