1//===- X86InstrFPStack.td - FPU Instruction Set ------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the X86 x87 FPU instruction set, defining the 10// instructions, and properties of the instructions which are needed for code 11// generation, machine code emission, and analysis. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// FPStack specific DAG Nodes. 17//===----------------------------------------------------------------------===// 18 19def SDTX86Fld : SDTypeProfile<1, 1, [SDTCisFP<0>, 20 SDTCisPtrTy<1>]>; 21def SDTX86Fst : SDTypeProfile<0, 2, [SDTCisFP<0>, 22 SDTCisPtrTy<1>]>; 23def SDTX86Fild : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisPtrTy<1>]>; 24def SDTX86Fist : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>; 25 26def SDTX86CwdStore : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 27 28def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld, 29 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 30def X86fst : SDNode<"X86ISD::FST", SDTX86Fst, 31 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 32def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild, 33 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 34def X86fist : SDNode<"X86ISD::FIST", SDTX86Fist, 35 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 36def X86fp_to_mem : SDNode<"X86ISD::FP_TO_INT_IN_MEM", SDTX86Fst, 37 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 38def X86fp_cwd_get16 : SDNode<"X86ISD::FNSTCW16m", SDTX86CwdStore, 39 [SDNPHasChain, SDNPMayStore, SDNPSideEffect, 40 SDNPMemOperand]>; 41 42def X86fstf32 : PatFrag<(ops node:$val, node:$ptr), 43 (X86fst node:$val, node:$ptr), [{ 44 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f32; 45}]>; 46def X86fstf64 : PatFrag<(ops node:$val, node:$ptr), 47 (X86fst node:$val, node:$ptr), [{ 48 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f64; 49}]>; 50def X86fstf80 : PatFrag<(ops node:$val, node:$ptr), 51 (X86fst node:$val, node:$ptr), [{ 52 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f80; 53}]>; 54 55def X86fldf32 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{ 56 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f32; 57}]>; 58def X86fldf64 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{ 59 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f64; 60}]>; 61def X86fldf80 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{ 62 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f80; 63}]>; 64 65def X86fild16 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{ 66 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 67}]>; 68def X86fild32 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{ 69 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 70}]>; 71def X86fild64 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{ 72 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64; 73}]>; 74 75def X86fist32 : PatFrag<(ops node:$val, node:$ptr), 76 (X86fist node:$val, node:$ptr), [{ 77 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 78}]>; 79 80def X86fist64 : PatFrag<(ops node:$val, node:$ptr), 81 (X86fist node:$val, node:$ptr), [{ 82 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64; 83}]>; 84 85def X86fp_to_i16mem : PatFrag<(ops node:$val, node:$ptr), 86 (X86fp_to_mem node:$val, node:$ptr), [{ 87 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 88}]>; 89def X86fp_to_i32mem : PatFrag<(ops node:$val, node:$ptr), 90 (X86fp_to_mem node:$val, node:$ptr), [{ 91 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 92}]>; 93def X86fp_to_i64mem : PatFrag<(ops node:$val, node:$ptr), 94 (X86fp_to_mem node:$val, node:$ptr), [{ 95 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64; 96}]>; 97 98//===----------------------------------------------------------------------===// 99// FPStack pattern fragments 100//===----------------------------------------------------------------------===// 101 102def fpimm0 : FPImmLeaf<fAny, [{ 103 return Imm.isExactlyValue(+0.0); 104}]>; 105 106def fpimmneg0 : FPImmLeaf<fAny, [{ 107 return Imm.isExactlyValue(-0.0); 108}]>; 109 110def fpimm1 : FPImmLeaf<fAny, [{ 111 return Imm.isExactlyValue(+1.0); 112}]>; 113 114def fpimmneg1 : FPImmLeaf<fAny, [{ 115 return Imm.isExactlyValue(-1.0); 116}]>; 117 118// Some 'special' instructions - expanded after instruction selection. 119// Clobbers EFLAGS due to OR instruction used internally. 120// FIXME: Can we model this in SelectionDAG? 121let usesCustomInserter = 1, hasNoSchedulingInfo = 1, Defs = [EFLAGS] in { 122 def FP32_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP32:$src), 123 [(X86fp_to_i16mem RFP32:$src, addr:$dst)]>; 124 def FP32_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP32:$src), 125 [(X86fp_to_i32mem RFP32:$src, addr:$dst)]>; 126 def FP32_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP32:$src), 127 [(X86fp_to_i64mem RFP32:$src, addr:$dst)]>; 128 def FP64_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP64:$src), 129 [(X86fp_to_i16mem RFP64:$src, addr:$dst)]>; 130 def FP64_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP64:$src), 131 [(X86fp_to_i32mem RFP64:$src, addr:$dst)]>; 132 def FP64_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP64:$src), 133 [(X86fp_to_i64mem RFP64:$src, addr:$dst)]>; 134 def FP80_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP80:$src), 135 [(X86fp_to_i16mem RFP80:$src, addr:$dst)]>; 136 def FP80_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP80:$src), 137 [(X86fp_to_i32mem RFP80:$src, addr:$dst)]>; 138 def FP80_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP80:$src), 139 [(X86fp_to_i64mem RFP80:$src, addr:$dst)]>; 140} 141 142// All FP Stack operations are represented with four instructions here. The 143// first three instructions, generated by the instruction selector, use "RFP32" 144// "RFP64" or "RFP80" registers: traditional register files to reference 32-bit, 145// 64-bit or 80-bit floating point values. These sizes apply to the values, 146// not the registers, which are always 80 bits; RFP32, RFP64 and RFP80 can be 147// copied to each other without losing information. These instructions are all 148// pseudo instructions and use the "_Fp" suffix. 149// In some cases there are additional variants with a mixture of different 150// register sizes. 151// The second instruction is defined with FPI, which is the actual instruction 152// emitted by the assembler. These use "RST" registers, although frequently 153// the actual register(s) used are implicit. These are always 80 bits. 154// The FP stackifier pass converts one to the other after register allocation 155// occurs. 156// 157// Note that the FpI instruction should have instruction selection info (e.g. 158// a pattern) and the FPI instruction should have emission info (e.g. opcode 159// encoding and asm printing info). 160 161// FpIf32, FpIf64 - Floating Point Pseudo Instruction template. 162// f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1. 163// f64 instructions can use SSE2 and are predicated on FPStackf64 == !SSE2. 164// f80 instructions cannot use SSE and use neither of these. 165class FpIf32<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 166 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32]>; 167class FpIf64<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 168 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64]>; 169 170// Factoring for arithmetic. 171multiclass FPBinary_rr<SDNode OpNode> { 172// Register op register -> register 173// These are separated out because they have no reversed form. 174def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), TwoArgFP, 175 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>; 176def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), TwoArgFP, 177 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>; 178def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), TwoArgFP, 179 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>; 180} 181// The FopST0 series are not included here because of the irregularities 182// in where the 'r' goes in assembly output. 183// These instructions cannot address 80-bit memory. 184multiclass FPBinary<SDNode OpNode, Format fp, string asmstring, 185 bit Forward = 1> { 186// ST(0) = ST(0) + [mem] 187def _Fp32m : FpIf32<(outs RFP32:$dst), 188 (ins RFP32:$src1, f32mem:$src2), OneArgFPRW, 189 [!if(Forward, 190 (set RFP32:$dst, 191 (OpNode RFP32:$src1, (loadf32 addr:$src2))), 192 (set RFP32:$dst, 193 (OpNode (loadf32 addr:$src2), RFP32:$src1)))]>; 194def _Fp64m : FpIf64<(outs RFP64:$dst), 195 (ins RFP64:$src1, f64mem:$src2), OneArgFPRW, 196 [!if(Forward, 197 (set RFP64:$dst, 198 (OpNode RFP64:$src1, (loadf64 addr:$src2))), 199 (set RFP64:$dst, 200 (OpNode (loadf64 addr:$src2), RFP64:$src1)))]>; 201def _Fp64m32: FpIf64<(outs RFP64:$dst), 202 (ins RFP64:$src1, f32mem:$src2), OneArgFPRW, 203 [!if(Forward, 204 (set RFP64:$dst, 205 (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2)))), 206 (set RFP64:$dst, 207 (OpNode (f64 (extloadf32 addr:$src2)), RFP64:$src1)))]>; 208def _Fp80m32: FpI_<(outs RFP80:$dst), 209 (ins RFP80:$src1, f32mem:$src2), OneArgFPRW, 210 [!if(Forward, 211 (set RFP80:$dst, 212 (OpNode RFP80:$src1, (f80 (extloadf32 addr:$src2)))), 213 (set RFP80:$dst, 214 (OpNode (f80 (extloadf32 addr:$src2)), RFP80:$src1)))]>; 215def _Fp80m64: FpI_<(outs RFP80:$dst), 216 (ins RFP80:$src1, f64mem:$src2), OneArgFPRW, 217 [!if(Forward, 218 (set RFP80:$dst, 219 (OpNode RFP80:$src1, (f80 (extloadf64 addr:$src2)))), 220 (set RFP80:$dst, 221 (OpNode (f80 (extloadf64 addr:$src2)), RFP80:$src1)))]>; 222let mayLoad = 1 in 223def _F32m : FPI<0xD8, fp, (outs), (ins f32mem:$src), 224 !strconcat("f", asmstring, "{s}\t$src")>; 225let mayLoad = 1 in 226def _F64m : FPI<0xDC, fp, (outs), (ins f64mem:$src), 227 !strconcat("f", asmstring, "{l}\t$src")>; 228// ST(0) = ST(0) + [memint] 229def _FpI16m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i16mem:$src2), 230 OneArgFPRW, 231 [!if(Forward, 232 (set RFP32:$dst, 233 (OpNode RFP32:$src1, (X86fild16 addr:$src2))), 234 (set RFP32:$dst, 235 (OpNode (X86fild16 addr:$src2), RFP32:$src1)))]>; 236def _FpI32m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i32mem:$src2), 237 OneArgFPRW, 238 [!if(Forward, 239 (set RFP32:$dst, 240 (OpNode RFP32:$src1, (X86fild32 addr:$src2))), 241 (set RFP32:$dst, 242 (OpNode (X86fild32 addr:$src2), RFP32:$src1)))]>; 243def _FpI16m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i16mem:$src2), 244 OneArgFPRW, 245 [!if(Forward, 246 (set RFP64:$dst, 247 (OpNode RFP64:$src1, (X86fild16 addr:$src2))), 248 (set RFP64:$dst, 249 (OpNode (X86fild16 addr:$src2), RFP64:$src1)))]>; 250def _FpI32m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i32mem:$src2), 251 OneArgFPRW, 252 [!if(Forward, 253 (set RFP64:$dst, 254 (OpNode RFP64:$src1, (X86fild32 addr:$src2))), 255 (set RFP64:$dst, 256 (OpNode (X86fild32 addr:$src2), RFP64:$src1)))]>; 257def _FpI16m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i16mem:$src2), 258 OneArgFPRW, 259 [!if(Forward, 260 (set RFP80:$dst, 261 (OpNode RFP80:$src1, (X86fild16 addr:$src2))), 262 (set RFP80:$dst, 263 (OpNode (X86fild16 addr:$src2), RFP80:$src1)))]>; 264def _FpI32m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i32mem:$src2), 265 OneArgFPRW, 266 [!if(Forward, 267 (set RFP80:$dst, 268 (OpNode RFP80:$src1, (X86fild32 addr:$src2))), 269 (set RFP80:$dst, 270 (OpNode (X86fild32 addr:$src2), RFP80:$src1)))]>; 271let mayLoad = 1 in 272def _FI16m : FPI<0xDE, fp, (outs), (ins i16mem:$src), 273 !strconcat("fi", asmstring, "{s}\t$src")>; 274let mayLoad = 1 in 275def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src), 276 !strconcat("fi", asmstring, "{l}\t$src")>; 277} 278 279let Uses = [FPCW], mayRaiseFPException = 1 in { 280// FPBinary_rr just defines pseudo-instructions, no need to set a scheduling 281// resources. 282let hasNoSchedulingInfo = 1 in { 283defm ADD : FPBinary_rr<any_fadd>; 284defm SUB : FPBinary_rr<any_fsub>; 285defm MUL : FPBinary_rr<any_fmul>; 286defm DIV : FPBinary_rr<any_fdiv>; 287} 288 289// Sets the scheduling resources for the actual NAME#_F<size>m definitions. 290let SchedRW = [WriteFAddLd] in { 291defm ADD : FPBinary<any_fadd, MRM0m, "add">; 292defm SUB : FPBinary<any_fsub, MRM4m, "sub">; 293defm SUBR: FPBinary<any_fsub ,MRM5m, "subr", 0>; 294} 295 296let SchedRW = [WriteFMulLd] in { 297defm MUL : FPBinary<any_fmul, MRM1m, "mul">; 298} 299 300let SchedRW = [WriteFDivLd] in { 301defm DIV : FPBinary<any_fdiv, MRM6m, "div">; 302defm DIVR: FPBinary<any_fdiv, MRM7m, "divr", 0>; 303} 304} // Uses = [FPCW], mayRaiseFPException = 1 305 306class FPST0rInst<Format fp, string asm> 307 : FPI<0xD8, fp, (outs), (ins RSTi:$op), asm>; 308class FPrST0Inst<Format fp, string asm> 309 : FPI<0xDC, fp, (outs), (ins RSTi:$op), asm>; 310class FPrST0PInst<Format fp, string asm> 311 : FPI<0xDE, fp, (outs), (ins RSTi:$op), asm>; 312 313// NOTE: GAS and apparently all other AT&T style assemblers have a broken notion 314// of some of the 'reverse' forms of the fsub and fdiv instructions. As such, 315// we have to put some 'r's in and take them out of weird places. 316let SchedRW = [WriteFAdd], Uses = [FPCW], mayRaiseFPException = 1 in { 317def ADD_FST0r : FPST0rInst <MRM0r, "fadd\t{$op, %st|st, $op}">; 318def ADD_FrST0 : FPrST0Inst <MRM0r, "fadd\t{%st, $op|$op, st}">; 319def ADD_FPrST0 : FPrST0PInst<MRM0r, "faddp\t{%st, $op|$op, st}">; 320def SUBR_FST0r : FPST0rInst <MRM5r, "fsubr\t{$op, %st|st, $op}">; 321def SUB_FrST0 : FPrST0Inst <MRM5r, "fsub{r}\t{%st, $op|$op, st}">; 322def SUB_FPrST0 : FPrST0PInst<MRM5r, "fsub{r}p\t{%st, $op|$op, st}">; 323def SUB_FST0r : FPST0rInst <MRM4r, "fsub\t{$op, %st|st, $op}">; 324def SUBR_FrST0 : FPrST0Inst <MRM4r, "fsub{|r}\t{%st, $op|$op, st}">; 325def SUBR_FPrST0 : FPrST0PInst<MRM4r, "fsub{|r}p\t{%st, $op|$op, st}">; 326} // SchedRW 327let SchedRW = [WriteFCom], Uses = [FPCW], mayRaiseFPException = 1 in { 328def COM_FST0r : FPST0rInst <MRM2r, "fcom\t$op">; 329def COMP_FST0r : FPST0rInst <MRM3r, "fcomp\t$op">; 330} // SchedRW 331let SchedRW = [WriteFMul], Uses = [FPCW], mayRaiseFPException = 1 in { 332def MUL_FST0r : FPST0rInst <MRM1r, "fmul\t{$op, %st|st, $op}">; 333def MUL_FrST0 : FPrST0Inst <MRM1r, "fmul\t{%st, $op|$op, st}">; 334def MUL_FPrST0 : FPrST0PInst<MRM1r, "fmulp\t{%st, $op|$op, st}">; 335} // SchedRW 336let SchedRW = [WriteFDiv], Uses = [FPCW], mayRaiseFPException = 1 in { 337def DIVR_FST0r : FPST0rInst <MRM7r, "fdivr\t{$op, %st|st, $op}">; 338def DIV_FrST0 : FPrST0Inst <MRM7r, "fdiv{r}\t{%st, $op|$op, st}">; 339def DIV_FPrST0 : FPrST0PInst<MRM7r, "fdiv{r}p\t{%st, $op|$op, st}">; 340def DIV_FST0r : FPST0rInst <MRM6r, "fdiv\t{$op, %st|st, $op}">; 341def DIVR_FrST0 : FPrST0Inst <MRM6r, "fdiv{|r}\t{%st, $op|$op, st}">; 342def DIVR_FPrST0 : FPrST0PInst<MRM6r, "fdiv{|r}p\t{%st, $op|$op, st}">; 343} // SchedRW 344 345// Unary operations. 346multiclass FPUnary<SDNode OpNode, Format fp, string asmstring> { 347def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW, 348 [(set RFP32:$dst, (OpNode RFP32:$src))]>; 349def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), OneArgFPRW, 350 [(set RFP64:$dst, (OpNode RFP64:$src))]>; 351def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW, 352 [(set RFP80:$dst, (OpNode RFP80:$src))]>; 353def _F : FPI<0xD9, fp, (outs), (ins), asmstring>; 354} 355 356let SchedRW = [WriteFSign] in { 357defm CHS : FPUnary<fneg, MRM_E0, "fchs">; 358defm ABS : FPUnary<fabs, MRM_E1, "fabs">; 359} 360 361let Uses = [FPCW], mayRaiseFPException = 1 in { 362let SchedRW = [WriteFSqrt80] in 363defm SQRT: FPUnary<any_fsqrt,MRM_FA, "fsqrt">; 364 365let SchedRW = [WriteFCom] in { 366let hasSideEffects = 0 in { 367def TST_Fp32 : FpIf32<(outs), (ins RFP32:$src), OneArgFP, []>; 368def TST_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP, []>; 369def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>; 370} // hasSideEffects 371 372def TST_F : FPI<0xD9, MRM_E4, (outs), (ins), "ftst">; 373} // SchedRW 374} // Uses = [FPCW], mayRaiseFPException = 1 375 376// Versions of FP instructions that take a single memory operand. Added for the 377// disassembler; remove as they are included with patterns elsewhere. 378let SchedRW = [WriteFComLd], Uses = [FPCW], mayRaiseFPException = 1, 379 mayLoad = 1 in { 380def FCOM32m : FPI<0xD8, MRM2m, (outs), (ins f32mem:$src), "fcom{s}\t$src">; 381def FCOMP32m : FPI<0xD8, MRM3m, (outs), (ins f32mem:$src), "fcomp{s}\t$src">; 382 383def FCOM64m : FPI<0xDC, MRM2m, (outs), (ins f64mem:$src), "fcom{l}\t$src">; 384def FCOMP64m : FPI<0xDC, MRM3m, (outs), (ins f64mem:$src), "fcomp{l}\t$src">; 385 386def FICOM16m : FPI<0xDE, MRM2m, (outs), (ins i16mem:$src), "ficom{s}\t$src">; 387def FICOMP16m: FPI<0xDE, MRM3m, (outs), (ins i16mem:$src), "ficomp{s}\t$src">; 388 389def FICOM32m : FPI<0xDA, MRM2m, (outs), (ins i32mem:$src), "ficom{l}\t$src">; 390def FICOMP32m: FPI<0xDA, MRM3m, (outs), (ins i32mem:$src), "ficomp{l}\t$src">; 391} // SchedRW 392 393let SchedRW = [WriteMicrocoded] in { 394let Defs = [FPSW, FPCW], mayLoad = 1 in { 395def FLDENVm : FPI<0xD9, MRM4m, (outs), (ins anymem:$src), "fldenv\t$src">; 396def FRSTORm : FPI<0xDD, MRM4m, (outs), (ins anymem:$src), "frstor\t$src">; 397} 398 399let Defs = [FPSW, FPCW], Uses = [FPSW, FPCW], mayStore = 1 in { 400def FSTENVm : FPI<0xD9, MRM6m, (outs), (ins anymem:$dst), "fnstenv\t$dst">; 401def FSAVEm : FPI<0xDD, MRM6m, (outs), (ins anymem:$dst), "fnsave\t$dst">; 402} 403 404let Uses = [FPSW], mayStore = 1 in 405def FNSTSWm : FPI<0xDD, MRM7m, (outs), (ins i16mem:$dst), "fnstsw\t$dst">; 406 407let mayLoad = 1 in 408def FBLDm : FPI<0xDF, MRM4m, (outs), (ins f80mem:$src), "fbld\t$src">; 409let Uses = [FPCW] ,mayRaiseFPException = 1, mayStore = 1 in 410def FBSTPm : FPI<0xDF, MRM6m, (outs), (ins f80mem:$dst), "fbstp\t$dst">; 411} // SchedRW 412 413// Floating point cmovs. 414class FpIf32CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 415 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32, HasCMov]>; 416class FpIf64CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 417 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64, HasCMov]>; 418 419multiclass FPCMov<PatLeaf cc> { 420 def _Fp32 : FpIf32CMov<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), 421 CondMovFP, 422 [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, 423 cc, EFLAGS))]>; 424 def _Fp64 : FpIf64CMov<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), 425 CondMovFP, 426 [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, 427 cc, EFLAGS))]>; 428 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), 429 CondMovFP, 430 [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2, 431 cc, EFLAGS))]>, 432 Requires<[HasCMov]>; 433} 434 435let SchedRW = [WriteFCMOV] in { 436let Uses = [EFLAGS], Constraints = "$src1 = $dst" in { 437defm CMOVB : FPCMov<X86_COND_B>; 438defm CMOVBE : FPCMov<X86_COND_BE>; 439defm CMOVE : FPCMov<X86_COND_E>; 440defm CMOVP : FPCMov<X86_COND_P>; 441defm CMOVNB : FPCMov<X86_COND_AE>; 442defm CMOVNBE: FPCMov<X86_COND_A>; 443defm CMOVNE : FPCMov<X86_COND_NE>; 444defm CMOVNP : FPCMov<X86_COND_NP>; 445} // Uses = [EFLAGS], Constraints = "$src1 = $dst" 446 447let Predicates = [HasCMov] in { 448// These are not factored because there's no clean way to pass DA/DB. 449def CMOVB_F : FPI<0xDA, MRM0r, (outs), (ins RSTi:$op), 450 "fcmovb\t{$op, %st|st, $op}">; 451def CMOVBE_F : FPI<0xDA, MRM2r, (outs), (ins RSTi:$op), 452 "fcmovbe\t{$op, %st|st, $op}">; 453def CMOVE_F : FPI<0xDA, MRM1r, (outs), (ins RSTi:$op), 454 "fcmove\t{$op, %st|st, $op}">; 455def CMOVP_F : FPI<0xDA, MRM3r, (outs), (ins RSTi:$op), 456 "fcmovu\t{$op, %st|st, $op}">; 457def CMOVNB_F : FPI<0xDB, MRM0r, (outs), (ins RSTi:$op), 458 "fcmovnb\t{$op, %st|st, $op}">; 459def CMOVNBE_F: FPI<0xDB, MRM2r, (outs), (ins RSTi:$op), 460 "fcmovnbe\t{$op, %st|st, $op}">; 461def CMOVNE_F : FPI<0xDB, MRM1r, (outs), (ins RSTi:$op), 462 "fcmovne\t{$op, %st|st, $op}">; 463def CMOVNP_F : FPI<0xDB, MRM3r, (outs), (ins RSTi:$op), 464 "fcmovnu\t{$op, %st|st, $op}">; 465} // Predicates = [HasCMov] 466} // SchedRW 467 468let mayRaiseFPException = 1 in { 469// Floating point loads & stores. 470let SchedRW = [WriteLoad], Uses = [FPCW] in { 471let canFoldAsLoad = 1 in { 472def LD_Fp32m : FpIf32<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP, 473 [(set RFP32:$dst, (loadf32 addr:$src))]>; 474def LD_Fp64m : FpIf64<(outs RFP64:$dst), (ins f64mem:$src), ZeroArgFP, 475 [(set RFP64:$dst, (loadf64 addr:$src))]>; 476def LD_Fp80m : FpI_<(outs RFP80:$dst), (ins f80mem:$src), ZeroArgFP, 477 [(set RFP80:$dst, (loadf80 addr:$src))]>; 478} // canFoldAsLoad 479def LD_Fp32m64 : FpIf64<(outs RFP64:$dst), (ins f32mem:$src), ZeroArgFP, 480 [(set RFP64:$dst, (f64 (extloadf32 addr:$src)))]>; 481def LD_Fp64m80 : FpI_<(outs RFP80:$dst), (ins f64mem:$src), ZeroArgFP, 482 [(set RFP80:$dst, (f80 (extloadf64 addr:$src)))]>; 483def LD_Fp32m80 : FpI_<(outs RFP80:$dst), (ins f32mem:$src), ZeroArgFP, 484 [(set RFP80:$dst, (f80 (extloadf32 addr:$src)))]>; 485let mayRaiseFPException = 0 in { 486def ILD_Fp16m32: FpIf32<(outs RFP32:$dst), (ins i16mem:$src), ZeroArgFP, 487 [(set RFP32:$dst, (X86fild16 addr:$src))]>; 488def ILD_Fp32m32: FpIf32<(outs RFP32:$dst), (ins i32mem:$src), ZeroArgFP, 489 [(set RFP32:$dst, (X86fild32 addr:$src))]>; 490def ILD_Fp64m32: FpIf32<(outs RFP32:$dst), (ins i64mem:$src), ZeroArgFP, 491 [(set RFP32:$dst, (X86fild64 addr:$src))]>; 492def ILD_Fp16m64: FpIf64<(outs RFP64:$dst), (ins i16mem:$src), ZeroArgFP, 493 [(set RFP64:$dst, (X86fild16 addr:$src))]>; 494def ILD_Fp32m64: FpIf64<(outs RFP64:$dst), (ins i32mem:$src), ZeroArgFP, 495 [(set RFP64:$dst, (X86fild32 addr:$src))]>; 496def ILD_Fp64m64: FpIf64<(outs RFP64:$dst), (ins i64mem:$src), ZeroArgFP, 497 [(set RFP64:$dst, (X86fild64 addr:$src))]>; 498def ILD_Fp16m80: FpI_<(outs RFP80:$dst), (ins i16mem:$src), ZeroArgFP, 499 [(set RFP80:$dst, (X86fild16 addr:$src))]>; 500def ILD_Fp32m80: FpI_<(outs RFP80:$dst), (ins i32mem:$src), ZeroArgFP, 501 [(set RFP80:$dst, (X86fild32 addr:$src))]>; 502def ILD_Fp64m80: FpI_<(outs RFP80:$dst), (ins i64mem:$src), ZeroArgFP, 503 [(set RFP80:$dst, (X86fild64 addr:$src))]>; 504} // mayRaiseFPException = 0 505} // SchedRW 506 507let SchedRW = [WriteStore], Uses = [FPCW] in { 508def ST_Fp32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, 509 [(store RFP32:$src, addr:$op)]>; 510def ST_Fp64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, 511 [(truncstoref32 RFP64:$src, addr:$op)]>; 512def ST_Fp64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, 513 [(store RFP64:$src, addr:$op)]>; 514def ST_Fp80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, 515 [(truncstoref32 RFP80:$src, addr:$op)]>; 516def ST_Fp80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, 517 [(truncstoref64 RFP80:$src, addr:$op)]>; 518// FST does not support 80-bit memory target; FSTP must be used. 519 520let mayStore = 1, hasSideEffects = 0 in { 521def ST_FpP32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, []>; 522def ST_FpP64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>; 523def ST_FpP64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>; 524def ST_FpP80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, []>; 525def ST_FpP80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, []>; 526} // mayStore 527 528def ST_FpP80m : FpI_<(outs), (ins f80mem:$op, RFP80:$src), OneArgFP, 529 [(store RFP80:$src, addr:$op)]>; 530 531let mayStore = 1, hasSideEffects = 0 in { 532def IST_Fp16m32 : FpIf32<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>; 533def IST_Fp32m32 : FpIf32<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, 534 [(X86fist32 RFP32:$src, addr:$op)]>; 535def IST_Fp64m32 : FpIf32<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, 536 [(X86fist64 RFP32:$src, addr:$op)]>; 537def IST_Fp16m64 : FpIf64<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, []>; 538def IST_Fp32m64 : FpIf64<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, 539 [(X86fist32 RFP64:$src, addr:$op)]>; 540def IST_Fp64m64 : FpIf64<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, 541 [(X86fist64 RFP64:$src, addr:$op)]>; 542def IST_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, []>; 543def IST_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, 544 [(X86fist32 RFP80:$src, addr:$op)]>; 545def IST_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, 546 [(X86fist64 RFP80:$src, addr:$op)]>; 547} // mayStore 548} // SchedRW, Uses = [FPCW] 549 550let mayLoad = 1, SchedRW = [WriteLoad], Uses = [FPCW] in { 551def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src">; 552def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src">; 553def LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src">; 554let mayRaiseFPException = 0 in { 555def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src">; 556def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src">; 557def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src">; 558} 559} 560let mayStore = 1, SchedRW = [WriteStore], Uses = [FPCW] in { 561def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst">; 562def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst">; 563def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst">; 564def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst">; 565def ST_FP80m : FPI<0xDB, MRM7m, (outs), (ins f80mem:$dst), "fstp{t}\t$dst">; 566def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst">; 567def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst">; 568def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s}\t$dst">; 569def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l}\t$dst">; 570def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst">; 571} 572 573// FISTTP requires SSE3 even though it's a FPStack op. 574let Predicates = [HasSSE3], SchedRW = [WriteStore], Uses = [FPCW] in { 575def ISTT_Fp16m32 : FpI_<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, 576 [(X86fp_to_i16mem RFP32:$src, addr:$op)]>; 577def ISTT_Fp32m32 : FpI_<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, 578 [(X86fp_to_i32mem RFP32:$src, addr:$op)]>; 579def ISTT_Fp64m32 : FpI_<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, 580 [(X86fp_to_i64mem RFP32:$src, addr:$op)]>; 581def ISTT_Fp16m64 : FpI_<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, 582 [(X86fp_to_i16mem RFP64:$src, addr:$op)]>; 583def ISTT_Fp32m64 : FpI_<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, 584 [(X86fp_to_i32mem RFP64:$src, addr:$op)]>; 585def ISTT_Fp64m64 : FpI_<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, 586 [(X86fp_to_i64mem RFP64:$src, addr:$op)]>; 587def ISTT_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, 588 [(X86fp_to_i16mem RFP80:$src, addr:$op)]>; 589def ISTT_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, 590 [(X86fp_to_i32mem RFP80:$src, addr:$op)]>; 591def ISTT_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, 592 [(X86fp_to_i64mem RFP80:$src, addr:$op)]>; 593} // Predicates = [HasSSE3] 594 595let mayStore = 1, SchedRW = [WriteStore], Uses = [FPCW] in { 596def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst">; 597def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst">; 598def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), "fisttp{ll}\t$dst">; 599} 600 601// FP Stack manipulation instructions. 602let SchedRW = [WriteMove], Uses = [FPCW] in { 603def LD_Frr : FPI<0xD9, MRM0r, (outs), (ins RSTi:$op), "fld\t$op">; 604def ST_Frr : FPI<0xDD, MRM2r, (outs), (ins RSTi:$op), "fst\t$op">; 605def ST_FPrr : FPI<0xDD, MRM3r, (outs), (ins RSTi:$op), "fstp\t$op">; 606let mayRaiseFPException = 0 in 607def XCH_F : FPI<0xD9, MRM1r, (outs), (ins RSTi:$op), "fxch\t$op">; 608} 609 610// Floating point constant loads. 611let SchedRW = [WriteZero], Uses = [FPCW] in { 612def LD_Fp032 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP, 613 [(set RFP32:$dst, fpimm0)]>; 614def LD_Fp132 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP, 615 [(set RFP32:$dst, fpimm1)]>; 616def LD_Fp064 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP, 617 [(set RFP64:$dst, fpimm0)]>; 618def LD_Fp164 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP, 619 [(set RFP64:$dst, fpimm1)]>; 620def LD_Fp080 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP, 621 [(set RFP80:$dst, fpimm0)]>; 622def LD_Fp180 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP, 623 [(set RFP80:$dst, fpimm1)]>; 624} 625 626let SchedRW = [WriteFLD0], Uses = [FPCW], mayRaiseFPException = 0 in 627def LD_F0 : FPI<0xD9, MRM_EE, (outs), (ins), "fldz">; 628 629let SchedRW = [WriteFLD1], Uses = [FPCW], mayRaiseFPException = 0 in 630def LD_F1 : FPI<0xD9, MRM_E8, (outs), (ins), "fld1">; 631 632let SchedRW = [WriteFLDC], Defs = [FPSW], Uses = [FPCW], mayRaiseFPException = 0 in { 633def FLDL2T : I<0xD9, MRM_E9, (outs), (ins), "fldl2t", []>; 634def FLDL2E : I<0xD9, MRM_EA, (outs), (ins), "fldl2e", []>; 635def FLDPI : I<0xD9, MRM_EB, (outs), (ins), "fldpi", []>; 636def FLDLG2 : I<0xD9, MRM_EC, (outs), (ins), "fldlg2", []>; 637def FLDLN2 : I<0xD9, MRM_ED, (outs), (ins), "fldln2", []>; 638} // SchedRW 639 640// Floating point compares. 641let SchedRW = [WriteFCom], Uses = [FPCW], hasSideEffects = 0 in { 642def UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, []>; 643def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, []>; 644def UCOM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, []>; 645def COM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, []>; 646def COM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, []>; 647def COM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, []>; 648} // SchedRW 649} // mayRaiseFPException = 1 650 651let SchedRW = [WriteFCom], mayRaiseFPException = 1 in { 652// CC = ST(0) cmp ST(i) 653let Defs = [EFLAGS, FPSW], Uses = [FPCW] in { 654def UCOM_FpIr32: FpI_<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, 655 [(set EFLAGS, (X86any_fcmp RFP32:$lhs, RFP32:$rhs))]>, 656 Requires<[FPStackf32, HasCMov]>; 657def UCOM_FpIr64: FpI_<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, 658 [(set EFLAGS, (X86any_fcmp RFP64:$lhs, RFP64:$rhs))]>, 659 Requires<[FPStackf64, HasCMov]>; 660def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, 661 [(set EFLAGS, (X86any_fcmp RFP80:$lhs, RFP80:$rhs))]>, 662 Requires<[HasCMov]>; 663def COM_FpIr32: FpI_<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, 664 [(set EFLAGS, (X86strict_fcmps RFP32:$lhs, RFP32:$rhs))]>, 665 Requires<[FPStackf32, HasCMov]>; 666def COM_FpIr64: FpI_<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, 667 [(set EFLAGS, (X86strict_fcmps RFP64:$lhs, RFP64:$rhs))]>, 668 Requires<[FPStackf64, HasCMov]>; 669def COM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, 670 [(set EFLAGS, (X86strict_fcmps RFP80:$lhs, RFP80:$rhs))]>, 671 Requires<[HasCMov]>; 672} 673 674let Uses = [ST0, FPCW] in { 675def UCOM_Fr : FPI<0xDD, MRM4r, // FPSW = cmp ST(0) with ST(i) 676 (outs), (ins RSTi:$reg), "fucom\t$reg">; 677def UCOM_FPr : FPI<0xDD, MRM5r, // FPSW = cmp ST(0) with ST(i), pop 678 (outs), (ins RSTi:$reg), "fucomp\t$reg">; 679def UCOM_FPPr : FPI<0xDA, MRM_E9, // cmp ST(0) with ST(1), pop, pop 680 (outs), (ins), "fucompp">; 681} 682 683let Defs = [EFLAGS, FPSW], Uses = [ST0, FPCW] in { 684def UCOM_FIr : FPI<0xDB, MRM5r, // CC = cmp ST(0) with ST(i) 685 (outs), (ins RSTi:$reg), "fucomi\t{$reg, %st|st, $reg}">; 686def UCOM_FIPr : FPI<0xDF, MRM5r, // CC = cmp ST(0) with ST(i), pop 687 (outs), (ins RSTi:$reg), "fucompi\t{$reg, %st|st, $reg}">; 688 689def COM_FIr : FPI<0xDB, MRM6r, (outs), (ins RSTi:$reg), 690 "fcomi\t{$reg, %st|st, $reg}">; 691def COM_FIPr : FPI<0xDF, MRM6r, (outs), (ins RSTi:$reg), 692 "fcompi\t{$reg, %st|st, $reg}">; 693} 694} // SchedRW 695 696// Floating point flag ops. 697let SchedRW = [WriteALU] in { 698let Defs = [AX, FPSW], Uses = [FPSW], hasSideEffects = 0 in 699def FNSTSW16r : I<0xDF, MRM_E0, // AX = fp flags 700 (outs), (ins), "fnstsw\t{%ax|ax}", []>; 701let Defs = [FPSW], Uses = [FPCW] in 702def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world 703 (outs), (ins i16mem:$dst), "fnstcw\t$dst", 704 [(X86fp_cwd_get16 addr:$dst)]>; 705} // SchedRW 706let Defs = [FPSW,FPCW], mayLoad = 1 in 707def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16] 708 (outs), (ins i16mem:$dst), "fldcw\t$dst", []>, 709 Sched<[WriteLoad]>; 710 711// FPU control instructions 712let SchedRW = [WriteMicrocoded] in { 713def FFREE : FPI<0xDD, MRM0r, (outs), (ins RSTi:$reg), "ffree\t$reg">; 714def FFREEP : FPI<0xDF, MRM0r, (outs), (ins RSTi:$reg), "ffreep\t$reg">; 715 716let Defs = [FPSW, FPCW] in 717def FNINIT : I<0xDB, MRM_E3, (outs), (ins), "fninit", []>; 718// Clear exceptions 719let Defs = [FPSW] in 720def FNCLEX : I<0xDB, MRM_E2, (outs), (ins), "fnclex", []>; 721} // SchedRW 722 723// Operand-less floating-point instructions for the disassembler. 724let Defs = [FPSW] in 725def FNOP : I<0xD9, MRM_D0, (outs), (ins), "fnop", []>, Sched<[WriteNop]>; 726 727let SchedRW = [WriteMicrocoded] in { 728let Defs = [FPSW] in { 729def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>; 730def FXAM : I<0xD9, MRM_E5, (outs), (ins), "fxam", []>; 731def FDECSTP : I<0xD9, MRM_F6, (outs), (ins), "fdecstp", []>; 732def FINCSTP : I<0xD9, MRM_F7, (outs), (ins), "fincstp", []>; 733let Uses = [FPCW], mayRaiseFPException = 1 in { 734def F2XM1 : I<0xD9, MRM_F0, (outs), (ins), "f2xm1", []>; 735def FYL2X : I<0xD9, MRM_F1, (outs), (ins), "fyl2x", []>; 736def FPTAN : I<0xD9, MRM_F2, (outs), (ins), "fptan", []>; 737def FPATAN : I<0xD9, MRM_F3, (outs), (ins), "fpatan", []>; 738def FXTRACT : I<0xD9, MRM_F4, (outs), (ins), "fxtract", []>; 739def FPREM1 : I<0xD9, MRM_F5, (outs), (ins), "fprem1", []>; 740def FPREM : I<0xD9, MRM_F8, (outs), (ins), "fprem", []>; 741def FYL2XP1 : I<0xD9, MRM_F9, (outs), (ins), "fyl2xp1", []>; 742def FSIN : I<0xD9, MRM_FE, (outs), (ins), "fsin", []>; 743def FCOS : I<0xD9, MRM_FF, (outs), (ins), "fcos", []>; 744def FSINCOS : I<0xD9, MRM_FB, (outs), (ins), "fsincos", []>; 745def FRNDINT : I<0xD9, MRM_FC, (outs), (ins), "frndint", []>; 746def FSCALE : I<0xD9, MRM_FD, (outs), (ins), "fscale", []>; 747def FCOMPP : I<0xDE, MRM_D9, (outs), (ins), "fcompp", []>; 748} // Uses = [FPCW], mayRaiseFPException = 1 749} // Defs = [FPSW] 750 751let Uses = [FPSW, FPCW] in { 752def FXSAVE : I<0xAE, MRM0m, (outs), (ins opaquemem:$dst), 753 "fxsave\t$dst", [(int_x86_fxsave addr:$dst)]>, PS, 754 Requires<[HasFXSR]>; 755def FXSAVE64 : RI<0xAE, MRM0m, (outs), (ins opaquemem:$dst), 756 "fxsave64\t$dst", [(int_x86_fxsave64 addr:$dst)]>, 757 PS, Requires<[HasFXSR, In64BitMode]>; 758} // Uses = [FPSW, FPCW] 759 760let Defs = [FPSW, FPCW] in { 761def FXRSTOR : I<0xAE, MRM1m, (outs), (ins opaquemem:$src), 762 "fxrstor\t$src", [(int_x86_fxrstor addr:$src)]>, 763 PS, Requires<[HasFXSR]>; 764def FXRSTOR64 : RI<0xAE, MRM1m, (outs), (ins opaquemem:$src), 765 "fxrstor64\t$src", [(int_x86_fxrstor64 addr:$src)]>, 766 PS, Requires<[HasFXSR, In64BitMode]>; 767} // Defs = [FPSW, FPCW] 768} // SchedRW 769 770//===----------------------------------------------------------------------===// 771// Non-Instruction Patterns 772//===----------------------------------------------------------------------===// 773 774// Required for RET of f32 / f64 / f80 values. 775def : Pat<(X86fldf32 addr:$src), (LD_Fp32m addr:$src)>; 776def : Pat<(X86fldf32 addr:$src), (LD_Fp32m64 addr:$src)>; 777def : Pat<(X86fldf64 addr:$src), (LD_Fp64m addr:$src)>; 778def : Pat<(X86fldf32 addr:$src), (LD_Fp32m80 addr:$src)>; 779def : Pat<(X86fldf64 addr:$src), (LD_Fp64m80 addr:$src)>; 780def : Pat<(X86fldf80 addr:$src), (LD_Fp80m addr:$src)>; 781 782// Required for CALL which return f32 / f64 / f80 values. 783def : Pat<(X86fstf32 RFP32:$src, addr:$op), (ST_Fp32m addr:$op, RFP32:$src)>; 784def : Pat<(X86fstf32 RFP64:$src, addr:$op), (ST_Fp64m32 addr:$op, RFP64:$src)>; 785def : Pat<(X86fstf64 RFP64:$src, addr:$op), (ST_Fp64m addr:$op, RFP64:$src)>; 786def : Pat<(X86fstf32 RFP80:$src, addr:$op), (ST_Fp80m32 addr:$op, RFP80:$src)>; 787def : Pat<(X86fstf64 RFP80:$src, addr:$op), (ST_Fp80m64 addr:$op, RFP80:$src)>; 788def : Pat<(X86fstf80 RFP80:$src, addr:$op), (ST_FpP80m addr:$op, RFP80:$src)>; 789 790// Floating point constant -0.0 and -1.0 791def : Pat<(f32 fpimmneg0), (CHS_Fp32 (LD_Fp032))>, Requires<[FPStackf32]>; 792def : Pat<(f32 fpimmneg1), (CHS_Fp32 (LD_Fp132))>, Requires<[FPStackf32]>; 793def : Pat<(f64 fpimmneg0), (CHS_Fp64 (LD_Fp064))>, Requires<[FPStackf64]>; 794def : Pat<(f64 fpimmneg1), (CHS_Fp64 (LD_Fp164))>, Requires<[FPStackf64]>; 795def : Pat<(f80 fpimmneg0), (CHS_Fp80 (LD_Fp080))>; 796def : Pat<(f80 fpimmneg1), (CHS_Fp80 (LD_Fp180))>; 797 798// FP extensions map onto simple pseudo-value conversions if they are to/from 799// the FP stack. 800def : Pat<(f64 (any_fpextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP64)>, 801 Requires<[FPStackf32]>; 802def : Pat<(f80 (any_fpextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP80)>, 803 Requires<[FPStackf32]>; 804def : Pat<(f80 (any_fpextend RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP80)>, 805 Requires<[FPStackf64]>; 806 807// FP truncations map onto simple pseudo-value conversions if they are to/from 808// the FP stack. We have validated that only value-preserving truncations make 809// it through isel. 810def : Pat<(f32 (any_fpround RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP32)>, 811 Requires<[FPStackf32]>; 812def : Pat<(f32 (any_fpround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP32)>, 813 Requires<[FPStackf32]>; 814def : Pat<(f64 (any_fpround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP64)>, 815 Requires<[FPStackf64]>; 816