1//=- X86SchedSkylake.td - X86 Skylake Client Scheduling ------*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for Skylake Client to support 10// instruction scheduling and other instruction cost heuristics. 11// 12//===----------------------------------------------------------------------===// 13 14def SkylakeClientModel : SchedMachineModel { 15 // All x86 instructions are modeled as a single micro-op, and SKylake can 16 // decode 6 instructions per cycle. 17 let IssueWidth = 6; 18 let MicroOpBufferSize = 224; // Based on the reorder buffer. 19 let LoadLatency = 5; 20 let MispredictPenalty = 14; 21 22 // Based on the LSD (loop-stream detector) queue size and benchmarking data. 23 let LoopMicroOpBufferSize = 50; 24 25 // This flag is set to allow the scheduler to assign a default model to 26 // unrecognized opcodes. 27 let CompleteModel = 0; 28} 29 30let SchedModel = SkylakeClientModel in { 31 32// Skylake Client can issue micro-ops to 8 different ports in one cycle. 33 34// Ports 0, 1, 5, and 6 handle all computation. 35// Port 4 gets the data half of stores. Store data can be available later than 36// the store address, but since we don't model the latency of stores, we can 37// ignore that. 38// Ports 2 and 3 are identical. They handle loads and the address half of 39// stores. Port 7 can handle address calculations. 40def SKLPort0 : ProcResource<1>; 41def SKLPort1 : ProcResource<1>; 42def SKLPort2 : ProcResource<1>; 43def SKLPort3 : ProcResource<1>; 44def SKLPort4 : ProcResource<1>; 45def SKLPort5 : ProcResource<1>; 46def SKLPort6 : ProcResource<1>; 47def SKLPort7 : ProcResource<1>; 48 49// Many micro-ops are capable of issuing on multiple ports. 50def SKLPort01 : ProcResGroup<[SKLPort0, SKLPort1]>; 51def SKLPort23 : ProcResGroup<[SKLPort2, SKLPort3]>; 52def SKLPort237 : ProcResGroup<[SKLPort2, SKLPort3, SKLPort7]>; 53def SKLPort04 : ProcResGroup<[SKLPort0, SKLPort4]>; 54def SKLPort05 : ProcResGroup<[SKLPort0, SKLPort5]>; 55def SKLPort06 : ProcResGroup<[SKLPort0, SKLPort6]>; 56def SKLPort15 : ProcResGroup<[SKLPort1, SKLPort5]>; 57def SKLPort16 : ProcResGroup<[SKLPort1, SKLPort6]>; 58def SKLPort56 : ProcResGroup<[SKLPort5, SKLPort6]>; 59def SKLPort015 : ProcResGroup<[SKLPort0, SKLPort1, SKLPort5]>; 60def SKLPort056 : ProcResGroup<[SKLPort0, SKLPort5, SKLPort6]>; 61def SKLPort0156: ProcResGroup<[SKLPort0, SKLPort1, SKLPort5, SKLPort6]>; 62 63def SKLDivider : ProcResource<1>; // Integer division issued on port 0. 64// FP division and sqrt on port 0. 65def SKLFPDivider : ProcResource<1>; 66 67// 60 Entry Unified Scheduler 68def SKLPortAny : ProcResGroup<[SKLPort0, SKLPort1, SKLPort2, SKLPort3, SKLPort4, 69 SKLPort5, SKLPort6, SKLPort7]> { 70 let BufferSize=60; 71} 72 73// Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5 74// cycles after the memory operand. 75def : ReadAdvance<ReadAfterLd, 5>; 76 77// Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available 78// until 5/6/7 cycles after the memory operand. 79def : ReadAdvance<ReadAfterVecLd, 5>; 80def : ReadAdvance<ReadAfterVecXLd, 6>; 81def : ReadAdvance<ReadAfterVecYLd, 7>; 82 83def : ReadAdvance<ReadInt2Fpu, 0>; 84 85// Many SchedWrites are defined in pairs with and without a folded load. 86// Instructions with folded loads are usually micro-fused, so they only appear 87// as two micro-ops when queued in the reservation station. 88// This multiclass defines the resource usage for variants with and without 89// folded loads. 90multiclass SKLWriteResPair<X86FoldableSchedWrite SchedRW, 91 list<ProcResourceKind> ExePorts, 92 int Lat, list<int> Res = [1], int UOps = 1, 93 int LoadLat = 5> { 94 // Register variant is using a single cycle on ExePort. 95 def : WriteRes<SchedRW, ExePorts> { 96 let Latency = Lat; 97 let ResourceCycles = Res; 98 let NumMicroOps = UOps; 99 } 100 101 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to 102 // the latency (default = 5). 103 def : WriteRes<SchedRW.Folded, !listconcat([SKLPort23], ExePorts)> { 104 let Latency = !add(Lat, LoadLat); 105 let ResourceCycles = !listconcat([1], Res); 106 let NumMicroOps = !add(UOps, 1); 107 } 108} 109 110// A folded store needs a cycle on port 4 for the store data, and an extra port 111// 2/3/7 cycle to recompute the address. 112def : WriteRes<WriteRMW, [SKLPort237,SKLPort4]>; 113 114// Arithmetic. 115defm : SKLWriteResPair<WriteALU, [SKLPort0156], 1>; // Simple integer ALU op. 116defm : SKLWriteResPair<WriteADC, [SKLPort06], 1>; // Integer ALU + flags op. 117 118// Integer multiplication. 119defm : SKLWriteResPair<WriteIMul8, [SKLPort1], 3>; 120defm : SKLWriteResPair<WriteIMul16, [SKLPort1,SKLPort06,SKLPort0156], 4, [1,1,2], 4>; 121defm : X86WriteRes<WriteIMul16Imm, [SKLPort1,SKLPort0156], 4, [1,1], 2>; 122defm : X86WriteRes<WriteIMul16ImmLd, [SKLPort1,SKLPort0156,SKLPort23], 8, [1,1,1], 3>; 123defm : SKLWriteResPair<WriteIMul16Reg, [SKLPort1], 3>; 124defm : SKLWriteResPair<WriteIMul32, [SKLPort1,SKLPort06,SKLPort0156], 4, [1,1,1], 3>; 125defm : SKLWriteResPair<WriteIMul32Imm, [SKLPort1], 3>; 126defm : SKLWriteResPair<WriteIMul32Reg, [SKLPort1], 3>; 127defm : SKLWriteResPair<WriteIMul64, [SKLPort1,SKLPort5], 4, [1,1], 2>; 128defm : SKLWriteResPair<WriteIMul64Imm, [SKLPort1], 3>; 129defm : SKLWriteResPair<WriteIMul64Reg, [SKLPort1], 3>; 130def : WriteRes<WriteIMulH, []> { let Latency = 3; } 131 132defm : X86WriteRes<WriteBSWAP32, [SKLPort15], 1, [1], 1>; 133defm : X86WriteRes<WriteBSWAP64, [SKLPort06, SKLPort15], 2, [1,1], 2>; 134defm : X86WriteRes<WriteCMPXCHG,[SKLPort06, SKLPort0156], 5, [2,3], 5>; 135defm : X86WriteRes<WriteCMPXCHGRMW,[SKLPort23,SKLPort06,SKLPort0156,SKLPort237,SKLPort4], 8, [1,2,1,1,1], 6>; 136defm : X86WriteRes<WriteXCHG, [SKLPort0156], 2, [3], 3>; 137 138// TODO: Why isn't the SKLDivider used? 139defm : SKLWriteResPair<WriteDiv8, [SKLPort0,SKLDivider], 25, [1,10], 1, 4>; 140defm : X86WriteRes<WriteDiv16, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156], 76, [7,2,8,3,1,11], 32>; 141defm : X86WriteRes<WriteDiv32, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156], 76, [7,2,8,3,1,11], 32>; 142defm : X86WriteRes<WriteDiv64, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156], 76, [7,2,8,3,1,11], 32>; 143defm : X86WriteRes<WriteDiv16Ld, [SKLPort0,SKLPort23,SKLDivider], 29, [1,1,10], 2>; 144defm : X86WriteRes<WriteDiv32Ld, [SKLPort0,SKLPort23,SKLDivider], 29, [1,1,10], 2>; 145defm : X86WriteRes<WriteDiv64Ld, [SKLPort0,SKLPort23,SKLDivider], 29, [1,1,10], 2>; 146 147defm : X86WriteRes<WriteIDiv8, [SKLPort0,SKLDivider], 25, [1,10], 1>; 148defm : X86WriteRes<WriteIDiv16, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156], 102, [4,2,4,8,14,34], 66>; 149defm : X86WriteRes<WriteIDiv32, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156], 102, [4,2,4,8,14,34], 66>; 150defm : X86WriteRes<WriteIDiv64, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156], 102, [4,2,4,8,14,34], 66>; 151defm : X86WriteRes<WriteIDiv8Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>; 152defm : X86WriteRes<WriteIDiv16Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>; 153defm : X86WriteRes<WriteIDiv32Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>; 154defm : X86WriteRes<WriteIDiv64Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>; 155 156defm : SKLWriteResPair<WriteCRC32, [SKLPort1], 3>; 157 158def : WriteRes<WriteLEA, [SKLPort15]>; // LEA instructions can't fold loads. 159 160defm : SKLWriteResPair<WriteCMOV, [SKLPort06], 1, [1], 1>; // Conditional move. 161defm : X86WriteRes<WriteFCMOV, [SKLPort1], 3, [1], 1>; // x87 conditional move. 162def : WriteRes<WriteSETCC, [SKLPort06]>; // Setcc. 163def : WriteRes<WriteSETCCStore, [SKLPort06,SKLPort4,SKLPort237]> { 164 let Latency = 2; 165 let NumMicroOps = 3; 166} 167 168defm : X86WriteRes<WriteLAHFSAHF, [SKLPort06], 1, [1], 1>; 169defm : X86WriteRes<WriteBitTest, [SKLPort06], 1, [1], 1>; 170defm : X86WriteRes<WriteBitTestImmLd, [SKLPort06,SKLPort23], 6, [1,1], 2>; 171defm : X86WriteRes<WriteBitTestRegLd, [SKLPort0156,SKLPort23], 6, [1,1], 2>; 172defm : X86WriteRes<WriteBitTestSet, [SKLPort06], 1, [1], 1>; 173defm : X86WriteRes<WriteBitTestSetImmLd, [SKLPort06,SKLPort23], 5, [1,1], 3>; 174defm : X86WriteRes<WriteBitTestSetRegLd, [SKLPort0156,SKLPort23], 5, [1,1], 2>; 175 176// Bit counts. 177defm : SKLWriteResPair<WriteBSF, [SKLPort1], 3>; 178defm : SKLWriteResPair<WriteBSR, [SKLPort1], 3>; 179defm : SKLWriteResPair<WriteLZCNT, [SKLPort1], 3>; 180defm : SKLWriteResPair<WriteTZCNT, [SKLPort1], 3>; 181defm : SKLWriteResPair<WritePOPCNT, [SKLPort1], 3>; 182 183// Integer shifts and rotates. 184defm : SKLWriteResPair<WriteShift, [SKLPort06], 1>; 185defm : SKLWriteResPair<WriteShiftCL, [SKLPort06], 3, [3], 3>; 186defm : SKLWriteResPair<WriteRotate, [SKLPort06], 1, [1], 1>; 187defm : SKLWriteResPair<WriteRotateCL, [SKLPort06], 3, [3], 3>; 188 189// SHLD/SHRD. 190defm : X86WriteRes<WriteSHDrri, [SKLPort1], 3, [1], 1>; 191defm : X86WriteRes<WriteSHDrrcl,[SKLPort1,SKLPort06,SKLPort0156], 6, [1, 2, 1], 4>; 192defm : X86WriteRes<WriteSHDmri, [SKLPort1,SKLPort23,SKLPort237,SKLPort0156], 9, [1, 1, 1, 1], 4>; 193defm : X86WriteRes<WriteSHDmrcl,[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort0156], 11, [1, 1, 1, 2, 1], 6>; 194 195// BMI1 BEXTR/BLS, BMI2 BZHI 196defm : SKLWriteResPair<WriteBEXTR, [SKLPort06,SKLPort15], 2, [1,1], 2>; 197defm : SKLWriteResPair<WriteBLS, [SKLPort15], 1>; 198defm : SKLWriteResPair<WriteBZHI, [SKLPort15], 1>; 199 200// Loads, stores, and moves, not folded with other operations. 201defm : X86WriteRes<WriteLoad, [SKLPort23], 5, [1], 1>; 202defm : X86WriteRes<WriteStore, [SKLPort237, SKLPort4], 1, [1,1], 1>; 203defm : X86WriteRes<WriteStoreNT, [SKLPort237, SKLPort4], 1, [1,1], 2>; 204defm : X86WriteRes<WriteMove, [SKLPort0156], 1, [1], 1>; 205 206// Idioms that clear a register, like xorps %xmm0, %xmm0. 207// These can often bypass execution ports completely. 208def : WriteRes<WriteZero, []>; 209 210// Branches don't produce values, so they have no latency, but they still 211// consume resources. Indirect branches can fold loads. 212defm : SKLWriteResPair<WriteJump, [SKLPort06], 1>; 213 214// Floating point. This covers both scalar and vector operations. 215defm : X86WriteRes<WriteFLD0, [SKLPort05], 1, [1], 1>; 216defm : X86WriteRes<WriteFLD1, [SKLPort05], 1, [2], 2>; 217defm : X86WriteRes<WriteFLDC, [SKLPort05], 1, [2], 2>; 218defm : X86WriteRes<WriteFLoad, [SKLPort23], 5, [1], 1>; 219defm : X86WriteRes<WriteFLoadX, [SKLPort23], 6, [1], 1>; 220defm : X86WriteRes<WriteFLoadY, [SKLPort23], 7, [1], 1>; 221defm : X86WriteRes<WriteFMaskedLoad, [SKLPort23,SKLPort015], 7, [1,1], 2>; 222defm : X86WriteRes<WriteFMaskedLoadY, [SKLPort23,SKLPort015], 8, [1,1], 2>; 223defm : X86WriteRes<WriteFStore, [SKLPort237,SKLPort4], 1, [1,1], 2>; 224defm : X86WriteRes<WriteFStoreX, [SKLPort237,SKLPort4], 1, [1,1], 2>; 225defm : X86WriteRes<WriteFStoreY, [SKLPort237,SKLPort4], 1, [1,1], 2>; 226defm : X86WriteRes<WriteFStoreNT, [SKLPort237,SKLPort4], 1, [1,1], 2>; 227defm : X86WriteRes<WriteFStoreNTX, [SKLPort237,SKLPort4], 1, [1,1], 2>; 228defm : X86WriteRes<WriteFStoreNTY, [SKLPort237,SKLPort4], 1, [1,1], 2>; 229 230defm : X86WriteRes<WriteFMaskedStore32, [SKLPort237,SKLPort0], 2, [1,1], 2>; 231defm : X86WriteRes<WriteFMaskedStore32Y, [SKLPort237,SKLPort0], 2, [1,1], 2>; 232defm : X86WriteRes<WriteFMaskedStore64, [SKLPort237,SKLPort0], 2, [1,1], 2>; 233defm : X86WriteRes<WriteFMaskedStore64Y, [SKLPort237,SKLPort0], 2, [1,1], 2>; 234 235defm : X86WriteRes<WriteFMove, [SKLPort015], 1, [1], 1>; 236defm : X86WriteRes<WriteFMoveX, [SKLPort015], 1, [1], 1>; 237defm : X86WriteRes<WriteFMoveY, [SKLPort015], 1, [1], 1>; 238defm : X86WriteRes<WriteEMMS, [SKLPort05,SKLPort0156], 10, [9,1], 10>; 239 240defm : SKLWriteResPair<WriteFAdd, [SKLPort01], 4, [1], 1, 5>; // Floating point add/sub. 241defm : SKLWriteResPair<WriteFAddX, [SKLPort01], 4, [1], 1, 6>; 242defm : SKLWriteResPair<WriteFAddY, [SKLPort01], 4, [1], 1, 7>; 243defm : X86WriteResPairUnsupported<WriteFAddZ>; 244defm : SKLWriteResPair<WriteFAdd64, [SKLPort01], 4, [1], 1, 5>; // Floating point double add/sub. 245defm : SKLWriteResPair<WriteFAdd64X, [SKLPort01], 4, [1], 1, 6>; 246defm : SKLWriteResPair<WriteFAdd64Y, [SKLPort01], 4, [1], 1, 7>; 247defm : X86WriteResPairUnsupported<WriteFAdd64Z>; 248 249defm : SKLWriteResPair<WriteFCmp, [SKLPort01], 4, [1], 1, 5>; // Floating point compare. 250defm : SKLWriteResPair<WriteFCmpX, [SKLPort01], 4, [1], 1, 6>; 251defm : SKLWriteResPair<WriteFCmpY, [SKLPort01], 4, [1], 1, 7>; 252defm : X86WriteResPairUnsupported<WriteFCmpZ>; 253defm : SKLWriteResPair<WriteFCmp64, [SKLPort01], 4, [1], 1, 5>; // Floating point double compare. 254defm : SKLWriteResPair<WriteFCmp64X, [SKLPort01], 4, [1], 1, 6>; 255defm : SKLWriteResPair<WriteFCmp64Y, [SKLPort01], 4, [1], 1, 7>; 256defm : X86WriteResPairUnsupported<WriteFCmp64Z>; 257 258defm : SKLWriteResPair<WriteFCom, [SKLPort0], 2>; // Floating point compare to flags (X87). 259defm : SKLWriteResPair<WriteFComX, [SKLPort0], 2>; // Floating point compare to flags (SSE). 260 261defm : SKLWriteResPair<WriteFMul, [SKLPort01], 4, [1], 1, 5>; // Floating point multiplication. 262defm : SKLWriteResPair<WriteFMulX, [SKLPort01], 4, [1], 1, 6>; 263defm : SKLWriteResPair<WriteFMulY, [SKLPort01], 4, [1], 1, 7>; 264defm : X86WriteResPairUnsupported<WriteFMulZ>; 265defm : SKLWriteResPair<WriteFMul64, [SKLPort01], 4, [1], 1, 5>; // Floating point double multiplication. 266defm : SKLWriteResPair<WriteFMul64X, [SKLPort01], 4, [1], 1, 6>; 267defm : SKLWriteResPair<WriteFMul64Y, [SKLPort01], 4, [1], 1, 7>; 268defm : X86WriteResPairUnsupported<WriteFMul64Z>; 269 270defm : SKLWriteResPair<WriteFDiv, [SKLPort0,SKLFPDivider], 11, [1,3], 1, 5>; // Floating point division. 271//defm : SKLWriteResPair<WriteFDivX, [SKLPort0,SKLFPDivider], 11, [1,3], 1, 6>; 272defm : SKLWriteResPair<WriteFDivY, [SKLPort0,SKLFPDivider], 11, [1,5], 1, 7>; 273defm : X86WriteResPairUnsupported<WriteFDivZ>; 274//defm : SKLWriteResPair<WriteFDiv64, [SKLPort0,SKLFPDivider], 14, [1,3], 1, 5>; // Floating point double division. 275//defm : SKLWriteResPair<WriteFDiv64X, [SKLPort0,SKLFPDivider], 14, [1,3], 1, 6>; 276//defm : SKLWriteResPair<WriteFDiv64Y, [SKLPort0,SKLFPDivider], 14, [1,5], 1, 7>; 277defm : X86WriteResPairUnsupported<WriteFDiv64Z>; 278 279defm : SKLWriteResPair<WriteFSqrt, [SKLPort0,SKLFPDivider], 12, [1,3], 1, 5>; // Floating point square root. 280defm : SKLWriteResPair<WriteFSqrtX, [SKLPort0,SKLFPDivider], 12, [1,3], 1, 6>; 281defm : SKLWriteResPair<WriteFSqrtY, [SKLPort0,SKLFPDivider], 12, [1,6], 1, 7>; 282defm : X86WriteResPairUnsupported<WriteFSqrtZ>; 283defm : SKLWriteResPair<WriteFSqrt64, [SKLPort0,SKLFPDivider], 18, [1,6], 1, 5>; // Floating point double square root. 284defm : SKLWriteResPair<WriteFSqrt64X, [SKLPort0,SKLFPDivider], 18, [1,6], 1, 6>; 285defm : SKLWriteResPair<WriteFSqrt64Y, [SKLPort0,SKLFPDivider], 18, [1,12],1, 7>; 286defm : X86WriteResPairUnsupported<WriteFSqrt64Z>; 287defm : SKLWriteResPair<WriteFSqrt80, [SKLPort0,SKLFPDivider], 21, [1,7]>; // Floating point long double square root. 288 289defm : SKLWriteResPair<WriteFRcp, [SKLPort0], 4, [1], 1, 5>; // Floating point reciprocal estimate. 290defm : SKLWriteResPair<WriteFRcpX, [SKLPort0], 4, [1], 1, 6>; 291defm : SKLWriteResPair<WriteFRcpY, [SKLPort0], 4, [1], 1, 7>; 292defm : X86WriteResPairUnsupported<WriteFRcpZ>; 293 294defm : SKLWriteResPair<WriteFRsqrt, [SKLPort0], 4, [1], 1, 5>; // Floating point reciprocal square root estimate. 295defm : SKLWriteResPair<WriteFRsqrtX,[SKLPort0], 4, [1], 1, 6>; 296defm : SKLWriteResPair<WriteFRsqrtY,[SKLPort0], 4, [1], 1, 7>; 297defm : X86WriteResPairUnsupported<WriteFRsqrtZ>; 298 299defm : SKLWriteResPair<WriteFMA, [SKLPort01], 4, [1], 1, 5>; // Fused Multiply Add. 300defm : SKLWriteResPair<WriteFMAX, [SKLPort01], 4, [1], 1, 6>; 301defm : SKLWriteResPair<WriteFMAY, [SKLPort01], 4, [1], 1, 7>; 302defm : X86WriteResPairUnsupported<WriteFMAZ>; 303defm : SKLWriteResPair<WriteDPPD, [SKLPort5,SKLPort01], 9, [1,2], 3, 6>; // Floating point double dot product. 304defm : SKLWriteResPair<WriteDPPS, [SKLPort5,SKLPort01], 13, [1,3], 4, 6>; 305defm : SKLWriteResPair<WriteDPPSY, [SKLPort5,SKLPort01], 13, [1,3], 4, 7>; 306defm : X86WriteResPairUnsupported<WriteDPPSZ>; 307defm : SKLWriteResPair<WriteFSign, [SKLPort0], 1>; // Floating point fabs/fchs. 308defm : SKLWriteResPair<WriteFRnd, [SKLPort01], 8, [2], 2, 6>; // Floating point rounding. 309defm : SKLWriteResPair<WriteFRndY, [SKLPort01], 8, [2], 2, 7>; 310defm : X86WriteResPairUnsupported<WriteFRndZ>; 311defm : SKLWriteResPair<WriteFLogic, [SKLPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals. 312defm : SKLWriteResPair<WriteFLogicY, [SKLPort015], 1, [1], 1, 7>; 313defm : X86WriteResPairUnsupported<WriteFLogicZ>; 314defm : SKLWriteResPair<WriteFTest, [SKLPort0], 2, [1], 1, 6>; // Floating point TEST instructions. 315defm : SKLWriteResPair<WriteFTestY, [SKLPort0], 2, [1], 1, 7>; 316defm : X86WriteResPairUnsupported<WriteFTestZ>; 317defm : SKLWriteResPair<WriteFShuffle, [SKLPort5], 1, [1], 1, 6>; // Floating point vector shuffles. 318defm : SKLWriteResPair<WriteFShuffleY, [SKLPort5], 1, [1], 1, 7>; 319defm : X86WriteResPairUnsupported<WriteFShuffleZ>; 320defm : SKLWriteResPair<WriteFVarShuffle, [SKLPort5], 1, [1], 1, 6>; // Floating point vector shuffles. 321defm : SKLWriteResPair<WriteFVarShuffleY, [SKLPort5], 1, [1], 1, 7>; 322defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>; 323defm : SKLWriteResPair<WriteFBlend, [SKLPort015], 1, [1], 1, 6>; // Floating point vector blends. 324defm : SKLWriteResPair<WriteFBlendY, [SKLPort015], 1, [1], 1, 7>; 325defm : X86WriteResPairUnsupported<WriteFBlendZ>; 326defm : SKLWriteResPair<WriteFVarBlend, [SKLPort015], 2, [2], 2, 6>; // Fp vector variable blends. 327defm : SKLWriteResPair<WriteFVarBlendY,[SKLPort015], 2, [2], 2, 7>; 328defm : X86WriteResPairUnsupported<WriteFVarBlendZ>; 329 330// FMA Scheduling helper class. 331// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; } 332 333// Vector integer operations. 334defm : X86WriteRes<WriteVecLoad, [SKLPort23], 5, [1], 1>; 335defm : X86WriteRes<WriteVecLoadX, [SKLPort23], 6, [1], 1>; 336defm : X86WriteRes<WriteVecLoadY, [SKLPort23], 7, [1], 1>; 337defm : X86WriteRes<WriteVecLoadNT, [SKLPort23], 6, [1], 1>; 338defm : X86WriteRes<WriteVecLoadNTY, [SKLPort23], 7, [1], 1>; 339defm : X86WriteRes<WriteVecMaskedLoad, [SKLPort23,SKLPort015], 7, [1,1], 2>; 340defm : X86WriteRes<WriteVecMaskedLoadY, [SKLPort23,SKLPort015], 8, [1,1], 2>; 341defm : X86WriteRes<WriteVecStore, [SKLPort237,SKLPort4], 1, [1,1], 2>; 342defm : X86WriteRes<WriteVecStoreX, [SKLPort237,SKLPort4], 1, [1,1], 2>; 343defm : X86WriteRes<WriteVecStoreY, [SKLPort237,SKLPort4], 1, [1,1], 2>; 344defm : X86WriteRes<WriteVecStoreNT, [SKLPort237,SKLPort4], 1, [1,1], 2>; 345defm : X86WriteRes<WriteVecStoreNTY, [SKLPort237,SKLPort4], 1, [1,1], 2>; 346defm : X86WriteRes<WriteVecMaskedStore32, [SKLPort237,SKLPort0], 2, [1,1], 2>; 347defm : X86WriteRes<WriteVecMaskedStore32Y, [SKLPort237,SKLPort0], 2, [1,1], 2>; 348defm : X86WriteRes<WriteVecMaskedStore64, [SKLPort237,SKLPort0], 2, [1,1], 2>; 349defm : X86WriteRes<WriteVecMaskedStore64Y, [SKLPort237,SKLPort0], 2, [1,1], 2>; 350defm : X86WriteRes<WriteVecMove, [SKLPort05], 1, [1], 1>; 351defm : X86WriteRes<WriteVecMoveX, [SKLPort015], 1, [1], 1>; 352defm : X86WriteRes<WriteVecMoveY, [SKLPort015], 1, [1], 1>; 353defm : X86WriteRes<WriteVecMoveToGpr, [SKLPort0], 2, [1], 1>; 354defm : X86WriteRes<WriteVecMoveFromGpr, [SKLPort5], 1, [1], 1>; 355 356defm : SKLWriteResPair<WriteVecALU, [SKLPort05], 1, [1], 1, 5>; // Vector integer ALU op, no logicals. 357defm : SKLWriteResPair<WriteVecALUX, [SKLPort01], 1, [1], 1, 6>; 358defm : SKLWriteResPair<WriteVecALUY, [SKLPort01], 1, [1], 1, 7>; 359defm : X86WriteResPairUnsupported<WriteVecALUZ>; 360defm : SKLWriteResPair<WriteVecLogic, [SKLPort05], 1, [1], 1, 5>; // Vector integer and/or/xor. 361defm : SKLWriteResPair<WriteVecLogicX,[SKLPort015], 1, [1], 1, 6>; 362defm : SKLWriteResPair<WriteVecLogicY,[SKLPort015], 1, [1], 1, 7>; 363defm : X86WriteResPairUnsupported<WriteVecLogicZ>; 364defm : SKLWriteResPair<WriteVecTest, [SKLPort0,SKLPort5], 3, [1,1], 2, 6>; // Vector integer TEST instructions. 365defm : SKLWriteResPair<WriteVecTestY, [SKLPort0,SKLPort5], 3, [1,1], 2, 7>; 366defm : X86WriteResPairUnsupported<WriteVecTestZ>; 367defm : SKLWriteResPair<WriteVecIMul, [SKLPort0] , 5, [1], 1, 5>; // Vector integer multiply. 368defm : SKLWriteResPair<WriteVecIMulX, [SKLPort01], 5, [1], 1, 6>; 369defm : SKLWriteResPair<WriteVecIMulY, [SKLPort01], 5, [1], 1, 7>; 370defm : X86WriteResPairUnsupported<WriteVecIMulZ>; 371defm : SKLWriteResPair<WritePMULLD, [SKLPort01], 10, [2], 2, 6>; // Vector PMULLD. 372defm : SKLWriteResPair<WritePMULLDY, [SKLPort01], 10, [2], 2, 7>; 373defm : X86WriteResPairUnsupported<WritePMULLDZ>; 374defm : SKLWriteResPair<WriteShuffle, [SKLPort5], 1, [1], 1, 5>; // Vector shuffles. 375defm : SKLWriteResPair<WriteShuffleX, [SKLPort5], 1, [1], 1, 6>; 376defm : SKLWriteResPair<WriteShuffleY, [SKLPort5], 1, [1], 1, 7>; 377defm : X86WriteResPairUnsupported<WriteShuffleZ>; 378defm : SKLWriteResPair<WriteVarShuffle, [SKLPort5], 1, [1], 1, 5>; // Vector shuffles. 379defm : SKLWriteResPair<WriteVarShuffleX, [SKLPort5], 1, [1], 1, 6>; 380defm : SKLWriteResPair<WriteVarShuffleY, [SKLPort5], 1, [1], 1, 7>; 381defm : X86WriteResPairUnsupported<WriteVarShuffleZ>; 382defm : SKLWriteResPair<WriteBlend, [SKLPort5], 1, [1], 1, 6>; // Vector blends. 383defm : SKLWriteResPair<WriteBlendY, [SKLPort5], 1, [1], 1, 7>; 384defm : X86WriteResPairUnsupported<WriteBlendZ>; 385defm : SKLWriteResPair<WriteVarBlend, [SKLPort015], 2, [2], 2, 6>; // Vector variable blends. 386defm : SKLWriteResPair<WriteVarBlendY, [SKLPort015], 2, [2], 2, 6>; 387defm : X86WriteResPairUnsupported<WriteVarBlendZ>; 388defm : SKLWriteResPair<WriteMPSAD, [SKLPort5], 4, [2], 2, 6>; // Vector MPSAD. 389defm : SKLWriteResPair<WriteMPSADY, [SKLPort5], 4, [2], 2, 7>; 390defm : X86WriteResPairUnsupported<WriteMPSADZ>; 391defm : SKLWriteResPair<WritePSADBW, [SKLPort5], 3, [1], 1, 5>; // Vector PSADBW. 392defm : SKLWriteResPair<WritePSADBWX, [SKLPort5], 3, [1], 1, 6>; 393defm : SKLWriteResPair<WritePSADBWY, [SKLPort5], 3, [1], 1, 7>; 394defm : X86WriteResPairUnsupported<WritePSADBWZ>; 395defm : SKLWriteResPair<WritePHMINPOS, [SKLPort01], 4, [1], 1, 6>; // Vector PHMINPOS. 396 397// Vector integer shifts. 398defm : SKLWriteResPair<WriteVecShift, [SKLPort0], 1, [1], 1, 5>; 399defm : X86WriteRes<WriteVecShiftX, [SKLPort5,SKLPort01], 2, [1,1], 2>; 400defm : X86WriteRes<WriteVecShiftY, [SKLPort5,SKLPort01], 4, [1,1], 2>; 401defm : X86WriteRes<WriteVecShiftXLd, [SKLPort01,SKLPort23], 7, [1,1], 2>; 402defm : X86WriteRes<WriteVecShiftYLd, [SKLPort01,SKLPort23], 8, [1,1], 2>; 403defm : X86WriteResPairUnsupported<WriteVecShiftZ>; 404 405defm : SKLWriteResPair<WriteVecShiftImm, [SKLPort0], 1, [1], 1, 5>; // Vector integer immediate shifts. 406defm : SKLWriteResPair<WriteVecShiftImmX, [SKLPort01], 1, [1], 1, 6>; 407defm : SKLWriteResPair<WriteVecShiftImmY, [SKLPort01], 1, [1], 1, 7>; 408defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>; 409defm : SKLWriteResPair<WriteVarVecShift, [SKLPort01], 1, [1], 1, 6>; // Variable vector shifts. 410defm : SKLWriteResPair<WriteVarVecShiftY, [SKLPort01], 1, [1], 1, 7>; 411defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>; 412 413// Vector insert/extract operations. 414def : WriteRes<WriteVecInsert, [SKLPort5]> { 415 let Latency = 2; 416 let NumMicroOps = 2; 417 let ResourceCycles = [2]; 418} 419def : WriteRes<WriteVecInsertLd, [SKLPort5,SKLPort23]> { 420 let Latency = 6; 421 let NumMicroOps = 2; 422} 423def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>; 424 425def : WriteRes<WriteVecExtract, [SKLPort0,SKLPort5]> { 426 let Latency = 3; 427 let NumMicroOps = 2; 428} 429def : WriteRes<WriteVecExtractSt, [SKLPort4,SKLPort5,SKLPort237]> { 430 let Latency = 2; 431 let NumMicroOps = 3; 432} 433 434// Conversion between integer and float. 435defm : SKLWriteResPair<WriteCvtSS2I, [SKLPort1], 3>; 436defm : SKLWriteResPair<WriteCvtPS2I, [SKLPort1], 3>; 437defm : SKLWriteResPair<WriteCvtPS2IY, [SKLPort1], 3>; 438defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>; 439defm : SKLWriteResPair<WriteCvtSD2I, [SKLPort1], 3>; 440defm : SKLWriteResPair<WriteCvtPD2I, [SKLPort1], 3>; 441defm : SKLWriteResPair<WriteCvtPD2IY, [SKLPort1], 3>; 442defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>; 443 444defm : SKLWriteResPair<WriteCvtI2SS, [SKLPort1], 4>; 445defm : SKLWriteResPair<WriteCvtI2PS, [SKLPort1], 4>; 446defm : SKLWriteResPair<WriteCvtI2PSY, [SKLPort1], 4>; 447defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>; 448defm : SKLWriteResPair<WriteCvtI2SD, [SKLPort1], 4>; 449defm : SKLWriteResPair<WriteCvtI2PD, [SKLPort1], 4>; 450defm : SKLWriteResPair<WriteCvtI2PDY, [SKLPort1], 4>; 451defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>; 452 453defm : SKLWriteResPair<WriteCvtSS2SD, [SKLPort1], 3>; 454defm : SKLWriteResPair<WriteCvtPS2PD, [SKLPort1], 3>; 455defm : SKLWriteResPair<WriteCvtPS2PDY, [SKLPort1], 3>; 456defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>; 457defm : SKLWriteResPair<WriteCvtSD2SS, [SKLPort1], 3>; 458defm : SKLWriteResPair<WriteCvtPD2PS, [SKLPort1], 3>; 459defm : SKLWriteResPair<WriteCvtPD2PSY, [SKLPort1], 3>; 460defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>; 461 462defm : X86WriteRes<WriteCvtPH2PS, [SKLPort5,SKLPort015], 5, [1,1], 2>; 463defm : X86WriteRes<WriteCvtPH2PSY, [SKLPort5,SKLPort01], 7, [1,1], 2>; 464defm : X86WriteResUnsupported<WriteCvtPH2PSZ>; 465defm : X86WriteRes<WriteCvtPH2PSLd, [SKLPort23,SKLPort01], 9, [1,1], 2>; 466defm : X86WriteRes<WriteCvtPH2PSYLd, [SKLPort23,SKLPort01], 10, [1,1], 2>; 467defm : X86WriteResUnsupported<WriteCvtPH2PSZLd>; 468 469defm : X86WriteRes<WriteCvtPS2PH, [SKLPort5,SKLPort015], 5, [1,1], 2>; 470defm : X86WriteRes<WriteCvtPS2PHY, [SKLPort5,SKLPort01], 7, [1,1], 2>; 471defm : X86WriteResUnsupported<WriteCvtPS2PHZ>; 472defm : X86WriteRes<WriteCvtPS2PHSt, [SKLPort4,SKLPort5,SKLPort237,SKLPort01], 6, [1,1,1,1], 4>; 473defm : X86WriteRes<WriteCvtPS2PHYSt, [SKLPort4,SKLPort5,SKLPort237,SKLPort01], 8, [1,1,1,1], 4>; 474defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>; 475 476// Strings instructions. 477 478// Packed Compare Implicit Length Strings, Return Mask 479def : WriteRes<WritePCmpIStrM, [SKLPort0]> { 480 let Latency = 10; 481 let NumMicroOps = 3; 482 let ResourceCycles = [3]; 483} 484def : WriteRes<WritePCmpIStrMLd, [SKLPort0, SKLPort23]> { 485 let Latency = 16; 486 let NumMicroOps = 4; 487 let ResourceCycles = [3,1]; 488} 489 490// Packed Compare Explicit Length Strings, Return Mask 491def : WriteRes<WritePCmpEStrM, [SKLPort0, SKLPort5, SKLPort015, SKLPort0156]> { 492 let Latency = 19; 493 let NumMicroOps = 9; 494 let ResourceCycles = [4,3,1,1]; 495} 496def : WriteRes<WritePCmpEStrMLd, [SKLPort0, SKLPort5,SKLPort23, SKLPort015, SKLPort0156]> { 497 let Latency = 25; 498 let NumMicroOps = 10; 499 let ResourceCycles = [4,3,1,1,1]; 500} 501 502// Packed Compare Implicit Length Strings, Return Index 503def : WriteRes<WritePCmpIStrI, [SKLPort0]> { 504 let Latency = 10; 505 let NumMicroOps = 3; 506 let ResourceCycles = [3]; 507} 508def : WriteRes<WritePCmpIStrILd, [SKLPort0, SKLPort23]> { 509 let Latency = 16; 510 let NumMicroOps = 4; 511 let ResourceCycles = [3,1]; 512} 513 514// Packed Compare Explicit Length Strings, Return Index 515def : WriteRes<WritePCmpEStrI, [SKLPort0, SKLPort5, SKLPort0156]> { 516 let Latency = 18; 517 let NumMicroOps = 8; 518 let ResourceCycles = [4,3,1]; 519} 520def : WriteRes<WritePCmpEStrILd, [SKLPort0, SKLPort5, SKLPort23, SKLPort0156]> { 521 let Latency = 24; 522 let NumMicroOps = 9; 523 let ResourceCycles = [4,3,1,1]; 524} 525 526// MOVMSK Instructions. 527def : WriteRes<WriteFMOVMSK, [SKLPort0]> { let Latency = 2; } 528def : WriteRes<WriteVecMOVMSK, [SKLPort0]> { let Latency = 2; } 529def : WriteRes<WriteVecMOVMSKY, [SKLPort0]> { let Latency = 2; } 530def : WriteRes<WriteMMXMOVMSK, [SKLPort0]> { let Latency = 2; } 531 532// AES instructions. 533def : WriteRes<WriteAESDecEnc, [SKLPort0]> { // Decryption, encryption. 534 let Latency = 4; 535 let NumMicroOps = 1; 536 let ResourceCycles = [1]; 537} 538def : WriteRes<WriteAESDecEncLd, [SKLPort0, SKLPort23]> { 539 let Latency = 10; 540 let NumMicroOps = 2; 541 let ResourceCycles = [1,1]; 542} 543 544def : WriteRes<WriteAESIMC, [SKLPort0]> { // InvMixColumn. 545 let Latency = 8; 546 let NumMicroOps = 2; 547 let ResourceCycles = [2]; 548} 549def : WriteRes<WriteAESIMCLd, [SKLPort0, SKLPort23]> { 550 let Latency = 14; 551 let NumMicroOps = 3; 552 let ResourceCycles = [2,1]; 553} 554 555def : WriteRes<WriteAESKeyGen, [SKLPort0, SKLPort5, SKLPort015]> { // Key Generation. 556 let Latency = 20; 557 let NumMicroOps = 11; 558 let ResourceCycles = [3,6,2]; 559} 560def : WriteRes<WriteAESKeyGenLd, [SKLPort0, SKLPort5, SKLPort23, SKLPort015]> { 561 let Latency = 25; 562 let NumMicroOps = 11; 563 let ResourceCycles = [3,6,1,1]; 564} 565 566// Carry-less multiplication instructions. 567def : WriteRes<WriteCLMul, [SKLPort5]> { 568 let Latency = 6; 569 let NumMicroOps = 1; 570 let ResourceCycles = [1]; 571} 572def : WriteRes<WriteCLMulLd, [SKLPort5, SKLPort23]> { 573 let Latency = 12; 574 let NumMicroOps = 2; 575 let ResourceCycles = [1,1]; 576} 577 578// Catch-all for expensive system instructions. 579def : WriteRes<WriteSystem, [SKLPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite; 580 581// AVX2. 582defm : SKLWriteResPair<WriteFShuffle256, [SKLPort5], 3, [1], 1, 7>; // Fp 256-bit width vector shuffles. 583defm : SKLWriteResPair<WriteFVarShuffle256, [SKLPort5], 3, [1], 1, 7>; // Fp 256-bit width vector variable shuffles. 584defm : SKLWriteResPair<WriteShuffle256, [SKLPort5], 3, [1], 1, 7>; // 256-bit width vector shuffles. 585defm : SKLWriteResPair<WriteVarShuffle256, [SKLPort5], 3, [1], 1, 7>; // 256-bit width vector variable shuffles. 586 587// Old microcoded instructions that nobody use. 588def : WriteRes<WriteMicrocoded, [SKLPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite; 589 590// Fence instructions. 591def : WriteRes<WriteFence, [SKLPort23, SKLPort4]>; 592 593// Load/store MXCSR. 594def : WriteRes<WriteLDMXCSR, [SKLPort0,SKLPort23,SKLPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } 595def : WriteRes<WriteSTMXCSR, [SKLPort4,SKLPort5,SKLPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } 596 597// Nop, not very useful expect it provides a model for nops! 598def : WriteRes<WriteNop, []>; 599 600//////////////////////////////////////////////////////////////////////////////// 601// Horizontal add/sub instructions. 602//////////////////////////////////////////////////////////////////////////////// 603 604defm : SKLWriteResPair<WriteFHAdd, [SKLPort5,SKLPort01], 6, [2,1], 3, 6>; 605defm : SKLWriteResPair<WriteFHAddY, [SKLPort5,SKLPort01], 6, [2,1], 3, 7>; 606defm : SKLWriteResPair<WritePHAdd, [SKLPort5,SKLPort05], 3, [2,1], 3, 5>; 607defm : SKLWriteResPair<WritePHAddX, [SKLPort5,SKLPort015], 3, [2,1], 3, 6>; 608defm : SKLWriteResPair<WritePHAddY, [SKLPort5,SKLPort015], 3, [2,1], 3, 7>; 609 610// Remaining instrs. 611 612def SKLWriteResGroup1 : SchedWriteRes<[SKLPort0]> { 613 let Latency = 1; 614 let NumMicroOps = 1; 615 let ResourceCycles = [1]; 616} 617def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PADDS(B|W)irr", 618 "MMX_PADDUS(B|W)irr", 619 "MMX_PAVG(B|W)irr", 620 "MMX_PCMPEQ(B|D|W)irr", 621 "MMX_PCMPGT(B|D|W)irr", 622 "MMX_P(MAX|MIN)SWirr", 623 "MMX_P(MAX|MIN)UBirr", 624 "MMX_PSUBS(B|W)irr", 625 "MMX_PSUBUS(B|W)irr")>; 626 627def SKLWriteResGroup3 : SchedWriteRes<[SKLPort5]> { 628 let Latency = 1; 629 let NumMicroOps = 1; 630 let ResourceCycles = [1]; 631} 632def: InstRW<[SKLWriteResGroup3], (instregex "COM(P?)_FST0r", 633 "UCOM_F(P?)r")>; 634 635def SKLWriteResGroup4 : SchedWriteRes<[SKLPort6]> { 636 let Latency = 1; 637 let NumMicroOps = 1; 638 let ResourceCycles = [1]; 639} 640def: InstRW<[SKLWriteResGroup4], (instregex "JMP(16|32|64)r")>; 641 642def SKLWriteResGroup6 : SchedWriteRes<[SKLPort05]> { 643 let Latency = 1; 644 let NumMicroOps = 1; 645 let ResourceCycles = [1]; 646} 647def: InstRW<[SKLWriteResGroup6], (instrs FINCSTP, FNOP)>; 648 649def SKLWriteResGroup7 : SchedWriteRes<[SKLPort06]> { 650 let Latency = 1; 651 let NumMicroOps = 1; 652 let ResourceCycles = [1]; 653} 654def: InstRW<[SKLWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>; 655 656def SKLWriteResGroup8 : SchedWriteRes<[SKLPort15]> { 657 let Latency = 1; 658 let NumMicroOps = 1; 659 let ResourceCycles = [1]; 660} 661def: InstRW<[SKLWriteResGroup8], (instregex "ANDN(32|64)rr")>; 662 663def SKLWriteResGroup9 : SchedWriteRes<[SKLPort015]> { 664 let Latency = 1; 665 let NumMicroOps = 1; 666 let ResourceCycles = [1]; 667} 668def: InstRW<[SKLWriteResGroup9], (instregex "(V?)PADD(B|D|Q|W)(Y?)rr", 669 "VPBLENDD(Y?)rri")>; 670 671def SKLWriteResGroup10 : SchedWriteRes<[SKLPort0156]> { 672 let Latency = 1; 673 let NumMicroOps = 1; 674 let ResourceCycles = [1]; 675} 676def: InstRW<[SKLWriteResGroup10], (instrs CBW, CWDE, CDQE, 677 CMC, STC, 678 SGDT64m, 679 SIDT64m, 680 SMSW16m, 681 STRm, 682 SYSCALL)>; 683 684def SKLWriteResGroup11 : SchedWriteRes<[SKLPort4,SKLPort237]> { 685 let Latency = 1; 686 let NumMicroOps = 2; 687 let ResourceCycles = [1,1]; 688} 689def: InstRW<[SKLWriteResGroup11], (instrs FBSTPm, VMPTRSTm)>; 690def: InstRW<[SKLWriteResGroup11], (instregex "ST_FP(32|64|80)m")>; 691 692def SKLWriteResGroup13 : SchedWriteRes<[SKLPort5]> { 693 let Latency = 2; 694 let NumMicroOps = 2; 695 let ResourceCycles = [2]; 696} 697def: InstRW<[SKLWriteResGroup13], (instrs MMX_MOVQ2DQrr)>; 698 699def SKLWriteResGroup14 : SchedWriteRes<[SKLPort05]> { 700 let Latency = 2; 701 let NumMicroOps = 2; 702 let ResourceCycles = [2]; 703} 704def: InstRW<[SKLWriteResGroup14], (instrs FDECSTP, 705 MMX_MOVDQ2Qrr)>; 706 707def SKLWriteResGroup17 : SchedWriteRes<[SKLPort0156]> { 708 let Latency = 2; 709 let NumMicroOps = 2; 710 let ResourceCycles = [2]; 711} 712def: InstRW<[SKLWriteResGroup17], (instrs LFENCE, 713 WAIT, 714 XGETBV)>; 715 716def SKLWriteResGroup20 : SchedWriteRes<[SKLPort6,SKLPort0156]> { 717 let Latency = 2; 718 let NumMicroOps = 2; 719 let ResourceCycles = [1,1]; 720} 721def: InstRW<[SKLWriteResGroup20], (instregex "CLFLUSH")>; 722 723def SKLWriteResGroup21 : SchedWriteRes<[SKLPort237,SKLPort0156]> { 724 let Latency = 2; 725 let NumMicroOps = 2; 726 let ResourceCycles = [1,1]; 727} 728def: InstRW<[SKLWriteResGroup21], (instrs SFENCE)>; 729 730def SKLWriteResGroup23 : SchedWriteRes<[SKLPort06,SKLPort0156]> { 731 let Latency = 2; 732 let NumMicroOps = 2; 733 let ResourceCycles = [1,1]; 734} 735def: InstRW<[SKLWriteResGroup23], (instrs CWD, 736 JCXZ, JECXZ, JRCXZ, 737 ADC8i8, SBB8i8, 738 ADC16i16, SBB16i16, 739 ADC32i32, SBB32i32, 740 ADC64i32, SBB64i32)>; 741 742def SKLWriteResGroup25 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237]> { 743 let Latency = 2; 744 let NumMicroOps = 3; 745 let ResourceCycles = [1,1,1]; 746} 747def: InstRW<[SKLWriteResGroup25], (instrs FNSTCW16m)>; 748 749def SKLWriteResGroup27 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort15]> { 750 let Latency = 2; 751 let NumMicroOps = 3; 752 let ResourceCycles = [1,1,1]; 753} 754def: InstRW<[SKLWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>; 755 756def SKLWriteResGroup28 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> { 757 let Latency = 2; 758 let NumMicroOps = 3; 759 let ResourceCycles = [1,1,1]; 760} 761def: InstRW<[SKLWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8, 762 STOSB, STOSL, STOSQ, STOSW)>; 763def: InstRW<[SKLWriteResGroup28], (instregex "PUSH(16|32|64)rmr")>; 764 765def SKLWriteResGroup29 : SchedWriteRes<[SKLPort1]> { 766 let Latency = 3; 767 let NumMicroOps = 1; 768 let ResourceCycles = [1]; 769} 770def: InstRW<[SKLWriteResGroup29], (instregex "PDEP(32|64)rr", 771 "PEXT(32|64)rr")>; 772 773def SKLWriteResGroup30 : SchedWriteRes<[SKLPort5]> { 774 let Latency = 3; 775 let NumMicroOps = 1; 776 let ResourceCycles = [1]; 777} 778def: InstRW<[SKLWriteResGroup30], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)", 779 "VPBROADCAST(B|W)rr")>; 780 781def SKLWriteResGroup32 : SchedWriteRes<[SKLPort0,SKLPort0156]> { 782 let Latency = 3; 783 let NumMicroOps = 2; 784 let ResourceCycles = [1,1]; 785} 786def: InstRW<[SKLWriteResGroup32], (instrs FNSTSW16r)>; 787 788def SKLWriteResGroup35 : SchedWriteRes<[SKLPort0,SKLPort5]> { 789 let Latency = 3; 790 let NumMicroOps = 3; 791 let ResourceCycles = [1,2]; 792} 793def: InstRW<[SKLWriteResGroup35], (instregex "MMX_PH(ADD|SUB)SWrr")>; 794 795def SKLWriteResGroup36 : SchedWriteRes<[SKLPort5,SKLPort01]> { 796 let Latency = 3; 797 let NumMicroOps = 3; 798 let ResourceCycles = [2,1]; 799} 800def: InstRW<[SKLWriteResGroup36], (instregex "(V?)PHADDSW(Y?)rr", 801 "(V?)PHSUBSW(Y?)rr")>; 802 803def SKLWriteResGroup39 : SchedWriteRes<[SKLPort5,SKLPort0156]> { 804 let Latency = 3; 805 let NumMicroOps = 3; 806 let ResourceCycles = [2,1]; 807} 808def: InstRW<[SKLWriteResGroup39], (instrs MMX_PACKSSDWirr, 809 MMX_PACKSSWBirr, 810 MMX_PACKUSWBirr)>; 811 812def SKLWriteResGroup40 : SchedWriteRes<[SKLPort6,SKLPort0156]> { 813 let Latency = 3; 814 let NumMicroOps = 3; 815 let ResourceCycles = [1,2]; 816} 817def: InstRW<[SKLWriteResGroup40], (instregex "CLD")>; 818 819def SKLWriteResGroup41 : SchedWriteRes<[SKLPort237,SKLPort0156]> { 820 let Latency = 3; 821 let NumMicroOps = 3; 822 let ResourceCycles = [1,2]; 823} 824def: InstRW<[SKLWriteResGroup41], (instrs MFENCE)>; 825 826def SKLWriteResGroup42 : SchedWriteRes<[SKLPort06,SKLPort0156]> { 827 let Latency = 3; 828 let NumMicroOps = 3; 829 let ResourceCycles = [1,2]; 830} 831def: InstRW<[SKLWriteResGroup42], (instregex "RCL(8|16|32|64)r(1|i)", 832 "RCR(8|16|32|64)r(1|i)")>; 833 834def SKLWriteResGroup43 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort237]> { 835 let Latency = 3; 836 let NumMicroOps = 3; 837 let ResourceCycles = [1,1,1]; 838} 839def: InstRW<[SKLWriteResGroup43], (instrs FNSTSWm)>; 840 841def SKLWriteResGroup45 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237,SKLPort0156]> { 842 let Latency = 3; 843 let NumMicroOps = 4; 844 let ResourceCycles = [1,1,1,1]; 845} 846def: InstRW<[SKLWriteResGroup45], (instregex "CALL(16|32|64)r")>; 847 848def SKLWriteResGroup46 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06,SKLPort0156]> { 849 let Latency = 3; 850 let NumMicroOps = 4; 851 let ResourceCycles = [1,1,1,1]; 852} 853def: InstRW<[SKLWriteResGroup46], (instrs CALL64pcrel32)>; 854 855def SKLWriteResGroup47 : SchedWriteRes<[SKLPort0]> { 856 let Latency = 4; 857 let NumMicroOps = 1; 858 let ResourceCycles = [1]; 859} 860def: InstRW<[SKLWriteResGroup47], (instregex "MUL_(FPrST0|FST0r|FrST0)")>; 861 862def SKLWriteResGroup48 : SchedWriteRes<[SKLPort01]> { 863 let Latency = 4; 864 let NumMicroOps = 1; 865 let ResourceCycles = [1]; 866} 867def: InstRW<[SKLWriteResGroup48], (instregex "(V?)CVTDQ2PS(Y?)rr", 868 "(V?)CVT(T?)PS2DQ(Y?)rr")>; 869 870def SKLWriteResGroup53 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237]> { 871 let Latency = 4; 872 let NumMicroOps = 3; 873 let ResourceCycles = [1,1,1]; 874} 875def: InstRW<[SKLWriteResGroup53], (instregex "IST(T?)_FP(16|32|64)m", 876 "IST_F(16|32)m")>; 877 878def SKLWriteResGroup54 : SchedWriteRes<[SKLPort0156]> { 879 let Latency = 4; 880 let NumMicroOps = 4; 881 let ResourceCycles = [4]; 882} 883def: InstRW<[SKLWriteResGroup54], (instrs FNCLEX)>; 884 885def SKLWriteResGroup55 : SchedWriteRes<[SKLPort6,SKLPort0156]> { 886 let Latency = 4; 887 let NumMicroOps = 4; 888 let ResourceCycles = [1,3]; 889} 890def: InstRW<[SKLWriteResGroup55], (instrs PAUSE)>; 891 892def SKLWriteResGroup56 : SchedWriteRes<[]> { 893 let Latency = 0; 894 let NumMicroOps = 4; 895 let ResourceCycles = []; 896} 897def: InstRW<[SKLWriteResGroup56], (instrs VZEROUPPER)>; 898 899def SKLWriteResGroup57 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort0156]> { 900 let Latency = 4; 901 let NumMicroOps = 4; 902 let ResourceCycles = [1,1,2]; 903} 904def: InstRW<[SKLWriteResGroup57], (instregex "LAR(16|32|64)rr")>; 905 906def SKLWriteResGroup58 : SchedWriteRes<[SKLPort23]> { 907 let Latency = 5; 908 let NumMicroOps = 1; 909 let ResourceCycles = [1]; 910} 911def: InstRW<[SKLWriteResGroup58], (instregex "MOVSX(16|32|64)rm(8|16|32)", 912 "MOVZX(16|32|64)rm(8|16)", 913 "(V?)MOVDDUPrm")>; // TODO: Should this be SKLWriteResGroup67? 914 915def SKLWriteResGroup59 : SchedWriteRes<[SKLPort0,SKLPort5]> { 916 let Latency = 5; 917 let NumMicroOps = 2; 918 let ResourceCycles = [1,1]; 919} 920def: InstRW<[SKLWriteResGroup59], (instrs MMX_CVTPI2PDirr, 921 CVTDQ2PDrr, 922 VCVTDQ2PDrr)>; 923 924def SKLWriteResGroup60 : SchedWriteRes<[SKLPort5,SKLPort015]> { 925 let Latency = 5; 926 let NumMicroOps = 2; 927 let ResourceCycles = [1,1]; 928} 929def: InstRW<[SKLWriteResGroup60], (instregex "MMX_CVT(T?)PD2PIirr", 930 "MMX_CVT(T?)PS2PIirr", 931 "(V?)CVT(T?)PD2DQrr", 932 "(V?)CVTPD2PSrr", 933 "(V?)CVTPS2PDrr", 934 "(V?)CVTSD2SSrr", 935 "(V?)CVTSI642SDrr", 936 "(V?)CVTSI2SDrr", 937 "(V?)CVTSI2SSrr", 938 "(V?)CVTSS2SDrr")>; 939 940def SKLWriteResGroup61 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06]> { 941 let Latency = 5; 942 let NumMicroOps = 3; 943 let ResourceCycles = [1,1,1]; 944} 945def: InstRW<[SKLWriteResGroup61], (instregex "STR(16|32|64)r")>; 946 947def SKLWriteResGroup63 : SchedWriteRes<[SKLPort06,SKLPort0156]> { 948 let Latency = 5; 949 let NumMicroOps = 5; 950 let ResourceCycles = [1,4]; 951} 952def: InstRW<[SKLWriteResGroup63], (instrs XSETBV)>; 953 954def SKLWriteResGroup65 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> { 955 let Latency = 5; 956 let NumMicroOps = 6; 957 let ResourceCycles = [1,1,4]; 958} 959def: InstRW<[SKLWriteResGroup65], (instregex "PUSHF(16|64)")>; 960 961def SKLWriteResGroup67 : SchedWriteRes<[SKLPort23]> { 962 let Latency = 6; 963 let NumMicroOps = 1; 964 let ResourceCycles = [1]; 965} 966def: InstRW<[SKLWriteResGroup67], (instrs VBROADCASTSSrm, 967 VPBROADCASTDrm, 968 VPBROADCASTQrm)>; 969def: InstRW<[SKLWriteResGroup67], (instregex "(V?)MOVSHDUPrm", 970 "(V?)MOVSLDUPrm")>; 971 972def SKLWriteResGroup68 : SchedWriteRes<[SKLPort0]> { 973 let Latency = 6; 974 let NumMicroOps = 2; 975 let ResourceCycles = [2]; 976} 977def: InstRW<[SKLWriteResGroup68], (instrs MMX_CVTPI2PSirr)>; 978 979def SKLWriteResGroup69 : SchedWriteRes<[SKLPort0,SKLPort23]> { 980 let Latency = 6; 981 let NumMicroOps = 2; 982 let ResourceCycles = [1,1]; 983} 984def: InstRW<[SKLWriteResGroup69], (instrs MMX_PADDSBirm, 985 MMX_PADDSWirm, 986 MMX_PADDUSBirm, 987 MMX_PADDUSWirm, 988 MMX_PAVGBirm, 989 MMX_PAVGWirm, 990 MMX_PCMPEQBirm, 991 MMX_PCMPEQDirm, 992 MMX_PCMPEQWirm, 993 MMX_PCMPGTBirm, 994 MMX_PCMPGTDirm, 995 MMX_PCMPGTWirm, 996 MMX_PMAXSWirm, 997 MMX_PMAXUBirm, 998 MMX_PMINSWirm, 999 MMX_PMINUBirm, 1000 MMX_PSUBSBirm, 1001 MMX_PSUBSWirm, 1002 MMX_PSUBUSBirm, 1003 MMX_PSUBUSWirm)>; 1004 1005def SKLWriteResGroup70 : SchedWriteRes<[SKLPort0,SKLPort01]> { 1006 let Latency = 6; 1007 let NumMicroOps = 2; 1008 let ResourceCycles = [1,1]; 1009} 1010def: InstRW<[SKLWriteResGroup70], (instregex "(V?)CVTSS2SI(64)?rr", 1011 "(V?)CVT(T?)SD2SI(64)?rr")>; 1012 1013def SKLWriteResGroup72 : SchedWriteRes<[SKLPort6,SKLPort23]> { 1014 let Latency = 6; 1015 let NumMicroOps = 2; 1016 let ResourceCycles = [1,1]; 1017} 1018def: InstRW<[SKLWriteResGroup72], (instrs FARJMP64m)>; 1019def: InstRW<[SKLWriteResGroup72], (instregex "JMP(16|32|64)m")>; 1020 1021def SKLWriteResGroup75 : SchedWriteRes<[SKLPort23,SKLPort15]> { 1022 let Latency = 6; 1023 let NumMicroOps = 2; 1024 let ResourceCycles = [1,1]; 1025} 1026def: InstRW<[SKLWriteResGroup75], (instregex "ANDN(32|64)rm", 1027 "MOVBE(16|32|64)rm")>; 1028 1029def SKLWriteResGroup76 : SchedWriteRes<[SKLPort23,SKLPort0156]> { 1030 let Latency = 6; 1031 let NumMicroOps = 2; 1032 let ResourceCycles = [1,1]; 1033} 1034def: InstRW<[SKLWriteResGroup76], (instrs POP16r, POP32r, POP64r)>; 1035def: InstRW<[SKLWriteResGroup76], (instregex "POP(16|32|64)rmr")>; 1036 1037def SKLWriteResGroup78 : SchedWriteRes<[SKLPort5,SKLPort01]> { 1038 let Latency = 6; 1039 let NumMicroOps = 3; 1040 let ResourceCycles = [2,1]; 1041} 1042def: InstRW<[SKLWriteResGroup78], (instregex "(V?)CVTSI642SSrr")>; 1043 1044def SKLWriteResGroup80 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06,SKLPort0156]> { 1045 let Latency = 6; 1046 let NumMicroOps = 4; 1047 let ResourceCycles = [1,1,1,1]; 1048} 1049def: InstRW<[SKLWriteResGroup80], (instregex "SLDT(16|32|64)r")>; 1050 1051def SKLWriteResGroup82 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> { 1052 let Latency = 6; 1053 let NumMicroOps = 4; 1054 let ResourceCycles = [1,1,1,1]; 1055} 1056def: InstRW<[SKLWriteResGroup82], (instregex "SAR(8|16|32|64)m(1|i)", 1057 "SHL(8|16|32|64)m(1|i)", 1058 "SHR(8|16|32|64)m(1|i)")>; 1059 1060def SKLWriteResGroup83 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> { 1061 let Latency = 6; 1062 let NumMicroOps = 4; 1063 let ResourceCycles = [1,1,1,1]; 1064} 1065def: InstRW<[SKLWriteResGroup83], (instregex "POP(16|32|64)rmm", 1066 "PUSH(16|32|64)rmm")>; 1067 1068def SKLWriteResGroup84 : SchedWriteRes<[SKLPort6,SKLPort0156]> { 1069 let Latency = 6; 1070 let NumMicroOps = 6; 1071 let ResourceCycles = [1,5]; 1072} 1073def: InstRW<[SKLWriteResGroup84], (instrs STD)>; 1074 1075def SKLWriteResGroup85 : SchedWriteRes<[SKLPort23]> { 1076 let Latency = 7; 1077 let NumMicroOps = 1; 1078 let ResourceCycles = [1]; 1079} 1080def: InstRW<[SKLWriteResGroup85], (instregex "LD_F(32|64|80)m")>; 1081def: InstRW<[SKLWriteResGroup85], (instrs VBROADCASTF128, 1082 VBROADCASTI128, 1083 VBROADCASTSDYrm, 1084 VBROADCASTSSYrm, 1085 VMOVDDUPYrm, 1086 VMOVSHDUPYrm, 1087 VMOVSLDUPYrm, 1088 VPBROADCASTDYrm, 1089 VPBROADCASTQYrm)>; 1090 1091def SKLWriteResGroup86 : SchedWriteRes<[SKLPort0,SKLPort5]> { 1092 let Latency = 7; 1093 let NumMicroOps = 2; 1094 let ResourceCycles = [1,1]; 1095} 1096def: InstRW<[SKLWriteResGroup86], (instrs VCVTDQ2PDYrr)>; 1097 1098def SKLWriteResGroup88 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1099 let Latency = 6; 1100 let NumMicroOps = 2; 1101 let ResourceCycles = [1,1]; 1102} 1103def: InstRW<[SKLWriteResGroup88], (instregex "(V?)PMOV(SX|ZX)BDrm", 1104 "(V?)PMOV(SX|ZX)BQrm", 1105 "(V?)PMOV(SX|ZX)BWrm", 1106 "(V?)PMOV(SX|ZX)DQrm", 1107 "(V?)PMOV(SX|ZX)WDrm", 1108 "(V?)PMOV(SX|ZX)WQrm")>; 1109 1110def SKLWriteResGroup89 : SchedWriteRes<[SKLPort5,SKLPort01]> { 1111 let Latency = 7; 1112 let NumMicroOps = 2; 1113 let ResourceCycles = [1,1]; 1114} 1115def: InstRW<[SKLWriteResGroup89], (instrs VCVTPD2PSYrr, 1116 VCVTPS2PDYrr, 1117 VCVTPD2DQYrr, 1118 VCVTTPD2DQYrr)>; 1119 1120def SKLWriteResGroup91 : SchedWriteRes<[SKLPort23,SKLPort015]> { 1121 let Latency = 7; 1122 let NumMicroOps = 2; 1123 let ResourceCycles = [1,1]; 1124} 1125def: InstRW<[SKLWriteResGroup91], (instrs VINSERTF128rm, 1126 VINSERTI128rm, 1127 VPBLENDDrmi)>; 1128def: InstRW<[SKLWriteResGroup91, ReadAfterVecXLd], 1129 (instregex "(V?)PADD(B|D|Q|W)rm", 1130 "(V?)PSUB(B|D|Q|W)rm")>; 1131 1132def SKLWriteResGroup92 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1133 let Latency = 7; 1134 let NumMicroOps = 3; 1135 let ResourceCycles = [2,1]; 1136} 1137def: InstRW<[SKLWriteResGroup92], (instrs MMX_PACKSSDWirm, 1138 MMX_PACKSSWBirm, 1139 MMX_PACKUSWBirm)>; 1140 1141def SKLWriteResGroup94 : SchedWriteRes<[SKLPort23,SKLPort0156]> { 1142 let Latency = 7; 1143 let NumMicroOps = 3; 1144 let ResourceCycles = [1,2]; 1145} 1146def: InstRW<[SKLWriteResGroup94], (instrs LEAVE, LEAVE64, 1147 SCASB, SCASL, SCASQ, SCASW)>; 1148 1149def SKLWriteResGroup95 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort01]> { 1150 let Latency = 7; 1151 let NumMicroOps = 3; 1152 let ResourceCycles = [1,1,1]; 1153} 1154def: InstRW<[SKLWriteResGroup95], (instregex "(V?)CVTTSS2SI(64)?rr")>; 1155 1156def SKLWriteResGroup96 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05]> { 1157 let Latency = 7; 1158 let NumMicroOps = 3; 1159 let ResourceCycles = [1,1,1]; 1160} 1161def: InstRW<[SKLWriteResGroup96], (instrs FLDCW16m)>; 1162 1163def SKLWriteResGroup98 : SchedWriteRes<[SKLPort6,SKLPort23,SKLPort0156]> { 1164 let Latency = 7; 1165 let NumMicroOps = 3; 1166 let ResourceCycles = [1,1,1]; 1167} 1168def: InstRW<[SKLWriteResGroup98], (instrs LRETQ, RETQ)>; 1169 1170def SKLWriteResGroup100 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> { 1171 let Latency = 7; 1172 let NumMicroOps = 5; 1173 let ResourceCycles = [1,1,1,2]; 1174} 1175def: InstRW<[SKLWriteResGroup100], (instregex "ROL(8|16|32|64)m(1|i)", 1176 "ROR(8|16|32|64)m(1|i)")>; 1177 1178def SKLWriteResGroup100_1 : SchedWriteRes<[SKLPort06]> { 1179 let Latency = 2; 1180 let NumMicroOps = 2; 1181 let ResourceCycles = [2]; 1182} 1183def: InstRW<[SKLWriteResGroup100_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1, 1184 ROR8r1, ROR16r1, ROR32r1, ROR64r1)>; 1185 1186def SKLWriteResGroup101 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> { 1187 let Latency = 7; 1188 let NumMicroOps = 5; 1189 let ResourceCycles = [1,1,1,2]; 1190} 1191def: InstRW<[SKLWriteResGroup101], (instregex "XADD(8|16|32|64)rm")>; 1192 1193def SKLWriteResGroup102 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> { 1194 let Latency = 7; 1195 let NumMicroOps = 5; 1196 let ResourceCycles = [1,1,1,1,1]; 1197} 1198def: InstRW<[SKLWriteResGroup102], (instregex "CALL(16|32|64)m")>; 1199def: InstRW<[SKLWriteResGroup102], (instrs FARCALL64m)>; 1200 1201def SKLWriteResGroup103 : SchedWriteRes<[SKLPort6,SKLPort06,SKLPort15,SKLPort0156]> { 1202 let Latency = 7; 1203 let NumMicroOps = 7; 1204 let ResourceCycles = [1,3,1,2]; 1205} 1206def: InstRW<[SKLWriteResGroup103], (instrs LOOP)>; 1207 1208def SKLWriteResGroup107 : SchedWriteRes<[SKLPort1,SKLPort23]> { 1209 let Latency = 8; 1210 let NumMicroOps = 2; 1211 let ResourceCycles = [1,1]; 1212} 1213def: InstRW<[SKLWriteResGroup107], (instregex "PDEP(32|64)rm", 1214 "PEXT(32|64)rm")>; 1215 1216def SKLWriteResGroup108 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1217 let Latency = 8; 1218 let NumMicroOps = 2; 1219 let ResourceCycles = [1,1]; 1220} 1221def: InstRW<[SKLWriteResGroup108], (instregex "FCOM(P?)(32|64)m")>; 1222def: InstRW<[SKLWriteResGroup108], (instrs VPBROADCASTBYrm, 1223 VPBROADCASTWYrm, 1224 VPMOVSXBDYrm, 1225 VPMOVSXBQYrm, 1226 VPMOVSXWQYrm)>; 1227 1228def SKLWriteResGroup110 : SchedWriteRes<[SKLPort23,SKLPort015]> { 1229 let Latency = 8; 1230 let NumMicroOps = 2; 1231 let ResourceCycles = [1,1]; 1232} 1233def: InstRW<[SKLWriteResGroup110], (instrs VPBLENDDYrmi)>; 1234def: InstRW<[SKLWriteResGroup110, ReadAfterVecYLd], 1235 (instregex "VPADD(B|D|Q|W)Yrm", 1236 "VPSUB(B|D|Q|W)Yrm")>; 1237 1238def SKLWriteResGroup112 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { 1239 let Latency = 8; 1240 let NumMicroOps = 4; 1241 let ResourceCycles = [1,2,1]; 1242} 1243def: InstRW<[SKLWriteResGroup112], (instregex "MMX_PH(ADD|SUB)SWrm")>; 1244 1245def SKLWriteResGroup116 : SchedWriteRes<[SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { 1246 let Latency = 8; 1247 let NumMicroOps = 5; 1248 let ResourceCycles = [1,1,1,2]; 1249} 1250def: InstRW<[SKLWriteResGroup116], (instregex "RCL(8|16|32|64)m(1|i)", 1251 "RCR(8|16|32|64)m(1|i)")>; 1252 1253def SKLWriteResGroup117 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> { 1254 let Latency = 8; 1255 let NumMicroOps = 6; 1256 let ResourceCycles = [1,1,1,3]; 1257} 1258def: InstRW<[SKLWriteResGroup117], (instregex "ROL(8|16|32|64)mCL", 1259 "ROR(8|16|32|64)mCL", 1260 "SAR(8|16|32|64)mCL", 1261 "SHL(8|16|32|64)mCL", 1262 "SHR(8|16|32|64)mCL")>; 1263 1264def SKLWriteResGroup119 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { 1265 let Latency = 8; 1266 let NumMicroOps = 6; 1267 let ResourceCycles = [1,1,1,2,1]; 1268} 1269def: SchedAlias<WriteADCRMW, SKLWriteResGroup119>; 1270 1271def SKLWriteResGroup120 : SchedWriteRes<[SKLPort0,SKLPort23]> { 1272 let Latency = 9; 1273 let NumMicroOps = 2; 1274 let ResourceCycles = [1,1]; 1275} 1276def: InstRW<[SKLWriteResGroup120], (instrs MMX_CVTPI2PSirm)>; 1277 1278def SKLWriteResGroup121 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1279 let Latency = 9; 1280 let NumMicroOps = 2; 1281 let ResourceCycles = [1,1]; 1282} 1283def: InstRW<[SKLWriteResGroup121], (instrs PCMPGTQrm, 1284 VPCMPGTQrm, 1285 VPMOVSXBWYrm, 1286 VPMOVSXDQYrm, 1287 VPMOVSXWDYrm, 1288 VPMOVZXWDYrm)>; 1289 1290def SKLWriteResGroup123 : SchedWriteRes<[SKLPort23,SKLPort01]> { 1291 let Latency = 9; 1292 let NumMicroOps = 2; 1293 let ResourceCycles = [1,1]; 1294} 1295def: InstRW<[SKLWriteResGroup123], (instregex "MMX_CVT(T?)PS2PIirm", 1296 "(V?)CVTPS2PDrm")>; 1297 1298def SKLWriteResGroup128 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> { 1299 let Latency = 9; 1300 let NumMicroOps = 4; 1301 let ResourceCycles = [2,1,1]; 1302} 1303def: InstRW<[SKLWriteResGroup128], (instregex "(V?)PHADDSWrm", 1304 "(V?)PHSUBSWrm")>; 1305 1306def SKLWriteResGroup131 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> { 1307 let Latency = 9; 1308 let NumMicroOps = 5; 1309 let ResourceCycles = [1,2,1,1]; 1310} 1311def: InstRW<[SKLWriteResGroup131], (instregex "LAR(16|32|64)rm", 1312 "LSL(16|32|64)rm")>; 1313 1314def SKLWriteResGroup133 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1315 let Latency = 10; 1316 let NumMicroOps = 2; 1317 let ResourceCycles = [1,1]; 1318} 1319def: InstRW<[SKLWriteResGroup133], (instregex "(ADD|SUB|SUBR)_F(32|64)m", 1320 "ILD_F(16|32|64)m")>; 1321def: InstRW<[SKLWriteResGroup133], (instrs VPCMPGTQYrm)>; 1322 1323def SKLWriteResGroup134 : SchedWriteRes<[SKLPort01,SKLPort23]> { 1324 let Latency = 10; 1325 let NumMicroOps = 2; 1326 let ResourceCycles = [1,1]; 1327} 1328def: InstRW<[SKLWriteResGroup134], (instregex "(V?)CVTDQ2PSrm", 1329 "(V?)CVTPS2DQrm", 1330 "(V?)CVTSS2SDrm", 1331 "(V?)CVTTPS2DQrm")>; 1332 1333def SKLWriteResGroup138 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { 1334 let Latency = 10; 1335 let NumMicroOps = 3; 1336 let ResourceCycles = [1,1,1]; 1337} 1338def: InstRW<[SKLWriteResGroup138], (instrs MMX_CVTPI2PDirm)>; 1339 1340def SKLWriteResGroup139 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> { 1341 let Latency = 10; 1342 let NumMicroOps = 3; 1343 let ResourceCycles = [1,1,1]; 1344} 1345def: InstRW<[SKLWriteResGroup139], (instregex "(V?)CVTSD2SSrm")>; 1346 1347def SKLWriteResGroup140 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> { 1348 let Latency = 10; 1349 let NumMicroOps = 4; 1350 let ResourceCycles = [2,1,1]; 1351} 1352def: InstRW<[SKLWriteResGroup140], (instrs VPHADDSWYrm, 1353 VPHSUBSWYrm)>; 1354 1355def SKLWriteResGroup143 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { 1356 let Latency = 10; 1357 let NumMicroOps = 8; 1358 let ResourceCycles = [1,1,1,1,1,3]; 1359} 1360def: InstRW<[SKLWriteResGroup143], (instregex "XCHG(8|16|32|64)rm")>; 1361 1362def SKLWriteResGroup145 : SchedWriteRes<[SKLPort0,SKLFPDivider]> { 1363 let Latency = 11; 1364 let NumMicroOps = 1; 1365 let ResourceCycles = [1,3]; 1366} 1367def : SchedAlias<WriteFDivX, SKLWriteResGroup145>; // TODO - convert to ZnWriteResFpuPair 1368 1369def SKLWriteResGroup146 : SchedWriteRes<[SKLPort0,SKLPort23]> { 1370 let Latency = 11; 1371 let NumMicroOps = 2; 1372 let ResourceCycles = [1,1]; 1373} 1374def: InstRW<[SKLWriteResGroup146], (instregex "MUL_F(32|64)m")>; 1375 1376def SKLWriteResGroup147 : SchedWriteRes<[SKLPort01,SKLPort23]> { 1377 let Latency = 11; 1378 let NumMicroOps = 2; 1379 let ResourceCycles = [1,1]; 1380} 1381def: InstRW<[SKLWriteResGroup147], (instrs VCVTDQ2PSYrm, 1382 VCVTPS2PDYrm, 1383 VCVTPS2DQYrm, 1384 VCVTTPS2DQYrm)>; 1385 1386def SKLWriteResGroup149 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1387 let Latency = 11; 1388 let NumMicroOps = 3; 1389 let ResourceCycles = [2,1]; 1390} 1391def: InstRW<[SKLWriteResGroup149], (instregex "FICOM(P?)(16|32)m")>; 1392 1393def SKLWriteResGroup150 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { 1394 let Latency = 11; 1395 let NumMicroOps = 3; 1396 let ResourceCycles = [1,1,1]; 1397} 1398def: InstRW<[SKLWriteResGroup150], (instregex "(V?)CVTDQ2PDrm")>; 1399 1400def SKLWriteResGroup151 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort01]> { 1401 let Latency = 11; 1402 let NumMicroOps = 3; 1403 let ResourceCycles = [1,1,1]; 1404} 1405def: InstRW<[SKLWriteResGroup151], (instregex "(V?)CVTSS2SI64rm", 1406 "(V?)CVT(T?)SD2SI(64)?rm", 1407 "VCVTTSS2SI64rm", 1408 "(V?)CVT(T?)SS2SIrm")>; 1409 1410def SKLWriteResGroup152 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> { 1411 let Latency = 11; 1412 let NumMicroOps = 3; 1413 let ResourceCycles = [1,1,1]; 1414} 1415def: InstRW<[SKLWriteResGroup152], (instrs CVTPD2PSrm, 1416 CVTPD2DQrm, 1417 CVTTPD2DQrm, 1418 MMX_CVTPD2PIirm, 1419 MMX_CVTTPD2PIirm)>; 1420 1421def SKLWriteResGroup154 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> { 1422 let Latency = 11; 1423 let NumMicroOps = 7; 1424 let ResourceCycles = [2,3,2]; 1425} 1426def: InstRW<[SKLWriteResGroup154], (instregex "RCL(16|32|64)rCL", 1427 "RCR(16|32|64)rCL")>; 1428 1429def SKLWriteResGroup155 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> { 1430 let Latency = 11; 1431 let NumMicroOps = 9; 1432 let ResourceCycles = [1,5,1,2]; 1433} 1434def: InstRW<[SKLWriteResGroup155], (instrs RCL8rCL)>; 1435 1436def SKLWriteResGroup156 : SchedWriteRes<[SKLPort06,SKLPort0156]> { 1437 let Latency = 11; 1438 let NumMicroOps = 11; 1439 let ResourceCycles = [2,9]; 1440} 1441def: InstRW<[SKLWriteResGroup156], (instrs LOOPE, LOOPNE)>; 1442 1443def SKLWriteResGroup160 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort01]> { 1444 let Latency = 12; 1445 let NumMicroOps = 4; 1446 let ResourceCycles = [1,1,1,1]; 1447} 1448def: InstRW<[SKLWriteResGroup160], (instregex "CVTTSS2SI64rm")>; 1449 1450def SKLWriteResGroup162 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1451 let Latency = 13; 1452 let NumMicroOps = 3; 1453 let ResourceCycles = [2,1]; 1454} 1455def: InstRW<[SKLWriteResGroup162], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>; 1456 1457def SKLWriteResGroup163 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { 1458 let Latency = 13; 1459 let NumMicroOps = 3; 1460 let ResourceCycles = [1,1,1]; 1461} 1462def: InstRW<[SKLWriteResGroup163], (instrs VCVTDQ2PDYrm)>; 1463 1464def SKLWriteResGroup166 : SchedWriteRes<[SKLPort0,SKLFPDivider]> { 1465 let Latency = 14; 1466 let NumMicroOps = 1; 1467 let ResourceCycles = [1,3]; 1468} 1469def : SchedAlias<WriteFDiv64, SKLWriteResGroup166>; // TODO - convert to ZnWriteResFpuPair 1470def : SchedAlias<WriteFDiv64X, SKLWriteResGroup166>; // TODO - convert to ZnWriteResFpuPair 1471 1472def SKLWriteResGroup166_1 : SchedWriteRes<[SKLPort0,SKLFPDivider]> { 1473 let Latency = 14; 1474 let NumMicroOps = 1; 1475 let ResourceCycles = [1,5]; 1476} 1477def : SchedAlias<WriteFDiv64Y, SKLWriteResGroup166_1>; // TODO - convert to ZnWriteResFpuPair 1478 1479def SKLWriteResGroup169 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { 1480 let Latency = 14; 1481 let NumMicroOps = 3; 1482 let ResourceCycles = [1,1,1]; 1483} 1484def: InstRW<[SKLWriteResGroup169], (instregex "MUL_FI(16|32)m")>; 1485 1486def SKLWriteResGroup170 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> { 1487 let Latency = 14; 1488 let NumMicroOps = 10; 1489 let ResourceCycles = [2,4,1,3]; 1490} 1491def: InstRW<[SKLWriteResGroup170], (instrs RCR8rCL)>; 1492 1493def SKLWriteResGroup171 : SchedWriteRes<[SKLPort0]> { 1494 let Latency = 15; 1495 let NumMicroOps = 1; 1496 let ResourceCycles = [1]; 1497} 1498def: InstRW<[SKLWriteResGroup171], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>; 1499 1500def SKLWriteResGroup174 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> { 1501 let Latency = 15; 1502 let NumMicroOps = 10; 1503 let ResourceCycles = [1,1,1,5,1,1]; 1504} 1505def: InstRW<[SKLWriteResGroup174], (instregex "RCL(8|16|32|64)mCL")>; 1506 1507def SKLWriteResGroup177 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> { 1508 let Latency = 16; 1509 let NumMicroOps = 14; 1510 let ResourceCycles = [1,1,1,4,2,5]; 1511} 1512def: InstRW<[SKLWriteResGroup177], (instrs CMPXCHG8B)>; 1513 1514def SKLWriteResGroup178 : SchedWriteRes<[SKLPort0156]> { 1515 let Latency = 16; 1516 let NumMicroOps = 16; 1517 let ResourceCycles = [16]; 1518} 1519def: InstRW<[SKLWriteResGroup178], (instrs VZEROALL)>; 1520 1521def SKLWriteResGroup179 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> { 1522 let Latency = 17; 1523 let NumMicroOps = 2; 1524 let ResourceCycles = [1,1,5]; 1525} 1526def : SchedAlias<WriteFDivXLd, SKLWriteResGroup179>; // TODO - convert to ZnWriteResFpuPair 1527 1528def SKLWriteResGroup180 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156]> { 1529 let Latency = 17; 1530 let NumMicroOps = 15; 1531 let ResourceCycles = [2,1,2,4,2,4]; 1532} 1533def: InstRW<[SKLWriteResGroup180], (instrs XCH_F)>; 1534 1535def SKLWriteResGroup184 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort06,SKLPort0156]> { 1536 let Latency = 18; 1537 let NumMicroOps = 8; 1538 let ResourceCycles = [1,1,1,5]; 1539} 1540def: InstRW<[SKLWriteResGroup184], (instrs CPUID, RDTSC)>; 1541 1542def SKLWriteResGroup185 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> { 1543 let Latency = 18; 1544 let NumMicroOps = 11; 1545 let ResourceCycles = [2,1,1,4,1,2]; 1546} 1547def: InstRW<[SKLWriteResGroup185], (instregex "RCR(8|16|32|64)mCL")>; 1548 1549def SKLWriteResGroup186 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> { 1550 let Latency = 19; 1551 let NumMicroOps = 2; 1552 let ResourceCycles = [1,1,4]; 1553} 1554def : SchedAlias<WriteFDiv64Ld, SKLWriteResGroup186>; // TODO - convert to ZnWriteResFpuPair 1555 1556def SKLWriteResGroup189 : SchedWriteRes<[SKLPort0]> { 1557 let Latency = 20; 1558 let NumMicroOps = 1; 1559 let ResourceCycles = [1]; 1560} 1561def: InstRW<[SKLWriteResGroup189], (instregex "DIV_(FPrST0|FST0r|FrST0)")>; 1562 1563def SKLWriteResGroup190 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> { 1564 let Latency = 20; 1565 let NumMicroOps = 2; 1566 let ResourceCycles = [1,1,4]; 1567} 1568def : SchedAlias<WriteFDiv64XLd, SKLWriteResGroup190>; // TODO - convert to ZnWriteResFpuPair 1569 1570def SKLWriteResGroup192 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { 1571 let Latency = 20; 1572 let NumMicroOps = 8; 1573 let ResourceCycles = [1,1,1,1,1,1,2]; 1574} 1575def: InstRW<[SKLWriteResGroup192], (instrs INSB, INSL, INSW)>; 1576 1577def SKLWriteResGroup193 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort0156]> { 1578 let Latency = 20; 1579 let NumMicroOps = 10; 1580 let ResourceCycles = [1,2,7]; 1581} 1582def: InstRW<[SKLWriteResGroup193], (instrs MWAITrr)>; 1583 1584def SKLWriteResGroup195 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> { 1585 let Latency = 21; 1586 let NumMicroOps = 2; 1587 let ResourceCycles = [1,1,8]; 1588} 1589def : SchedAlias<WriteFDiv64YLd, SKLWriteResGroup195>; // TODO - convert to ZnWriteResFpuPair 1590 1591def SKLWriteResGroup196 : SchedWriteRes<[SKLPort0,SKLPort23]> { 1592 let Latency = 22; 1593 let NumMicroOps = 2; 1594 let ResourceCycles = [1,1]; 1595} 1596def: InstRW<[SKLWriteResGroup196], (instregex "DIV_F(32|64)m")>; 1597 1598def SKLWriteResGroupVEX2 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> { 1599 let Latency = 18; 1600 let NumMicroOps = 5; // 2 uops perform multiple loads 1601 let ResourceCycles = [1,2,1,1]; 1602} 1603def: InstRW<[SKLWriteResGroupVEX2], (instrs VGATHERDPDrm, VPGATHERDQrm, 1604 VGATHERQPDrm, VPGATHERQQrm, 1605 VGATHERQPSrm, VPGATHERQDrm)>; 1606 1607def SKLWriteResGroupVEX4 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> { 1608 let Latency = 20; 1609 let NumMicroOps = 5; // 2 uops peform multiple loads 1610 let ResourceCycles = [1,4,1,1]; 1611} 1612def: InstRW<[SKLWriteResGroupVEX4], (instrs VGATHERDPDYrm, VPGATHERDQYrm, 1613 VGATHERDPSrm, VPGATHERDDrm, 1614 VGATHERQPDYrm, VPGATHERQQYrm, 1615 VGATHERQPSYrm, VPGATHERQDYrm)>; 1616 1617def SKLWriteResGroupVEX8 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> { 1618 let Latency = 22; 1619 let NumMicroOps = 5; // 2 uops perform multiple loads 1620 let ResourceCycles = [1,8,1,1]; 1621} 1622def: InstRW<[SKLWriteResGroupVEX8], (instrs VGATHERDPSYrm, VPGATHERDDYrm)>; 1623 1624def SKLWriteResGroup198 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort5,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { 1625 let Latency = 23; 1626 let NumMicroOps = 19; 1627 let ResourceCycles = [2,1,4,1,1,4,6]; 1628} 1629def: InstRW<[SKLWriteResGroup198], (instrs CMPXCHG16B)>; 1630 1631def SKLWriteResGroup202 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { 1632 let Latency = 25; 1633 let NumMicroOps = 3; 1634 let ResourceCycles = [1,1,1]; 1635} 1636def: InstRW<[SKLWriteResGroup202], (instregex "DIV_FI(16|32)m")>; 1637 1638def SKLWriteResGroup206 : SchedWriteRes<[SKLPort0,SKLPort23]> { 1639 let Latency = 27; 1640 let NumMicroOps = 2; 1641 let ResourceCycles = [1,1]; 1642} 1643def: InstRW<[SKLWriteResGroup206], (instregex "DIVR_F(32|64)m")>; 1644 1645def SKLWriteResGroup208 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { 1646 let Latency = 30; 1647 let NumMicroOps = 3; 1648 let ResourceCycles = [1,1,1]; 1649} 1650def: InstRW<[SKLWriteResGroup208], (instregex "DIVR_FI(16|32)m")>; 1651 1652def SKLWriteResGroup209 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort06,SKLPort0156]> { 1653 let Latency = 35; 1654 let NumMicroOps = 23; 1655 let ResourceCycles = [1,5,3,4,10]; 1656} 1657def: InstRW<[SKLWriteResGroup209], (instregex "IN(8|16|32)ri", 1658 "IN(8|16|32)rr")>; 1659 1660def SKLWriteResGroup210 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { 1661 let Latency = 35; 1662 let NumMicroOps = 23; 1663 let ResourceCycles = [1,5,2,1,4,10]; 1664} 1665def: InstRW<[SKLWriteResGroup210], (instregex "OUT(8|16|32)ir", 1666 "OUT(8|16|32)rr")>; 1667 1668def SKLWriteResGroup211 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> { 1669 let Latency = 37; 1670 let NumMicroOps = 31; 1671 let ResourceCycles = [1,8,1,21]; 1672} 1673def: InstRW<[SKLWriteResGroup211], (instregex "XRSTOR(64)?")>; 1674 1675def SKLWriteResGroup212 : SchedWriteRes<[SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort15,SKLPort0156]> { 1676 let Latency = 40; 1677 let NumMicroOps = 18; 1678 let ResourceCycles = [1,1,2,3,1,1,1,8]; 1679} 1680def: InstRW<[SKLWriteResGroup212], (instrs VMCLEARm)>; 1681 1682def SKLWriteResGroup213 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> { 1683 let Latency = 41; 1684 let NumMicroOps = 39; 1685 let ResourceCycles = [1,10,1,1,26]; 1686} 1687def: InstRW<[SKLWriteResGroup213], (instrs XSAVE64)>; 1688 1689def SKLWriteResGroup214 : SchedWriteRes<[SKLPort5,SKLPort0156]> { 1690 let Latency = 42; 1691 let NumMicroOps = 22; 1692 let ResourceCycles = [2,20]; 1693} 1694def: InstRW<[SKLWriteResGroup214], (instrs RDTSCP)>; 1695 1696def SKLWriteResGroup215 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> { 1697 let Latency = 42; 1698 let NumMicroOps = 40; 1699 let ResourceCycles = [1,11,1,1,26]; 1700} 1701def: InstRW<[SKLWriteResGroup215], (instrs XSAVE)>; 1702def: InstRW<[SKLWriteResGroup215], (instregex "XSAVEC", "XSAVES")>; 1703 1704def SKLWriteResGroup216 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> { 1705 let Latency = 46; 1706 let NumMicroOps = 44; 1707 let ResourceCycles = [1,11,1,1,30]; 1708} 1709def: InstRW<[SKLWriteResGroup216], (instregex "XSAVEOPT")>; 1710 1711def SKLWriteResGroup217 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05,SKLPort06,SKLPort0156]> { 1712 let Latency = 62; 1713 let NumMicroOps = 64; 1714 let ResourceCycles = [2,8,5,10,39]; 1715} 1716def: InstRW<[SKLWriteResGroup217], (instrs FLDENVm)>; 1717 1718def SKLWriteResGroup218 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> { 1719 let Latency = 63; 1720 let NumMicroOps = 88; 1721 let ResourceCycles = [4,4,31,1,2,1,45]; 1722} 1723def: InstRW<[SKLWriteResGroup218], (instrs FXRSTOR64)>; 1724 1725def SKLWriteResGroup219 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> { 1726 let Latency = 63; 1727 let NumMicroOps = 90; 1728 let ResourceCycles = [4,2,33,1,2,1,47]; 1729} 1730def: InstRW<[SKLWriteResGroup219], (instrs FXRSTOR)>; 1731 1732def SKLWriteResGroup220 : SchedWriteRes<[SKLPort5,SKLPort05,SKLPort0156]> { 1733 let Latency = 75; 1734 let NumMicroOps = 15; 1735 let ResourceCycles = [6,3,6]; 1736} 1737def: InstRW<[SKLWriteResGroup220], (instrs FNINIT)>; 1738 1739def SKLWriteResGroup223 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort237,SKLPort06,SKLPort0156]> { 1740 let Latency = 106; 1741 let NumMicroOps = 100; 1742 let ResourceCycles = [9,1,11,16,1,11,21,30]; 1743} 1744def: InstRW<[SKLWriteResGroup223], (instrs FSTENVm)>; 1745 1746def: InstRW<[WriteZero], (instrs CLC)>; 1747 1748 1749// Instruction variants handled by the renamer. These might not need execution 1750// ports in certain conditions. 1751// See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs", 1752// section "Skylake Pipeline" > "Register allocation and renaming". 1753// These can be investigated with llvm-exegesis, e.g. 1754// echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 1755// echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 1756 1757def SKLWriteZeroLatency : SchedWriteRes<[]> { 1758 let Latency = 0; 1759} 1760 1761def SKLWriteZeroIdiom : SchedWriteVariant<[ 1762 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1763 SchedVar<NoSchedPred, [WriteALU]> 1764]>; 1765def : InstRW<[SKLWriteZeroIdiom], (instrs SUB32rr, SUB64rr, 1766 XOR32rr, XOR64rr)>; 1767 1768def SKLWriteFZeroIdiom : SchedWriteVariant<[ 1769 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1770 SchedVar<NoSchedPred, [WriteFLogic]> 1771]>; 1772def : InstRW<[SKLWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr, 1773 VXORPDrr)>; 1774 1775def SKLWriteFZeroIdiomY : SchedWriteVariant<[ 1776 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1777 SchedVar<NoSchedPred, [WriteFLogicY]> 1778]>; 1779def : InstRW<[SKLWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr)>; 1780 1781def SKLWriteVZeroIdiomLogicX : SchedWriteVariant<[ 1782 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1783 SchedVar<NoSchedPred, [WriteVecLogicX]> 1784]>; 1785def : InstRW<[SKLWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr)>; 1786 1787def SKLWriteVZeroIdiomLogicY : SchedWriteVariant<[ 1788 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1789 SchedVar<NoSchedPred, [WriteVecLogicY]> 1790]>; 1791def : InstRW<[SKLWriteVZeroIdiomLogicY], (instrs VPXORYrr)>; 1792 1793def SKLWriteVZeroIdiomALUX : SchedWriteVariant<[ 1794 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1795 SchedVar<NoSchedPred, [WriteVecALUX]> 1796]>; 1797def : InstRW<[SKLWriteVZeroIdiomALUX], (instrs PCMPGTBrr, VPCMPGTBrr, 1798 PCMPGTDrr, VPCMPGTDrr, 1799 PCMPGTWrr, VPCMPGTWrr)>; 1800 1801def SKLWriteVZeroIdiomALUY : SchedWriteVariant<[ 1802 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1803 SchedVar<NoSchedPred, [WriteVecALUY]> 1804]>; 1805def : InstRW<[SKLWriteVZeroIdiomALUY], (instrs VPCMPGTBYrr, 1806 VPCMPGTDYrr, 1807 VPCMPGTWYrr)>; 1808 1809def SKLWritePSUB : SchedWriteRes<[SKLPort015]> { 1810 let Latency = 1; 1811 let NumMicroOps = 1; 1812 let ResourceCycles = [1]; 1813} 1814 1815def SKLWriteVZeroIdiomPSUB : SchedWriteVariant<[ 1816 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1817 SchedVar<NoSchedPred, [SKLWritePSUB]> 1818]>; 1819def : InstRW<[SKLWriteVZeroIdiomPSUB], (instrs PSUBBrr, VPSUBBrr, 1820 PSUBDrr, VPSUBDrr, 1821 PSUBQrr, VPSUBQrr, 1822 PSUBWrr, VPSUBWrr, 1823 VPSUBBYrr, 1824 VPSUBDYrr, 1825 VPSUBQYrr, 1826 VPSUBWYrr)>; 1827 1828def SKLWritePCMPGTQ : SchedWriteRes<[SKLPort5]> { 1829 let Latency = 3; 1830 let NumMicroOps = 1; 1831 let ResourceCycles = [1]; 1832} 1833 1834def SKLWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[ 1835 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1836 SchedVar<NoSchedPred, [SKLWritePCMPGTQ]> 1837]>; 1838def : InstRW<[SKLWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr, 1839 VPCMPGTQYrr)>; 1840 1841 1842// CMOVs that use both Z and C flag require an extra uop. 1843def SKLWriteCMOVA_CMOVBErr : SchedWriteRes<[SKLPort06]> { 1844 let Latency = 2; 1845 let ResourceCycles = [2]; 1846 let NumMicroOps = 2; 1847} 1848 1849def SKLWriteCMOVA_CMOVBErm : SchedWriteRes<[SKLPort23,SKLPort06]> { 1850 let Latency = 7; 1851 let ResourceCycles = [1,2]; 1852 let NumMicroOps = 3; 1853} 1854 1855def SKLCMOVA_CMOVBErr : SchedWriteVariant<[ 1856 SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [SKLWriteCMOVA_CMOVBErr]>, 1857 SchedVar<NoSchedPred, [WriteCMOV]> 1858]>; 1859 1860def SKLCMOVA_CMOVBErm : SchedWriteVariant<[ 1861 SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [SKLWriteCMOVA_CMOVBErm]>, 1862 SchedVar<NoSchedPred, [WriteCMOV.Folded]> 1863]>; 1864 1865def : InstRW<[SKLCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>; 1866def : InstRW<[SKLCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>; 1867 1868// SETCCs that use both Z and C flag require an extra uop. 1869def SKLWriteSETA_SETBEr : SchedWriteRes<[SKLPort06]> { 1870 let Latency = 2; 1871 let ResourceCycles = [2]; 1872 let NumMicroOps = 2; 1873} 1874 1875def SKLWriteSETA_SETBEm : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06]> { 1876 let Latency = 3; 1877 let ResourceCycles = [1,1,2]; 1878 let NumMicroOps = 4; 1879} 1880 1881def SKLSETA_SETBErr : SchedWriteVariant<[ 1882 SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [SKLWriteSETA_SETBEr]>, 1883 SchedVar<NoSchedPred, [WriteSETCC]> 1884]>; 1885 1886def SKLSETA_SETBErm : SchedWriteVariant<[ 1887 SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [SKLWriteSETA_SETBEm]>, 1888 SchedVar<NoSchedPred, [WriteSETCCStore]> 1889]>; 1890 1891def : InstRW<[SKLSETA_SETBErr], (instrs SETCCr)>; 1892def : InstRW<[SKLSETA_SETBErm], (instrs SETCCm)>; 1893 1894} // SchedModel 1895